C8051F981-GMR [SILICON]
Microcontroller;型号: | C8051F981-GMR |
厂家: | SILICON |
描述: | Microcontroller |
文件: | 总2页 (文件大小:46K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
C8051F98x
Ultra Low Power, High-Performance MCU
High-Speed 8051 µC Core
Ultra-Low Power
-
Pipe-lined instruction architecture; executes 70% of instructions
in 1 or 2 system clocks
-
-
-
-
-
-
-
150 µA/MHz active current from 1.8–3.6 V @ 25 MHz
10 nA sleep current with data retention; BOD disabled
50 nA sleep current with data retention; BOD enabled
300 nA sleep current with smaRTClock (internal oscillator)
600 nA sleep current with smaRTClock (external crystal)
2 µs wake up from sleep
-
-
25 MIPS peak throughput with 25 MHz clock
Expanded interrupt handler
Memory
-
-
512 bytes internal data RAM (256 + 256)
1.5 µs analog settling time
Up to 8 kB Flash; In-system programmable in 512 byte sectors;
Full read/write/erase functionality over the entire supply range
Supply Voltage 1.8 to 3.6 V
-
-
Built-in brown-out detector
On-Chip Debug
On-chip LDO regulator for core supply
-
On-chip debug circuitry facilitates full speed, non-intrusive in-
system debug
Analog to Digital Converter
-
-
-
-
-
-
-
75 ksps with 12-bit resolution
Digital Peripherals
300 ksps with 10-bit resolution
-
-
-
-
-
Up to 17 port I/O; Programmable drive strength
Hardware enhanced UART, SPI and SMBus™ serial ports
CRC block provides 16-Bit CCITT polynomial calculation
Four general purpose 16-bit counter/timers
330 ksps with 8-bit resolution
Up to 10-channels
Autonomous burst mode with 16-bit averaging accumulator
VREF from external pin, VDD, or internal regulator
Built-in temperature sensor
16-bit programmable counter array (PCA) with three capture/
compare modules and enhanced PWM functionality
Internal 6-Bit Current Reference
Clock Sources
-
-
2 ranges: source or sink capability
Enhanced resolution via PWM interpolation
-
-
-
-
24.5 MHz ±2% oscillator; supports crystal-less UART operation
Comparator
Low power internal oscillator: 20 MHz
-
-
-
Programmable hysteresis and response time
Configurable as interrupt or reset source
Low current (< 0.4 µA)
External oscillator: Crystal, RC, C, CMOS clock
Can switch clock sources on-the-fly; useful for power saving
modes
Development Kit: C8051F996DK
Temperature Range: -40 to +85 °C
Package Options
-
-
-
24-pin QFN (4x4 mm), RoHS compliant
24-pin QSOP (easy to hand solder) RoHS compliant
20-pin QFN (3x3 mm), RoHS compliant
Port I/O Configuration
CIP-51 8051
Power On
P0.0/VREF
P0.1/AGND
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7/IREF0
Reset/PMU
Controller Core
Digital Peripherals
UART
Wake
Reset
8 kB ISP Flash
Program Memory
Port 0
Drivers
Timers 0,
256 Byte SRAM
256 Byte XRAM
Debug /
Programming
Hardware
1, 2, 3
C2CK/RST
Priority
Crossbar
Decoder
WDT
PCA/
P1.0/CP0+
P1.1/CP0-
P1.2
P1.3
P1.4
P1.5
P1.6/XTAL3
P1.7/XTAL4
C2D
CRC
Engine
SMBus
SPI
VDD
VREG
Port 1
Drivers
Digital
Power
SYSCLK
Crossbar Control
SFR
Bus
Precision
24.5 MHz
Oscillator
Analog Peripherals
Port 2
Drivers
P2.7/C2D
Low Power
20 MHz
6-bit
IREF0
IREF
Oscillator
GND
External
VREF
Internal
VREF
External
Oscillator
Circuit
XTAL1
XTAL2
VDD
VREF
A
M
U
X
Temp
Sensor
12-bit
ADC
XTAL3
XTAL4
SmaRTClock
Oscillator
GND
CP0
+
-
P1.0
P1.1
System Clock
Configuration
Comparator
Ultra Low-Power MCU
Copyright © 2010 by Silicon Laboratories
5.18.2010
C8051F98x
Ultra Low Power, High-Performance MCU
Selected Electrical Specifications
(At 25 C°)
Parameter
Conditions
Min
Typ
Max
Units
Supply Input Voltage
1.8
—
3.6
V
Clock = 24.5 MHz
(±2% internal precision oscillator)
Supply Current with CPU Active
—
150
—
µA/MHz
Sleep mode; BOD off
Sleep mode; BOD on
—
—
.010
.050
.300
—
—
—
—
25
—
—
µA
µA
Supply Current (shutdown)
(VBAT = 1.8 V)
Sleep mode; smaRTClock running
—
µA
Clock Frequency Range
Wakeup Time
DC
—
MHz
µs
2
Analog Settling Time
—
1.5
µs
Internal Oscillator
Precision oscillator
Low power oscillator
A/D Converter
24
18
24.5
20
25
22
MHz
MHz
Frequency
Resolution
12/10
bits
Throughput Rate
—
—
75/300
ksps
C8051F9xx Ultra Low Power Product Family
Part #
Flash
Mem.
RAM
(Bytes)
MIPS
(Peak)
Digital
I/O
Communications
ADC
Sensing
Channels
Operating
Voltage
Package
Dev kit
2
C8051F930
C8051F931
C8051F920
C8051F921
C8051F911
C8051F912
C8051F901
C8051F902
C8051F980
C8051F981
C8051F982
C8051F983
C8051F985
C8051F986
C8051F987
C8051F988
C8051F989
C8051F990
64 kB
64 kB
32 kB
32 kB
16 kB
16 kB
8 kB
4352
4352
4352
4352
768
768
768
768
512
512
512
512
512
512
512
512
512
512
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
24
16
24
16
16
16
16
16
16
16
16
16
16
17
17
17
17
16
10-bit
10-bit
10-bit
10-bit
10-bit
12-bit
10-bit
12-bit
12-bit
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
13
13
14
0.9–3.6 V
0.9–3.6 V
0.9–3.6 V
0.9–3.6 V
0.9–3.6 V
0.9–3.6 V
0.9–3.6 V
0.9–3.6 V
1.8–3.6 V
1.8–3.6 V
1.8–3.6 V
1.8–3.6 V
1.8–3.6 V
1.8–3.6 V
1.8–3.6 V
1.8–3.6 V
1.8–3.6 V
1.8–3.6 V
1.8–3.6 V
1.8–3.6 V
1.8–3.6 V
QFN32/LQFP32
QFN24
C8051F930DK
C8051F930DK
C8051F930DK
C8051F930DK
C8051F912DK
C8051F912DK
C8051F912DK
C8051F912DK
C8051F996DK
C8051F996DK
C8051F996DK
C8051F996DK
C8051F996DK
C8051F996DK
C8051F996DK
C8051F996DK
C8051F996DK
C8051F996DK
EMIF, I C, 2xSPI, UART
2
I C, 2xSPI, UART
2
QFN32/LQFP32
QFN24
EMIF, I C, 2xSPI, UART
2
I C, 2xSPI, UART
2
QFN24/QSOP24
QFN24/QSOP24
QFN24/QSOP24
QFN24/QSOP24
QFN20
I C, 2xSPI, UART
2
I C, 2xSPI, UART
2
I C, 2xSPI, UART
2
8 kB
I C, 2xSPI, UART
2
8 kB
8 kB
4 kB
4 kB
2 kB
8 kB
8 kB
4 kB
4 kB
8 kB
I C, SPI, UART
2
QFN20
I C, SPI, UART
2
10-bit
—
QFN20
I C, SPI, UART
2
QFN20
I C, SPI, UART
2
—
QFN20
I C, SPI, UART
2
12-bit
—
QFN24/QSOP24
QFN24/QSOP24
QFN24/QSOP24
QFN24/QSOP24
QFN20
I C, SPI, UART
2
I C, SPI, UART
2
10-bit
—
I C, SPI, UART
2
I C, SPI, UART
2
12-bit
—
I C, SPI, UART
2
C8051F991
C8051F996
C8051F997
8 kB
8 kB
8 kB
512
512
512
25
25
25
16
17
17
QFN20
C8051F996DK
C8051F996DK
C8051F996DK
I C, SPI, UART
2
12-bit
—
QFN24/QSOP24
QFN24/QSOP24
I C, SPI, UART
2
14
I C, SPI, UART
Ultra Low-Power MCU
Copyright © 2010 by Silicon Laboratories
5.18.2010
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders
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