SI3050-EVB [SILICON]
Ability to read and write DAA registers;
| 型号： | SI3050-EVB |
| 厂家： | 
SILICON |
| 描述： | Ability to read and write DAA registers |
| 文件： | 总16页 (文件大小：187K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si3050-EVB
Si3050 EVALUATION BOARDS: Si3050PPT-EVB, Si3050PPT1-EVB,
Si3050FMPPT-EVB
Description
Features
The
Si3050
evaluation
boards
provide
the Ability to read and write DAA registers
telecommunications system engineer an easy way to
evaluate the functionality of Silicon Laboratories’
Si3050/Si3019 or Si3050/3018 integrated voice direct
access arrangement (DAA) solutions. The Si3050
integrates an SPI, PCM, and GCI serial interface as well
as system-side DAA functionality. In conjunction with
the Si3019 or Si3018 global line-side silicon DAA chip, it
provides a low-cost, solid-state, globally-compliant
voice DAA solution.
DAC waveform generation from a series of standard
waveforms or from a .wav file
ADC data capture and display in either time or
frequency domain
Recommended layout for key components
Daisy-chain support
There are three different Si3050 evaluation boards
available:
The Si3050PPT-EVB allows evaluation of the
Si3050 and Si3019 devices in TSSOP packages.
The Si3050PPT1-EVB allows evaluation of the
Si3050 and Si3018 devices in TSSOP packages.
The Si3050FMPPT-EVB allows evaluation of the
Si3050 and Si3019 devices in QFN packages.
The Si3050 evaluation boards can be easily controlled
from a PC using the supplied application software.
Functional Block Diagram
Si-LINK
FPGA
Daughter Card
PPT
TIP
RING
SPI
BOM
Si3050 Si3019
Optional
Ground Start
Circuit
Optional
Speaker
BNC/Audio
Precision Box
PCM/GCI
Rev. 1.1 7/11
Copyright © 2011 by Silicon Laboratories
Si3050-EVB
Si3050-EVB
1.2. Power Supply
1. Functional Description
Power is supplied to the Si-LINK motherboard by
means of J1 and J4. J4 is a 2.1 mm power jack that
allows the use of a wall transformer. A 9 V supply/
300 mA is typically used, but the on-board voltage
regulator will also work with a dc voltage between 7.5 V
and 20 V. A diode bridge is used to correct polarity. The
on-board regulator, U7, provides 5 V to the call progress
circuit, the on-board oscillator, and other boards daisy
chained to the motherboard. This 5 V is further
regulated to 3.3 V to power the daughter card and the
input/output ports of the motherboard's FPGA. A third
regulator provides 2.5 V for the core voltage of the
FPGA. J1 is a no-connect in this application.
The
Si3050
evaluation
boards
provide
the
telecommunications system engineer an easy way to
evaluate the Si3050 plus Si3018/3019 solution. Silicon
Labs’ DAAs are integrated direct access arrangements
that provide a digital, low-cost, solid-sate interface to
worldwide telephone lines. Through the patented
ISOcap™ technology, these chipsets eliminate the need
for an analog frond end (AFE), an isolation transformer,
relays, opto-isolators, and a 2- to 4-wire hybrid.
The Si3050 evaluation boards also support the
connection of multiple devices on an SPI/PCM
interface. The evaluation boards provide
straightforward means of evaluating this feature.
a
1.3. Clock Generation
The evaluation board consists of the Si-LINK
motherboard and one of the three available Si3050 The Si3050 requires an FSYNC, PCLK, and SCLK
daughter cards. A custom ribbon cable is also provided input. An on-board oscillator (Y1) is used by the FPGA
to connect to the parallel port of a PC. Contact a Silicon to clock all the subsystems as well as generate and
Laboratories representative for more information.
provide the FSYNC, PCLK, and SCLK to the DAA.
FPGA is designed to use a 32.768 MHz oscillator
(included with the board).
1.1. Motherboard-Daughter Card Connec-
tion
1.4. Reset Circuit
The Si3050 daughter card connects to the Si-LINK
motherboard through five sockets, JS1–JS5. JS1 is a
5x2 socket and JS2 is a 2x2 socket connecting SPI
digital signals of the Si3050. JS3 is a 5x2 socket
connection reserved for future use. JS4 is a 5x2 socket
connection that routes the Vdd regulated supply. JS5 is
a 5x2 socket connection to the PCM digital signals of
the Si3050. JS3 is a no-connect in this application.
The Si3050 chipset requires an active low pulse on
RESET following power up and whenever all registers
need to be reset. For development purposes, the Si-
Link motherboard includes a reset push button, SW1,
that is used by the FPGA to generate a reset pulse of
the DAA.
1.5. Line Connection
J1 is provided to connect the Si3050 daughter board to
a standard RJ-11 connector. The system cannot
execute an off-hook command without the phone line
connected.
1.6. PC Parallel Port
JP2 and P3 connect through the Silicon Labs custom
ribbon cable to the parallel port of the PC. The parallel
port connection allows the designer to read and write
the DAA registers using the evaluation software
included with the evaluation board.
2
Rev. 1.1
Si3050-EVB
By changing the jumper configuration prior to powering
the board, the mode of the board can be set according
2. Configuring the Si-LINK
The Si-LINK motherboard is used to interface the to Tables 1–3.
Si3050 to a PC or other audio system for easy
JP10 is the sixth jumper on the Si-LINK motherboard.
evaluation. It uses an FPGA to translate the parallel port
interface to either SPI/PCM, SPI-only, or GCI to
communicate with the Si3050.
Moving this jumper to the INT position routes pin 9 of
the Si3050 to the Si-LINK motherboard. When the
jumper is in the AOUT position, this signal is routed to
When in SPI/PCM mode, the PCM audio data and SPI the optional call progress speaker system, which is not
control data are communicated from the controlling PC populated by default on the evaluation platform. Refer to
using the aforementioned software. This mode allows the AOUT PWM circuit in the Si3050 data sheet for
the user to evaluate the DAA without any lab equipment values used to populate this circuit.
other than a PC.
By selecting SPI-only operation, the PC is still used to
control the DAA through the SPI bus, but the PCM
audio data is routed from an external source. This
external source may be an Audio Precision system
using the P1 and P2 headers or a PCM highway using
the BNC connectors, J5–J8 (not populated).
Table 1. PCM or GCI Highway Mode Selection
SCLK
SDI
Mode Selected
1
0
X
0
PCM Mode
GCI Mode,
B2 Channel used
GCI Mode,
To evaluate the Si3050’s operation with the GCI
interface, the PC may be used to send the audio data
and control. The FPGA performs the necessary
translation to communicate to the Si3050 in this mode.
0
1
B1 Channel used
Note: Values shown are the states of the pins at the
rising edge of RESET.
The fourth mode of operation is the pass-thru mode. In
this mode, the FPGA is only used to route the GCI bus
to the Audio Precision or BNC headers on the Si-LINK
board. In this mode, a PC is not required to control the
evaluation platform.
Table 2. Pin Functionality in PCM or GCI
Highway Mode
Pin Name PCM Mode
GCI Mode
Mode
SPI/PCM
SPI-Only
GCI
JP3 (Source)
JP4 (Format)
SDI_THRU SPI Data Through-
put pin for Daisy
Sub-frame
Selector, bit 2
0
1
0
1
0
0
1
1
Chaining Operation
(Connects to the SDI
pin of the subse-
quent device in the
daisy chain)
Pass-Thru
SCLK
SDI
SPI Clock Input
PCM/GCI Mode
Selector
3. Configuring the Si3050DC-EVB
SPI Serial Data Input B1/B2 Channel
Selector
The Si3050DC-EVB has six jumpers. The first five
control the boot-strap options for configuring the
Si3050. The default state is set to allow the Si3050 to be
controlled using the SPI bus. See Figure 1.
SDO
SPI Serial Data Out- Sub-frame
put
Selector, bit 1
SPI Chip Select
Sub-frame
CS
Selector, bit 0
FSYNC
PCM Frame Sync
Input
GCI Frame Sync
Input
0 SDI_THRU 1
0
CS
1
0
SCLK 1
0
SDO
1
0
SDI
1
PCLK
DTX
PCM Input Clock
GCI Input Clock
Figure 1. SPI Control Mode Default State
PCM Data Transmit GCI Data Transmit
PCM Data Receive GCI Data Receive
DRX
Note: This table denotes pin functionality after the rising
edge of RESET and mode selection.
Rev. 1.1
3
Si3050-EVB
Table 3. GCI Mode Sub-Frame Selection
SDI_THRU
SDO
CS
GCI Subframe 0 Selected
(Voice channels 1–2)
1
1
1
0
0
1
1
0
0
1
GCI Subframe 1 Selected
(Voice channels 3–4)
1
1
1
0
0
0
0
0
1
0
1
0
1
0
GCI Subframe 2 Selected
(Voice channels 5–6)
GCI Subframe 3 Selected
(Voice channels 7–8)
GCI Subframe 4 Selected
(Voice channels 9–10)
GCI Subframe 5 Selected
(Voice channels 11–12)
GCI Subframe 6 Selected
(Voice channels 13–14)
GCI Subframe 7 Selected
(Voice channels 15–16)
4
Rev. 1.1
Si3050-EVB
4. Evaluation Software
5. Using the Si3050PPT-EVB
The Si3050 evaluation boards include an easy-to-use
graphical interface for controlling the evaluation
platform. This software allows the system designer to
characterize the Si3050 DAA performance without
constructing any custom hardware. The evaluation
software includes the following features:
Application Software
A shortcut for starting the application software that
controls the evaluation board is installed in the Windows
Start Menu under the Programs folder in the “Si3050
Evaluation Software” folder.
Ability to read and write DAA registers using the SPI
5.1. Application Menus
Three pulldown menus are used to configure the
operation of the software:
or GCI bus
DAC waveform generation from a series of standard
waveforms or from a .wav file
Run:
ADC data capture and display in either the time or
Exit: Stops the program
Save: Stores the audio waveform into .wav files
Configure:
frequency domain using either PCM or GCI bus
Daisy-chain support
Transmit and receive path attenuation and gain
Configure DAA: Display hardware status and user
configuration. User can set advanced software options.
Reset DAA: Resets DAA and executes basic
initialization sequences on Reg 1, Reg 5–7, Reg 33–37,
and Reg 42
settings
Ring detection
Loop current measurement
4.1. PC System Requirements
The application software for the Si3050 evaluation
boards has the following system requirements:
Design Tool
Register Map: Displays Register Map of Si3050
Signal Flow Diagram: Displays Signal Flow Diagram of
Si3050 and Si3019.
Transhybrid Loss Calculation: Calculate transhybrid loss
over frequency
®
®
®
Windows98 , Windows2000 , or WindowsXP
Available parallel port
®
EPP or ECP parallel port mode for Windows 98
Ringing: Help user program ring validation registers.
®
EPP parallel port mode for Windows 2000 and
Help: Displays information about the evaluation
®
board
WindowsXP
®
450 MHz Pentium II or greater recommended
64 MB of memory or greater recommended
4.2. Installation
The supplied CD contains the Si3050PPT-EVB windows
driver files as well as a setup utility for installing the
evaluation software.
To install the Si3050PPT-EVB software, run the
installation program on the “Silicon Laboratories
Wireline Software CD.” The path for the installation
program is Si3050 Evaluation Software\setup.exe. The
installer guides the user through the installation process
for Si3050PPT-EVB.exe and the LabVIEW Run-Time
engine.
Rev. 1.1
5
Si3050-EVB
Figure 2. Si3050PPT-EVB Evaluation Software in the DSP Mode Control and
RCV Source Control View
PCLK Frequency: Selects the frequency of the
5.2. DSP Mode and RCV Source Control
View
The user interface in the DSP Mode and RCV Source
PCLK in PCM mode from 256 kHz to 8.192 MHz in
power of 2.
Control view for the Si3050PPT_EVB software is shown SCLK Frequency: Selects the frequency of the
in Figure 2. This figure shows the DAA’s mode of
communication and RCV source for each channel when
the application is launched.
SCLK from 256 kHz to 8.192 MHz in power of 2.
SPI Mode: Selects the length of CS to either 8-bit or
16-bit.
DSP Mode Control
GCI Clock Mode: Selects the frequency and clock
mode of PCLK in GCI mode from either 1x
2.048 MHz or 2x 4.096 MHz.
DSP mode control is described in the following list:
Format: Selects the format of the audio data to be
transmitted over PCM or GCI bus. By changing the
format, the software will automatically execute a
write to DAA Register 33 PCMF bits or DAA
Register 44 GCIF bits.
GCI Subframe: Selects the subframe in GCI mode
with which to communicate.
B-Channel: Selects the B channel desired during
GCI communication.
Changes in the DSP Mode panel will not take effect until
assertion of the “Reset & Reinitialize the System”
button.
DAA Interface Mode: Selects the mode of operation
of the DAA from SPI/PCM, SPI/BNC, GCI, or GCI/
BNC. Upon startup, this mode will reflect the “format”
and “source” jumper selection on the SiLink (mother)
board. The selection made via the jumper can be
overwritten here.
5.2.1. RCV Source Control
RCV Source Control utilizes the daisy-chain capability
of the DAA in SPI/PCM communication mode. RCV
source determines the source of audio data for each
device on the SiLink board.
PCM Clock Mode: Selects the clock mode of PCM
from 1x to 2x.
Changes in RCV source will not take effect until
assertion of the “Update RCV Source” button.
6
Rev. 1.1
Si3050-EVB
Figure 3. Si3050PPT-EVB Evaluation Software in the Audio Data Monitoring View
Amplitude: Sets the amplitude of the DAC
waveform in either volts or the units of DAC codes.
The units are determined by the Amplitude Units
control.
5.3. Audio Data Monitoring View
The audio data monitoring view is discussed in the
following sections.
5.3.1. Receive Audio Data of Channel#
Frequency: Selects the frequency (Hz) of the
waveform to generate. The actual waveform
frequency may vary slightly from the entered value.
This variation is due to the requirement to fit an
integer number of samples into the transmit buffer.
The control is updated to reflect the actual waveform
frequency generated. The equation for calculating
the frequency of the waveform is as follows:
Allows selection of channel to control and view. The
Audio Data Monitoring view allows the generation of
DAC data and the capture and display of ADC data.
Operation of the front panel in Line Monitoring view is
detailed in the following list. See Figure 3.
5.3.2. TX Control
DAC Waveform: Selects the waveform to be
generated by the DAC. The waveform types are as
follows: dc, Sine, Square, Ramp, and .wav file.
Actual Frequency = round ((Waveform Frequency/DAC
Sample Rate) x BufferSize) x (DAC Sample Rate/
BufferSize)
TX Gain (dB): Selects the transmit path gain/
attenuation.
TX Mute: Mutes the transmit path
Rev. 1.1
7
Si3050-EVB
5.3.3. RX Control
5.3.6. Wave Display Controls
Monitor Mode: Allows the selection of several data
modes. Digital Loopback mode routes the DAC data
back to the receive path. On-hook mode configures
the DAA to the on-hook mode. Off-hook mode
configures the DAA to the off-hook mode. On-hook
line monitoring mode configures the DAA to the line
monitoring state.
Display Type: Selects how the ADC data is
displayed on the Waveform Graph (time or
frequency domain).
Amplitude Units: Sets the amplitude units for the
Waveform Graph and Amplitude control to either
volts or codes.
Acquisition: Used to run or pause the codec data
stream. Upon pausing the acquisition of the data, it
displays measurement values regardless of the
status of “display measurement” under the Configure
menu.
RX Gain (dB): Selects the receive path gain/
attenuation.
RX Mute: Mutes the receive path
Ring Detect Mode: Allows selection of full-wave or
half-wave ring detection.
X Autoscale: Automatically scales the X-axis of the
graph to fit the entire waveform.
5.3.4. Dialer
Y Autoscale: Automatically scales the Y-axis to fit
Dial Number: Inputs dial number
Dial: Executes dial
5.3.5. Measurement
the entire vertical range of the waveform.
Xmin: Sets the origin of the X-axis when X
Autoscale is disabled.
Loop Current: Displays the loop current when in off-
X Zoom: Used to zoom a portion of the displayed
waveform when X Autoscale is disabled. The
waveform starts at Xmin and 1/X Zoom of the total
waveform is displayed.
hook mode.
Ring Detect Bits: Displays the state of the ring
detect bits when in on-hook mode.
Off-Hook: Indicates that the DAA is in the off-hook
Yo: Sets the origin of the Y-axis when Y Autoscale is
disabled. Half of the waveform is displayed above
Yo, and half is displayed below Yo.
state.
DC Level/SINAD: Displays either the dc level of the
time domain waveform or the SINAD of the
frequency domain waveform.
RMS Level/Frequency: Displays either the rms
level of the time domain waveform or the frequency
of the largest peak in the frequency domain
waveform.
Num Avg for FFT: When in FFT display, the
software will automatically average waveforms. This
panel selects the number of averages to take.
8
Rev. 1.1
Si3050-EVB
Figure 4. Si3050PPT-EVB Evaluation Software in the Register Table Display View
Write DAA Regs: Causes the contents of the DAA
Reg Value control to be written to the DAA Reg Num
register.
5.4. Register Table Display View
The DAA Register view allows the Si3050 DAA
registers to be read or written. The user interface for the
DAA Register view is shown in Figure 4. Operation of
the front panel in the DAA Register view is detailed in
the following list:
Broadcast: Turns on the broadcast bit (SPI only).
FDT: Shows the status of FDT bit, which indicates
the Si3050 is communicating with the Si3019.
Off-Hook: Shows the status of the off-hook bit, DAA
Table: This table displays the contents of the Si3050
Register 5, bit 1.
DAA registers in realtime.
CIR Bits: Allows writing and reading of CIR bits.
DAA Reg Num: The Si3050 DAA register number to
(GCI only).
write (in decimal).
DAA Reg Value: The contents to write to the register
selected by the DAA Reg Num control (in
hexadecimal).
Rev. 1.1
9
Si3050-EVB
Figure 5. Configure DAA Panel
5.5. Advanced Configuration
Advanced configuration of the application software is
accomplished by using the “Configure DAA” selection in
the “Configure” menu. The configuration panel is shown
in Figure 5. The panel contents are detailed in the
following list:
FFT Window: The FFT window applied to the time
domain data before calculating the FFT.
Acquisition Buffer Size: This is the size of the
buffer, in samples, that is acquired and displayed on
the Line Monitoring mode waveform graph. The
buffer size can be set to between 1024 and 65536
samples in increments of 512 samples.
Display Measurement: Takes realtime
measurements of audio waveform.
10
Rev. 1.1
Si3050-EVB
Figure 6. Si3050 Signal Flow Diagram
5.6. Signal Flow Diagrams
5.7. Si3050 Signal Path Control
The signal flow diagrams of the application software PCML: Turns on/off the PCML bit on DAA Register
shown in Figure 6 on page 11 and Figure 7 on page 12
assist users with programming DAA.
33, bit 7
TX Mute: Turns on/off the TXM bit on DAA Register
15, bit 7
TX Gain: Writes to TGA2, TXG2, TGA3, and TXG3
on DAA Register 38 and 40
IIRE: Turns on/off IIRE bit on Register 16, bit 4
DDL: Turns on/off DDL bit on Register 10, bit 1
RX Mute: Turns on/off RXM bit on Register 15, bit 0
RX Gain: Writes to RGA2, RXG2, RGA3, and RXG3
on DAA Register 39 and 41
FILT: Turns on/off FILT bit on Register 31, bit 1
ARM: Writes to ARM on Register 20
ATM: Writes to ATM on Register 21
INTE: Turns on/off INTE bit on Register 2, bit 7
INTP: Turns on/off INTP bit on Register 2, bit 6
AOUT: Writes to PWMM and PWEM on Register 1
Si3019 Signal Path Control
Rev. 1.1
11
Si3050-EVB
Figure 7. Si3019 Signal Flow Diagram
5.8. Si3019 Signal Path Control
AL: Turns on/off AL bit on Register 2, bit 3
HBE: Turns on/off HBE bit on Register 2, bit 1
RXE: Turns on/off RXE bit on Register 2, bit 0
IDL: Turns on/off IDL bit on Register 1, bit 1
PDL: Turns on/off PDL bit on Register 6, bit 4
FULL: Turns on/off FULL bit on Register 31, bit 7
12
Rev. 1.1
Si3050-EVB
Figure 8. Transhybrid Loss
5.9. Transhybrid Loss Calculation
When “Transhybrid Loss Calculation” is selected, the
Si3050PPT-EVB software will drive a signal with
different frequencies and measure the transhybrid loss
based on the following equation: TL = 20Log(TXpk-pk/
RXpk-pk). Frequencies used to measure this start
from100 Hz to 4000 Hz in 20 Hz steps.
Rev. 1.1
13
Si3050-EVB
5.10. Ringing
RNGV-Enable: Turns on/off RNGV bit on Register
24, bit7
RAS[5:0]: Update RAS bits on Register 24
RMX[5:0]: Update RMX bits on Register 22
RCC[2:0]: Update RCC bits on Register 23
RTO[3:0]: Update RTO bits on Register 23
RDLY[2:0]: Update RDLY bits on Register 22 & 23
Fmin(Hz): Calculate fmin based on RAS bits
Fmin(Hz): Calculate fmax based on RAS bits and
RMX bits
Ring confirmation count (ms): Shows ring
confirmation count based on RCC bits
Ring timeout(ms): Displays ring timeout based on
RTO bits
Ring delay(ms): displays ring delay based on RDLY
bits
Figure 9. Ringing
14
Rev. 1.1
Si3050-EVB
DOCUMENT CHANGE LIST
Revision 0.2 to Revision 0.3
Updated schematics
Updated BOMs
Updated layers
Revision 0.3 to Revision 0.4
"1. Functional Description" on page 2: deleted text
Table 3 moved
Figure 4 updated
Figure 8 updated
"5.8. Si3019 Signal Path Control" on page 12: Added
text.
"5.9. Transhybrid Loss Calculation" on page 13
added.
Revision 0.4 to Revision 1.0
Updated Si3050 EVB schematics.
Updated Si3050 EVB layout.
Updated Si3050 EVB BOM.
Added notification of support for Windows XP.
Updated layout figure titles.
Revision 1.0 to Revision 1.1
Updated to include Si3050PPT1-EVB and
Si3050FMPPT-EVB as well as Si3050PPT-EVB
Removed schematics, BOM, and layout sections;
these are included on the disk supplied with the
evaluation boards.
Rev. 1.1
15
Si3050-EVB
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Please visit the Silicon Labs Technical Support web page:
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-
sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap-
plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Si-LINK, Silicon Laboratories, and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
16
Rev. 1.1
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