SI50122-A1-GM [SILICON]
Processor Specific Clock Generator, 100MHz, CMOS, PDSO10, TDFN-10;
| 型号： | SI50122-A1-GM |
| 厂家： | 
SILICON |
| 描述： | Processor Specific Clock Generator, 100MHz, CMOS, PDSO10, TDFN-10 时钟 光电二极管 外围集成电路 |
| 文件： | 总14页 (文件大小：1143K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si50122-A1/A2
CRYSTAL-LESS PCI-EXPRESS GEN1 DUAL OUTPUT
CLOCK GENERATOR
Features
Crystal-less clock generator with
integrated CMEMS
Triangular spread spectrum
profile for maximum EMI
reduction (Si50122-A2)
Industrial Temperature –40 to 85 °C
2.5 V, 3.3 V Power supply
PCI-Express Gen 1 compliant
Two PCIe 100 MHz differential HCSL
outputs
One 25 MHz single-ended LVCMOS Small package 10-pin TDFN
output
(2.0 x 2.5 mm)
Supports Serial (ATA) at 100 MHz
Low power differential output buffers
No termination resistors required for
differential output clocks
Si50122-A1 does not support spread
spectrum outputs
Si50122-A2 supports 0.5%
down spread outputs
Ordering Information:
See page 10
Applications
Pin Assignments
Si50122-A1/A2
Network Attached Storage
Multi-function Printer
Digital TV
Solid State Drives (SSD)
Wireless Access Point
Home Gateway
VSS
REFOUT
NC
1
2
3
4
5
10
9
VDD
VDD
Set top box
Digital Video Camera
Description
8
DIFF2
DIFF2
Si50122-A1/A2 is a high-performance, crystal-less PCIe clock generator that can
generate two 100 MHz PCIe clock and one 25 MHz LVCMOS clock outputs. The
differential clock outputs are compliant to PCIe Gen1 specifications. The ultra-
small footprint (2.0 x 2.5 mm) and industry leading low-power consumption makes
Si50122-A1/A2 the ideal clock solution for consumer and embedded applications
where board space is limited and low power is needed.
7
DIFF1
DIFF1
6
VSS
Patents pending
Functional Block Diagram
VDD
REFOUT
DIFF1
PLL
(SSC)
Divider
CMEMS
DIFF2
VSS
Rev 0.7 9/14
Copyright © 2014 by Silicon Laboratories
Si50122-A1/A2
Si50122-A1/A2
2
Rev 0.7
Si50122-A1/A2
TABLE OF CONTENTS
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Test and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
5. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
6. Recommended Design Guideline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Rev 0.7
3
Si50122-A1/A2
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Supply Voltage (3.3 V Supply)
V
V
3.3 V ± 10%
2.97
3.3
3.63
V
DD
DD
Supply Voltage (2.5 V Supply)
2.5 V ± 10%
2.25
2.5
2.75
V
Table 2. DC Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Operating Voltage
V
V
3.3 V ± 10%
2.97
3.30
3.63
V
DD
(V = 3.3 V)
DD
Operating Voltage
2.5 V ± 10%
2.25
2.5
2.75
V
DD
DD
(V = 2.5 V)
DD
Operating Supply Current
I
Full Active; 3.3 V ± 10%
Full Active; 2.5 V ± 10%
Input Pin Capacitance
Output Pin Capacitance
—
—
—
—
20
18
3
23
21
5
mA
mA
pF
Input Pin Capacitance
Output Pin Capacitance
C
IN
C
—
5
pF
OUT
4
Rev 0.7
Si50122-A1/A2
Table 3. AC Electrical Specifications
Parameter
DIFF Clocks
Symbol
Test Condition
Min
Typ
Max
Unit
Duty Cycle
T
Measured at 0 V differential
Measured at 0 V differential
45
—
—
—
—
—
55
100
—
%
DC
Skew
T
ps
SKEW
Output Frequency
Frequency Accuracy
F
V
= 3.3 V
DD
100
—
MHz
ppm
OUT
F
All output clocks
100
ACC
Measured differentially from
±150 mV
Slew rate
t
0.6
—
—
5.0
35
V/ns
ps
r/f2
PCIe Gen1 Pk-Pk Jitter
Pk-Pk
Pk-Pk
PCIe Gen 1,
20.7
GEN1
GEN1
V
V
= 3.3 V ±10%
DD
PCIe Gen1 Pk-Pk Jitter
PCIe Gen 1,
= 2.5 V ±10%
—
25
—
40
ps
DD
Crossing Point Voltage at 0.7 V
Swing
V
300
550
mV
OX
Voltage High
V
—
–0.3
—
—
—
1.15
—
V
V
HIGH
Voltage Low
V
S
LOW
RNG
MOD
Spread Range
Down Spread, –A2 only
–A2 only
—
–0.5
33
%
Modulation Frequency
25 MHz at 3.3 V
Duty Cycle
F
30
31.5
kHz
T
Measurement at 1.5 V
45
—
—
—
—
—
1.2
1.2
—
55
3.0
3.0
250
100
%
ns
DC
Output Rise Time
Output Fall Time
Cycle to Cycle Jitter
Long Term Accuracy
Powerup Time
t
C = 10 pF, 20% to 80%
L
r
t
C = 10 pF, 20% to 80%
ns
f
L
T
Measurement at 1.5 V
Measured at 1.5 V
ps
CCJ
ACC
L
—
ppm
Clock Stabilization from Powerup
T
First power up to first output
—
—
10
ms
STABLE
*Note: Visit www.pcisig.com for complete PCIe specifications.
Rev 0.7
5
Si50122-A1/A2
Table 4. Thermal Conditions
Parameter
Symbol
Test Condition
Min
Typ
Max Unit
Temperature, Storage
T
Non-functional
–65
150
85
°C
°C
°C
S
Temperature, Operating Ambient
Temperature, Junction
T
Functional
Functional
–40
—
A
T
150
J
Dissipation, Junction to Case
Dissipation, Junction to Ambient
Ø
JEDEC (JESD 51)
JEDEC (JESD 51)
—
38.3 °C/W
90.4 °C/W
JC
JA
Ø
—
Table 5. Absolute Maximum Conditions
Parameter
Main Supply Voltage
Symbol
Test Condition
Min
Typ
Max Unit
V
—
4.6
4.6
—
V
DD_3.3 V
Input Voltage
V
Relative to V
–0.5
V
DC
IN
SS
ESD Protection (Human Body Model)
Flammability Rating
ESD
JEDEC (JESD 22 - A114) 2000
UL (Class)
V
HBM
UL-94
V–0
Note: While using multiple power supplies, the voltage on any input or I/O pin cannot exceed the power pin during powerup.
Power supply sequencing is not required.
6
Rev 0.7
Si50122-A1/A2
2. Test and Measurement Setup
Figure 1–Figure 3 show the test load configuration for the differential clock signals.
M easurem ent
Point
L1
OUT+
50
2 pF
L1 = 5"
M easurem ent
Point
L1
OUT-
50
2 pF
Figure 1. 0.7 V Differential Load Configuration
Figure 2. Differential Measurement for Differential Output Signals
(for AC Parameters Measurement)
Rev 0.7
7
Si50122-A1/A2
Figure 3. Single-ended Measurement for Differential Output Signals
(for AC Parameters Measurement)
L1 = 0.5", L2 = 5"
Measurement
Point
50
REF
L2
L1
10 pF
33
Figure 4. Single-ended Clocks with Single Load Configuration
Figure 5. Single-ended Output Signal (for AC Parameter Measurement)
8
Rev 0.7
Si50122-A1/A2
3. Pin Descriptions
VSS
1
2
3
4
5
10
9
VDD
VDD
REFOUT
NC
8
DIFF2
DIFF2
7
DIFF1
DIFF1
6
VSS
Figure 6. 10-Pin TDFN
Table 6. Si50122-Ax-GM 10-Pin TDFN Descriptions
Pin #
Name
Type
Description
GND
Connect to Ground
1
VSS
O, SE 25 MHz LVCMOS clock output
NC No Connect; do not connect this pin to anything.
2
3
REFOUT
NC
O, DIF 0.7 V, 100 MHz differential clock output
O, DIF 0.7 V, 100 MHz differential clock output
4
DIFF1
DIFF1
VSS
5
GND
Connect to Ground
6
O, DIF 0.7 V, 100 MHz differential clock output
O, DIF 0.7 V, 100 MHz differential clock output
7
DIFF2
DIFF2
8
PWR
PWR
Power supply
Power supply
9
V
V
DD
DD
10
Rev 0.7
9
Si50122-A1/A2
4. Ordering Guide
Part Number
Si50122-A1-GM
Si50122-A1-GMR
Si50122-A2-GM
Si50122-A2-GMR
Spread Option
Package Type
10-pin TDFN
Temperature
No Spread
No Spread
Industrial, –40 to 85 C
Industrial, –40 to 85 C
Industrial, –40 to 85 C
Industrial, –40 to 85 C
10-pin TDFN—Tape and Reel
10-pin TDFN
–0.5% Spread
–0.5% Spread
10-pin TDFN—Tape and Reel
GMR
Si50122
Ax
Operating Temp Range:
G: -40 to +85 °C
Base part number
M:10-TDFNPackage,ROHS6,Pb-free
R: Tape & Reel
(blank) = Tubes
A: Product Revision A
x=1: non-spread outputs
x=2: -0.5% spread outputs
Figure 7. Ordering Information
10
Rev 0.7
Si50122-A1/A2
5. Package Outlines
Figure 8. 10-Pin TDFN Package Drawing
Rev 0.7
11
Si50122-A1/A2
Table 7. Package Diagram Dimensions
Symbol
Min
0.80
0.00
Nom
0.85
Max
0.90
0.05
A
A1
—
A3
0.203 REF.
0.25
b
0.20
0.30
D
2.00 BSC.
0.50 BSC
2.50 BSC.
0.4
e
E
L
0.35
0.45
aaa
bbb
ccc
ddd
eee
Notes:
0.10
0.10
0.10
0.05
0.08
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerances per ANSI Y14.5M-1994.
3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
4. This drawing conforms to the JEDEC Solid State Outline MO-229.
12
Rev 0.7
Si50122-A1/A2
6. Recommended Design Guideline
3.3V / 2.5V
FB
VDD
4.7uF 0.1uF
Si50122
Figure 9. Recommended Application Schematic
Note: FB Specifications: DC resistance 0.1–0.3 , Impedance at 100 MHz > 1000
Rev 0.7
13
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using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific
device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories
reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy
or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply
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