SI5350A-B09240-GM_技术文档

Si5350A-B

FACTORY-PROGRAMMABLE ANY-FREQUENCY CMOS

CLOCK GENERATOR

Features



www.silabs.com/custom-timing

Generates up to 8 non-integer-related

frequencies from 2.5 kHz to 200 MHz

Exact frequency synthesis at each

output (0 ppm error)



Operates from a low-cost, fixed

frequency crystal: 25 or 27 MHz

Separate voltage supply pins provide

level translation:

Core VDD: 1.8 V, 2.5 V or 3.3 V

Output VDDO: 1.8 V, 2.5 V or 3.3 V

10-MSOP



Glitchless frequency changes

Low output period jitter: < 70 ps pp, typ  Excellent PSRR eliminates external

Configurable Spread Spectrum

selectable at each output

User-configurable control pins:

Output Enable (OEB_0/1/2)

Power Down (PDN)

Frequency Select (FS_0/1)

Spread Spectrum Enable (SSEN)

Supports static phase offset

Rise/fall time control

power supply filtering

Very low power consumption

(25 mA core, typ)

Available in 2 packages types:

10-MSOP: 3 outputs

20-QFN (4x4 mm): 8 outputs

PCIE Gen 1 compatible

Supports HCSL jitter compatible

swing

20-QFN



Ordering Information:

See page 17

Applications



HDTV, DVD/Blu-ray, set-top box

Audio/video equipment, gaming

Printers, scanners, projectors

Handheld instrumentation



Residential gateways

Networking/communication

Servers, storage

XO replacement

Description

The Si5350A is a highly-flexible, user-definable custom clock generator that is ideally

suited for replacing crystals and crystal oscillators in cost-sensitive applications.

Based on a PLL + high resolution fractional divider MultiSynth^TMarchitecture, the

Si5350A can generate any frequency up to 200 MHz on each of its outputs with

0 ppm error. Spread spectrum is selectable (on/off) on any of the outputs. Custom

pin-controlled Si5350A devices can be requested using the ClockBuilder web-based

part number utility (www.silabs.com/ClockBuilder).

Functional Block Diagram

Si5350A (20-QFN)

VDDOA

XA

MultiSynth

PLL

A

CLK0

CLK1

0

VDDO

OSC

Si5350A (10-MSOP)

MultiSynth

1

XB

XA

XB

VDDOB

CLK2

PLL

B

PLL

MultiSynth

2

MultiSynth 0

MultiSynth 1

MultiSynth 2

CLK0

CLK1

CLK2

OSC

A

MultiSynth

3

CLK3

PLL

B

P0

P1

VDDOC

CLK4

MultiSynth

4

Control

Logic

P0

P1

MultiSynth

5

CLK5

Control

Logic

P2

P3

P4

VDDOD

CLK6

MultiSynth

6

MultiSynth

7

CLK7

Rev. 1.1 9/18

Si5350A-B

Table 1. The Complete Si5350/51 Clock Generator Family

Part Number

I2C or Pin

I2C

Frequency Reference

XTAL only

Programmed?

Blank

Outputs Datasheet

3

8

3

8

3

8

3

8

3

8

Si5351-B

Si5350A-B

Si5350B-B

Si5350C-B

Si5351A-B-GT

I2C

XTAL only

Blank

Si5351A-B-GM

I2C

XTAL and/or Voltage

XTAL and/or CLKIN

XTAL only

Blank

Si5351B-B-GM

I2C

Blank

Si5351C-B-GM

I2C

Factory Pre-Programmed

Si5351A-Bxxxxx-GT

Si5351A-Bxxxxx-GM

Si5351B-Bxxxxx-GM

Si5351C-Bxxxxx-GM

Si5350A-Bxxxxx-GT

Si5350A-Bxxxxx-GM

Si5350B-Bxxxxx-GT

Si5350B-Bxxxxx-GM

Si5350C-Bxxxxx-GT

Si5350C-Bxxxxx-GM

Notes:

I2C

XTAL only

I2C

XTAL and/or Voltage

XTAL and/or CLKIN

XTAL only

I2C

XTAL only

XTAL and/or Voltage

XTAL and/or CLKIN

1. XTAL = 25/27 MHz, Voltage = 0 to VDD, CLKIN = 10 to 100 MHz. "xxxxx" = unique custom code.

2. Create custom, factory pre-programmed parts at www.silabs.com/ClockBuilder.

2

Rev. 1.1

Si5350A-B

TABLE OF CONTENTS

Section

Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2. Typical Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

2.1. Si5350A Replaces Multiple Clocks and XOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

2.2. Applying a Reference Clock at XTAL Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

2.3. HCSL Compatible Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

4. Configuring the Si5350A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

4.1. Crystal Inputs (XA, XB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

4.2. Output Clocks (CLK0–CLK7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

4.3. Programmable Control Pins (P0–P4) Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

4.4. Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

5.1. 20-pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

5.2. 10-pin MSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

6. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

7. 20-Pin QFN Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

8. Land Pattern: 20-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

9. 10-pin MSOP Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

10. Land Pattern: 10-Pin MSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

11. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

11.1. 20-Pin QFN Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

11.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

11.3. 10-Pin MSOP Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

11.4. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Rev. 1.1

3

Si5350A-B

1. Electrical Specifications

Table 2. Recommended Operating Conditions

Parameter

Symbol

Test Condition

Min

–40

1.71

2.25

3.0

Typ

25

Max

85

Unit

°C

V

Ambient Temperature

T

A

1.8

2.5

3.3

1.8

2.5

3.3

1.89

2.75

3.60

1.89

2.75

3.60

Core Supply Voltage

Output Buffer Voltage

V

DD

V

1.71

2.25

3.0

V

DDOx

V

Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.

Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted. VDD

and VDDOx can be operated at independent voltages. Power supply sequencing for VDD and VDDOx requires that all

VDDOx be powered up either before or at the same time as VDD.

Table 3. DC Characteristics

(V_DD= 1.8 V ±5%, 2.5 V ±10%, or 3.3 V ±10%, T_A= –40 to 85 °C)

Parameter

Symbol

Test Condition

Enabled 3 outputs

Min

—

Typ

20

Max

30

Unit

mA

µA

Core Supply Current*

I

Enabled 8 outputs

—

25

40

DD

Power Down (PDN = VDD)

—

50

Output Buffer Supply

Current (Per Output)*

I

C = 5 pF

—

2.2

5.6

mA

DDOx

L

Pins P1, P2, P3, P4

I

—

50

10

30

—

µA



P1-P4

V

< 3.6 V

Input Current

P1-P4

I

Pin P0

P0

3.3 V VDDO, default high

drive.

Output Impedance

Z

OI

*Note: Output clocks less than or equal to 100 MHz.

4

Rev. 1.1

Si5350A-B

Table 4. AC Characteristics

(V_DD= 1.8 V ±5%, 2.5 V ±10%, or 3.3 V ±10%, T_A= –40 to 85 °C)

Parameter

Powerup Time

Symbol

Test Condition

From V = V to valid output

Min

Typ

Max Unit

DD

DDmin

T

—

2

10

1

ms

RDY

clock, C = 5 pF, f

> 1 MHz

L

CLKn

From V = V

to valid output

DDmin

DD

Powerup Time, PLL Bypass Mode

T

—

0.5

BYP

clock, C = 5 pF, f

> 1 MHz

L

CLKn

From OEB assertion to valid clock

output, C = 5 pF, f > 1 MHz

Output Enable Time

T

—

10

µs

OE

L

CLKn

Output Frequency Transition Time

T

f

> 1 MHz

FREQ

CLKn

Spread Spectrum Frequency

Deviation

Down spread.

Selectable in 0.1% steps.

SS

–0.1

30

—

–2.5

33

%

DEV

Spread Spectrum Modulation Rate

SS

31.5

kHz

MOD

Table 5. Input Characteristics

(V_DD= 1.8 V ±5%, 2.5 V ±10%, or 3.3 V ±10%, T_A= –40 to 85 °C)

Parameter

Symbol

Test Condition

Min

25

Typ

—

Max

27

Unit

Crystal Frequency

f

MHz

V

XTAL

P0-P4 Input Low Voltage

V

–0.1

—

0.3 x V

3.60

IL_P0-4

DD

V

= 2.5 V or 3.3 V 0.7 x V

—

V

DD

P0-P4 Input High Voltage

V

IH_P0-4

V

= 1.8 V

0.8 x V

—

3.60

V

DD

Table 6. Output Characteristics

(V_DD= 1.8 V ±5%, 2.5 V ±10%, or 3.3 V ±10%, T_A= –40 to 85 °C)

Parameter Symbol Test Condition

Min

Typ

—

50

1

Max

Unit

1

Frequency Range

Load Capacitance

F

0.0025

—

200

15

MHz

pF

%

CLK

C

F

< 100 MHz

CLK

L

F

< 160 MHz, Measured at V /2

45

55

CLK

DD

Duty Cycle

DC

t /t

> 160 MHz, Measured at V /2

40

60

%

CLK

DD

Rise/Fall Time

Output High Voltage

Output Low Voltage

Notes:

20%–80%, C = 5 pF

—

1.5

—

ns

V

r f

L

V

– 0.6

DD

—

OH

V

—

0.6

V

OL

1. Only two unique frequencies above 112.5 MHz can be simultaneously output.

2. Measured over 10k cycles. Jitter is only specified at the default high drive strength (50  output impedance).

3. Jitter is highly dependent on device frequency configuration. Specifications represent a “worst case, real world”

frequency plan; actual performance may be substantially better. Three-output 10MSOP package measured with clock

outputs of 74.25, 24.576, and 48 MHz. Eight-output 20QFN package measured with clock outputs of 33.33, 74.25, 27,

24.576, 22.5792, 28.322, 125, and 48 MHz.

Rev. 1.1

5

Si5350A-B

Table 6. Output Characteristics (Continued)

(V_DD= 1.8 V ±5%, 2.5 V ±10%, or 3.3 V ±10%, T_A= –40 to 85 °C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

20-QFN, 4 outputs running,

1 per VDDO

—

40

95

ps pk-

pk

2,3

Period Jitter

J

PER

10-MSOP or 20-QFN,

all outputs running

—

70

50

70

155

90

20-QFN, 4 outputs running,

1 per VDDO

2,3

Cycle-to-Cycle Jitter

J

ps pk

CC

10-MSOP or 20-QFN,

all outputs running

150

Notes:

1. Only two unique frequencies above 112.5 MHz can be simultaneously output.

2. Measured over 10k cycles. Jitter is only specified at the default high drive strength (50  output impedance).

3. Jitter is highly dependent on device frequency configuration. Specifications represent a “worst case, real world”

frequency plan; actual performance may be substantially better. Three-output 10MSOP package measured with clock

outputs of 74.25, 24.576, and 48 MHz. Eight-output 20QFN package measured with clock outputs of 33.33, 74.25, 27,

24.576, 22.5792, 28.322, 125, and 48 MHz.

Table 7. 25 MHz Crystal Requirements^1,2

Parameter

Symbol

Min

—

Typ

25

—

Max

—

Unit

MHz

pF

Crystal Frequency

Load Capacitance

f

XTAL

C

6

12

L

Equivalent Series Resistance

Crystal Max Drive Level

Notes:

r

—

150

—



ESR

d

100

—

µW

L

1. Crystals which require load capacitances of 6, 8, or 10 pF should use the device’s internal load capacitance for

optimum performance. See register 183 bits 7:6. A crystal with a 12 pF load capacitance requirement should use a

combination of the internal 10 pF load capacitance in addition to external 2 pF load capacitance (e.g., by using 4pF

capacitors on XA and XB).

2. Refer to “AN551: Crystal Selection Guide” for more details.

Table 8. 27 MHz Crystal Requirements^1,2

Parameter

Symbol

Min

—

Typ

27

—

Max

—

Unit

MHz

pF

Crystal Frequency

Load Capacitance

f

XTAL

C

6

12

L

Equivalent Series Resistance

Crystal Max Drive Level Spec

Notes:

r

—

150

—



ESR

d

100

—

µW

L

1. Crystals which require load capacitances of 6, 8, or 10 pF should use the device’s internal load capacitance for

optimum performance. See register 183 bits 7:6. A crystal with a 12 pF load capacitance requirement should use a

combination of the internal 10 pF load capacitance in addition to external 2 pF load capacitance (e.g., by using 4pF

capacitors on XA and XB).

2. Refer to “AN551: Crystal Selection Guide” for more details.

6

Rev. 1.1

Si5350A-B

Table 9. Thermal Characteristics

Parameter

Symbol

Test Condition

Package

10-MSOP

20-QFN

Value

Unit

°C/W

131

119

Thermal Resistance

Junction to Ambient



Still Air

JA

Thermal Resistance

Junction to Case



Still Air

20-QFN

16

°C/W

JC

Table 10. Absolute Maximum Ratings

Parameter

DC Supply Voltage

Symbol

Test Condition

Value

Unit

V

–0.5 to 3.8

V

DD_max

V

Pins P1, P2, P3, P4

P0

IN_P1-4

Input Voltage

V

–0.5 to (V +0.3)

V

IN_P0

DD

V

Pins XA, XB

–0.5 to 1.3 V

–55 to 150

V

IN_XA/B

Junction Temperature

T

°C

J

Note: Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be

restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum

rating conditions for extended periods may affect device reliability.

Rev. 1.1

7

Si5350A-B

2. Typical Application

2.1. Si5350A Replaces Multiple Clocks and XOs

The Si5350A is a user-definable custom clock generator that is ideally suited for replacing crystals and crystal

oscillators in cost-sensitive applications. An example application is shown in Figure 1.

74.25

MHz

74.25 MHz or

1.001

33.3333 MHz

Video

Processor

CPU

27 MHz

XA

24.576 MHz

CLK3

Audio

Processor

27 MHz

Si5350A

22.5792 MHz

CLK4

XB

48 MHz

USB

Controller

28.322 MHz

HDMI

Port

125 MHz

Ethernet

PHY

Figure 1. Example of an Si5350A in an Audio/Video Application

2.2. Applying a Reference Clock at XTAL Input

The Si5350A can be driven with a clock signal through the XA input pin.

V_IN= 1 V_PP

25/27 MHz

Multi

Synth

0

PLLA

PLLB

XA

Multi

Synth

1

0.1 µF

OSC

XB

Multi

Synth

N

Note: Float the XB input while driving

the XA input with a clock

Figure 2. Si5350A Driven by a Clock Signal

8

Rev. 1.1

Si5350A-B

2.3. HCSL Compatible Outputs

The Si5350A can be configured to support HCSL compatible swing when the VDDO of the output pair of interest is

set to 2.5 V (i.e., VDDOA must be 2.5 V when using CLK0/1; VDDOB must be 2.5 V for CLK2/3 and so on).

The circuit in Figure 3 must be applied to each of the two clocks used, and one of the clocks in the pair must also

be inverted to generate a differential pair.

Z_O= 50 

R₁

Multi

Synth

0

PLLA

PLLB

0 

511 

240 

R₂

OSC

HCSL

CLKIN

Z_O= 50 

R₁

Multi

Synth

1

511 

240 

R₂

Multi

Synth

N

Note: The complementary -180 degree

out of phase output clock is generated

using the INV function

Figure 3. Si5350A Output is HCSL Compatible

Rev. 1.1

9

Si5350A-B

3. Functional Description

The Si5350A’s synthesis architecture consists of two high-frequency PLLs in addition to one high-resolution

fractional MultiSynth^TMdivider per output. A block diagram of both the 3-output and 8-output versions are shown in

Figure 4. This unique architecture allows the Si5350A to simultaneously generate up to eight independent, non-

integer-related frequencies. In addition, each MultiSynth^TMis configurable with two different frequencies (F1_x,

F2_x). This allows a pin controlled glitchless frequency change at each output (CLK0 to CLK5).

VDDO

VDD

10-MSOP

MultiSynth 0

F1_0

XA

XB

PLL

A

R0

R1

R2

CLK0

CLK1

CLK2

OSC

F2_0

FS

MultiSynth 1

F1_1

PLL

B

F2_1

MultiSynth 2

F1_2

P0

P1

Control

Logic

F2_2

MultiSynth 3

GND

VDD

20-QFN

MultiSynth 0

F1_0

F2_0

VDDOA

CLK0

R0

R1

R2

R3

R4

R5

FS

XA

XB

PLL

A

OSC

MultiSynth 1

F1_1

CLK1

PLL

B

F2_1

MultiSynth 2

F1_2

VDDOB

CLK2

F2_2

MultiSynth 3

F1_3

CLK3

F2_3

MultiSynth 4

F1_4

VDDOC

CLK4

F2_4

MultiSynth 5

F1_5

CLK5

P0

P1

P2

P3

P4

F2_5

Control

Logic

VDDOD

CLK6

MultiSynth 6

F1_6

R6

R7

MultiSynth 7

CLK7

F1_7

GND

Figure 4. Block Diagrams of 3-Output and 8-Output Si5350A Devices

10

Rev. 1.1

Si5350A-B

4. Configuring the Si5350A

The Si5350A is a factory-programmed custom clock generator that is user definable with a simple to use web-

based utility (www.silabs.com/ClockBuilder). The ClockBuilder utility provides a simple graphical interface that

allows the user to enter input and output frequencies along with other custom features as described in the following

sections. All synthesis calculations are automatically performed by ClockBuilder to ensure an optimum

configuration. A unique part number is assigned to each custom configuration.

4.1. Crystal Inputs (XA, XB)

The Si5350A uses a fixed-frequency standard AT-cut crystal as a reference to synthesize its output clocks.

4.1.1. Crystal Frequency

The Si5350A can operate using either a 27 MHz or a 25 MHz crystal.

4.1.2. Internal XTAL Load Capacitors

Internal load capacitors are provided to eliminate the need for external components when connecting a XTAL to the

Si5350A. The total internal XTAL load capacitance (C ) can be selected to be 0, 6, 8, or 10 pF. XTALs with

L

alternate load capacitance requirements are supported using additional external load capacitance  2 pF (e.g., by

using  4 pF capacitors on XA and XB) as shown in Figure 5.

XA

XB

Optional internal

load capacitance

0, 6, 8,10 pF

Optional additional

external load

capacitance

(< 2 pF)

Figure 5. External XTAL with Optional Load Capacitors

4.2. Output Clocks (CLK0–CLK7)

The Si5350A is orderable as a 3-output (10-MSOP) or 8-output (20-QFN) clock generator. Output clocks CLK0 to

CLK5 can be ordered with two clock frequencies (F1_x, F2_x) which are selectable with the optional frequency

select pins (FS0/1). See “4.3.3. Frequency Select (FS_0, FS_1)” for more details on the operation of the frequency

select pins.

4.2.1. Output Clock Frequency

Outputs can be configured at any frequency from 2.5 kHz up to 200 MHz. However, only two unique frequencies

above 112.5 MHz can be simultaneously output. For example, 125 MHz (CLK0), 130 MHz (CLK1), and 150 MHz

(CLKx) is not allowed. Note that multiple copies of frequencies above 112.5 MHz can be provided, for example,

125 MHz could be provided on four outputs (CLKS0-3) simultaneously with 130 MHz on four different outputs

(CLKS4-7).

4.2.2. .Spread Spectrum

Spread spectrum can be enabled on any of the clock outputs that use PLLA as its reference. Spread spectrum is

useful for reducing electromagnetic interference (EMI). Enabling spread spectrum on an output clock modulates its

frequency, which effectively reduces the overall amplitude of its radiated energy. Note that spread spectrum is not

available on clocks synchronized to PLLB.

The Si5350A supports several levels of spread spectrum allowing the designer to choose an ideal compromise

between system performance and EMI compliance.

An optional spread spectrum enable pin (SSEN) is configurable to enable or disable the spread spectrum feature.

Rev. 1.1

11

Si5350A-B

See “4.3.1. Spread Spectrum Enable (SSEN)” for details.

Reduced

Center

Amplitude

Frequency

and EMI

Amplitude

f_c

No Spread

Spectrum

Down Spread

Figure 6. Available Spread Spectrum Profiles

4.2.3. Invert/Non-Invert

By default, each of the output clocks are generated in phase (non-inverted) with respect to each other. An option to

invert any of the clock outputs is also available.

4.2.4. Output State When Disabled

There are up to three output enable pins configurable on the Si5350A as described in “4.3.4. Output Enable

(OEB_0, OEB_1, OEB_2)” . The output state when disabled for each of the outputs is configurable as output high,

output low, or high-impedance.

4.2.5. Powering Down Unused Outputs

Unused clock outputs can be completely powered down to conserve power.

4.3. Programmable Control Pins (P0–P4) Options

Up to five programmable control pins (P0-P4) are configurable allowing direct pin control of the following features:

4.3.1. Spread Spectrum Enable (SSEN)

An optional control pin allows disabling the spread spectrum feature for all outputs that were configured with

spread spectrum enabled. Hold SSEN low to disable spread spectrum. The SSEN pin provides a convenient

method of evaluating the effect of using spread spectrum clocks during EMI compliance testing.

4.3.2. Power Down (PDN)

An optional power down control pin allows a full shutdown of the Si5350A to minimize power consumption when its

output clocks are not being used. The Si5350A is in normal operation when the PDN pin is held low and is in power

down mode when held high. Power consumption when the device is in power down mode is indicated in Table 3 on

page 4.

4.3.3. Frequency Select (FS_0, FS_1)

The Si5350A offers the option of configuring up to two frequencies per clock output on CLK0-CLK5. This is a useful

feature for applications that need to support more than one clock rate on the same output. An example of this is

shown in Figure 7 where the FS pins selects which frequency is generated from the clock output: F1_0 is

generated when FS is set low, and F2_0 is generated when FS is set high.

27 MHz

74.25

MHz

FS0

Bit Level

or

Output Frequency Selected

XA

XB

74.25

1.001

0

F1_0:

F2_0:

74.25 MHz

74.25

MHz

1.001

Video

Processor

CLK0

1

FS0

Si5350A

Figure 7. Example of Generating Two Clock Frequencies from the Same Clock Output

12

Rev. 1.1

Si5350A-B

Up to two frequency select pins are available on the Si5350A. Each of the frequency select pins can be linked to

any of the clock outputs as shown in Figure 8. For example, FS_0 can be linked to control clock frequency

selection on CLK0, CLK3, and CLK5; FS_1 can be used to control clock frequency selection on CLK1, CLK2, and

CLK4. Any other combination is also possible. The frequency select feature is not available for CLKs 6 and 7.

The Si5350A uses control circuitry to ensure that frequency changes are glitchless. This ensures that the clock

always completes its last cycle before starting a new clock cycle of a different frequency.

Customizable FS Control

Glitchless Frequency Changes

FS

MultiSynth 0

CLK0

CLK1

FS

New frequency starts

at its leading edge

MultiSynth 1

FS_0

FS_1

FS_0

Output Frequency

F1_0, F1_3, F1_5

F2_0, F2_3, F2_5

0

1

FS

MultiSynth 2

CLK2

CLK3

Frequency_A

Frequency_B

FS

Frequency_A

MultiSynth 3

CLKx

FS

MultiSynth 4

CLK4

CLK5

CLK6

CLK7

FS_1

Output Frequency

F1_1, F1_2, F1_4

F2_1, F2_2, F2_4

0

1

MultiSynth 5

FS

Full cycle completes before

changing to a new frequency

Cannot be controlled

by FS pins

Figure 8. Example Configuration of a Pin-Controlled Frequency Select (FS)

4.3.4. Output Enable (OEB_0, OEB_1, OEB_2)

Up to three output enable pins (OEB_0/1/2) are available on the Si5350A. Similar to the FS pins, each OEB pin can

be linked to any of the output clocks. In the example shown in Figure 9, OEB_0 is linked to control CLK0, CLK3,

and CLK5; OEB_1 is linked to control CLK6 and CLK7, and OEB_2 is linked to control CLK1, CLK2, CLK4, and

CLK5. Any other combination is also possible. If more than one OEB pin is linked to the same CLK output, the pin

forcing a disable state will be dominant. Clock outputs are enabled when the OEB pin is held low.

The output enable control circuitry ensures glitchless operation by starting the output clock cycle on the first leading

edge after OEB is asserted (OEB = low). When OEB is released (OEB = high), the clock is allowed to complete its

full clock cycle before going into a disabled state. This is shown in Figure 9. When disabled, the output state is

configurable as disabled high, disabled low, or disabled in high-impedance.

Customizable OEB Control

Glitchless Output Enable

CLK0

OEB

OEB_0

Output State

CLK Enabled

CLK Disabled

OEB_0

OEB_1

CLK1

0

1

OEB

Clock continues until

cycle is complete

Clock starts on the

first leading edge

CLK2

CLK3

OEB

OEB_1

Output State

CLK Enabled

CLK Disabled

CLKx

OEBx

0

1

CLK4

CLK5

CLK6

CLK7

OEB

OEB_2

Output State

CLK Enabled

CLK Disabled

OEB_2

OEB

0

1

Figure 9. Example Configuration of a Pin-Controlled Output Enable

Rev. 1.1

13

Si5350A-B

4.4. Design Considerations

The Si5350A is a self-contained clock generator that requires very few external components. The following general

guidelines are recommended to ensure optimum performance.

4.4.1. Power Supply Decoupling/Filtering

The Si5350A has built-in power supply filtering circuitry to help keep the number of external components to a

minimum. All that is recommended is one 0.1 to 1.0 µF decoupling capacitor per power supply pin. This capacitor

should be mounted as close to the VDD and VDDO pins as possible without using vias.

4.4.2. Power Supply Sequencing

The VDD and VDDOx (i.e., VDDO0, VDDO1, VDDO2, VDDO3) power supply pins have been separated to allow

flexibility in output signal levels. Power supply sequencing for VDD and VDDOx requires that all VDDOx be

powered up either before or at the same time as VDD. Unused VDDOx pins should be tied to VDD.

4.4.3. External Crystal

The external crystal should be mounted as close to the pins as possible using short PCB traces. The XA and XB

traces should be kept away from other high-speed signal traces. See “AN551: Crystal Selection Guide” for more

details.

4.4.4. External Crystal Load Capacitors

The Si5350A provides the option of using internal and external crystal load capacitors. If external load capacitors

are used, they should be placed as close to the XA/XB pads as possible. See “AN551: Crystal Selection Guide” for

more details.

4.4.5. Unused Pins

Unused control pins (P0–P4) should be tied to GND.

Unused output pins (CLK0–CLK7) should be left floating.

4.4.6. Trace Characteristics

The Si5350A features various output drive strength settings. It is recommended to configure the trace

characteristics as shown in Figure 10 when the default high output drive setting is used.

Z_O= 50 ohms

R = 0 ohms

CLK

(Optional resistor for

EMI management)

Figure 10. Recommended Trace Characteristics with Default Drive Strength Setting

14

Rev. 1.1

Si5350A-B

5. Pin Descriptions

5.1. 20-pin QFN

XA

XB

P0

P1

P2

1

2

3

4

5

15 CLK7

14 VDDOD

13 CLK0

12 CLK1

11 VDDOA

GND

PAD

Figure 11. Si5350A 20-Pin QFN Top View

Pin Name Pin Number

Pin Type*

Function

XA

XB

1

I

Input pin for external XTAL

Output clock 0

2

I

CLK0

CLK1

CLK2

CLK3

CLK4

CLK5

CLK6

CLK7

P0

13

O

I

12

Output clock 1

9

Output clock 2

8

Output clock 3

19

Output clock 4

17

Output clock 5

16

Output clock 6

15

Output clock 7

3

User configurable input pin 0. See 4.4.5.

User configurable input pin 1. See 4.4.5.

User configurable input pin 2. See 4.4.5.

User configurable input pin 3. See 4.4.5.

User configurable input pin 4. See 4.4.5.

Core voltage supply pin. See 4.4.2

P1

4

I

P2

5

I

P3

6

I

P4

7

I

VDD

VDDOA

VDDOB

VDDOC

VDDOD

GND

20

P

11

Output voltage supply pin for CLK0 and CLK1. See 4.4.2

Output voltage supply pin for CLK2 and CLK3. See 4.4.2

Output voltage supply pin for CLK4 and CLK5. See 4.4.2

Output voltage supply pin for CLK6 and CLK7. See 4.4.2

Ground

10

18

14

Center Pad

*Note: I = Input, O = Output, P = Power

Rev. 1.1

15

Si5350A-B

5.2. 10-pin MSOP

VDD

XA

CLK0

CLK1

GND

1

2

3

10

9

XB

8

P0

P1

VDDO

CLK2

4

5

7

6

Figure 12. Si5350A 10-pin MSOP Top View

Pin Name

Pin Type*

Function

Number

XA

XB

2

3

I

Input pin for external XTAL

Output clock 0

CLK0

CLK1

CLK2

P0

10

9

O

I

Output clock 1

6

Output clock 2

4

User configurable input pin 0

User configurable input pin 1

P1

5

I

VDD

VDDO

GND

1

P

Core voltage supply pin. See 4.4.2

7

Output clock voltage supply pin for CLK0, CLK1, and CLK2. See 4.4.2

Ground

8

*Note: I = Input, O = Output, P = Power

16

Rev. 1.1

Si5350A-B

6. Ordering Information

Factory programmed Si5350A devices can be requested using the ClockBuilder web-based utility available at:

www.silabs.com/ClockBuilder. A unique part number is assigned to each custom configuration as indicated in

Figure 13. Use ClockBuilder to create custom part numbers or consult a Silicon Labs sales representative for other

custom NVM configurations.

Si5350A

BXXXXX

XXX

Blank = Coil Tape

R = Tape and Reel

GT =10-MSOP

GM=20-QFN

B

= Product Revision B

XXXXX = Unique Custom Cod.e A five character code will be

assigned for each unique custom configuration

Evaluation Boards

Si535x-TMSTK

For evaluation of

Si5350A-Bxxxxx-GT (10 MSOP)

For evaluation of

Si5350A-Bxxxxx-GM (20 QFN)

Si535x-B20QFN-EVB

Figure 13. Custom Clock Part Numbers

Rev. 1.1

17

Si5350A-B

7. 20-Pin QFN Package Outline

Figure 14 illustrates the package details for the Si5350A-B in a 20-pin QFN package. Table 11 lists the values for

the dimensions shown in the illustration.

C

D2

A

D

B

D2/2

A1

L

E

E2

E2/2

b

A

e

Figure 14. 20-pin QFN Package Drawing

18

Rev. 1.1

Si5350A-B

Table 11. Package Dimensions

Dimension

Min

0.80

0.00

0.20

Nom

0.85

Max

A

A1

b

0.90

0.05

0.30

—

0.25

D

4.00 BSC

2.70

D2

e

2.65

2.75

0.50 BSC

4.00 BSC

2.70

E

E2

L

2.65

0.35

—

2.75

0.45

0.10

0.40

aaa

—

bbb

ccc

ddd

—

0.10

0.08

0.10

Notes:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to JEDEC Outline MO-220, variation VGGD-5.

4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for

Small Body Components.

Rev. 1.1

19

Si5350A-B

8. Land Pattern: 20-Pin QFN

Figure 15 shows the recommended land pattern details for the Si5350 in a 20-Pin QFN package. Table 12 lists the

values for the dimensions shown in the illustration.

Figure 15. 20-Pin QFN Land Pattern

20

Rev. 1.1

Si5350A-B

Table 12. PCB Land Pattern Dimensions

Symbol

C1

Millimeters

4.0

C2

4.0

E

0.50 BSC

0.30

X1

X2

2.70

Y1

0.80

Y2

2.70

Notes:

General

1. All dimensions shown are in millimeters

(mm) unless otherwise noted.

2. This land pattern design is based on IPC-

7351 guidelines.

Solder Mask Design

3. All metal pads are to be non-solder mask

defined (NSMD). Clearance between the

solder mask and the metal pad is to be

60 µm minimum, all the way around the pad.

Stencil Design

4. A stainless steel, laser-cut and electro-

polished stencil with trapezoidal walls should

be used to assure good solder paste release.

5. The stencil thickness should be 0.125 mm

(5 mils).

6. The ratio of stencil aperture to land pad size

should be 1:1 for all perimeter pads.

7. A 2x2 array of 1.10 x 1.10 mm openings on

1.30 mm pitch should be used for the center

ground pad.

Card Assembly

8. A No-Clean, Type-3 solder paste is

recommended.

9. The recommended card reflow profile is per

the JEDEC/IPC J-STD-020 specification for

Small Body components.

Rev. 1.1

21

Si5350A-B

9. 10-pin MSOP Package Outline

Figure 16 illustrates the package details for the Si5350A-B in a 10-pin MSOP package. Table 13 lists the values for

the dimensions shown in the illustration.

Figure 16. 10-pin MSOP Package Drawing

22

Rev. 1.1

Si5350A-B

Table 13. 10-MSOP Package Dimensions

Dimension

Min

—

Nom

Max

1.10

0.15

0.95

0.33

0.23

A

A1

A2

b

—

0.00

0.75

0.17

0.08

0.85

—

c

—

D

3.00 BSC

4.90 BSC

3.00 BSC

0.50 BSC

0.60

E

E1

e

L

0.40

0.80

L2

q

0.25 BSC

—

0

8

aaa

bbb

ccc

ddd

—

0.20

0.25

0.10

0.08

—

Notes:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to the JEDEC Solid State Outline MO-137, Variation C

4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body

Components.

Rev. 1.1

23

Si5350A-B

10. Land Pattern: 10-Pin MSOP

Figure 17 shows the recommended land pattern details for the Si5350A-B in a 10-Pin MSOP package. Table 14

lists the values for the dimensions shown in the illustration.

Figure 17. 10-Pin MSOP Land Pattern

24

Rev. 1.1

Si5350A-B

Table 14. PCB Land Pattern Dimensions

Symbol

Millimeters

Min

Max

C1

E

4.40 REF

0.50 BSC

G1

X1

Y1

Z1

3.00

—

0.30

1.40 REF

—

5.80

Notes:

General

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ASME Y14.5M-1994.

3. This Land Pattern Design is based on the IPC-7351 guidelines.

4. All dimensions shown are at Maximum Material Condition (MMC). Least

Material Condition (LMC) is calculated based on a Fabrication

Allowance of 0.05mm.

Solder Mask Design

5. All metal pads are to be non-solder mask defined (NSMD). Clearance

between the solder mask and the metal pad is to be 60 µm minimum, all

the way around the pad.

Stencil Design

6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal

walls should be used to assure good solder paste release.

7. The stencil thickness should be 0.125 mm (5 mils).

8. The ratio of stencil aperture to land pad size should be 1:1.

Card Assembly

9. A No-Clean, Type-3 solder paste is recommended.

10. The recommended card reflow profile is per the JEDEC/IPC J-STD-

020C specification for Small Body components.

Rev. 1.1

25

Si5350A-B

11. Top Marking

11.1. 20-Pin QFN Top Marking

Figure 18. 20-Pin QFN Top Marking

11.2. Top Marking Explanation

Mark Method:

Pin 1 Mark:

Laser

Filled Circle = 0.50 mm Diameter

(Bottom-Left Corner)

Font Size:

0.60 mm (24 mils)

Line 1 Mark Format

Line 2 Mark Format:

Device Part Number

TTTTTT = Mfg Code*

Si5350

Manufacturing Code from the Assembly Purchase

Order Form.

Line 3 Mark Format:

YY = Year

WW = Work Week

Assigned by the Assembly House. Corresponds to

the year and work week of the assembly date.

*Note: The code shown in the “TTTTTT” line does not correspond to the orderable part number or frequency plan. It is used

for package assembly quality tracking purposes only.

26

Rev. 1.1

Si5350A-B

11.3. 10-Pin MSOP Top Marking

Figure 19. 10-Pin MSOP Top Marking

11.4. Top Marking Explanation

Mark Method:

Pin 1 Mark:

Laser

Mold Dimple (Bottom-Left Corner)

0.60 mm (24 mils)

Device Part Number

TTTT = Mfg Code*

Font Size:

Line 1 Mark Format

Line 2 Mark Format:

Si5350

Line 2 from the “Markings” section of the Assembly

Purchase Order form.

Line 3 Mark Format:

YWW = Date Code

Assigned by the Assembly House.

Y = Last Digit of Current Year (Ex: 2013 = 3)

WW = Work Week of Assembly Date.

*Note: The code shown in the “TTTT” line does not correspond to the orderable part number or frequency plan. It is used for

package assembly quality tracking purposes only.

Rev. 1.1

27

Si5350A-B

DOCUMENT CHANGE LIST

Revision 0.75 to Revision 1.0

 Extended frequency range from 8 MHz-160 MHz to

2.5 kHz-200 MHz.

 Added 1.8 V VDD support.

 Updated block diagrams for clarity.

 Added complete Si5350/1 family table, Table 1.

 Added top mark information.

 Added land pattern drawings.

 Added PowerUp Time, PLL Bypass mode, Table 4.

 Clarified Down Spread step sizes in Table 4.

 Updated max jitter specs (typ unchanged) in Table 6.

 Clarified power supply sequencing requirement,

Section 4.4.2.

Revision 1.0 to Revision 1.1

 Updated "6. Ordering Information" on page 17.

Changed “Blank = Bulk” to “Blank = Coil Tape” in

Figure 13.

28

Rev. 1.1

ClockBuilder Pro

One-click access to Timing tools,

documentation, software, source

code libraries & more. Available for

Windows and iOS (CBGo only).

www.silabs.com/CBPro

Timing Portfolio

www.silabs.com/timing

SW/HW

www.silabs.com/CBPro

Quality

www.silabs.com/quality

Support and Community

community.silabs.com

Disclaimer

Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or

intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical"

parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes

without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included

information. Silicon Labs shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses granted

hereunder to design or fabricate any integrated circuits. The products are not designed or authorized to be used within any Life Support System without the specific written consent of

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destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.

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型号：	SI5350A-B09240-GM
厂家：	SILICON
描述：	Processor Specific Clock Generator, 外围集成电路
文件：	总29页 (文件大小：622K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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