SC63C0316 [SILAN]
AUDIO CONTROL SYSTEM WITH BUILTIN; 带有内置的音频控制系统
| 型号： | SC63C0316 |
| 厂家： | 
SILAN MICROELECTRONICS JOINT-STOCK |
| 描述： | AUDIO CONTROL SYSTEM WITH BUILTIN |
| 文件： | 总24页 (文件大小：281K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SC63C0316
AUDIO CONTROL SYSTEM WITH BUILT•IN 4•BIT MCU
DESCRIPTION
The SC63C0316 single•chip CMOS microcontroller is designed fo
very high performance. With an up•to•14•digit dLiCreDct drive
capability, 4•channel A/D converter, 8•bit timer/counter, PLL frequency
synthesizer. The SC63C0316 offers you an excellent design solutio
for
a wide variety of applications, especiathlloyse requiring DTS
support.
Up to 56 pins of the 80p•in QFP package can be dedicated to I/O
Eight vectored interrupts provide fast responseto internal and external
events. In addition, the SC63C0316's advanced CMOS technol
ensures low power consumption and a wide operating voltage range.
QFP•80•14×20•0.8
ORDERING INFORMATION
Device Package
FEATURES
Memory
SC63C0316 QFP•80•14 x 20•0.8
* 512•nibble RAM
* 16K•byte ROM
A/D Converter
I/O Pins
* 4•channels with 8•bit resolution
Bit Sequential Carrier Buffer
* Support 16•bit serial data transfer in
arbitrary format
* Input only: 4 pins
* Output only: 28 pins
* I/O: 24 pins
LCD Controller/Driver
PLL Frequency Synthesizer
* Level = 300 mVp•p (min)
* AMVCO range = 0.5 MHz to 30 MHz
* FMVCO range = 30 MHz to 150 MHz
16•Bit Intermediate Frequency (IF)
Counter
* Maximum 14•digit LCD direct drive capability
* 28 segment x 4 common signals
* Display modes: Static, 1/2 duty (1/2 bias)
1/3 duty (1/2 or 1/3 bias), 1/4 duty (1/3 bias)
8•Bit Basic Timer
* Programmable interval timer functions
* Watch•dog timer function
8•Bit Timer/Counter
* Level = 300 mVp•p (min)
* AMIF range = 100 kHz to 1 MHz
* FMIF range =5MHz to 15 MHz
Watch Timer
* Programmable 8•bit timer
* External event counter
* Time interval generation
0.5 s, 3.9 ms at 32.768 kHz
* Frequency outputs to BUZ pin
* Clock source generation for LCD
Interrupts
* Arbitrary clock frequency output
* External clock signal divider
* Serial I/O interface clock generator
8•Bit Serial I/O Interface
* 8•bit transmit/receive mode
* 8•bit receive mode
* Four internal vectored interrupts
* Four external vectored interrupts
* Two quasi•interrupts
* Data direction selectable (LSB•first or MSB•first)
* Internal or external clock source
Memory•Mapped I/O Structure
* Data memory bank 15
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
REV:1.0
2004.08.03
Http: www.silan.com.cn
Page 1 of 24
SC63C0316
Three Power•Down Modes
Operating Temperature
* Idle: Only CPU clock stops
* – 40 °C to 85 °C
* Stop1: Main system or subsystem clock stops
* Stop2: Main system and subsystem clock stop
* CE low: PLL and IFC stop
Operating Voltage Range
* 1.8 V to 5.5 V at 3MHz
* PLL/IFC operation: 2.5V to 3.5V or
4.0V to 5.5V
Oscillation Sources
* Crystal or ceramic oscillator for main system clock
* Crystal for subsystem clock
APPLICATIONS
* Main system clock frequency: 4.5 MHz (Typ)
* Subsystem clock frequency: 32.768 kHz (Typ)
* CPU clock divider circuit (by 4, 8, or 64)
Instruction Execution Times
* Auto audio system
* Other audio system
* 0.9, 1.8, 14.2 ms at 4.5 MHz
* 122 ms at 32.768 kHz (subsystem)
BLOCK DIAGRAM
ABSOLUTE MAXIMUM RATINGS (Tamb=25°C)
Characteristics
Supply Voltage
Symbol
Value
•0.3 • 6.5
•0.3 • V +0.3
Unit
V
V
DD
V
I1
V
DD
Input Voltage
V
I2
•0.3 • V +0.3
DD
Output Voltage
Output Current High
V
•0.3 • V +0.3
V
O
DD
•15
•30
I
mA
OH
(To be continued)
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
REV:1.0
2004.08.03
Http: www.silan.com.cn
Page 2 of 24
SC63C0316
(Continued)
Characteristics
Symbol
Value
Unit
+30˄Peak value˅
Output Current Low
mA
IOL
+100˄Peak value˅
Operating Temperature
Storage Temperature
T
•40 ~ 85
•65~150
°C
°C
amb
T
stg
DC CHARACTERISTICS (Tamb=•40°C to +85°C, VDD=3.5V to 6.0V)
Characteristics
Symbol
Test condition
Min.
Typ.
Max.
Unit
All
input nspi except
tho
V
0.7V
V
V
V
IH1
IH2
DD
DD
DD
DD
DD
DD
specified below for VIH2•VIH4
Port 0, 1, 6, 7, and
RESET
V
0.8V
0.7V
Ports 4, 5, 7 and 8 with pupll•
resistors assigned
Input High Voltage
•••
V
V
V
IH3
Ports 4, 5, 7 and 8 are open•
0.7V
9
DD
drain
Xin, Xout and Xtin
V
DD
•0.5
V
DD
IH4
All
input
pins
except
V
0.3V
IL1
DD
DD
specified below for CIL2•Vil3
Ports 0, 1, 6, 7, 9, 10
RESET
Input Low Voltage
•••
•••
V
V
V
V
0.2V
IL2
Xin, Xout and XTin
0.4
IL3
V
=4.5V to 6.0V, I=•1mA,
OH
DD
V
DD
V
DD
V
DD
V
DD
•1.0
•0.5
•2.0
•1.0
V
OH1
Ports 0, 2•10
=•100mA
I
OH
Output High Voltage
•••
•••
V
DD
=4.5V to 6.0V, I =•100mA,
OH
V
OH2
Ports 11•13 only
=•30mA
I
OH
V
=4.5V to 6.0V, I=1.6mA,
OL
DD
0.8
2
Ports 4,5,7 and 8only
=•1.6mA, Ports 0,2,3,6,9,10
I
OL
V
V
OL1
0.4
0.2
EO1, and Eo2 only
=400mA, Ports 0, 2, 3, 6,
Output Low Voltage
•••
V
I
OL
•••
•••
10, EO1 and EO2 only
=4.5V to 6.0V, I =100mA,
V
DD
OL
1
1
Port 11, 12 and 13 only
=50mA
OL2
I
OL
VI=V
,
all input pins exc
and those speci
below for ILIH2•ILIH3
DD
RESET
Input High Leakage Current
I
•••
3
mA
LIH1
(To be continued)
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
REV:1.0
2004.08.03
Http: www.silan.com.cn
Page 3 of 24
SC63C0316
(Continued)
Characteristics
Symbol
Test condition
V =V , Xin, Xout, Xtin only
Min.
Typ.
Max.
Unit
I
25
mA
LIH2
I
DD
Input High Leakage Current
Input Low Leakage Current
V =9V, Ports 4,5,7 and
8
I
I
20
mA
LIH3
open•drain
V =0V, all input pins except Xin
I
I
•3
•20
3
LIL1
LIL2
Xout, XTin and
RESET
•••
•••
mA
I
V =0V, Xin, Xout, and XTin only
I
V =V , all output pins excep
O
DD
I
I
LOH1
LOH2
Output
High
Low
ageLeak
L
for ports 4, 5, 7 and 8
•••
•••
•••
•••
mA
mA
Current
V =9V, Ports 4, 5, 7 and 8 are
O
20
3
open•drain
Output
I
V =0V
O
LOL
Current
V =0V; V =5V±10%, Port 03•,
I
DD
15
30
15
46
90
40
80
200
70
R
L1
6, 9, and 10 (except P1.3)
=3V±10%,
V
DD
V =V •2V,
V =5V±10%,
DD
O
DD
Pull•up Resistor
kW
R
L2
Ports 4, 5, 7 and 8 only
=3V±10%,
V
DD
10
100
200
2.5
60
V =0V; V =5V±10%,
I
DD
RESET
230
490
400
800
VDD
R
L3
V
••
=3V±10%,
DD
LCD Drive Voltage
V
LCD
V
LCD
Voltage
D
R
••
50
•••
•••
100
140
kW
LCD
Resistor
V
V
V
V
V
=5V±10%,
=3V±10%,
=5V±10%,
=3V±10%,
=5V±10%,(3),
3
10
3
6
DD
DD
DD
DD
DD
COM Output Impedance
SEG Output Impedance
R
COM
kW
kW
15
20
60
R
SEG
10
4.
I
crystal oscillator, C1=C2=22pF
CE high; PLL operates
12
25
DD1 (2)
Idle
mode;
=5VV±10%,
DD
•••
•••
mA
4.5MHz crystal oscillator, CP
clock =fxx/4, CE low; PLL stops.
1.4
1.8
I
DD2
Supply Current (1)
V
DD
=3V±10%,
CPU
0.23
25
1.0
120
30
=fxx/64
=3V±10%,
V
DD
32kzH
crysta
I
I
DD3 (4)
DD4 (5)
oscillator, CE low; PLL stops.
mA
Idle mode; V =3V±10%, 32kHz
DD
20
crystal oscillator.
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
REV:1.0
2004.08.03
Http: www.silan.com.cn
Page 4 of 24
SC63C0316
DC CHARACTERISTICS (concluded) (Tamb=•40°C to +85°C, VDD=2.7V to 6.0V)
Characteristics
Supply Current (cont)
NOTES:
Symbol
Test condition
Min.
Typ.
0.6
Max.
5
Unit
Stop 1 mode; XTin=0V
V
=5V±10%, CPU clock=fxx/4,
DD
I
I
mA
DD5
DD6
CE low; PLL stops
V
V
=3V±10%, CPU clock=fxx/64
=5V±10%, 4.5MHz crystal
0.2
3
DD
DD
•••
4.2
8
oscillator, CPU clock=fxx/4, CE
low; PLL stops
mA
V
DD
=3V±10%, CPU clock=fxx/64
0.7
1.2
2.0
Stop 2 mode; Xtin=0V,
V =5V±10%, CPU clock=fxx/4,
DD
I
0.12
mA
DD7 (2)
CE low; PLL stops
1. Currents in the following circuits are not included; on•chip pull•up resistors, output port drive currents, internal
LCD voltage dividing resistors and A/D converter.
2. IDD1 and IDD7 are guaranteed in Tamb = – 20 °C to + 85 °C
3. Data includes power consumption for subsystem clock oscillation.
4. For high•speed controller operation, the power control register (PCON) must be set to 0011B.
5. For low•speed controller operation, the power control register (PCON) must be set to 0000B.
6. When the system clock control register, SCMOD, is set to 1001B, main system clock oscillation stops and the
subsystem clock is used.
MAIN SYSTEM OSCILLATOR CHARACTERISTICS (Tamb=•40°C to +85°C, VDD=2.7V to 6.0V)
Oscillator
Characteristics
Test condition
Min
Typ
Max Units
Oscillation frequency (1)
••
0.4
••
5.0
MHz
Ceramic
Stabilization occurs when VDD is
equal to the mini mum oscillator
voltage range
Oscillator
Stabilization time (2)
••
••
4
ms
Oscillation frequency (1)
Stabilization (2)
••
0.4
4.5
6.0
MHz
ms
Crystal
VDD=4.5V~6.0V
VDD=2.7V~4.5V
••
••
••
••
10
30
Oscillator
XIN input frequency (1)
••
••
0.4
••
••
4.5
MHz
ns
External
Clock
XIN input high and low
level width
111
1250
NOTES:
1. Oscillation frequency and Xin input frequency data are for oscillator characteristics only.
2. Stabilization time is the interval required for oscillator stabilization after a power•on occurs, or when Stop mode
is terminated.
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
REV:1.0
2004.08.03
Http: www.silan.com.cn
Page 5 of 24
SC63C0316
SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS
Oscillator
Characteristics
Test condition
Min
32
••
Typ
32.768
1.0
Max
35
Units
Oscillation frequency(1)
••
kHz
Crystal
VDD=4.5V~5.5V
VDD=1.8V~4.5V
••
2
Oscillator
Stabilization time (2)
s
••
••
10
XTIN input frequency (1)
XTIN input high and low
level width (tXH, tXL)
32
••
100
kHz
ms
External
clock
••
5
••
15
Note:1. Oscillation frequency and XTIN input frequency data are for oscillator characteristics only.
2. Stabilization time is the interval required for oscillator stabilization after a power•on occurs.
PIN CONFIGURATIONS
80
79 78 77 76 75 74 73 72 71 70 69 68
67 66 65
P4.1/SO
P4.2/SI
1
2
3
4
5
6
7
8
9
FMIF
64
63
62
61
60
59
58
57
AMIF
VSS1
P4.3/CLO
P5.0/ADC0
VCOAM
VCOFM
P5.1/ADC1
P5.2/ADC2
P2.3
P2.2
P5.3/ADC3
P6.0/KS0
P2.1
P6.1/KS1
56 P2.0
SEG27/P13.3
SDAT/P6.2/KS2 10
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
SCLK/P6.3/KS3
VDD/VDD0
11
l2
SEG26/P13.2
SEG25/P13.1
SEG24/P13.0
SC63C0316
13
14
15
16
17
18
19
VSS/VSS0
XOUT
SEG23/P12.3
XIN
SEG22/P12.2
SEG21/P12.1
SEG20/P12.0
VPP/TEST
XTIN
XTOUT
SEG19/P11.3
SEG18/P11.2
RESET/RESET
BIAS
20
21
22
23
SEG17/P11.1
SEG16/P11.0
SEG15/P10.3
VLC0
VLC1
VLC2
SEG14/P10.2
SEG13/P10.1
COM0 24
3
25 26 27 28 29 30 31 32 33 34 35 36 37
38 39 40
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
REV:1.0
2004.08.03
Http: www.silan.com.cn
Page 6 of 24
SC63C0316
PIN DESCRIPTION
Pin No.
72
Symbol
Description
P0.0
P0.1
P0.2
P0.3
P1.0
P1.1
P1.2
P1.3
4•bit I/O port.
73
1•bit or 4•bit read, write, and test are possible.
Pull•up resistors can be configured by software.
74
75
76
4•bit input port.
77
1•bit or 4•bit read and test are possible.
Pull•up resistors can be configured by software.
78
79
4•bit I/O ports.
56•59
68•71
P2.0~ P2.3
P3.0~P3.3
1•bit, 4•bit or 8•bit read, write and test are possible.
Pull•up resistors can be configured by software.
Ports 2 and 3 can be paired to support 8•bit data transfer.
80
1
P4.0
P4.1
P4.2
P4.3
P5.0
P5.1
P5.2
P5.3
P6.0
P6.1
P6.2
P6.3
P7.0
P7.1
P7.2
P7.3
P8.0
P8.1
P8.2
P8.3
P9.0
P9.1
P9.2
P9.3
P10.0
P10.1
P10.2
P10.3
4•bit I/O ports.
1•bit, 4•bit or 8•bit read, write and test are possible.
Pull•up resistors can be configured by software.
2
3
4
5
Ports 4 and 5 can be paired to support 8•bit data transfer.
6
7
8
4•bit I/O port.
9
1•bit, 4•bit or 8•bit read, write and test are possible.
Pull•up resistors can be configured by software.
10
11
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
1•bit or 4•bit output port.
Alternatively used for LCD segment output.
1•bit or 4•bit output port.
Alternatively used for LCD segment output.
1•bit or 4•bit output port.
Alternatively used for LCD segment output.
1•bit or 4•bit output port.
Alternatively used for LCD segment output.
(To be continued)
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
REV:1.0
2004.08.03
Http: www.silan.com.cn
Page 7 of 24
SC63C0316
(Continued)
Pin No.
44
Symbol
P11.0
P11.1
P11.2
P11.3
P12.0
P12.1
P12.2
P12.3
P13.0
P13.1
P13.2
P13.3
COM0•COM3
BIAS
Description
1•bit or 4•bit output port.
45
46
Alternatively used for LCD segment output.
47
48
49
1•bit or 4•bit output port.
Alternatively used for LCD segment output.
50
51
52
53
1•bit or 4•bit output port.
Alternatively used for LCD segment output.
54
55
24•27
20
Common signal output for LCD display
LCD power control
21
VLC0
LCD power supply.
22
VLC1
Voltage dividing resistors are assignable by
software
23
VLC2
12
VDD0
VSS0
Main power supply
13
Main Ground
19
RESET
XOUT
XIN
System reset pin
14
Crystal, or ceramic oscillator pin for main system clock. (For external clock
input, use XIN and input XIN’s reverse phase to XOUT)
15
18
XTOUT
XTIN
Crystal oscillator pin for subsystem clock. (For external clock input, use XTIN
and input XTIN’s reverse phase to XTOUT)
17
16
TEST
Test signal input (must be connected to VSS for normal operation)
Input pin for checking device power.
67
CE
Normal operation is high level and PLL/IFC operation is stopped at low level.
60
61
66
64
63
65
62
72
73
74
VCOFM
VCOAM
EO
External VCOFM/AM signal inputs.
PLL’s phase error output
FMIF
FM/AM intermediate frequency signal inputs.
AMIF
VDD1
VSS1
BTCO
TCLO0
TCL0
PLL/IFC power supply
PLL/IFC ground
Basic timer overflow output signal
Timer/counter 0 clock output signal
External clock input for timer/counter 0
2,4,8 or 16 kHz frequency output for buzzer sound for 4.19 MHz main system
clock or 32.768 kHz subsystem clock
75
BUZ
(To be continued)
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
REV:1.0
2004.08.03
Http: www.silan.com.cn
Page 8 of 24
SC63C0316
(Continued)
Pin No.
76
Symbol
INT0
Description
External interrupt. The triggering edges (rising/falling) are selectable. Only
INT0 is synchronized with system clock.
Quasi•interrupt with detection of rising edge signal.
External interrupt input with detection of rising or falling edges.
SIO interface clock signal
77
INT1
78
INT2
79
INT4
80
SCK
1
SI
SIO interface data input signal
2
SO
SIO interface data output signal
3
CLO
CPU clock output
8•11
4•7
28•55
KS0•KS3
ADC0•ADC3
SEG0•SEG27
Quasi•interrupt input with falling edge detection
ADC input ports.
LCD segment signal output.
FUNCTION DESCRIPTION
INTERRUPTS
The SC63C0316 has four external interrupts, four internal interrupts and two quasi•interrupts. Table 1 shows
the conditions for interrupt generation. The request flags that allow these interrupts to be generated are cleared
by hardware when the service routine is vectored. The quasi•interrupt's request flags must be cleared by
software.
Figure 1. Interrupt Control Circuit Diagram
IE0 IE4 IEB
IE2 IEW IEIF IECE IET0 IE1
IMOD1
IMOD0
INTB
IRQB
IRQ4
IRQ0
IRQ1
IRQS
IRQT0
INT4
#
@
INT0
INT1
@
INTS
INTT0
INTCE
INTIF
IRQCE
IRQIF
INTW
IRQW
IRQ2
INT2
KS0•KS3
SELECTOR
IMOD2
POWER•DOWN
MODE RELEASE
SIGNAL
IME IPR
IS1 IS0
INTERRUPT CONTROL UNIT
VECTOR INTERRUPT
GENERATOR
# = NOISE FILTERING CIRCUIT
@ = EDGE DETECTION CIRCUIT
Note : INT0 can release idle mode only when fxx/64 is selected as a asmpling clock
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
REV:1.0
2004.08.03
Http: www.silan.com.cn
Page 9 of 24
SC63C0316
TABLE1. Interrupt request flag conditions and priorities
Interrupt Internal/
Interrupt
Request flag
name
Condition for IRQx flag setting
source
INTB
External
priority
I
Reference time interval signal from basic timer
Both rising and falling edges detected at INT4
Rising or falling edge detected at INT0 pin
Rising or falling edge detected at INT1 pin
Completion signal for serial transmit•and•receive or
receive•only operation
1
1
2
3
IRQB
INT4
E
E
E
IRQ4
INT0
IRQ0
INT1
IRQ1
INTS
I
4
IRQS
INTT0
INTCE
INTIF
I
E
I
Signals for TCNT0 and TREF0 retgisters match
When falling edge is detected at CE pin
When gate closes
5
6
7
IRQT0
IRQCE
IRQIF
Rising edge detected at INT2 or else a falling edge is
detected at any of the KS0•KS3 pins
Time interval of 0.5s or 3.19ms
INT2*
E
••
••
IRQ2
INTW
I
IRQW
* The quasi•interrupt INT2 is only used for testing incoming signals.
INTERRUPT ENABLE FLAGS (IEx)
IEx flags, when set to "1", enable specific interrupt requests to be serviced. When the interrupt request flag is
set to "1", an interrupt will not be serviced until its corresponding IEx flag is also enabled. The IPR register
contains a global disable bit, IME, which disables all interrupt at once.
INTERRUPT PRIORITY
Each interrupt source can also be individually programmed to high levels by modifying the IPR register. When
IS1 = 0 and IS0 = 1, a low•priority interrupt can itself be interrupted by a high•priority interrupt, but not by another
low•priority interrupt.
If you clear the interrupt status flags (IS1 and IS0) to "0" in a interrupt service routine, a high•priority interrupt
can be interrupted by low•priority interrupt (multi•level interrupt). Before the IPR can be modified by 4•bit write
instructions, all interrupts must first be disabled by a DI instruction.
When all interrupts are low priority (the lower three bits of the IPR register are "0"), the interrupt requested first
will have high priority. Therefore, the first•requested interrupt cannot be superseded by any other interrupt.
If two or more interrupt requests are received simultaneously, the priority level is determined according to the
standard interrupt priorities, where the default priority is assigned by hardware when the lower three IPR bits =
"0".
In this case, the higher•priority interrupt request is serviced and the other interrupt is inhibited. Then, when the
high•priority interrupt is returned from its service routine by an IRET instruction, the inhibited service routine is
started.
Table 2. Interrupt Priority Register Settings
IPR.2
IPR.1
IPR.0
Result of IPR Bit Setting
Process all interrupt requests at default priority settings.
INTB and INT4 at highest priority.
INT0 at highest priority.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
INT1 at highest priority.
INTS at highest priority.
INTT0 at highest priority.
INTCE at highest priority.
INTIF at highest priority.
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
REV:1.0
2004.08.03
Http: www.silan.com.cn
Page 10 of 24
SC63C0316
Table 3. Default Priorities
Source
INTB, INT4
INT0
Default Priority
1
2
3
4
5
6
7
INT1
INTS
INTT0
INTCE
INTIF
The interrupt controller can service multiple interrupts in two ways: as two•level interrupts, where either all
interrupt requests or only those of highest priority are serviced (see Figure 2), or as multi•level interrupts, when
the interrupt service routine for a lower•priority request is accepted during the execution of a higher priority
routine. (See Figure 3)
Figure 2: Two•level Interrupt handling
Figure 3: Multi•level Interrupt handling
Normal program
Single
processing (status 0)
interrupt
2•level
INT disable
interrupt
3•level
interrupt
INT disable
Status 1
Status 0
Set IPR
Modify status
INT enable
INT enable
Low or
High level
Interrupt
Low or
High level
Interrupt
High level
Interrupt
Generated
Status 1
Status 2
Generated
Generated
Status 0
NOTE: If more than four interrupts are being processed at one time, you can avoid possible loss of working
register data by using the PUSH RR instruction to save register contents to the stack before the service
routines are executed in the same register bank. When the routines have executed successfully, you can
restore the register contents from the stack to working memory using the POP instruction.
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
REV:1.0
2004.08.03
Http: www.silan.com.cn
Page 11 of 24
SC63C0316
Interrupt execute flowchart
A vectored interrupt is generated when the following flags and register settings, corresponding to the specific
interrupt (INTn) are set to logic one:
— Interrupt enable flag (IEx)
— Interrupt master enable flag (IME)
— Interrupt request flag (IRQx)
— Interrupt status flags (IS0, IS1)
— Interrupt priority register (IPR)
If all conditions are satisfied for the execution of a requested service routine, the start address of the interrupt is
loaded into the program counter and the program starts executing the service routine from this address.
Figure 4 Interrupt execution flowchart
Interrupt is generated (INT xx)
Request flag (IRQx)
1
No
IEx=1?
Yes
Retain value until IEx=1
Generate corresponding vector
interrupt and release power•down mode
No
IME=1?
Retain value until IME=1
Yes
Yes
Retain vaule until interrupt
service routine is completed
IS1,0=0,0?
No
No
IS1,0=0,1?
Yes
No
High•priorityinterrupt
IS1, 0=0, 1
Yes
IS1, 0=1, 0
Store contents of PC and PSW in the stack area;
set PC contens to corresponding vector address
Yes
Are both interrupt sources of shared
vector address used?
IRQx flag vaule remains 1
No
Jump to interrupt start address
Reset corresponding IRQx flag
Jump to interrupt start address
Verify interrupt source and clear
IRQx with a BTSTZ instruction
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
REV:1.0
2004.08.03
Http: www.silan.com.cn
Page 12 of 24
SC63C0316
EXTERNAL INTERRUPTS
The external interrupt mode registers IMOD0 and IMOD1 are used to control the triggering edge of the input
signal at INT0 and INT1, respectively. The INT4 interrupt is an exception because its input signal generates an
interrupt request on both rising and falling edges.
When a sampling clock rate of fxx/64 is used for INT0, an interrupt request flag must be cleared before 16
machine cycles have elapsed. Since the INT0 pin has a clock•driven noise filtering circuit built into it, please take
the following precautions when you use it:
—
To trigger an interrupt, the input signal width at INT0 must be at least two times wider than the pulse width of
the clock selected by IMOD0. This is true even when the INT0 pin is used for general•purpose input.
— Because the INT0 input sampling clock does not operate during Stop or Idle mode, you cannot use INT0 to
release power•down mode.
EXTERNAL INTERRUPT MODE REGISTER
The external interrupt 2 (INT2) mode register, IMOD2, is used to select INT2 and KSn pins as interrupt input. If
a rising edge is detected at the INT2 pin, or when a falling edge is detected at any one of the pins (KS0–KS3),
the IRQ2 flag is set to "1" and a release signal for power•down mode is generated.
If one or more of the pins which are configured as key Interrupt (KS0–KS7) are in Low input or Low output
state, the key Interrupt can not be occured.
Figure 5.
INT2
Rising Edge Detection Circuit
P6.3/KS3
P6.2/KS2
P6.1/KS1
P6.0/KS0
Falling Edge
Detection
Circuit
Clock
Selector
IRQ2
IMOD2
Note: To generate a key interrupt on a falling edge at KS0•KS3, all
KS0•KS3 pins must be configured to input mode.
I/O PORTS
The SC63C0316 has 14 ports. There are total of 4 input pins, 28 output pins, 16 configurable I/O pins, and 8
nchannel open•drain I/O pins, for a maximum number of 56 I/O pins.
Pin addresses for all ports except ports 7•13 are mapped in bank 15 of the RAM. Ports 7•13 pin addresses are
in bank 1 of the RAM. The contents of I/O port pin latches can be read, written, or tested at the corresponding
address using bit manipulation instructions.
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
REV:1.0
2004.08.03
Http: www.silan.com.cn
Page 13 of 24
SC63C0316
PORT MODE FLAGS (PM FLAGS)
Port mode flags (PM) are used to configure I/O ports to input or output mode by setting or clearing the
corresponding I/O buffer. If a PM bit is "0", the corresponding I/O pin is set to input mode. If the PM bit is "1", the
pin is set to output mode. PM flags are addressable by 8•bit write instructions only.
PULL•UP RESISTOR MODE REGISTER (PUMOD)
The pull•up resistor mode register, PUMOD, is an 8•bit register used to assign internal pull•up resistors by
software to specific I/O ports. When a PUMOD bit is "1", a pull•up resistor is assigned to the corresponding I/O
port: When a configurable I/O port pin is used as an output pin, its assigned pull•up resistor is automatically
disabled, even though the pin's pull•up is enabled by a corresponding PUMOD bit setting.
PUMOD is addressable by 8•bit write instructions only. A system reset clears PUMOD values to logic zero,
automatically disconnecting all software•assignable port pull•up resistors.
Table 4. Pull•Up Resistor Mode Register (PUMOD) Organization
PUMOD ID
Address
FDCH
Bit3
PUR3
"0"
Bit2
Bit1
Bit0
PUR2
PUR6
PUR1
PUR5
PUR0
PUR4
PUMOD
FDDH
Table 5. Port Mode Group Flags (8•Bit W)
PM Group ID
Address
FE6H
FE7H
FE8H
FE9H
FEAH
FEBH
FECH
FEDH
Bit3/7
PM0.3
“0”
Bit2/6
PM0.2
“0”
Bit1/5
PM0.1
“0”
Bit0/4
PM0.0
“0”
PMG0
PM2.3
PM3.3
PM4.3
PM5.3
PM6.3
“0”
PM2.2
PM3.2
PM4.2
PM5.2
PM6.2
“0”
PM2.1
PM3.1
PM4.1
PM5.1
PM6.1
“0”
PM2.0
PM3.0
PM4.0
PM5.0
PM6.0
“0”
PMG1
PMG2
PMG3
N•CHANNEL OPEN•DRAIN MODE REGISTER(PNE)
The N•channel, open•drain mode register, PNE, is used to configure port 7 to 13 to N•channel open•drain
modes or push•pull modes.
When a bit in the PNE register is set to “1”, the corresponding output pin is configured to N•channel open•drain;
when set to “0”, the output pin is configured to push•pull mode.
The PNE register consists of an 8•bit register, as shown below, PNE can be addressed by 8•bit write
instructions only.
Table 6. N•channel open drain mode register (PNE) setting
ID
Address
FD6H
Bit 3/7
PNE10
“0”
Bit 2/6
PNE9
Bit1/5
PNE8
Bit0/4
PNE7
PNE
FD7H
PNE13
PNE12
PNE11
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
REV:1.0
2004.08.03
Http: www.silan.com.cn
Page 14 of 24
SC63C0316
A/D CONVERTER
To operate the A/D converter, one of the four analog input channels is selected by writing the appropriate value
to the ADC mode register.
To start the converter, the ADSTR flag in the control register AFLAG must be set to "1". Conversion speed is
determined by the oscillator frequency and the CPU clock. When the A/D operation is complete, the EOC flag
must be tested in order to verify that the conversion was successful. When the EOC value is "0", the converted
digital values stored in the data register ADATA can be read.
Figure 6. A/D Converter Circuit Diagram
DATA BUS
ADMOD
"0"
AFLAG
"0"
.2
.1
.0
ADSTR EOC
"0"
ADATA
8
AD3
AD2
AD1
AD0
VAin
VDA
Successive
Approximation
Logic
CMP
MULRIPLEXER
DAC
Resistor String
8
AVREF
AVSS
Digital•To•Analog Converter
Figure 7. A/D Converter Timing Diagram
tinit
tconv = 10 x 8/fx
One Machine Cycle
ADSTR
EOC
ADATA
Previous
Value
Valid
DATA
Value Remains Undetermined
ADC DIGITAL•TO•ANALOG CONVERTER (DAC)
The 8•bit digital•to•analog converter (DAC) generates analog voltage reference values for the comparator.
The DAC is a 256•step resistor string type digital•to•analog converter that uses successive approximation logic
to convert digital input into the reference analog voltage, VDA. The VDA values are input from the DAC to the
comparator where they are compared to the multiplexed external analog source voltage, VAin. Since the DAC
has 8•bit resolution, it generates the 256•step analog reference voltage.
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
REV:1.0
2004.08.03
Http: www.silan.com.cn
Page 15 of 24
SC63C0316
ADC DATA REGISTER (ADATA)
The A/D converter data register, ADATA, is an 8•bit register in which digital data values are stored as an A/D
conversion operation is completed. Digital values stored in ADATA are retained until another conversion
operation is initiated. ADATA is addressable by 8•bit read instructions only.
ADC MODE REGISTER (ADMOD)
The analog•to•digital converter mode register, ADMOD, is used to select one of four analog channels as the
analog data input source. Bit 3 in the ADMOD register is always "0".
Table 7. A/D Converter Mode Register Settings (1, 4•Bit R/W)
ADMOD.2 ADMOD.1 ADMOD.0
Effect of ADMOD Bit Setting
Select input channel AD0
1
0
0
0
0
0
1
1
0
1
0
1
Select input channel AD1
Select input channel AD2
Select input channel AD3
NOTE: If ADMOD.2–ADMOD.0 = 0, disable analog input channel selection.
PLL FREQUENCY SYNTHESIZER
The phase locked loop (PLL) frequency synthesizer locks medium frequency (MF), high frequency (HF), and
very high frequency (VHF) signals to a fixed frequency using a phase difference comparison system.
Figure 8. PLL Frequency Synthesizer Block Diagram
4
8
PLMOD
2 NF
PLLD(16•bit)
PLMOD.3,2
4
12
1
Input
Circuit
Swallow
Counter
Prescaler
VCOFM
VCOAM
PLMOD.3
Input
Circuit
Programmable
Counter
Selector
Phase
Comparator
Charge
Pump
EO
PLMOD.2
Reference Frequency
Generator
Unlock
Detector
PLLREF
4
ULFG
PLL FREQUENCY SYNTHESIZER FUNCTIONS
The PLL frequency synthesizer divides the signal frequency at the VCOAM or VCOFM pin using the
programmable divider. It then outputs the phase difference between the divided frequency and reference
frequency at the EO pins.
NOTE
The PLL frequency synthesizer operates only when the CE pin is high level; it enters the disable mode when
the CE pin is low.
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
REV:1.0
2004.08.03
Http: www.silan.com.cn
Page 16 of 24
SC63C0316
PHASE DETECTOR, CHARGE PUMP, AND UNLOCK DETECTOR
The phase comparator compares the phase difference between divided frequency (fN) output from the
programmable divider and the reference frequency (fr) output from the reference frequency generator.
The charge pump outputs the phase comparator's output from error output pins EO. The relation between the
error output pin output, divided frequency fN, and reference frequency fr is shown below:
fr > fN = Low level output
fr < fN = High level output
fr = fN = Floating level
When PLL operation is started by setting PLMOD register, PLL unlock flag (ULFG) in the PLL flag register
(PLLREG) has unlock state information between the reference frequency and divided frequency. The unlock
detector detects the unlock state of the PLL frequency synthesizer. The unlock flag in the PLLREG register is set
to "1" in unlock state. If ULFG = "0", the PLL lock state is selected.
PLLREG
ULFG
CEFG
IFCFG
0
ULFG is set continuously at a period of reference frequency f r by unlock detector. You must therefore read
ULFG flag in the PLLREG register at periods longer than 1/f r of the reference frequency. ULFG is reset when it
is read. PLLREG register can be read by 1•bit or 4•bit RAM control register instructions.
PLL operation is decided by CE (chip enable) pin state. The PLL frequency synthesizer is disabled and the
error output pin is set to floating state while the CE pin is low. When CE pin is high level, PLL is operating
normally.
The chip enable flag (CEFG) in the PLLREG register has information about CE pin state. When the CE pin
changes its low state to high, CEFG flag is set to logic one and CE reset operation occurs. When the CE pin
changes its high state to low, CEFG flag is set to logic zero and CE interrupt is generated.
INTERMEDIATE FREQUENCY COUNTER
The SC63C0316 uses an intermediate frequency counter (IFC) to count the frequency of the AM or FM signal
at FMIF or AMIF pin. The IFC block consists of a 1/2 divider, gate control circuit, IFC mode register (IFMOD) and
a 16•bit binary counter.
During gate time, the 16•bit IFC counts the input frequency at the FMIF or AMIF pins. The FMIF or AMIF pin
input signal for the 16•bit counter is selected by IFMOD register. The 16•bit binary counter (IFCNT1–IFCNT0) can
be read by 8•bit RAM control instructions only.
When the FMIF pin input signal is selected, the signal is divided by 2. When the AMIF pin input signal is
directly connected to the IFC, it is not divided.
By setting the IFMOD register, the gate is opened for 1•ms, 4•ms, or 8•ms periods. During the open period of
the gate, input frequency is counted by the 16•bit counter. When the gate is closed, the counting operation is
complete, and an interrupt is generated.
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
REV:1.0
2004.08.03
Http: www.silan.com.cn
Page 17 of 24
SC63C0316
Figure 9. IF Counter Block Diagram
1/2
Divider
FMIF
AMIF
Selector
If Counter
(16 Bit)
8
Gate
Control
Circuit
DATA BUS
1 ms
4 ms
8 ms
IFMOD
3
2
1
0
Gate Signal
Generator
DATA BUS
1KHz Internal Signal
Table 8. IF Counter Frequency Ranges
Pin
Voltage Level
300mVpp(min)
300mVpp(min)
Frequency Range
AMIF
FMIF
0.1MHz to 1MHz
5MHz to 15MHz
INPUT PIN CONFIGURATION
The AMIF and FMIF pins have built•in AC amplifiers (see Figure 32). The DC component of the input signal
must be stripped off by the external capacitor. When the AMIF or FMIF pin is selected for the IFC function and
the switch is turned on voltage of each pin increases to approximately 1/2 VDD after sufficiently long time. If the
pin voltage does not increase to approximately 1/2 VDD , the AC amplifier exceeds its operating range, possibly
causing an IFC malfunction. To prevent this from occurring, you should program a sufficiently long time delay
interval before starting the count operation.
Figure 10. AMIF and FMIF Pin Configuration
SW
External
Frequency
To internal
Counter
FMIF
AMIF
LCD CONTROLLER/DRIVER
The SC63C0316 microcontroller can directly drive 4 com x 28•segment LCD panel. Data written to the LCD
display RAM can be transferred to the segment signal pins automatically without program control.
When a subsystem clock is selected as the LCD clock source, the LCD display is enabled even during the
Stop1 and Idle power•down modes.
LCD RAM ADDRESS AREA
RAM addresses 1E4H–1FFH are used as LCD data memory. These locations can be addressed by 1•bit or 4•
bit instructions. When the bit value of a display segment is "1", the LCD display is turned on; when the bit value is
"0", the display is turned off.
Display RAM data are sent out through segment pins SEG0–SEG27 using a direct memory access (DMA)
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
REV:1.0
2004.08.03
Http: www.silan.com.cn
Page 18 of 24
SC63C0316
method that is synchronized with the fLCD signal.
RAM addresses in this location that are not used for LCD display can be allocated to general•purpose use.
Figure 11. LCD Display Data RAM Organization
SEG0
SEG1
1E4H BIT3 BIT2 BIT1 BIT0
1E5H
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
1F8H
1F9H
1FAH
1FBH
1FCH
1FDH
1FEH
1FFH
COM3 COM2 COM1 COM0
Figure 12. LCD Circuit Diaram
1FFH.3
1FFH.2
1FFH.1
1FFH.0
P
O
R
T
M
U
X
S
E
L
4
SEG27/P13.3
/
S
E
G
M
E
N
T
1F4H.3
1F4H.2
1F4H.1
1F4H.0
1F4H.3
1F4H.2
1F4H.1
1F4H.0
M
U
X
S
E
L
4
4
M
U
X
S
E
L
D
R
I
SEG1/P7.1
SEG0/P7.0
V
E
R
FFFH.3
FFFH.2
FFFH.1
FFFH.0
4
FF7H.3
FF7H.2
FF7H.1
FF7H.0
4
fLCD
COM3
COM2
COM1
TIMING
CONTROLLER
COM
CONTROL
8
LPOT
COM0
BIAS
VLC0
VLC1
LCD
VOLTAGE
CONTROL
LMOD
LCON
4
4
VLC2
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
REV:1.0
2004.08.03
Http: www.silan.com.cn
Page 19 of 24
SC63C0316
LCD CONTROL REGISTER (LCON)
The LCON register is used to turn the LCD display on and off and to control the flow of current to dividing
resistors in the LCD circuit. When LCON.0 is logic zero, the LCD display is turned off and the current to the
dividing resistors is cut off, regardless of the current LMOD.3 value.
Table 9. LCD Control Register (LCON) Organization (4•Bit W)
LCON Bit
LCON.3
LCON.2
Setting
Description
0
0
0
1
0
Always set to logic zero.
Always set to logic zero.
Port 6 input enable
LCON.1
Port 6 input disable
LCD output low, cut off current to dividing resistor
When LMOD.3=”0”: turn display off.
LCON.0
1
When LMOD.3=”1”: COM and SEG output in display mode.
Table 10 Relationship of LCON.0 and LMOD.3 Bit Settings
LCON.0 LMOD.3 COM0–COM3 SEG0–SEG31
P11.0–P13.3
LCD display off
,
cut off
0
x
0
1
Output low; LCD display off Output low; LCD display off
current to dividing resistors
LCD display off
LCD display off
LCD display off
1
COM output correspondsSEG output corresponds to
LCD display on
to display mode
display mode
NOTE:'x' means 'don't care.'
LCD MODE REGISTER (LMOD)
The LCD mode control register LMOD is used to control display mode; LCD clock, segment or port output, and
display on/off. The LCD clock signal, LCDCK, determines the frequency of COM signal scanning of each
segment output. This is also referred to as the 'frame frequency.
Because LCDCK is generated by dividing the watch timer clock (fw), the watch timer must be enabled when
the LCD display is turned on. The LCD display can continue to operate during Idle and Stop modes if a
subsystem clock is used as the watch timer source.
Table 11. LCD Clock Signal (LCDCK) Frame Frequency
LCDCK Frequency
fw/29 (64Hz)
Static
64
1/2 Duty
32
1/3 Duty
21
1/4 Duty
16
fw/28 (128Hz)
fw/27 (256Hz)
fw/26 (512Hz)
128
256
512
64
43
32
128
85
64
256
171
128
NOTES: 'fw' is the watch timer clock frequency of 32.768 kHz.
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
Http: www.silan.com.cn
REV:1.0
2004.08.03
Page 20 of 24
SC63C0316
Table12. Maximum Number of Display Digits Per Duty Cycle
LCD Duty
Static
1/2
LCD Bias
Static
1/2
COM Output Pins
COM0
Maximum Digit Display 8 Segment Pins)
4
COM0–COM1
COM0–COM2
COM0–COM2
COM0–COM3
8
1/3
1/2
12
12
16
1/3
1/3
1/4
1/3
Table 13. LCD Mode Control Register (LMOD) Organization (8•Bit W)
LMOD.7
LCD voltage dividing register control bit
Internal voltage dividing resistor.
0
1
External voltage dividing resistor; internal voltage dividing resistors are off.
LMOD.6
Always logic zero
LMOD.5
LMOD.4
LCD Clock (LCDCK) Frequency
0
0
1
1
0
1
0
1
fw/2 9 = 64 Hz
fw/28 = 128 Hz
fw/27 = 256 Hz
fw/26 = 512 Hz
LMOD.3
LMOD.2
LMOD.1
LMOD.0
Duty and Bias Selection for LCD Display
0
1
1
1
1
1
x
0
0
0
0
1
x
0
0
1
1
0
x
0
1
0
1
0
LCD display off
1/4 duty, 1/3 bias
1/3 duty, 1/3 bias
1/2 duty, 1/2 bias
1/3 duty, 1/2 bias
Static
NOTE:'x' means 'don't care'.
LCD DRIVE VOLTAGE
The LCD display is turned on only when the voltage difference between the common and segment signals is
greater than VLCD. The LCD display is turned off when the difference between the common and segment signal
voltages is less than VLCD.
NOTE: The LCD panel display may deteriorate if a DC voltage is applied that lies between the common and
segment signal voltage. Therefore, always drive the LCD panel with AC voltage
COMMON (COM) SIGNALS
The common signal output pin selection (COM pin selection) varies according to the selected duty cycle.
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
REV:1.0
2004.08.03
Http: www.silan.com.cn
Page 21 of 24
SC63C0316
Table 14. Common Signal Pins Used Per Duty Cycle
Display Mode
Static
COM0 Pin
Selected
Selected
Selected
Selected
COM1 Pin
N/C
COM2 Pin
N/C
COM3 Pin
N/C
1/2 duty
Selected
Selected
Selected
N/C
N/C
1/3 duty
Selected
Selected
N/C
1/4 duty
Selected
NOTE:’NC’means that no connection is required
Figure 13. LCD Common Signal Waveform (static)
COM0
VLC0
VLCD
VSS
Tf=T
T: LCDCK
Tf: Frame Frequency
Figure 14. LCD Common Signal Waveforms at 1/2 Bias (1/2, 1/3 Duty)
VLC0
COM0,1
(1/2 Duty)
VLC1,2
VSS
VLCD
Tf=2 x T
VLC0
VLC1,2
VSS
COM0,1
(1/3 Duty)
VLCD
T: LCDCK
Tf=Frame Frequency
Tf=3 x T
Figure 15. LCD Common Signal Waveforms at 1/3 Bias (1/3, 1/4 Duty)
VLC0
VLC1
VLCD
COM0•2
(1/3 Duty)
VLC2
VSS
Tf = 3 x T
VLC0
VLC1
VLC2
VSS
VLCD
COM0•3
(1/4 Duty)
Tf = 4 x T
T: LCDCK
Tf=Frame Frequency
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
REV:1.0
2004.08.03
Http: www.silan.com.cn
Page 22 of 24
SC63C0316
SEGMENT (SEG) SIGNALS
The 40 LCD segment signal pins are connected to corresponding display RAM locations at 1E0H–1FFH. Bits
0–3 of the display RAM are synchronized with the common signal output pins COM0, COM1, COM2, and COM3.
Figure 16. Select/No•Select Bias Signals in Static Display Mode
Select
No•Select
VLC0
COM
SEG
VSS
VLC0
VSS
T
T
T = LCDCK
SERIAL I/O INTERFACE
Using the serial I/O interface, you can exchange 8•bit data with an external device. The serial interface can run
off an internal or an external clock source, or the TOL0 signal that is generated by the 8•bit timer/counter 0, TC0.
If you use the TOL0 clock signal, you can modify its frequency to adjust the serial data transmission rate.
Figure 17. Serial I/O Interface Circuit Diagram
Internal Bus
8
LSB or MSB first
SO
Sbuf (8•Bit)
SI
R
Overflow
IRQS
Q
D
CK
P4.0/SCK
TOL0
Q0
Q1
Q2
3•Bit Counter
CPU Clock
Clock
Selecor
fxx/24
R
S
Q
Clear
SMOD.7 SMOD.6 SMOD.5
•
SMOD.3 SMOD.2 SMOD.1 SMOD.0
Bits*
8
Internal Bus
* Instruction Execution
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
REV:1.0
2004.08.03
Http: www.silan.com.cn
Page 23 of 24
SC63C0316
PACKAGE OUTLINE
QFP•80•14×20•0.8
UNIT: mm
HANDLING MOS DEVICES:
Electrostatic charges can exist in many things. All of our MOS devices are internally protected against
electrostatic discharge but they can be damaged if the following precautions are not taken:
· Persons at a work bench should be earthed via a wrist strap.
· Equipment cases should be earthed.
· All tools used during assembly, including soldering tools and solder baths, must be earthed.
· MOS devices should be packed for dispatch in antistatic/conductive containers.
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
REV:1.0
2004.08.03
Http: www.silan.com.cn
Page 24 of 24
相关型号：
©2020 ICPDF网 联系我们和版权申明