PE340G2DBIR [SILICOM]
Dual Port Fiber 40 Gigabit Ethernet PCI Express Content Director Bypass Server Adapter;
| 型号： | PE340G2DBIR |
| 厂家： | 
Silicom |
| 描述： | Dual Port Fiber 40 Gigabit Ethernet PCI Express Content Director Bypass Server Adapter PC |
| 文件： | 总12页 (文件大小：744K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PE340G2DBIR
Dual Port Fiber 40 Gigabit Ethernet PCI Express Content Director Bypass Server Adapter Intel®
FM10420 Based
Product Description
Silicom’s 40 Gigabit Ethernet PCI Express content aware director
Bypass server adapters is designed for servers and high-end
appliances.
The Silicom content aware director server adapter is designed with
an on board smart routing architecture that enables packets to be
redirected or dropped based on defined rules.
The Silicom’s 40 Gigabit Ethernet content aware packet director reduces host system process since only packets that are defined
to be targeted to the host systems are routed to the host; other packets can be routed to the other port or can be dropped by the
content aware hardware routing architecture.
The Silicom’s 40 Gigabit Ethernet content aware packet director is targeted to network applications that needs to process, monitor
or bypass packets based on defined rules. The adapter supports three main modes of operation: Content Aware Bypass, Content
Aware TAP and content Aware filtering NIC.
Content Aware Bypass
Silicom’s 40 Gigabit Ethernet content aware director provides intelligent
packet redirection capability where rules specify which packets are
directed to the host system and which packets are directed to the other
port (Bypass).
Content Aware TAP
Silicom’s 40 Gigabit Ethernet content aware director provides intelligent
packet redirection capability where all packets are directed to the other
port (Bypassed) and rules specify which packets are copied to the host
system ( TAP).
Content Aware Filtering NIC
Silicom’s 40 Gigabit Ethernet content aware provides intelligent packet redirection capability where rules specify which packets are
directed to the host or dropped.
The Silicom 40 Gigabit Ethernet PCI Express content director server adapter is based on Intel FM10420 Ethernet controller and a
L3 switch router. T
1Page
Silicom Ltd. Connectivity Solutions
he Silicom’s 40 Gigabit Ethernet PCI Express adapter is based on standard L2 driver and with the content director engine reduces
CPU host system processing.
The Silicom 40 Gigabit Ethernet PCI Express content aware server adapter offers simple integration into any PCI Express X16 to
40Gigabit Network.
Key Features
Content Aware Director:
Provides intelligent packet redirection capability where rules specify which packets are directed to the host system and which
packets are directed to the other port (Bypass)
Provides intelligent packet redirection capability where all packets are directed to the other port (Bypassed) and rules that
specify which packets are copied to the host system ( TAP)
Provides intelligent packet filtering / drop capability where rules specify which packets are directed to the host or dropped
Provides redirection rules that can be defined using source IP/ destination IP / Source Port / Destination Port / VLAN tuples
Redirection and packet filtering / drop are performed by the hardware itself in wire speed and do not require any software and
CPU host system power processing
Intelligent redirect mechanism is controllable via software
Intelligent routing mechanism is controllable via software
Support 2x40G / QSFP+ ports
40G QSFP+ Ports support 40GBase-SR4 and 40GBase-LR4
Bypass / Disconnect:
Bypass / Disconnect Ethernet ports on Power Fail, System Hangs or Software Application Hangs
Software programmable Bypass, Disconnect or Normal Mode
On Board Watch Dog Timer (WDT) Controller
Software programmable time out interval
Software Programmable WDT Enable / Disable counter
Software programmable Bypass Capability Enable / Disable
Software Programmable Disconnect Capability Enable / Disable
Software Programmable mode (Bypass, Normal or Disconnect mode) at Power up
Software Programmable mode (Bypass, Normal mode) at Power off
Independent Bypass operation in every two ports
Emulates standard NIC
Common Key features:
Host Interface:
2Page
Silicom Ltd. Connectivity Solutions
PCI Express X16 lane
Support PCI Express Base Specification Revision 3.0, 8GT/s, 5GT/s or 2.5GT/s
Intel FM10420 Features:
Single-element 4MB shared memory
L2/L3/L4/OpenFlow forwarding & ACLs
Stateless load balancing to CPUs
Datacenter Bridging (lossless Ethernet)
32K 40-bit TCAM entries
16K MAC & NextHop tables
Up to 300Gbps High-bandwidth CPU interface
2x 50Gbps 8-lane PCIe interfaces
Up to 2 40G (4 x 10G)
300ns network latency (100GbE)
1000nS host-network latency
LAN Features:
256 queues per PCIe x8 interface
SR-IOV (64 VFs per PCIe x8 interface)
IP/TCP/UDP checksum
Receive side scaling (RSS)
TCP segmentation offload (TSO/LSO)
LEDs indicator for link/Activity
Technical Specifications
Bypass Specifications:
3,276,800 mSec (3,276.8 Sec): Maximum
100 mSec ( 0.1 Sec) : Minimum
WDT Interval (Software
Programmable):
WDT Interval = (2^wdt_interval_parameter)*(0.1) sec.
wdt_interval_parameter: { Valid Range: 0-15}
– QS41: Fiber 40GBASE-SR4 Ethernet Technical Specifications:
IEEE Standard / Network
Fiber 40Gigabit Ethernet, 40GBASE-SR4
topology:
(840 to 860 nm LAN PHY).
3Page
Silicom Ltd. Connectivity Solutions
IEEE 802.3ba
Data Transfer Rate:
10.5 GBd per lane
Cables and Operating
distance:
50um, (OM3) 1500 MHz*Km, 0.5 to 100 m
50um, (OM4) 3500 MHz*Km, 0.5 to 150 m
Maximum: -1.0 dBm per lane
Minimum: -7.6 dBm per lane
Output Transmit Power:
Optical Receive Sensitivity:
Maximum Input Power:
Minimum: -5.4 dBm
Maximum: 2.4 dBm
– QS43: Fiber 40GBASE-SR4 Ethernet Technical Specifications:
Fiber 40Gigabit Ethernet, 40GBASE-SR4
IEEE Standard / Network
(840 to 860 nm LAN PHY).
topology:
IEEE 802.3ba
Data Transfer Rate:
10.5 GBd per lane
50um, (OM3) 1500 MHz*Km, 0.5 to 150 m
Cables and Operating
distance:
50um, (OM4) 3500 MHz*Km, 0.5 to 200 m
* Defined as half as the distance as specified in the optical transceiver
Maximum: 0.5 dBm per lane
Minimum: -7.5 dBm per lane
Output Transmit Power:
Optical Receive Sensitivity:
Maximum Input Power:
Minimum -7.5dBm
Maximum: 2.4 dBm
– QL4: Fiber 40GBASE-LR4 Ethernet Technical Specifications:
Fiber 40Gigabit Ethernet, 40GBASE-LR4
(1264.5nm – 1277.5nm ;
IEEE Standard / Network
topology:
1284.5nm – 1297.5nm ;
1304.5nm – 1317.5nm ;
1324.5nm – 1337.5nm LAN PHY).
IEEE 802.3ba
Data Transfer Rate:
10.3125 GBd per lane
4Page
Silicom Ltd. Connectivity Solutions
SMF-28, 10Km
Cables and Operating
distance:
* Defined as half as the distance as specified in the optical transceiver
Maximum: 2.3 dBm per lane
Minimum: -7.0dBm per lane
Output Transmit Power:
Optical Receive Sensitivity:
Maximum Input Power:
Maximum: -9.6 dBm
Maximum: 2.3 dBm
Operating Systems Support
Operating system support:
Linux
General Technical Specifications
Interface Standard:
PCI-Express Base Specification Revision 3.0(8 GTs)
Standard height long add-in card: 241.3mm X 111.15mm (9.5”X 4.376”)
X16 Lane
Board Size:
PCI Express Card Type:
+3.3V +-9%,
+12V +- 8%
PCI Express Voltage:
External Voltage from external
PW jack:
+12V ± 8%
PCI Connector:
Controller:
Holder:
Gold Finger: X16 Lane
Intel FM10420
Metal Bracket
Weight:
450gr (15.874oz)
20.16W: Typical Full 40GBase-SR4 Fraffic
19.44W: Typical 40GBase-SR4 Link (No Traffic)
23.28W: Typical Full 40GBase-LR4 Fraffic
22.92W: Typical 40GBase-LR4 Link (No Traffic)
19.08W: Typical Bypass Mode
Power Consumption:
5Page
Silicom Ltd. Connectivity Solutions
Operating Humidity:
Operating Temperature:
Storage:
0%–90%, non-condensing
0°C – 40°C (32°F – 104°F) Air flow requirement 200FLM
-40°C–65°C (-40°F–149°F)
FCC 47CFR Part 15:2013, Subpart B Class B
Conducted emissions
Radiated emissions
EN 55022: 2010, Class B
Conducted disturbance at mains terminals
Conducted disturbance at telecommunication port
Radiated disturbance
EN 61000-3-2: 2006+A1(09)+A2(09)
Harmonic current emissions
EMC Certifications:
EN 61000-3-3: 2008
Voltage fluctuations and flicker
EN 55024: 2010
Immunity to electrostatic discharge (ESD)
Radiated immunity to radio frequency electromagnetic field
Conducted immunity to electrical fast transients / bursts (EFT/ B)
Conducted immunity to voltage surges
Conducted immunity to disturbances induced by radio frequency field
Conducted immunity to voltage dips and short interruptions
53 (Years)
MTBF*:
LEDs
* The prediction was performed for 40°C Ambient temperature, GB Environmental condition.
The reliability prediction was performed in accordance with Telcordia SR-332.
(1) Link/Act 40Gbps LED per port :
Link : Turns on Green
Activity : Blinks Green
KINGBRIGHT, P/N KPBA-3010SYKCGKC, or compatible. d : 574 nm)
(1) Bi- color LED per segment (2 ports):
LEDs:
Normal : Off
Bypass : Turns on Green (KINGBRIGHT, P/N KPBA- 3010SYKCGKC, or compatible. d : 574
nm)
Disconnect : Turns on Yellow (KINGBRIGHT, P/N KPBA-3010SYKCGKC, or compatible. d :
590 nm)
LEDs are located on the PCB, visible via holes in the metal bracket.
LEDs location:
Each green Link/Act 40G LED (1 LED per port) is located below its own connector port.
6Page
Silicom Ltd. Connectivity Solutions
The yellow/green LED for disconnect and bypass is located between the 2 ports
(2) MTP/MTP (SR4)
(2) LC/LC (LR4)
Connectors:
Functional Description
Director – Content Aware Bypass
Silicom’s 40 Gigabit Ethernet content aware director Provides intelligent packet redirection capability where rules specify which
packets are directed to the host system and which packets are directed to the other port (Bypass).
Figure 1: Content Aware Bypass Functional Block Diagram
Figure 1 illustrates functional block diagram of content aware Bypass:
Figure 1 illustrates functional block diagram of content aware Bypass:
Packets received in port A and meet rule are directed to port B, other packets are directed to port C (Bypass).
Packets received in port C and meet rule are directed to port D, other packets are directed to port A (Bypass).
Director Content Awar TAP
Silicom’s 40 Gigabit Ethernet content aware director Provides intelligent packet redirection capability where all packets are directed
to the other port (Bypassed) and rules specify which packets are copied to the host system (TAP).
Figure 2: Content Aware TAP Functional Block Diagram
7Page
Silicom Ltd. Connectivity Solutions
Figure 2 illustrates functional block diagram of content aware TAP:
Packets received in port A and meet rule are directed to ports B and C (TAP), other packets are directed to port C (Bypass).
Packets received in port C and meet rule are directed to ports D and A (TAP), other packets are directed to port A (Bypass).
Director – Content Filtering NIC
Silicom’s 40 Gigabit Ethernet content aware provides intelligent packet redirection capability where rules specify which packets are
directed to the host or dropped.
Figure 3: Content Aware Filtering NIC Functional Block Diagram
Figure 3 illustrates functional block diagram of content aware TAP:
Packets received in port A and meet rule, direct to port B. Packets received in port A and do not meet rule are dropped.
Packets received in port C and meet rule, direct to port D. Packets received in port C and do not meet rule are Dropt.
Director: Rules Classification and capabilities
The Redirector supports the following capabilities:
Maximum total number of rules is 16K
Each of the 16K rules can be defined to any port the on board multi-layer switch
Each rule refers to incoming packet
Rules are executed per order. First rule that matches will be executed
Rules can be added and removed on the fly
Each rule can include one or more classification fields. A rule match will be when all fields defined are match
Each field can have a bit masking to check part of the classification field
Per port statistics can be read, like packets count, errors, VLAN, and more
Rules and action are done in wire speed at any packet size
Rules classification fields
Rules classification is done based on the first 128 bytes of the packets. The following list provides rules classification fields
MAC address, source & destination
8Page
Silicom Ltd. Connectivity Solutions
IPv4 – source & destination IP
IPv6 – source & destination IP
L4 Port – source & destination port
Ethernet Protocol – ethertype
IP Protocol num
VLAN ID tagging
User defined fields
DSCP – match the different services code point – the six most significant bits of the Type of Service octet (IPv4) or Traffic Class
octet (IPv6).*
IPv6 Flow Label*
IP length*
ISL Frame Type*
ISL USER*
Source & destination port range*
VLAN priority*
VLAN tag type*
TCP flags*
TOS – match Type of Service octet (IPv4) or Traffic Class octet (IPv6)*
TTL field in a IPv4 header or Hop Limit in a IPv6 header*
*Future SW supports
Execution per rule
The following Executions per rule are supported:
Drop – when a rule matches the packet will be dropped
Redirect – when a rule matches redirect the packet to the defined destination port
Mirror – when a rule matches copy packet also to a defined destination port
Director Advanced Features:
Port trunking between the Intel port to Intel port connected to it for load balancing between the different Intel ports
Port trunking between the different External Intel port to the external switch connected to it for load balancing between the
different external ports.
Session balancing with L3/L4 hashing or other mechanism
ISL (Inter Switch Link) Tagging per port can be added to the packets per configuration
ISL Tagging can be removed and can be forward to specific port per the ISL index.
Quality of Service support with the following features:
9Page
Silicom Ltd. Connectivity Solutions
Priority levels: 16 internal “switch” priorities, 8 or 16 VLAN priorities (optional use of CFI bit as an extra VLAN priority bit)
Arbitrary mapping of ingress VLAN priority to an internal VLAN priority
Arbitrary mapping of an internal VLAN priority to egress VLAN priority
Arbitrary mapping of internal VLAN priority to switch priority
Arbitrary mapping of DSCP to switch priority, configurable priority source selection.
Scheduler: 8 traffic classes, arbitrary mapping of switch priorities to traffic class, deficit weighted round-robin or strict priority.
Notification: Two congestion notifications can be supported;
Virtual output queue congestion notification (VCN) and Intel proprietary backward congestion notification (FCN).
Open Flow support (consistent with OpenFlow protocol standard)
sFlow support
User defined Packet transmission with two optional modes: 1. Simple mode – transmit on specific port. 2. Switched mode –
where switch determines destination port/ports, or with specific information such as whether or not egress processing rules
should be applied.
Storm Control Management – Switch can support a variety storm controller. Each storm controller can be programmable to
define rat, condition (like unicast ICMP frames whose TTL is at most 1), frame type (can be OR’ed), ingress & egress port ports.
Actions: do nothing, drops frames to port (according to filter)
*Future SW supports
Bypass / Disconnect
Silicom’s Bypass adapter supports the following mode states: Normal/inline, Bypass/Fail-To-Wire and Disconnect modes.
Normal/Inline mode
In Normal mode, the ports are independent interfaces (see Figure 6: Normal mode, one Bypass pair is illustrated).
Figure 4: Normal Mode Functional Block Diagram
Bypass/Fail-To-Wire mode
10Page
Silicom Ltd. Connectivity Solutions
In Bypass mode, the connections of the Ethernet network ports are disconnected from the interfaces and switched over to the other
port to create a crossed connection loop-back between the Ethernet ports. The connections of the interfaces are left unconnected.
(See Figure 7: one Bypass pair illustrated)
Figure 5: Bypass Mode Functional Block Diagram
Disconnect mode
In Disconnect mode, the transmit connections of the interfaces are disconnected from the ports. The switch / router connected to
the adapter does not detect link partner (See Figure 8):
Figure 6: Disconnect Mode Functional Block Diagram
Bypass/Disconnect Features:
Silicom’s Bypass server adapter supports software programmable to select Normal, Bypass or Disconnect modes. Silicom’s
Bypass adapters supports Disable Bypass, Disable Disconnected capabilities; hence, if those adapters receive Disable Bypass
capability / Disable Disconnect commands, the adapter does not Bypass / does not Disconnect its Ethernet ports, The Disable
Bypass Capabilities are reserved also after power off. This feature enables to emulate a standard NIC.
Key Features:
All modes of operation are fully software configured with a well-defined and easy to use API
11Page
Silicom Ltd. Connectivity Solutions
Disable bypass/Disconnect for a standard NIC emulation and operation, retained even with power cycle
Range of Watchdog timer timing, configurable for detecting appliance failure
Watchdog timer reset function by application or self-reset by the product bypass driver
Easy to read product status and product features capabilities
Fast switching between mode with less than 10mS of transit time
Compatible with all Silicom bypass products, one driver set and command set for all products
Order Information
P/N
Description
Notes
RoHS Compliant,
X16 Gen 3,
Dual port Fiber (SR4) 40 Gigabit Ethernet PCI
Express Content Director Bypass Server Adapter
PE340G2DBIR-QS41
based on Intel FM10420,
on board support for Fiber SR4 up to length
100m on OM3 MMF
RoHS Compliant,
X16 Gen 3,
Dual port Fiber (SR4) 40 Gigabit Ethernet PCI
Express Content Director Bypass Server Adapter
PE340G2DBIR-QS43
based on Intel FM10420,
on board support for Fiber SR4 300m on OM3
MMF
RoHS Compliant,
Dual port Fiber (LR4) 40 Gigabit Ethernet PCI
Express Content Director Bypass Server Adapter
X16 Gen 3,
PE340G2DBIR-QL4
based on Intel FM10420,
on board support for Fiber LR4
1V9
12Page
Silicom Ltd. Connectivity Solutions
相关型号：
PE340G2DBIR-QL4
Dual Port Fiber 40 Gigabit Ethernet PCI Express Content Director Bypass Server Adapter
SILICOM
PE340G2DBIR-QS41
Dual Port Fiber 40 Gigabit Ethernet PCI Express Content Director Bypass Server Adapter
SILICOM
PE340G2DBIR-QS43
Dual Port Fiber 40 Gigabit Ethernet PCI Express Content Director Bypass Server Adapter
SILICOM
©2020 ICPDF网 联系我们和版权申明