514FCA001000BAG [SILICON]
Oscillator;
| 型号： | 514FCA001000BAG |
| 厂家： | 
SILICON |
| 描述： | Oscillator |
| 文件： | 总38页 (文件大小：762K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si514
2
ANY-FREQUENCY I C PROGRAMMABLE XO (100 kHZ TO 250 MHZ)
Features
602
Programmable to any frequency
from 100 kHz to 250 MHz
0.026 ppb frequency tuning
resolution
Glitch suppression on OE, power
on and frequency transitions
Low jitter operation
2- to 4-week lead times
Total stability includes 10-year
aging
Comprehensive production test
coverage includes crystal ESR and
DLD
On-chip LDO for power supply
noise filtering
3.3, 2.5, or 1.8 V operation
Differential (LVPECL, LVDS,
HCSL) or CMOS output options
Optional integrated 1:2 CMOS
fanout buffer
5x7mm, 3.2x5mm
2.5x3.2mm
Industry standard 5x7, 3.2x5, and
2.5x3.2 mm packages
Ordering Information:
o
–40 to 85 C operation
See page 28.
Pin Assignments:
Applications
See page 27.
All-digital PLLs
Datacom
DAC+ VCXO replacement
SONET/SDH/OTN
3G-SDI/HD-SDI/SDI
Industrial automation
FPGA/ASIC clock generation
FPGA synchronization
VDD
1
2
3
6
5
4
SDA
SCL
GND
CLK–
CLK+
Description
2
The Si514 user-programmable I C XO utilizes Silicon Laboratories' advanced PLL
technology to provide any frequency from 100 kHz to 250 MHz with programming
resolution of 0.026 parts per billion. The Si514 uses a single integrated crystal and
Silicon Labs’ proprietary DSPLL synthesizer to generate any frequency across this
2
range using simple I C commands. Ultra-fine tuning resolution replaces DACs and
VCXOs with an all-digital PLL solution that improves performance where
synchronization is necessary or in free-running reference clock applications. This
solution provides superior supply noise rejection, simplifying low jitter clock
generation in noisy environments. Crystal ESR and DLD are individually
production-tested to guarantee performance and enhance reliability.
The Si514 is factory-configurable for a wide variety of user specifications, including
2
startup frequency, I C address, supply voltage, output format, and stability. Specific
configurations are factory-programmed at time of shipment, eliminating long lead
times and non-recurring engineering charges associated with custom frequency
oscillators.
Functional Block Diagram
Rev. 1.1 12/17
Copyright © 2017 by Silicon Laboratories
Si514
Si514
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. Solder Reflow and Rework Requirements for 2.5x3.2 mm Packages . . . . . . . . . . . . . .11
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.1. Programming a New Output Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.2. Programming a Small Frequency Change (sub ±1000 ppm) . . . . . . . . . . . . . . . . . .13
3.3. Programming a Large Frequency Change (> ±1000 ppm) . . . . . . . . . . . . . . . . . . . .14
4. All-Digital PLL Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
5. User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
5.1. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
5.2. Register Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
5.3. I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
6. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
6.1. Dual CMOS (1:2 Fanout Buffer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
7. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
8. Package Outline Diagram: 5 x 7 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
9. PCB Land Pattern: 5 x 7 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
10. Package Outline Diagram: 3.2 x 5.0 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
11. PCB Land Pattern: 3.2 x 5.0 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
12. Package Outline Diagram: 2.5 x 3.2 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
13. PCB Land Pattern: 2.5 x 3.2 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
14. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
14.1. Si514 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
14.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
2
Rev. 1.1
Si514
1. Electrical Specifications
Table 1. Operating Specifications
VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85 oC
Parameter
Supply Voltage
Symbol
Test Condition
3.3 V option
2.5 V option
1.8 V option
Min
2.97
2.25
1.71
—
Typ
3.3
2.5
1.8
21
Max
3.63
2.75
1.89
26
Units
V
V
DD
V
V
Supply Current
I
CMOS, 100 MHz,
single-ended
mA
DD
LVDS
(output enabled)
—
—
19
39
41
—
—
23
43
44
18
85
mA
mA
mA
mA
LVPECL
(output enabled)
HCSL
(output enabled)
—
Tristate
(output disabled)
—
o
Operating Temperature
T
–40
C
A
Table 2. Input Characteristics
VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85 oC
Parameter
Symbol Test Condition
Min
Typ
Max
—
Units
SDA, SCL Input Voltage High
SDA, SCL Input Voltage Low
V
0.80 x V
—
—
—
V
IH
DD
V
0.20 x V
V
IL
DD
Rev. 1.1
3
Si514
Table 3. Output Clock Frequency Characteristics
VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85 oC
Parameter
Programmable
Symbol
Test Condition
CMOS, Dual CMOS
LVDS/LVPECL/HCSL
Min
0.1
0.1
—
Typ
—
Max
212.5
250
Units
MHz
MHz
ppb
F
F
O
O
Frequency Range
—
Frequency
M
0.026
—
RES
Reprogramming
Resolution
Frequency Range for
Small Frequency Change
(Continuous Glitchless
Output)
From center frequency
–1000
—
+1000
ppm
Settling time for Small
Frequency Change
<±1000 ppm from
center frequency
—
—
—
—
100
10
µs
Settling time for Large
Frequency Change (Out-
put Squelched during Fre-
quency Transition)
>±1000 ppm from
center frequency
ms
Total Stability*
Frequency Stability Grade C
Frequency Stability Grade B
Frequency Stability Grade A
Frequency Stability Grade C
Frequency Stability Grade B
Frequency Stability Grade A
–30
–50
–100
–20
–25
–50
—
—
—
—
—
—
—
—
+30
+50
+100
+20
+25
+50
10
ppm
ppm
ppm
ppm
ppm
ppm
ms
Temperature Stability
Startup Time
Disable Time
T
Minimum V until output
DD
SU
frequency (F ) within specification
O
T
F < 10 MHz
—
—
—
—
—
—
—
—
40
5
µs
µs
µs
µs
D
O
F 10 MHz
O
Enable Time
T
F < 10 MHz
60
20
E
O
F 10 MHz
O
*Note: Total stability includes initial accuracy, operating temperature, supply voltage change, load change, shock and
vibration (not under operation), and 10 years aging at 40 oC.
4
Rev. 1.1
Si514
Table 4. Output Clock Levels and Symmetry
VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85 oC
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
CMOS Output Logic
High
V
0.85 x V
—
—
V
OH
DD
CMOS Output Logic
Low
V
—
—
0.15 x V
V
OL
DD
CMOS Output Logic
High Drive
I
3.3 V
2.5 V
–8
–6
–4
8
—
—
—
—
—
—
0.8
—
—
—
—
—
—
1.2
mA
mA
mA
mA
mA
mA
ns
OH
1.8 V
CMOS Output Logic
Low Drive
I
3.3 V
OL
2.5 V
6
1.8 V
4
CMOS Output
Rise/Fall Time
T /T
0.1 to 125 MHz,
—
R
F
C = 15 pF
L
(20 to 80% V
)
DD
0.1 to 212.5 MHz,
—
—
0.6
—
0.9
ns
ps
C = no load
L
LVPECL/HCSL Out-
put Rise/Fall Time
(20 to 80% V
T /T
565
R
F
F
)
DD
LVDS Output Rise/Fall T /T
Time (20 to 80% V
—
—
—
800
—
ps
V
R
)
DD
LVPECL Output Com-
mon Mode
V
V
50 to V – 2 V, single-ended
V
–
DD
OC
DD
1.4 V
LVPECL Output Swing
V
50 to V – 2 V, single-ended
0.55
1.13
0.83
0.25
0.8
0.90
1.33
1.00
0.45
V
V
O
DD
PPSE
LVDS Output Common
Mode
100 line-line, 3.3/2.5 V
100 line-line, 1.8 V
1.23
0.92
0.35
V
OC
V
LVDS Output Swing
V
Single-ended 100 differential
O
PPSE
termination
HCSL Output
V
50 to ground
0.35
0.38
0.42
V
OC
Common Mode
HCSL Output Swing
Duty Cycle
V
Single-ended
0.58
48
0.73
50
0.85
52
V
O
PPSE
DC
%
Rev. 1.1
5
Si514
Table 5. Output Clock Jitter and Phase Noise (LVPECL)
VDD = 2.5 or 3.3 V ±10%, TA = –40 to +85 oC; Output Format = LVPECL
Parameter
Symbol
Test Condition
Min
—
Typ
—
Max
1.3
11
Units
ps
1
Period Jitter (RMS) JPRMS
Period Jitter (Pk-Pk) JPPKPK
10 k samples
1
10 k samples
—
—
ps
Phase Jitter (RMS)
φJ
1.875 MHz to 20 MHz integration
—
0.31
0.5
ps
2
bandwidth (brickwall)
12 kHz to 20 MHz integration band-
—
0.8
1.0
ps
2
width
Phase Noise,
156.25 MHz
φN
100 Hz
1 kHz
—
—
—
—
—
—
—
—
—
—
–86
–109
–116
–123
–136
3.0
—
—
—
—
—
—
—
—
—
—
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
ps
10 kHz
100 kHz
1 MHz
Additive RMS
JPSR
SPR
10 kHz sinusoidal noise
100 kHz sinusoidal noise
500 kHz sinusoidal noise
1 MHz sinusoidal noise
Jitter Due to Power
3
3.5
ps
Supply Noise
3.5
ps
3.5
ps
Spurious
LVPECL output, 156.25 MHz,
offset > 10 kHz
–75
dBc
Notes:
1. Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25,
212.5, 250 MHz.
2. Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 and 250 MHz.
3. 156.25 MHz. Increase in jitter on output clock due to sinewave noise added to VDD (2.5/3.3 V = 100 mVPP).
6
Rev. 1.1
Si514
Table 6. Output Clock Jitter and Phase Noise (LVDS)
VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85 oC; Output Format = LVDS
Symbol
Test Condition
Min
Typ
Max
Unit
Parameter
1
Period Jitter
(RMS)
JPRMS
10k samples
—
—
2.1
ps
1
Period Jitter
(Pk-Pk)
JPPKPK
10k samples
—
—
—
18
ps
ps
Phase Jitter
(RMS)
φJ
1.875 MHz to 20 MHz integration
0.25
0.55
2
bandwidth (brickwall)
12 kHz to 20 MHz integration band-
—
0.8
1.0
ps
2
width (brickwall)
Phase Noise,
156.25 MHz
φN
100 Hz
1 kHz
—
—
—
—
—
—
–86
–109
–116
–123
–136
–75
—
—
—
—
—
—
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc
10 kHz
100 kHz
1 MHz
Spurious
SPR
LVPECL output, 156.25 MHz,
offset>10 kHz
Notes:
1. Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25,
212.5, 250 MHz.
2. Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 and 250 MHz.
Rev. 1.1
7
Si514
Table 7. Output Clock Jitter and Phase Noise (HCSL)
VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85 oC; Output Format = HCSL
Symbol
Test Condition
Min
Typ
Max
Unit
Parameter
*
Period Jitter
(RMS)
JPRMS
10k samples
—
—
1.2
ps
*
Period Jitter
(Pk-Pk)
JPPKPK
10k samples
—
—
—
11
ps
ps
Phase Jitter
(RMS)
φJ
1.875 MHz to 20 MHz integration
0.25
0.30
*
bandwidth (brickwall)
12 kHz to 20 MHz integration band-
—
0.8
1.0
ps
*
width (brickwall)
Phase Noise,
156.25 MHz
φN
100 Hz
1 kHz
—
—
—
—
—
—
–90
–112
–120
–127
–140
–75
—
—
—
—
—
—
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc
10 kHz
100 kHz
1 MHz
Spurious
SPR
LVPECL output, 156.25 MHz,
offset>10 kHz
*Note: Applies to an output frequency of 100 MHz.
8
Rev. 1.1
Si514
Table 8. Output Clock Jitter and Phase Noise (CMOS, Dual CMOS)
VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85 oC; Output Format = CMOS, Dual CMOS
Symbol
Test Condition
Min
Typ
Max
Unit
Parameter
Phase Jitter
φJ
1.875 MHz to 20 MHz integration
—
0.25
0.35
ps
2
(RMS)
bandwidth (brickwall)
12 kHz to 20 MHz integration band-
—
0.8
1.0
ps
2
width (brickwall)
Phase Noise,
156.25 MHz
φN
100 Hz
1 kHz
—
—
—
—
—
—
–86
–108
–115
–123
–136
–75
—
—
—
—
—
—
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc
10 kHz
100 kHz
1 MHz
Spurious
SPR
LVPECL output, 156.25 MHz,
offset>10 kHz
Notes:
1. Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25,
212.5 MHz.
2. Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 MHz.
Table 9. Environmental Compliance and Package Information
Parameter
Conditions/Test Method
MIL-STD-883, Method 2002
MIL-STD-883, Method 2007
MIL-STD-883, Method 2003
MIL-STD-883, Method 1014
MIL-STD-883, Method 2036
Gold over Nickel
Mechanical Shock
Mechanical Vibration
Solderability
Gross and Fine Leak
Resistance to Solder Heat
Contact Pads
Rev. 1.1
9
Si514
Table 10. Thermal Characteristics
Parameter
Symbol
Test Condition
Still air
Value
110
Units
°C/W
°C/W
*
CLCC, Thermal Resistance Junction to Ambient
JA
*
2x5 x 3.2 mm, Thermal Resistance Junction to Ambient
Still air
164
JA
*Note: Applies to 5 x 7 and 3.2 x 5 mm packages.
Table 11. Absolute Maximum Ratings1
Parameter
Maximum Operating Temperature
Storage Temperature
Symbol
Rating
Units
o
T
85
C
AMAX
o
T
–55 to +125
–0.5 to +3.8
C
S
Supply Voltage
V
V
V
DD
Input Voltage (any input pin)
ESD Sensitivity (HBM, per JESD22-A114)
V
–0.5 to V + 0.3
I
DD
HBM
2
kV
2
o
Soldering Temperature (Pb-free profile)
T
260
C
PEAK
2
Soldering Temperature Time at T
(Pb-free profile)
T
20–40
sec
PEAK
P
Notes:
1. Stresses beyond those listed in this table may cause permanent damage to the device. Functional operation or
specification compliance is not implied at these conditions. Exposure to maximum rating conditions for extended
periods may affect device reliability.
2. The device is compliant with JEDEC J-STD-020E.
10
Rev. 1.1
Si514
2. Solder Reflow and Rework Requirements for 2.5x3.2 mm Packages
Reflow of Silicon Labs' components should be done in a manner consistent with the IPC/JEDEC J-STD-20E
standard. The temperature of the package is not to exceed the classification Temperature provided in the standard.
The part should not be within -5°C of the classification or peak reflow temperature (T
) for longer than 30
PEAK
seconds. Key to maintaining the integrity of the component is providing uniform heating and cooling of the part
during reflow and rework. Uniform heating is achieved through having a preheat soak and controlling the
temperature ramps in the process. J-STD-20E provides minimum and maximum temperatures and times for the
preheat/Soak step that need to be followed, even for rework. The entire assembly area should be heated during
rework. Hot air should be flowed from both the bottom of the board and the top of the component. Heating from the
top only will cause un-even heating of component and can lead to part integrity issues. Temperature Ramp-up rate
are not to exceed 3°C/second. Temperature ramp-down rates from peak to final temperature are not to exceed
6°C/second. Time from 25°C to peak temperature is not to exceed 8 min for Pb-free solders.
Rev. 1.1
11
Si514
3. Functional Description
The Si514 offers system designers a programmable, low jitter XO solution with exceptionally fine frequency tuning
resolution. To enable designers to take full advantage of this flexibility and performance, Silicon Laboratories
provides an easy-to-use evaluation kit and intuitive suite of Windows-based software utilities to simplify the Si514
programming process.
®
The Si5xx-PROG-EVB kit contains the Programmable Oscillator Software suite and an EVB Driver (USBXpress )
for use with USB-equipped PCs. Go to
http://www.silabs.com/products/clocksoscillators/Pages/DevelopmentTools.aspx for more information.
Alternatively, “3.1. Programming a New Output Frequency” provides designers a detailed description, along with
examples, of the frequency programming requirements and process for designers who are interested in learning
more about the programming algorithms implemented within the Programmable Oscillator Software suite.
3.1. Programming a New Output Frequency
The output frequency (Fout) is determined by programming the feedback multiplier (M=M_Int.M_Frac), High-
Speed Divider (HS_DIV), and Low-Speed Divider (LS_DIV) according to the following formula:
FXO M
-------------------------------------------------
=
Fout
HS_DIV LS_DIV
where FXO = 31.98MHz
Figure 1. Block Diagram of Si514
The value of the feedback multiplier M is adjustable in the following range:
65.04065041 M 78.17385866.
This keeps the VCO frequency within the range of 2080 MHz F
2500 MHz, since the VCO frequency is the
VCO
product of the internal fixed-frequency crystal (F ) and the high-resolution 29-bit fractional multiplier (M). This 29-
XO
bit resolution of M allows the VCO frequency to have a frequency tuning resolution of 0.026 ppb.
The device comes from the factory with a pre-programmed center frequency within the range of
100 kHz F
250 MHz, as specified by the 6-digit code in the part number. (See section “7. Ordering
OUT
Information” for more information.) To change from the factory-programmed frequency to a different value, the user
must follow one of two algorithms based on the magnitude of the frequency change.
“Small Frequency Change.” To change the frequency by < ±1000 ppm, the user must keep the same center
frequency and only update the value of M. Refer to section "3.2. Programming a Small Frequency Change (sub
±1000 ppm)" on page 13.
“Large Frequency Change.” To change the frequency by ±1000 ppm, the user must change the center
frequency. This may require updates to the output dividers (HS_DIV and/or LS_DIV) and possibly the LP1 and
12
Rev. 1.1
Si514
LP2 values, in addition to updating the value of M, which requires the VCO to be recalibrated. Refer to section
"3.3. Programming a Large Frequency Change (> ±1000 ppm)" on page 14. Figure 2 provides a graphic
depiction of the difference between small and large frequency changes.
Small Frequency Change
Range of small
Large Frequency Change
frequency change
FCENTER
FCENTER
-1000 ppm
+1000 ppm
FVCO_MIN
FVCO_MAX
(2080 MHz)
(2500 MHz)
FCENTER
F'CENTER
Programming a new center frequency requires a VCO
calibration and the output should be squelched
Figure 2. Small vs. Large Frequency Change Illustration
3.2. Programming a Small Frequency Change (sub ±1000 ppm)
The value of the feedback multiplier, M is the only parameter that needs to be updated for output frequency
changes less than ±1000 ppm from the center frequency (recalibrating the VCO is NOT required). This enables
the output to remain continuous during the change. For example, the output frequency can be swept continuously
between 148.5 MHz and 148.352 MHz (i.e., –0.997 ppm) with no output discontinuities or glitches by changing M
in either multiple steps or in a single step. For small frequency changes, each update of M requires 100 µs to settle.
Note: It is not possible to implement a frequency change ≥ ±1000 ppm using multiple small frequency changes
without changing the center frequency and recalibrating the VCO.
Use the following procedure to make small frequency changes:
1. If the current value of M is already known, then skip to step 2; else, using the serial port, read the current M
value (Registers 5-9).
2. Calculate the new value of M as follows (all values are in decimal format):
29
a. Mcurrent = M_Int + M_Frac/2 (Eq 2.2)
b. Mnew = Mcurrent x F _new / F _current (Eq 2.3)
out
out
c. M_Intnew = INT[Mnew]*
(Eq 2.4)
29
d. M_Fracnew = (Mnew – INT[Mnew]) x 2
(Eq 2.5)
*Where INT[n] rounds n down to the nearest integer (e.g., INT[3.9] = 3)
2
3. Using the I C port, write the new value of M_Frac[23:0] (Not all registers need to be updated.)
(Registers: 5, 6, 7)
4. If necessary, write new value of M_Int[2:0] and M_Frac[28:24] register. (Register 8)
5. Write M_Int[8:3]. (Register 9) Frequency changes take effect when M_Int[8:3] is written.
Example 2.1:
An Si514 generating a 148.5 MHz clock must be reconfigured “on-the-fly” to generate a 148.352 MHz clock. This
represents a change of –0.996.633 ppm which is within the ±1000 ppm window.
1. Read the current value of M:
a. Register 5 = 0xD3 (M_Frac[7:0])
b. Register 6 = 0x65 (M_Frac[15:8])
c. Register 7 = 0x7C (M_Frac[23:16])
Rev. 1.1
13
Si514
d. Register 8 = 0x49 (M_Int[2:0],M_Frac[28:24])
e. Register 9 = 0x09 (M_Int[8:3])
f. M_Int = 0b001001010 = 0x4A = 0d74
g. M_Frac = 0x097C65D3 = 159,147,475
29
29
h. M= M_Int + M_Frac/2 = 74 + 159,147,475/2 = 74.296435272321105
2. Calculate Mnew:
a. Mnew = 74.296435272321105 x 148.352/148.5 = 74.2223889933965
b. M_Intnew = 74 = 0x4A
29
c. M_Fracnew = 0.2223889933965 x 2 = 119,394,181 = 0x071DCF85
3. Write Mnew to Registers 5-7:
a. Register 5 = 0x85
b. Register 6 = 0xCF
c. Register 7 = 0x1D
4. Write Mnew to Register 8:
a. Register 8 = 0x47
5. Write Mnew to Register 9:
a. Register 9 = 0x09
3.3. Programming a Large Frequency Change (> ±1000 ppm)
Large frequency changes are those that vary the F
frequency by an amount greater than ±1000 ppm from an
VCO
operating F
. Figure 2 illustrates the difference between large and small frequency changes. Changing from
CENTER
F
to F'
requires a calibration cycle that resets internal circuitry to establish F'
as the new
CENTER
CENTER
CENTER
operating center frequency. The below steps are recommended when performing large frequency changes:
1. Disable the output: Write OE register bit to a 0 (Register 132, bit2)
2. If using one of the standard frequencies listed in Table 12, then write the new LP1, LP2, M_Frac, M_Int,
HS_DIV and LS_DIV register values according to the table (be sure to write M_Int[8:3] (Register 9) after writing
to the M_Frac registers (Registers 5-8)). Skip to Step 9. If the desired frequency is not in the table, then follow
steps 4-8 below.
3. Determine the minimum value of LS_DIV (minimizing LS_DIV minimizes the number of dividers on the output
stage, thus minimizing jitter) according to the following formula:
a. LS_DIV = F
(MIN)/(F
x HS_DIV(MAX)) (Eq 2.6)
OUT
VCO
b. LS_DIV = 2080/(F
(MHz) x 1022) (Eq 2.7)
OUT
i. Since LS_DIV is restricted to: dividing by 1,2,4,8,16,32, choose the next largest value over the
result derived in Eq 2.7 (e.g., if result is 4.135, choose LS_DIV = 8)
4. Determine the minimum value for HS_DIV (this optimizes timing margins)
a. HS_DIV(MIN) = F
(MIN)/(F
x LS_DIV) (Eq 2.8)
OUT
VCO
b. HS_DIV(MIN) = 2080/(F
(MHz) x LS_DIV) (Eq 2.9)
OUT
i.HS_DIV(MIN) will be the next even number greater than or equal to the result derived in Eq 2.9
(keeping in the range of 10-1022)
Note: SPEED_GRADE_MIN (Reg 48) ≤ LS_DIV x HS_DIV ≤ SPEED_GRADE_MAX (Reg 49); If outside this range, the output
will be forced to the disabled state.
5. Determine a value for M according to the following formula (all values are in decimal format):
a. M = LS_DIV x HS_DIV x F
b. M = LS_DIV x HS_DIV x F
c. M_Int = INT[M] (Eq 2.12)
/F (Eq 2.10)
OUT XO
(MHz)/31.98 (Eq 2.11)
OUT
29
d. M_Frac = (M – INT[M]) x 2 (Eq 2.13)
14
Rev. 1.1
Si514
Table 12. Standard Frequency Table
HEX
DEC
Fout
M
M_INT M_FRAC HSDIV LSDIV LP1 LP2 M_INTX M_FRACX HSDIVX LSDIVX LP1_X LP2_X
(MHz)
0.100000 65.04065041
1.544000 65.08167605
2.048000 65.06466542
4.096000 65.06466542
4.915200 65.16712946
19.440000 65.65103189
24.576000 66.08930582
25.000000 65.66604128
27.000000 65.85365854
38.880000 65.65103189
44.736000 67.14596623
54.000000 67.54221388
62.500000 66.44777986
65.536000 65.57698562
74.175824 69.58332458
74.250000 69.65290807
77.760000 68.08255159
106.250000 66.44777986
125.000000 70.3564728
148.351648 74.22221288
148.500000 74.29643527
150.000000 65.66604128
155.520000 68.08255159
156.250000 68.40212633
212.500000 66.44777986
250.000000 78.17385866
65
65
65
65
65
65
66
65
65
65
67
67
66
65
69
69
68
66
70
74
74
65
68
68
66
78
21824021
43849494
34716981
34716981
89726943
349520087
47945695
357578187
458304437
349520087
78365022
291098862
240399983
309766794
313169998
350527350
44319550
240399983
191379875
119299633
159147475
357578187
44319550
215889929
240399983
93339658
650
674
1016
508
424
108
86
5
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
2
3
3
3
2
3
3
2
4
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
3
3
3
3
4
41
41
41
41
41
41
42
41
41
41
43
43
42
41
45
45
44
42
46
4A
4A
41
44
44
42
4E
14D0215
29D1716
211BD35
211BD35
5591FDF
14D540D7
2DB97DF
155035CB
1B512BB5
14D540D7
4ABC15E
1159D0EE
E54366F
1276AA8A
12AA984E
14E49F76
2A4433E
E54366F
B6839A3
71C5E31
97C65D3
155035CB
2A4433E
CDE3809
E54366F
590400A
28A
2A2
3F8
1FC
1A8
6C
56
54
4E
36
30
28
22
20
1E
1E
1C
14
12
10
10
E
5
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
2
3
3
3
2
3
3
2
4
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
3
3
3
3
4
84
78
54
48
40
34
32
30
30
28
20
18
16
16
14
14
E
14
E
10
A
10
A
Rev. 1.1
15
Si514
6. Determine values for LP1 and LP2 according to Table 13:
Table 13. LP1, LP2 Values
Fvco_max
Fvco_min
M_max
M_min
LP1
4
LP2
4
2500000000.00000
2425467616.18572
2332545246.89005
2170155235.53450
2087014168.27005
2425467616.18572
2332545246.89005
2170155235.53450
2087014168.27005
2080000000.00000
78.173858662
75.843265046
72.937624981
67.859763463
65.259980246
75.843265046
72.937624981
67.859763463
65.259980246
65.040650407
3
4
3
3
2
3
2
2
7. Write new LP1, LP2, M_Frac, M_Int, HS_DIV and LS_DIV register values (be sure to write M_Int[8:3] (Register
9) after writing to the M_Frac registers (Registers 5-8)
8. Write FCAL (Register 132, bit 0) to a 1 (this bit auto-resets, so it will always read as 0).
9. Enable the output: Write OE register bit to a 1.
The Si514 does not automatically detect large frequency changes. The user needs to assert the FCAL register bit
to initiate the calibration cycle required to re-center the VCO around the new frequency. Large frequency changes
are discontinuous and output may skip to intermediate frequencies or generate glitches. Resetting the OE bit
before FCAL will prevent intermediate frequencies from appearing on the output while Si514 completes a
calibration cycle and settles to F'
. Settling time for large frequency changes is 10 msec maximum.
CENTER
Example 2.2:
The user has a part that is programmed with SPEED_GRADE_MIN = 20 and SPEED_GRADE_MAX = 250 that is
programmed from the factory for F = 50 MHz and wants to change to an STS-1 rate of 51.84 MHz. This
OUT
represents a change of +36,800 ppm which exceeds ±1000 ppm and therefore requires a large frequency change
process.
1. Write Reg 132, bit 2 to a 0 to disable the output.
2. Since 51.84 MHz is not in Table 2.1, the divider parameters must be calculated.
3. Calculate LS_DIV by using Eq 2.7:
a. LS_DIV = 2080/(51.84 x 1022) = 0.039
b. Since 0.039 < 1, use a divide-by-one (bypass), therefore LS_DIV = 0
4. Calculate HS_DIV(MIN) by using Eq 2.9:
a. HS_DIV(MIN) = 2080/(51.84 x 1) = 40.123
b. Since 40.123 > 40, use HS_DIV(MIN) = 42 = 0x2A
5. From Eq 2.11:
a. M = 1 x 42 x 51.84/31.98 = 68.08255159474
b. M_Int = 68 = 0x44
29
c. M_Frac = 0.08255259474 x 2 = 44,320,087 = 0x2A44557
6. From Table 2.2:
a. LP1 = 3
b. LP2 = 3
16
Rev. 1.1
Si514
7. Write Registers 0, 5-11:
a. Register 0 = 0x33
b. Register 5 = 0x57 (M_Frac[7:0])
c. Register 6 = 0x45 (M_Frac[15:8])
d. Register 7 = 0xA4 (M_Frac[23:16])
e. Register 8 = 0x42 (M_Int[2:0],M_Frac[28:24])
f. Register 9 = 0x05 (M_Int[8:3])
g. Register 10 = 0x2A
h. Register 11 = 0x00
8. Calibrate the VCO by writing Register 132, bit 0 to a 1.
9. Enable the output by writing Register 132, bit 2 to a 1.
Rev. 1.1
17
Si514
4. All-Digital PLL Applications
The Si514 uses a high resolution divider M that enables fine frequency adjustments with resolution better than
0.026 parts per billion. Fine frequency adjustments are useful when making frequency corrections that compensate
for changing ambient conditions, long term aging or when locking the Si514 to an input clock reference. Figure 3
shows a typical implementation using a system IC such as an FPGA to control the output of the Si514 in a phase-
locked application. Refer to “AN575: An Introduction to FPGA-Based ADPLLs” for more information.
Si514
SCL
SDA
Fin
I2C Control
÷
Loop
Filter
Command
Conversion
I2C
Master
PD
CLK_OUT
FB
Any Frequency
DSPLL
÷
FPGA
Figure 3. All-Digital PLL Application Using Si514 with Dual CMOS Output
Since small frequency changes must be within ±1000 ppm of the center frequency, HS_DIV and LS_DIV remain
constant. The below expression can be used to calculate a new M divider value based on a desired output
2
frequency shift, where ∆F
is in ppm.
OUT
M2 = M11 – FOUT 10–6
Some systems, particularly those that use feedback control, can simplify the computation by implementing an
approximate frequency change based on toggling a bit position or adding/subtracting a bit to the existing M_Frac
value. Since M ranges approximately ±10% between 65.04065041 and 78.17385866, the effect of changing
M_Frac by a single bit depends only slightly on the absolute value of M.
For M=71 near the midpoint of the range, toggling M_Frac[0] changes the output frequency by 0.026 ppb. Each
higher order bit doubles the influence such that toggling M_Frac[1] is 0.052 ppb, M_Frac[2] is 0.1 ppb, etc. Figure 4
shows this trend across multiple registers generalized to M_Frac[N]. Coarse changes greater than ±1.7 ppm are
possible but most applications require finer transitions. Toggling each bit involves incrementing or decrementing
the bit position. Writing M_Int[8:3] in register 9 completes the operation.
1.7ppm
6.7ppb
M = 71.000000000000
0.026ppb
M_Int[8:0] = 000100111
M_Frac[28:0] = 00000000000000000000000000000
M_Frac[23:16] = 00000000
M_Frac[15:8] = 00000000
M_Frac[7:0] = 00000000
Figure 4. Output Frequency Change When Toggling M_Frac[N], M=71
18
Rev. 1.1
Si514
5. User Interface
5.1. Register Map
Table 14 displays the Si514 user register map. Registers not shown are reserved. Registers with reserved bits are
read-modify-write.
Table 14. User Register Map
Address
Bit
7
6
5
4
3
2
1
0
0
5
LP1[3:0]
LP2[3:0]
M_Frac [7:0]
M_Frac [15:8]
M_Frac [23:16]
6
7
8
M_Int [2:0]
M_Frac [28:24]
M_Int [8:3]
HS_DIV [7:0]
9
10
11
14
128
132
LS_DIV [ 2:0]
OE_STATE [1:0]
HS_DIV [9:8]
RST
OE
FCAL
Rev. 1.1
19
Si514
5.2. Register Detailed Description
Note: Registers not shown are reserved. Registers with reserved bits are read-modify-write.
Register 0.
Bit
7
6
5
4
3
2
1
0
Name
Type
LP1[3:0]
R/W
LP2[3:0]
R/W
Default
Varies
Varies
Bit
Name
Function
7:4
3:0
LP1[3:0]
LP2[3:0]
Sets loop compensation factor LP1. Value depends on VCO frequency.
Sets loop compensation factor LP2. Value depends on VCO frequency.
Register 5.
Bit
7
6
5
4
3
2
1
0
Name
Type
M_Frac[7:0]
R/W
Default
Varies
Bit
Name
Function
7:0
M_Frac[7:0] Fractional part of feedback divider M that sets up the output frequency. Frequency
updates take effect when M_Int[8:3] is written.
Register 6.
Bit
7
6
5
4
3
2
1
0
Name
Type
M_Frac[15:8]
R/W
Default
Varies
Bit
Name
Function
7:0
M_Frac[15:8] Fractional part of feedback divider M that sets up the output frequency. Frequency
updates take effect when M_Int[8:3] is written.
20
Rev. 1.1
Si514
Register 7.
Bit
7
6
5
4
3
2
1
0
Name
Type
M_Frac[23:16]
R/W
Default
Varies
Bit
Name
Function
7:0
M_Frac[23:16] Fractional part of feedback divider M that sets up the output frequency. Frequency
updates take effect when M_Int[8:3] is written.
Register 8.
Bit
7
6
5
4
3
2
M_Frac[28:24]
R/W
1
0
Name
Type
M_Int[2:0]
R/W
Default
Varies
Varies
Bit
Name
M_Int[2:0]
Function
7:5
Integer part of feedback divider M that sets the output frequency. Frequency updates
take effect when M_Int[8:3] is written.
4:0
M_Frac[28:24] Fractional part of feedback divider M that sets up the output frequency. Frequency
updates take effect when M_Int[8:3] is written.
Rev. 1.1
21
Si514
Register 9.
Bit
7
6
5
4
3
2
1
0
Name
Type
M_Int[8:3]
R/W
R/W
R/W
Default
Varies
Bit
7:6
5:0
Name
Function
Reserved
M_Int[8:3]
Integer part of feedback divider M that sets the output frequency. Frequency updates
take effect when M_Int[8:3] is written.
Register 10.
Bit
7
6
5
4
3
2
1
0
Name
Type
HS_DIV[7:0]
R/W
Default
Varies
Bit
Name
Function
7:0
HS_DIV[7:0] Integer divider that divides VCO frequency and provides output to LS_DIV. Follow the
large frequency change procedure when updating. The allowed values are even num-
bers in the range from 10 to 1022 (i.e., 10, 12, 14, 16, ...., 1022). The decimal value
represents the actual divide value (i.e. 12 means divide-by-12).
22
Rev. 1.1
Si514
Register 11.
Bit
7
6
5
LS_DIV[2:0]
R/W
4
3
2
1
0
Name
Type
HS_DIV[9:8]
R/W
R/W
R/W
R/W
Default
Varies
Varies
Bit
7
Name
Reserved
Function
6:4
LS_DIV[2:0] Last output divider stage. Used during large frequency changes. To update, follow
large frequency change procedure. LS_DIV value updates asynchronously.
000: divide-by-1
001: divide-by-2
010: divide-by-4
011: divide-by-8
100: divide-by-16
101: divide-by-32
All others reserved.
3:2
1:0
Reserved
HS_DIV[9:8] Integer divider that divides VCO frequency and provides output to LS-DIV. Follow the
large frequency change procedure when updating. The allowed values are even num-
bers in the range from 10 to 1022 (i.e., 10, 12, 14, 16, ..., 1022). The decimal value
represents the actual divide value (i.e., 12 means divide-by-12).
Register 14.
Bit
7
6
5
4
3
2
1
0
Name
Type
OE_STATE[1:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
Bit
7:6
5:4
Name
Reserved
Function
OE_STATE[1:0] Sets logic state of output when output disabled.
00: high impedance
10: logic low when output disabled
01: logic high when output disabled
11: reserved
3:0
Reserved
Rev. 1.1
23
Si514
Register 128.
Bit
7
6
5
4
3
2
1
0
Name
Type
RST
R/W
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
Bit
Name
Function
7
RST
Global Reset.
Resets all register values to default values. Self-clearing.
6:0
Reserved
Register 132.
Bit
7
6
5
4
3
2
OE
R/W
1
1
0
FCAL
R/W
0
Name
Type
R/W
R/W
R/W
R/W
R/W
R/W
Default
Bit
7:3
2
Name
Reserved
OE
Function
Output Enable.
OE can stop in high, low or high impedance state.
1: Output driver enabled.
0: Output driver powered down. OE_STATE register determines output state when dis-
abled.
1
0
Reserved
FCAL
Initiates frequency calibration cycle. Necessary when making large frequency
changes. Frequency calibration cycle takes 10 msec maximum. To prevent intermedi-
ate frequencies on the output, set disable output using OE register. Self-clearing.
24
Rev. 1.1
Si514
2
5.3. I C Interface
2
Configuration and operation of the Si514 is controlled by reading and writing to the RAM space using the I C
interface. The device operates in slave mode with 7-bit addressing and can operate in Standard-Mode (100 kbps)
or Fast-Mode (400 kbps). Burst data transfer with auto address increments are also supported.
2
The I C bus consists of a bidirectional serial data line (SDA) and a serial clock input (SCL). Both the SDA and SCL
2
pins must be connected to the VDD supply via an external pull-up as recommended by the I C specification. The
2
Si514 7-bit I C slave address is user-customized during the part number configuration process. See "6. Pin
Descriptions" on page 27 for more details.
2
Data is transferred MSB first in 8-bit words as specified by the I C specification. A write command consists of a 7-
bit device (slave) address + a write bit, an 8-bit register address, and 8 bits of data as shown in Figure 5.
A write burst operation is also shown where every additional data word is written using an auto-incremented
address.
Write Operation – Single Byte
S
Slv Addr [6:0]
0
A
Reg Addr [7:0]
A
Data [7:0]
A
A
P
Write Operation - Burst (Auto Address Increment)
Slv Addr [6:0] Reg Addr [7:0] Data [7:0]
S
0
A
A
Data [7:0]
A
P
Reg Addr +1
1 – Read
0 – Write
A – Acknowledge (SDA LOW)
N – Not Acknowledge (SDA HIGH)
S – START condition
From slave to master
From master to slave
P – STOP condition
Figure 5. I2C Write Operation
A read operation is performed in two stages. A data write is used to set the register address, then a data read is
performed to retrieve the data from the set address. A read burst operation is also supported. This is shown in
Figure 6.
Rev. 1.1
25
Si514
Read Operation – Single Byte
S
Slv Addr [6:0]
0
A Reg Addr [7:0]
A
P
P
S
Slv Addr [6:0]
1
A
Data [7:0]
N
Read Operation - Burst (Auto Address Increment)
S
S
Slv Addr [6:0]
Slv Addr [6:0]
0
1
A Reg Addr [7:0]
Data [7:0]
A
P
A
A
Data [7:0]
N P
Reg Addr +1
1 – Read
0 – Write
A – Acknowledge (SDA LOW)
N – Not Acknowledge (SDA HIGH)
S – START condition
From slave to master
From master to slave
P – STOP condition
Figure 6. I2C Read Operation
2
2
The timing specifications and timing diagram for the I C bus is compatible with the I C-Bus standard. SDA timeout
is supported for compatibility with SMBus interfaces.
2
The I C bus can be operated at a bus voltage of 1.71 to 3.63 V and is 3.3 V tolerant.
26
Rev. 1.1
Si514
6. Pin Descriptions
VDD
1
2
3
6
5
4
SDA
SCL
GND
CLK–
CLK+
Table 15. Si514 Pin Descriptions
Pin
1
Name
SDA
Function
I2C Serial Data.
2
SCL
I2C Serial Clock.
3
GND
CLK+
CLK-
Electrical and Case Ground.
Clock Output.
4
5
Complementary clock output (LVPECL, LVDS, HCSL, and
Complementary dual CMOS formats).
Clock output for in-phase dual CMOS format.
No connect (N/C) for single-ended CMOS format.
6
VDD
Power Supply Voltage.
6.1. Dual CMOS (1:2 Fanout Buffer)
Dual CMOS output format ordering options support either complementary or in-phase output signals. This feature
enables replacement of multiple XOs with a single Si514 device.
~
Complementary
Outputs
~
In-Phase
Outputs
Figure 7. Integrated 1:2 CMOS Buffer Supports Complementary or In-Phase Outputs
Rev. 1.1
27
Si514
7. Ordering Information
The Si514 supports a wide variety of options including startup frequency, stability, output format, and VDD. Specific
device configurations are programmed into the Si514 at time of shipment. Configurations can be specified using
the Part Number Configuration chart below. Silicon Labs provides a web browser-based part number configuration
utility to simplify this process. To access this tool refer to www.silabs.com/oscillators and click “Customize” in the
product table. The Si514 XO series is supplied in industry-standard, RoHS-compliant, 2.5 x 3.2 mm, 3.2 x 5.0 mm,
and 5 x 7 mm packages. Tape and reel packaging is an ordering option.
A = Revision: A
G = Temp Range: -40°C to 85°C
R = Tape & Reel; Blank = Trays.
Series
514
Output Format
Package
6-pin
LVPECL, LVDS, HCSL,
CMOS, Dual CMOS
1st Option Code:
Output Format
514 X X X XXXXXX X AGR
VDD
Output Format
A
B
C
D
E
F
3.3V
3.3V
3.3V
3.3V
2.5V
2.5V
2.5V
2.5V
1.8V
1.8V
1.8V
3.3V
3.3V
2.5V
2.5V
1.8V
1.8V
LVPECL
LVDS
3rd Option Code:
Frequency Grade
CMOS
HCSL
LVPECL
Package Option
Dimensions
CMOS (MHz) LVPECL, LVDS, HCSL (MHz)
A
B
C
0.1 to 212.5
0.1 to 170
0.1 to 125
0.1 to 250
0.1 to 170
0.1 to 125
LVDS
A
5 x 7 mm
G
H
J
CMOS
B
C
3.2 x 5 mm
HCSL
2.5 x 3.2 mm
LVDS
K
L
CMOS
6-digit Frequency and Default I2C Address Code
2nd Option Code:
HCSL
Frequency Stability
M
N
P
Q
R
S
Dual CMOS (In-phase)
Dual CMOS (Complementary)
Dual CMOS (In-phase)
Dual CMOS (Complementary)
Dual CMOS (In-phase)
Dual CMOS (Complementary)
Code
Description
Total
Temperature
±50ppm
The Si514 supports a user-defined start-up
frequency which must be in the same range as
specified by the Frequency Grade code. A
user-defined, 7-bit I2C address is supported.
Each unique start-up frequency/I2C address
combination is assigned a 6-digit code by:
www.silabs.com/VCXOPartNumber.
A
B
C
±100ppm
±50ppm
±30ppm
xxxxxx
±25ppm
±20ppm
Figure 8. Part Number Convention
Example orderable part number: 514ECB000107AAG supports 2.5 V LVPECL, ±30 ppm total stability, user
programmable output frequency range from 100 kHz to 170 MHz, 5x7 mm package and –40 to 85 °C temperature
range. The frequency code designates 10 MHz startup with I2C address of 0x55. Refer to www.silabs.com/VCXO
lookup to look up the attributes of any Silicon Labs orderable XO/VCXO part number.
Note: CMOS and Dual CMOS maximum frequency is 212.5 MHz.
28
Rev. 1.1
Si514
8. Package Outline Diagram: 5 x 7 mm, 6-pin
Figure 9 illustrates the 5 x 7 mm, 6-pin package details for the Si514. Table 16 lists the values for the dimensions
shown in the illustration.
Figure 9. Si514 Outline Diagram
Table 16. Package Diagram Dimensions (mm)
Dimension
Min
1.50
1.30
0.50
Nom
1.65
Max
1.80
1.50
0.70
A
b
1.40
c
0.60
D
5.00 BSC
4.40
D1
e
4.30
4.50
2.54 BSC
7.00 BSC
6.20
E
E1
H
6.10
0.55
1.17
0.05
1.80
6.30
0.75
1.37
0.15
2.60
0.65
L
1.27
L1
p
0.10
—
R
0.70 REF
0.15
aaa
bbb
ccc
ddd
eee
0.15
0.10
0.10
0.05
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
Rev. 1.1
29
Si514
9. PCB Land Pattern: 5 x 7 mm, 6-pin
Figure 10 illustrates the 5 x 7 mm, 6-pin PCB land pattern for the Si514. Table 17 lists the values for the
dimensions shown in the illustration.
Figure 10. Si514 PCB Land Pattern
Table 17. PCB Land Pattern Dimensions (mm)
Dimension
(mm)
4.20
2.54
1.55
1.95
C1
E
X1
Y1
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least
Material Condition (LMC) is calculated based on a Fabrication Allowance of
0.05 mm.
Solder Mask Design
5. All metal pads are to be non-solder mask defined (NSMD). Clearance
between the solder mask and the metal pad is to be 60 µm minimum, all the
way around the pad.
Stencil Design
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls
should be used to assure good solder paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1.
Card Assembly
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
30
Rev. 1.1
Si514
10. Package Outline Diagram: 3.2 x 5.0 mm, 6-pin
Figure illustrates the 3.2 x 5 mm package details for the Si514. Table 18 lists the values for the dimensions shown
in the illustration.
Figure 11. Si514 Outline Diagram
Table 18. Package Diagram Dimensions (mm)
Dimension
Min
1.06
0.54
0.35
Nom
1.17
Max
1.33
0.74
0.55
A
b
0.64
c
0.45
D
3.20 BSC
2.60
D1
e
2.55
2.65
1.27 BSC
5.00 BSC
4.40
E
E1
H
4.35
0.45
0.80
0.05
1.17
4.45
0.65
1.00
0.15
1.37
0.55
L
0.90
L1
p
0.10
1.27
R
0.32 REF
0.15
aaa
bbb
ccc
ddd
eee
0.15
0.10
0.10
0.05
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
Rev. 1.1
31
Si514
11. PCB Land Pattern: 3.2 x 5.0 mm, 6-pin
Figure 12 illustrates the 3.2 x 5.0 mm PCB land pattern for the Si514. Table 19 lists the values for the dimensions
shown in the illustration.
Figure 12. Si514 Recommended PCB Land Pattern
Table 19. PCB Land Pattern Dimensions (mm)
Dimension
(mm)
2.60
1.27
0.80
1.70
C1
E
X1
Y1
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Solder Mask Design
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the
pad.
Stencil Design
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls
should be used to assure good solder paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1.
Card Assembly
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
32
Rev. 1.1
Si514
12. Package Outline Diagram: 2.5 x 3.2 mm, 6-pin
Figure 13 illustrates the package details for the 2.5 x 3.2 mm Si514. Table 20 lists the values for the dimensions
shown in the illustration.
Figure 13. Si514 Outline Diagram
Rev. 1.1
33
Si514
Table 20. Package Diagram Dimensions (mm)
Dimension
Min
Nom
—
Max
A
—
1.1
A1
A2
W
0.26 REF
0.7 REF
0.65
0.45
0.7
0.75
0.55
D
e
3.20 BSC
1.25 BSC
2.50 BSC
0.30 BSC
0.5
E
M
L
D1
E1
SE
aaa
bbb
ddd
2.5 BSC
1.65 BSC
0.825 BSC
0.1
0.2
0.08
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
34
Rev. 1.1
Si514
13. PCB Land Pattern: 2.5 x 3.2 mm, 6-pin
Figure 14 illustrates the 2.5 x 3.2 mm PCB land pattern for the Si514. Table 21 lists the values for the dimensions
shown in the illustration.
Figure 14. Si514 Recommended PCB Land Pattern
Table 21. PCB Land Pattern Dimensions (mm)
Dimension
(mm)
C1
1.9
E
2.50
0.70
1.05
X1
Y1
Notes:
General
3. All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
4. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Stencil Design
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be
used to assure good solder paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.
Card Assembly
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification
for Small Body Components.
Rev. 1.1
35
Si514
14. Top Marking
Use the part number configuration utility located at: www.silabs.com/VCXOpartnumber to cross-reference the mark
code to a specific device configuration.
14.1. Si514 Top Marking
4 C CC CC
T T T T T T
Y Y WW
14.2. Top Marking Explanation
Mark Method:
Laser
Line 1 Marking:
4 = Si514
4CCCCC
CCCCC = Mark Code
Line 2 Marking:
Line 3 Marking:
TTTTTT = Assembly Manufacturing Code TTTTTT
Pin 1 indicator.
Circle with 0.5 mm diameter;
left-justified
YY = Year.
YYWW
WW = Work week.
Characters correspond to the year and
work week of package assembly.
36
Rev. 1.1
Si514
REVISION HISTORY
Revision 1.1
December, 2017
Added new 2.5 x 3.2 mm package.
Revision 1.0
Updated Table 1 on page 3.
Updates to supply current typical and maximum values for CMOS, LVDS, LVPECL and HCSL.
CMOS frequency test condition corrected to 100 MHz.
Updates to OE VIH minimum and VIL maximum values.
Updated Table 2 on page 3.
Dual CMOS nominal frequency maximum added.
Total stability footnotes clarified for 10 year aging at 40 °C.
Disable time maximum values updated.
Enable time parameter added.
Updated Table 3 on page 4.
CMOS output rise / fall time typical and maximum values updated.
LVPECL/HCSL output rise / fall time maximum value updated.
LVPECL output swing maximum value updated.
LVDS output common mode typical and maximum values updated.
HCSL output swing maximum value updated.
Duty cycle minimum and maximum values tightened to 48/52%.
Updated Table 5 on page 6.
Phase jitter test condition and maximum value updated.
Phase noise typical values updated.
Additive RMS jitter due to external power supply noise typical values updated.
Footnote 3 updated limiting the VDD to 2.5/3.3V
Added Tables 6, 7, 8 for LVDS, HCSL, CMOS, and Dual CMOS operations.
Moved Absolute Maximum Ratings table.
Added note to Figure 8 clarifying CMOS and Dual CMOS maximum frequency.
Updated Figure 9 outline diagram to correct pinout.
Updated “14. Top Marking” section and moved to page 36.
Rev. 1.1
37
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514FCBXXXXXXBAGR
Clock Generator, 170MHz, CMOS, PDSO6, 3.20 X 5 MM, ROHS COMPLIANT PACKAGE-6
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