516FAB000109BAG [SILICON]
Oscillator, 0.1MHz Min, 250MHz Max, 0.109MHz Nom;
| 型号： | 516FAB000109BAG |
| 厂家： | 
SILICON |
| 描述： | Oscillator, 0.1MHz Min, 250MHz Max, 0.109MHz Nom |
| 文件： | 总24页 (文件大小：622K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si516
DUAL FREQUENCY VOLTAGE-CONTROLLED
CRYSTAL OSCILLATOR (VCXO) 100 kHZ TO 250 MHZ
Features
Supports any frequency from
100 kHz to 250 MHz
Available CMOS, LVPECL,
LVDS, and HCSL outputs
i5
Two selectable output frequencies Optional 1:2 CMOS fanout buffer
Low-jitter operation
3.3 and 2.5 V supply options
Industry-standard 5x7, 3.2x5, and
2.5x3.2 mm packages
Short lead times: <2 weeks
AT-cut fundamental mode crystal
ensures high reliability/low aging
5X7MM, 3.2X5MM
2.5X3.2MM
Pb-free/RoHS-compliant
High power supply noise rejection Selectable Kv (60, 90, 120,
Ordering Information:
1% control voltage linearity
150 ppm/V)
See page 14.
Applications
SONET/SDH/OTN
PON
Low Jitter PLLs
xDSL
Broadcast video
Telecom
Switches/routers
FPGA/ASIC clock generation
Pin Assignments:
See page 12.
1
2
3
VDD
NC
6
5
4
Vc
FS
Description
The Si516 dual frequency VCXO utilizes Silicon Laboratories' advanced PLL
technology to provide any frequency from 100 kHz to 250 MHz. Unlike a
traditional VCXO where a different crystal is required for each output
frequency, the Si516 uses one fixed crystal and Silicon Labs’ proprietary
synthesizer to generate any frequency across this range. This IC-based
approach allows the crystal resonator to provide enhanced reliability,
improved mechanical robustness, and excellent stability. In addition, this
solution provides superior control voltage linearity and supply noise
rejection, improving PLL stability and simplifying low jitter PLL design in
noisy environments. The Si516 is factory-configurable for a wide variety of
user specifications, including frequency, supply voltage, output format,
tuning slope and stability. Specific configurations are factory-programmed at
time of shipment, eliminating long lead times and non-recurring engineering
charges associated with custom frequency oscillators.
CLK
GND
CMOS Dual VCXO
1
2
3
VDD
6
5
4
Vc
FS
CLK–
CLK+
GND
LVPECL/LVDS/HCSL/Dual CMOS
Dual VCXO
Functional Block Diagram
Rev. 1.2 6/18
Copyright © 2018 by Silicon Laboratories
Si516
Si516
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. Solder Reflow and Rework Requirements for 2.5x3.2 mm Packages . . . . . . . . . . . . . .11
3. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.1. Dual CMOS Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
4. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
5. Package Outline Diagram: 5 x 7 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
6. PCB Land Pattern: 5 x 7 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
7. Package Outline Diagram: 3.2 x 5.0 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
8. PCB Land Pattern: 3.2 x 5.0 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
9. Package Outline Diagram: 2.5 x 3.2 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
10. PCB Land Pattern: 2.5 x 3.2 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
11. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
11.1. Si516 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
11.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
2
Rev. 1.2
Si516
1. Electrical Specifications
Table 1. Recommended Operating Conditions
VDD = 2.5 or 3.3 V ±10%, TA = –40 to +85 oC
Parameter
Symbol
Test Condition
3.3 V option
2.5 V option
Min
2.97
2.25
—
Typ
3.3
2.5
24
Max
3.63
2.75
29
Unit
V
Supply Voltage
V
DD
V
Supply Current
I
CMOS, 100 kHz,
single-ended
mA
DD
LVDS
(output enabled)
—
—
—
—
22
42
44
—
26
46
47
22
mA
mA
mA
mA
V
LVPECL
(output enabled)
HCSL
(output enabled)
Tristate
(output disabled)
FS "1" Setting
V
0.80 x V
—
—
—
45
—
—
0.20 x V
—
IH
DD
FS "0" Setting
V
V
IL
DD
FS Internal Pull-Up Resistor
Operating Temperature
R
—
k
I
o
T
–40
85
C
A
Rev. 1.2
3
Si516
Table 2. Vc Control Voltage Input
VDD = 2.5 or 3.3 V ±10%, TA = –40 to +85 oC
Parameter
Symbol
Test Condition
Min
Typ
/2
Max
Unit
V
Control Voltage Range
V
0.1 x V
V
0.9 x V
DD
C
DD
DD
Control Voltage Tuning Slope
Kv
Ordering option
60, 90, 120, 150
ppm/V
(10 to 90% V
Kv Variation
)
DD
Kv_var
—
—
±10
%
Control Voltage Linearity
Modulation Bandwidth
Vc Input Impedance
L
BSL
–5
—
—
±1
10
+5
—
—
%
kHz
k
VC
BW
Z
100
VC
Table 3. Output Clock Frequency Characteristics
VDD = 2.5 or 3.3 V ±10%, TA = –40 to +85 oC
Parameter
Symbol
Test Condition
Min
0.1
0.1
–20
—
Typ
—
Max
212.5
250
Unit
MHz
MHz
ppm
ppm
ppm
ms
Nominal Frequency
F
F
CMOS, Dual CMOS
O
O
LVDS/LVPECL/HCSL
—
o
Temperature Stability
Aging
S
T = –40 to +85 C
—
+20
T
A
A
Frequency drift over 10-year life
Ordering option
—
±8.5
Minimum Absolute Pull Range APR
±30, ±50,±80, ±100
Startup Time
T
Minimum V until output fre-
—
—
10
SU
DD
quency (F ) within specification
O
Disable Time
T
F > 10 MHz
—
—
—
—
—
—
—
—
—
—
5
µs
µs
µs
µs
ms
D
O
F < 10 MHz
40
20
60
10
O
Enable Time
T
F > 10 MHz
O
D
F < 10 MHz
O
Settling Time after FS Change
t
FRQ
4
Rev. 1.2
Si516
Table 4. Output Clock Levels and Symmetry
VDD = 2.5 or 3.3 V ±10%, TA = –40 to +85 oC
Parameter
Symbol
Test Condition
Min
Typ
—
Max
—
Unit
CMOS Output Logic High
CMOS Output Logic Low
V
0.85 x V
V
OH
DD
V
—
–8
–6
8
—
0.15 x V
—
V
OL
DD
CMOS Output Logic High
Drive
I
3.3 V
2.5 V
—
mA
mA
mA
mA
ns
OH
—
—
CMOS Output Logic Low
Drive
I
3.3 V
—
—
OL
2.5 V
6
—
—
CMOS Output Rise/Fall Time
T /T
0.1 to 125 MHz,
—
0.8
1.2
R
F
(20 to 80% V
)
C = 15 pF
DD
L
0.1 to 212.5 MHz,
—
—
0.6
—
0.9
ns
ps
C = no load
L
LVPECL/HCSL Output
Rise/Fall Time
T /T
565
R
F
F
(20 to 80% V
)
DD
LVDS Output Rise/Fall Time
(20 to 80% V
T /T
—
—
800
—
ps
V
R
)
DD
LVPECL Output Common
Mode
V
50 to V – 2 V,
—
V
–
DD
OC
DD
single-ended
1.4 V
LVPECL Output Swing
LVDS Output Common Mode
LVDS Output Swing
V
50 to V – 2 V,
0.55
1.13
0.25
0.8
0.90
1.33
0.42
V
O
DD
PPSE
single-ended
V
100 line-line,
1.23
0.38
V
OC
V
= 3.3/2.5 V
DD
V
Single-ended 100
differential termination
V
V
O
PPSE
HCSL Output Common Mode
HCSL Output Swing
Duty Cycle
V
50 to ground
0.35
0.58
48
0.38
0.73
50
0.42
0.85
52
V
OC
V
Single-ended
O
PPSE
DC
%
Rev. 1.2
5
Si516
Table 5. Output Clock Jitter and Phase Noise (LVPECL)
VDD = 2.5 or 3.3 V ±10%, TA = –40 to +85 oC; Output Format = LVPECL
Parameter
Symbol
Test Condition
Min
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Typ
—
Max
1.3
11
1.3
0.5
—
Unit
ps
1
Period Jitter (RMS)
Period Jitter (PK-PK)
Phase Jitter (RMS)
J
10 k samples
PRMS
1
J
10 k samples (brickwall)
—
ps
PPKPK
2
φJ
12 kHz to 20 MHz (brickwall)
0.9
ps
2
1.875 MHz to 20 MHz (brickwall)
0.25
–71
–94
–113
–124
–136
4.0
ps
Phase Noise, 155.52 MHz
φN
100 Hz offset
1 kHz offset
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
ps
—
10 kHz offset
—
100 kHz offset
—
1 MHz offset
—
Additive RMS Jitter Due to
External Power Supply
J
100 kHz sinusoidal noise
200 kHz sinusoidal noise
500 kHz sinusoidal noise
1 MHz sinusoidal noise
—
PSRR
3.5
—
ps
3
Noise
3.5
—
ps
3.5
—
ps
Spurious Performance
SPR
F = 156.25 MHz,
–75
—
dBc
O
Offset > 10 kHz
Notes:
1. Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25,
212.5, 250 MHz.
2. Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5, 250 MHz.
3. 156.25 MHz. Increase in jitter on output clock due to spurs introduced by sinewave noise added to VDD (100 mVPP).
6
Rev. 1.2
Si516
Table 6. Output Clock Jitter and Phase Noise (LVDS)
VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85 oC; Output Format = LVDS
Symbol
Test Condition
Min
Typ
Max
Unit
Parameter
1
Period Jitter
(RMS)
JPRMS
10k samples
—
—
2.1
ps
1
Period Jitter
(Pk-Pk)
JPPKPK
φJ
10k samples
—
—
—
18
ps
ps
Phase Jitter
(RMS)
1.875 MHz to 20 MHz integration
0.25
0.55
2
bandwidth (brickwall)
12 kHz to 20 MHz integration band-
—
0.8
1.1
ps
2
width (brickwall)
Phase Noise,
156.25 MHz
φN
100 Hz
1 kHz
—
—
—
—
—
—
–72
–93
—
—
—
—
—
—
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc
10 kHz
100 kHz
1 MHz
–114
–123
–136
–75
Spurious
SPR
LVPECL output, 156.25 MHz,
offset>10 kHz
Notes:
1. Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25,
212.5, 250 MHz.
2. Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 and 250 MHz.
Rev. 1.2
7
Si516
Table 7. Output Clock Jitter and Phase Noise (HCSL)
VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85 oC; Output Format = HCSL
Symbol
Test Condition
Min
Typ
Max
Unit
Parameter
*
Period Jitter
(RMS)
JPRMS
10k samples
—
—
1.2
ps
*
Period Jitter
(Pk-Pk)
JPPKPK
φJ
10k samples
—
—
—
11
ps
ps
Phase Jitter
(RMS)
1.875 MHz to 20 MHz integration
0.25
0.30
*
bandwidth (brickwall)
12 kHz to 20 MHz integration band-
—
0.8
1.0
ps
*
width (brickwall)
Phase Noise,
156.25 MHz
φN
100 Hz
1 kHz
—
—
—
—
—
—
–75
–98
—
—
—
—
—
—
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc
10 kHz
100 kHz
1 MHz
–117
–127
–136
–75
Spurious
SPR
LVPECL output, 156.25 MHz,
offset>10 kHz
*Note: Applies to an output frequency of 100 MHz.
8
Rev. 1.2
Si516
Table 8. Output Clock Jitter and Phase Noise (CMOS, Dual CMOS)
VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85 oC; Output Format = CMOS, Dual CMOS
Symbol
Test Condition
Min
Typ
Max
Unit
Parameter
Phase Jitter
(RMS)
φJ
1.875 MHz to 20 MHz integration
—
0.25
0.35
ps
2
bandwidth (brickwall)
12 kHz to 20 MHz integration band-
—
0.8
1.1
ps
2
width (brickwall)
Phase Noise,
156.25 MHz
φN
100 Hz
1 kHz
—
—
—
—
—
—
–71
–93
—
—
—
—
—
—
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc
10 kHz
100 kHz
1 MHz
–113
–123
–136
–75
Spurious
SPR
LVPECL output, 156.25 MHz,
offset > 10 kHz
Notes:
1. Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25,
212.5 MHz.
2. Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 MHz.
Table 9. Environmental Compliance and Package Information
Parameter
Conditions/Test Method
MIL-STD-883, Method 2002
MIL-STD-883, Method 2007
MIL-STD-883, Method 2003
MIL-STD-883, Method 1014
MIL-STD-883, Method 2036
Gold over Nickel
Mechanical Shock
Mechanical Vibration
Solderability
Gross and Fine Leak
Resistance to Solder Heat
Contact Pads
Rev. 1.2
9
Si516
Table 10. Thermal Characteristics
Parameter
Symbol
Test Condition
Still air
Value
110
Unit
°C/W
°C/W
CLCC, Thermal Resistance Junction to Ambient
JA
2.5x3.2mm, Thermal Resistance Junction to Ambient
Still air
164
JA
Table 11. Absolute Maximum Ratings1
Parameter
Symbol
Rating
Unit
°
Maximum Operating Temperature
Storage Temperature
T
85
C
AMAX
°
T
–55 to +125
–0.5 to +3.8
C
S
Supply Voltage
V
V
V
DD
Input Voltage (any input pin)
ESD Sensitivity (HBM, per JESD22-A114)
V
–0.5 to V + 0.3
I
DD
HBM
2
kV
2
°
Soldering Temperature (Pb-free profile)
T
260
C
PEAK
2
Soldering Temperature Time at T
(Pb-free profile)
T
20–40
sec
PEAK
P
Notes:
1. Stresses beyond those listed in this table may cause permanent damage to the device. Functional operation or
specification compliance is not implied at these conditions. Exposure to maximum rating conditions for extended
periods may affect device reliability.
2. The device is compliant with JEDEC J-STD-020E.
10
Rev. 1.2
Si516
2. Solder Reflow and Rework Requirements for 2.5x3.2 mm Packages
Reflow of Silicon Labs' components should be done in a manner consistent with the IPC/JEDEC J-STD-20E
standard. The temperature of the package is not to exceed the classification Temperature provided in the standard.
The part should not be within -5°C of the classification or peak reflow temperature (T
) for longer than 30
PEAK
seconds. Key to maintaining the integrity of the component is providing uniform heating and cooling of the part
during reflow and rework. Uniform heating is achieved through having a preheat soak and controlling the
temperature ramps in the process. J-STD-20E provides minimum and maximum temperatures and times for the
preheat/Soak step that need to be followed, even for rework. The entire assembly area should be heated during
rework. Hot air should be flowed from both the bottom of the board and the top of the component. Heating from the
top only will cause un-even heating of component and can lead to part integrity issues. Temperature Ramp-up rate
are not to exceed 3°C/second. Temperature ramp-down rates from peak to final temperature are not to exceed
6°C/second. Time from 25°C to peak temperature is not to exceed 8 min for Pb-free solders.
Rev. 1.2
11
Si516
3. Pin Descriptions
1
VDD
NC
1
2
3
VDD
6
5
4
6
5
4
Vc
FS
Vc
FS
2
3
CLK–
CLK+
CLK
GND
GND
CMOS Dual VCXO
LVPECL/LVDS/HCSL/Dual CMOS
Dual VCXO
Table 12. Si516 Pin Descriptions (CMOS)
Pin
1
Name
CMOS Function
Control Voltage Input.
V
C
2
FS
Frequency Select.
0 = First frequency selected.
1 = Second frequency selected.
3
4
5
6
GND
CLK
NC
Electrical and Case Ground.
Clock Output.
No connect. Make no external connection to this pin.
Power Supply Voltage.
V
DD
Table 13. Si516 Pin Descriptions (LVPECL/LVDS/HCSL/Dual CMOS)
Pin
1
Name
LVPECL/LVDS/HCSL/Dual CMOS Function
Control Voltage Input.
V
C
2
FS
Frequency Select.
0 = First frequency selected.
1 = Second frequency selected.
3
4
5
6
GND
CLK+
CLK–
Electrical and Case Ground.
Clock Output.
Complementary Clock Output.
Power Supply Voltage.
V
DD
12
Rev. 1.2
Si516
3.1. Dual CMOS Buffer
Dual CMOS output format ordering options support either complementary or in-phase output signals. This feature
enables replacement of multiple VCXOs with a single Si516 device.
~
Complementary
Outputs
~
In-Phase
Outputs
Figure 1. Integrated 1:2 CMOS Buffer Supports Complementary or In-Phase Output
Rev. 1.2
13
Si516
4. Ordering Information
The Si516 supports a variety of options including frequency, minimum absolute pull range (APR), tuning slope,
output format, and V . Specific device configurations are programmed into the Si516 at time of shipment.
DD
Configurations are specified using the Part Number Configuration chart shown below. Silicon Labs provides a web
browser-based part number configuration utility to simplify this process. To access this tool refer to
www.silabs.com/oscillators and click “Customize” in the product table. The Si516 VCXO series is supplied in
industry-standard, RoHS compliant, lead-free, 2.5 x 3.2 mm, 3.2 x 5.0 mm, and 5 x 7 mm packages. Tape and reel
packaging is an ordering option.
6-digit Frequency Designator Code
Series
516
Dual Frequency VCXO
Output Format
LVPECL, LVDS, HCSL,
CMOS, Dual CMOS
Package
Code
Description
This 6-digit code represents a unique
combination of two frequencies. Frequencies
from 100 kHz to 250 MHz (differential) or 212.5
MHz (CMOS) are supported. For more info:
www.silabs.com/VCXOPartNumber.
xxxxxx
A = Revision: A
G = Temp Range: -40°C to 85°Cꢀ
R = Tape & Reel; Blank = &RLOꢀ7DSH
1st Option Code: Output Format
VDD
Output Format
A
B
C
D
E
F
3.3V
3.3V
3.3V
3.3V
2.5V
2.5V
2.5V
2.5V
3.3V
3.3V
2.5V
2.5V
LVPECL
LVDS
CMOS
HCSL
Package
Dimensionsꢀ
LVPECL
3rd Option Code*
Aꢀ 5 x 7 mm
LVDS
Bꢀ 3.2 x 5 mm
G
H
M
N
P
Q
CMOS
2nd Option Code: Absolute Pull Range (all ppm values)
ꢁꢂꢃꢀ[ꢀꢄꢂꢁꢀPP
&
HCSL
Minimum APR
Minimum APR
Temp
Stability
FS = 0
Kv
FS = 1
Kv
Dual CMOS (In-phase)
Dual CMOS (Complementary)
Dual CMOS (In-phase)
Dual CMOS (Complementary)
3.3 V
100ppm
100ppm
100ppm
100ppm
80ppm
80ppm
80ppm
50ppm
50ppm
30ppm
2.5 V
80ppm
80ppm
80ppm
80ppm
50ppm
50ppm
50ppm
30ppm
30ppm
N/S
3.3 V
100ppm
80ppm
50ppm
30ppm
80ppm
50ppm
30ppm
50ppm
30ppm
30ppm
2.5 V
A
B
C
D
E
F
20ppm
20ppm
20ppm
20ppm
20ppm
20ppm
20ppm
20ppm
20ppm
20ppm
150ppm/V
150ppm/V
150ppm/V
150ppm/V
120ppm/V
120ppm/V
120ppm/V
90ppm/V
90ppm/V
60ppm/V
150ppm/V
120ppm/V
90ppm/V
60ppm/V
120ppm/V
90ppm/V
60ppm/V
90ppm/V
60ppm/V
60ppm/V
80ppm
50ppm
30ppm
N/S
N/S = not supported
* 3rd Option Code:
Frequency Select Functionality
50ppm
30ppm
N/S
FS Functionality
G
H
J
(FS = 0 selects lower frequency)
A
30ppm
N/S
Frequencies in descending order
(FS = 0 selects higher frequency)
B
K
N/S
Figure 2. Part Number Convention
Example ordering part number: 516AAB000213AAG.
The series prefix, 516, indicates the device is a dual frequency VCXO.
The 1st option code A specifies the output format is LVPECL and powered from a 3.3 V supply. The Absolute Pull
Range code A indicates a temperature stability of ±20 ppm with a tuning slope of ±150 ppm/V. The 3rd option code
B specifies the frequencies are listed in descending order and FS = 0 selects the higher frequency.
The frequency code is 000213. Per this convention, and as indicated by the part number lookup utility at
www.silabs.com/VCXOpartnumber, the two output frequencies are 156.25 MHz and 125 MHz. The package code
A refers to the 5 x 7 mm footprint with six pins. The last A refers to the product revision, G indicates the
temperature range (–40 to +85 °C), and R specifies the device ships in tape and reel format.
14
Rev. 1.2
Si516
5. Package Outline Diagram: 5 x 7 mm, 6-pin
Figure 3 illustrates the package details for the Si516. Table 14 lists the values for the dimensions shown in the
illustration.
Figure 3. Si516 Outline Diagram
Table 14. Package Diagram Dimensions (mm)
Dimension
Min
Nom
Max
A
1.50
1.65
1.80
b
c
1.30
0.50
1.40
0.60
1.50
0.70
D
5.00 BSC
4.40
D1
e
4.30
4.50
2.54 BSC
7.00 BSC
6.20
E
E1
H
6.10
0.55
1.17
0.05
1.80
6.30
0.75
1.37
0.15
2.60
0.65
L
1.27
L1
p
0.10
—
R
0.70 REF
0.15
aaa
bbb
ccc
ddd
eee
0.15
0.10
0.10
0.05
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
Rev. 1.2
15
Si516
6. PCB Land Pattern: 5 x 7 mm, 6-pin
Figure 4 illustrates the 5 x 7 mm PCB land pattern for the Si516. Table 15 lists the values for the dimensions shown
in the illustration.
Figure 4. Si516 PCB Land Pattern
Table 15. PCB Land Pattern Dimensions (mm)
Dimension
(mm)
4.20
2.54
1.55
1.95
C1
E
X1
Y1
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition
(LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Solder Mask Design
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Stencil Design
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to
assure good solder paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1.
Card Assembly
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small
Body Components.
16
Rev. 1.2
Si516
7. Package Outline Diagram: 3.2 x 5.0 mm, 6-pin
Figure illustrates the package details for the 3.2 x 5 mm Si516. Table 16 lists the values for the dimensions shown
in the illustration.
Figure 5. Si516 Outline Diagram
Table 16. Package Diagram Dimensions (mm)
Dimension
Min
1.06
0.54
0.35
Nom
1.17
Max
1.33
0.74
0.55
A
b
0.64
c
0.45
D
3.20 BSC
2.60
D1
e
2.55
2.65
1.27 BSC
5.00 BSC
4.40
E
E1
H
4.35
0.45
0.80
0.05
1.17
4.45
0.65
1.00
0.15
1.37
0.55
L
0.90
L1
p
0.10
1.27
R
0.32 REF
0.15
aaa
bbb
ccc
ddd
eee
0.15
0.10
0.10
0.05
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
Rev. 1.2
17
Si516
8. PCB Land Pattern: 3.2 x 5.0 mm, 6-pin
Figure 6 illustrates the recommended 3.2 x 5 mm PCB land pattern for the Si516. Table 17 lists the values for the
dimensions shown in the illustration.
Figure 6. Si516 PCB Land Pattern
Table 17. PCB Land Pattern Dimensions (mm)
Dimension
(mm)
2.60
1.27
0.80
1.70
C1
E
X1
Y1
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Solder Mask Design
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Stencil Design
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be
used to assure good solder paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1.
Card Assembly
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification
for Small Body Components.
18
Rev. 1.2
Si516
9. Package Outline Diagram: 2.5 x 3.2 mm, 6-pin
Figure 7 illustrates the package details for the 2.5 x 3.2 mm Si516. Table 18 lists the values for the dimensions
shown in the illustration.
Figure 7. Si516 Outline Diagram
Rev. 1.2
19
Si516
Table 18. Package Diagram Dimensions (mm)
Dimension
Min
Nom
—
Max
A
—
1.1
A1
A2
W
0.26 REF
0.7 REF
0.65
0.45
0.7
0.75
0.55
D
e
3.20 BSC
1.25 BSC
2.50 BSC
0.30 BSC
0.5
E
M
L
D1
E1
SE
aaa
bbb
ddd
2.5 BSC
1.65 BSC
0.825 BSC
0.1
0.2
0.08
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
20
Rev. 1.2
Si516
10. PCB Land Pattern: 2.5 x 3.2 mm, 6-pin
Figure 8 illustrates the 2.5 x 3.2 mm PCB land pattern for the Si516. Table 19 lists the values for the dimensions
shown in the illustration.
Figure 8. Si516 Recommended PCB Land Pattern
Table 19. PCB Land Pattern Dimensions (mm)
Dimension
(mm)
C1
1.9
E
2.50
0.70
1.05
X1
Y1
Notes:
General
3. All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
4. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Stencil Design
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be
used to assure good solder paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.
Card Assembly
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification
for Small Body Components.
Rev. 1.2
21
Si516
11. Top Marking
Use the part number configuration utility located at: www.silabs.com/VCXOPartNumber to cross-reference the
mark code to a specific device configuration.
11.1. Si516 Top Marking
6 C CC CC
T T T T T T
Y Y WW
11.2. Top Marking Explanation
Mark Method:
Laser
Line 1 Marking:
6 = Si516
6CCCCC
CCCCC = Mark Code
Line 2 Marking:
Line 3 Marking:
TTTTTT = Assembly Manufacturing Code TTTTTT
Pin 1 indicator.
Circle with 0.5 mm diameter;
left-justified
YY = Year.
YYWW
WW = Work week.
Characters correspond to the year and
work week of package assembly.
22
Rev. 1.2
Si516
REVISION HISTORY
Revision 1.2
June, 2018
Changed “Trays” to “Coil Tape” in Ordering Guide.
Revision 1.1
December, 2017
Added 2.5 x 3.2 mm package.
Revision 1.0
Updated Table 1 on page 3.
Updates to supply current typical and maximum values for CMOS, LVDS, LVPECL and HCSL.
CMOS frequency test condition corrected to 100 MHz.
Updates to OE VIH minimum and VIL maximum values.
Updated Table 3 on page 4.
Dual CMOS nominal frequency maximum added.
Disable time maximum values updated.
Enable time parameter added.
Updated Table 4 on page 5.
CMOS output rise / fall time typical and maximum values updated.
LVPECL/HCSL output rise / fall time maximum value updated.
LVPECL output swing maximum value updated.
LVDS output common mode typical and maximum values updated.
HCSL output swing maximum value updated.
Duty cycle minimum and maximum values tightened to 48/52%.
Updated Table 5 on page 6.
Phase jitter test condition, typical and maximum value updated.
Phase noise typical values updated.
Additive RMS jitter due to external power supply noise typical values updated.
Added Tables 6, 7, 8 for LVDS, HCSL, CMOS and Dual CMOS operations.
Added note to Figure 2 clarifying CMOS and Dual CMOS maximum frequency.
Updated Figure outline diagram to correct pinout.
Updated “11. Top Marking” section and moved to page 22.
Rev. 1.2
23
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