530BB970M000GR [SILICON]
Oscillator;
| 型号： | 530BB970M000GR |
| 厂家： | 
SILICON |
| 描述： | Oscillator |
| 文件： | 总8页 (文件大小：165K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si530
PRELIMINARY DATA SHEET
CRYSTAL OSCILLATOR (XO)
(10 MHZ TO 1.4 GHZ)
Features
®
Available with any-rate output
frequencies from 10 MHz to 945 MHz
and selected frequencies to 1.4 GHz
Industry-standard 7x5 mm package
Available CMOS, LVPECL, LVDS,
and CML outputs
3rd generation DSPLL with
superior jitter performance
Internal fixed crystal frequency
ensures high reliability and low
aging
Si5602
Lead-free/RoHS-compliant
3x better frequency stability than
SAW-based oscillators
Applications
Test and measurement equipment
xDSL
10 GbE LAN/WAN
Low-jitter clock generation
Industrial electronics
Clock and data recovery
Ordering Information:
See page 7.
Description
®
The Si530 XO utilizes Silicon Laboratories advanced DSPLL circuitry to
provide a low jitter clock at high frequencies. The Si530 is available with
any-rate output frequency from 10 to 945 MHz and selected frequencies to
1400 MHz. Unlike a traditional XO, the crystal frequency inside the Si530 is
fixed for a wide range of output frequencies. This IC based approach allows
the crystal resonator to be optimized for superior frequency stability,
reliability and mechanical integrity. In addition, DSPLL clock synthesis
provides superior supply noise rejection, simplifying the task of generating
low jitter clocks in noisy environments typically found in communication
systems. The Si530 IC based XO is factory configurable for a wide variety of
user specifications including frequency, supply voltage and output format.
Specific configurations are factory programmed into the Si530 at time of
shipment, thereby eliminating the long lead times associated with custom
oscillators.
Functional Block Diagram
VDD
CLK– CLK+
Any-rate
10–1400 MHz
DSPLL®
Fixed
Frequency
XO
Clock
Synthesis
OE
GND
Copyright © 2005 by Silicon Laboratories
Preliminary Rev. 0.2 8/05
Si530
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si530
1. Electrical Specifications
Table 1. Si530 Electrical Specifications
Parameter
Min
Typ
Max
Units
Notes
Frequency
Nominal Frequency
Specified at time of order by
10
10
—
—
945
160
P/N. Also available in bands from 970
to 1134 MHz and 1213 to 1417 MHz.
MHz
LVDS/CML/LVPECL
CMOS
Initial Accuracy
Measured at +25 °C at time of
shipping.
–1.5
—
+1.5
ppm
ppm
ppm
–20
–50
—
—
+20
+50
Option specified at time of order by
P/N.
Temperature Stability
Aging
Frequency drift over projected 15 year
life.
—
—
—
±10
Outputs
Measured at:
LVPECL: VDD – 1.3 V (differential)
Symmetry
45
55
%
LVDS:
CMOS:
1.25 V (differential)
VDD/2
RMS Jitter for F
> 500 MHz
F
> 500 MHz
OUT
OUT
12 kHz to 20 MHz
50 kHz to 80 MHz
—
—
0.27
0.30
—
—
ps Differential Modes:
LVPECL/LVDS/CML
RMS Jitter for F
500 MHz
of 125 to
125 < F
Differential Modes:
< 500 MHz
OUT
OUT
12 kHz to 20 MHz
—
0.5
—
ps LVPECL/LVDS/CML
Period Jitter for F
Peak-to-Peak
RMS
<160 MHz
Any output
ps N = 1000 cycles
OUT
—
—
5
1
—
—
LVPECL Output Option
mid-level
swing (diff)
V
DD – 1.42
1.1
—
—
—
VDD – 1.25
1.9
V
VPP
VPP
50 Ω to VDD – 2.0 V
0.5
0.93
swing (single-ended)
LVDS Output Option
mid-level
swing (diff)
1.125
0.5
1.2
0.7
1.275
0.9
V
VPP
Rterm = 100 Ω (differential)
Rterm = 100 Ω (differential)
CML Output Option
—
0.35
VDD – 0.36
0.425
—
0.5
V
VPP
mid-level
swing
2
Preliminary Rev. 0.2
Si530
Table 1. Si530 Electrical Specifications (Continued)
Parameter
Min
Typ
Max
Units
Notes
CMOS Output Option
0.8xVDD
—
—
—
VDD
0.4
V
CL = 15 pF
V
VOL
OH
—
—
—
—
—
—
350
2
8
ps CML/LVPECL/LVDS at 20%/80%
Rise/Fall time
ns
ns
CMOS with V = 1.8 V & CL = 15 pF
DD
CMOS with V = 3.3 V & CL = 15 pF
DD
Inputs
Voltage (VDD
)
2.97
2.25
1.71
3.3
2.5
1.8
3.63
2.75
1.89
3.3 V option
2.5 V option
1.8 V option
V
Optional parameter specified by P/N
Current
—
—
90
60
—
—
mA
V
Output enabled
TriState mode
Output Enable
VIH
VIL
0.75xVDD
—
—
—
VDD
0.5
Table 2. Absolute Maximum Ratings
Parameter
Supply Voltage (V
Symbol
Rating
Units
)
V
–0.5 to +3.8
–55 to +125
V
DD
DD
Storage Temperature
T
°C
S
Table 3. Environmental Conditions
Parameter
Conditions/Test Method
Operating Temperature
Mechanical Shock
Mechanical Vibration
Solderability
–40 to +85 °C
MIL-STD-883F, Method 2002.3 B
MIL-STD-883F, Method 2007.3 A
MIL-STD-883F, Method 203.8
MIL-STD-883F, Method 1014.7
MIL-STD-883F, Method 2016
Gross & Fine Leak
Resistance to Solvents
Preliminary Rev. 0.2
3
Si530
Table 4. Pinout
Pin
Symbol
LVDS/LVPECL/CML Function
CMOS Function
Tri-state output enable
Disabled = logic “0”
Enable = logic “1”
1
OE (CMOS only)
No connection
Tri-state output enable
Disabled = logic “0”
Enable = logic “1”
2
OE (LVPECL,LVDS,CML)
No connection
3
4
5
6
GND
CLK+
CLK–
Electrical and Case Ground
Oscillator Output
Electrical and Case Ground
Oscillator Output
Complementary output
Power Supply Voltage
No connection
V
Power Supply Voltage
DD
4
Preliminary Rev. 0.2
Si530
2. Outline Diagram and Suggested Pad Layout
Figure 1 illustrates the package details for the Si530. Table 5 lists the values for the dimensions shown in the
illustration.
Figure 1. Si530 Outline Diagram
Table 5. Package Diagram Dimensions (mm)
Dimension
Min
1.45
1.2
Nom
1.65
Max
1.85
1.6
A
b
1.4
c
0.60 TYP.
7.00 BSC.
6.2
D
D1
e
6.10
6.30
2.54 BSC.
5.00 BSC.
4.40
E
E1
L
4.30
1.07
4.50
1.47
1.27
S
1.815 BSC.
0.7 REF.
—
R
aaa
bbb
ccc
ddd
—
—
—
—
0.15
0.15
0.10
0.10
—
—
—
Preliminary Rev. 0.2
5
Si530
3. 6-Pin PCB Land Pattern
Figure 2 illustrates the 6-pin PCB land pattern for the Si530. Table 6 lists the values for the dimensions shown in
the illustration.
Figure 2. Si530 PCB Land Pattern
Table 6. PCB Land Pattern Dimensions (mm)
Dimension
Min
Max
D2
e
5.08 REF
2.54 BSC
4.15 REF
E2
GD
GE
VD
VE
X
0.84
2.00
—
—
8.20 REF
7.30 REF
1.70 TYP
2.15 REF
Y
ZD
ZE
—
—
6.78
6.30
Notes:
1. Dimensioning and tolerancing per the ANSI Y14.5M-1994 specification.
2. Land pattern design based on IPC-7351 guidelines.
3. All dimensions shown are at maximum material condition (MMC).
4. Controlling dimension is in millimeters (mm).
6
Preliminary Rev. 0.2
Si530
4. Ordering Information
The Si530 XO was designed to support a variety of options including frequency, output format, and V . Specific
DD
device configurations are programmed into the Si530 at time of shipment. Configurations can be specified using
the part number configuration chart below. The Si530 XO series is supplied in an industry-standard 6-pad, 7x5 mm
package.
Part numbers for the Si530 XO are determined by following configuration tables. Silicon Labs provides a Windows-
based part number configuration tool to simplify this process. Refer to www.silabs.com/VCXO to access this tool
and for further ordering instructions.
X
530
XXXMXXX
G
R
X
B
Tape & Reel Packaging
530 XO Product
Family
Operating Temp Range (°C)
-40 to +85°C
G
Part Revision Letter
Frequency
(e.g., 622M080 is 622.080 MHz)
1st Option Code
2nd Option Code
VDD Output Format
Temp Stability (ppm, max, ±)
A
B
50
20
A
B
C
D
E
F
G
H
J
3.3 LVPECL
3.3 LVDS
3.3 CMOS
3.3 CML
2.5 LVPECL
2.5 LVDS
2.5 CMOS
2.5 CML
1.8 CMOS
1.8 CML
K
Notes:
CMOS available to 160 MHz.
Example P/N: 530AB622M080BGR is a 7x5 XO in a 6 pad package. The frequency is 622.080 MHz, with a 3.3 V supply and PECL output.
Stability is specifed as ± 20 ppm. The part is specified for -40 to +85 °C operation and will be shipped in tape and reel format.
Preliminary Rev. 0.2
7
Si530
CONTACT INFORMATION
Silicon Laboratories Inc.
4635 Boston Lane
Austin, TX 78735
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Email: VCXOinfo@silabs.com
Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-
sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap-
plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
8
Preliminary Rev. 0.2
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