531AB622M080BGR [SILICON]
CRYSTAL OSCILLATOR (XO) (10 MHZ TO 1.4 GHZ); 晶体振荡器( XO ) ( 10 MHz至1.4 GHz)的型号: | 531AB622M080BGR |
厂家: | SILICON |
描述: | CRYSTAL OSCILLATOR (XO) (10 MHZ TO 1.4 GHZ) |
文件: | 总10页 (文件大小:184K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Si530/531
PRELIMINARY DATA SHEET
CRYSTAL OSCILLATOR (XO)
(10 MHZ TO 1.4 GHZ)
Features
Si5602
Available with any-rate output
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
®
3rd generation DSPLL with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Pb-free/RoHS-compliant
Ordering Information:
Applications
See page 6.
SONET/SDH
Networking
SD/HD video
Clock and data recovery
FPGA/ASIC clock generation
Pin Assignments:
See page 5.
Description
(Top View)
®
The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry
to provide a low jitter clock at high frequencies. The Si530/531 is available
with any-rate output frequency from 10 to 945 MHz and select frequencies to
1400 MHz. Unlike a traditional XO, where a different crystal is required for
each output frequency, the Si530/531 uses one fixed crystal to provide a
wide range of output frequencies. This IC based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In addition,
DSPLL clock synthesis provides superior supply noise rejection, simplifying
the task of generating low jitter clocks in noisy environments typically found in
communication systems. The Si530/531 IC based XO is factory configurable
for a wide variety of user specifications including frequency, supply voltage,
output format, and temperature stability. Specific configurations are factory
programmed at time of shipment, thereby eliminating long lead times
associated with custom oscillators.
VDD
1
2
3
6
5
4
NC
OE
CLK–
CLK+
GND
Si530 (LVDS/LVPECL/CML)
VDD
1
2
3
6
5
4
OE
NC
NC
Functional Block Diagram
GND
CLK+
VDD
CLK– CLK+
Si530 (CMOS)
VDD
1
2
3
6
5
4
OE
NC
Any-rate
10–1400 MHz
DSPLL®
Clock
Synthesis
Fixed
Frequency
XO
CLK–
CLK+
GND
Si531 (LVDS/LVPECL/CML)
OE
GND
Preliminary Rev. 0.4 5/06
Copyright © 2006 by Silicon Laboratories
Si530/531
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si530/531
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol
Test Condition
3.3 V option
Min
2.97
2.25
1.71
—
Typ
3.3
2.5
1.8
90
Max
3.63
2.75
1.89
—
Units
1
V
DD
Supply Voltage
2.5 V option
V
1.8 V option
Supply Current
I
Output enabled
TriState mode
DD
mA
—
60
—
2
Output Enable (OE)
V
0.75 x V
—
—
—
IH
DD
V
V
—
0.5
85
IL
Operating Temperature Range
T
–40
—
ºC
A
Notes:
1. Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 6 for further details.
2. OE pin includes a 17 kΩ pullup resistor to VDD. Pulling OE to ground causes outputs to tristate.
Table 2. CLK± Output Frequency Characteristics
Parameter
Symbol
Test Condition
LVPECL/LVDS/CML
CMOS
Min
10
Typ
—
Max
945
160
Units
Nominal Frequency1,2
O
f
MHz
10
—
Initial Accuracy
Measured at +25 °C at
time of shipping
fi
—
±1.5
—
ppm
ppm
∆f/f
–20
–50
—
—
+20
+50
Temperature Stability1,3
Aging
O
Frequency drift over
projected 15 year life
fa
—
—
—
—
±10
10
ppm
ms
Powerup Time4
tOSC
Notes:
1. See Section 3. "Ordering Information" on page 6 for further details.
2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz.
3. Selectable parameter specified by part number.
4. Time from powerup or tristate mode to fO.
2
Preliminary Rev. 0.4
Si530/531
Table 3. CLK± Output Levels and Symmetry
Parameter
Symbol
Test Condition
mid-level
Min
VDD – 1.42
1.1
Typ
—
Max
VDD – 1.25
1.9
Units
V
1
LVPECL Output Option
V
O
VOD
VSE
swing (diff)
VPP
VPP
V
—
swing (single-ended)
mid-level
0.5
0.93
1.275
0.50
—
—
2
LVDS Output Option
V
1.125
0.32
—
1.20
0.40
O
swing (diff)
VOD
VO
VPP
V
2
CML Output Option
mid-level
V
– 0.75
DD
VOD
VOH
VOL
swing (diff)
0.70
0.8 x VDD
—
0.95
—
1.20
VDD
VPP
3
CMOS Output Option
I
= 32 mA
OH
V
IOL = 32 mA
—
0.4
Rise/Fall time (20/80%)
Symmetry (duty cycle)
tR, F
t
LVPECL/LVDS/CML
CMOS with CL = 15 pF
—
—
350
ps
ns
—
1
—
SYM
LVPECL:
LVDS:
V
– 1.3 V (diff)
DD
45
—
55
%
1.25 V (diff)
/2
CMOS:
V
DD
Notes:
1. 50 Ω to VDD – 2.0 V.
2. Rterm = 100 Ω (differential).
3. CL = 15 pF
Table 4. CLK± Output Phase Jitter
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Phase Jitter (RMS)*
φJ
φJ
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.27
0.30
—
—
ps
for F
> 500 MHz
OUT
Phase Jitter (RMS)*
for F of 125 to 500 MHz
12 kHz to 20 MHz (OC-48)
—
0.50
—
ps
OUT
*Note: Differential Modes: LVPECL/LVDS/CML. Refer to AN256 for further information.
Table 5. CLK± Output Period Jitter
Parameter
Period Jitter*
Symbol
Test Condition
RMS
Min
—
Typ
1
Max
—
Units
J
ps
PER
for F < 160 MHz
OUT
Peak-to-Peak
—
5
—
*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles.
Preliminary Rev. 0.4
3
Si530/531
Table 6. Absolute Maximum Ratings1
Parameter
Supply Voltage
Symbol
Rating
Units
Volts
Volts
ºC
V
–0.5 to +3.8
DD
Input Voltage (any input pin)
Storage Temperature
V
–0.5 to V + 0.3
I
DD
T
–55 to +125
>2500
260
S
ESD Sensitivity (HBM, per JESD22-A114)
ESD
Volts
ºC
2
Soldering Temperature (Pb-free profile)
T
PEAK
2
Soldering Temperature Time @ T
(Pb-free profile)
t
10
seconds
PEAK
P
Notes:
1. Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional
operation or specification compliance is not implied at these conditions.
2. Refer to Si5xx Packaging FAQ available for download at www.silabs.com/VCXO for further information, including
soldering profiles.
Table 7. Environmental Compliance
The Si530/531 meets the following qualification test requirements.
Parameter
Conditions/ Test Method
MIL-STD-883F, Method 2002.3 B
MIL-STD-883F, Method 2007.3 A
MIL-STD-883F, Method 203.8
MIL-STD-883F, Method 1014.7
MIL-STD-883F, Method 2016
Mechanical Shock
Mechanical Vibration
Solderability
Gross & Fine Leak
Resistance to Solvents
4
Preliminary Rev. 0.4
Si530/531
2. Pin Descriptions
(Top View)
VDD
VDD
VDD
6
1
2
3
6
5
4
1
2
3
6
5
4
1
2
3
OE
NC
NC
OE
OE
NC
5
NC
CLK–
CLK–
CLK+
GND
GND
4
GND
CLK+
CLK+
Si531
Si530
Si530
LVDS/LVPECL/CML
LVDS/LVPECL/CML
CMOS
Table 8. Pinout for Si530 Series
LVDS/LVPECL/CML Function
Pin
Symbol
OE (CMOS only)
OE
CMOS Function
Output enable
1
No connection
0 = clock output disabled (outputs tristated)
1 = clock output enabled
Output enable
2
(LVPECL,LVDS, 0 = clock output disabled (outputs tristated)
No connection
CML)
GND
CLK+
CLK–
1 = clock output enabled
Electrical and Case Ground
Oscillator Output
3
4
5
6
Electrical and Case Ground
Oscillator Output
Complementary output
Power Supply Voltage
No connection
V
Power Supply Voltage
DD
Table 9. Pinout for Si531 Series
Pin
Symbol
LVDS/LVPECL/CML Function
Output enable
1
OE (LVPECL, LVDS, CML)
0 = clock output disabled (outputs tristated)
1 = clock output enabled
2
3
4
5
6
No connection
GND
No connection
Electrical and Case Ground
Oscillator Output
CLK+
CLK–
Complementary output
Power Supply Voltage
V
DD
Preliminary Rev. 0.4
5
Si530/531
3. Ordering Information
The Si530/531 XO was designed to support a variety of options including frequency, temperature stability, output
format, and V . Specific device configurations are programmed into the Si530/531 at time of shipment.
DD
Configurations can be specified using the Part Number Configuration chart below. Silicon Laboratories provides a
web browser-based part number configuration utility to simplify this process. Refer to
www.silabs.com/VCXOPartNumber to access this tool and for further ordering instructions. The Si530 and Si531
XO series are supplied in an industry-standard, RoHS compliant, 6-pad, 5 x 7 mm package. The 531 Series
supports an alternate OE pinout (pin #1) for the LVPECL, LVDS, and CML output formats. See Tables 8 and 9 for
the pinout differences between the Si530 and Si531 series.
X
530
XXXMXXX
G
R
X
B
Tape & Reel Packaging
Blank = Trays
530 XO Product
Family
Operating Temp Range (°C)
-40 to +85°C
G
Part Revision Letter
Frequency (e.g., 622M080 is 622.080 MHz)
Available frequency range is 10 to 945 MHz, 970 to 1134 MHz, and
1213 to 1417 MHz. The position of “M” shifts to denote higher or
lower frequencies.
1st Option Code
2nd Option Code
VDD Output Format
Temp Stability (ppm, max, ±)
A
B
50
20
A
B
C
D
E
F
G
H
J
3.3 LVPECL
3.3 LVDS
3.3 CMOS
3.3 CML
2.5 LVPECL
2.5 LVDS
2.5 CMOS
2.5 CML
1.8 CMOS
1.8 CML
K
Notes:
CMOS available to 160 MHz.
Example P/N: 530AB622M080BGR is a 5 x 7 XO in a 6 pad package. The frequency is 622.080 MHz, with a 3.3 V supply and PECL output.
Temperature stability is specifed as ± 20 ppm. The part is specified for -40 to +85 °C ambient temperature range operation and is shipped in
tape and reel format.
Figure 1. Part Number Convention
6
Preliminary Rev. 0.4
Si530/531
4. Outline Diagram and Suggested Pad Layout
Figure 2 illustrates the package details for the Si530/531. Table 10 lists the values for the dimensions shown in the
illustration.
Figure 2. Si530/531 Outline Diagram
Table 10. Package Diagram Dimensions (mm)
Dimension
Min
1.45
1.2
Nom
1.65
Max
1.85
1.6
A
b
1.4
c
0.60 TYP.
7.00 BSC.
6.2
D
D1
e
6.10
6.30
2.54 BSC.
5.00 BSC.
4.40
E
E1
L
4.30
1.07
4.50
1.47
1.27
S
1.815 BSC.
0.7 REF.
—
R
aaa
bbb
ccc
ddd
—
—
—
—
0.15
0.15
0.10
0.10
—
—
—
Preliminary Rev. 0.4
7
Si530/531
5. 6-Pin PCB Land Pattern
Figure 3 illustrates the 6-pin PCB land pattern for the Si530/531. Table 11 lists the values for the dimensions shown
in the illustration.
Figure 3. Si530/531 PCB Land Pattern
Table 11. PCB Land Pattern Dimensions (mm)
Dimension
Min
Max
D2
e
5.08 REF
2.54 BSC
4.15 REF
E2
GD
GE
VD
VE
X
0.84
2.00
—
—
8.20 REF
7.30 REF
1.70 TYP
2.15 REF
Y
ZD
ZE
—
—
6.78
6.30
Notes:
1. Dimensioning and tolerancing per the ANSI Y14.5M-1994 specification.
2. Land pattern design based on IPC-7351 guidelines.
3. All dimensions shown are at maximum material condition (MMC).
4. Controlling dimension is in millimeters (mm).
8
Preliminary Rev. 0.4
Si530/531
DOCUMENT CHANGE LIST
Revision 0.3 to Revision 0.4
Updated references from Si530 to Si530/531.
Added Table 9, “Pinout for Si531 Series,” on page 5.
Updated 3. "Ordering Information" on page 6 to add
the Si531 series.
Added Table 7, “Environmental Compliance,” on
page 4.
Preliminary Rev. 0.4
9
Si530/531
CONTACT INFORMATION
Silicon Laboratories Inc.
4635 Boston Lane
Austin, TX 78735
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Email: VCXOinfo@silabs.com
Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
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quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
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Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
10
Preliminary Rev. 0.4
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