532AA970M000BGR [SILICON]
Oscillator;
| 型号： | 532AA970M000BGR |
| 厂家： | 
SILICON |
| 描述： | Oscillator |
| 文件： | 总10页 (文件大小：201K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si532
PRELIMINARY DATA SHEET
CRYSTAL OSCILLATOR (XO)
(10 MHZ TO 1.4 GHZ)
Features
ꢀ
Available with any-rate output
ꢀ
Internal fixed crystal frequency
ensures high reliability and low
aging
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
ꢀ
ꢀ
Two selectable output frequencies ꢀ Available CMOS, LVPECL,
®
LVDS, and CML outputs
3rd generation DSPLL with superior
ꢀ
ꢀ
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
jitter performance
ꢀ
3x better frequency stability than
SAW-based oscillators
ꢀ
Pb-free/RoHS-compliant
Ordering Information:
Applications
See page 6.
ꢀ
ꢀ
ꢀ
SONET/SDH
Networking
SD/HD video
ꢀ
ꢀ
Clock and data recovery
FPGA/ASIC clock generation
Pin Assignments:
See page 5.
Description
(Top View)
The Si532 dual frequency XO utilizes Silicon Laboratories’ advanced
®
DSPLL circuitry to provide a low jitter clock at high frequencies. The Si532 is
VDD
1
2
3
6
5
4
FS
OE
available with any-rate output frequency from 10 to 945 MHz and select
frequencies to 1400 MHz. Unlike a traditional XO where a different crystal is
required for each output frequency, the Si532 uses one fixed crystal
frequency to provide a wide range of output frequencies. This IC based
approach allows the crystal resonator to provide exceptional frequency
stability and reliability. In addition, DSPLL clock synthesis provides superior
supply noise rejection, simplifying the task of generating low jitter clocks in
noisy environments typically found in communication systems. The Si532 IC
based XO is factory configurable for a wide variety of user specifications
including frequency, supply voltage, output format, and temperature stability.
Specific configurations are factory programmed at time of shipment, thereby
eliminating long lead times associated with custom oscillators.
CLK–
CLK+
GND
(LVDS/LVPECL/CML)
VDD
1
2
3
6
5
4
FS
OE
NC
Functional Block Diagram
GND
CLK
VDD
CLK– CLK+
(CMOS)
Any-rate
10–1400 MHz
DSPLL®
Fixed
Frequency
XO
Clock
Synthesis
FS
OE
GND
Preliminary Rev. 0.4 5/06
Copyright © 2006 by Silicon Laboratories
Si532
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si532
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol
Test Condition
3.3 V option
Min
2.97
2.25
1.71
—
Typ
3.3
2.5
1.8
90
Max
3.63
2.75
1.89
—
Units
1
V
DD
Supply Voltage
2.5 V option
V
1.8 V option
Supply Current
I
Output enabled
TriState mode
DD
mA
—
60
—
2
Output Enable (OE)
V
0.75 x V
—
—
—
IH
DD
V
V
—
0.5
85
IL
Operating Temperature Range
T
–40
—
ºC
A
Notes:
1. Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 6 for further details.
2. OE pin includes a 17 kΩ pullup resistor to VDD. Pulling OE to ground causes outputs to tristate.
Table 2. CLK± Output Frequency Characteristics
Parameter
Symbol
Test Condition
LVPECL/LVDS/CML
CMOS
Min
10
Typ
—
Max
945
160
Units
Nominal Frequency1,2
O
f
MHz
10
—
Initial Accuracy
Measured at +25 °C at
time of shipping
fi
—
±1.5
—
ppm
ppm
ppm
∆f/f
–20
–50
—
—
+20
+50
Temperature Stability1,3
Aging
O
Frequency drift over
projected 15 year life
fa
—
—
±10
Powerup Time4
tOSC
tFRQ
—
—
—
—
10
10
ms
ms
Settling Time After FS Change
Notes:
1. See Section 3. "Ordering Information" on page 6 for further details.
2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz.
3. Selectable parameter specified by part number.
4. Time from powerup or tristate mode to fO.
2
Preliminary Rev. 0.4
Si532
Table 3. CLK± Output Levels and Symmetry
Parameter
Symbol
Test Condition
mid-level
Min
VDD – 1.42
1.1
Typ
—
Max
Units
V
1
VDD – 1.25
1.9
LVPECL Output Option
V
O
VOD
VSE
swing (diff)
VPP
VPP
V
—
swing (single-ended)
mid-level
0.5
0.93
1.275
0.50
—
—
2
LVDS Output Option
V
1.125
0.32
—
1.20
0.40
O
swing (diff)
VOD
VO
VPP
V
2
CML Output Option
mid-level
V
– 0.75
DD
VOD
VOH
VOL
swing (diff)
0.70
0.8 x VDD
—
0.95
—
1.20
VDD
0.4
VPP
3
CMOS Output Option
I
= 32 mA
OH
V
IOL = 32 mA
—
Rise/Fall time (20/80%)
Symmetry (duty cycle)
tR, F
t
LVPECL/LVDS/CML
CMOS with CL = 15 pF
—
—
350
ps
ns
—
1
—
SYM
LVPECL:
LVDS:
V
– 1.3 V (diff)
DD
45
—
55
%
1.25 V (diff)
/2
CMOS:
V
DD
Notes:
1. 50 Ω to VDD – 2.0 V.
2. Rterm = 100 Ω (differential).
3. CL = 15 pF
Table 4. CLK± Output Phase Jitter
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Phase Jitter (RMS)*
φJ
φJ
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.27
0.30
—
—
ps
for F
> 500 MHz
OUT
Phase Jitter (RMS)*
for F of 125 to 500 MHz
12 kHz to 20 MHz (OC-48)
—
0.50
—
ps
OUT
*Note: Differential Modes: LVPECL/LVDS/CML. Refer to AN256 for further information.
Table 5. CLK± Output Period Jitter
Parameter
Period Jitter*
Symbol
Test Condition
RMS
Min
—
Typ
1
Max
—
Units
J
ps
PER
for F < 160 MHz
OUT
Peak-to-Peak
—
5
—
*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles.
Preliminary Rev. 0.4
3
Si532
Table 6. CLK± Output Phase Noise (Typical)
Configuration
f
81.25 MHz
LVDS
312.5 MHz
LVPECL
1066 MHz
LVPECL
Units
C
Output
Offest Frequency (f)
L (f)
100 Hz
1 kHz
10 kHz
100 kHz
1 MHz
–110
–127
–134
–136
–143
–147
n/a
–100
–115
–119
–123
–135
–144
–147
–87
–102
–107
–111
–121
–135
–142
dBc/Hz
10 MHz
100 MHz
Table 7. Absolute Maximum Ratings1
Parameter
Supply Voltage
Symbol
Rating
–0.5 to +3.8
Units
V
Volts
Volts
ºC
DD
Input Voltage (any input pin)
Storage Temperature
V
–0.5 to V + 0.3
I
DD
T
–55 to +125
>2500
260
S
ESD Sensitivity (HBM, per JESD22-A114)
ESD
Volts
ºC
2
Soldering Temperature (Pb-free profile)
T
PEAK
2
Soldering Temperature Time @ T
(Pb-free profile)
t
10
seconds
PEAK
P
Notes:
1. Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional
operation or specification compliance is not implied at these conditions.
2. Refer to Si5xx Packaging FAQ available for download at www.silabs.com/VCXO for further information, including
soldering profiles.
Table 8. Environmental Compliance
The Si532 meets the following qualification test requirements.
Parameter
Conditions/ Test Method
MIL-STD-883F, Method 2002.3 B
MIL-STD-883F, Method 2007.3 A
MIL-STD-883F, Method 203.8
MIL-STD-883F, Method 1014.7
MIL-STD-883F, Method 2016
Mechanical Shock
Mechanical Vibration
Solderability
Gross & Fine Leak
Resistance to Solvents
4
Preliminary Rev. 0.4
Si532
2. Pin Descriptions
(Top View)
VDD
VDD
1
2
3
6
5
4
1
6
5
4
FS
OE
FS
OE
2
3
NC
CLK–
CLK+
GND
GND
CLK
LVDS/LVPECL/CML
CMOS
Table 9. Pin Descriptions
Pin
Symbol
LVDS/LVPECL/CML Function
CMOS Function
Frequency Select
Frequency Select
1
FS*
0 = First frequency selected
1 = Second frequency selected
0 = First frequency selected
1 = Second frequency selected
Output enable
Output enable
2
OE*
0 = clock output disabled (outputs tristated) 0 = clock output disabled (outputs tristated)
1 = clock output enabled
Electrical and Case Ground
Oscillator Output
1 = clock output enabled
Electrical and Case Ground
Oscillator Output
3
4
5
6
GND
CLK+
CLK–
Complementary output
Power Supply Voltage
No connection
V
Power Supply Voltage
DD
*Note: FS and OE include a 17 kΩ pullup resistor to VDD. See Section 3. “Ordering Information” for details on frequency value
ordering.
Preliminary Rev. 0.4
5
Si532
3. Ordering Information
The Si532 XO was designed to support a variety of options including frequency, temperature stability, output
format, and V . Specific device configurations are programmed into the Si532 at time of shipment. Configurations
DD
can be specified using the Part Number Configuration chart below. Silicon Laboratories provides a web browser-
based part number configuration utility to simplify this process. Refer to www.silabs.com/VCXOPartNumber to
access this tool and for further ordering instructions. The Si532 is supplied in an industry-standard, RoHS
compliant, 6-pad, 5 x 7 mm package.
X
X
B
G
R
532
XXXXXX
R = Tape & Reel
Blank = Trays
532 Dual XO
Product Family
Operating Temp Range (°C)
–40 to +85 °C
G
Device Revision Letter
6-digit Frequency Designator Code
1st Option Code
Two unique frequencies can be specified within the following bands of frequencies: 10 to
945 MHz, 970 to 1134 MHz, and 1213 to 1417 MHz. A six digit code will be assigned for
the specified combination of frequencies. Codes > 000100 refer to dual XOs programmed
with the lower frequency value selected when FS = 0, and the higher value when FS = 1.
Six digit codes < 000100 refer to dual XOs programmed with the higher frequency value
selected when FS = 0, and the lower value when FS = 1.
Code
A
B
C
D
E
F
G
H
J
VDD
3.3
Output Format
LVPECL
LVDS
CMOS
CML
3.3
3.3
3.3
2.5
2.5
2.5
2.5
1.8
1.8
LVPECL
LVDS
CMOS
CML
2nd Option Code
CMOS
CML
Code Temperature Stability (ppm, max, ±)
K
A
B
50
20
Note:
CMOS available to 160 MHz.
Example Part Number: 532AB000108BGR is a 5 x 7 mm Dual XO in a 6 pad package. Since the six digit code (000108) is > 000100,
f0 is 644.53125 MHz (lower frequency) and f1 is 693.48299 (higher frequency), with a 3.3 V supply and LVPECL output. Temperature
stability is specified as ± 20 ppm. The part is specified for a -40 to +85 C° ambient temperature range operation and is shipped in tape
and reel format.
Figure 1. Part Number Convention
6
Preliminary Rev. 0.4
Si532
4. Outline Diagram and Suggested Pad Layout
Figure 2 illustrates the package details for the Si532. Table 10 lists the values for the dimensions shown in the
illustration.
Figure 2. Si532 Outline Diagram
Table 10. Package Diagram Dimensions (mm)
Dimension
Min
1.45
1.2
Nom
1.65
Max
1.85
1.6
A
b
1.4
c
0.60 TYP
7.00 BSC
6.2
D
D1
e
6.10
6.30
2.54 BSC
5.00 BSC
4.40
E
E1
L
4.30
1.07
4.50
1.47
1.27
S
1.815 BSC
0.7 REF
—
R
aaa
bbb
ccc
ddd
—
—
—
—
0.15
0.15
0.10
0.10
—
—
—
Preliminary Rev. 0.4
7
Si532
5. 6-Pin PCB Land Pattern
Figure 3 illustrates the 6-pin PCB land pattern for the Si532. Table 11 lists the values for the dimensions shown in
the illustration.
Figure 3. Si532 PCB Land Pattern
Table 11. PCB Land Pattern Dimensions (mm)
Dimension
Min
Max
D2
e
5.08 REF
2.54 BSC
4.15 REF
E2
GD
GE
VD
VE
X
0.84
2.00
—
—
8.20 REF
7.30 REF
1.70 TYP
2.15 REF
Y
ZD
ZE
—
—
6.78
6.30
Notes:
1. Dimensioning and tolerancing per the ANSI Y14.5M-1994 specification.
2. Land pattern design based on IPC-7351 guidelines.
3. All dimensions shown are at maximum material condition (MMC).
4. Controlling dimension is in millimeters (mm).
8
Preliminary Rev. 0.4
Si532
DOCUMENT CHANGE LIST
Revision 0.3 to Revision 0.4
ꢀ Updated 1. "Electrical Specifications" on page 2.
ꢁ Updated ordering and format of Tables 1–9.
ꢁ Updated LVDS and CML in Table 3, “CLK± Output
Levels and Symmetry,” on page 3.
ꢀ Added Table 6, “CLK± Output Phase Noise
(Typical),” on page 4.
Preliminary Rev. 0.4
9
Si532
CONTACT INFORMATION
Silicon Laboratories Inc.
4635 Boston Lane
Austin, TX 78735
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Email: VCXOinfo@silabs.com
Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-
sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap-
plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
10
Preliminary Rev. 0.4
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