532MA000105DGR [SILICON]
LVPECL Output Clock Oscillator,;
| 型号： | 532MA000105DGR |
| 厂家： | 
SILICON |
| 描述： | LVPECL Output Clock Oscillator, 振荡器 |
| 文件： | 总12页 (文件大小：464K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si532
REVISION D
DUAL FREQUENCY CRYSTAL OSCILLATOR (XO)
(10 MHZ TO 1.4 GHZ)
Features
Available with any-frequency output
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
Two selectable output frequencies
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
rd
®
3
generation DSPLL with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Pb-free/RoHS-compliant
Ordering Information:
Applications
See page 7.
SONET/SDH
Networking
SD/HD video
Test and measurement
Clock and data recovery
FPGA/ASIC clock generation
Pin Assignments:
See page 6.
Description
(Top View)
The Si532 dual frequency XO utilizes Silicon Laboratories’ advanced
®
DSPLL circuitry to provide a low jitter clock at high frequencies. The Si532 is
VDD
1
2
3
6
5
4
FS
OE
available with any-frequency output frequency from 10 to 945 MHz and select
frequencies to 1400 MHz. Unlike a traditional XO where a different crystal is
required for each output frequency, the Si532 uses one fixed crystal
frequency to provide a wide range of output frequencies. This IC based
approach allows the crystal resonator to provide exceptional frequency
stability and reliability. In addition, DSPLL clock synthesis provides superior
supply noise rejection, simplifying the task of generating low jitter clocks in
noisy environments typically found in communication systems. The Si532 IC
based XO is factory configurable for a wide variety of user specifications
including frequency, supply voltage, output format, and temperature stability.
Specific configurations are factory programmed at time of shipment, thereby
eliminating long lead times associated with custom oscillators.
CLK–
CLK+
GND
(LVDS/LVPECL/CML)
VDD
1
2
3
6
5
4
FS
OE
NC
Functional Block Diagram
GND
CLK
VDD
CLK– CLK+
(CMOS)
Any-frequency
10–1400 MHz
DSPLL®
Fixed
Frequency
XO
Clock
Synthesis
FS
OE
GND
Rev. 1.4 6/18
Copyright © 2018 by Silicon Laboratories
Si532
Si532
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol
Test Condition
3.3 V option
2.5 V option
1.8 V option
Min
2.97
2.25
1.71
Typ
3.3
2.5
1.8
Max
3.63
2.75
1.89
Units
1
V
V
V
V
Supply Voltage
DD
Supply Current
I
Output enabled
LVPECL
CML
DD
—
—
—
—
121
108
98
111
99
90
81
mA
LVDS
CMOS
88
Tristate mode
—
0.75 x V
—
60
—
—
—
75
—
mA
V
Output Enable (OE)
V
IH
DD
and Frequency Select (FS)2
V
0.5
85
V
IL
Operating Temperature Range
T
–40
ºC
A
Notes:
1. Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 7 for further details.
2. OE and FS pins include a 17 k pullup resistor to VDD. Pulling OE to ground causes outputs to tristate.
Table 2. CLK± Output Frequency Characteristics
Parameter
Symbol
Test Condition
LVPECL/LVDS/CML
CMOS
Min
10
Typ
—
Max Units
Nominal Frequency1,2
O
f
945
160
MHz
MHz
10
—
Initial Accuracy
Measured at +25 °C at time of
shipping
fi
—
±1.5
—
ppm
ppm
Temperature Stability1,3
–7
–20
–50
—
—
—
+7
+20
+50
Aging
Frequency drift over first year
Frequency drift over 20 year life
Temp stability = ±7 ppm
—
—
—
—
—
—
—
—
—
—
±3
ppm
ppm
ppm
ppm
ppm
fa
±10
Total Stability
±20
Temp stability = ±20 ppm
Temp stability = ±50 ppm
±31.5
±61.5
Notes:
1. See Section 3. "Ordering Information" on page 7 for further details.
2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz.
3. Selectable parameter specified by part number.
4. Time from powerup or tristate mode to fO.
2
Rev. 1.4
Si532
Table 2. CLK± Output Frequency Characteristics (Continued)
Parameter
Powerup Time4
Symbol
tOSC
Test Condition
Min
—
Typ
—
Max Units
10
10
ms
ms
Settling Time After FS Change
tFRQ
—
—
Notes:
1. See Section 3. "Ordering Information" on page 7 for further details.
2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz.
3. Selectable parameter specified by part number.
4. Time from powerup or tristate mode to fO.
Table 3. CLK± Output Levels and Symmetry
Parameter
Symbol
Test Condition
mid-level
Min
VDD – 1.42
1.1
Typ
—
Max
VDD – 1.25
1.9
Units
V
LVPECL Output Option1
V
O
VOD
VSE
swing (diff)
VPP
VPP
—
swing (single-ended)
mid-level
0.55
—
0.95
LVDS Output Option2
CML Output Option2
V
1.125
1.20
1.275
V
O
swing (diff)
VOD
VO
0.5
—
0.7
0.9
—
VPP
V
2.5/3.3 V option mid-level
1.8 V option mid-level
V
V
– 1.30
DD
—
– 0.36
—
V
DD
2.5/3.3 V option swing (diff)
1.8 V option swing (diff)
1.10
0.35
0.8 x VDD
—
1.50
1.90
0.50
VDD
0.4
350
—
VPP
VPP
V
VOD
0.425
—
CMOS Output Option3
Rise/Fall time (20/80%)
Symmetry (duty cycle)
VOH
VOL
I
= 32 mA
OH
IOL = 32 mA
—
tR, F
t
LVPECL/LVDS/CML
—
—
ps
ns
CMOS with C = 15 pF
—
1
L
SYM
LVPECL:
VDD – 1.3 V
(diff)
LVDS:
CMOS:
45
—
55
%
1.25 V (diff)
VDD/2
Notes:
1. 50 to VDD – 2.0 V.
2. Rterm = 100 (differential).
3. CL = 15 pF
Rev. 1.4
3
Si532
Table 4. CLK± Output Phase Jitter
Parameter
Phase Jitter (RMS)1
Symbol
Test Condition
Min
—
Typ
0.25
0.26
0.36
0.34
Max
0.40
0.37
0.50
0.42
Units
ps
J
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
12 kHz to 20 MHz (OC-48)
for FOUT > 500 MHz
—
ps
Phase Jitter (RMS)1
for FOUT of 125 to 500 MHz
J
—
ps
2
50 kHz to 80 MHz (OC-192)
—
ps
Phase Jitter (RMS)1
for FOUT of 125 and 156.25 MHz Only
J
J
12 kHz to 20 MHz (Brickwall)
—
0.25
0.40
ps
2
Phase Jitter (RMS)
for FOUT of 10 to 160 MHz
CMOS Output Only
12 kHz to 20 MHz (OC-48)
—
—
0.62
0.61
—
—
ps
ps
2
50 kHz to 20 MHz
Notes:
1. Refer to AN256 for further information.
2. Max offset frequencies: 80 MHz for FOUT > 250 MHz, 20 MHz for 50 MHz < FOUT <250 MHz,
2 MHz for 10 MHz < FOUT <50 MHz.
Table 5. CLK± Output Period Jitter
Parameter
Period Jitter*
Symbol
Test Condition
RMS
Min
—
Typ
2
Max
—
Units
ps
J
PER
Peak-to-Peak
—
14
—
ps
*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information.
Table 6. CLK± Output Phase Noise (Typical)
Offset Frequency (f)
120.00 MHz
LVDS
156.25 MHz
LVPECL
622.08 MHz
LVPECL
Units
100 Hz
1 kHz
10 kHz
100 kHz
1 MHz
–112
–122
–132
–137
–144
–150
n/a
–105
–122
–128
–135
–144
–147
n/a
–97
–107
–116
–121
–134
–146
–148
dBc/Hz
10 MHz
100 MHz
4
Rev. 1.4
Si532
Table 7. Environmental Compliance
The Si532 meets the following qualification test requirements.
Parameter
Mechanical Shock
Conditions/Test Method
MIL-STD-883, Method 2002
MIL-STD-883, Method 2007
MIL-STD-883, Method 2003
MIL-STD-883, Method 1014
MIL-STD-883, Method 2036
J-STD_020, MSL1
Mechanical Vibration
Solderability
Gross & Fine Leak
Resistance to Solder Heat
Moisture Sensitivity Level
Contact Pads
Gold over Nickel
Table 8. Thermal Characteristics
(Typical values TA = 25 ºC, VDD = 3.3 V)
Parameter
Symbol
Test Condition
Still Air
Min
—
Typ
84.6
38.8
—
Max
Unit
°C/W
°C/W
°C
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Case
Ambient Temperature
—
—
JA
Still Air
—
JC
T
–40
—
85
A
Junction Temperature
T
—
125
°C
J
Table 9. Absolute Maximum Ratings1
Parameter
Maximum Operating Temperature
Supply Voltage, 1.8 V Option
Symbol
Rating
85
Units
T
ºC
AMAX
V
V
–0.5 to +1.9
–0.5 to +3.8
V
DD
DD
Supply Voltage, 2.5/3.3 V Option
Input Voltage (any input pin)
V
V
–0.5 to V + 0.3
V
ºC
I
DD
Storage Temperature
T
–55 to +125
2500
S
ESD Sensitivity (HBM, per JESD22-A114)
Soldering Temperature (Pb-free profile)2
ESD
V
T
260
ºC
PEAK
Soldering Temperature Time @ TPEAK (Pb-free profile)2
t
20–40
seconds
P
Notes:
1. Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional
operation or specification compliance is not implied at these conditions.
2. The device is compliant with JEDEC J-STD-020C. Refer to Si5xx Packaging FAQ available for download at
www.silabs.com/VCXO for further information, including soldering profiles.
Rev. 1.4
5
Si532
2. Pin Descriptions
(Top View)
VDD
VDD
1
2
3
6
5
4
1
6
5
4
FS
OE
FS
OE
2
3
NC
CLK–
CLK+
GND
GND
CLK
LVDS/LVPECL/CML
CMOS
Table 10. Pin Descriptions
Pin
Symbol
LVDS/LVPECL/CML Function
CMOS Function
Frequency Select
Frequency Select
1
FS*
0 = First frequency selected
1 = Second frequency selected
0 = First frequency selected
1 = Second frequency selected
Output enable
Output enable
2
OE*
0 = clock output disabled (outputs tristated) 0 = clock output disabled (outputs tristated)
1 = clock output enabled
Electrical and Case Ground
Oscillator Output
1 = clock output enabled
Electrical and Case Ground
Oscillator Output
3
4
5
6
GND
CLK+
CLK–
Complementary Output
Power Supply Voltage
No connection
V
Power Supply Voltage
DD
*Note: FS and OE include a 17 k pullup resistor to VDD. See Section 3. “Ordering Information” for details on frequency value
ordering.
6
Rev. 1.4
Si532
3. Ordering Information
The Si532 XO supports a variety of options including frequency, temperature stability, output format, and V
.
DD
Specific device configurations are programmed into the Si532 at time of shipment. Configurations can be specified
using the Part Number Configuration chart below. Silicon Laboratories provides a web browser-based part number
configuration utility to simplify this process. Refer to www.silabs.com/VCXOPartNumber to access this tool and for
further ordering instructions. The Si532 is supplied in an industry-standard, RoHS-compliant, 6-pad, 5 x 7 mm
package.
X
X
D
G
R
532
XXXXXX
R = Tape & Reel
Blank = Coil Tape
532 Dual XO
Product Family
Operating Temp Range (°C)
–40 to +85 °C
1st Option Code
VDD Output Format Output Enable Polarity
G
A
B
C
D
E
F
G
H
J
K
M
N
P
Q
R
S
T
3.3 LVPECL
3.3 LVDS
3.3 CMOS
3.3 CML
2.5 LVPECL
2.5 LVDS
2.5 CMOS
2.5 CML
1.8 CMOS
1.8 CML
3.3 LVPECL
3.3 LVDS
3.3 CMOS
3.3 CML
2.5 LVPECL
2.5 LVDS
2.5 CMOS
2.5 CML
1.8 CMOS
1.8 CML
High
High
High
High
High
High
High
High
High
High
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Device Revision Letter
6-digit Frequency Designator Code
Two unique frequencies can be specified within the following bands of
frequencies: 10 to 945 MHz, 970 to 1134 MHz, and 1213 to 1417 MHz. A
six digit code will be assigned for the specified combination of frequencies.
Codes > 000100 refer to dual XOs programmed with the lower frequency
value selected when FS = 0, and the higher value when FS = 1. Six digit
codes < 000100 refer to dual XOs programmed with the higher frequency
value selected when FS = 0, and the lower value when FS = 1.
2nd Option Code
Code Temperature Stability (ppm, max, ±) Total Stablility (ppm, max, ±)
U
V
W
A
B
C
50
20
7
61 .5
31 .5
20
Note:
CMOS available to 160 MHz.
Example Part Number: 532AB000108DGR is a 5 x 7 mm Dual XO in a 6 pad package. Since the six digit code (000108) is > 000100,
f0 is 644.53125 MHz (lower frequency) and f1 is 693.48299 (higher frequency), with a 3.3 V supply, LVPECL output, and Output
Enable active high polarity. Temperature stability is specified as ±20 ppm. The part is specified for a –40 to +85 C° ambient
temperature range operation and is shipped in tape and reel format.
Figure 1. Part Number Convention
Rev. 1.4
7
Si532
4. Outline Diagram and Suggested Pad Layout
Figure 2 illustrates the package details for the Si532. Table 11 lists the values for the dimensions shown in the
illustration.
Figure 2. Si532 Outline Diagram
Table 11. Package Diagram Dimensions (mm)
Dimension
Min
1.50
1.30
0.50
Nom
1.65
Max
1.80
1.50
0.70
A
b
1.40
c
0.60
D
5.00 BSC
4.40
D1
e
4.30
4.50
2.54 BSC
7.00 BSC
6.20
E
E1
H
6.10
0.55
1.17
1.80
6.30
0.75
1.37
2.60
0.65
L
1.27
p
—
R
0.70 REF
0.15
aaa
bbb
ccc
ddd
eee
0.15
0.10
0.10
0.05
8
Rev. 1.4
Si532
5. Si532 Mark Specification
Figure 3 illustrates the mark specification for the Si532. Table 12 lists the line information.
Figure 3. Mark Specification
Table 12. Si53x Top Mark Description
Line
Position
Description
1
1–10
“SiLabs 532”
2
3
1–10
Si532: Option1 + Option2 + ConfigNum(6) + Temp
Trace Code
Position 1
Pin 1 orientation mark (dot)
Product Revision (D)
Position 2
Position 3–6
Position 7
Tiny Trace Code (4 alphanumeric characters per assembly release instructions)
Year (least significant year digit), to be assigned by assembly site (ex: 2007 = 7)
Calendar Work Week number (1–53), to be assigned by assembly site
“+” to indicate Pb-Free and RoHS-compliant
Position 8–9
Position 10
Rev. 1.4
9
Si532
6. 6-Pin PCB Land Pattern
Figure 4 illustrates the 6-pin PCB land pattern for the Si532. Table 13 lists the values for the dimensions shown in
the illustration.
Figure 4. Si532 PCB Land Pattern
Table 13. PCB Land Pattern Dimensions (mm)
Dimension
Min
Max
D2
e
5.08 REF
2.54 BSC
4.15 REF
E2
GD
GE
VD
VE
X
0.84
2.00
—
—
8.20 REF
7.30 REF
1.70 TYP
2.15 REF
Y
ZD
ZE
—
—
6.78
6.30
Notes:
1. Dimensioning and tolerancing per the ANSI Y14.5M-1994 specification.
2. Land pattern design based on IPC-7351 guidelines.
3. All dimensions shown are at maximum material condition (MMC).
4. Controlling dimension is in millimeters (mm).
10
Rev. 1.4
Si532
Revision 1.3 to Revision 1.31
DOCUMENT CHANGE LIST
Revision 1.0 to Revision 1.1
May 2, 2016
Updated Table 4 to include 125 MHz and
Updated Table 1, “Recommended Operating
156.25 MHz jitter measurements.
Conditions,” on page 2.
Device maintains stable operation over –40 to +85 ºC
operating temperature range.
Revision 1.31 to Revision 1.4
June, 2018
Supply current specifications updated for revision D.
Changed “Trays” to “Coil Tape” in section
Updated Table 2, “CLK± Output Frequency
3. “Ordering Information”.
Characteristics,” on page 2.
Added specification for ±20 ppm lifetime stability
(±7 ppm temperature stability) XO.
Updated Table 3, “CLK± Output Levels and
Symmetry,” on page 3.
Updated LVDS differential peak-peak swing
specifications.
Updated Table 4, “CLK± Output Phase Jitter,” on
page 4.
Updated Table 5, “CLK± Output Period Jitter,” on
page 4.
Revised period jitter specifications.
1
Updated Table 9, “Absolute Maximum Ratings ,” on
page 5 to reflect the soldering temperature time at
260 ºC is 20–40 sec per JEDEC J-STD-020C.
Updated 3. "Ordering Information" on page 7.
Changed ordering instructions to revision D.
Added 5. "Si532 Mark Specification" on page 9.
Revision 1.1 to Revision 1.2
Updated 2.5 V/3.3 V and 1.8 V CML output level
specifications for Table 3 on page 3.
Added footnotes clarifying max offset frequency test
conditions for Table 4 on page 4.
Removed the words "Differential Modes:
LVPECL/LVDS/CML" in the footnote referring to
AN256 in Table 4 on page 4.
Added CMOS phase jitter specs to Table 4 on
page 4.
Updated Table 7 on page 5 to include the "Moisture
Sensitivity Level" and "Contact Pads" rows.
Revised Figure 2 on page 8 to reflect current
package outline diagram.
Updated Figure 3 and Table 12 on page 9 to reflect
specific marking information. Previously, Figure 3
was generic.
Revision 1.2 to Revision 1.3
Added Table 8, “Thermal Characteristics,” on
page 5.
Rev. 1.4
11
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