541FAB001022BAGR [SILICON]
CMOS Output Clock Oscillator,;
| 型号： | 541FAB001022BAGR |
| 厂家： | 
SILICON |
| 描述： | CMOS Output Clock Oscillator, 振荡器 |
| 文件： | 总16页 (文件大小：621K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
™
Ultra Series Crystal Oscillator
Si541 Data Sheet
Ultra Low Jitter Dual Any-Frequency XO (125 fs), 0.2 to 1500 MHz
The Si541 Ultra Series™ oscillator utilizes Silicon Laboratories’ advanced 4th gen-
eration DSPLL® technology to provide an ultra-low jitter, low phase noise clock at
two selectable frequencies. The device is factory-programmed to provide any two
selectable frequencies from 0.2 to 1500 MHz with <1 ppb resolution and maintains
exceptionally low jitter for both integer and fractional frequencies across its operat-
ing range. The Si541 offers excellent reliability and frequency stability as well as
guaranteed aging performance. On-chip power supply filtering provides industry-
leading power supply noise rejection, simplifying the task of generating low jitter
clocks in noisy systems that use switched-mode power supplies. Offered in indus-
try-standard 3.2x5 mm and 5x7 mm footprints, the Si541 has a dramatically simpli-
fied supply chain that enables Silicon Labs to ship custom frequency samples 1-2
weeks after receipt of order. Unlike a traditional XO, where a different crystal is re-
quired for each output frequency, the Si541 uses one simple crystal and a DSPLL
IC-based approach to provide the desired output frequencies. This process also
guarantees 100% electrical testing of every device. The Si541 is factory-configura-
ble for a wide variety of user specifications, including frequency, output format,
and OE pin location/polarity. Specific configurations are factory-programmed at
time of shipment, eliminating the long lead times associated with custom oscilla-
tors.
KEY FEATURES
• Available with any two selectable frequencies
from 0.2 MHz to 1500 MHz
• Very low jitter: 125 fs Typ RMS
(12 kHz – 20 MHz)
• Excellent PSRR and supply noise immunity:
–80 dBc Typ
• 7 ppm stability option (-40 to 85 C)
• 3.3 V, 2.5 V and 1.8 V V supply operation
DD
from the same part number
• LVPECL, LVDS, CML, HCSL, CMOS, and
Dual CMOS output options
• 3.2×5, 5x7 mm package footprints
• Any custom frequency available with 1-2
week lead times
APPLICATIONS
Pin Assignments
• 100G/200G/400G OTN, coherent optics
• 10G/40G/100G optical ethernet
1
2
3
6
5
4
VDD
CLK-
CLK+
OE/FS
FS/OE
GND
• 3G-SDI/12G-SDI/24G-SDI broadcast video
• Servers, switches, storage, NICs, search
acceleration
• Test and measurement
• Clock and data recovery
• FPGA/ASIC clocking
(Top View)
Fixed
Frequency
Crystal
Frequency
Flexible
DSPLL
Pin #
Descriptions
Low
Noise
Driver
1, 2
Selectable via ordering option
OE = Output enable; FS = Frequency Select
DCO
Digital
Phase
Detector
Digital
Phase Error
Loop
OSC
Cancellation
Filter
3
4
5
GND = Ground
Flexible
Formats,
1.8V – 3.3V
Phase Error
CLK+ = Clock output
Fractional
Operation
Divider
CLK- = Complementary clock output. Not used
for CMOS.
NVM
Control
Power Supply Regulation
6
VDD = Power supply
OE, Frequency Select
(Pin Control)
Built-in Power Supply
Noise Rejection
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Rev. 1.0
Si541 Data Sheet
Ordering Guide
1. Ordering Guide
The Si541 XO supports a variety of options including frequency, output format, and OE pin location/polarity, as shown in the chart
below. Specific device configurations are programmed into the part at time of shipment, and samples are available in 1-2 weeks. Silicon
Laboratories provides an online part number configuration utility to simplify this process. Refer to www.silabs.com/oscillators to access
this tool and for further ordering instructions.
Temp Stability Total Stability2
XO Series
Description
Package
5x7 mm
Temperature Grade
541
Dual Frequency
A
B
G
-40 to 85 °C
A
B
C
± 20 ppm
± 10 ppm
± 7 ppm
± 50 ppm
± 25 ppm
± 20 ppm
3.2x5 mm
541
A
A
A
-
-
-
-
-
-
A
B
G
R
Device Revision
OE
Pin
FS
Pin
Order
Option
OE Polarity
Signal Format
VDD Range
A
Pin 1 Active High Pin 2
Reel
LVPECL
LVDS
2.5, 3.3 V
A
B
C
D
E
B
Pin 1 Active Low Pin 2
R
Tape and Reel
Coil Tape
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
C Pin 2 Active High Pin 1
D Pin 2 Active Low Pin 1
<Blank>
CMOS
CML
Frequency Code3
Description
HCSL
Dual CMOS
(In-Phase)
Dual CMOS
1.8, 2.5, 3.3 V
F
Two unique frequencies can be specified
within the supported range of the selected
signal format. Either frequency can be
assigned to FS=0 or FS=1. A six digit numeric
code will be assigned for the specific
combination of frequencies.
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
G
H
(Complementary)
xxxxxx
1
Custom
Notes:
1. Contact Silicon Labs for non-standard configurations.
2. Total stability includes temp stability, initial accuracy, load pulling, VDD variation, and 20 year aging at 70 °C.
3. Create custom part numbers at www.silabs.com/oscillators.
1.1 Technical Support
Frequently Asked Questions (FAQ)
Oscillator Phase Noise Lookup Utility
Quality and Reliability
www.silabs.com/Si541-FAQ
www.silabs.com/oscillator-phase-noise-lookup
www.silabs.com/quality
Development Kits
www.silabs.com/oscillator-tools
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Rev. 1.0 | 2
Si541 Data Sheet
Electrical Specifications
2. Electrical Specifications
Table 2.1. Electrical Specifications
Test Condition/Comment
VDD = 1.8 V, 2.5 or 3.3 V ± 5%, TA = –40 to 85 ºC
Parameter
Temperature Range
Frequency Range
Symbol
TA
Min
–40
0.2
0.2
0.2
3.135
2.375
1.71
—
Typ
—
Max
85
Unit
ºC
FCLK
LVPECL, LVDS, CML
HCSL
—
1500
400
250
3.465
2.625
1.89
132
111
125
108
125
100
20
MHz
MHz
MHz
V
—
CMOS, Dual CMOS
3.3 V
—
Supply Voltage
Supply Current
VDD
3.3
2.5
1.8
100
75
80
74
80
64
—
2.5 V
V
1.8 V
V
IDD
LVPECL (output enabled)
LVDS/CML (output enabled)
HCSL (output enabled)
CMOS (output enabled)
Dual CMOS (output enabled)
Tristate Hi-Z (output disabled)
Frequency stability Grade A
Frequency stability Grade B
Frequency stability Grade C
Frequency stability Grade A
Frequency stability Grade B
Frequency stability Grade C
LVPECL/LVDS/CML
CMOS / Dual CMOS, (CL = 5 pF)
HCSL, FCLK >50 MHz
All formats
mA
mA
mA
mA
mA
mA
ppm
ppm
ppm
ppm
ppm
ppm
ps
—
—
—
—
—
Temperature Stability
–20
–10
–7
—
10
—
7
Total Stability1
FSTAB
–50
–25
–20
—
—
50
—
25
—
20
Rise/Fall Time
TR/TF
—
350
1.5
(20% to 80% VPP
Duty Cycle
)
—
0.5
—
ns
—
550
55
ps
DC
VIH
VIL
45
—
%
Output Enable (OE)
Frequency Select (FS)2
0.7 × VDD
—
—
—
V
—
0.3 × VDD
3
V
TD
Output Disable Time, FCLK >10 MHz
Output Enable Time, FCLK > 10 MHz
Settling Time after FS Change
—
—
µs
TE
—
—
20
µs
TFS
tOSC
—
—
10
ms
ms
Powerup Time
Time from 0.9 × VDD until output fre-
quency (FCLK) within spec
—
—
10
LVPECL Output Option3
VOC
VO
Mid-level
VDD – 1.42
1.1
—
—
VDD – 1.25
1.9
V
Swing (diff)
VPP
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Rev. 1.0 | 3
Si541 Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition/Comment
Mid-level (2.5 V, 3.3 V VDD)
Mid-level (1.8 V VDD)
Swing (diff)
Min
1.125
0.8
Typ
1.20
0.9
0.7
750
0
Max
1.275
1.0
Unit
V
LVDS Output Option4
VOC
V
VO
VOH
VOL
VC
0.5
0.9
VPP
mV
mV
mV
VPP
HCSL Output Option5
Output voltage high
Output voltage low
Crossing voltage
660
–150
250
0.6
850
150
550
1.0
350
0.8
CML Output Option
(AC-Coupled)
VO
Swing (diff)
CMOS Output Option
VOH
VOL
IOH = 8/6/4 mA for 3.3/2.5/1.8 V VDD 0.85 × VDD
IOL = 8/6/4 mA for 3.3/2.5/1.8 V VDD
—
—
—
V
V
—
0.15 × VDD
Notes:
1. Total Stability includes temperature stability, initial accuracy, load pulling, VDD variation, and aging for 20 yrs at 70 ºC.
2. OE includes a 50 kΩ pull-up to VDD for OE active high. Includes a 50 kΩ pull-down to GND for OE active low. FS includes a 50
kΩ pull-up to VDD.
3. 50 Ω to VDD – 2.0 V.
4. Rterm = 100 Ω (differential).
5. 50 Ω to GND.
Table 2.2. Clock Output Phase Jitter and PSRR
VDD = 1.8 V, 2.5 or 3.3 V ± 5%, TA = –40 to 85 ºC
Parameter
Symbol
Test Condition/Comment
Differential Formats
CMOS, Dual CMOS
Differential Formats
CMOS, Dual CMOS
100 kHz sine wave
200 kHz sine wave
500 kHz sine wave
1 MHz sine wave
Min
—
—
—
—
—
—
—
—
Typ
125
200
150
200
-83
-83
-82
-85
Max
200
—
Unit
fs
Phase Jitter (RMS, 12kHz - 20MHz)1
3.2 x 5 mm, FCLK ≥ 100 MHz
ϕJ
fs
Phase Jitter (RMS, 12kHz - 20MHz)1
5 x 7 mm, FCLK ≥ 100 MHz
200
—
fs
fs
Spurs Induced by External Power Supply
Noise, 50 mVpp Ripple. LVDS 156.25 MHz
Output
PSRR
—
—
dBc
—
—
Note:
1. Guaranteed by characterization. Jitter inclusive of any spurs.
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Rev. 1.0 | 4
Si541 Data Sheet
Electrical Specifications
Table 2.3. 3.2 x 5 mm Clock Output Phase Noise (Typical)
Offset Frequency (f)
100 Hz
156.25 MHz LVDS
200 MHz LVDS
–107
644.53125 MHz LVDS
Unit
dBc/Hz
Unit
–110
–121
–132
–139
–151
–160
–161
–99
1 kHz
–120
–109
–121
–127
–138
–155
–157
10 kHz
–130
100 kHz
–137
1 MHz
–149
10 MHz
–161
20 MHz
–162
Offset Frequency (f)
156.25 MHz
LVPECL
200 MHz
LVPECL
644.53125 MHz
LVPECL
100 Hz
1 kHz
–113
–123
–133
–139
–151
–162
–163
–110
–120
–130
–137
–149
–166
–167
–100
–110
–119
–127
–138
–156
–157
10 kHz
100 kHz
1 MHz
dBc/Hz
10 MHz
20 MHz
Phase jitter measured with Agilent E5052 using a differential-to-single ended converter (balun or buffer). Measurements collected for
>700 commonly used frequencies. Phase noise plots for specific frequencies are available using our free, online Oscillator Phase Noise
Lookup Tool at www.silabs.com/oscillators.
Figure 2.1. Phase Jitter vs. Output Frequency
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Rev. 1.0 | 5
Si541 Data Sheet
Electrical Specifications
Table 2.4. Environmental Compliance and Package Information
Parameter
Test Condition
Mechanical Shock
Mechanical Vibration
Solderability
MIL-STD-883, Method 2002
MIL-STD-883, Method 2007
MIL-STD-883, Method 2003
MIL-STD-883, Method 1014
MIL-STD-883, Method 2036
1
Gross and Fine Leak
Resistance to Solder Heat
Moisture Sensitivity Level (MSL)
Contact Pads
Gold over Nickel
Note:
1. For additional product information not listed in the data sheet (e.g. RoHS Certifications, MDDS data, qualification data, REACH
Declarations, ECCN codes, etc.), refer to our "Corporate Request For Information" portal found here: www.silabs.com/support/
quality/Pages/RoHSInformation.aspx.
Table 2.5. Thermal Conditions
Package
Parameter
Symbol
ΘJA
ΘJB
TJ
Test Condition
Still Air, 85 ºC
Still Air, 85 ºC
Still Air, 85 ºC
Still Air, 85 ºC
Still Air, 85 ºC
Still Air, 85 ºC
Value
80.3
50.8
125
Unit
ºC/W
ºC/W
ºC
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Board
Max Junction Temperature
3.2×5 mm
6-pin CLCC
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Board
Max Junction Temperature
ΘJA
ΘJB
TJ
68.4
52.9
125
ºC/W
ºC/W
ºC
5 × 7 mm
6-pin CLCC
Table 2.6. Absolute Maximum Ratings1
Parameter
Symbol
TAMAX
TS
Rating
95
Unit
Maximum Operating Temp.
Storage Temperature
Supply Voltage
ºC
ºC
ºC
V
–55 to 125
–0.5 to 3.8
–0.5 to VDD + 0.3
2.0
VDD
Input Voltage
VIN
ESD HBM (JESD22-A114)
Solder Temperature2
HBM
TPEAK
kV
ºC
260
2
TP
20–40
sec
Solder Time at TPEAK
Notes:
1. Stresses beyond those listed in this table may cause permanent damage to the device. Functional operation specification
compliance is not implied at these conditions. Exposure to maximum rating conditions for extended periods may affect device
reliability.
2. The device is compliant with JEDEC J-STD-020.
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Rev. 1.0 | 6
Si541 Data Sheet
Dual CMOS Buffer
3. Dual CMOS Buffer
Dual CMOS output format ordering options support either complementary or in-phase signals for two identical frequency outputs. This
feature enables replacement of multiple XOs with a single Si541 device.
~
Complementary
Outputs
~
In-Phase
Outputs
Figure 3.1. Integrated 1:2 CMOS Buffer Supports Complementary or In-Phase Outputs
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Rev. 1.0 | 7
Si541 Data Sheet
Recommended Output Terminations
4. Recommended Output Terminations
The output drivers support both AC-coupled and DC-coupled terminations as shown in figures below.
VDD
VDD
R1
VDD (3.3V, 2.5V)
CLK+
VDD (3.3V, 2.5V)
CLK+
R1
R1
R1
50 Ω
50 Ω
50 Ω
50 Ω
CLK-
CLK-
LVPECL
Receiver
LVPECL
Receiver
Si54x
Si54x
Rp
Rp
R2
R2
R2
R2
AC-Coupled LVPECL – Thevenin Termination
DC-Coupled LVPECL – Thevenin Termination
VDD (3.3V, 2.5V)
50 Ω
VDD (3.3V, 2.5V)
50 Ω
CLK+
CLK+
R1
R2
R1
50 Ω
50 Ω
50 Ω
50 Ω
VDD
VDD
VTT
VTT
CLK-
Rp
CLK-
R2
50 Ω
50 Ω
LVPECL
Receiver
LVPECL
Receiver
Si54x
Si54x
Rp
AC-Coupled LVPECL - 50 Ω w/VTT Bias
DC-Coupled LVPECL - 50 Ω w/VTT Bias
Figure 4.1. LVPECL Output Terminations
AC Coupled LVPECL
Termination Resistor Values
DC Coupled LVPECL
Termination Resistor Values
VDD
R1
R2
Rp
VDD
3.3 V
2.5 V
R1
R2
3.3 V
2.5 V
127 Ω
250 Ω
82.5 Ω
62.5 Ω
130 Ω
90 Ω
127 Ω
250 Ω
82.5 Ω
62.5 Ω
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Rev. 1.0 | 8
Si541 Data Sheet
Recommended Output Terminations
(3.3V, 2.5V, 1.8V)
VDD
(3.3V, 2.5V, 1.8V)
VDD
50 Ω
50 Ω
33 Ω
CLK+
CLK-
CLK+
50 Ω
50 Ω
100 Ω
33 Ω
50 Ω
CLK-
50 Ω
LVDS
Receiver
HCSL
Receiver
Si54x
Si54x
DC-Coupled LVDS
Source Terminated HCSL
(3.3V, 2.5V, 1.8V)
(3.3V, 2.5V, 1.8V)
VDD
VDD
50 Ω
CLK+
CLK+
50 Ω
100 Ω
CLK-
CLK-
50 Ω
50 Ω
50 Ω
50 Ω
LVDS
Receiver
HCSL
Receiver
Si54x
Si54x
AC-Coupled LVDS
Destination Terminated HCSL
Figure 4.2. LVDS and HCSL Output Terminations
(3.3V, 2.5V, 1.8V)
VDD
(3.3V, 2.5V, 1.8V)
VDD
CLK
50 Ω
50 Ω
CLK+
CLK-
50 Ω
10 Ω
100 Ω
NC
CMOS
Receiver
Si54x
CML
Si54x
Receiver
CML Termination without VCM
Single CMOS Termination
(3.3V, 2.5V, 1.8V)
VDD
(3.3V, 2.5V, 1.8V)
VDD
CLK+
50 Ω
50 Ω
CLK+
50 Ω
50 Ω
50 Ω
50 Ω
VCM
10 Ω
10 Ω
CLK-
CLK-
Si54x
CML
CMOS
Receivers
Si54x
Receiver
CML Termination with VCM
Dual CMOS Termination
Figure 4.3. CML and CMOS Output Terminations
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Rev. 1.0 | 9
Si541 Data Sheet
Package Outline
5. Package Outline
5.1 Package Outline (5×7 mm)
The figure below illustrates the package details for the 5×7 mm Si541. The table below lists the values for the dimensions shown in the
illustration.
Figure 5.1. Si541 (5×7 mm) Outline Diagram
Table 5.1. Package Diagram Dimensions (mm)
Dimension
Min
1.13
0.50
0.50
1.30
0.50
Nom
1.28
Max
1.43
0.60
0.60
1.50
0.70
Dimension
Min
1.17
0.05
1.70
Nom
1.27
Max
1.37
0.15
1.90
A
L
A2
0.55
L1
0.10
A3
0.55
p
—
b
1.40
R
0.70 REF
0.15
c
0.60
aaa
bbb
ccc
ddd
eee
D
5.00 BSC
4.40
0.15
D1
4.30
4.50
0.08
e
E
2.54 BSC
7.00 BSC
6.20
0.10
0.05
E1
6.10
6.30
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
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Rev. 1.0 | 10
Si541 Data Sheet
Package Outline
5.2 Package Outline (3.2×5 mm)
The figure below illustrates the package details for the 3.2×5 mm Si541. The table below lists the values for the dimensions shown in
the illustration.
Figure 5.2. Si541 (3.2×5 mm) Outline Diagram
Table 5.2. Package Diagram Dimensions (mm)
Dimension
Min
1.06
0.54
0.35
Nom
1.17
Max
1.33
0.74
0.55
A
b
0.64
c
0.45
D
3.20 BSC
2.60
D1
e
2.55
2.65
1.27 BSC
5.00 BSC
4.40
E
E1
H
4.35
0.45
0.80
0.05
1.36
4.45
0.65
1.00
0.15
1.56
0.55
L
0.90
L1
p
0.10
1.46
R
0.32 REF
0.15
aaa
bbb
ccc
ddd
eee
0.15
0.08
0.10
0.05
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
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Rev. 1.0 | 11
Si541 Data Sheet
PCB Land Pattern
6. PCB Land Pattern
6.1 PCB Land Pattern (5×7 mm)
The figure below illustrates the 5×7 mm PCB land pattern for the Si541. The table below lists the values for the dimensions shown in
the illustration.
Figure 6.1. Si541 (5×7 mm) PCB Land Pattern
Table 6.1. PCB Land Pattern Dimensions (mm)
Dimension
(mm)
4.20
2.54
1.55
1.95
C1
E
X1
Y1
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a
Fabrication Allowance of 0.05 mm.
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
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Rev. 1.0 | 12
Si541 Data Sheet
PCB Land Pattern
6.2 PCB Land Pattern (3.2×5 mm)
The figure below illustrates the 3.2×5.0 mm PCB land pattern for the Si541. The table below lists the values for the dimensions shown
in the illustration.
Figure 6.2. Si541 (3.2×5 mm) PCB Land Pattern
Table 6.2. PCB Land Pattern Dimensions (mm)
Dimension
(mm)
2.60
1.27
0.80
1.70
C1
E
X1
Y1
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a
Fabrication Allowance of 0.05 mm.
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
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Rev. 1.0 | 13
Si541 Data Sheet
Top Marking
7. Top Marking
The figure below illustrates the mark specification for the Si541. The table below lists the line information.
Figure 7.1. Mark Specification
Table 7.1. Si541 Top Mark Description
Line
Position
1–8
Description
1
2
"Si541", xxx = Ordering Option 1, Option 2, Option 3 (e.g. Si541AAA)
1–6
Frequency Code
(6-digit custom code as described in the Ordering Guide)
3
Trace Code
Pin 1 orientation mark (dot)
Product Revision (B)
Position 1
Position 2
Position 3–5
Position 6–7
Position 8–9
Tiny Trace Code (3 alphanumeric characters per assembly release instructions)
Year (last two digits of the year), to be assigned by assembly site (ex: 2017 = 17)
Calendar Work Week number (1–53), to be assigned by assembly site
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Rev. 1.0 | 14
Si541 Data Sheet
Revision History
8. Revision History
Revision 1.0
July, 2018
• Added 20 ppm total stability option.
Revision 0.75
March, 2018
• Added 25 ppm total stability option.
Revision 0.71
December 11, 2017
• Added 5x7 package and land pattern.
Revision 0.7
June 27, 2017
• Initial release.
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Rev. 1.0 | 15
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