545GAD250M000BAGR [SILICON]
CMOS Output Clock Oscillator,;
| 型号： | 545GAD250M000BAGR |
| 厂家： | 
SILICON |
| 描述： | CMOS Output Clock Oscillator, 机械 振荡器 |
| 文件： | 总14页 (文件大小：959K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
™
Ultra Series Crystal Oscillator
Si545 Data Sheet
Ultra Low Jitter Any-Frequency XO (80 fs), 0.2 to 1500 MHz
KEY FEATURES
The Si545 Ultra Series™ oscillator utilizes Silicon Laboratories’ advanced 4th
generation DSPLL® technology to provide an ultra-low jitter, low phase noise clock at
any output frequency. The device is factory-programmed to any frequency from 0.2 to
1500 MHz with <1 ppb resolution and maintains exceptionally low jitter for both
integer and fractional frequencies across its operating range. The Si545 offers
excellent reliability and frequency stability as well as guaranteed aging performance.
On-chip power supply filtering provides industry-leading power supply noise rejection,
simplifying the task of generating low jitter clocks in noisy systems that use switched-
mode power supplies. Offered in a small, industry-standard 3.2×5 mm footprint, the
Si545 has a dramatically simplified supply chain that enables Silicon Labs to ship
custom frequency samples 1-2 weeks after receipt of order. Unlike a traditional XO,
where a different crystal is required for each output frequency, the Si545 uses one
simple crystal and a DSPLL IC-based approach to provide the desired output
frequency. This process also guarantees 100% electrical testing of every device. The
Si545 is factory-configurable for a wide variety of user specifications, including
frequency, output format, and OE pin location/polarity. Specific configurations are
factory-programmed at time of shipment, eliminating the long lead times associated
with custom oscillators.
• Available with any frequency from 0.2
MHz to 1500 MHz
• Ultra low jitter: 80 fs Typ RMS
(12 kHz – 20 MHz)
• Excellent PSRR and supply noise
immunity: –80 dBc Typ
• 3x tighter stability than SAW oscillators
• 3.3 V, 2.5 V and 1.8 V V supply
DD
operation from the same part number
• LVPECL, LVDS, CML, HCSL, CMOS,
and Dual CMOS output options
• 3.2×5 mm package footprint
• Samples available with 1-2 week lead
times
APPLICATIONS
Pin Assignments
• 100G/200G/400G OTN, coherent optics
• 10G/40G/100G optical ethernet
• 3G-SDI/12G-SDI/24G-SDI broadcast
video
1
2
3
6
5
4
VDD
CLK-
CLK+
OE/NC
NC/OE
GND
• Datacenter
• Test and measurement
• Clock and data recovery
• FPGA/ASIC clocking
(Top View)
Fixed
Frequency
Crystal
Frequency
Flexible
DSPLL
Pin #
Descriptions
Low
Noise
Driver
1, 2
Selectable via ordering option
DCO
Digital
Phase
Detector
Digital
Phase Error
Loop
OE = Output enable; NC = No connect
OSC
Cancellation
Filter
Flexible
Formats,
1.8V – 3.3V
3
4
5
6
GND = Ground
Phase Error
Fractional
Operation
Divider
CLK+ = Clock output
NVM
Control
CLK- = Complementary clock output. Not used for CMOS.
VDD = Power supply
Power Supply Regulation
Output Enable
(Pin Control)
Built-in Power Supply
Noise Rejection
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Rev. 0.7
Si545 Data Sheet
Ordering Guide
1. Ordering Guide
The Si545 XO supports a variety of options including frequency, output format, and OE pin location/polarity, as shown in the chart
below. Specific device configurations are programmed into the part at time of shipment, and samples are available in 1-2 weeks. Silicon
Laboratories provides an online part number configuration utility to simplify this process. Refer to www.silabs.com/oscillators to access
this tool and for further ordering instructions.
Total Stability2
XO Series
Description
Temp Stability
Package
Temperature Grade
545
Single Frequency
A
B
3.2x5 mm
G
-40 to 85 °C
20 ppm
50 ppm
545
A
A
A
-
-
-
-
-
-
-
B
A
G
R
Device Revision
Order
Option
A
Signal Format
VDD Range
OE Pin OE Polarity
Reel
LVPECL
LVDS
2.5, 3.3 V
A
B
C
D
Pin 1
Pin 1
Pin 2
Pin 2
Active High
Active Low
Active High
Active Low
R
Tape and Reel
Coil Tape
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
B
C
D
E
<Blank>
CMOS
CML
Frequency Code3
Mxxxxxx
Description
HCSL
FCLK < 1 MHz
Dual CMOS
(In-Phase)
Dual CMOS
1.8, 2.5, 3.3 V
F
xMxxxxx
1 MHz ≤ FCLK < 10 MHz
xxMxxxx
10 MHz ≤ FCLK < 100 MHz
100 MHz ≤ FCLK < 1000 MHz
1000 MHz ≤ FCLK ≤ 1500 MHz
Custom code if FCLK > 6 digits
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
G
X
xxxMxxx
(Complementary)
Custom1
xxxxMxx
xxxxxx
Notes:
1. Contact Silicon Labs for non-standard configurations.
2. Total stability includes temp stability, initial accuracy, load pulling, VDD variation, and 20 year aging at 70 °C.
3. For example: 156.25 MHz = 156M250; 25 MHz = 25M0000. Create custom part numbers at www.silabs.com/oscillators.
1.1 Technical Support
Frequently Asked Questions (FAQ)
Oscillator Phase Noise Lookup Utility
Quality and Reliability
www.silabs.com/Si545-FAQ
www.silabs.com/oscillator-phase-noise-lookup
www.silabs.com/quality
Development Kits
www.silabs.com/oscillator-tools
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Rev. 0.7 | 2
Si545 Data Sheet
Electrical Specifications
2. Electrical Specifications
Table 2.1. Electrical Specifications
Test Condition/Comment
VDD = 1.8 V, 2.5 or 3.3 V ± 5%, TA = –40 to 85 ºC
Parameter
Temperature Range
Frequency Range
Symbol
TA
Min
–40
0.2
0.2
0.2
3.135
2.375
1.71
—
Typ
—
Max
85
Unit
ºC
FCLK
LVPECL, LVDS, CML
HCSL
—
1500
400
250
3.465
2.625
1.89
153
121
126
127
141
112
20
MHz
MHz
MHz
V
—
CMOS, Dual CMOS
3.3 V
—
Supply Voltage
Supply Current
VDD
3.3
2.5
1.8
107
83
86
87
92
73
—
2.5 V
V
1.8 V
V
IDD
LVPECL (output enabled)
LVDS/CML (output enabled)
HCSL (output enabled)
CMOS (output enabled)
Dual CMOS (output enabled)
Tristate Hi-Z (output disabled)
Frequency stability Grade A
Frequency stability Grade A
mA
mA
mA
mA
mA
mA
ppm
ppm
—
—
—
—
—
Temperature Stability
–20
–50
Total Stability1
FSTAB
TR/TF
—
50
Rise/Fall Time
LVPECL/LVDS/CML
CMOS / Dual CMOS, (CL = 5 pF)
HCSL, FCLK >50 MHz
All formats
—
—
0.5
—
—
—
—
—
—
—
350
ps
ns
ps
%
(20% to 80% VPP
Duty Cycle
)
—
1.5
—
450
DC
VIH
VIL
TD
45
55
Output Enable (OE)2
0.7 × VDD
—
V
—
—
—
—
0.3 × VDD
V
Output Disable Time, FCLK > 10 MHz
Output Enable Time, FCLK > 10 MHz
3
µs
µs
ms
TE
20
10
Powerup Time
tOSC
Time from 0.9 × VDD until output fre-
quency (FCLK) within spec
LVPECL Output Option3
VOC
VO
Mid-level
Swing (diff)
VDD – 1.42
1.1
—
—
VDD – 1.25
1.9
V
VPP
V
LVDS Output Option4
VOC
Mid-level (2.5 V, 3.3 V VDD)
Mid-level (1.8 V VDD)
Swing (diff)
1.125
0.8
1.20
0.9
0.7
1.275
1.0
V
VO
0.5
0.9
VPP
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Rev. 0.7 | 3
Si545 Data Sheet
Electrical Specifications
Parameter
Symbol
VOH
VOL
Test Condition/Comment
Output voltage high
Output voltage low
Crossing voltage
Min
660
–150
250
0.6
Typ
750
0
Max
850
150
550
1.0
Unit
mV
mV
mV
VPP
HCSL Output Option5
VC
350
0.8
CML Output Option
(AC-Coupled)
VO
Swing (diff)
CMOS Output Option
VOH
VOL
IOH = 8/6/4 mA for 3.3/2.5/1.8 V VDD 0.85 × VDD
IOL = 8/6/4 mA for 3.3/2.5/1.8 V VDD
—
—
—
V
V
—
0.15 × VDD
Notes:
1. Total Stability includes ±20 ppm temperature stability, initial accuracy, load pulling, VDD variation, and aging for 20 yrs at 70 ºC.
2. OE includes a 50 kΩ pull-up to VDD for OE active high. Includes a 50 kΩ pull-down to GND for OE active low.
3. 50 Ω to VDD – 2.0 V.
4. Rterm = 100 Ω (differential).
5. 50 Ω to GND.
Table 2.2. Clock Output Phase Jitter and PSRR
VDD = 1.8 V, 2.5 or 3.3 V ± 5%, TA = –40 to 85 ºC
Parameter
Symbol
Test Condition/Comment
FCLK ≥ 200 MHz
Min
—
Typ
80
Max
110
150
125
—
Unit
fs
Phase Jitter (RMS, 12kHz - 20MHz)1
All Differential Formats
ϕJ
100 MHz ≤ FCLK < 200 MHz
LVPECL @ 156.25 MHz
10 MHz ≤ FCLK ≤ 250 MHz
—
100
90
fs
—
fs
Phase Jitter (RMS, 12kHz - 20MHz)1
CMOS / Dual CMOS Formats
ϕJ
—
200
fs
Spurs Induced by External Power Supply
Noise, 50 mVpp Ripple. LVDS 156.25 MHz
Output
PSRR
100 kHz sine wave
200 kHz sine wave
500 kHz sine wave
1 MHz sine wave
—
—
—
—
-83
-83
-82
-85
—
—
—
—
dBc
Note:
1. Guaranteed by characterization. Jitter inclusive of any spurs.
Table 2.3. Clock Output Phase Noise (Typical)
Offset Frequency (f)
156.25 MHz LVDS
200 MHz LVDS
–102
644.53125 MHz LVDS
Unit
100 Hz
–106
–133
–140
–145
–152
–160
–161
94
–92
–119
–127
–132
–139
–154
–155
80
1 kHz
–129
10 kHz
–138
100 kHz
–142
dBc/Hz
1 MHz
10 MHz
–150
–160
20 MHz
–161
Phase Jitter (RMS, 12kHz - 20MHz)
84
fs
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Rev. 0.7 | 4
Si545 Data Sheet
Electrical Specifications
Offset Frequency (f)
156.25 MHz
LVPECL
200 MHz
LVPECL
644.53125 MHz
Unit
LVPECL
100 Hz
–103
–130
–140
–145
–152
–162
–163
92
–104
–128
–138
–142
–150
–162
–163
80
–91
1 kHz
–118
–127
–132
–140
–155
–156
81
10 kHz
100 kHz
dBc/Hz
1 MHz
10 MHz
20 MHz
Phase Jitter (RMS, 12kHz - 20MHz)
fs
Phase jitter measured with Agilent E5052 using a differential-to-single ended converter (balun or buffer). Measurements collected for
>700 commonly used frequencies. Phase noise plots for specific frequencies are available using our free, online Oscillator Phase Noise
Lookup Tool at www.silabs.com/oscillators.
Figure 2.1. Phase Jitter vs. Output Frequency
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Rev. 0.7 | 5
Si545 Data Sheet
Electrical Specifications
Table 2.4. Environmental Compliance and Package Information
Parameter
Test Condition
Mechanical Shock
Mechanical Vibration
Solderability
MIL-STD-883, Method 2002
MIL-STD-883, Method 2007
MIL-STD-883, Method 2003
MIL-STD-883, Method 1014
MIL-STD-883, Method 2036
1
Gross and Fine Leak
Resistance to Solder Heat
Moisture Sensitivity Level (MSL)
Contact Pads
Gold over Nickel
Note:
1. For additional product information not listed in the data sheet (e.g. RoHS Certifications, MDDS data, qualification data, REACH
Declarations, ECCN codes, etc.), refer to our "Corporate Request For Information" portal found here: www.silabs.com/support/
quality/Pages/RoHSInformation.aspx.
Table 2.5. Thermal Conditions
Package
Parameter
Symbol
ΘJA
Test Condition
Still Air, 85 °C
Still Air, 85 °C
Still Air, 85 °C
Value
80.3
50.8
125
Unit
ºC/W
ºC/W
ºC
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Board
Max Junction Temperature
3.2×5 mm
6-pin CLCC
ΘJB
TJ
Table 2.6. Absolute Maximum Ratings1
Parameter
Symbol
TAMAX
TS
Rating
95
Unit
Maximum Operating Temp.
Storage Temperature
Supply Voltage
ºC
ºC
ºC
V
–55 to 125
–0.5 to 3.8
–0.5 to VDD + 0.3
2.0
VDD
Input Voltage
VIN
ESD HBM (JESD22-A114)
Solder Temperature2
HBM
TPEAK
kV
ºC
260
2
TP
20–40
sec
Solder Time at TPEAK
Notes:
1. Stresses beyond those listed in this table may cause permanent damage to the device. Functional operation specification
compliance is not implied at these conditions. Exposure to maximum rating conditions for extended periods may affect device
reliability.
2. The device is compliant with JEDEC J-STD-020.
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Rev. 0.7 | 6
Si545 Data Sheet
Dual CMOS Buffer
3. Dual CMOS Buffer
Dual CMOS output format ordering options support either complementary or in-phase signals for two identical frequency outputs. This
feature enables replacement of multiple XOs with a single Si545 device.
~
Complementary
Outputs
~
In-Phase
Outputs
Figure 3.1. Integrated 1:2 CMOS Buffer Supports Complementary or In-Phase Outputs
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Rev. 0.7 | 7
Si545 Data Sheet
Recommended Output Terminations
4. Recommended Output Terminations
The output drivers support both AC-coupled and DC-coupled terminations as shown in figures below.
VDD
VDD
R1
VDD (3.3V, 2.5V)
CLK+
VDD (3.3V, 2.5V)
CLK+
R1
R1
R1
50 Ω
50 Ω
50 Ω
50 Ω
CLK-
CLK-
LVPECL
Receiver
LVPECL
Receiver
Si54x
Si54x
Rp
Rp
R2
R2
R2
R2
AC-Coupled LVPECL – Thevenin Termination
DC-Coupled LVPECL – Thevenin Termination
VDD (3.3V, 2.5V)
50 Ω
VDD (3.3V, 2.5V)
50 Ω
CLK+
CLK+
R1
R2
R1
50 Ω
50 Ω
50 Ω
50 Ω
VDD
VDD
VTT
VTT
CLK-
Rp
CLK-
R2
50 Ω
50 Ω
LVPECL
Receiver
LVPECL
Receiver
Si54x
Si54x
Rp
AC-Coupled LVPECL - 50 Ω w/VTT Bias
DC-Coupled LVPECL - 50 Ω w/VTT Bias
Figure 4.1. LVPECL Output Terminations
AC Coupled LVPECL
Termination Resistor Values
DC Coupled LVPECL
Termination Resistor Values
VDD
R1
R2
Rp
VDD
3.3 V
2.5 V
R1
R2
3.3 V
2.5 V
127 Ω
250 Ω
82.5 Ω
62.5 Ω
130 Ω
90 Ω
127 Ω
250 Ω
82.5 Ω
62.5 Ω
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Rev. 0.7 | 8
Si545 Data Sheet
Recommended Output Terminations
(3.3V, 2.5V, 1.8V)
VDD
(3.3V, 2.5V, 1.8V)
VDD
50 Ω
50 Ω
33 Ω
CLK+
CLK-
CLK+
50 Ω
50 Ω
100 Ω
33 Ω
50 Ω
CLK-
50 Ω
LVDS
Receiver
HCSL
Receiver
Si54x
Si54x
DC-Coupled LVDS
Source Terminated HCSL
(3.3V, 2.5V, 1.8V)
(3.3V, 2.5V, 1.8V)
VDD
VDD
50 Ω
CLK+
CLK+
50 Ω
100 Ω
CLK-
CLK-
50 Ω
50 Ω
50 Ω
50 Ω
LVDS
Receiver
HCSL
Receiver
Si54x
Si54x
AC-Coupled LVDS
Destination Terminated HCSL
Figure 4.2. LVDS and HCSL Output Terminations
(3.3V, 2.5V, 1.8V)
VDD
(3.3V, 2.5V, 1.8V)
VDD
CLK
50 Ω
50 Ω
CLK+
CLK-
50 Ω
10 Ω
100 Ω
NC
CMOS
Receiver
Si54x
CML
Si54x
Receiver
CML Termination without VCM
Single CMOS Termination
(3.3V, 2.5V, 1.8V)
VDD
(3.3V, 2.5V, 1.8V)
VDD
CLK+
50 Ω
50 Ω
CLK+
50 Ω
50 Ω
50 Ω
50 Ω
VCM
10 Ω
10 Ω
CLK-
CLK-
Si54x
CML
CMOS
Receivers
Si54x
Receiver
CML Termination with VCM
Dual CMOS Termination
Figure 4.3. CML and CMOS Output Terminations
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Rev. 0.7 | 9
Si545 Data Sheet
Package Outline
5. Package Outline
The figure below illustrates the package details for the 3.2 × 5 mm Si545. The table below lists the values for the dimensions shown in
the illustration.
Figure 5.1. Si545 Outline Diagram
Table 5.1. Package Diagram Dimensions (mm)
Dimension
Min
1.06
0.54
0.35
Nom
1.17
Max
1.28
0.74
0.55
A
b
0.64
c
0.45
D
3.20 BSC
2.60
D1
e
2.55
2.65
1.27 BSC
5.00 BSC
4.40
E
E1
H
4.35
0.45
0.90
0.05
1.17
4.45
0.65
1.10
0.15
1.37
0.55
L
1.00
L1
p
0.10
1.27
R
0.32 REF
0.15
aaa
bbb
ccc
ddd
eee
0.15
0.10
0.10
0.05
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
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Rev. 0.7 | 10
Si545 Data Sheet
PCB Land Pattern
6. PCB Land Pattern
The figure below illustrates the 3.2 × 5.0 mm PCB land pattern for the Si545. The table below lists the values for the dimensions shown
in the illustration.
Figure 6.1. Si545 PCB Land Pattern
Table 6.1. PCB Land Pattern Dimensions (mm)
Dimension
(mm)
2.60
1.27
0.80
1.70
C1
E
X1
Y1
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a
Fabrication Allowance of 0.05 mm.
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
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Rev. 0.7 | 11
Si545 Data Sheet
Top Marking
7. Top Marking
The figure below illustrates the mark specification for the Si545. The table below lists the line information.
Figure 7.1. Mark Specification
Table 7.1. Si545 Top Mark Description
Line
Position
1–8
Description
1
2
"Si545", xxx = Ordering Option 1, Option 2, Option 3 (e.g. Si545AAA)
1–7
Frequency Code
(e.g. 100M000 or 6-digit custom code as described in the Ordering Guide)
3
Trace Code
Pin 1 orientation mark (dot)
Product Revision (A)
Position 1
Position 2
Position 3–5
Position 6–7
Position 8–9
Tiny Trace Code (3 alphanumeric characters per assembly release instructions)
Year (last two digits of the year), to be assigned by assembly site (ex: 2017 = 17)
Calendar Work Week number (1–53), to be assigned by assembly site
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Rev. 0.7 | 12
Si545 Data Sheet
Revision History
8. Revision History
8.1 Revision 0.7
June 27, 2017
• Initial release.
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Rev. 0.7 | 13
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intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical"
parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes
without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included
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