554DC000159DG [SILICON]
Oscillator;
| 型号： | 554DC000159DG |
| 厂家： | 
SILICON |
| 描述： | Oscillator |
| 文件： | 总15页 (文件大小：486K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si554
REVISION D
QUAD FREQUENCY VOLTAGE-CONTROLLED CRYSTAL
OSCILLATOR (VCXO) 10 MHZ TO 1.4 GHZ
Features
Available with any-rate output
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
frequencies from 10–945 MHz and
selected frequencies to 1.4 GHz
Four selectable output frequencies
Si5602
®
3rd generation DSPLL with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Pb-free/RoHS-compliant
Ordering Information:
Applications
See page 10.
SONET/SDH
xDSL
10 GbE LAN / WAN
Low jitter clock generation
Optical modules
Clock and data recovery
Pin Assignments:
See page 9.
Description
The Si554 quad-frequency VCXO utilizes Silicon Laboratories’ advanced
DSPLL circuitry to provide a very low jitter clock for all output frequencies.
(Top View)
®
The Si554 is available with any-rate output frequency from 10 to 945 MHz
and selected frequencies to 1400 MHz. Unlike traditional VCXOs, where a
different crystal is required for each output frequency, the Si554 uses one
fixed crystal frequency to provide a wide range of output frequencies. This
IC-based approach allows the crystal resonator to provide exceptional
frequency stability and reliability. In addition, DSPLL clock synthesis
provides superior supply noise rejection, simplifying the task of generating
low jitter clocks in noisy environments typically found in communication
systems. The Si554 IC-based VCXO is factory-configurable for a wide
variety of user specifications including frequency, supply voltage, output
format, tuning slope, and temperature stability. Specific configurations are
factory-programmed at time of shipment, thereby eliminating the long lead
times associated with custom oscillators.
FS[1]
7
VC
VDD
1
2
3
6
5
4
OE
CLK–
CLK+
GND
8
FS[0]
Functional Block Diagram
VDD
CLK- CLK+
Any-rate
10–1400 MHz
DSPLL®
Fixed
Frequency XO
FS0
FS1
Clock Synthesis
ADC
Vc
OE
GND
Rev. 1.2 6/18
Copyright © 2018 by Silicon Laboratories
Si554
Si554
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol
Test Condition
3.3 V option
2.5 V option
1.8 V option
Min
2.97
2.25
1.71
Typ
3.3
2.5
1.8
Max
3.63
2.75
1.89
Units
1
V
V
V
Supply Voltage
V
DD
Supply Current
Output enabled
LVPECL
CML
—
—
—
—
130
117
108
98
120
108
99
mA
I
DD
LVDS
90
CMOS
Tristate mode
—
0.75 x V
—
60
—
—
—
75
—
mA
V
Output Enable (OE)
and Frequency Select FS[1:0]
V
IH
DD
2
V
0.5
85
V
IL
Operating Temperature Range
T
–40
ºC
A
Notes:
1. Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 10 for further details.
2. OE and FS[1:0] pins include a 17 k resistor to VDD.
Table 2. VC Control Voltage Input
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
1,2,3
Control Voltage Tuning Slope
10 to 90% of V
—
33
45
—
ppm/V
DD
90
K
V
135
180
356
4
Control Voltage Linearity
BSL
–5
–10
9.3
500
—
±1
±5
+5
+10
10.7
—
%
%
L
VC
Incremental
Modulation Bandwidth
BW
10.0
—
kHz
k
V
V Input Impedance
Z
C
VC
Nominal Control Voltage
V
@ f
V /2
DD
—
CNOM
O
Control Voltage Tuning Range
V
0
V
V
C
DD
Notes:
1. Positive slope; selectable option by part number. See Section 3. "Ordering Information" on page 10.
2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.
3. KV variation is ±10% of typical values.
4. BSL determined from deviation from best straight line fit with VC ranging from 10 to 90% of VDD. Incremental slope
determined with VC ranging from 10 to 90% of VDD
.
2
Rev. 1.2
Si554
Table 3. CLK± Output Frequency Characteristics
Parameter
Symbol
Test Condition
LVDS/CML/LVPECL
CMOS
Min
10
Typ
—
Max
Units
MHz
MHz
1,2,3
f
945
160
O
Nominal Frequency
10
—
1,4
Temperature Stability
T = –40 to +85 °C
–20
–50
–100
—
—
—
+20
+50
+100
A
ppm
1,4
Absolute Pull Range
Aging
APR
tOSC
±12
—
—
—
—
—
—
±375
±3
ppm
ppm
Frequency drift over first year.
Frequency drift over 15 year life.
—
±10
10
5
Power up Time
—
ms
ms
Settling Time After FS[1:0]
Change
t
Both FS[1] and FS[0] changing
simultaneously
—
20
FRQ
Notes:
1. See Section 3. "Ordering Information" on page 10 for further details.
2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz.
3. Nominal output frequency set by VCNOM = VDD/2.
4. Selectable parameter specified by part number.
5. Time from power up or tristate mode to fO (to within ±1 ppm of fO).
Table 4. CLK± Output Levels and Symmetry
Parameter
Symbol
Test Condition
mid-level
Min
VDD – 1.42
1.1
Typ
—
Max
VDD – 1.25
1.9
Units
V
1
LVPECL Output Option
V
O
VOD
VSE
swing (diff)
—
VPP
VPP
swing (single-ended)
mid-level
0.55
—
0.95
2
LVDS Output Option
V
O
1.125
0.5
1.20
0.7
1.275
0.9
V
swing (diff)
VOD
VO
VPP
2
CML Output Option
2.5/3.3 V option mid-level
1.8 V option mid-level
—
—
V
V
– 1.30
—
—
V
DD
– 0.36
V
DD
2.5/3.3 V option swing (diff)
1.8 V option swing (diff)
1.10
1.50
1.90
VPP
VPP
VOD
0.35
0.425
—
0.50
VDD
0.4
3
VOH
VOL
0.8 x VDD
CMOS Output Option
I
= 32 mA
OH
V
IOL = 32 mA
—
—
—
—
Rise/Fall time (20/80%)
Symmetry (duty cycle)
tR, F
t
LVPECL/LVDS/CML
—
350
—
ps
ns
CMOS with C = 15 pF
1
L
SYM
LVPECL:
(diff)
V
– 1.3 V
DD
45
—
55
%
LVDS:
CMOS:
1.25 V (diff)
/2
V
DD
Notes:
1. 50 to VDD – 2.0 V.
2. Rterm = 100 (differential).
3. CL = 15 pF
Rev. 1.2
3
Si554
Table 5. CLK± Output Phase Jitter
Parameter
Symbol
Test Condition
Kv = 33 ppm/V
Min
Typ
Max
Units
1,2,3
Phase Jitter (RMS)
for F > 500 MHz
J
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.26
0.26
—
—
ps
OUT
Kv = 45 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.27
0.26
—
—
ps
ps
ps
ps
ps
Kv = 90 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.32
0.26
—
—
Kv = 135 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.40
0.27
—
—
Kv = 180 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.49
0.28
—
—
Kv = 356 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.87
0.33
—
—
Notes:
1. Refer to AN255, AN256, and AN266 for further information.
2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.
3. See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply
rejection (PSR) advantage of Si55x versus SAW-based solutions.
4. Max jitter for LVPECL output with VC=1.65V, VDD=3.3V, 155.52 MHz.
5. Max offset frequencies: 80 MHz for FOUT > 250 MHz, 20 MHz for 50 MHz < FOUT <250 MHz,
2 MHz for 10 MHz < FOUT <50 MHz.
4
Rev. 1.2
Si554
Table 5. CLK± Output Phase Jitter (Continued)
Parameter
Symbol
Test Condition
Kv = 33 ppm/V
Min
Typ
Max
Units
1,2,3,4,5
Phase Jitter (RMS)
for F of 125 to 500 MHz
J
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.37
0.33
—
—
ps
OUT
Kv = 45 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.37
0.33
0.4
—
ps
ps
ps
ps
ps
Kv = 90 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.43
0.34
—
—
Kv = 135 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.50
0.34
—
—
Kv = 180 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.59
0.35
—
—
Kv = 356 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
1.00
0.39
—
—
Notes:
1. Refer to AN255, AN256, and AN266 for further information.
2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.
3. See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply
rejection (PSR) advantage of Si55x versus SAW-based solutions.
4. Max jitter for LVPECL output with VC=1.65V, VDD=3.3V, 155.52 MHz.
5. Max offset frequencies: 80 MHz for FOUT > 250 MHz, 20 MHz for 50 MHz < FOUT <250 MHz,
2 MHz for 10 MHz < FOUT <50 MHz.
Rev. 1.2
5
Si554
Table 5. CLK± Output Phase Jitter (Continued)
Parameter
Symbol
Test Condition
Kv = 33 ppm/V
Min
Typ
Max
Units
1,2,5
Phase Jitter (RMS)
for F 10 to 160 MHz
J
12 kHz to 20 MHz (OC-48)
50 kHz to 20 MHz
—
—
0.63
0.62
—
—
ps
OUT
CMOS Output Only
Kv = 45 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 20 MHz
—
—
0.63
0.62
—
—
ps
ps
ps
ps
ps
Kv = 90 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 20 MHz
—
—
0.67
0.66
—
—
Kv = 135 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 20 MHz
—
—
0.74
0.72
—
—
Kv = 180 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 20 MHz
—
—
0.83
0.8
—
—
Kv = 356 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 20 MHz
—
—
1.26
1.2
—
—
Notes:
1. Refer to AN255, AN256, and AN266 for further information.
2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.
3. See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply
rejection (PSR) advantage of Si55x versus SAW-based solutions.
4. Max jitter for LVPECL output with VC=1.65V, VDD=3.3V, 155.52 MHz.
5. Max offset frequencies: 80 MHz for FOUT > 250 MHz, 20 MHz for 50 MHz < FOUT <250 MHz,
2 MHz for 10 MHz < FOUT <50 MHz.
Table 6. CLK± Output Period Jitter
Parameter
Period Jitter*
Symbol
Test Condition
RMS
Min
—
Typ
2
Max
—
Units
ps
J
PER
Peak-to-Peak
—
14
—
ps
*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information.
6
Rev. 1.2
Si554
Table 7. CLK± Output Phase Noise (Typical)
Offset Frequency
74.25 MHz
90 ppm/V
LVPECL
491.52 MHz
45 ppm/V
LVPECL
622.08 MHz
135 ppm/V
LVPECL
Units
100 Hz
1 kHz
10 kHz
100 kHz
1 MHz
–87
–114
–132
–142
–148
–150
n/a
–75
–65
–90
–100
–116
–124
–135
–146
–147
–109
–121
–134
–146
–147
dBc/Hz
10 MHz
100 MHz
Table 8. Environmental Compliance
The Si554 meets the following qualification test requirements.
Parameter
Mechanical Shock
Conditions/Test Method
MIL-STD-883F, Method 2002.3 B
MIL-STD-883F, Method 2007.3 A
MIL-STD-883F, Method 203.8
MIL-STD-883F, Method 1014.7
MIL-STD-883F, Method 2016
J-STD-020, MSL 1
Mechanical Vibration
Solderability
Gross & Fine Leak
Resistance to Solvents
Moisture Sensitivity Level
Contact Pads
J-STD-020, MSL 1
Table 9. Thermal Characteristics
(Typical values TA = 25 ºC, VDD = 3.3 V)
Parameter
Symbol
Test Condition
Still Air
Min
—
Typ
84.6
38.8
—
Max
—
Unit
°C/W
°C/W
°C
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Case
Ambient Temperature
JA
Still Air
—
—
JC
T
–40
—
85
A
Junction Temperature
T
—
125
°C
J
Rev. 1.2
7
Si554
Table 10. Absolute Maximum Ratings1
Parameter
Maximum Operating Temperature
Supply Voltage, 1.8 V Option
Supply Voltage, 2.5/3.3 V Option
Input Voltage (any input pin)
Symbol
Rating
85
Units
T
ºC
AMAX
V
V
–0.5 to +1.9
–0.5 to +3.8
V
DD
DD
V
V
–0.5 to V + 0.3
V
ºC
I
DD
Storage Temperature
T
–55 to +125
2000
S
ESD Sensitivity (HBM, per JESD22-A114)
ESD
V
2
Soldering Temperature (Pb-free profile)
T
260
ºC
PEAK
2
Soldering Temperature Time @ T
(Pb-free profile)
t
20–40
seconds
PEAK
P
Notes:
1. Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional
operation or specification compliance is not implied at these conditions. Exposure to maximum rating conditions for
extended periods may affect device reliability.
2. The device is compliant with JEDEC J-STD-020C. Refer to Si5xx Packaging FAQ available for download from
www.silabs.com/VCXO for further information, including soldering profiles.
8
Rev. 1.2
Si554
2. Pin Descriptions
(Top View)
FS[1]
7
VC
VDD
1
6
5
4
OE
2
3
CLK–
CLK+
GND
8
FS[0]
Table 11. Si554 Pin Descriptions
Type
Pin
Name
Function
Control Voltage
1
V
Analog Input
C
Output Enable (Polarity = High):
0 = clock output disabled (outputs tri-stated)
1 = clock output enabled
2
OE*
Input
Electrical and Case Ground
Oscillator Output
3
4
GND
Ground
Output
Output
CLK+
Complementary Output
(N/C for CMOS)
CLK–
(N/A for CMOS)
5
Power Supply Voltage
Frequency Select MSB
Frequency Select LSB
6
7
8
V
Power
Input
Input
DD
FS[1]*
FS[0]*
*Note: FS[1:0] and OE include a 17 k pullup resistor to VDD. Output Enable polarity selectable at time of order. See Section
3. "Ordering Information" on page 10 for details on frequency select and OE polarity ordering options.
Rev. 1.2
9
Si554
3. Ordering Information
The Si554 supports a variety of options including frequency, temperature stability, tuning slope, output format, and
V
.
Specific device configurations are programmed into the Si554 at time of shipment. Configurations are
DD
specified using the Part Number Configuration chart shown below. Silicon Labs provides a web browser-based part
number configuration utility to simplify this process. Refer to www.silabs.com/VCXOPartNumber to access this tool
and for further ordering instructions. The Si554 VCXO series is supplied in an industry-standard, RoHS-compliant,
lead-free, 8-pad, 5 x 7 mm package. Tape and reel packaging is an ordering option.
X
X
D
G
R
554
XXXXXX
R = Tape & Reel
Blank = Coil Tape
554 Quad VCXO
Product Family
Operating Temp Range (°C)
–40 to +85 °C
G
Device Revision Letter
6-digit Frequency Designator Code
Four unique frequencies can be specified within the following bands of frequencies : 10 to
945 MHz, 970 to 1134 MHz, and 1213 to 1417 MHz. A six digit code will be assigned for
the specified combination of frequencies . Codes > 000100 refer to XOs programmed with
the lowest frequency value selected when FS [1:0] = 00, and the highest value when
FS[1:0] = 11. Six digit codes < 000100 refer to XOs programmed with the highest
frequency value selected when FS [1:0] = 00, and the lowest value when FS [1:0] = 11.
1st Option Code
VDD Output Format Output Enable Polarity
2nd Option Code
A
B
C
D
E
F
G
H
J
K
M
N
P
Q
R
S
T
3.3 LVPECL
3.3 LVDS
3.3 CMOS
3.3 CML
2.5 LVPECL
2.5 LVDS
2.5 CMOS
2.5 CML
1.8 CMOS
1.8 CML
3.3 LVPECL
3.3 LVDS
3.3 CMOS
3.3 CML
2.5 LVPECL
2.5 LVDS
2.5 CMOS
2.5 CML
1.8 CMOS
1.8 CML
High
High
High
High
High
High
High
High
High
High
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Temperature
Stability
± ppm (max)
Tuning Slope
Minimum APR
(±ppm) for VDD @
Kv
ppm/V (typ)
180
Code
A
B
C
D
E
F
G
H
J
K
M
3.3 V
100
30
150
80
2.5 V
75
Note 6
125
30
Note 6
75
300
145
104
220
1.8 V
25
Note 6
75
25
Note 6
50
235
105
70
155
Note 6
100
100
50
50
20
50
20
20
20
90
180
90
45
135
356
180
135
25
100
375
185
130
295
12
100
20
356
33
Note 6
Notes:
1. For best jitter and phase noise performance , always choose the smallest Kv that meets
the application s minimum APR requirements . Unlike SAW-based solutions which
require higher higher Kv values to account for their higher temperature dependence ,
the Si55x series provides lower Kv options to minimize noise coupling and jitter in real -
world PLL designs. See AN255 and AN266 for more information.
2. APR is the ability of a VCXO to track a signal over the product lifetime . A VCXO with an
APR of ±25 ppm is able to lock to a clock with a ± 25 ppm stability over 15 years over all
operating conditions.
U
V
W
Note:
CMOS available to 160 MHz.
3. Nominal Pull range (±) = 0.5 x VDD x tuning slope.
4. Nominal Absolute Pull Range (±APR) = Pull range – stability – lifetime aging
= 0.5 x VDD x tuning slope – stability – 10 ppm
5. Minimum APR values noted above include worst case values for all parameters .
6. Combination not available.
Example Part Number: 554AF000124DGR is a 5 x 7 mm Quad VCXO in an 8 pad package. Since the six digit code (000124) is > 000100, f0 is
622.08 MHz (lowest frequency), f1 is 644.53125, f2 is 657.42188, and f3 is 669.32658 MHz (highest frequency), with a 3.3 V supply, LVPECL
output, and Output Enable active high polarity. Temperature stability is specified as ±50 ppm and the tuning slope is 135 ppm/V. The part is specified
for a –40 to +85 C° ambient temperature range operation and is shipped in tape and reel format .
Figure 1. Part Number Convention
10
Rev. 1.2
Si554
4. Package Outline and Suggested Pad Layout
Figure 2 illustrates the package details for the Si554. Table 12 lists the values for the dimensions shown in the
illustration.
Figure 2. Si554 Outline Diagram
Table 12. Package Diagram Dimensions (mm)
Dimension
Min
1.50
1.30
0.90
0.50
0.30
Nom
1.65
1.40
1.00
0.60
—
Max
1.80
1.50
1.10
0.70
0.60
A
b
b1
c
c1
D
D1
e
E
E1
H
L
L1
p
5.00 BSC
4.40
2.54 BSC
7.00 BSC
6.20
4.30
4.50
6.10
0.55
1.17
1.07
1.80
6.30
0.75
1.37
1.27
2.60
0.65
1.27
1.17
—
R
0.70 REF
—
aaa
bbb
ccc
ddd
eee
—
—
—
—
—
0.15
0.15
0.10
0.10
0.05
—
—
—
—
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
Rev. 1.2
11
Si554
5. 8-Pin PCB Land Pattern
Figure 3 illustrates the 8-pin PCB land pattern for the Si554. Table 13 lists the values for the dimensions shown in
the illustration.
Figure 3. Si554 PCB Land Pattern
Table 13. PCB Land Pattern Dimensions (mm)
Dimension
Min
Max
D2
D3
5.08 REF
5.705 REF
2.54 BSC
4.20 REF
e
E2
GD
GE
VD
VE
0.84
2.00
—
—
8.20 REF
7.30 REF
1.70 TYP
1.545 TYP
2.15 REF
1.3 REF
X1
X2
Y1
Y2
ZD
—
—
6.78
6.30
ZE
Note:
1. Dimensioning and tolerancing per the ANSI Y14.5M-1994
specification.
2. Land pattern design follows IPC-7351 guidelines.
3. All dimensions shown are at maximum material condition
(MMC).
4. Controlling dimension is in millimeters (mm).
12
Rev. 1.2
Si554
6. Top Marking
6.1. Si554 Top Marking
6.2. Top Marking Explanation
Line
Position
Description
1
1–10
“SiLabs”+ Part Family Number, 554 (First 3 characters in part number)
2
1–10
Si554: Option1+Option2+Freq(7)+Temp
Si554 w/ 8-digit resolution: Option1+Option2+ConfigNum(6)+Temp
3
Trace Code
Position 1
Pin 1 orientation mark (dot)
Product Revision (D)
Position 2
Tiny Trace Code (4 alphanumeric characters per assembly release instructions)
Year (least significant year digit), to be assigned by assembly site (ex: 2007 = 7)
Calendar Work Week number (1–53), to be assigned by assembly site
“+” to indicate Pb-Free and RoHS-compliant
Position 3–6
Position 7
Position 8–9
Position 10
Rev. 1.2
13
Si554
DOCUMENT CHANGE LIST
Revision 0.6 to Revision 1.0
Updated Table 4 on page 3.
Updated 2.5 V/3.3 V and 1.8 V CML output level
specifications.
Updated Table 5 on page 4.
Removed the words “Differential Modes:
LVPECL/LVDS/CML” in the footnote referring to AN256.
Added footnotes clarifying max offset frequency test
conditions.
Added CMOS phase jitter specs.
Updated Table 10 on page 8.
Separated 1.8 V, 2.5 V/3.3 V supply voltage
specifications.
Updated ESD HBM sensitivity rating.
Updated and clarified Table 8 on page 7
Added “Moisture Sensitivity Level” and “Contact Pads”
rows.
Updated 6. "Top Marking" on page 13 to reflect
specific marking information (previously, figure was
generic).
Updated 4. "Package Outline and Suggested Pad
Layout" on page 11.
Added cyrstal impedance pin in Figure 2 on page 11 and
Table 12 on page 11.
Reordered spec tables and back matter to conform
to data sheet quality conventions.
Revision 1.0 to Revision 1.1
Added Table 9, “Thermal Characteristics,” on
page 7.
Revision 1.1 to Revision 1.2
June, 2018
Changed “Trays” to “Coil Tape” in section
3. “Ordering Information”.
14
Rev. 1.2
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相关型号：
554DC000197BGR
CMOS/TTL Output Clock Oscillator, 132.8125MHz Nom, ROHS COMPLIANT, SMD, 8 PIN
SILICON
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