554HBXXXXXXBG [SILICON]
SiPHY OC-192/STM-64 TRANSMITTER; SiPHY的OC-192 / STM-64发射机
| 型号： | 554HBXXXXXXBG |
| 厂家： | 
SILICON |
| 描述： | SiPHY OC-192/STM-64 TRANSMITTER |
| 文件： | 总20页 (文件大小：296K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si5540
PRELIMINARY DATA SHEET
SiPHY™ OC-192/STM-64 TRANSMITTER
Features
Complete SONET/SDH transmitter for OC-192/STM-64 data rates with integrated
™
16:1 multiplexer and DSPLL based clock multiplier unit:
Data Rates Supported: OC-192/STM-64,
10GbE, and 10.7 Gbps FEC
Low Power Operation 0.6 W (typ)
Small Footprint: 99-Pin BGA Package
(11 x 11 mm)
OIF SFI-4 Compliant Interface
Output Clock Powerdown
Operates with 155 or 622 MHz
Reference Sources
Optional 3.3 V Supply Pin for
LVTTL Compatible Outputs
Single 1.8 V Supply Operation
DSPLL™ Based Clock Multiplier Unit
w/ selectable loop filter bandwidths
Bottom View
Applications
Ordering Information:
See page 17.
Sonet/SDH/ATM Routers
Add/Drop Multiplexers
Digital Cross Connects
Optical Transceiver Modules
Sonet/SDH Test Equipment
Description
The Si5540 is a fully integrated low-power transmitter for high-speed serial
communication systems. It combines high speed clock generation with a 16:1
multiplexer to serialize data for OC-192/STM-64 applications. The Si5540 is based
™
on Silicon Laboratories’ DSPLL technology which eliminates the external loop
filter components required by traditional clock multiplier units. In addition,
selectable loop filter bandwidths are provided to ensure superior jitter performance
while relaxing the jitter requirements on external clock distribution subsystems.
Support for data streams up to 10.7 Gbps is also provided for applications that
employ forward error correction (FEC).
The Si5540 represents a new standard in low jitter, low power and small size for
10 Gbps serial transmitters. It operates from a single 1.8 V supply over the
industrial temperature range (–40°C to 85°C).
Functional Block Diagram
REFSEL
2
REFCLK
REFRATE
TXCLK16IN
DSPLLTM
CMU
TXLOL
BWSEL
2
16
TXCLK16OUT
TXCLK16IN
÷
TXCLKDSBL
TXCLKOUT
2
2
2
32
TXDIN[15:0]
FIFORST
TXDOUT
Reset
Control
Bias
FIFOERR
TXMSBSEL
REXT
RESET
TXSQLCH
Preliminary Rev. 0.31 8/01
Copyright © 2001 by Silicon Laboratories
Si5540-DS031
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si5540
2
Preliminary Rev. 0.31
Si5540
TABLE OF CONTENTS
Section
Page
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
DSPLL™ Clock Multiplier Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Serialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Clock Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Si5540 Pinout: 99-Pin BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Pin Descriptions: Si5540 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Preliminary Rev. 0.31
3
Si5540
Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol
Test Condition
Min*
Typ
Unit
Max*
85
Ambient Temperature
T
–40
1.71
1.71
25
—
°C
V
A
LVTTL Output Supply Voltage
Si5540 Supply Voltage
V
3.47
1.89
DD33
V
1.8
V
DD
*Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25°C unless otherwise stated.
V
SIGNAL +
Differential
I/Os
VIS
Single Ended Voltage
VICM, VOCM
SIGNAL –
(SIGNAL +) – (SIGNAL –)
Differential Peak-to-Peak Voltage
t
VID,VOD (VID = 2VIS)
Differential
Voltage Swing
Figure 1. Differential Voltage Measurement (TXDIN, TXDOUT, TXCLK16IN, TXCLK16OUT)
tsu
thd
TXDOUT,
TXDIN
tCP
tCH
TXCLKOUT,
TXCLK16IN
Figure 2. Data to Clock Delay
80%
20%
All Differential
IOs
tF
tR
Figure 3. Rise/Fall Time Measurement
4
Preliminary Rev. 0.31
Si5540
Table 2. DC Characteristics, V = 1.8 V
DD
(VDD = 1.8 V ±5%, TA = –40°C to 85°C)
Parameter
Symbol Test Condition
Min
—
Typ
333
0.6
0.9
Max
TBD
TBD
1.0
Unit
mA
W
Supply Current
Power Dissipation
IDD
PD
—
Common Mode Output Voltage
(TXDOUT,TXCLKOUT)
VOCM
.8
V
Differential Output Voltage Swing
VOD
See Figure 1
800
1000
1200
mV
(pk-pk)
(TXDOUT,TXCLKOUT), Differential pk-pk
LVPECL Input Voltage High (REFCLK)
LVPECL Input Voltage Low (REFCLK)
VIH
VIL
VID
1.975
1.32
250
2.3
1.6
—
2.59
1.99
2600
V
V
LVPECL Input Voltage Swing (REFCLK),
Differential pk-pk
mV
(pk-pk)
LVPECL Input Common Mode (REFCLK)
VICM
RIN
1.65
42
1.95
50
2.30
58
V
Input Impedance
Each input to
Ω
common mode
(REFCLK, TXDIN, TXCLK16IN)
LVDS Input High Voltage (TXDIN,
TXCLK16IN)
VIH
VIL
—
0.0
100
—
—
—
2.4
—
V
V
LVDS Input Low Voltage (TXDIN,
TXCLK16IN)
LVDS Input Voltage, Single Ended pk-pk
(TXDIN, TXCLK16IN)
VISE
600
mV
(pk-pk)
LVDS Input Common Mode Voltage
(TXDIN, TXCLK16IN)
VICM
VOH
.8
2.0
—
2.4
V
LVDS Output High Voltage
(TXCLK16OUT)
100 Ω Load
Line-to-Line
TBD
1.475
V
LVDS Output Low Voltage
(TXCLK16OUT)
VOL
100 Ω Load
Line-to-Line
0.925
250
—
TBD
550
V
LVDS Output Voltage, Single Ended pk-pk
(TXCLK16OUT)
VOSE
100 Ω Load
Line-to-Line, See
Figure 1
400
mV
(pk-pk)
LVDS Output Common Mode Voltage
(TXCLK16OUT)
VOCM
ISC–
ISC+
VIL2
1.125
—
1.20
25
1.275
TBD
—
V
mA
µA
V
Output Short to GND
(TXCLK16OUT, TXDOUT, TXCLKOUT)
Output Short to VDD
(TXCLK16OUT, TXDOUT, TXCLKOUT)
TBD
—
–100
—
LVTTL Input Voltage Low
0.8
(TXCLKDSBL, FIFORST, TXSQLCH,
BWSEL, REFRATE, REFSEL, TXMSBSEL,
RESET)
Preliminary Rev. 0.31
5
Si5540
Table 2. DC Characteristics, V = 1.8 V (Continued)
DD
(VDD = 1.8 V ±5%, TA = –40°C to 85°C)
Parameter
Symbol Test Condition
VIH2
Min
Typ
Max
Unit
Input Voltage High
2.0
—
—
V
(TXCLKDSBL, FIFORST, TXSQLCH,
BWSEL, REFRATE, REFSEL, TXMSBSEL,
RESET)
Input Low Current
IIL
—
—
10
—
—
—
10
10
—
µA
µA
kΩ
(TXCLKDSBL, FIFORST, TXSQLCH,
BWSEL, REFRATE, REFSEL, TXMSBSEL,
RESET)
Input High Current
IIH
(TXCLKDSBL, FIFORST, TXSQLCH,
BWSEL, REFRATE, REFSEL, TXMSBSEL,
RESET)
Input Impedance
RIN
(TXCLKDSBL, FIFORST, TXSQLCH,
BWSEL, REFRATE, REFSEL, TXMSBSEL,
RESET)
LVTTL Output Voltage Low
(FIFOERR, TXLOL)
VOL2
VDD33 = 1.8 V
VDD33 = 3.3 V
VDD33 = 1.8 V
VDD33 = 3.3 V
—
—
—
—
—
—
0.4
0.4
—
V
V
LVTTL Output Voltage High
(FIFOERR, TXLOL)
VOH2
1.4
2.4
—
6
Preliminary Rev. 0.31
Si5540
Table 3. AC Characteristics (TXCLK16OUT, TXCLK16IN, TXCLKOUT, TXDIN, TXDOUT)
(VDD = 1.8 V ±5%, TA = –40°C to 85°C)
Parameter
Symbol
Test Condition
Min
—
Typ
9.95
—
Max
10.7
55
Unit
GHz
%
TXCLKOUT Frequency
TXCLKOUT Duty Cycle
fclkout
tch/tcp, Figure 2
Figure 3
45
—
Output Rise Time
(TXCLKOUT, TXDOUT)
tR
tF
25
—
ps
Output Fall Time
Figure 3
—
25
—
ps
(TXCLKOUT, TXDOUT)
TXCLKOUT Setup to TXDOUT
TXCLKOUT Hold From TXDOUT
Output Return Loss
tsu
thd
Figure 2
Figure 2
25
25
—
—
—
—
ps
ps
400 kHz–10 GHz
10 GHz–16 GHz
TBD
TBD
—
—
—
—
dB
dB
TXCLK16OUT Frequency
TXCLK16OUT Duty Cycle
TXCLK16OUT Rise & Fall Times
TXDIN Setup to TXCLK16IN
TXDIN Hold from TXCLK16IN
TXCLK16IN Frequency
fCLKIN
Figure 2
—
40
622
—
667
60
MHz
%
tch/tcp, Figure 2
tR, tF
tDSIN
tDHIN
fCLKIN
100
—
—
300
300
300
667
60
ps
—
ps
—
—
ps
—
622
—
MHz
%
TXCLK16IN Duty Cycle
tch/tcp, Figure 2
40
TXCLK16IN Rise & Fall Times
tR, tF
100
—
300
ps
Table 4. AC Characteristics (Clock Multiplier Characteristics)
(VDD = 1.8 V ±5%, TA = –40°C to 85°C)
Parameter
Symbol
JDET(PP)
JGEN(RMS)
JBW
Test Condition
Min
—
—
—
—
—
—
—
—
40
Typ
0.020
0.005
—
Max
TBD
TBD
12
Unit
UIPP
UIRMS
kHz
kHz
dB
Jitter Generation—Deterministic
Jitter Generation—Random
Jitter Transfer Bandwidth
PRBS-23
BWSEL = 0
BWSEL = 1
—
50
Jitter Transfer Peaking
Acquisition Time
0.05
15
0.1
20
TAQ
Valid REFCLK
REFRATE = 1
REFRATE = 0
ms
Input Reference Clock Frequency RCFREQ
622
155
—
667
167
60
MHz
MHz
%
Input Reference Clock Duty
Cycle
RCDUTY
RCTOL
Input Reference Clock Frequency
Tolerance
–100
—
100
ppm
Note: Bellcore specifications: GR-1377-CORE, Issue 5, December 1998.
Preliminary Rev. 0.31
7
Si5540
Table 5. Absolute Maximum Ratings
Parameter
Symbol
VDD
Value
–0.5 to 3.0
–0.5 to 3.6
–0.3 to (VDD+ 0.3)
±50
Unit
V
DC Supply Voltage
LVTTL Input Voltage
VDD33
VDIF
V
Differential Input Voltages
Maximum Current any output PIN
Operating Junction Temperature
Storage Temperature Range
V
mA
°C
°C
°C
TJCT
TSTG
–55 to 150
–55 to 150
275
Package Temperature
(soldering 10 seconds)
ESD HBM Tolerance (100 pf, 1.5 kΩ)
TBD
V
Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Table 6. Thermal Characteristics
Parameter
Symbol
Test Condition
Value
Unit
Thermal Resistance Junction to Ambient
ϕ
Still Air
35
°C/W
JA
8
Preliminary Rev. 0.31
Si5540
Functional Description
The Si5540 is a fully integrated, low power, SONET/ bandwidth is selected via the BWSEL control input. In
SDH transmitter for OC-192/STM-64 applications. It traditional PLL implementations, changing the loop filter
combines a high performance clock multiplier unit bandwidth would require changing the values of
(CMU) with a 16:1 serializer that has a low-speed external loop filter components.
interface compliant with the Optical Interface Forum
(OIF) SFI-4 standard.
In narrowband mode, a loop filter cutoff of 12 kHz is
provided. This setting makes the Si5540 more tolerant
The CMU uses a phase-locked loop (PLL) architecture of jitter on the reference clock source. As a result, the
based on Silicon Laboratories’ proprietary DSPLL™ complexity of the clock distribution circuitry used to
technology. This technology is used to generate ultra- generate the physical layer reference clocks can be
low jitter clock and data outputs that provide significant simplified without compromising jitter margin to the
margin to the SONET/SDH specifications. The DSPLL SONET/SDH specification.
architecture also utilizes a digitally implemented loop
In wideband mode, the loop filter provides a cutoff of
filter that eliminates the need for external loop filter
50 kHz. This setting is desirable in applications where
components. As a result, sensitive noise coupling nodes
the reference clock is provided by a low jitter source like
that typically cause degraded jitter performance in
the Si5364 Clock Synchronization IC or Si5320
Precision Clock Multiplier/Jitter Attenuator IC. This
crowded PCB environments are removed.
The DSPLL also reduces the complexity and allows the DSPLL to more closely track the precision
performance requirements of reference clock reference source resulting in the best possible jitter
distribution strategies for OC-192/STM-64 optical port performance.
cards. This is possible because the DSPLL provides
selectable wideband and narrowband loop filter settings
Reference Clock
that allow the user to set the jitter attenuation The CMU within the Si5530 is designed to operate with
characteristics of the CMU to accommodate reference reference clock sources that are either 1/16th or 1/64th
clock sources that have a high jitter content. Unlike the desired output data rate. The CMU will support
traditional analog PLL implementations, the loop filter operation with data rates between 9.9 Gbps and
bandwidth is controlled by a digital filter inside the 10.7 Gbps and the reference clock should be scaled
DSPLL and can be changed without any modification to accordingly. For example, to support 10.66 Gbps
external components.
operation the reference clock source would be
approximately 167 MHz or 666 MHz. The REFRATE
input pin is used to configure the device for operation
with one of the two supported reference clock
submultiples of the data rate.
DSPLL™ Clock Multiplier Unit
The Si5540’s clock multiplier unit (CMU) uses Silicon
Laboratories’ proprietary DSPLL technology to generate
a low jitter, high frequency clock source capable of
producing a high speed serial clock and data output with
significant margin to the SONET/SDH specifications.
This is achieved by using a digital signal processing
(DSP) algorithm to replace the loop filter commonly
found in analog PLL designs. This algorithm processes
the phase detector error term and generates a digital
control value to adjust the frequency of the voltage
controlled oscillator (VCO). Because external loop filter
components are not required, sensitive noise entry
points are eliminated, thus making the DSPLL less
susceptible to board-level noise sources. Therefore,
SONET/SDH jitter compliance is easier to attain in the
application.
The Si5540 supports operation with two selectable
reference clock sources. The first configuration uses an
externally provided reference clock that is input via
REFCLK. The second configuration uses the parallel
data clock, TXCLK16IN, as the reference clock source.
When using TXCLK16IN as the reference source, the
narrowband loop filter setting may be preferable to
remove jitter that may be present on the data clock. The
selection of reference clock configuration is controlled
via the REFSEL input. The Si5540 will drive the TXLOL
output high to indicate the DSPLL has locked to the
selected reference source.
Serialization
The Si5540 includes serialization circuitry that
combines a FIFO with a parallel to serial shift register.
Low speed data on the parallel input bus, TXDIN[15:0],
is latched into the FIFO on the rising edge of
TXCLK16IN. The data in the FIFO is clocked into the
Programmable Loop Filter Bandwidth
The digital loop filter in the Si5530 provides two
bandwidth settings that support either wideband or
narrowband jitter transfer characteristics. The filter
Preliminary Rev. 0.31
9
Si5540
shift register by an output clock, TXCLK16OUT, that is
produced by dividing down the high speed transmit
clock, TXCLKOUT, by a factor of 16. The TXCLK16OUT
clock output is provided to support 16 bit word transfers
between the Si5540 and upstream devices using a
counter clocking scheme. The high-speed serial data
stream is clocked out of the shift register using
TXCLKOUT.
Clock Disable
The Si5540 provides a clock disable pin, TXCLKDSBL,
that is used to disable the high-speed serial data clock
output, TXCLKOUT. When the TXCLKDSBL pin is
asserted, the positive and negative terminals of CLK-
OUT are tied to 1.5 V through 50 Ω on-chip resistors.
This feature is used to reduce power consumption in
applications that do not use the high speed transmit
data clock.
Input FIFO
The Si5540 integrates a FIFO to decouple data
transferred into the FIFO via TXCLK16IN from data
Bias Generation Circuitry
transferred into the shift register via TXCLK16OUT. The The Si5540 makes use of an external resistor to set
FIFO is eight parallel words deep and accommodates internal bias currents. The external resistor allows pre-
any static phase delay that may be introduced between cise generation of bias currents which significantly
TXCLK16OUT and TXCLK16IN in counter clocking reduces power consumption versus traditional imple-
schemes. Further, the FIFO will accommodate a phase mentations that use an internal resistor. The bias gener-
drift or wander between TXCLK16IN and TXCLK16OUT ation circuitry requires
a
3.09 kΩ (1%) resistor
of up to three parallel data words.
connected between REXT and GND.
The FIFO circuitry indicates an overflow or underflow
condition by asserting FIFOERR high. This output can
be used to recenter the FIFO read/write pointers by
tieing it directly to the FIFORST input. The Si5540 will
also recenter the read/write pointers after the device’s
power on reset, external reset via RESET, and each
time the DSPLL transitions from an out of lock state to a
locked state (TXLOL transitions from low to high).
Parallel Input To Serial Output Relationship
The Si5540 provides the capability to select the order in
which data on the parallel input bus is transmitted seri-
ally. Data on this bus can be transmitted MSB first or
LSB first depending on the setting of TXMSBSEL. If
TXMSBSEL is tied low, TXDIN0 is transmitted first fol-
lowed in order by TXDIN1 through TXDIN15. If TXMSB-
SEL is tied high, TXDIN15 is transmitted first followed in
order by TXDIN14 through TXDIN0. This feature simpli-
fies board routing when ICs are mounted on both sides
of the PCB.
Transmit Data Squelch
To prevent the transmission of corrupted data into the
network, the Si5540 provides a control pin that can be
used to force the high speed data output, TXDOUT, to 0.
By driving TXSQLCH low TXDOUT will be forced to 0.
Reset
A device reset can be forced by holding the RESET pin
low for at least 1 µs. When RESET is asserted low, the
input FIFO pointers reset and the digital control circuitry
initializes. When RESET transitions high to start normal
operation, the DSPLL will be calibrated.
10
Preliminary Rev. 0.31
Si5540
Differential Output Circuitry
The Si5540 utilizes a current-mode logic (CML) architecture to drive the high speed serial output clock and data on
TXCLKOUT and TXDOUT. An example of output termination with ac coupling is shown in Figure 4. In applications
where direct dc coupling is possible, the 250 nF capacitors may be omitted. The differential peak-to-peak voltage
swing of the CML architecture is listed in Table 2 on page 5.
1.5 V
VDD
50 Ω
50 Ω
50 Ω
Zo = 50 Ω
Zo = 50 Ω
250 nF
250 nF
50 Ω
VDD
24 mA
Figure 4. CML Output Driver Termination (TXCLKOUT, TXDOUT)
Preliminary Rev. 0.31
11
Si5540
Si5540 Pinout: 99 BGA
10
9
8
7
6
5
4
3
2
1
RSVD_
VDD33
A
B
C
D
E
F
TXDIN[12]–
TXDIN[12]+
TXDIN[14]–
TXDIN[14]+
REFCLK–
REFCLK+
TXSQLCH
REFRATE
RSVD_
VDD33
TXDIN[10]+
TXDIN[10]–
TXDIN[8]+
TXDIN[8]–
TXDIN[6]+
TXDIN[6]–
TXDIN[4]+
TXDIN[4]–
TXDIN[2]+
TXDIN[11]+
TXDIN[11]–
TXDIN[9]+
TXDIN[9]–
TXDIN[13]–
TXDIN[13]+
TXDIN[15]–
TXDIN[15]+
TXCLKDSBL
RESET
VDD
REFSEL
VDD33
GND
TXCLKOUT+
TXCLKOUT–
GND
GND
GND
GND
GND
GND
GND
RSVD_
GND
GND
VDD
VDD
VDD
RSVD_
GND
GND
VDD
VDD
VDD
VDD
GND
RSVD_
GND
GND
VDD
VDD
VDD
VDD
GND
TXDOUT+
TXDOUT–
GND
TXDIN[7]+
TXDIN[7]–
TXDIN[5]+
RSVD_
GND
G
H
J
GND
VDD
VDD
VDD
VDD
GND
GND
GND
GND
GND
GND
BWSEL
NC
RSVD_
GND
TXDIN[3]+
TXDIN[0]+
TXDIN[3]–
TXDIN[0]–
TXDIN[1]+
TXDIN[1]–
TXMSBSEL
TXLOL
FIFORST
REXT
TXDIN[5]–
TXDIN[2]–
TXCLK16
IN+
TXCLK16
IN–
TXCLK16
OUT+
TXCLK16
OUT–
K
FIFOERR
Bottom View
Figure 5. Si5540 Pin Configuration (Bottom View)
12
Preliminary Rev. 0.31
Si5540
1
2
3
4
5
6
7
8
9
10
RSVD_
VDD33
A
B
C
D
E
F
REFRATE
TXSQLCH
REFCLK+
REFCLK-
TXDIN[14]+
TXDIN[14]–
TXDIN[12]+
TXDIN[12]–
RSVD_
VDD33
GND
TXCLKOUT+
TXCLKOUT–
GND
REFSEL
VDD33
TXCLKDSBL
RESET
VDD
TXDIN[15]+
TXDIN[15]–
TXDIN[13]+
TXDIN[13]–
TXDIN[11]+
TXDIN[11]–
TXDIN[9]+
TXDIN[9]–
TXDIN[7]+
TXDIN[7]–
TXDIN[5]+
TXDIN[5]–
TXDIN[2]–
TXDIN[10]+
TXDIN[10]–
TXDIN[8]+
TXDIN[8]–
TXDIN[6]+
TXDIN[6]–
TXDIN[4]+
TXDIN[4]–
TXDIN[2]+
GND
GND
GND
GND
GND
NC
GND
GND
GND
GND
RSVD_
GND
VDD
VDD
VDD
GND
RSVD_
GND
VDD
VDD
VDD
VDD
GND
RSVD_
GND
TXDOUT+
TXDOUT–
GND
VDD
VDD
VDD
VDD
GND
RSVD_
GND
G
H
J
VDD
VDD
VDD
VDD
GND
BWSEL
GND
GND
GND
GND
GND
RSVD_
GND
REXT
TXMSBSEL
TXDIN[1]–
TXDIN[1]+
TXDIN[3]–
TXDIN[0]–
TXDIN[3]+
TXDIN[0]+
TXLOL
TXCLK16
OUT–
TXCLK16
OUT+
TXCLK16
IN–
TXCLK16
IN+
K
FIFOERR
FIFORST
Top View
Figure 6. Si5540 Pin Configuration (Transparent Top View)
Preliminary Rev. 0.31
13
Si5540
Pin Descriptions: Si5540
Pin Number(s)
Pin Name
I/O
Signal Level
Description
Bandwidth Select DSPLL.
H3
BWSEL
I
LVTTL
This input selects loop bandwidth of the DSPLL.
BWSEL = 0: Loop bandwidth set to 12 kHz
BWSEL = 1: Loop bandwidth set to 50 kHz.
FIFO Error.
K1
K2
FIFOERR
O
LVTTL
LVTTL
This output is driven high when a FIFO over-
flow/underflow has occurred. This output will
stick high until reset by asserting FIFORST.
FIFO Reset.
FIFORST
GND
I
This input, when asserted high, resets the read/
write FIFO pointers to their initial state.
B1, C5–8, C2, D8,
D2, E8, E1–2, F8,
F2, G8, G2, H4–
8, H1
GND
GND.
No Connect.
H2
NC
—
I
Reserved for device testing; leave electrically
unconnected.
Differential Reference Clock.
A5–6
REFCLK+,
REFCLK–
LVPECL
LVTTL
The reference clock sets the operating fre-
quency of the PLL used to generate the output
clock frequency. The Si5540 will operate with
reference clock frequencies that are either 1/
16th or 1/64th the output clock rate.
Reference Frequency Select.
A2
REFRATE
I
This input configures the CMU to operate with
one of two possible reference clock frequen-
cies. When REFRATE = 1, the CMU will oper-
ate with a reference that is 1/16th the output
clock rate. When REFRATE = 0, the CMU will
operate with a reference that is 1/64th the out-
put clock rate.
Reference Clock Selection.
B3
C4
REFSEL
RESET
I
I
LVTTL
LVTTL
This inputs selects the reference clock source
used by the CMU. When REFSEL = 0, the low
speed data input clock, TXCLK16IN, is used as
the CMU reference. When REFSEL = 1, the ref-
erence clock provided on REFCLK is used.
Device Reset.
Forcing this input low for at least 1 µs will cause
a device reset. For normal operation, this pin
should be held high.
14
Preliminary Rev. 0.31
Si5540
Pin Number(s)
Pin Name
I/O
Signal Level
Description
External Bias Resistor.
J1
REXT
This resistor is used by onboard circuitry to
establish bias currents within the device. This
pin must be connected to GND through a
3.09 kΩ (1%) resistor.
Reserved Tie to Ground.
D3, E3, F3, G3,
J3
RSVD_GND
—
Must tie directly to GND for proper operation.
Reserved Tie to VDD33.
A3, B2
K5–6
RSVD_VDD33
—
I
Must tie directly to VDD33 for proper operation.
Differential Data Clock Input.
TXCLK16IN–,
TXCLK16IN+
LVDS
LVDS
The rising edge of this input clocks data present
on TXDIN into the device.
Divided Down Output Clock.
K3–4
TXCLK16OUT+,
TXCLK16OUT–
O
This clock output is generated by dividing down
the high speed output clock, TXCLKOUT, by a
factor of 16. It is intended for use in counter
clocking schemes that transfer data between
the system ASIC and the Si5540.
High Speed Clock Disable.
B4
TXCLKDSBL
I
O
I
LVTTL
CML
When this input is high, the output driver for
TXCLKOUT is disabled. In applications that do
not require the output data clock, the output
clock driver should be disabled to save power.
High Speed Clock Output.
C1, D1
TXCLKOUT+,
TXCLKOUT–
The high speed output clock, TXCLKOUT, is
generated by the PLL in the clock multiplier
unit. It’s frequency is nominally 16 or 64 times
the selected reference source.
Differential Parallel Data Input.
A7–10, B5–10,
C9–10, D9–10,
E9–10, F9–10,
G9–10, H9–10,
J5–10, K7–10
TXDIN[15:0]–,
TXDIN[15:0]+
LVDS
The 16-bit data word present on these pins is
multiplexed into a high speed serial stream and
output on TXDOUT. The data on these inputs is
clocked into the device by the rising edge of
TXCLKIN.
Differential High Speed Data Output.
F1, G1
TXDOUT+,
TXDOUT–
O
O
CML
The 16-bit word input on TXDIN[15:0] is multi-
plexed into a high speed serial stream that is
output on these pins. This output is updated by
the rising edge of TXCLKOUT.
CMU Loss-of-Lock.
J2
TXLOL
LVTTL
The output is asserted low when the CMU is not
phase locked to the selected reference source.
Preliminary Rev. 0.31
15
Si5540
Pin Number(s)
Pin Name
I/O
Signal Level
Description
Data Bus Transmit Order.
J4
TXMSBSEL
I
LVTTL
For TXMSBSEL = 0, data on TXDIN[0] is trans-
mitted first followed by TXDIN[1] through
TXDIN[15].
For TXMSBSEL = 1, TXDIN[15] is transmitted
first followed by TXDIN[14] through TXDIN[0].
Transmit Data Squelch.
A4
TXSQLCH
I
LVTTL
1.8 V
If TXSQLCH is asserted low, the output data
stream on TXDOUT will be forced to 0. If
TXSQLCH = 1, TX squelching is turned off.
Supply Voltage.
D4–7, E4–7,
F4–7, G4–7,
VDD
VDD
Nominally 1.8 V.
Digital Output Supply.
VDD33 1.8 V or 3.3 V
C3
VDD33
Must be tied to either 1.8 V or 3.3 V. When tied
to 3.3 V, LVTTL compatible output voltage
swings on TXLOL and FIFOERR are sup-
ported.
16
Preliminary Rev. 0.31
Si5540
Ordering Guide
Table 7. Ordering Guide
Part Number
Package
Temperature
Si5540-BC
99 BGA
–40°C to 85°C
Preliminary Rev. 0.31
17
Si5540
Package Outline
Figure 7 illustrates the package details for the Si5540. Table 8 lists the values for the dimensions shown in the
illustration.
A1 Ball Pad
Corner
A1 Ball Pad
Corner
A
D
10
9
8
7
6
5
4
3
2
1
A1
A
B
C
D
E
F
e
E
G
H
J
b
K
e
1.00 Ref
A2
Seating
Plane
Top View
Side View
Bottom View
Figure 7. 99-Ball Grid Array (BGA)
Table 8. Package Diagram Dimensions
Symbol
Millimeters
Nom
Min
1.30
0.31
0.65
—
Max
1.50
0.41
0.75
—
A
A1
A2
b
1.40
0.36
0.70
0.46
D
E
e
—
—
—
11.00
11.00
1.00
—
—
—
18
Preliminary Rev. 0.31
Si5540
NOTES:
Preliminary Rev. 0.31
19
Si5540
Contact Information
Silicon Laboratories Inc.
4635 Boston Lane
Austin, TX 78735
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Email: productinfo@silabs.com
Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-
sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap-
plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Silicon Laboratories, Silicon Labs, SiPHY, and DSPLL are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
20
Preliminary Rev. 0.31
相关型号：
554HC000249BGR
CMOS/TTL Output Clock Oscillator, 693.48299MHz Nom, ROHS COMPLIANT, SMD, 8 PIN
SILICON
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