554HD1417M000BGR [SILICON]
Oscillator;型号: | 554HD1417M000BGR |
厂家: | SILICON |
描述: | Oscillator |
文件: | 总12页 (文件大小:215K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Si554
QUAD FREQUENCY VCXO (10 MHZ TO 1.4 GHZ)
Features
ꢀ
Available with any-rate output
frequencies from 10–945 MHz and
select frequencies to 1.4 GHz
ꢀ
Internal fixed crystal frequency
ensures high reliability and low
aging
Si5602
ꢀ
ꢀ
Four selectable output frequencies ꢀ Available CMOS, LVPECL, LVDS
®
& CML outputs
3rd generation DSPLL with superior
jitter performance
ꢀ
ꢀ
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
ꢀ
3x better frequency stability than
SAW-based oscillators
ꢀ
Pb-free/RoHS-compliant
Ordering Information:
Applications
See page 7.
ꢀ
ꢀ
ꢀ
SONET/SDH
xDSL
10 GbE LAN / WAN
ꢀ
ꢀ
ꢀ
Low jitter clock generation
Optical Modules
Clock and data recovery
Pin Assignments:
See page 6.
Description
The Si554 quad frequency VCXO utilizes Silicon Laboratories advanced
DSPLL circuitry to provide a very low jitter clock for all output frequencies.
(Top View)
®
The Si554 is available with any-rate output frequency from 10 to 945 MHz
and select frequencies to 1400 MHz. Unlike traditional VCXOs where a
different crystal is required for each output frequency, the Si554 uses one
fixed crystal frequency to provide a wide range of output frequencies. This
IC based approach allows the crystal resonator to provide exceptional
frequency stability and reliability. In addition, DSPLL clock synthesis
provides superior supply noise rejection, simplifying the task of generating
low jitter clocks in noisy environments typically found in communication
systems. The Si554 IC-based VCXO is factory configurable for a wide
variety of user specifications including frequency, supply voltage, output
format, tuning slope, and temperature stability. Specific configurations are
factory programmed at time of shipment, thereby eliminating long lead times
associated with custom oscillators.
FS[1]
7
VC
VDD
1
2
3
6
5
4
OE
CLK–
CLK+
GND
8
FS[0]
Functional Block Diagram
VDD
CLK- CLK+
Any-rate
10–1400 MHz
DSPLL®
Fixed
Frequency XO
FS0
FS1
Clock Synthesis
ADC
Vc
OE
GND
Rev. 0.5 7/06
Copyright © 2006 by Silicon Laboratories
Si554
Si554
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol
Test Condition
3.3 V option
2.5 V option
1.8 V option
Min
2.97
2.25
1.71
Typ
3.3
2.5
1.8
Max
3.63
2.75
1.89
Units
1
V
DD
Supply Voltage
V
Supply Current
I
Output enabled
LVPECL
CML
DD
—
—
—
—
130
117
108
98
120
108
99
mA
LVDS
CMOS
90
TriState mode
—
0.75 x V
—
60
—
—
—
70
—
Output Enable (OE)
and Frequency Select FS[1:0]
V
IH
DD
2
V
V
0.5
85
IL
3
Operating Temperature Range
T
–40
ºC
A
Notes:
1. Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 7 for further details.
2. OE and FS[1:0] pins include a 17 kΩ pullup resistor to VDD. Pulling OE to ground causes outputs to tristate.
3. If the device is powered up below –20 ºC and the ambient temperature rises by approximately 105 ºC during normal
operation, the device will perform a one-time recalibration. The output is squelched for approximately 2–3 ms during
this recalibration.
Table 2. VC Control Voltage Input
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
1,2,3
Control Voltage Tuning Slope
K
10 to 90% of V
—
45
90
—
ppm/V
V
DD
135
180
4
Control Voltage Linearity
L
BSL
–5
–10
9.3
500
—
±1
±5
+5
+10
10.7
—
VC
%
Incremental
Modulation Bandwidth
BW
10.0
—
kHz
kΩ
V
V Input Impedance
Z
C
VC
Nominal Control Voltage
V
@ f
3/8 x V
DD
—
CNOM
O
Control Voltage Tuning Range
V
0
V
V
C
DD
Notes:
1. Positive slope; selectable option by part number. See Section 3. "Ordering Information" on page 7.
2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.
3. KV variation is ±28% of typical values.
4. BSL determined from deviation from best straight line fit with VC ranging from 10 to 90% of VDD. Incremental slope
determined with VC ranging from 10 to 90% of VDD
.
2
Rev. 0.5
Si554
Table 3. CLK± Output Frequency Characteristics
Parameter
Symbol
Test Condition
LVDS/CML/LVPECL
CMOS
Min
10
Typ
—
Max
Units
1,2,3
f
945
160
O
Nominal Frequency
MHz
10
—
1,4
Temperature Stability
∆f/f
T = –40 to +85 ºC
–20
–50
–100
—
—
—
+20
+50
+100
O
A
ppm
1,4
Absolute Pull Range
Aging
APR
±25
—
—
—
±150
±10
ppm
ppm
Frequency drift over 15
year life.
5
Power up Time
tOSC
—
—
—
—
10
20
ms
ms
Settling Time After FS[1:0] Change
t
Both FS[1] and FS[0]
FRQ
changing simultaneously
Notes:
1. See Section 3. "Ordering Information" on page 7 for further details.
2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz.
3. Nominal output frequency set by VCNOM = 3/8 x VDD
.
4. Selectable parameter specified by part number.
5. Time from power up or tristate mode to fO (to within ±1 ppm of fO).
Table 4. CLK± Output Levels and Symmetry
Parameter
Symbol
Test Condition
mid-level
Min
DD – 1.42
1.1
Typ
—
Max
VDD – 1.25
1.9
Units
V
1
LVPECL Output Option
V
V
O
VOD
VSE
swing (diff)
—
VPP
VPP
swing (single-ended)
mid-level
0.5
—
0.93
2
LVDS Output Option
V
1.125
0.32
1.20
0.40
1.275
0.50
V
O
swing (diff)
VOD
VPP
2
CML Output Option
VO
mid-level
—
V
– 0.75
—
1.20
VDD
0.4
V
DD
VOD
VOH
VOL
swing (diff)
0.70
0.95
—
VPP
3
CMOS Output Option
I
= 32 mA
0.8 x VDD
OH
V
IOL = 32 mA
—
—
—
—
Rise/Fall time (20/80%)
Symmetry (duty cycle)
tR, F
t
LVPECL/LVDS/CML
CMOS with CL = 15 pF
—
350
—
ps
ns
1
SYM
LVPECL:
LVDS:
V
– 1.3 V (diff)
DD
45
—
55
%
1.25 V (diff)
/2
CMOS:
V
DD
Notes:
1. 50 Ω to VDD – 2.0 V.
2. Rterm = 100 Ω (differential).
3. CL = 15 pF
Rev. 0.5
3
Si554
Table 5. CLK± Output Phase Jitter
Parameter
Symbol
Test Condition
Kv = 45 ppm/V
Min
Typ
Max
Units
1,2,3
Phase Jitter (RMS)
for F > 500 MHz
φJ
ps
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.35
0.38
—
—
OUT
Kv = 90 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.43
0.41
—
—
Kv = 135 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.52
0.46
—
—
Kv = 180 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.64
0.52
—
—
1,2,3
Phase Jitter (RMS)
for F of 125 to 500 MHz
φJ
Kv = 45 ppm/V
ps
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.42
0.58
—
—
OUT
Kv = 90 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.48
0.60
—
—
Kv = 135 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.57
0.64
—
—
Kv = 180 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.67
0.68
—
—
Notes:
1. Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, and AN266 for further information.
2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.
3. See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply
rejection (PSR) advantage of Si55x versus SAW-based solutions.
Table 6. CLK± Output Period Jitter
Parameter
Period Jitter*
Symbol
Test Condition
RMS
Min
—
Typ
2
Max
—
Units
J
ps
PER
for F < 160 MHz
OUT
Peak-to-Peak
—
14
—
*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information.
4
Rev. 0.5
Si554
Table 7. CLK± Output Phase Noise (Typical)
Configuration
f
74.25 MHz
45 ppm/V
CMOS
300 MHz
90 ppm/V
LVPECL
622.08 MHz
45 ppm/V
LVPECL
Units
C
K
V
Output
Offset Frequency (f)
L (f)
–94
–117
–128
–135
–138
–143
n/a
–74
–98
–77
100 Hz
1 kHz
10 kHz
100 kHz
1 MHz
–101
–114
–118
–128
–144
–147
–112
–122
–134
–144
–147
dBc/Hz
10 MHz
100 MHz
Table 8. Absolute Maximum Ratings1
Parameter
Supply Voltage
Symbol
Rating
–0.5 to +3.8
Units
Volts
Volts
ºC
V
DD
Input Voltage (any input pin)
Storage Temperature
V
–0.5 to V + 0.3
I
DD
T
–55 to +125
>2500
260
S
ESD Sensitivity (HBM, per JESD22-A114)
ESD
Volts
ºC
2
Soldering Temperature (Pb-free profile)
T
PEAK
2
Soldering Temperature Time @ T
(Pb-free profile)
t
10
seconds
PEAK
P
Notes:
1. Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional
operation or specification compliance is not implied at these conditions.
2. Refer to Si5xx Packaging FAQ available for download from www.silabs.com/VCXO for further information, including
soldering profiles.
Table 9. Environmental Compliance
The Si554 meets the following qualification test requirements.
Parameter
Conditions/ Test Method
MIL-STD-883F, Method 2002.3 B
MIL-STD-883F, Method 2007.3 A
MIL-STD-883F, Method 203.8
MIL-STD-883F, Method 1014.7
MIL-STD-883F, Method 2016
Mechanical Shock
Mechanical Vibration
Solderability
Gross & Fine Leak
Resistance to Solvents
Rev. 0.5
5
Si554
2. Pin Descriptions
(Top View)
FS[1]
7
VC
VDD
1
6
5
4
OE
2
3
CLK–
CLK+
GND
8
FS[0]
Table 10. Si554 Pin Descriptions
Type
Pin
Name
Function
1
V
Analog Input
Control Voltage
C
Output Enable:
2
OE*
Input
0 = clock output disabled (outputs tri-stated)
1 = clock output enabled
3
4
GND
Ground
Output
Output
Electrical and Case Ground
Oscillator Output
CLK+
CLK–
(N/A for CMOS)
Complementary Output
(N/C for CMOS)
5
6
7
8
V
Power
Input
Input
Power Supply Voltage
Frequency Select MSB
Frequency Select LSB
DD
FS[1]*
FS[0]*
*Note: FS[1:0] and OE include a 17 kΩ pullup resistor to VDD. Consult Section 3. "Ordering Information" on page 7 for details
on frequency value ordering.
6
Rev. 0.5
Si554
3. Ordering Information
The Si554 was designed to support a variety of options including frequency, temperature stability, tuning slope,
output format, and V Specific device configurations are programmed into the Si554 at time of shipment.
Configurations are specified using the Part Number Configuration chart shown below. Silicon Labs provides a web
browser-based part number configuration utility to simplify this process. Refer to
.
DD
www.silabs.com/VCXOPartNumber to access this tool and for further ordering instructions. The Si554 VCXO
series is supplied in an industry-standard, RoHS compliant, lead-free, 8-pad, 5 x 7 mm package. Tape and reel
packaging is an ordering option.
X
X
B
G
R
554
XXXXXX
R = Tape & Reel
Blank = Trays
554 Quad VCXO
Product Family
Operating Temp Range (°C)
–40 to +85 °C
G
Device Revision Letter
6-digit Frequency Designator Code
Four unique frequencies can be specified within the following bands of frequencies: 10 to
945 MHz, 970 to 1134 MHz, and 1213 to 1417 MHz. A six digit code will be assigned for
the specified combination of frequencies. Codes > 000100 refer to XOs programmed with
the lowest frequency value selected when FS[1:0] = 00, and the highest value when
FS[1:0] = 11. Six digit codes < 000100 refer to XOs programmed with the highest
frequency value selected when FS[1:0] = 00, and the lowest value when FS[1:0] = 11.
1st Option Code
VDD Output Format Output Enable Polarity
2nd Option Code
A
B
C
D
E
F
G
H
J
K
M
N
P
Q
R
S
T
3.3 LVPECL
3.3 LVDS
3.3 CMOS
3.3 CML
2.5 LVPECL
2.5 LVDS
2.5 CMOS
2.5 CML
1.8 CMOS
1.8 CML
3.3 LVPECL
3.3 LVDS
3.3 CMOS
3.3 CML
2.5 LVPECL
2.5 LVDS
2.5 CMOS
2.5 CML
1.8 CMOS
1.8 CML
High
High
High
High
High
High
High
High
High
High
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Temperature
Stability
± ppm (max)
Tuning Slope
Minimum APR
(±ppm)
@ 2.5 V
75
Kv
ppm/V (typ)
180
Code
A
B
C
D
@ 3.3 V
100
30
150
80
@ 1.8 V
25
Note 6
75
25
Note 6
50
100
100
50
50
20
90
180
90
45
Note 6
125
30
Note 6
75
E
F
25
100
50
135
Notes:
1. For best jitter and phase noise performance, always choose the smallest Kv that meets
the application’s minimum APR requirements. Unlike SAW-based solutions which
require higher higher Kv values to account for their higher temperature dependence,
the Si55x series provides lower Kv options to minimize noise coupling and jitter in real-
world PLL designs. See AN255 and AN266 for more information.
2. APR is the ability of a VCXO to track a signal over the product lifetime. A VCXO with an
APR of ±25 ppm is able to lock to a clock with a ±25 ppm stability, over 15 years.
3. Nominal Pull range (±) = 0.5 x VDD x tuning slope.
4. Nominal Absolute Pull Range (±APR) = Pull range – stability – lifetime aging
=0.5 x VDD x tuning slope – stability – 10 ppm
5. Minimum APR values noted above include worst case values for all parameters.
6. Combination not available.
U
V
W
Note:
CMOS available to 160 MHz.
Example Part Number: 554AF000124BGR is a 5 x 7 mm Quad VCXO in an 8 pad package. Since the six digit code (000124) is > 000100, f0 is
622.08 MHz (lowest frequency), f1 is 644.53125, f2 is 657.42188, and f3 is 669.32658 MHz (highest frequency), with a 3.3 V supply, LVPECL
output, and Output Enable active high polarity. Temperature stability is specified as ±50 ppm and the tuning slope is 135 ppm/V. The part is specified
for a –40 to +85 C° ambient temperature range operation and is shipped in tape and reel format.
Figure 1. Part Number Convention
Rev. 0.5
7
Si554
4. Outline Diagram and Suggested Pad Layout
Figure 2 illustrates the package details for the Si554. Table 11 lists the values for the dimensions shown in the
illustration.
Figure 2. Si554 Outline Diagram
Table 11. Package Diagram Dimensions (mm)
Dimension
Min
1.45
1.2
Nom
1.65
Max
1.85
1.6
A
b
1.4
c
0.60 TYP
1.17
d
0.97
6.10
1.37
6.30
D
7.00 BSC
6.2
D1
e
2.54 BSC
5.00 BSC
4.40
E
E1
L
4.30
1.07
0.8
4.50
1.47
1.2
1.27
M
1.0
S
1.815 BSC
0.7 REF
—
R
aaa
bbb
ccc
ddd
—
—
—
—
0.15
0.15
0.10
0.10
—
—
—
8
Rev. 0.5
Si554
5. 8-Pin PCB Land Pattern
Figure 3 illustrates the 8-pin PCB land pattern for the Si554. Table 12 lists the values for the dimensions shown in
the illustration.
Figure 3. Si554 PCB Land Pattern
Table 12. PCB Land Pattern Dimensions (mm)
Dimension
Min
Max
D2
D3
5.08 REF
5.705 REF
2.54 BSC
4.20 REF
e
E2
GD
GE
VD
VE
0.84
2.00
—
—
8.20 REF
7.30 REF
1.70 TYP
1.545 TYP
2.15 REF
1.3 REF
X1
X2
Y1
Y2
ZD
—
—
6.78
6.30
ZE
Note:
1. Dimensioning and tolerancing per the ANSI Y14.5M-1994
specification.
2. Land pattern design follows IPC-7351 guidelines.
3. All dimensions shown are at maximum material condition
(MMC).
4. Controlling dimension is in millimeters (mm).
Rev. 0.5
9
Si554
DOCUMENT CHANGE LIST
Revision 0.3 to Revision 0.4
ꢀ Updated Table 1, “Recommended Operating
Conditions,” on page 2.
ꢁ Added maximum supply current specifications.
ꢁ Specified relationship between temperature at startup
and operation temperature.
ꢀ Added Output Enable active polarity as an option in
Figure 1, “Part Number Convention,” on page 7.
Revision 0.4 to Revision 0.5
ꢀ Updated Note 3 in Table 1, “Recommended
Operating Conditions,” on page 2.
ꢀ Updated Figure 1, “Part Number Convention,” on
page 7.
10
Rev. 0.5
Si554
NOTES:
Rev. 0.5
11
Si554
CONTACT INFORMATION
Silicon Laboratories Inc.
4635 Boston Lane
Austin, TX 78735
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Email: VCXOinfo@silabs.com
Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
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Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
12
Rev. 0.5
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