562BAA002529BBG [SILICON]
LVDS Output Clock Oscillator,;
| 型号： | 562BAA002529BBG |
| 厂家： | 
SILICON |
| 描述： | LVDS Output Clock Oscillator, |
| 文件： | 总17页 (文件大小：949K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
™
Ultra Series Crystal Oscillator
Si562 Data Sheet
Ultra Low Jitter Quad Any-Frequency XO (90 fs), 0.2 to 3000
MHz
KEY FEATURES
• Available with any four selectable
frequencies from 200 kHz to 3000 MHz
The Si562 Ultra Series™ oscillator utilizes Silicon Laboratories’ advanced 4th gener-
ation DSPLL® technology to provide an ultra-low jitter, low phase noise clock at four
selectable frequencies. The device is factory-programmed to provide any four se-
lectable frequencies from 0.2 to 3000 MHz with <1 ppb resolution and maintains ex-
ceptionally low jitter for both integer and fractional frequencies across its operating
range. The Si562 offers excellent reliability and frequency stability as well as guar-
anteed aging performance. On-chip power supply filtering provides industry-leading
power supply noise rejection, simplifying the task of generating low jitter clocks in
noisy systems that use switched-mode power supplies. Offered in industry-standard
3.2x5 mm and 5x7 mm footprints, the Si562 has a dramatically simplified supply
chain that enables Silicon Labs to ship custom frequency samples 1-2 weeks after
receipt of order. Unlike a traditional XO, where a different crystal is required for each
output frequency, the Si562 uses one simple crystal and a DSPLL IC-based ap-
proach to provide the desired output frequencies. This process also guarantees
100% electrical testing of every device. The Si562 is factory-configurable for a wide
variety of user specifications, including frequency, output format, and OE pin loca-
tion/polarity. Specific configurations are factory-programmed at time of shipment,
eliminating the long lead times associated with custom oscillators.
• Ultra low jitter: 90 fs RMS typical
(12 kHz – 20 MHz)
• Excellent PSRR and supply noise
immunity: –80 dBc Typ
• 20 ppm temp stability (-40 to 85 °C)
• 3.3 V, 2.5 V and 1.8 V V supply
DD
operation from the same part number
• LVPECL, LVDS, CML, HCSL, CMOS, and
Dual CMOS output options
• 3.2x5, 5x7 mm package footprints
• Samples available with 1-2 week lead times
APPLICATIONS
• 100G/200G/400G OTN, coherent optics
• 10G/25G/40G/100G Ethernet
Pin Assignments
• 3G-SDI/12G-SDI/24G-SDI broadcast video
FS1
• Servers, switches, storage, NICs, search
acceleration
7
1
2
3
6
5
4
VDD
CLK-
CLK+
OE/NC
NC/OE
GND
• Test and measurement
• Clock and data recovery
• FPGA/ASIC clocking
8
FS0
(Top View)
Pin #
Descriptions
Selectable via ordering option
Fixed
Frequency
Crystal
Frequency
Flexible
DSPLL
1, 2
Low
Noise
Driver
OE = Output enable; NC = No Connect
DCO
Digital
Phase
Detector
Digital
Loop
Filter
3
4
5
6
7
8
GND = Ground
OSC
Phase Error
Cancellation
Flexible
Formats,
1.8V – 3.3V
Operation
CLK+ = Clock output
Phase Error
Fractional
Divider
CLK- = Complementary clock output. Not used for CMOS.
VDD = Power supply
NVM
Control
Power Supply Regulation
FS1 = Frequency Select 1
OE, Frequency Select
(Pin Control)
Built-in Power Supply
Noise Rejection
FS0 = Frequency Select 0
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Rev. 1.0
Si562 Data Sheet
Ordering Guide
1. Ordering Guide
The Si562 XO supports a variety of options including frequency, output format, and OE pin location/polarity, as shown in the chart
below. Specific device configurations are programmed into the part at time of shipment, and samples are available in 1-2 weeks. Silicon
Laboratories provides an online part number configuration utility to simplify this process. Refer to www.silabs.com/oscillators to access
this tool and for further ordering instructions.
XO Series
Description
Temp Stability Total Stability2
± 20 ppm
± 50 ppm
Package
5x7 mm
Temperature Grade
562
Quad Frequency
A
A
B
G
-40 to 85 °C
3.2x5 mm
562
A
A
A
-
-
-
-
-
-
A
B
G
R
Device Revision
Order
Option
A
OE
Pin
Pin 1
Signal Format
VDD Range
OE Polarity
LVPECL
LVDS
2.5, 3.3 V
A
Active High
Active Low
Active High
Active Low
Reel
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
B
C
D
E
B
Pin 1
R
Tape and Reel
Coil Tape
CMOS
CML
C Pin 2
D Pin 2
<Blank>
HCSL
Frequency Code3
Description
Dual CMOS
(In-Phase)
Dual CMOS
1.8, 2.5, 3.3 V
F
Four unique frequencies can be specified
within the supported range of the selected
signal format. The frequencies can be
arranged in any order from FS[1:0]=00 to
FS[1:0]=11. A six digit numeric code will be
assigned for the specific combination of
frequencies.
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
G
X
(Complementary)
Custom1
xxxxxx
Notes:
1. Contact Silicon Labs for non-standard configurations.
2. Total stability includes temp stability, initial accuracy, load pulling, VDD variation, and 20 year aging at 70 °C.
3. Create custom part numbers at www.silabs.com/oscillators.
1.1 Technical Support
Frequently Asked Questions (FAQ)
Oscillator Phase Noise Lookup Utility
Quality and Reliability
www.silabs.com/Si562-FAQ
www.silabs.com/oscillator-phase-noise-lookup
www.silabs.com/quality
Development Kits
www.silabs.com/oscillator-tools
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Rev. 1.0 | 2
Si562 Data Sheet
Electrical Specifications
2. Electrical Specifications
Table 2.1. Electrical Specifications
Test Condition/Comment
VDD = 1.8 V, 2.5 or 3.3 V ± 5%, TA = –40 to 85 ºC
Parameter
Temperature Range
Frequency Range
Symbol
TA
Min
–40
0.2
0.2
0.2
3.135
2.375
1.71
—
Typ
—
Max
85
Unit
ºC
FCLK
LVPECL, LVDS, CML
HCSL
—
3000
400
250
3.465
2.625
1.89
160
157
130
135
145
—
MHz
MHz
MHz
V
—
CMOS, Dual CMOS
3.3 V
—
Supply Voltage
Supply Current
VDD
3.3
2.5
1.8
110
90
85
85
95
73
—
2.5 V
V
1.8 V
V
IDD
LVPECL (output enabled)
LVDS/CML (output enabled)
HCSL (output enabled)
CMOS (output enabled)
Dual CMOS (output enabled)
Tristate Hi-Z (output disabled)
Frequency stability Grade A
Frequency stability Grade A
mA
mA
mA
mA
mA
mA
ppm
ppm
—
—
—
—
—
Temperature Stability
–20
–50
20
Total Stability1
FSTAB
TR/TF
—
50
Rise/Fall Time
LVPECL/LVDS/CML
—
—
—
350
1.5
ps
ns
(20% to 80% VPP
)
CMOS / Dual CMOS
(CL = 5 pF)
0.5
HCSL, FCLK >50 MHz
All formats
—
—
—
—
—
—
—
—
—
550
ps
%
Duty Cycle
DC
VIH
VIL
45
55
Output Enable (OE)
Frequency Select (FS0, FS1)2
0.7 × VDD
—
V
—
—
—
—
—
0.3 × VDD
V
TD
Output Disable Time, FCLK > 10 MHz
Output Enable Time, FCLK > 10 MHz
Settling Time after FS Change
3
µs
µs
ms
ms
TE
20
10
10
TFS
tOSC
Powerup Time
Time from 0.9 × VDD until output fre-
quency (FCLK) within spec
LVPECL Output Option3
VOC
VO
Mid-level
VDD – 1.42
1.1
—
—
—
VDD – 1.25
1.9
V
Swing (diff, FCLK < 1.5 GHz)
VPP
VPP
Swing (diff, FCLK > 1.5 GHz)6
0.55
1.7
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Rev. 1.0 | 3
Si562 Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition/Comment
Mid-level (2.5 V, 3.3 V VDD)
Mid-level (1.8 V VDD)
Min
1.125
0.8
Typ
1.20
0.9
Max
1.275
1.0
Unit
V
LVDS Output Option4
VOC
V
VO
Swing (diff, FCLK < 1.5 GHz)
0.5
0.7
0.9
VPP
VPP
Swing (diff, FCLK > 1.5 GHz) 6
Output voltage high
0.25
0.5
0.8
HCSL Output Option5
VOH
VOL
VC
660
–150
250
0.6
800
0
850
150
550
1.0
mV
mV
mV
VPP
VPP
Output voltage low
Crossing voltage
410
0.8
0.55
CML Output Option (AC-Coupled)
VO
Swing (diff, FCLK < 1.5 GHz)
Swing (diff, FCLK > 1.5 GHz)6
0.3
0.9
CMOS Output Option
VOH
VOL
IOH = 8/6/4 mA for 3.3/2.5/1.8 V VDD 0.85 × VDD
IOL = 8/6/4 mA for 3.3/2.5/1.8 V VDD
—
—
—
V
V
—
0.15 × VDD
Notes:
1. Total Stability includes temperature stability, initial accuracy, load pulling, VDD variation, and aging for 20 yrs at 70 ºC.
2. OE includes a 50 kΩ pull-up to VDD for OE active high, or includes a 50 kΩ pull-down to GND for OE active low. FS0 and FS1
pins each include a 50 kΩ pull-up to VDD. NC (No Connect) pins include a 50 kΩ pull-down to GND.
3. Rterm = 50 Ω to VDD – 2.0 V (see Figure 4.1).
4. Rterm = 100 Ω (differential) (see Figure 4.2).
5. Rterm = 50 Ω to GND (see Figure 4.2).
6. Refer to the figure below for Typical Clock Output Swing Amplitudes vs Frequency.
Figure 2.1. Typical Clock Output Swing Amplitudes vs. Frequency
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Rev. 1.0 | 4
Si562 Data Sheet
Electrical Specifications
Table 2.2. Clock Output Phase Jitter and PSRR
VDD = 1.8 V, 2.5 or 3.3 V ± 5%, TA = –40 to 85 ºC
Parameter
Symbol
Test Condition/Comment
FCLK ≥ 200 MHz
Min
—
Typ
90
Max
140
160
125
Unit
fs
Phase Jitter (RMS, 12 kHz - 20 MHz)1
All Differential Formats
ϕJ
100 MHz ≤ FCLK < 200 MHz
LVPECL @ 156.25 MHz
—
105
95
fs
—
fs
Phase Jitter (RMS, 12 kHz - 20 MHz)1
CMOS / Dual CMOS Formats
ϕJ
10 MHz ≤ FCLK < 250 MHz
—
200
—
fs
Spurs Induced by External Power Supply
Noise, 50 mVpp Ripple. LVDS 156.25 MHz
Output
PSRR
100 kHz sine wave
200 kHz sine wave
500 kHz sine wave
1 MHz sine wave
-83
-83
-82
-85
dBc
Note:
1. Jitter inclusive of any spurs.
Table 2.3. 3.2 x 5 mm Clock Output Phase Noise (Typical)
Offset Frequency (f)
100 Hz
156.25 MHz LVDS
200 MHz LVDS
–100
644.53125 MHz LVDS
Unit
–105
–129
–136
–142
–150
–159
–160
–92
1 kHz
–126
–116
–125
–131
–138
–153
–154
10 kHz
–133
100 kHz
–140
dBc/Hz
1 MHz
–148
10 MHz
–161
20 MHz
–162
Offset Frequency (f)
156.25 MHz
LVPECL
200 MHz
LVPECL
644.53125 MHz
LVPECL
Unit
100 Hz
1 kHz
–109
–131
–135
–143
–150
–160
–161
–102
–126
–134
–141
–148
–162
–163
–92
–119
–124
–130
–138
–154
–155
10 kHz
100 kHz
1 MHz
dBc/Hz
10 MHz
20 MHz
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Rev. 1.0 | 5
Si562 Data Sheet
Electrical Specifications
Figure 2.2. Phase Jitter vs. Output Frequency
Phase jitter measured with Agilent E5052 using a differential-to-single ended converter (balun or buffer). Measurements collected for
>700 commonly used frequencies. Phase noise plots for specific frequencies are available using our free, online Oscillator Phase Noise
Lookup Tool at www.silabs.com/oscillators.
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Rev. 1.0 | 6
Si562 Data Sheet
Electrical Specifications
Table 2.4. Environmental Compliance and Package Information
Parameter
Test Condition
Mechanical Shock
Mechanical Vibration
Solderability
MIL-STD-883, Method 2002
MIL-STD-883, Method 2007
MIL-STD-883, Method 2003
MIL-STD-883, Method 1014
MIL-STD-883, Method 2036
1
Gross and Fine Leak
Resistance to Solder Heat
Moisture Sensitivity Level (MSL)
Contact Pads
Gold over Nickel
Note:
1. For additional product information not listed in the data sheet (e.g. RoHS Certifications, MDDS data, qualification data, REACH
Declarations, ECCN codes, etc.), refer to our "Corporate Request For Information" portal found here: www.silabs.com/support/
quality/Pages/RoHSInformation.aspx.
Table 2.5. Thermal Conditions
Package
Parameter
Symbol
ΘJA
ΘJB
TJ
Test Condition
Still Air, 85 °C
Still Air, 85 °C
Still Air, 85 °C
Still Air, 85 °C
Still Air, 85 °C
Still Air, 85 °C
Value
79.1
49.6
125
Unit
ºC/W
ºC/W
ºC
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Board
Max Junction Temperature
3.2×5 mm
8-pin CLCC
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Board
Max Junction Temperature
ΘJA
ΘJB
TJ
67.1
51.7
125
ºC/W
ºC/W
ºC
5×7 mm
8-pin CLCC
Table 2.6. Absolute Maximum Ratings1
Parameter
Symbol
TAMAX
TS
Rating
95
Unit
Maximum Operating Temp.
Storage Temperature
Supply Voltage
ºC
ºC
ºC
V
–55 to 125
–0.5 to 3.8
–0.5 to VDD + 0.3
2.0
VDD
Input Voltage
VIN
ESD HBM (JESD22-A114)
Solder Temperature2
HBM
TPEAK
kV
ºC
260
2
TP
20–40
sec
Solder Time at TPEAK
Notes:
1. Stresses beyond those listed in this table may cause permanent damage to the device. Functional operation specification
compliance is not implied at these conditions. Exposure to maximum rating conditions for extended periods may affect device
reliability.
2. The device is compliant with JEDEC J-STD-020.
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Rev. 1.0 | 7
Si562 Data Sheet
Dual CMOS Buffer
3. Dual CMOS Buffer
Dual CMOS output format ordering options support either complementary or in-phase signals for two identical frequency outputs. This
feature enables replacement of multiple XOs with a single Si562 device.
~
Complementary
Outputs
~
In-Phase
Outputs
Figure 3.1. Integrated 1:2 CMOS Buffer Supports Complementary or In-Phase Outputs
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Rev. 1.0 | 8
Si562 Data Sheet
Recommended Output Terminations
4. Recommended Output Terminations
The output drivers support both AC-coupled and DC-coupled terminations as shown in figures below.
VDD
VDD
R1
VDD (3.3V, 2.5V)
CLK+
VDD (3.3V, 2.5V)
CLK+
R1
R1
R1
50 Ω
50 Ω
50 Ω
50 Ω
CLK-
CLK-
LVPECL
Receiver
LVPECL
Receiver
Rp
Rp
Si56x
Si56x
R2
R2
R2
R2
AC-Coupled LVPECL – Thevenin Termination
DC-Coupled LVPECL – Thevenin Termination
VDD (3.3V, 2.5V)
50 Ω
VDD (3.3V, 2.5V)
50 Ω
CLK+
CLK+
R1
R2
R1
50 Ω
50 Ω
50 Ω
50 Ω
VDD
VDD
VTT
VTT
CLK-
Rp
CLK-
R2
50 Ω
50 Ω
LVPECL
Receiver
LVPECL
Receiver
Si56x
Si56x
Rp
AC-Coupled LVPECL - 50 Ω w/VTT Bias
DC-Coupled LVPECL - 50 Ω w/VTT Bias
Figure 4.1. LVPECL Output Terminations
AC-Coupled LVPECL
Termination Resistor Values
DC-Coupled LVPECL
Termination Resistor Values
VDD
R1
R2
Rp
VDD
3.3 V
2.5 V
R1
R2
3.3 V
2.5 V
127 Ω
250 Ω
82.5 Ω
62.5 Ω
130 Ω
90 Ω
127 Ω
250 Ω
82.5 Ω
62.5 Ω
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Rev. 1.0 | 9
Si562 Data Sheet
Recommended Output Terminations
(3.3V, 2.5V, 1.8V)
VDD
(3.3V, 2.5V, 1.8V)
VDD
50 Ω
50 Ω
33 Ω
CLK+
CLK-
CLK+
50 Ω
50 Ω
100 Ω
33 Ω
50 Ω
CLK-
50 Ω
LVDS
Receiver
HCSL
Receiver
Si56x
Si56x
DC-Coupled LVDS
Source Terminated HCSL
(3.3V, 2.5V, 1.8V)
(3.3V, 2.5V, 1.8V)
VDD
VDD
50 Ω
CLK+
CLK+
50 Ω
100 Ω
CLK-
CLK-
50 Ω
50 Ω
50 Ω
50 Ω
LVDS
Receiver
HCSL
Receiver
Si56x
Si56x
AC-Coupled LVDS
Destination Terminated HCSL
Figure 4.2. LVDS and HCSL Output Terminations
(3.3V, 2.5V, 1.8V)
VDD
(3.3V, 2.5V, 1.8V)
VDD
CLK
50 Ω
50 Ω
CLK+
CLK-
50 Ω
10 Ω
100 Ω
NC
CMOS
Receiver
CML
Receiver
Si56x
Si56x
CML Termination without VCM
Single CMOS Termination
(3.3V, 2.5V, 1.8V)
VDD
(3.3V, 2.5V, 1.8V)
VDD
CLK+
50 Ω
50 Ω
CLK+
50 Ω
50 Ω
50 Ω
50 Ω
VCM
10 Ω
10 Ω
CLK-
CLK-
CML
Receiver
CMOS
Receivers
Si56x
Si56x
CML Termination with VCM
Dual CMOS Termination
Figure 4.3. CML and CMOS Output Terminations
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Rev. 1.0 | 10
Si562 Data Sheet
Package Outline
5. Package Outline
5.1 Package Outline (5x7 mm)
The figure below illustrates the package details for the 5x7 mm Si562. The table below lists the values for the dimensions shown in the
illustration.
Figure 5.1. Si562 (5x7 mm) Outline Diagram
Table 5.1. Package Diagram Dimensions (mm)
Dimension
Min
1.07
0.40
0.45
1.30
0.50
0.50
Nom
1.18
Max
1.33
0.60
0.65
1.50
0.70
0.70
Dimension
Min
6.10
1.07
1.00
1.70
Nom
6.20
Max
6.30
1.27
1.20
1.90
A
E1
L
A2
0.50
1.17
A3
0.55
L1
1.10
b
1.40
p
--
b1
0.60
R
0.70 REF
0.15
c
0.60
aaa
bbb
ccc
ddd
eee
D
5.00 BSC
4.40
0.15
D1
4.30
4.50
0.08
e
E
2.54 BSC
7.00 BSC
0.10
0.05
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
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Rev. 1.0 | 11
Si562 Data Sheet
Package Outline
5.2 Package Outline (3.2x5 mm)
The figure below illustrates the package details for the 5x3.2 mm Si562. The table below lists the values for the dimensions shown in
the illustration.
Figure 5.2. Si562 (3.2x5 mm) Outline Diagram
Table 5.2. Package Diagram Dimensions (mm)
Dimension
MIN
1.02
0.50
0.45
0.54
0.54
NOM
1.17
MAX
1.33
0.60
0.55
0.74
0.75
Dimension
MIN
NOM
2.85 BSC
0.9
MAX
A
E1
L
A2
0.55
0.8
1.0
A3
0.50
L1
0.45
0.05
0.15
0.55
0.65
0.15
0.25
b
0.64
L2
0.10
b1
0.64
L3
0.20
D
5.00 BSC
4.65 BSC
1.27 BSC
1.625 TYP
3.20 BSC
aaa
bbb
ccc
ddd
eee
0.15
D1
0.15
e
e1
0.08
0.10
E
0.05
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
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Rev. 1.0 | 12
Si562 Data Sheet
PCB Land Pattern
6. PCB Land Pattern
6.1 PCB Land Pattern (5x7 mm)
The figure below illustrates the 5x7 mm PCB land pattern for the Si562. The table below lists the values for the dimensions shown in
the illustration.
Figure 6.1. Si562 (5x7 mm) PCB Land Pattern
Table 6.1. PCB Land Pattern Dimensions (mm)
Dimension
(mm)
4.20
6.05
2.54
1.55
Dimension
(mm)
1.95
1.80
0.75
C1
C2
E
Y1
X2
Y2
X1
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a
Fabrication Allowance of 0.05 mm.
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020D specification for Small Body Components.
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Rev. 1.0 | 13
Si562 Data Sheet
PCB Land Pattern
6.2 PCB Land Pattern (3.2x5 mm)
The figure below illustrates the 3.2x5.0 mm PCB land pattern for the Si562. The table below lists the values for the dimensions shown
in the illustration.
Figure 6.2. Si562 (3.2x5 mm) PCB Land Pattern
Table 6.2. PCB Land Pattern Dimensions (mm)
Dimension
(mm)
2.70
1.27
4.30
0.74
Dimension
(mm)
0.90
1.60
0.70
C1
E
X2
Y1
Y2
E1
X1
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a
Fabrication Allowance of 0.05 mm.
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
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Si562 Data Sheet
Top Marking
7. Top Marking
The figure below illustrates the mark specification for the Si562. The table below lists the line information.
Figure 7.1. Mark Specification
Table 7.1. Si562 Top Mark Description
Line
Position
1–8
Description
1
2
"Si562", xxx = Ordering Option 1, Option 2, Option 3 (e.g. Si562AAA)
1–6
Frequency Code
(6-digit custom code as described in the Ordering Guide)
3
Trace Code
Pin 1 orientation mark (dot)
Product Revision (B)
Position 1
Position 2
Position 3–5
Position 6–7
Position 8–9
Tiny Trace Code (3 alphanumeric characters per assembly release instructions)
Year (last two digits of the year), to be assigned by assembly site (ex: 2017 = 17)
Calendar Work Week number (1–53), to be assigned by assembly site
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Si562 Data Sheet
Revision History
8. Revision History
Revision 1.0
June, 2018
• Initial release.
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