564AAAA002028ABG [SILICON]
LVPECL Output Clock Oscillator,;
| 型号： | 564AAAA002028ABG |
| 厂家： | 
SILICON |
| 描述： | LVPECL Output Clock Oscillator, 振荡器 |
| 文件： | 总35页 (文件大小：1035K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
™
Ultra Series Crystal Oscillator
Si564 Data Sheet
Ultra Low Jitter I2C Programmable XO (90 fs), 0.2 to
3000 MHz
KEY FEATURES
• I2C programmable to any frequency from 0.2 to
3000 MHz with < 1 ppb resolution
The Si564 Ultra Series™ oscillator utilizes Silicon Laboratories’ advanced 4th
generation DSPLL® technology to provide an ultra-low jitter, low phase noise
clock at any output frequency. The device is user-programmed via simple
I2C commands to provide any frequency from 0.2 to 3000 MHz with <1 ppb
resolution and maintains exceptionally low jitter for both integer and fraction-
al frequencies across its operating range. The Si564 offers excellent reliabili-
ty and frequency stability as well as guaranteed aging performance. On-chip
power supply filtering provides industry-leading power supply noise rejection,
simplifying the task of generating low jitter clocks in noisy systems that use
switched-mode power supplies. The Si564 has a dramatically simplified sup-
ply chain that enables Silicon Labs to ship custom frequency samples 1-2
weeks after receipt of order. Unlike a traditional XO, where a different crystal
is required for each output frequency, the Si564 uses one simple crystal and
a DSPLL IC-based approach to provide the desired output frequency. The
Si564 is factory-configurable for a wide variety of user specifications, includ-
ing startup frequency, I2C address, output format, and OE pin location/
polarity. Specific configurations are factory-programmed at time of shipment,
eliminating the long lead times associated with custom oscillators.
• Ultra low jitter: 90 fs RMS Typ (12 kHz – 20 MHz)
• Configure up to 4 pin-selectable startup frequencies
• I2C interface supports 100 kbps, 400 kbps, and 1
Mbps (Fast Mode Plus)
• Excellent PSRR and supply noise immunity: –80
dBc Typ
• 3.3 V, 2.5 V and 1.8 V V supply operation from
DD
the same part number
• LVPECL, LVDS, CML, HCSL, CMOS, and Dual
CMOS output options
• 3.2x5, 5x7 mm package footprints
• Samples available with 1-2 week lead times
APPLICATIONS
• 100G/200G/400G OTN, coherent optics, PAM4
• 10G/40G/100G optical ethernet
Pin Assignments
• 3G-SDI/12G-SDI/24G-SDI broadcast video
• Servers, switches, storage, search acceleration
• Test and measurement
SDA
7
OE/FS/NC
NC/OE/FS
GND
1
2
3
6
5
4
VDD
CLK–
CLK+
• FPGA/ASIC clocking
8
SCL
(Top View)
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Rev. 1.0
Fixed
Frequency
Crystal
Frequency
Flexible
DSPLL
Pin #
Descriptions
Selectable via ordering option
Low
Noise
Driver
DCO
1, 2
Digital
Phase
Detector
Digital
Loop
Filter
OSC
Phase Error
Cancellation
OE = Output enable; FS = Frequency Select; NC = No connect
Flexible
Formats,
Phase Error
3
4
5
6
7
8
GND = Ground
1.8V – 3.3V
Operation
Fractional
Divider
NVM
Control
CLK+ = Clock output
Power Supply Regulation
CLK- = Complementary clock output. Not used for CMOS.
VDD = Power supply
OE, Frequency Select
(I2C and Pin Control)
Built-in Power Supply
Noise Rejection
SDA = I2C Serial Data
SCL = I2C Serial Clock
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Rev. 1.0
Si564 Data Sheet
Ordering Guide
1. Ordering Guide
The Si564 XO supports a variety of options including startup frequency, output format, and OE pin location/polarity, as shown in the
chart below. Specific device configurations are programmed into the part at time of shipment, and samples are available in 1-2 weeks.
Silicon Laboratories provides an online part number configuration utility to simplify this process. Refer to www.silabs.com/oscillators to
access this tool and for further ordering instructions.
XO Series
Description
Temp Stability Total Stability2
± 20 ppm ± 50 ppm
Temperature Grade
Package
5x7 mm
564
I2C Oscillator
A
A
B
G
-40 to 85 °C
3.2x5 mm
564
A
A
A
A
-
-
-
-
-
-
A
B
G
R
Device Revision
Order
Option
Code
Supported Frequency Range
Code
Reel
Signal Format
VDD Range
A
B
C
D
0.2-3000 MHz
0.2-1500 MHz
0.2-800 MHz
R
Tape and Reel
Coil Tape
LVPECL
LVDS
2.5, 3.3 V
A
B
C
D
E
<Blank>
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
CMOS
CML
0.2-325 MHz (CMOS available to 250 MHz)
HCSL
Frequency
Code3
Pinout Option
Dual CMOS
(In-Phase)
Dual CMOS
Description
1.8, 2.5, 3.3 V
F
FS0
FS1
Code
OE Pin OE Polarity
(Dual) (Quad)
The Si564 supports one,
two, or four user-defined
startup frequencies in the
range selected by the
Supported Frequency
Range code. A user-
defined 7-bit I2C address
is supported. Each unique
startup configuration and
I2C address combination
is assigned a 6-digit code.
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
G
X
--
--
--
(Complementary)
A
B
C
D
E
F
Pin 1
Pin 1
Pin 2
Pin 2
Pin 1
Pin 1
Pin 2
Pin 2
--
Active High
Active Low
Active High
Active Low
Active High
Active Low
Active High
Active Low
--
Custom1
--
--
--
--
--
xxxxxx
Pin 2
Pin 2
Pin 1
Pin 1
Pin 1
--
--
G
H
J
--
--
Pin 2
Single
Dual
Quad
Codes A, B
Codes E, F
Code J
SDA
SDA
SDA
7
7
7
OE
NC
1
2
3
6
VDD
OE
FS0
1
2
3
6
5
4
VDD
FS0
FS1
1
2
3
6
5
4
VDD
5
4
CLK–
CLK+
CLK–
CLK+
CLK–
CLK+
GND
GND
GND
8
8
8
SCL
SCL
SCL
Codes C, D
Codes G, H
SDA
7
SDA
7
NC
OE
1
2
3
6
5
4
VDD
FS0
OE
1
2
3
6
5
4
VDD
CLK–
CLK+
CLK–
CLK+
GND
GND
8
8
SCL
SCL
If replacing Si570A-K, use Code C
If replacing Si570M-W, use Code D
Notes:
1. Contact Silicon Labs for non-standard configurations.
2. Total stability includes temp stability, initial accuracy, load pulling, VDD variation, and 20 year aging at 70 °C.
3. Create custom part numbers at www.silabs.com/oscillators.
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Rev. 1.0 | 3
Si564 Data Sheet
Ordering Guide
1.1 Technical Support
Frequently Asked Questions (FAQ)
Oscillator Phase Noise Lookup Utility
Quality and Reliability
www.silabs.com/Si564-FAQ
www.silabs.com/oscillator-phase-noise-lookup
www.silabs.com/quality
Development Kits
www.silabs.com/oscillator-tools
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Rev. 1.0 | 4
Si564 Data Sheet
Electrical Specifications
2. Electrical Specifications
Table 2.1. Electrical Specifications
Test Condition/Comment
VDD = 1.8 V, 2.5 or 3.3 V ± 5%, TA = –40 to 85 ºC
Parameter
Temperature Range
Frequency Range
Symbol
TA
Min
–40
0.2
0.2
0.2
3.135
2.375
1.71
—
Typ
—
Max
85
Unit
ºC
FCLK
LVPECL, LVDS, CML
HCSL
—
3000
400
250
3.465
2.625
1.89
160
157
130
135
145
—
MHz
MHz
MHz
V
—
CMOS, Dual CMOS
3.3 V
—
Supply Voltage
Supply Current
VDD
3.3
2.5
1.8
110
90
85
85
95
73
—
2.5 V
V
1.8 V
V
IDD
LVPECL (output enabled)
LVDS/CML (output enabled)
HCSL (output enabled)
CMOS (output enabled)
Dual CMOS (output enabled)
Tristate Hi-Z (output disabled)
Frequency stability Grade A
Frequency stability Grade A
mA
mA
mA
mA
mA
mA
ppm
ppm
—
—
—
—
—
Temperature Stability
–20
–50
20
Total Stability1
FSTAB
TR/TF
—
50
Rise/Fall Time
LVPECL/LVDS/CML
—
—
—
350
1.5
ps
ns
(20% to 80% VPP
)
CMOS / Dual CMOS
(CL = 5 pF)
0.5
HCSL, FCLK >50 MHz
All formats
—
—
—
—
—
—
—
—
—
550
ps
%
Duty Cycle
DC
VIH
VIL
45
55
Output Enable (OE),
0.7 × VDD
—
V
Frequency Select (FS0, FS1)2
—
—
—
—
—
0.3 × VDD
V
TD
Output Disable Time, FCLK >10 MHz
Output Enable Time, FCLK >10 MHz
Settling Time after FS Change
3
µs
µs
ms
ms
TE
20
10
10
TFS
tOSC
Powerup Time
Time from 0.9 × VDD until output fre-
quency (FCLK) within spec
LVPECL Output Option3
VOC
VO
Mid-level
VDD – 1.42
1.1
—
—
—
VDD – 1.25
1.9
V
Swing (diff, FCLK < 1.5 GHz)
VPP
VPP
Swing (diff, FCLK > 1.5 GHz)6
0.55
1.7
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Si564 Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition/Comment
Mid-level (2.5 V, 3.3 V VDD)
Mid-level (1.8 V VDD)
Min
1.125
0.8
Typ
1.20
0.9
Max
1.275
1.0
Unit
V
LVDS Output Option4
VOC
V
VO
Swing (diff, FCLK < 1.5 GHz)
0.5
0.7
0.9
VPP
VPP
Swing (diff, FCLK > 1.5 GHz) 6
Output voltage high
0.25
0.5
0.8
HCSL Output Option5
VOH
VOL
VC
660
–150
250
0.6
800
0
850
150
550
1.0
mV
mV
mV
VPP
VPP
Output voltage low
Crossing voltage
410
0.8
0.55
CML Output Option (AC-Coupled)
VO
Swing (diff, FCLK < 1.5 GHz)
Swing (diff, FCLK > 1.5 GHz)6
0.3
0.9
CMOS Output Option
VOH
VOL
IOH = 8/6/4 mA for 3.3/2.5/1.8V VDD 0.85 × VDD
IOL = 8/6/4 mA for 3.3/2.5/1.8V VDD
—
—
—
V
V
—
0.15 × VDD
Notes:
1. Total Stability includes temperature stability, initial accuracy, load pulling, VDD variation, and aging for 20 yrs at 70 ºC.
2. OE includes a 50 kΩ pull-up to VDD for OE active high, or includes a 50 kΩ pull-down to GND for OE active low. FS0 and FS1
pins each include a 50 kΩ pull-up to VDD. NC (No Connect) pins include a 50 kΩ pull-down to GND.
3. Rterm = 50 Ω to VDD – 2.0 V (see Figure 4.1).
4. Rterm = 100 Ω (differential) (see Figure 4.2).
5. Rterm = 50 Ω to GND (see Figure 4.2).
6. Refer to the figure below for Typical Clock Output Swing Amplitudes vs Frequency.
Figure 2.1. Typical Clock Output Swing Amplitudes vs. Frequency
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Si564 Data Sheet
Electrical Specifications
Table 2.2. I2C Characteristics
VDD = 1.8, 2.5, or 3.3 V ± 5%, TA = –40 to 85 ºC
Parameter
Symbol
Test Condition/Comment
Min
Typ
Max
Unit
SDA, SCL Input Voltage High
VIH
0.70 x
VDD
—
—
V
SDA, SCL Input Voltage Low
VIL
—
—
0.30 x
VDD
V
Frequency Reprogramming Resolution
MRES
—
0.026
—
—
ppb
Frequency Range for Small Frequency
Change (Continuous Glitchless Output)
From center frequency
-950
+950
ppm
Settling Time for Small Frequency Change
< ±950 ppm from center
frequency
—
—
—
—
100
10
μs
Settling Time for Large Frequency Change
(Output Squelched during Frequency Transi-
tion)
> ±950 ppm from center
frequency
ms
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Si564 Data Sheet
Electrical Specifications
Table 2.3. Clock Output Phase Jitter and PSRR
VDD = 1.8 V, 2.5 or 3.3 V ± 5%, TA = –40 to 85 ºC
Parameter
Symbol
Test Condition/Comment
FCLK ≥ 200 MHz
Min
—
Typ
90
Max
140
160
125
Unit
fs
Phase Jitter (RMS, 12 kHz - 20 MHz)1
All Differential Formats
ϕJ
100 MHz ≤ FCLK < 200 MHz
LVPECL @ 156.25 MHz
—
105
95
fs
—
fs
Phase Jitter (RMS, 12 kHz - 20 MHz)1
CMOS / Dual CMOS Formats
ϕJ
10 MHz ≤ FCLK < 250 MHz
—
200
—
fs
Spurs Induced by External Power Supply
Noise, 50 mVpp Ripple. LVDS 156.25 MHz
Output
PSRR
100 kHz sine wave
200 kHz sine wave
500 kHz sine wave
1 MHz sine wave
-83
-83
-82
-85
dBc
Note:
1. Jitter inclusive of any spurs.
Table 2.4. 3.2 x 5 mm Clock Output Phase Noise (Typical)
Offset Frequency (f)
100 Hz
156.25 MHz LVDS
200 MHz LVDS
–100
644.53125 MHz LVDS
Unit
–105
–129
–136
–142
–150
–159
–160
–92
1 kHz
–126
–116
–125
–131
–138
–153
–154
10 kHz
–133
100 kHz
–140
dBc/Hz
1 MHz
–148
10 MHz
–161
20 MHz
–162
Offset Frequency (f)
156.25 MHz
LVPECL
200 MHz
LVPECL
644.53125 MHz
LVPECL
Unit
100 Hz
1 kHz
–109
–131
–135
–143
–150
–160
–161
–102
–126
–134
–141
–148
–162
–163
–92
–119
–124
–130
–138
–154
–155
10 kHz
100 kHz
1 MHz
dBc/Hz
10 MHz
20 MHz
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Si564 Data Sheet
Electrical Specifications
Figure 2.2. Phase Jitter vs. Output Frequency
Phase jitter measured with Agilent E5052 using a differential-to-single ended converter (balun or buffer). Measurements collected for
>700 commonly used frequencies. Phase noise plots for specific frequencies are available using our free, online Oscillator Phase Noise
Lookup Tool at www.silabs.com/oscillators.
Table 2.5. Environmental Compliance and Package Information
Parameter
Test Condition
MIL-STD-883, Method 2002
MIL-STD-883, Method 2007
MIL-STD-883, Method 2003
MIL-STD-883, Method 1014
MIL-STD-883, Method 2036
1
Mechanical Shock
Mechanical Vibration
Solderability
Gross and Fine Leak
Resistance to Solder Heat
Moisture Sensitivity Level (MSL)
Contact Pads
Gold over Nickel
Note:
1. For additional product information not listed in the data sheet (e.g. RoHS Certifications, MDDS data, qualification data, REACH
Declarations, ECCN codes, etc.), refer to our "Corporate Request For Information" portal found here: www.silabs.com/support/
quality/Pages/RoHSInformation.aspx.
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Rev. 1.0 | 9
Si564 Data Sheet
Electrical Specifications
Table 2.6. Thermal Conditions
Package
Parameter
Symbol
Test Condition
Still Air, 85 ºC
Still Air, 85 ºC
Still Air, 85 ºC
Still Air, 85 ºC
Still Air, 85 ºC
Still Air, 85 ºC
Value
79.1
49.6
125
Unit
ºC/W
ºC/W
ºC
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Board
Max Junction Temperature
ΘJA
ΘJB
TJ
3.2 × 5 mm
8-pin CLCC
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Board
Max Junction Temperature
ΘJA
ΘJB
TJ
67.1
51.7
125
ºC/W
ºC/W
ºC
5 × 7 mm
8-pin CLCC
Table 2.7. Absolute Maximum Ratings1
Parameter
Symbol
TAMAX
TS
Rating
95
Unit
Maximum Operating Temp.
Storage Temperature
Supply Voltage
ºC
ºC
ºC
V
–55 to 125
–0.5 to 3.8
–0.5 to VDD + 0.3
2.0
VDD
Input Voltage
VIN
ESD HBM (JESD22-A114)
Solder Temperature2
HBM
TPEAK
kV
ºC
260
2
TP
20–40
sec
Solder Time at TPEAK
Notes:
1. Stresses beyond those listed in this table may cause permanent damage to the device. Functional operation specification
compliance is not implied at these conditions. Exposure to maximum rating conditions for extended periods may affect device
reliability.
2. The device is compliant with JEDEC J-STD-020.
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Rev. 1.0 | 10
Si564 Data Sheet
Dual CMOS Buffer
3. Dual CMOS Buffer
Dual CMOS output format ordering options support either complementary or in-phase signals for two identical frequency outputs. This
feature enables replacement of multiple XOs with a single Si564 device.
~
Complementary
Outputs
~
In-Phase
Outputs
Figure 3.1. Integrated 1:2 CMOS Buffer Supports Complementary or In-Phase Outputs
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Rev. 1.0 | 11
Si564 Data Sheet
Recommended Output Terminations
4. Recommended Output Terminations
The output drivers support both AC-coupled and DC-coupled terminations as shown in figures below.
VDD
VDD
R1
VDD (3.3V, 2.5V)
CLK+
VDD (3.3V, 2.5V)
CLK+
R1
R1
R1
50 Ω
50 Ω
50 Ω
50 Ω
CLK-
CLK-
LVPECL
Receiver
LVPECL
Receiver
Rp
Rp
Si56x
Si56x
R2
R2
R2
R2
AC-Coupled LVPECL – Thevenin Termination
DC-Coupled LVPECL – Thevenin Termination
VDD (3.3V, 2.5V)
50 Ω
VDD (3.3V, 2.5V)
50 Ω
CLK+
CLK+
R1
R2
R1
50 Ω
50 Ω
50 Ω
50 Ω
VDD
VDD
VTT
VTT
CLK-
Rp
CLK-
R2
50 Ω
50 Ω
LVPECL
Receiver
LVPECL
Receiver
Si56x
Si56x
Rp
AC-Coupled LVPECL - 50 Ω w/VTT Bias
DC-Coupled LVPECL - 50 Ω w/VTT Bias
Figure 4.1. LVPECL Output Terminations
AC-Coupled LVPECL
Termination Resistor Values
DC-Coupled LVPECL
Termination Resistor Values
VDD
R1
R2
Rp
VDD
3.3 V
2.5 V
R1
R2
3.3 V
2.5 V
127 Ω
250 Ω
82.5 Ω
62.5 Ω
130 Ω
90 Ω
127 Ω
250 Ω
82.5 Ω
62.5 Ω
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Si564 Data Sheet
Recommended Output Terminations
(3.3V, 2.5V, 1.8V)
VDD
(3.3V, 2.5V, 1.8V)
VDD
50 Ω
50 Ω
33 Ω
CLK+
CLK-
CLK+
50 Ω
50 Ω
100 Ω
33 Ω
50 Ω
CLK-
50 Ω
LVDS
Receiver
HCSL
Receiver
Si56x
Si56x
DC-Coupled LVDS
Source Terminated HCSL
(3.3V, 2.5V, 1.8V)
(3.3V, 2.5V, 1.8V)
VDD
VDD
50 Ω
CLK+
CLK+
50 Ω
100 Ω
CLK-
CLK-
50 Ω
50 Ω
50 Ω
50 Ω
LVDS
Receiver
HCSL
Receiver
Si56x
Si56x
AC-Coupled LVDS
Destination Terminated HCSL
Figure 4.2. LVDS and HCSL Output Terminations
(3.3V, 2.5V, 1.8V)
VDD
(3.3V, 2.5V, 1.8V)
VDD
CLK
50 Ω
50 Ω
CLK+
CLK-
50 Ω
10 Ω
100 Ω
NC
CMOS
Receiver
CML
Receiver
Si56x
Si56x
CML Termination without VCM
Single CMOS Termination
(3.3V, 2.5V, 1.8V)
VDD
(3.3V, 2.5V, 1.8V)
VDD
CLK+
50 Ω
50 Ω
CLK+
50 Ω
50 Ω
50 Ω
50 Ω
VCM
10 Ω
10 Ω
CLK-
CLK-
CML
Receiver
CMOS
Receivers
Si56x
Si56x
CML Termination with VCM
Dual CMOS Termination
Figure 4.3. CML and CMOS Output Terminations
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Si564 Data Sheet
Configuring Si564 Output Frequency via I2C
5. Configuring Si564 Output Frequency via I2C
The Si564 oscillator device contains a fixed frequency crystal and frequency synthesis IC using Silicon Labs patented DSPLL™ technol-
ogy, all enclosed in a standard hermetically sealed crystal oscillator (XO) package. The internal crystal provides the reference frequen-
cy used by the DSPLL frequency synthesis IC. The output frequency of the Si564 oscillator device can be dynamically set via I2C regis-
ter settings in the DSPLL frequency synthesis IC. DSPLL technology provides unmatched frequency flexibility with superior output jitter/
phase noise performance and part per trillion frequency accuracy. This document describes how to calculate the required Si564 register
values used to set device output frequency, and how to load these values into the Si564 device.
OSC
Digital
Phase
Detector
Phase
Error
Cancellation
Digital
Loop
Filter
Out+
Out-
Digital
VCO
HSDIV
LSDIV
Phase Error
OE
Control
Power
Supply
Processing
Logic
and NVM
FBDIV
I2C / FS
VDD GND
Figure 5.1. Si564 Block Diagram
The figure above is a simplified high-level block diagram of the Si564 oscillator device. The output frequency is set by a combination of
three divider blocks highlighted in the above block diagram.
1. FBDIV - DSPLLTM Feedback Divider used to set Digital VCO frequency
2. HSDIV - High-Speed Output Divider
3. LSDIV - Low-Speed Output Divider
The final device output frequency is based on the digital VCO frequency divided by the product of HSDIV and LSDIV divider settings.
The limits of each of these internal blocks (both digital VCO and dividers) determines the valid operating frequency range of the device.
The FBDIV divider, is a fractional fixed-point divider with a total length of 43 bits consisting of an 11-bit integer field (FBINT) and a 32 bit
fractional field (FBFRAC) where total FBDIV = [FBINT].[FBFRAC] with an implied decimal point as shown. This bit format is known as
an 11.32 fixed point format where the integer portion is 11 bits and fractional portion is 32 bits, for a total of 43 bits.
The HSDIV divider is an integer divider, 11 bits in length, containing a binary divider value. One noteworthy feature of the HSDIV divider
is a special duty cycle correction circuit that allows odd divide ratios of lower divider values (4-33 only) with 50% duty cycle output. This
feature is useful when LSDIV divide ratio is set to 1.
The LSDIV divider performs power-of-2 divides ranging from divide by 1 (20) to divide by 32 (25). The register controlling the LSDIV
divider is 3 bits in length, holding the power-of-2 divide ratio (divider exponent). For example, if LSDIV register = 3 the LSDIV divide
ratio is 23 = 8. Values greater than 5 (i.e. LSDIV register = 6 or 7) still map into a divide by 32.
The tables below summarize the divider limits for LSDIV, HSDIV, FBDIV. These limits and restrictions must be observed when deriving
divider register values, as will be explained in later sections.
Table 5.1. Si564 Divider Range Limits
Divider
Upper Limit
2046
Lower Limit
HSDIV[10:0] (unsigned)
4
LSDIV[2:0] 1 (unsigned)
FBDIV[42:0] hex (unsigned)
FBDIV[42:0] int.frac (unsigned)
32 (2^5)
1 (2^0)
7FDFFFFFFFF
03C00000000
60.0
2045.99999999976
Note:
1. LSDIV is power of 2 divider. See LSDIV table below for actual divide ratio based on LSDIV register value.
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Si564 Data Sheet
Configuring Si564 Output Frequency via I2C
Table 5.2. Additional LSDIV and HSDIV Divider Restrictions
LSDIV
Register Value
0
Divide Ratio
HSDIV Value Restrictions
4-33 even or odd values 1
,
1
34-2046 even values only
4-2046 even or odd values
4-2046 even or odd values
4-2046 even or odd values
4-2046 even or odd values
4-2046 even or odd values
4-2046 even or odd values
4-2046 even or odd values
1
2
3
4
5
6
7
2
4
8
16
32
32
32
Note:
1. HSDIV can implement low value (4-33) odd divide ratios while providing a 50% duty cycle output due to special duty cycle correc-
tion circuit.
Note that all divider values (FBDIV, HSDIV, LSDIV) are unsigned and contain only positive values.
The Si564 high-performance oscillator family has three different speed grade offerings, each covering a specific frequency range. The
table below outlines the output frequency range coverage by each speed grade, the corresponding min and max VCO frequency for
that speed grade, and the nominal crystal frequency. The information in the table below is needed when calculating divider settings for
a given device, speed grade, and output frequency.
Table 5.3. Si564 Speed Grades, Crystal Frequency, and VCO Range Limits
Device
Speed Grade
Xtal freq (MHz) Min Output Freq
(MHz)
Max Output
Freq (MHz)
Min Fvco (GHz) Max Fvco (GHz)
Si564
A
B
C
D
152.6
152.6
152.6
152.6
0.2
0.2
0.2
0.2
3000
1500
800
10.8
10.8
10.8
10.8
13.122222022
12.511886114
12.206718160
12.206718160
325
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Si564 Data Sheet
Configuring Si564 Output Frequency via I2C
5.1 Output Frequency Equations
The basic equations used to derive the output frequency are given below and can be easily inferred from the device block diagram in
Figure 5.2 Si564 Frequency Definition Block Diagram on page 16. Equation 1 is the relationship between the output frequency
(Fout), and the VCO frequency (Fvco) and total output divider ratio (HSDIV * LSDIV). Equation 2 is the relationship between the VCO
frequency (Fvco), the fixed crystal oscillator frequency (Fosc), and the feedback divider (FBDIV).
Fout = Fvco / (HSDIV x LSDIV)
Equation 1
Fvco = (Fosc x FBDIV)
Equation 2
OSC
Digital
Phase
Detector
Phase
Error
Cancellation
Digital
Loop
Filter
Out+
Out-
Digital
VCO
HSDIV
LSDIV
Phase Error
OE
Control
Power
Supply
Processing
Logic
and NVM
FBDIV
I2C / FS
VDD GND
Figure 5.2. Si564 Frequency Definition Block Diagram
Equation 3a is a rearranged Equation 1 to solve for the total output divider (HSDIV *LSDIV) given Fout and Fvco. Equation 3b is rear-
ranged again solving for Fvco given Fout and (HSDIV * LSDIV).
(HSDIV x LSDIV) = Fvco / Fout
Equation 3a
Fvco = Fout x (HSDIV x LSDIV)
Equation 3b
Equation 4 is a rearranged Equation 2 to now solve for FBDIV given Fvco and Fosc.
FBDIV = Fvco / Fosc
Equation 4
Equations 3a, 3b, and 4 will be used in the process of deriving the required divider values to provide a desired output frequency. The
basic process is outlined below.
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Si564 Data Sheet
Configuring Si564 Output Frequency via I2C
5.2 General Process Steps for Divider Calculation
1. Estimate a theoretical total output divider value (HSDIV * LSDIV) based on desired Fout while targeting the minimum valid Fvco
frequency using Eqn. 3a and . Use floating point calculations for this step.
• Result: Floating point value of total (HSDIV * LSDIV).
2. Derive a valid LSDIV divider value based on LSDIV and HSDIV divider limitations using the lowest possible value for LSDIV.
For example, if (HSDIV * LSDIV) = 8.22, use LSDIV =1 and HSDIV = 8.22 versus LSDIV = 2 and HSDIV = 4.11.
• Result: Valid LSDIV value.
3. Using LSDIV value from #2 above, find nearest valid integer HSDIV divider value resulting in Fvco being equal to or greater than
Fvco min, which observing all HSDIV limitations. Use Eqns. 3a/3b as necessary.
• Result: Valid HSDIV value.
4. With valid integer HSDIV and LSDIV values, calculate the required Fvco frequency with Eqn. 3b. (Fvco must remain in valid range
per .)
• Result: Valid VCO frequency.
5. With the derived valid Fvco frequency, use Eqn 4 to calculate required FBDIV based on device specific Fosc frequency from .
• Result: Valid FBDIV value
6. At this point all FBDIV, HSDIV and LSDIV values required to generate the desired output frequency have been calculated. These
three divider values must be now be appropriately formatted to fit the register format expected by the device. This is described in a
later section.
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Si564 Data Sheet
Configuring Si564 Output Frequency via I2C
5.3 Example: Deriving Si564 Divider Settings for 156.75 MHz Output
The general process of deriving divider values for a specific output frequency is outlined in the previous section and now will be used in
this example. To reiterate, all calculations must be done while observing divider limits and valid VCO frequency range limits for your
device. In this example, the device is Si564 and with a desired output frequency of 156.75 MHz, the speed grade required will be “C” or
better. (One important note: All divider and register settings derived for any speed grade will work without modification for all faster
speed grades on the same base part number device.)
Example VB code that implements the following divider calculation process is given in 5.8 Si564 Frequency Planner VB Code
and can be used for implementing any supported output frequency.
Step 1: Find the valid theoretical lower limit of the total output divider (HSDIV*LSDIV) based on the desired output frequency and low-
est valid VCO frequency. This will bias the divider solution to the lowest possible VCO frequency since this will provide the best per-
formance solution.
Given the valid Si564 VCO range is 10.8000 GHz to 12.1097 GHz, the minimum theoretical values for (HSDIV * LSDIV) for the example
156.75 MHz output frequency are given in Equation 3:
Minimum (HSDIV*LSDIV) = (10.8000 GHz / 156.75 MHz) = 68.89952…
Step 2: Find valid LSDIV divisor value given minimum (HSDIV*LSDIV) from step 1. For best performance, preference should be given
to implementation of the total output divider (HSDIV*LSDIV) using HSDIV with LSDIV divide ratio = 1, if possible. Use LSDIV divide
ratios > 1 only if HSDIV alone cannot implement the required output divider. Since the total (HSDIV*LSDIV) value of 68.8995… is less
than the HSDIV maximum divider value of 2046, the LSDIV divide ratio value will be 1, which corresponds to a LSDIV register setting
of 0, since the LSDIV divider can only be a power of 2 value (see Table 5.2 Additional LSDIV and HSDIV Divider Restrictions on page
15 for valid LSDIV settings).
LSDIV divide ratio = 1, therefore LSDIV register value = 0
Step 3: Find HSDIV divisor value. Given LSDIV = 1, HSDIV must implement 68.8995… or greater. Since HSDIV is an integer divider,
the next greatest integer is 69. But, checking valid HSDIV values when LSDIV divide ratio = 1, we see 69 is NOT valid since it is greater
than 33 and an odd value. This means the next greater integer value must be used, which is 70 (now even value). Note that 68 would
not be valid since 68 is less than 68.8995… and would result in a VCO frequency below the lower VCO frequency limit.
HSDIV divide ratio = 70, which gives HSDIV register value = 70 decimal (or hex value = 0x46)
Step 4: Calculate a valid VCO frequency and corresponding floating point FBDIV value. Given the calculated output divider value
(HSDIV*LSDIV) = 70, the VCO frequency must be set to (156.75 MHz * 70) = 10.9725 GHz. Note that 10.9725 GHz is indeed within the
valid VCO frequency range per Table 5.3 Si564 Speed Grades, Crystal Frequency, and VCO Range Limits on page 15.
Fvco = 10.9725 GHz
Step 5: Calculate the FBDIV value necessary to provide a 10.9725 GHz Fvco using a 152.6 MHz crystal as reference (Si564 device).
The floating point FBDIV value required to attain 10.9725 GHz with a 152.6 MHz crystal reference can be calculated as follows:
FBDIV (float) = 10.9725 GHz / 152.6 MHz = 71.9036697247707
(Color coded to highlight Integer and Fractional parts)
Step 6: Format each divider value into the required register format. LSDIV and HSDIV are simply binary values and can be directly
used. FBDIV must first be put into 11.32 fixed point format. Converting the floating point FBDIV value into the 11.32 fixed point hex
value required by the Si564 is done as follows:
Integer value = 71 decimal. Convert 71 to 11 bit hex = 0x047. This is FBINT.
Fractional value = 0.9036697247707. Multiply fractional value by 2^32 = 3881231914.2752. Now extract only the integer part of the
result which is 3881231914. Convert 3881231914 to 32 bit hex = 0xE756E62A. This is FBFRAC.
The resulting 11.32 fixed point hex number is therefore:
FBDIV = FBINT.FBFRAC = 0x047E756E62A
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Si564 Data Sheet
Configuring Si564 Output Frequency via I2C
At this point we have calculated all the required divider values. The table below summarizes the resulting divider values for implement-
ing a 156.75 MHz output clock on the Si564.
Table 5.4. Divider Register Values for Si564 Configured for 156.75 MHz Output Clock
Divider Register
LSDIV
Decimal Value
Hex Value
0x0
Reg Length (bits)
0
70
3
11
HSDIV
0x046
FBDIV
199.318801089918
0x0C7519CF2BF
43 (11+32)
5.4 Mapping Divider Settings into Register Values
For the previous 156.75 MHz example, the divider value to register mapping is shown in the table below. Note that Register 24 is a
packed register and contains bits from both LSDIV and HSDIV registers as follows: LSDIV[2:0] maps into Reg24[6:4] and HSDIV[10:8]
maps into Reg24[2:0]. Note that bits Reg24[7] and Reg24[3] are not used and indicated with ‘x’ in the RegName field below. See also
the Register Map Reference section for specific bit positioning within registers.
Table 5.5. Si564 Divider Register Values for 156.75 MHz Output Clock Configuration
Register (Decimal)
Hex Value
Reg Name
HSDIV[7:0]
23
24
46
00
x:LSDIV[2:0]:x:HSDIV[10:8]
26
27
28
29
30
31
2A
E6
56
E7
47
00
FBDIV[7:0]
FBDIV[15:8]
FBDIV[23:16]
FBDIV[31:24]
FBDIV[39:32]
FBDIV[42:40]
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Si564 Data Sheet
Configuring Si564 Output Frequency via I2C
5.5 I2C Register Write Procedure to Set Output Frequency
After the frequency setting registers (Reg 23-Reg31) are calculated, there is a procedure that must be followed involving other specific
control registers for the device to properly use the new frequency setting registers. Simply writing Reg23-Reg31 is not enough. The
following procedure must be performed as shown to properly configure the Si564 for the desired output frequency. In other words, all
the following register writes must be done, and in the exact sequence shown.
This programming sequence consists of three distinct phases.
1. Writing to specific registers to get the device ready to be updated.
2. Writing the calculated frequency (divider) settings for the desired output frequency.
3. Writing to specific registers necessary to start-up the device after divider registers have been updated. The new output frequency
will appear on output.
The divider values shown in the table below are for the previously described Si564 example for an output frequency of 156.75 MHz (for
other frequencies, replace the divider values in registers 23-31 with values specific to your frequency requirements leaving the other
highlighted register values unchanged).
Table 5.6. Si564 Register Write Sequence to Set Output Frequency
Register (decimal)
Write Data (hex)
Description
Purpose
255
0x00
Set page register to point to
page 0
Get Device Ready for Update
69
0x00
Disable FCAL override (to allow
FCAL for this Freq Update)
17
23
24
26
27
28
29
30
31
7
0x00
0x46
0x00
0x2A
0xE6
0x56
0xE7
0x47
0x00
0x08
Synchronously disable output
HSDIV[7:0]
LSDIV[2:0]:HSDIV[10:8]
FBDIV[7:0]
FBDIV[15:8]
Update Dividers
FBDIV[23:16]
FBDIV[31:24]
FBDIV[39:32]
FBDIV[42:40]
Start FCAL using new divider
values
Startup Device
17
0x01
Synchronously enable output
Note: Refer to the device data sheet for default Si564 I2C address or to the device data sheet addendum for your specific I2C address.
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Si564 Data Sheet
Configuring Si564 Output Frequency via I2C
5.6 Digitally Controlled Oscillator – ADPLL: Small, Fast Frequency Changes
The Si564 can make small, fast frequency adjustments over a range of +/- 950 ppm (parts-per-million) around the device output fre-
quency (set as described in previous sections). This mode is typically used in applications requiring a digitally controlled oscillator
(DCO) for digital PLL or other types of frequency control loops. We refer to this type of application as an all-digital PLL or ADPLL.
The ADPLL mode uses a single 24 bit register, ADPLL_DELTA_M[23:0], to add an offset to the VCO frequency to affect the small fre-
quency change. This offset is added in a synchronous fashion to prevent frequency discontinuities and can be updated as fast as the
max I2C bus speed of 1 MHz will allow. The frequency offset can be positive or negative over a range of -950 ppm to +950 ppm with
0.0001164 ppm resolution.
The equation for this frequency change is simply,
ADPLL_DELTA_M[23:0] = ∆ FoutPPM / 0.0001164
Where ∆ FoutPPM is the desired ppm change in output frequency, ADPLL_DELTA_M[23:0] is a two’s complement 24 bit value, and
0.0001164 is a constant per-bit ppm value. The 24 bit ADPLL_DELTA_M[23:0] value is written into three sequential 8 bit registers in
LSByte to MSByte order via I2C. Upon writing the MSByte, the frequency change takes effect. Below is an example VB to implement
this feature. (Note that writing ADPLL_DELTA_M[23:0] = 0x000 will result in no frequency offset and return to the nominal output fre-
quency.)
VB Code example for ADPLL (small frequency change) calculation and operation:
nAddr = Device I2C address
PPM_Delta = desired PPM frequency shift
Function Set_ADPLL(ByVal nAddr As UInteger, ByVal PPM_Delta As Double) As Integer
Dim ADPLL_PPM_StepSize As Double = 0.0001164
Dim ADPLL_Delta_M As Integer
Dim Reg231 As UInteger = 0
Dim Reg232 As UInteger = 0
Dim Reg233 As UInteger = 0
Dim ReturnCode As Integer = 0 '1=OK, -1 PPM requested is out of bounds
If (PPM_Delta <= 950 And PPM_Delta >= -950) Then
ADPLL_Delta_M = (PPM_Delta / ADPLL_PPM_StepSize)
Reg231 = (ADPLL_Delta_M And &HFF)
Reg232 = (ADPLL_Delta_M >> 8) And &HFF
Reg233 = (ADPLL_Delta_M >> 16) And &HFF
I2C_Write(nAddr, 0, 231, Reg231)
I2C_Write(nAddr, 0, 232, Reg232)
I2C_Write(nAddr, 0, 233, Reg233)
'write “Reg231” value to register 231 at nAddr, page 0 (LSByte)
'write “Reg232” value to register 232 at nAddr, page 0
'write “Reg233” value to register 233 at nAddr, page 0 (MSByte
)
ReturnCode = 1
ReturnCode = -1
Else
End If
Return (ReturnCode)
End Function
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Si564 Data Sheet
Configuring Si564 Output Frequency via I2C
5.7 Register Map Reference
Table 5.7. Register Map Reference Summary
Register
(decimal)
Register Bit
Type
Reset
Value
7
6
5
4
3
2
1
0
7
RESET
<Reserved> = 3'b000
MS_ICAL
2
<Reserved> = 3'b000
R/W
0x00
17
23
<Unused>
HSDIV[7:0]
<Unused>
FBDIV[7:0]
ODC_OE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x01
0x54
0x00
0x00
0x00
0x00
0x00
0x64
0x00
0x01
0x00
0x00
0x00
0x00
24
<Unused>
LSDIV[2:0]
HSDIV[10:8]
26
27
FBDIV[15:8]
FBDIV[23:16]
FBDIV[31:24]
FBDIV[39:32]
28
29
30
31
<Unused>
FBDIV[42:40]
69
FCAL_OVR
<Reserved> = 7'b0000001
ADPLL_DELTA_M[7:0]
231
232
233
255
ADPLL_DELTA_M[15:8]
ADPLL_DELTA_M[23:16]
<Reserved> = 6'b000000
PAGE[1:0]
Table 5.8. Register Bit Field Summary
Register Bit Field Name
RESET
Bit Field (#bits)
Register
Description
1
1
7
7
Set to 1 to reset device. Self clearing.
Set to 1 to initiate FCAL. Self clearing.
MS_ICAL2
HSDIV[10:0]
11
23-24
HSDIV is High-speed output divider value
in unsigned 11-bit binary format. Valid di-
vide values are from 5 to 2046, with values
of 5-33 even or odd, and values 34-2046
restricted to even values only.
LSDIV[2:0]
3
24
LSDIV sets a power-of-2 output divider.
Values of 0,1,2,3,4,5,6,7 result in divide ra-
tio of 1,2,4,8,16,32,32,32 respectively. Note
that a value of 0 (divide-by-1) essentially
bypasses this divider.
FBDIV[42:0]
43
26-31
The main DSPLL system feedback divide
(FBDIV) value for Si56x. This 43 bit value is
composed of an unsigned 11-bit integer
value (FBDIV[42:32]) concatenated with a
32-bit fractional value (FBDIV[31:0]), for an
11.32 fixed point binary format. The valid
range of the 11-bit integer part is from 60 to
2045
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Si564 Data Sheet
Configuring Si564 Output Frequency via I2C
Register Bit Field Name
Bit Field (#bits)
Register
Description
FCAL_OVR
1
69
FCAL Override: If set to 1, FCAL is by-
passed. Clear to 0 to allow FCAL.
ADPLL_DELTA_M[23:0]
24
231-233
Digital word to effect small frequency shifts
to base frequency. Value is 24 bit 2's com-
plement causing a 0.0001164 ppm per bit
shift in frequency. Positive values = positive
freq shift, negative values = negative freq
shift. Valid range is -8161513 to +8161512,
representing a max PPM shift range of
-950 ppm to +950 ppm, with 0 value repre-
senting 0 PPM shift. Writing a new
ADPLL_DELTA_M value will take effect
upon writing to the MSByte (Register 233).
Therefore, value updates should follow the
sequence of writing in register order Reg
231...Reg 232...Reg 233.
PAGE[1:0]
2
255
Sets which page of registers the I2C port is
reading/writing. The size of a page is 256
bytes which is the addressable range of an
I2C "set address" command. The value of
PAGE is multiplied by 256 and added to
what "set address" has set. Physically, the
2 PAGE bits become bits [9:8] of the devi-
ce's internal register map address. This
mechanism allows for more than 256 regis-
ters to be addressed within the 8 bit I2C
"set address" limitation.
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Si564 Data Sheet
Configuring Si564 Output Frequency via I2C
5.8 Si564 Frequency Planner VB Code
--------------------------------------------------------------------------------------------------
Module Main
'
' Si56x Frequency Planner Code
'
'
'Set Target device type, Speed grade, and desired output frequency
'
Public Device As Integer = 564
'
Public SpeedGrade As String = "D" 'Can only be "A" or "B" or "C" or “D”
Public Output_Freq As Double = 312500000.0 'Output frequency in Hz (initially set to 312.5 MHz)
'Set in 'SetLimits" function...
Public Fvco_max As Double 'Fvco Max per Table 3
Public Fvco_min As Double 'Fvco Min per Table 3
Public Xtal_freq As Double 'Xtal_Freq per Table 3
Public Fout_min As Double 'Minimum output frequency
Public Fout_max As Double 'Maximum output frequency
Sub Main()
'
' Device divider limits (see Tables 1 & 2)
'
Dim HSDIV_UpperLimit As Integer = 2046
Dim HSDIV_LowerLimit As Integer = 4
Dim HSDIV_LowerLimit_Odd As Integer = 5
Dim HSDIV_UpperLimit_Odd As Integer = 33
Dim LSDIV_UpperLimit As Integer = 5
Dim LSDIV_LowerLimit As Integer = 0
'min count for odd HSDIV divisor
'max count for odd HSDIV divisor
Dim FBDIV_UpperLimit As Double = 2045 + ((2 ^ 32 - 1) / (2 ^ 32))
Dim FBDIV_LowerLimit As Double = 60.0
'
' Working variables
'
Dim Min_HSLS_Div As Double
Dim LSDIV_Div As Double
Dim LSDIV_Reg As Integer
Dim HSDIV As Double
' actual LSDIV divide ratio
' LSDIV as encoded in power of 2 for device register use
Dim FBDIV As Double
Dim Fvco As Double
Dim FBDIV_Int As UInteger
Dim FBDIV_Frac As UInteger
Dim Reg23 As UInteger = 0
Dim Reg24 As UInteger = 0
Dim Reg26 As UInteger = 0
Dim Reg27 As UInteger = 0
Dim Reg28 As UInteger = 0
Dim Reg29 As UInteger = 0
Dim Reg30 As UInteger = 0
Dim Reg31 As UInteger = 0
'HSDIV[7:0]
'OD_LSDIV[2:0],HSDIV[10:8]
'FBDIV[7:0]
(*2^4,/2^8)
'FBDIV[15:8]
(/2^8)
'FBDIV[23:16] (/2^16)
'FBDIV[31:24] (/2^24)
'FBDIV[39:32] (/2^32)
'FBDIV[42:40] (/2^40)
'
' Set device limits based on device type and speed grade.
' (Checks if desired output frequency is valid based on device and speed grade)
'
If SetLimits(Device, SpeedGrade, Output_Freq) = 0 Then
'
' If limits are set and output frequency is valid, calculate frequency plan...
'***********************************************************************************************
'
Step 1: Find theoretical HSDIV *LSDIV value based on lowest valid VCO frequency...
(Assumes "Output_Freq" has been tested and is in valid range for the device grade accord
'
ing to Table 3)
'
Min_HSLS_Div = Fvco_min / Output_Freq
s check Output_Freq!
' Floating point HS*LS div value. Remember to first bound
'Step 2: Find LSDIV divisor value given Min_HSLS_Div value
'
LSDIV_Div = Math.Ceiling(Min_HSLS_Div / HSDIV_UpperLimit) ' Divisor value of LSDIV, NOT yet encode
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Si564 Data Sheet
Configuring Si564 Output Frequency via I2C
d as power of 2
If (LSDIV_Div > 32) Then LSDIV_Div = 32 ' clip at 32 (max LSDIV divisor)
'
'Encode LSDIV divisor value into next nearest 'power of 2' value if not already. This will be LSDIV
_Reg
'
LSDIV_Reg = Math.Ceiling(Math.Log(LSDIV_Div, 2))
2. Will range from 0 to 5.
' LSDIV_Reg now encoded as proper power of
' Adjust LSDIV_Div (holder of divisor) based on rounded power of 2 value in LSDIV_Reg
LSDIV_Div = 2 ^ LSDIV_Reg 'LSDIV_Div divisor now synchronized to actual LSDIV_Reg.
'
'Step 3: Find HSDIV divisor value using known LSDIV divisor
'
HSDIV = Math.Ceiling(Min_HSLS_Div / LSDIV_Div)
If ((LSDIV_Reg > 0) Or ((HSDIV >= HSDIV_LowerLimit_Odd) And (HSDIV <= HSDIV_UpperLimit_Odd))) Then
HSDIV = HSDIV ' Leaves HSDIV as even or odd only if LSDIV_Div = 1 and HSDIV is from 4 to 33.
Else
If ((HSDIV Mod 2) <> 0) Then
HSDIV = HSDIV + 1
End If
'If HSDIV is an odd value...
'...make it even by rounding up
'If already even, leave it alone
End If
'
' Step 4: Now calculate Fvco and FBDIV
'
Fvco = (HSDIV * LSDIV_Div * Output_Freq)
FBDIV = Fvco / Xtal_freq
'Calculate Fvco based on valid HSDIV,LSDIV, and Fout
'Finally, calculate FBDIV based on xtal freq
'Calculate 11.32 fixed point FBDIV value (MCTL_M)
'Extract Integer part
FBDIV_Int = Int(FBDIV)
'Extract fractional part
FBDIV = (FBDIV - FBDIV_Int)
FBDIV = FBDIV * (2 ^ 32)
FBDIV_Frac = Int(FBDIV)
'
'Generate Register values based on LSDIV, HSDIV, and FBDIV (MCTL_M)
'
Reg23 = (HSDIV And &HFF)
Reg24 = ((HSDIV >> 8) And &H7) Or ((LSDIV_Reg And &H7) << 4)
Reg26 = (FBDIV_Frac And &HFF)
Reg27 = (FBDIV_Frac >> 8) And &HFF
Reg28 = (FBDIV_Frac >> 16) And &HFF
Reg29 = (FBDIV_Frac >> 24) And &HFF
Reg30 = (FBDIV_Int) And &HFF
Reg31 = (FBDIV_Int >> 8) And &H7
'*************************************************************************
Else
Console.WriteLine("*** Device invalid or Device limits exceeded. Frequency plan not calculated.")
End If
End Sub
'
' Sets device limits according to Table 3
'
'
Returns 0 if limits are set and output frequency is valid
Returns -1 if device not found or output frequency/speed grade is invalid
Function SetLimits(ByVal Device As Integer, ByVal SpeedGrade As String, ByVal Output_Freq As Double) As Int
eger
Dim ReturnCode As Integer
ReturnCode = 0
If Device = 569 Then
Xtal_freq = 152600000.0
If SpeedGrade = "A" Then
Fvco_min = 10800000000.0
Fvco_max = 13122222022.0
Fout_min = 200000.0
Fout_max = 3000000000.0
If ((Output_Freq < Fout_min) Or (Output_Freq > Fout_max)) Then
ReturnCode = -1
End If
ElseIf SpeedGrade = "B" Then
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Rev. 1.0 | 25
Si564 Data Sheet
Configuring Si564 Output Frequency via I2C
Fvco_min = 10800000000.0
Fvco_max = 12511886114.0
Fout_min = 200000.0
Fout_max = 1500000000.0
If ((Output_Freq < Fout_min) Or (Output_Freq > Fout_max)) Then
ReturnCode = -1
End If
ElseIf SpeedGrade = "C" Then
Fvco_min = 10800000000.0
Fvco_max = 12206718160.0
Fout_min = 200000.0
Fout_max = 800000000.0
If ((Output_Freq < Fout_min) Or (Output_Freq > Fout_max)) Then
ReturnCode = -1
End If
ElseIf SpeedGrade = "D" Then
Fvco_min = 10800000000.0
Fvco_max = 12206718160.0
Fout_min = 200000.0
Fout_max = 325000000.0
If ((Output_Freq < Fout_min) Or (Output_Freq > Fout_max)) Then
ReturnCode = -1
End If
Else
ReturnCode = -1
End If
Else
ReturnCode = -1
'Speed Grade not found
'Device type not found
End If
Return (ReturnCode)
End Function
End Module
--------------------------------------------------------------------------
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Rev. 1.0 | 26
Si564 Data Sheet
Configuring Si564 Output Frequency via I2C
5.9 Table of Common Frequencies for Si564 (152.6 MHz xtal)
Fout (MHz) LSDIV HSDIV FBDIV Fvco (GHz) Reg 23 Reg 24 Reg 26 Reg 27 Reg 28 Reg 29 Reg 30 Reg 31
70.656
100
0
0
0
0
154
108
88
88
74
74
74
72
72
70
70
66
64
54
52
44
44
40
36
36
34
27
26
22
22
18
18
17
15
14
71.30422018 10.881024
70.77326343 10.8
9Ah
6Ch
58h
58h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
BAh
A7h
04h
34h
07h
63h
7Dh
A7h
84h
46h
D8h
C2h
A7h
A7h
17h
04h
34h
A7h
1Ch
A3h
14h
A7h
17h
04h
34h
84h
1Ch
14h
A3h
C0h
5Fh
97h
92h
1Fh
5Fh
08h
AAh
97h
4Fh
2Ah
B4h
9Dh
97h
97h
41h
92h
1Fh
97h
3Ah
C8h
A6h
97h
41h
92h
1Fh
4Fh
3Ah
A6h
C8h
A6h
E1h
F4h
80h
79h
9Ah
05h
51h
F4h
C9h
E6h
9Fh
87h
F4h
F4h
5Ah
80h
79h
F4h
B2h
DEh
63h
F4h
5Ah
80h
79h
C9h
B2h
63h
DEh
FDh
4Dh
C5h
DCh
15h
F0h
03h
3Ah
C5h
78h
56h
ACh
ADh
C5h
C5h
69h
DCh
15h
C5h
60h
B8h
CDh
C5h
69h
DCh
15h
78h
60h
CDh
B8h
64h
47h
46h
46h
48h
47h
48h
48h
46h
48h
47h
47h
48h
46h
46h
48h
46h
48h
46h
49h
49h
47h
46h
48h
46h
48h
48h
49h
47h
49h
49h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
122.88
125
70.86133683 10.81344
72.08387942 11
148.351648 0
148.5
148.945454 0
71.93985552 10.97802195 4Ah
72.01179554 10.989 4Ah
72.22780862 11.0219636 4Ah
0
150
0
0
0
0
0
0
0
0
0
0
0
0
0
70.77326343 10.8
48h
48h
46h
46h
42h
40h
36h
34h
2Ch
2Ch
28h
24h
24h
153.6
155.52
156.25
168.04
168.75
200
72.47182176 11.0592
71.33944954 10.8864
71.67431193 10.9375
72.67785059 11.09064
70.77326343 10.8
70.77326343 10.8
212.5
245.76
250
72.41153342 11.05
70.86133683 10.81344
72.08387942 11
270
70.77326343 10.8
311.04
312.5
73.37771953 11.19744
73.72214941 11.25
322.265625 0
71.80230177 10.95703125 22h
400
0
0
0
0
0
0
0
0
0
70.77326343 10.8
1Bh
1Ah
16h
16h
12h
12h
425
72.41153342 11.05
70.86133683 10.81344
72.08387942 11
491.52
500
614.4
622.08
644.53125
750
72.47182176 11.0592
73.37771953 11.19744
71.80230177 10.95703125 11h
73.72214941 11.25
73.39449541 11.2
0Fh
0Eh
800
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Rev. 1.0 | 27
Si564 Data Sheet
Configuring Si564 Output Frequency via I2C
5.10 I2C Interface
Configuration and operation of the Si564 is controlled by reading and writing to the RAM space using the I2C interface. The device
operates in slave mode with 7-bit addressing and can operate in Standard-Mode (100 kbps), Fast-Mode (400 kbps), or Fast-Mode Plus
(1 Mbps). Burst data transfer with auto address increments are also supported.
The I2C bus consists of a bidirectional serial data line (SDA) and a serial clock input (SCL). Both the SDA and SCL pins must be con-
nected to the VDD supply via an external pull-up as recommended by the I2C specification. The Si564 7-bit I2C slave address is user-
customized during the part number configuration process.
Data is transferred MSB first in 8-bit words as specified by the I2C specification. A write command consists of a 7-bit device (slave)
address + a write bit, an 8-bit register address, and 8 bits of data as shown in the figure below.
A write burst operation is also shown where every additional data word is written using an auto-incremented address.
Write Operation – Single Byte
S
Slv Addr [6:0]
0
A
Reg Addr [7:0]
A
Data [7:0]
A
A
P
Write Operation - Burst (Auto Address Increment)
Slv Addr [6:0] Reg Addr [7:0] Data [7:0]
S
0
A
A
Data [7:0]
A
P
Reg Addr +1
1 – Read
0 – Write
A – Acknowledge (SDA LOW)
N – Not Acknowledge (SDA HIGH)
S – START condition
From slave to master
From master to slave
P – STOP condition
Figure 5.3. I2C Write Operation
A read operation is performed in two stages. A data write is used to set the register address, then a data read is performed to retrieve
the data from the set address. A read burst operation is also supported. This is shown in the figure below.
Read Operation – Single Byte
S
Slv Addr [6:0]
0
A
Reg Addr [7:0]
A
P
P
S
Slv Addr [6:0]
1
A
Data [7:0]
N
Read Operation - Burst (Auto Address Increment)
S
S
Slv Addr [6:0]
Slv Addr [6:0]
0
1
A
A
Reg Addr [7:0]
Data [7:0]
A
P
A
Data [7:0]
N P
Reg Addr +1
1 – Read
0 – Write
A – Acknowledge (SDA LOW)
N – Not Acknowledge (SDA HIGH)
S – START condition
From slave to master
From master to slave
P – STOP condition
Figure 5.4. I2C Read Operation
The timing specifications and timing diagram for the I2C bus is compatible with the I2C-Bus standard. SDA timeout is supported for
compatibility with SMBus interfaces.
The I2C bus can be operated at a bus voltage of 1.71 to 3.63 V and should be the same voltage as the Si564 VDD.
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Rev. 1.0 | 28
Si564 Data Sheet
Package Outline
6. Package Outline
6.1 Package Outline (5x7 mm)
The figure below illustrates the package details for the 5x7 mm Si564. The table below lists the values for the dimensions shown in the
illustration.
Figure 6.1. Si564 (5x7 mm) Outline Diagram
Table 6.1. Package Diagram Dimensions (mm)
Dimension
Min
1.07
0.40
0.45
1.30
0.50
0.50
Nom
1.18
Max
1.33
0.60
0.65
1.50
0.70
0.70
Dimension
Min
6.10
1.07
1.00
1.70
Nom
6.20
Max
6.30
1.27
1.20
1.90
A
E1
L
A2
0.50
1.17
A3
0.55
L1
1.10
b
1.40
p
--
b1
0.60
R
0.70 REF
0.15
c
0.60
aaa
bbb
ccc
ddd
eee
D
5.00 BSC
4.40
0.15
D1
4.30
4.50
0.08
e
E
2.54 BSC
7.00 BSC
0.10
0.05
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
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Rev. 1.0 | 29
Si564 Data Sheet
Package Outline
6.2 Package Outline (3.2x5 mm)
The figure below illustrates the package details for the 5x3.2 mm Si564. The table below lists the values for the dimensions shown in
the illustration.
Figure 6.2. Si564 (3.2x5 mm) Outline Diagram
Table 6.2. Package Diagram Dimensions (mm)
Dimension
MIN
1.02
0.50
0.45
0.54
0.54
NOM
1.17
MAX
1.33
0.60
0.55
0.74
0.75
Dimension
MIN
NOM
2.85 BSC
0.9
MAX
A
E1
L
A2
0.55
0.8
1.0
A3
0.50
L1
0.45
0.05
0.15
0.55
0.65
0.15
0.25
b
0.64
L2
0.10
b1
0.64
L3
0.20
D
5.00 BSC
4.65 BSC
1.27 BSC
1.625 TYP
3.20 BSC
aaa
bbb
ccc
ddd
eee
0.15
D1
0.15
e
e1
0.08
0.10
E
0.05
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
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Rev. 1.0 | 30
Si564 Data Sheet
PCB Land Pattern
7. PCB Land Pattern
7.1 PCB Land Pattern (5x7 mm)
The figure below illustrates the 5x7 mm PCB land pattern for the Si564. The table below lists the values for the dimensions shown in
the illustration.
Figure 7.1. Si564 (5x7 mm) PCB Land Pattern
Table 7.1. PCB Land Pattern Dimensions (mm)
Dimension
(mm)
4.20
6.05
2.54
1.55
Dimension
(mm)
1.95
1.80
0.75
C1
C2
E
Y1
X2
Y2
X1
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a
Fabrication Allowance of 0.05 mm.
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020D specification for Small Body Components.
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Rev. 1.0 | 31
Si564 Data Sheet
PCB Land Pattern
7.2 PCB Land Pattern (3.2x5 mm)
The figure below illustrates the 3.2x5.0 mm PCB land pattern for the Si564. The table below lists the values for the dimensions shown
in the illustration.
Figure 7.2. Si564 (3.2x5 mm) PCB Land Pattern
Table 7.2. PCB Land Pattern Dimensions (mm)
Dimension
(mm)
2.70
1.27
4.30
0.74
Dimension
(mm)
0.90
1.60
0.70
C1
E
X2
Y1
Y2
E1
X1
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a
Fabrication Allowance of 0.05 mm.
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
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Rev. 1.0 | 32
Si564 Data Sheet
Top Marking
8. Top Marking
The figure below illustrates the mark specification for the Si564. The table below lists the line information.
Figure 8.1. Mark Specification
Table 8.1. Si564 Top Mark Description
Line
Position
1–8
Description
"Si564", xxx = Ordering Option 1, Option 2, Option 3 (e.g. Si564AAA)
x = Frequency Range Supported as described in the 1. Ordering Guide
6-digit custom Frequency Code as described in the 1. Ordering Guide
Trace Code
1
2
1
2–7
3
Position 1
Position 2
Pin 1 orientation mark (dot)
Product Revision (B)
Position 3–5
Position 6–7
Position 8–9
Tiny Trace Code (3 alphanumeric characters per assembly release instructions)
Year (last two digits of the year), to be assigned by assembly site (ex: 2017 = 17)
Calendar Work Week number (1–53), to be assigned by assembly site
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Rev. 1.0 | 33
Si564 Data Sheet
Revision History
9. Revision History
Revision 1.0
June, 2018
• Initial release.
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Rev. 1.0 | 34
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