571ACAFREQDGR [SILICON]
LVPECL Output Clock Oscillator, 10MHz Min, 945MHz Max, ROHS COMPLIANT PACKAGE-8;型号: | 571ACAFREQDGR |
厂家: | SILICON |
描述: | LVPECL Output Clock Oscillator, 10MHz Min, 945MHz Max, ROHS COMPLIANT PACKAGE-8 机械 振荡器 |
文件: | 总26页 (文件大小:316K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Si570/Si571
PRELIMINARY DATA SHEET
ANY-RATE I2C PROGRAMMABLE XO/VCXO
Features
ꢀ
Any-rate programmable output
frequencies from 10 to 945 MHz and
select frequencies to 1.4 GHz
ꢀ
Internal fixed crystal frequency
ensures high reliability and low
aging
2
ꢀ
ꢀ
Available LVPECL, CMOS,
LVDS, and CML outputs
Industry-standard 5x7 mm
package
Pb-free/RoHS-compliant
1.8, 2.5, or 3.3 V supply
ꢀ
ꢀ
I C serial interface
®
3rd generation DSPLL with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
ꢀ
ꢀ
ꢀ
Applications
Ordering Information:
ꢀ
ꢀ
ꢀ
SONET / SDH
xDSL
10 GbE LAN / WAN
ꢀ
ꢀ
ꢀ
Low-jitter clock generation
Optical modules
Clock and data recovery
See page 21.
Pin Assignments:
Description
See page 20.
®
The Si570 XO/Si571 VCXO utilizes Silicon Laboratories’ advanced DSPLL
circuitry to provide a low-jitter clock at any frequency. The Si570/Si571 are
user-programmable to any output frequency from 10 to 945 MHz and select
frequencies to 1400 MHz with <1 ppb resolution. The device is programmed
(Top View)
SDA
7
2
via an I C serial interface. Unlike traditional XO/VCXOs where a different
NC
VDD
1
2
3
6
5
4
crystal is required for each output frequency, the Si57x uses one fixed-
frequency crystal and a DSPLL clock synthesis IC to provide any-rate
frequency operation. This IC-based approach allows the crystal resonator to
provide exceptional frequency stability and reliability. In addition, DSPLL
clock synthesis provides superior supply noise rejection, simplifying the task
of generating low-jitter clocks in noisy environments typically found in
communication systems.
OE
CLK–
CLK+
GND
8
SCL
Functional Block Diagram
Si570
CLK-
CLK+
VDD
SDA
7
Any-rate
VC
VDD
1
2
3
6
5
4
Fixed
Frequency
XO
10-1400 MHz
DSPLL®Clock
Synthesis
SDA
SCL
OE
CLK–
CLK+
Si571 only
GND
ADC
8
SCL
GND
OE
Si571
VC
Rev. 0.31 8/07
Copyright © 2007 by Silicon Laboratories
Si570/Si571
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si570/Si571
2
Rev. 0.31
Si570/Si571
TABLE OF CONTENTS
Section
Page
1. Detailed Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.1. Frequency Programming Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.2. Frequency Programming Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.3. I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
4. Serial Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
5. Si570 (XO) Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
6. Si571 (VCXO) Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
7. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
8. Si57x Mark Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
9. Outline Diagram and Suggested Pad Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
10. 8-Pin PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Rev. 0.31
3
Si570/Si571
1. Detailed Block Diagrams
VDD
GND
fXTAL
M
CLKOUT+
CLKOUT–
DCO
÷HS_DIV
÷N1
+
fosc
RFREQ
Frequency
Control
OE
Control
Interface
SDA
SCL
NVM
RAM
Figure 1. Si570 Detailed Block Diagram
VDD
GND
fXTAL
M
CLKOUT+
CLKOUT–
VC
ADC
DCO
÷HS_DIV
÷N1
+
fosc
VCADC
RFREQ
Frequency
Control
OE
SDA
SCL
Control
Interface
NVM
RAM
Figure 2. Si571 Detailed Block Diagram
4
Rev. 0.31
Si570/Si571
2. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol
Test Condition
3.3 V option
2.5 V option
1.8 V option
Min
2.97
2.25
1.71
Typ
3.3
2.5
1.8
Max
3.63
2.75
1.89
Units
1
V
V
Supply Voltage
DD
Output enabled
LVPECL
CML
—
—
—
—
130
117
108
98
120
108
99
Supply Current
I
mA
DD
LVDS
CMOS
90
TriState mode
—
0.75 x V
—
60
—
—
—
75
—
V
IH
DD
2
V
Output Enable (OE)
V
0.5
85
IL
T
–40
ºC
Operating Temperature Range
A
Notes:
1. Selectable parameter specified by part number. See Section "7. Ordering Information" on page 21 for further details.
2. OE pin includes a 17 kΩ pullup resistor to VDD or a 17 kΩ pulldown to GND depending on the OE polarity specified in
the part number. See "7. Ordering Information" on page 21.
Table 2. VC Control Voltage Input
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
33
45
90
1,2,3
K
V 10 to 90% of V
—
—
ppm/V
Control Voltage Tuning Slope
V
C
DD
135
180
356
BSL
–5
–10
9.3
500
—
±1
±5
+5
+10
10.7
—
4
L
%
Control Voltage Linearity
VC
Incremental
BW
10.0
—
kHz
kΩ
V
Modulation Bandwidth
Z
V Input Impedance
VC
C
V
@ f
V /2
DD
—
Nominal Control Voltage
CNOM
O
V
0
V
V
Control Voltage Tuning Range
C
DD
Notes:
1. Positive slope; selectable option by part number. See "7. Ordering Information" on page 21.
2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.
3. KV variation is ±10% of typical values.
4. BSL determined from deviation from best straight line fit with VC ranging from 10 to 90% of VDD. Incremental slope
determined with VC ranging from 10 to 90% of VDD
.
Rev. 0.31
5
Si570/Si571
Table 3. CLK± Output Frequency Characteristics
Parameter
Symbol
Test Condition
LVPECL/LVDS/CML
CMOS
Min
10
Typ
—
Max
945
160
Units
Programmable Frequency
f
MHz
O
1,2,3
Range
10
—
–20
–50
–100
—
—
—
+20
+50
+100
1,4
T = –40 to +85 ºC
ppm
Temperature Stability
A
Frequency drift over first year
Frequency drift over 15 year life
Temp stability = ±20 ppm
—
—
—
—
—
—
—
—
—
—
±3
±10
ppm
ppm
ppm
ppm
ppm
ms
Aging
fa
—
±31.5
±61.5
±375
10
Total Stability
Temp stability = ±50 ppm
—
1,4
APR
±25
—
Absolute Pull Range
5
t
Power up Time
OSC
f within ±100 ppm of f
—
100
10
µs
1
0
Settling Time after Frequency
Change
t
FRQ
f > ±100 ppm of f
—
ms
1
0
Notes:
1. See Section "7. Ordering Information" on page 21 for further details.
2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz.
3. Nominal output frequency set by VCNOM = 1/2 x VDD
4. Selectable parameter specified by part number.
5. Time from power up or tristate mode to fO.
.
6
Rev. 0.31
Si570/Si571
Table 4. CLK± Output Levels and Symmetry
Parameter
Symbol
Test Condition
mid-level
Min
VDD – 1.42
1.1
Typ
—
Max
VDD – 1.25
1.9
Units
V
1
LVPECL Output Option
V
O
VOD
VSE
swing (diff)
VPP
VPP
—
swing (single-ended)
mid-level
0.55
—
0.95
2
LVDS Output Option
V
1.125
0.5
1.20
0.7
1.275
0.9
V
O
swing (diff)
VOD
VPP
VO
mid-level
—
0.70
0.8 x VDD
—
V
– 0.75
—
1.20
VDD
0.4
V
DD
2
CML Output Option
VOD
VOH
VOL
swing (diff)
0.95
—
VPP
I
= 32 mA
OH
3
V
CMOS Output Option
IOL = 32 mA
—
LVPECL/LVDS/CML
—
—
350
—
ps
ns
t
t
Rise/Fall time (20/80%)
Symmetry (duty cycle)
R, F
CMOS with C = 15 pF
—
1
L
LVPECL:
LVDS:
CMOS:
V
– 1.3 V (diff)
DD
SYM
45
—
55
%
1.25 V (diff)
/2
V
DD
Notes:
1. 50 Ω to VDD – 2.0 V.
2. Rterm = 100 Ω (differential).
3. CL = 15 pF
Table 5. CLK± Output Phase Jitter (Si570)
Parameter
Symbol
Test Condition
Min
Typ
Max
0.40
0.37
0.50
0.42
Units
Phase Jitter (RMS)*
φJ
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
12 kHz to 20 MHz (OC-48)
50 kHz to 20 MHz (OC-192)
—
—
—
—
0.25
0.26
0.36
0.34
ps
for F
> 500 MHz
OUT
Phase Jitter (RMS)*
for F of 125 to 500 MHz
φJ
ps
OUT
*Note: Differential Modes: LVPECL/LVDS/CML. Refer to AN256 for further information.
Rev. 0.31
7
Si570/Si571
Table 6. CLK± Output Phase Jitter (Si571)
Parameter
Symbol
Test Condition
Kv = 33 ppm/V
Min
Typ
Max
Units
1,2,3
Phase Jitter (RMS)
for F > 500 MHz
φJ
ps
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.26
0.26
—
—
OUT
Kv = 45 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.27
0.26
—
—
Kv = 90 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.32
0.26
—
—
Kv = 135 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.40
0.27
—
—
Kv = 180 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.49
0.28
—
—
Kv = 356 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.87
0.33
—
—
Notes:
1. Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, and AN266 for further information.
2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.
3. See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply
rejection (PSR) advantage of Si55x versus SAW-based solutions.
8
Rev. 0.31
Si570/Si571
Table 6. CLK± Output Phase Jitter (Si571) (Continued)
Parameter
Symbol
Test Condition
Kv = 33 ppm/V
Min
Typ
Max
Units
1,2,3
Phase Jitter (RMS)
for F of 125 to 500 MHz
φJ
ps
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.37
0.33
—
—
OUT
Kv = 45 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.37
0.33
—
—
Kv = 90 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.43
0.34
—
—
Kv = 135 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.50
0.34
—
—
Kv = 180 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.59
0.35
—
—
Kv = 356 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
1.00
0.39
—
—
Notes:
1. Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, and AN266 for further information.
2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.
3. See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply
rejection (PSR) advantage of Si55x versus SAW-based solutions.
Table 7. CLK± Output Period Jitter
Parameter
Symbol
Test Condition
RMS
Min
—
Typ
2
Max
—
Units
J
ps
Period Jitter*
PER
Peak-to-Peak
—
14
—
*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to “AN279: Estimating Period Jitter
from Phase Noise” for further information.
Rev. 0.31
9
Si570/Si571
Table 8. Typical CLK± Output Phase Noise (Si570)
Offset Frequency (f)
120.00 MHz
LVDS
156.25 MHz
LVPECL
622.08 MHz
LVPECL
Units
100 Hz
1 kHz
10 kHz
100 kHz
1 MHz
–112
–122
–132
–137
–144
–150
n/a
–105
–122
–128
–135
–144
–147
n/a
–97
–107
–116
–121
–134
–146
–148
dBc/Hz
10 MHz
100 MHz
Table 9. Typical CLK± Output Phase Noise (Si571)
Offset Frequency
74.25 MHz
90 ppm/V
LVPECL
491.52 MHz
622.08 MHz
135 ppm/V
LVPECL
Units
45 ppm/V
LVPECL
100 Hz
1 kHz
10 kHz
100 kHz
1 MHz
–87
–114
–132
–142
–148
–150
n/a
–75
–65
–90
–100
–116
–124
–135
–146
–147
–109
–121
–134
–146
–147
dBc/Hz
10 MHz
100 MHz
Table 10. Absolute Maximum Ratings
Parameter
Supply Voltage
Symbol
Rating
–0.5 to +3.8
Units
V
Volts
Volts
ºC
DD
Input Voltage
V
–0.5 to V + 0.3
I
DD
Storage Temperature
T
–55 to +125
>2500
S
ESD Sensitivity (HBM, per JESD22-A114)
Soldering Temperature (lead-free profile)
ESD
Volts
ºC
T
260
PEAK
Soldering Temperature Time @ T
(lead-free profile)
t
20–40
seconds
PEAK
P
Notes:
1. Stresses beyond the absolute maximum ratings may cause permanent damage to the device. Functional operation or
specification compliance is not implied at these conditions.
2. The device is compliant with JEDEC J-STD-020C. Refer to Si5xx Packaging FAQ available for download at
www.silabs.com/VCXO for further information, including soldering profiles.
10
Rev. 0.31
Si570/Si571
Table 11. Environmental Compliance
The Si570/571 meets the following qualification test requirements.
Parameter
Mechanical Shock
Conditions/Test Method
MIL-STD-883F, Method 2002.3 B
MIL-STD-883F, Method 2007.3 A
MIL-STD-883F, Method 203.8
MIL-STD-883F, Method 1014.7
MIL-STD-883F, Method 2016
Mechanical Vibration
Solderability
Gross & Fine Leak
Resistance to Solvents
Table 12. Programming Constraints
(VDD = 3.3 V ±10%, TA = –40 to 85 ºC)
Parameter
Symbol
Test Condition
Min
10
Typ
—
Max
945
Unit
MHz
MHz
HS_DIV x N1 > = 6
HS_DIV x N1 = 5
N1 = 1
970
—
1134
Output Frequency
CKO
F
HS_DIV = 4
N1 = 1
1.2125
—
—
1.4175
—
GHz
ppb
M and RFREQ Value LSB
Resolution
M
114.285 MHz
0.09
RES
3rd Overtone Crystal
Internal Oscillator Frequency
Unfreeze to NewFreq Delay
f
4850
—
—
—
5670
10
MHz
ms
OSC
Rev. 0.31
11
Si570/Si571
3.2.2. Calculating the Reference Frequency Multi-
plier (RFREQ)
3. Functional Description
The Si570 XO and the Si571 VCXO are low-jitter,
programmable oscillators ideally suited for applications
requiring multiple frequencies. The Si57x can be
programmed to generate any output clock rate between
10 and 1.4 GHz with <1 ppb resolution. Output jitter
performance exceeds the strict requirements of high-
speed communication systems including OC-48/OC-
192 and 10 Gigabit Ethernet.
RFREQ is a binary representation of the reference
frequency multiplier and is 38 bits in length. To convert
from a decimal number to the binary number RFREQ
must be broken into two parts: the integer portion and
the fractional portion. The first 10 most-significant-bits
(MSBs) of RFREQ represent the integer portion, and
the lower 28 least-significant-bits (LSB's) represent the
fractional portion. The integer portion can be converted
The Si57x employs Silicon Laboratories’ third- directly from decimal to binary (e.g. decimal
generation digital signal processing based phase- 43 = hexadecimal 02Bh--the leading nibble only
®
locked loop (DSPLL ) technology providing excellent occupies two bits of RFREQ). The fractional portion
28
jitter performance, digital programmability, and stability should be made into an integer by multiplying by 2
while requiring minimal external components. At the and truncating (or rounding) the result as follows:
core of the Si57x is a digitally-controlled oscillator (e.g. 0.54587216*2^28 = 146531442.18730496; then,
(DCO) based on DSPLL technology that is driven by a truncate to 146531442). The truncated value can then
digital frequency control word and produces a low-jitter be
converted
to
binary
(e.g.
decimal
output clock. (See "1. Detailed Block Diagrams" on 146531442 = hexadecimal 8BBE472h). The resulting
page 4.)
binary RFREQ for 43.54587216 is 02B8BBE472h
(02Bh concatenated with 8BBE472h).
3.1. Frequency Programming Summary
3.2.3. Programming Procedure
The output frequency is determined by programming
the output dividers (HS_DIV and N1) and the fine
frequency control value (RFREQ). The value
programmed into RFREQ is a high-resolution 38-bit
value that adjusts the DCO frequency in a range from
The following steps must be followed to set a new
output frequency:
1. Read the frequency configuration (RFREQ, HS_DIV,
and N1) from the device after power-up or reset.
4.85 to 5.67 GHz. The output of the DCO is divided 2. Calculate the actual nominal crystal frequency
down by HS_DIV and N1 to produce the desired output
frequency. The 38-bit length of RFREQ provides an
output frequency resolution of better than 1 ppb.
(f
) as: (f
= f x HS_DIV x N1)/RFREQ
XTAL
XTAL 0
where f is the nominal output frequency.
0
3. Choose new output frequency (f ).
1
4. Choose the output dividers (HS_DIV and N1) for the
new output frequency by ensuring the DCO
3.2. Frequency Programming Details
Programming consists of the following basic steps:
deriving the actual crystal frequency, choosing new
output dividers (HS_DIV & N1), calculating a new
frequency multiplier (RFREQ), and writing the new
frequency set into the device (HS_DIV, N1, and
RFREQ).
oscillation frequency (f ) is within the allowed
osc
internal oscillator frequency (See Table 12) where:
f
= f x HS_DIV x N1.
osc
1
5. Calculate the new crystal frequency multiplication
ratio (RFREQ ) as: f = f x RFREQ.
1
osc
XTAL
6. Freeze the DCO (bit 4 of Register 137).
3.2.1. Selecting the Correct Output Dividers
7. Write the frequency configuration (RFREQ, HS_DIV,
and N1).
By listing all of the combinations of HS_DIV and N1,
one can choose the output divider set with the lowest
power within the allowed internal oscillator frequency 8. Unfreeze the DCO and assert the NewFreq bit (bit 6
range as specified in Table 12. The sets of dividers
should be sorted to minimize f for power dissipation
of Register 135) within the maximum delay specified
in Table 12, “Programming Constraints,” on page 11.
osc
and to minimize N1 divider's power consumption.
Silicon Laboratories’ Si57x software automatically
provides this optimization and returns the smallest
HS_DIV x N1 combination with the highest HS_DIV
value.
3.2.4. Programming Procedure Example
The Si57x-EVB software can be used to generate
examples as needed.
12
Rev. 0.31
Si570/Si571
2
3.3. I C Interface
2
The control interface to the Si570 is an I C-compatible
2-wire bus for bidirectional communication. The bus
consists of a bidirectional serial data line (SDA) and a
serial clock input (SCL). Both lines must be connected
to the positive supply via an external pullup. Fast mode
operation is supported for transfer rates up to 400 kbps
2
as specified in the I C-Bus Specification standard.
Figure 3 shows the command format for both read and
write access. Data is always sent MSB first. The timing
2
specifications and timing diagram for the I C bus can be
2
found in the I C-Bus Specification standard (fast mode
2
operation). The device I C address is specified in the
part number.
S
S
Slave Address
0
A
Byte Address
A
Data
A
Data
A
P
Write Command
Slave Address
0
A
Byte Address
A
S
Slave Address
1
A
Data
A
Data
A
P
Read Command
Address auto incremented after each data read or write
A – Acknowledge (SDA LOW)
S – START condition
From master to slave
From slave to master
P – STOP condition
Figure 3. I2C Command Format
Rev. 0.31
13
Si570/Si571
4. Serial Port Registers
Note: Any register not listed here is reserved and must not be written. All bits are R/W unless otherwise noted.
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
7
High Speed/
N1 Dividers
HS_DIV[2:0]
N1[6:2]
8
9
Reference
Frequency
N1[1:0]
RFREQ[37:32]
Reference
Frequency
RFREQ[31:24]
RFREQ[23:16]
RFREQ[15:8]
RFREQ[7:0]
10
11
Reference
Frequency
Reference
Frequency
12
135
137
Reference
Frequency
Reset/Memory RST_REG NewFreq
Control
RECALL
Freeze DCO
Freeze
DCO
14
Rev. 0.31
Si570/Si571
Register 7. High Speed/N1 Dividers
Bit
D7
D6
HS_DIV[2:0]
R/W
D5
D4
D3
D2
N1[6:2]
R/W
D1
D0
Name
Type
Bit
Name
Function
7:5
HS_DIV[2:0] DCO High Speed Divider.
Sets value for high speed divider that takes the DCO output f
as its clock input.
OSC
000 = 4
001 = 5
010 = 6
011 = 7
100 = Not used.
101 = 9
110 = Not used.
111 = 11
4:0
N1[6:2]
CLKOUT Output Divider.
7
Sets value for CLKOUT output divider. Allowed values are [1] and [2, 4, 6, ..., 2 ]. Illegal
odd divider values will be rounded up to the nearest even value. The value for the N1 reg-
ister can be calculated by taking the divider ratio minus one. For example, to divide by 10,
write 0001001 (9 decimal) to the N1 registers.
0000000 = 1
7
1111111 = 2
Register 8. Reference Frequency
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
N1[1:0]
R/W
RFREQ[37:32]
R/W
Bit
Name
Function
7:6
N1[1:0]
CLKOUT Output Divider.
7
Sets value for CLKOUT output divider. Allowed values are [1, 2, 4, 6, ..., 2 ]. Illegal odd
divider values will be rounded up to the nearest even value. The value for the N1 regis-
ter can be calculated by taking the divider ratio minus one. For example, to divide by
10, write 0001001 (9 decimal) to the N1 registers.
0000000 = 1
7
1111111 = 2
5:0
RFREQ[37:32] Reference Frequency.
Frequency control input to DCO.
Rev. 0.31
15
Si570/Si571
Register 9. Reference Frequency
Bit
D7
D6
D5
D4
D3
D2
D2
D2
D1
D1
D1
D0
D0
D0
Name
Type
RFREQ[31:24]
R/W
Bit
Name
Function
7:0
RFREQ[31:24]
Reference Frequency.
Frequency control input to DCO.
Register 10. Reference Frequency
Bit
D7
D6
D5
D4
D3
Name
Type
RFREQ[23:16]
R/W
Bit
Name
Function
7:0
RFREQ[23:16] Reference Frequency.
Frequency control input to DCO.
Register 11. Reference Frequency
Bit
D7
D6
D5
D4
RFREQ[15:8]
R/W
D3
Name
Type
Bit
Name
Function
7:0
RFREQ[15:8] Reference Frequency.
Frequency control input to DCO.
16
Rev. 0.31
Si570/Si571
Register 12. Reference Frequency
Bit
D7
D6
D5
D4
RFREQ[7:0]
R/W
D3
D2
D1
D0
Name
Type
Bit
Name
Function
7:0
RFREQ[7:0]
Reference Frequency.
Frequency control input to DCO.
Register 135. Reset/Memory Control
Bit
Name RST_REG NewFreq
Type R/W R/W
Reset settings = 00xx xx00
D7
D6
D5
D4
D3
N/A
R/W
D2
D1
D0
RECALL
R/W
Bit
Name
Function
7
RST_REG
Internal Reset.
0 = Normal operation.
1 = Reset of all internal logic. Output tristated during reset.
Upon completion of internal logic reset, RST_REG is internally reset to zero.
6
NewFreq
New frequency applied.
Alerts the DSPLL that a new frequency configuration has been applied. This bit will
clear itself when the new frequency is applied.
5:1
0
N/A
Always zero.
RECALL
Recall NVM into RAM.
0 = No operation.
1 = Write NVM bits into RAM. Bit is internally reset following completion of operation.
Rev. 0.31
17
Si570/Si571
Register 137. Freeze DCO
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Freeze
DCO
Type
R/W
Reset settings = 00xx xx00
Bit
7:5
4
Name
Function
Reserved
Freeze DCO Freeze DCO.
Freezes the DSPLL so the frequency configuration can be modified.
3:0
Reserved
18
Rev. 0.31
Si570/Si571
5. Si570 (XO) Pin Descriptions
(Top View)
SDA
7
NC
VDD
1
2
3
6
5
4
OE
CLK–
CLK+
GND
8
SCL
Table 13. Si570 Pin Descriptions
Type
Pin
Name
Function
1
NC
N/A
No Connect.
Output Enable:
See "7. Ordering Information" on page 21.
2
OE
Input
3
4
GND
Ground
Output
Output
Electrical and Case Ground.
CLK+
Oscillator Output.
CLK–
(N/A for CMOS)
Complementary Output
(N/C for CMOS).
5
6
7
V
Power
Power Supply Voltage.
DD
2
SDA
Bidirectional
Open Drain
I C Serial Data.
2
8
SCL
Input
I C Serial Clock.
Rev. 0.31
19
Si570/Si571
6. Si571 (VCXO) Pin Descriptions
(Top View)
SDA
7
VC
VDD
1
6
5
4
OE
2
3
CLK–
CLK+
GND
8
SCL
Table 14. Si571 Pin Descriptions
Type
Pin
Name
Function
1
V
Analog Input
Input
Control Voltage
C
Output Enable:
2
OE
See "7. Ordering Information" on page 21.
Electrical and Case Ground
3
4
GND
Ground
Output
Output
CLK+
Oscillator Output
CLK–
(N/A for CMOS)
Complementary Output
(N/C for CMOS)
5
6
7
V
Power
Power Supply Voltage
DD
2
SDA
Bidirectional
Open Drain
I C Serial Data
2
8
SCL
Input
I C Serial Clock
20
Rev. 0.31
Si570/Si571
7. Ordering Information
The Si570/Si571 supports a wide variety of options including frequency range, start-up frequency, temperature
stability, tuning slope, output format, and V . Specific device configurations are programmed into the Si570/Si571
DD
at time of shipment. Configurations are specified using the Part Number Configuration chart shown below. Silicon
Labs provides a web browser-based part number configuration utility to simplify this process. Refer to
www.silabs.com/VCXOPartNumber to access this tool and for further ordering instructions. The Si570/Si571 XO/
VCXO series is supplied in an industry-standard, RoHS compliant, Pb-free, 8-pad, 5 x 7 mm package. Tape and
reel packaging is an ordering option.
X
X
D
G
R
57x
XXX XXX
X
R = Tape & Reel
Blank = Trays
Operating Temp Range (°C)
–40 to +85 °C
570 Programmable
XO Product Family
G
Device Revision Letter
571 Programmable
VCXO Product Family
Six-Digit Start-up Frequency/I2C Address Designator
The Si57x supports a user-defined start-up frequency within the following
bands of frequencies: 10–945 MHz, 970–1134 MHz, and 1213–1417 MHz.
The start-up frequency must be in the same frequency range as that
specified by the Frequency Grade 3rd option code.
1st Option Code
The Si57x supports a user-defined I2C 7-bit address. Each unique start-up
frequency/I2C address combination is assigned a six-digit numerical code.
This code can be requested during the part number request process. Refer
to www.silabs.com/VCXOPartNumber to request an Si57x part number.
VDD Output Format Output Enable Polarity
A
B
C
D
E
F
G
H
J
K
M
N
P
Q
R
S
T
3.3 LVPECL
3.3 LVDS
3.3 CMOS
3.3 CML
2.5 LVPECL
2.5 LVDS
2.5 CMOS
2.5 CML
1.8 CMOS
1.8 CML
3.3 LVPECL
3.3 LVDS
3.3 CMOS
3.3 CML
2.5 LVPECL
2.5 LVDS
2.5 CMOS
2.5 CML
1.8 CMOS
1.8 CML
High
High
High
High
High
High
High
High
High
High
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
3rd Option Code
Frequency Grade
Code
Frequency Range Supported (MHz)
10-945, 970-1134, 1213-1417.5
10-810
10-215
A
B
C
2nd Option Code
Code Temperature Stability (ppm, max, ±) Total Stablility (ppm, max, ±)
Si570
A
B
50
20
61.5
31.5
U
V
W
2nd Option Code
Temperature
Stability
± ppm (max)
Tuning Slope
Minimum APR
(±ppm) for VDD @
Note:
Kv
ppm/V (typ)
180
CMOS available to 160 MHz.
Code
A
B
C
3.3 V
100
30
150
80
2.5 V
75
Note 6
125
1.8 V
25
Note 6
75
100
100
50
90
180
90
D
50
30
25
E
F
G
H
J
K
M
20
50
20
20
20
100
20
45
135
356
180
135
356
33
25
Note 6
75
300
145
104
Note 6
50
235
105
70
100
375
185
130
295
12
220
Note 6
155
Note 6
Si571
Notes:
1. For best jitter and phase noise performance, always choose the smallest Kv that meets
the application’s minimum APR requirements. Unlike SAW-based solutions which
require higher higher Kv values to account for their higher temperature dependence,
the Si55x series provides lower Kv options to minimize noise coupling and jitter in real-
world PLL designs. See AN255 and AN266 for more information.
2. APR is the ability of a VCXO to track a signal over the product lifetime. A VCXO with an
APR of ±25 ppm is able to lock to a clock with a ±25 ppm stability over 15 years over all
operating conditions.
3. Nominal Pull range (±) = 0.5 x VDD x tuning slope.
4. Nominal Absolute Pull Range (±APR) = Pull range – stability – lifetime aging
=0.5 x VDD x tuning slope – stability – 10 ppm
5. Minimum APR values noted above include worst case values for all parameters.
6. Combination not available.
Figure 4. Part Number Convention
Rev. 0.31
21
Si570/Si571
8. Si57x Mark Specification
Figure 5 illustrates the mark specification for the Si57x. Table 15 lists the line information.
6
4
5
SiLabs 123
1 2 3 4 5 6 7 8 9 0
R T T T T Y W W +
1
2
3
Figure 5. Mark Specification
Table 15. Si57x Top Mark Description
Line
Position
1–10
Description
1
2
3
“SiLabs”+ Part Family Number, 5xx (First 3 characters in part number)
Si570, Si571: Option1 + Option2 + Option3 + ConfigNum(6) + Temp
1–10
Trace Code
Position 1
Pin 1 orientation mark (dot)
Product Revision (D)
Position 2
Tiny Trace Code (4 alphanumeric characters per assembly release instructions)
Year (least significant year digit), to be assigned by assembly site (ex: 2007 = 7)
Calendar Work Week number (1–53), to be assigned by assembly site
“+” to indicate Pb-Free and RoHS-compliant
Position 3–6
Position 7
Position 8–9
Position 10
22
Rev. 0.31
Si570/Si571
9. Outline Diagram and Suggested Pad Layout
Figure 6 illustrates the package details for the Si570/Si571. Table 16 lists the values for the dimensions shown in
the illustration.
Figure 6. Si570/Si571 Outline Diagram
Table 16. Package Diagram Dimensions (mm)
Dimension
Min
1.45
1.2
Nom
1.65
Max
1.85
1.6
A
b
1.4
c
0.60 TYP
1.17
d
0.97
6.10
1.37
6.30
D
7.00 BSC
6.2
D1
e
2.54 BSC
5.00 BSC
4.40
E
E1
L
4.30
1.07
0.8
4.50
1.47
1.2
1.27
M
1.0
S
1.815 BSC
0.7 REF
—
R
aaa
bbb
ccc
ddd
—
—
—
—
0.15
0.15
0.10
0.10
—
—
—
Rev. 0.31
23
Si570/Si571
10. 8-Pin PCB Land Pattern
Figure 7 illustrates the 8-pin PCB land pattern for the Si570/Si571. Table 17 lists the values for the dimensions
shown in the illustration.
Figure 7. Si570/Si571 PCB Land Pattern
Table 17. PCB Land Pattern Dimensions (mm)
Dimension
Min
Max
D2
D3
5.08 REF
5.705 REF
2.54 BSC
4.20 REF
e
E2
GD
GE
VD
VE
0.84
2.00
—
—
8.20 REF
7.30 REF
1.70 TYP
1.545 TYP
2.15 REF
1.3 REF
X1
X2
Y1
Y2
ZD
—
—
6.78
6.30
ZE
Note:
1. Dimensioning and tolerancing per the ANSI Y14.5M-1994
specification.
2. Land pattern design follows IPC-7351 guidelines.
3. All dimensions shown are at maximum material condition
(MMC).
4. Controlling dimension is in millimeters (mm).
24
Rev. 0.31
Si570/Si571
Revision 0.3 to Revision 0.31
DOCUMENT CHANGE LIST
ꢀ Updated "3.2.3. Programming Procedure" on page
12.
Revision 0.1 to Revision 0.2
ꢀ Updated " Description" on page 1.
ꢁ Corrected Step 6 to read “bit 4”.
ꢀ Corrected Freeze DCO bit location in Register 137 to
bit 4 on pages 14 and 18.
ꢀ Updated "1. Detailed Block Diagrams" on page 4 for
both XO and VCXO.
ꢀ Updated the Nominal Control Voltage in Table 2, “V
C
Control Voltage Input,” on page 5.
ꢀ Updated tables to reflect slight performance
differences between Si570 and Si571.
ꢀ Added detail to the "3.2. Frequency Programming
Details" on page 12.
ꢀ Revised "3.2.3. Programming Procedure" on page
12.
ꢁ Procedure now requires use of two frequency
configuration register sets.
ꢁ Procedure now recommends disabling output at
powerup to protect equipment not expecting the
default output frequency.
ꢀ Added second frequency configuration register set
to the register tables.
ꢀ Added frequency configuration select register.
ꢀ Updated "7. Ordering Information" on page 21 to be
consistent with the Si55x series devices.
Revision 0.2 to Revision 0.3
ꢀ Updated Table 1, “Recommended Operating
Conditions,” on page 5.
ꢁ Device maintains stable operation over –40 to +85 ºC
operating temperature range.
ꢁ Supply current specifications updated.
ꢀ Updated Table 4, “CLK± Output Levels and
Symmetry,” on page 7.
ꢁ Updated LVDS differential peak-peak swing
specifications.
ꢀ Updated Table 5, “CLK± Output Phase Jitter
(Si570),” on page 7.
ꢀ Updated Table 6, “CLK± Output Phase Jitter
(Si571),” on page 8.
ꢀ Updated Table 7, “CLK± Output Period Jitter,” on
page 9.
ꢁ Revised period jitter specifications.
ꢀ Updated Table 10, “Absolute Maximum Ratings,” on
page 10 to reflect the soldering temperature time at
260 ºC is 20–40 sec per JEDEC J-STD-020C.
ꢀ Updated device programming procedure in Section
"3.2.3. Programming Procedure" on page 12.
ꢀ Updated "7. Ordering Information" on page 21.
ꢁ Changed ordering instructions to revision D.
ꢀ Added "8. Si57x Mark Specification" on page 22.
Rev. 0.31
25
Si570/Si571
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Email: VCXOinfo@silabs.com
Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-
sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap-
plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
26
Rev. 0.31
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