591NB500M000DGR [SILICON]
Oscillator;型号: | 591NB500M000DGR |
厂家: | SILICON |
描述: | Oscillator |
文件: | 总15页 (文件大小:392K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Si590/591
1 ps MAX JITTER CRYSTAL OSCILLATOR (XO)
(10 MHZ TO 810 MHZ)
Features
Available with any-frequency output
frequencies from 10 to 810 MHz
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry Standard 5x7 and
3.2x5 mm packages
Pb-free/RoHS-compliant
–40 to +85 ºC operating
temperature range
®
3rd generation DSPLL with superior
jitter performance: 1 ps max jitter
Better frequency stability than SAW-
based oscillators
Internal fundamental mode crystal
ensures high reliability
Ordering Information:
Applications
See page 7.
SONET/SDH (OC-3/12/48)
Networking
SD/HD SDI/3G SDI video
Test and measurement
Storage
FPGA/ASIC clock generation
Pin Assignments:
See page 6.
Description
®
(Top View)
The Si590/591 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry
to provide a low jitter clock at high frequencies. The Si590/591 supports any
frequency from 10 to 810 MHz. Unlike a traditional XO, where a unique
crystal is required for each output frequency, the Si590/591 uses one fixed
crystal to provide a wide range of output frequencies. This IC based
approach allows the crystal resonator to provide exceptional frequency
stability and reliability. In addition, DSPLL clock synthesis provides superior
supply noise rejection, simplifying the task of generating low jitter clocks in
noisy environments typically found in communication systems. The
Si590/591 IC based XO is factory configurable for a wide variety of user
specifications including frequency, supply voltage, output format, and
stability. Specific configurations are factory programmed at time of shipment,
thereby eliminating long lead times associated with custom oscillators.
VDD
1
2
3
6
5
4
NC
OE
CLK–
CLK+
GND
Si590 (LVDS/LVPECL/CML)
VDD
1
2
3
6
5
4
OE
NC
Functional Block Diagram
NC
VDD
CLK– CLK+
GND
CLK
Si590 (CMOS)
17 k*
Any-rate
10–810 MHz
DSPLL®
Clock
Synthesis
Fixed
Frequency
XO
VDD
1
2
3
6
5
4
OE
NC
OE
CLK–
CLK+
17 k*
GND
Si591 (LVDS/LVPECL/CML)
*Note: Output Enable High/Low Options Available – See Ordering Information
GND
Rev. 1.1 12/17
Copyright © 2017 by Silicon Laboratories
Si590/591
Si590/591
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Symbol
Test Condition
Min
Typ
Max
Units
Parameter
1
V
3.3 V option
2.5 V option
1.8 V option
2.97
2.25
1.71
3.3
2.5
1.8
3.63
2.75
1.89
Supply Voltage
DD
V
Supply Current
I
Output enabled
LVPECL
CML
DD
—
—
—
—
110
100
90
125
110
100
90
mA
LVDS
CMOS
80
Tristate mode
—
0.75 x V
—
60
—
—
—
75
—
2
Output Enable (OE)
V
IH
DD
V
V
0.5
85
IL
Operating Temperature Range
T
–40
ºC
A
Notes:
1. Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 7 for further details.
2. OE pin includes an internal 17 k pullup resistor to VDD for output enable active high or a 17 k pull-down resistor to
GND for output enable active low. See 3. "Ordering Information" on page 7.
Table 2. CLK± Output Frequency Characteristics
Symbol
Test Condition
Min
Typ
Max
Units
Parameter
Nominal Frequency1,2
O
f
LVPECL/LVDS/CML
CMOS
10
10
—
—
810
160
MHz
Initial Accuracy
Total Stability
Measured at +25 °C at time of
shipping
fi
—
±1.5
—
ppm
Note 3, second option code “D”
Note 3, second option code “C”
Note 4, second option code “B”
Note 4, second option code “A”
second option code “D”
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
±20
±30
±50
±100
±7
ppm
ppm
ppm
ppm
ppm
ppm
ppm
ppm
ms
Temperature Stability
second option code “C”
±20
±25
±50
10
second option code “B”
second option code “A”
Powerup Time5
tOSC
Notes:
1. See Section 3. "Ordering Information" on page 7 for further details.
2. Specified at time of order by part number.
3. Includes initial accuracy, temperature, shock, vibration, power supply and load drift, and 10 years aging at 40 °C. See
3. "Ordering Information" on page 7.
4. Includes initial accuracy, temperature, shock, vibration, power supply and load drift, and 15 years aging at 70 °C. See
3. "Ordering Information" on page 7.
5. Time from powerup or tristate mode to fO.
2
Rev. 1.1
Si590/591
Table 3. CLK± Output Levels and Symmetry
Symbol
Test Condition
Min
Typ
Max
Units
Parameter
1
mid-level
swing (diff)
VDD – 1.42
1.1
—
—
—
VDD – 1.25
1.9
V
LVPECL Output Option
V
O
VOD
VSE
VPP
VPP
swing (single-ended)
mid-level
0.55
0.95
2
LVDS Output Option
V
O
1.125
0.5
1.20
0.7
1.275
0.9
V
swing (diff)
VOD
VO
VPP
2.5/3.3 V option mid-level
1.8 V option mid-level
—
—
V
V
– 1.30
—
—
DD
V
– 0.36
DD
2
CML Output Option
2.5/3.3 V option swing (diff)
1.8 V option swing (diff)
1.10
1.50
1.90
VOD
VPP
0.35
0.425
—
0.50
VDD
0.4
3
CMOS Output Option
VOH
VOL
0.8 x VDD
V
—
—
—
—
Rise/Fall time (20/80%)
Symmetry (duty cycle)
tR, F
t
LVPECL/LVDS/CML
—
350
—
ps
ns
CMOS with C = 15 pF
2
L
SYM
LVPECL:
LVDS:
CMOS:
V
– 1.3 V (diff)
DD
1.25 V (diff)
/2
45
—
55
%
V
DD
Notes:
1. 50 to VDD – 2.0 V.
2. Rterm = 100 (differential).
3. CL = 15 pF. Sinking or sourcing 12 mA for VDD = 3.3 V, 6 mA for VDD = 2.5 V, 3 mA for VDD = 1.8 V.
Table 4. CLK± Output Phase Jitter
Parameter
Symbol
Test Condition
Min
Typ
Max Units
1
Phase Jitter (RMS)
J
12 kHz to 20 MHz
—
0.5
1.0
ps
for 50 MHz < F
< 810 MHz
OUT
(LVPECL/LVDS/CML)
1
Phase Jitter (RMS)
J
J
12 kHz to 20 MHz,
155.52 MHz output frequency
—
—
0.4
0.6
0.7
1.0
ps
ps
(LVPECL/LVDS/CML)
2
Phase Jitter (RMS)
12 kHz to 20 MHz
for 50 MHz < F
(CMOS)
< 160 MHz
OUT
Notes:
1. Refer to AN256 for further information.
2. Single-ended CMOS output phase jitter measured using 33 series termination into 50 phase noise test equipment.
3.3 V supply voltage option only.
Rev. 1.1
3
Si590/591
Table 5. CLK± Output Period Jitter
Parameter
Symbol
Test Condition
RMS
Min
—
Typ
—
Max
3
Units
Period Jitter*
J
ps
PER
Peak-to-Peak
—
—
35
*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information.
\Table 6. Environmental Compliance and Package Information
Parameter
Conditions/Test Method
MIL-STD-883, Method 2002
MIL-STD-883, Method 2007
MIL-STD-883, Method 2003
MIL-STD-883, Method 1014
MIL-STD-883, Method 2036
Gold over Nickel
Mechanical Shock
Mechanical Vibration
Solderability
Gross and Fine Leak
Resistance to Solder Heat
Contact Pads
Table 7. Thermal Characteristics
(Typical values TA = 25 ºC, VDD = 3.3 V)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
5x7mm, Thermal Resistance Junction to
Ambient
Still Air
—
84.6
—
°C/W
JA
5x7mm, Thermal Resistance Junction to
Case
Still Air
Still Air
Still Air
—
—
—
38.8
31.1
13.3
—
—
—
°C/W
°C/W
°C/W
JC
3.2x5mm, Thermal Resistance Junction to
Ambient
JA
3.2x5mm, Thermal Resistance Junction to
Case
JC
Ambient Temperature
Junction Temperature
T
–40
—
—
—
85
°C
°C
A
T
125
J
4
Rev. 1.1
Si590/591
Table 8. Absolute Maximum Ratings1
Symbol
Rating
Units
Parameter
Maximum Operating Temperature
Supply Voltage, 1.8 V Option
Supply Voltage, 2.5/3.3 V Option
Input Voltage (any input pin)
Storage Temperature
T
85
ºC
V
AMAX
V
V
–0.5 to +1.9
–0.5 to +3.8
DD
DD
V
V
–0.5 to V + 0.3
V
ºC
I
DD
T
–55 to +125
2500
S
ESD Sensitivity (HBM, per JESD22-A114)
ESD
V
2
Soldering Temperature (Pb-free profile)
T
260
ºC
PEAK
2
Soldering Temperature Time @ T
(Pb-free profile)
t
20–40
seconds
PEAK
P
Notes:
1. Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional
operation or specification compliance is not implied at these conditions. Exposure to maximum rating conditions for
extended periods may affect device reliability.
2. The device is compliant with JEDEC J-STD-020C. Refer to Si5xx Packaging FAQ available for download at
www.silabs.com/VCXO for further information, including soldering profiles.
Rev. 1.1
5
Si590/591
2. Pin Descriptions
(Top View)
VDD
VDD
VDD
1
2
3
6
5
4
1
2
3
6
5
4
1
2
3
6
5
4
OE
NC
NC
OE
OE
NC
NC
CLK–
CLK+
CLK–
CLK+
GND
GND
GND
CLK
Si591
LVDS/LVPECL/CML
Si590
Si590
LVDS/LVPECL/CML
CMOS
Table 9. Pinout for Si590 Series
Pin
Symbol
LVDS/LVPECL/CML Function
No connection
Make no external connection to this pin
CMOS Function
Output enable
1
OE*
Output enable
No connection
2
OE*
Make no external connection to this pin
Electrical and Case Ground
Oscillator Output
3
4
5
GND
CLK+
CLK–
Electrical and Case Ground
Oscillator Output
Complementary Output
No connection
Make no external connection to this pin
6
V
Power Supply Voltage
Power Supply Voltage
DD
*Note: OE pin includes an internal 17 k pullup resistor to VDD for output enable active high or a 17 k pulldown resistor to
GND for output enable active low. See 3. "Ordering Information" on page 7.
Table 10. Pinout for Si591 Series
Pin
Symbol
LVDS/LVPECL/CML Function
1
OE*
Output enable
No connection
Make no external connection to this pin
No connection
Make no external connection to this pin
2
3
4
5
6
GND
CLK+
CLK–
Electrical and Case Ground
Oscillator Output
Complementary output
Power Supply Voltage
V
DD
*Note: OE pin includes an internal 17 k pullup resistor to VDD for output enable active high or a 17 k pulldown resistor to
GND for output enable active low. See 3. "Ordering Information" on page 7.
6
Rev. 1.1
Si590/591
3. Ordering Information
The Si590/591 XO supports a variety of options including frequency, temperature stability, output format, and V
.
DD
Specific device configurations are programmed into the Si590/591 at time of shipment. Configurations can be
specified using the Part Number Configuration chart below. Silicon Laboratories provides a web browser-based
part number configuration utility to simplify this process. To access this tool refer to www.silabs.com/oscillators and
click “Customize” in the product table. The Si590 and Si591 XO series are supplied in an industry-standard, RoHS
compliant, 6-pad, 5 x 7 mm and 3.2 x 5 mm packages. The Si591 Series supports an alternate OE pinout (pin #1)
for LVPECL, LVDS, and CML output formats. See Tables 9 and 10 for the pinout differences between the Si590
and Si591 series.
X
59x
XXXMXXX
G
R
X
D
Tape & Reel Packaging
Blank = Trays
590 or 591 XO
Product Family
Operating Temp Range (°C)
–40 to +85°C
G
1st Option Code
VDD Output Format Output Enable Polarity
Part Revision Letter
Frequency (e.g., 148M352 is 148.352 MHz)
A
B
C
D
E
F
G
H
J
K
M
N
P
Q
R
S
T
3.3 LVPECL
3.3 LVDS
3.3 CMOS
3.3 CML
High
High
High
High
High
High
High
High
High
High
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Available frequency range is 10 to 810 MHz. The position of “M” shifts
to denote higher or lower frequencies. If the frequency of interest
requires greater than 6 digit resolution, a six digit code will be
assigned for the specific frequency.
2.5 LVPECL
2.5 LVDS
2.5 CMOS
2.5 CML
2nd Option Code
1.8 CMOS
1.8 CML
Code Package Total Stablility (ppm, max, ±) Temperature Stablility (ppm, max, ±)
3.3 LVPECL
3.3 LVDS
3.3 CMOS
3.3 CML
A
B
C
D
E
F
5x7 mm
5x7 mm
5x7 mm
5x7 mm
3.2x5 mm
3.2x5 mm
3.2x5 mm
100
50
30
20
100
50
50
25
20
7
50
25
20
2.5 LVPECL
2.5 LVDS
2.5 CMOS
2.5 CML
G
30
U
V
W
1.8 CMOS
1.8 CML
Note:
CMOS available to 160 MHz.
Example P/N: 590BB148M352DGR is a 5 x 7 XO in a 6 pad package. The frequency is 148.352 MHz, with a 3.3 V supply, LVDS output, and
Output Enable active high polarity. Overall stability is specifed as ± 50 ppm. The device is specified for –40 to +85 °C ambient temperature
range operation and is shipped in tape and reel format.
Figure 1. Part Number Convention
Rev. 1.1
7
Si590/591
4. Package Outline Drawing: 5 x 7 mm, 6-pin
Figure 2 illustrates the package details for the 5 x 7 mm Si590/591. Table 11 lists the values for the dimensions
shown in the illustration.
Figure 2. Si590/591 Outline Diagram
Table 11. Package Diagram Dimensions (mm)
Dimension
Min
1.50
1.30
0.50
Nom
1.65
Max
1.80
1.50
0.70
A
b
1.40
c
0.60
D
5.00 BSC
4.40
D1
e
4.30
4.50
2.54 BSC
7.00 BSC
6.20
E
E1
H
6.10
0.55
1.17
0.05
1.80
6.30
0.75
1.37
0.15
2.60
0.65
L
1.27
L1
p
0.10
—
R
0.70 REF
0.15
aaa
bbb
ccc
ddd
eee
0.15
0.10
0.10
0.05
8
Rev. 1.1
Si590/591
5. PCB Land Pattern: 5 x 7 mm, 6-pin
Figure 3 illustrates the 6-pin PCB land pattern for the 5 x 7 mm Si590/591. Table 12 lists the values for the
dimensions shown in the illustration.
Figure 3. Si590/591 PCB Land Pattern
Table 12. PCB Land Pattern Dimensions (mm)
Dimension
(mm)
4.20
2.54
1.55
1.95
C1
E
X1
Y1
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between
the solder mask and the metal pad is to be 60 µm minimum, all the way around
the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls
should be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
Rev. 1.1
9
Si590/591
6. Package Outline Drawing: 3.2 x 5 mm, 6-pin
Figure illustrates the package details for the 3.2 x 5 mm Si590/591. Table 13 lists the values for the dimensions
shown in the illustration.
Figure 4. Si590/591 Outline Diagram
Table 13. Package Diagram Dimensions (mm)
Dimension
Min
1.02
0.99
Nom
1.17
1.10
Max
1.32
1.21
Dimension
Min
Nom
2.85 BSC
1.91 BSC
0.45
0.10
0.10 REF
0.15
Max
A
A1
A2
A3
b
E1
E2
L
0.5 BSC
0.30 BSC
0.35
0.05
0.55
0.15
L2
0.54
0.35
R1
aaa
bbb
ccc
ddd
eee
0.64
0.45
5.00 BSC
0.74
0.55
B1
D
0.15
D1
4.65 BSC
3.38 BSC
1.27 BSC
3.20 BSC
0.08
D2
e
E
0.10
0.05
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
10
Rev. 1.1
Si590/591
7. PCB Land Pattern: 3.2 x 5 mm, 6-pin
Figure 5 illustrates the 6-pin PCB land pattern for the 3.2 x 5 mm Si590/591. Table 14 lists the values for the
dimensions shown in the illustration.
Figure 5. Si590/591 PCB Land Pattern
Table 14. PCB Land Pattern Dimensions (mm)
Dimension
(mm)
2.91
1.27
0.80
1.10
C1
E
X1
Y1
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition
(LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used
to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for
Small Body Components.
Rev. 1.1
11
Si590/591
8. Si590/Si591 Top Marking: 5 x 7 mm
Figure 6 illustrates the mark specification for the 5 x 7 mm Si590/Si591. Table 15 lists the line information.
Figure 6. Top Mark Specification
Table 15. Si59x Top Mark Description
Line
Position
Description
1
1–10
“SiLabs”+ Part Family Number, 59x (First 3 characters in part number where x = 0
indicates a 590 device and x = 1 indicates a 591 device)
2
3
1–10
Si590, Si591: Option1 + Option2 + Freq(7) + Temp
Si590/Si591 w/ 8-digit resolution: Option1 + Option2 + ConfigNum(6) + Temp
Trace Code
Position 1
Pin 1 orientation mark (dot)
Product Revision (D)
Position 2
Tiny Trace Code (4 alphanumeric characters per assembly release instructions)
Year (least significant year digit), to be assigned by assembly site (ex: 2009 = 9)
Calendar Work Week number (1–53), to be assigned by assembly site
“+” to indicate Pb-Free and RoHS-compliant
Position 3–6
Position 7
Position 8–9
Position 10
12
Rev. 1.1
Si590/591
9. Si590/Si591 Top Marking: 3.2 x 5 mm
Figure 7 illustrates the mark specification for the 3.2 x 5 mm Si590/Si591. Table 16 lists the line information.
Figure 7. Top Mark Specification
Table 16. Si59x Top Mark Description
Line
Position
Description
1
1–5
“Si”+ Part Family Number, 59x (First 3 characters in part number where x = 0 indi-
cates a 590 device and x = 1 indicates a 591 device)
6–8
1–9
Crystal trace code (3 alphanumeric characters assigned by assembly site)
2
3
Si590, Si591: Option1 + Option2 + Freq(7)
Si590/Si591 w/ 8-digit resolution: Option1 + Option2 + ConfigNum(6)
Trace Code
Position 1
Pin 1 orientation mark (dot)
Product Revision (D)
Position 2
Tiny Trace Code (3 alphanumeric characters per assembly release instructions)
Year (last two digits of year), to be assigned by assembly site (ex: 20017 = 17)
Calendar Work Week number (1–53), to be assigned by assembly site
Position 3–5
Position 6–7
Position 8–9
Rev. 1.1
13
Si590/591
REVISION HISTORY
Revision 1.1
December, 2017
Added 3.2 x 5 mm package.
Revision 1.0
Updated 2.5 V/3.3 V and 1.8 V CML output level specifications in Table 3 on page 3.
Updated Si590/591 devices to support frequencies up to 810 MHz for LVPECL, LVDS, and CML outputs.
Separated 1.8 V, 2.5 V/3.3 V supply voltage. specifications for CML output in Table 3 on page 3.
Updated Note 1 of Table 4 on page 3 to refer to AN256.
Updated Table 4 on page 3.
Updated phase jitter specification.
Updated Table 6 on page 4 to include the "Moisture Sensitivity Level" and "Contact Pads" rows.
Updated Figure 3 and Table 15 on page 12 to reflect specific marking information.
Added Table 7, “Thermal Characteristics,” on page 4.
Rearranged sections to conform to new quality standard.
Revision 0.4
Added ±7 ppm temperature stability ordering option in Table 4 on page 3 and Figure 1 on page 7.
Revision 0.3
Updated Table 4 on page 3 by adding the 155.51 MHz “Phase Jitter (RMS) (LVPECL/LVDS/CML)” row.
Updated and clarified Table 6 on page 4 to correct typos and include the “Moisture Sensitivity Level” and
“Contact Pads” rows.
Corrected BSC value in rows D and E in Table 11 on page 8.
Revision 0.25
Total Stability Maximum changed to ±30 in Table 2 on page 2.
Total Stability Maximum changed to ±30 in Figure 1 on page 7.
14
Rev. 1.1
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Trademark Information
Silicon Laboratories Inc.® , Silicon Laboratories®, Silicon Labs®, SiLabs® and the Silicon Labs logo®, Bluegiga®, Bluegiga Logo®, Clockbuilder®, CMEMS®, DSPLL®, EFM®,
EFM32®, EFR, Ember®, Energy Micro, Energy Micro logo and combinations thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZRadio®, EZRadioPRO®,
Gecko®, ISOmodem®, Micrium, Precision32®, ProSLIC®, Simplicity Studio®, SiPHY®, Telegesis, the Telegesis Logo®, USBXpress®, Zentri and others are trademarks or registered
trademarks of Silicon Labs. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or registered trademarks of ARM Holdings. Keil is a registered trademark of ARM Limited. All other
products or brand names mentioned herein are trademarks of their respective holders.
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
USA
http://www.silabs.com
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