595SC525M000DG [SILICON]

Oscillator;
595SC525M000DG
型号: 595SC525M000DG
厂家: SILICON    SILICON
描述:

Oscillator

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Si595  
REVISION D  
VOLTAGE-CONTROLLED CRYSTAL OSCILLATOR (VCXO)  
10 TO 525 MHZ  
Features  
Available with any-rate output  
frequencies from 10 to 525 MHz  
Available CMOS, LVPECL,  
LVDS, and CML outputs  
®
3.3, 2.5, and 1.8 V supply options  
Industry-standard 5 x 7 mm  
package and pinout  
Pb-free/RoHS-compliant  
–40 to +85 ºC operating range  
3rd generation DSPLL with  
superior jitter performance  
Internal fixed fundamental mode  
crystal frequency ensures high  
reliability and low aging  
Applications  
Ordering Information:  
See page 7.  
SONET/SDH (OC-3/12/48)  
Networking  
SD/HD SDI/3G SDI video  
FTTx  
Clock recovery and jitter cleanup PLLs  
FPGA/ASIC clock generation  
Pin Assignments:  
Description  
See page 6.  
®
The Si595 VCXO utilizes Silicon Laboratories’ advanced DSPLL circuitry to  
provide a low-jitter clock at high frequencies. The Si595 is available with  
any-rate output frequency from 10 to 525 MHz. Unlike traditional VCXOs,  
where a different crystal is required for each output frequency, the Si595  
uses one fixed crystal to provide a wide range of output frequencies. This IC-  
based approach allows the crystal resonator to provide exceptional  
frequency stability and reliability. In addition, DSPLL clock synthesis  
provides supply noise rejection, simplifying the task of generating low-jitter  
clocks in noisy environments. The Si595 IC-based VCXO is factory-  
configurable for a wide variety of user specifications including frequency,  
supply voltage, output format, tuning slope, and absolute pull range (APR).  
Specific configurations are factory programmed at time of shipment, thereby  
eliminating the long lead times associated with custom oscillators.  
(Top View)  
VC  
VDD  
1
2
3
6
5
4
OE  
CLK–  
CLK+  
GND  
Functional Block Diagram  
CLK– CLK+  
VDD  
Any-rate  
10–525 MHz  
DSPLL®  
Fixed  
Frequency  
XO  
Clock Synthesis  
ADC  
Vc  
OE  
GND  
Preliminary Rev. 0.2 8/09  
Copyright © 2009 by Silicon Laboratories  
Si595  
Si595  
1. Electrical Specifications  
Table 1. Recommended Operating Conditions  
Parameter  
Symbol  
Test Condition  
3.3 V option  
2.5 V option  
1.8 V option  
Min  
2.97  
2.25  
1.71  
Typ  
3.3  
2.5  
1.8  
Max  
3.63  
2.75  
1.89  
Units  
1
V
DD  
Supply Voltage  
V
Supply Current  
I
Output enabled  
LVPECL  
CML  
DD  
135  
120  
110  
100  
120  
110  
100  
90  
mA  
LVDS  
CMOS  
Tristate mode  
0.75 x V  
60  
75  
2
Output Enable (OE)  
V
IH  
DD  
V
V
0.5  
85  
IL  
Operating Temperature Range  
T
–40  
°C  
A
Notes:  
1. Selectable parameter specified by part number. See 3. "Ordering Information" on page 7 for further details.  
2. OE pin includes an internal 17 kpullup resistor to VDD for output enable active high or a 17 kpull-down resistor to  
GND for output enable active low. See 3. "Ordering Information" on page 7.  
Table 2. VC Control Voltage Input  
Parameter  
Symbol  
Test Condition  
Min  
Typ  
Max  
Units  
1,2,3  
Control Voltage Tuning Slope  
K
10 to 90% of V  
45  
95  
ppm/V  
V
DD  
125  
185  
380  
4
Control Voltage Linearity  
L
BSL  
–5  
–10  
9.3  
500  
±1  
±5  
+5  
+10  
10.7  
VC  
%
Incremental  
Modulation Bandwidth  
BW  
10.0  
kHz  
k  
pF  
V
V Input Impedance  
Z
C
VC  
V Input Capacitance  
C
50  
C
VC  
Nominal Control Voltage  
V
@ f  
V /2  
DD  
CNOM  
O
Control Voltage Tuning Range  
V
0
V
V
C
DD  
Notes:  
1. Positive slope; selectable option by part number. See 3. "Ordering Information" on page 7.  
2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR  
requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.  
3. KV variation is ±10% of typical values.  
4. BSL determined from deviation from best straight line fit with VC ranging from 10 to 90% of VDD. Incremental slope  
determined with VC ranging from 10 to 90% of VDD  
.
2
Preliminary Rev. 0.2  
Si595  
Table 3. CLK± Output Frequency Characteristics  
Parameter  
Symbol  
Test Condition  
LVDS/CML/LVPECL  
CMOS  
Min  
10  
Typ  
Max  
Units  
1,2,3  
1,4  
f
525  
160  
O
Nominal Frequency  
MHz  
10  
Temperature Stability  
T = –40 to +85 ºC  
–20  
–50  
+20  
+50  
A
ppm  
1,4  
Absolute Pull Range  
APR  
tOSC  
V
= 3.3 V  
±15  
±370  
10  
ppm  
ms  
DD  
5
Power up Time  
Notes:  
1. See Section 3. "Ordering Information" on page 7 for further details.  
2. Specified at time of order by part number.  
3. Nominal output frequency set by VCNOM = VDD/2.  
4. Selectable parameter specified by part number.  
5. Time from power up or tristate mode to fO.  
Table 4. CLK± Output Levels and Symmetry  
Parameter  
Symbol  
Test Condition  
mid-level  
Min  
Typ  
Max  
VDD – 1.25  
1.9  
Units  
V
1
LVPECL Output Option  
V
VDD – 1.42  
1.1  
O
VOD  
VSE  
swing (diff)  
VPP  
VPP  
swing (single-ended)  
mid-level  
0.55  
0.95  
2
LVDS Output Option  
V
1.125  
0.5  
1.20  
0.7  
1.275  
0.9  
V
O
swing (diff)  
VOD  
VPP  
2
CML Output Option  
VO  
mid-level  
0.70  
0.8 x VDD  
V
– 0.75  
1.20  
VDD  
0.4  
V
DD  
VOD  
VOH  
VOL  
swing (diff)  
0.95  
VPP  
3
CMOS Output Option  
V
tR, F  
t
Rise/Fall time (20/80%)  
Symmetry (duty cycle)  
LVPECL/LVDS/CML  
350  
ps  
ns  
CMOS with C = 15 pF  
2
L
SYM  
LVPECL:  
LVDS:  
CMOS:  
V
– 1.3 V (diff)  
DD  
1.25 V (diff)  
/2  
45  
55  
%
V
DD  
Notes:  
1. 50 to VDD – 2.0 V.  
2. Rterm = 100 (differential).  
3. CL = 15 pF. Sinking or sourcing 12 mA for VDD = 3.3 V, 6 mA for VDD = 2.5 V, 3 mA for VDD = 1.8 V.  
Preliminary Rev. 0.2  
3
Si595  
Table 5. CLK± Output Phase Jitter  
Parameter  
Symbol  
Test Condition  
Kv = 45 ppm/V  
Min  
Typ  
0.5  
0.5  
0.5  
0.5  
0.7  
Max  
Units  
1,2  
Phase Jitter (RMS)  
J  
ps  
for F  
525 MHz  
of 50 MHz < F  
12 kHz to 20 MHz  
OUT  
OUT  
Kv = 95 ppm/V  
12 kHz to 20 MHz  
Kv = 125 ppm/V  
12 kHz to 20 MHz  
Kv = 185 ppm/V  
12 kHz to 20 MHz  
Kv = 380 ppm/V  
12 kHz to 20 MHz  
Notes:  
1. Differential Modes: LVPECL/LVDS/CML. Refer to AN256 and AN266 for further information.  
2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR  
requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.  
Table 6. CLK± Output Period Jitter  
Parameter  
Period Jitter*  
Symbol  
Test Condition  
RMS  
Min  
Typ  
3
Max  
Units  
J
ps  
PER  
Peak-to-Peak  
35  
*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information.  
Table 7. CLK± Output Phase Noise (Typical)  
Offset Frequency  
74.25 MHz  
185 ppm/V  
LVPECL  
148.5 MHz  
185 ppm/V  
LVPECL  
155.52 MHz  
95 ppm/V  
LVPECL  
Units  
100 Hz  
1 kHz  
10 kHz  
100 kHz  
1 MHz  
–77  
–68  
–95  
–77  
–101  
–121  
–134  
–149  
–151  
–150  
–101  
–119  
–127  
–144  
–147  
–148  
–116  
–128  
–144  
–147  
–148  
dBc/Hz  
10 MHz  
20 MHz  
Table 8. Absolute Maximum Ratings1  
Parameter  
Maximum Operating Temperature  
Supply Voltage  
Symbol  
Rating  
Units  
T
85  
ºC  
V
AMAX  
V
–0.5 to +3.8  
DD  
4
Preliminary Rev. 0.2  
Si595  
Table 8. Absolute Maximum Ratings1  
Parameter  
Input Voltage  
Symbol  
Rating  
Units  
Volts  
ºC  
V
–0.5 to V + 0.3  
I
DD  
Storage Temperature  
T
–55 to +125  
2500  
S
ESD Sensitivity (HBM, per JESD22-A114)  
ESD  
Volts  
ºC  
2
Soldering Temperature (Pb-free profile)  
T
260  
PEAK  
2
Soldering Temperature Time @ T  
(Pb-free profile)  
t
20–40  
seconds  
PEAK  
P
Notes:  
1. Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional  
operation or specification compliance is not implied at these conditions. Exposure to maximum rating conditions for  
extended periods may affect device reliability.  
2. The device is compliant with JEDEC J-STD-020C. Refer to Si5xx Packaging FAQ available for download from  
www.silabs.com/VCXO for further information, including soldering profiles.  
Table 9. Environmental Compliance  
The Si595 meets the following qualification test requirements.  
Parameter  
Conditions/Test Method  
MIL-STD-883G, Method 2002.3 B  
MIL-STD-883G, Method 2007.3 A  
MIL-STD-883G, Method 203.8  
MIL-STD-883G, Method 1014.7  
MIL-STD-883G, Method 2015  
Mechanical Shock  
Mechanical Vibration  
Solderability  
Gross & Fine Leak  
Resistance to Solvents  
Preliminary Rev. 0.2  
5
Si595  
2. Pin Descriptions  
(Top View)  
VC  
VDD  
1
2
3
6
5
4
OE  
CLK–  
CLK+  
GND  
Table 10. Si595 Pin Descriptions  
Type  
Pin  
1
Name  
Function  
V
Analog Input  
Input  
Control Voltage  
Output Enable  
C
2
OE*  
GND  
CLK+  
3
Ground  
Output  
Electrical and Case Ground  
Oscillator Output  
4
CLK–  
(N/C for CMOS)  
Output  
Complementary Output  
(N/C for CMOS, do not make external connection)  
5
6
V
Power  
Power Supply Voltage  
DD  
*Note: OE pin includes a 17 kresistor to VDD for OE active high option or 17 kto GND for OE active low option.  
See 3. "Ordering Information" on page 7.  
6
Preliminary Rev. 0.2  
Si595  
3. Ordering Information  
The Si595 supports a variety of options including frequency, temperature stability, tuning slope, output format, and  
. Specific device configurations are programmed into the Si595 at time of shipment. Configurations are  
V
DD  
specified using the Part Number Configuration chart shown below. Silicon Labs provides a web browser-based part  
number configuration utility to simplify this process. Refer to www.silabs.com/VCXOPartNumber to access this tool  
and for further ordering instructions. The Si595 VCXO series is supplied in an industry-standard, RoHS compliant,  
lead-free, 6-pad, 5 x 7 mm package. Tape and reel packaging is an ordering option.  
X
X
D
G
R
595  
XXXMXXX  
R = Tape & Reel  
Blank = Trays  
595 VCXO  
Product Family  
Operating Temp Range (°C)  
–40 to +85 °C  
G
Device Revision Letter  
Frequency (e.g., 148M500 is 148.5 MHz)  
Available frequency range is 10 to 525 MHz. The position of “M” shifts  
to denote higher or lower frequencies. If the frequency of interest  
requires greater than 6 digit resolution, a six digit code will be  
assigned for the specific frequency.  
1st Option Code  
VDD Output Format Output Enable Polarity  
2nd Option Code  
Temperature  
Stability  
± ppm (max)  
Tuning Slope  
Minimum APR  
A
B
C
D
E
F
G
H
J
K
M
N
P
Q
R
S
T
3.3 LVPECL  
3.3 LVDS  
3.3 CMOS  
3.3 CML  
High  
High  
High  
High  
High  
High  
High  
High  
High  
High  
Low  
Low  
Low  
Low  
Low  
Low  
Low  
Low  
Low  
Low  
Kv  
ppm/V (typ)  
380  
(±ppm) for VDD @  
Code  
A
B
C
D
E
F
G
H
3.3 V  
370  
160  
130  
100  
65  
2.5 V  
275  
110  
80  
75  
50  
45  
20  
N/A  
1.8 V  
200  
80  
50  
40  
25  
10  
N/A  
N/A  
20  
20  
50  
20  
20  
50  
50  
20  
185  
185  
125  
95  
125  
95  
45  
2.5 LVPECL  
2.5 LVDS  
2.5 CMOS  
2.5 CML  
70  
35  
15  
1.8 CMOS  
1.8 CML  
3.3 LVPECL  
3.3 LVDS  
3.3 CMOS  
3.3 CML  
Notes:  
1. For best jitter and phase noise performance, always choose the smallest Kv that meets  
the application’s minimum APR requirements. Lower Kv options minimize noise  
coupling and jitter in real-world PLL designs. See AN266 for more information.  
2. APR is the ability of a VCXO to track a signal over the product lifetime. A VCXO with an  
APR of ±100 ppm is able to lock to a clock with a ±100 ppm stability over 15 years over  
all operating conditions.  
2.5 LVPECL  
2.5 LVDS  
2.5 CMOS  
2.5 CML  
U
V
W
1.8 CMOS  
1.8 CML  
3. Nominal Pull range (±) = 0.5 x VDD x tuning slope.  
4. Minimum APR values noted above include worst case values for all parameters.  
Note:  
CMOS available to 160 MHz.  
Example Part Number: 595AE148M500DGR is a 5 x 7 mm VCXO in a 6 pad package. The nominal frequency is 148.5 MHz, with a 3.3 V supply,  
LVPECL output, and Output Enable active high polarity. Temperature stability is specified as ±20 ppm and the tuning slope is 95 ppm/V. The part is  
specified for a –40 to +85 C° ambient temperature range operation and is shipped in tape and reel format.  
Figure 1. Part Number Convention  
Preliminary Rev. 0.2  
7
Si595  
4. Outline Diagram and Suggested Pad Layout  
Figure 2 illustrates the package details for the Si595. Table 11 lists the values for the dimensions shown in the  
illustration.  
Figure 2. Si595 Outline Diagram  
Table 11. Package Diagram Dimensions (mm)  
Dimension  
Min  
1.50  
1.30  
0.50  
Nom  
1.65  
Max  
1.80  
1.50  
0.70  
A
b
1.40  
c
0.60  
D
7.00 BSC  
4.40  
D1  
e
4.30  
4.50  
2.54 BSC.  
5.00 BSC.  
6.20  
E
E1  
H
6.10  
0.55  
1.17  
1.80  
6.30  
0.75  
1.37  
2.60  
0.65  
L
1.27  
p
R
0.70 REF  
0.15  
aaa  
bbb  
ccc  
ddd  
eee  
0.15  
0.10  
0.10  
0.50  
8
Preliminary Rev. 0.2  
Si595  
5. Si5xx Mark Specification  
Figure 3 illustrates the mark specification for the Si595. Table 12 lists the line information.  
6
4
5
SiLabs 123  
1 2 3 4 5 6 7 8 9 0  
R T T T T Y W W +  
1
2
3
Figure 3. Mark Specification  
Table 12. Si5xx Top Mark Description  
Description  
Line  
Position  
1–10  
1
2
“SiLabs”+ Part Family Number, 595 (First 3 characters in part number)  
1–10  
Si595: Option1+Option2+Freq(7)+Temp  
Si595 w/ 8-digit resolution: Option1+Option2+ConfigNum(6)+Temp  
3
Trace Code  
Position 1  
Pin 1 orientation mark (dot)  
Product Revision (D)  
Position 2  
Tiny Trace Code (4 alphanumeric characters per assembly release instructions)  
Year (least significant year digit), to be assigned by assembly site (ex: 2009 = 9)  
Calendar Work Week number (1–53), to be assigned by assembly site  
“+” to indicate Pb-Free and RoHS-compliant  
Position 3–6  
Position 7  
Position 8–9  
Position 10  
Preliminary Rev. 0.2  
9
Si595  
6. 6-Pin PCB Land Pattern  
Figure 4 illustrates the 6-pin PCB land pattern for the Si595. Table 13 lists the values for the dimensions shown in  
the illustration.  
Figure 4. Si595 PCB Land Pattern  
Table 13. PCB Land Pattern Dimensions (mm)  
Dimension  
Min  
Max  
D2  
e
5.08 REF  
2.54 BSC  
4.15 REF  
E2  
GD  
GE  
VD  
VE  
X
0.84  
2.00  
8.20 REF  
7.30 REF  
1.70 TYP  
2.15 REF  
Y
ZD  
ZE  
6.78  
6.30  
Notes:  
1. Dimensioning and tolerancing per the ANSI Y14.5M-1994 specification.  
2. Land pattern design based on IPC-7351 guidelines.  
3. All dimensions shown are at maximum material condition (MMC).  
4. Controlling dimension is in millimeters (mm).  
10  
Preliminary Rev. 0.2  
Si595  
DOCUMENT CHANGE LIST:  
Revision 0.1 to Revision 0.2  
Updated Table 5, “CLK± Output Phase Jitter,” on  
page 4.  
Updated typical phase jitter from 0.6 to 0.7 ps for  
kV = 380 ppm/V.  
Preliminary Rev. 0.2  
11  
Si595  
CONTACT INFORMATION  
Silicon Laboratories Inc.  
400 West Cesar Chavez  
Austin, TX 78701  
Tel: 1+(512) 416-8500  
Fax: 1+(512) 416-9669  
Toll Free: 1+(877) 444-3032  
Please visit the Silicon Labs Technical Support web page:  
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx  
and register to submit a technical support request.  
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.  
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from  
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features  
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-  
resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability  
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-  
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to  
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-  
sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap-  
plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.  
Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc.  
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.  
12  
Preliminary Rev. 0.2  

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