C8051F000_03 [SILICON]
Mixed-Signal 32KB ISP FLASH MCU Family; 混合信号32KB ISP功能的Flash MCU系列
| 型号： | C8051F000_03 |
| 厂家： | 
SILICON |
| 描述： | Mixed-Signal 32KB ISP FLASH MCU Family |
| 文件： | 总171页 (文件大小：5235K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Mixed-Signal 32KB ISP FLASH MCU Family
a
HIGH SPEED 8051 µC CORE
-
Pipelined Instruction Architecture; Executes 70% of
Instruction Set in 1 or 2 System Clocks
Up to 25MIPS Throughput with 25MHz Clock
21 Vectored Interrupt Sources
-
SAR ADC
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
12-Bit (C8051F000/1/2, C8051F005/6/7)
-
-
10-bit (C8051F010/1/2, C8051F015/6/7)
±1LSB INL; No Missing Codes
Programmable Throughput up to 100ksps
Up to 8 External Inputs; Programmable as Single-
Ended or Differential
MEMORY
-
-
-
256 Bytes Internal Data RAM (F000/01/02/10/11/12)
2304 Bytes Internal Data RAM (F005/06/07/15/16/17)
32k Bytes FLASH; In-System Programmable in 512 byte
Sectors
ꢀ
ꢀ
ꢀ
Programmable Amplifier Gain: 16, 8, 4, 2, 1, 0.5
Data Dependent Windowed Interrupt Generator
Built-in Temperature Sensor (± 3°C)
DIGITAL PERIPHERALS
-
-
Two 12-bit DACs
-
-
4 Byte-Wide Port I/O; All are 5V tolerant
Hardware SMBusTM (I2CTM Compatible), SPITM, and UART
Serial Ports Available Concurrently
Programmable 16-bit Counter/Timer Array with Five
Capture/Compare Modules
Two Analog Comparators
ꢀ
ꢀ
Programmable Hysteresis Values
Configurable to Generate Interrupts or Reset
-
-
Voltage Reference
ꢀ
ꢀ
2.4V; 15 ppm/°C
-
-
-
Four General Purpose 16-bit Counter/Timers
Dedicated Watch-Dog Timer
Available on External Pin
-
Precision VDD Monitor/Brown-out Detector
Bi-directional Reset
ON-CHIP JTAG DEBUG & BOUNDARY SCAN
CLOCK SOURCES
-
On-Chip Debug Circuitry Facilitates Full Speed, Non-
Intrusive In-System Debug (No Emulator Required!)
Provides Breakpoints, Single Stepping, Watchpoints, Stack
Monitor
-
-
-
Internal Programmable Oscillator: 2-to-16MHz
External Oscillator: Crystal, RC,C, or Clock
Can Switch Between Clock Sources on-the-fly; Useful in
Power Saving Modes
-
-
-
Inspect/Modify Memory and Registers
Superior Performance to Emulation Systems Using ICE-
Chips, Target Pods, and Sockets
SUPPLY VOLTAGE ........................2.7V to 3.6V
-
Typical Operating Current: 12.5mA @ 25MHz
6-4-PMinulTtipQleFPPow, e4r8S-aPviinngTSlQeeFp Pan,d3S2h-uPtdionwLn QMoFdPes
Temperature Range: –40°C to +85°C
-
-
IEEE1149.1 Compliant Boundary Scan
Low Cost Development Kit
ANALOG PERIPHERALS
DIGITAL I/O
PCA
TEMP
SENSOR
SMBus
SPI Bus
UART
SAR
ADC
PGA
VREF
Timer 0
Timer 1
Timer 2
Timer 3
12-Bit
DAC
+
-
+
12-Bit
DAC
-
VOLTAGE
COMPARATORS
HIGH-SPEED CONTROLLER CORE
8051 CPU
(25MIPS)
32KB
CLOCK
CIRCUIT
256/2304 B
SRAM
DEBUG
CIRCUITRY
SANITY
JTAG
21
ISP FLASH
INTERRUPTS CONTROL
Rev. 1.7 11/03
Copyright © 2003 by Silicon Laboratories
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
TABLE OF CONTENTS
1. SYSTEM OVERVIEW........................................................................................................8
Table 1.1. Product Selection Guide...................................................................................................................8
Figure 1.1. C8051F000/05/10/15 Block Diagram.............................................................................................9
Figure 1.2. C8051F001/06/11/16 Block Diagram...........................................................................................10
Figure 1.3. C8051F002/07/12/17 Block Diagram...........................................................................................11
1.1. CIP-51TM CPU.......................................................................................................................................12
Figure 1.4. Comparison of Peak MCU Execution Speeds...............................................................................12
Figure 1.5. On-Board Clock and Reset............................................................................................................13
1.2. On-Board Memory.................................................................................................................................14
Figure 1.6. On-Board Memory Map................................................................................................................14
1.3. JTAG Debug and Boundary Scan..........................................................................................................15
Figure 1.7. Debug Environment Diagram .......................................................................................................15
1.4. Programmable Digital I/O and Crossbar ...............................................................................................16
Figure 1.8. Digital Crossbar Diagram..............................................................................................................16
1.5. Programmable Counter Array................................................................................................................17
Figure 1.9. PCA Block Diagram .....................................................................................................................17
1.6. Serial Ports.............................................................................................................................................17
1.7. Analog to Digital Converter ..................................................................................................................18
Figure 1.10. ADC Diagram .............................................................................................................................18
1.8. Comparators and DACs.........................................................................................................................19
Figure 1.11. Comparator and DAC Diagram...................................................................................................19
2. ABSOLUTE MAXIMUM RATINGS*.............................................................................20
3. GLOBAL DC ELECTRICAL CHARACTERISTICS...................................................20
4. PINOUT AND PACKAGE DEFINITIONS ....................................................................21
Table 4.1. Pin Definitions................................................................................................................................21
Figure 4.1. TQFP-64 Pinout Diagram .............................................................................................................23
Figure 4.2. TQFP-64 Package Drawing ..........................................................................................................24
Figure 4.3. TQFP-48 Pinout Diagram .............................................................................................................25
Figure 4.4. TQFP-48 Package Drawing ..........................................................................................................26
Figure 4.5. LQFP-32 Pinout Diagram .............................................................................................................27
Figure 4.6. LQFP-32 Package Drawing ..........................................................................................................28
5. ADC (12-Bit, C8051F000/1/2/5/6/7 Only).........................................................................29
Figure 5.1. 12-Bit ADC Functional Block Diagram........................................................................................29
5.1. Analog Multiplexer and PGA................................................................................................................29
5.2. ADC Modes of Operation......................................................................................................................30
Figure 5.2. 12-Bit ADC Track and Conversion Example Timing...................................................................30
Figure 5.3. Temperature Sensor Transfer Function.........................................................................................31
Figure 5.4. AMX0CF: AMUX Configuration Register (C8051F00x)............................................................31
Figure 5.5. AMX0SL: AMUX Channel Select Register (C8051F00x)...........................................................32
Figure 5.6. ADC0CF: ADC Configuration Register (C8051F00x).................................................................33
Figure 5.7. ADC0CN: ADC Control Register (C8051F00x) ..........................................................................34
Figure 5.8. ADC0H: ADC Data Word MSB Register (C8051F00x).............................................................35
Figure 5.9. ADC0L: ADC Data Word LSB Register (C8051F00x)...............................................................35
5.3. ADC Programmable Window Detector.................................................................................................36
Figure 5.10. ADC0GTH: ADC Greater-Than Data High Byte Register (C8051F00x) ..................................36
Figure 5.11. ADC0GTL: ADC Greater-Than Data Low Byte Register (C8051F00x) ...................................36
Figure 5.12. ADC0LTH: ADC Less-Than Data High Byte Register (C8051F00x) .......................................36
Figure 5.13. ADC0LTL: ADC Less-Than Data Low Byte Register (C8051F00x).........................................36
Figure 5.14. 12-Bit ADC Window Interrupt Examples, Right Justified Data.................................................37
Figure 5.15. 12-Bit ADC Window Interrupt Examples, Left Justified Data...................................................37
Figure 5.15. 12-Bit ADC Window Interrupt Examples, Left Justified Data...................................................38
Rev. 1.7
2
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Table 5.1. 12-Bit ADC Electrical Characteristics............................................................................................38
Table 5.1. 12-Bit ADC Electrical Characteristics............................................................................................39
6. ADC (10-Bit, C8051F010/1/2/5/6/7 Only).........................................................................40
Figure 6.1. 10-Bit ADC Functional Block Diagram........................................................................................40
6.1. Analog Multiplexer and PGA................................................................................................................40
6.2. ADC Modes of Operation......................................................................................................................41
Figure 6.2. 10-Bit ADC Track and Conversion Example Timing...................................................................41
Figure 6.3. Temperature Sensor Transfer Function.........................................................................................42
Figure 6.4. AMX0CF: AMUX Configuration Register (C8051F01x)............................................................42
Figure 6.5. AMX0SL: AMUX Channel Select Register (C8051F01x)...........................................................43
Figure 6.6. ADC0CF: ADC Configuration Register (C8051F01x).................................................................44
Figure 6.7. ADC0CN: ADC Control Register (C8051F01x) ..........................................................................45
Figure 6.8. ADC0H: ADC Data Word MSB Register (C8051F01x).............................................................46
Figure 6.9. ADC0L: ADC Data Word LSB Register (C8051F01x)...............................................................46
6.3. ADC Programmable Window Detector.................................................................................................47
Figure 6.10. ADC0GTH: ADC Greater-Than Data High Byte Register (C8051F01x) ..................................47
Figure 6.11. ADC0GTL: ADC Greater-Than Data Low Byte Register (C8051F01x) ...................................47
Figure 6.12. ADC0LTH: ADC Less-Than Data High Byte Register (C8051F01x) .......................................47
Figure 6.13. ADC0LTL: ADC Less-Than Data Low Byte Register (C8051F01x).........................................47
Figure 6.14. 10-Bit ADC Window Interrupt Examples, Right Justified Data.................................................48
Figure 6.15. 10-Bit ADC Window Interrupt Examples, Left Justified Data...................................................48
Figure 6.15. 10-Bit ADC Window Interrupt Examples, Left Justified Data...................................................49
Table 6.1. 10-Bit ADC Electrical Characteristics............................................................................................49
Table 6.1. 10-Bit ADC Electrical Characteristics............................................................................................50
7. DACs, 12 BIT VOLTAGE MODE....................................................................................51
Figure 7.1. DAC Functional Block Diagram....................................................................................................51
Figure 7.2. DAC0H: DAC0 High Byte Register .............................................................................................52
Figure 7.3. DAC0L: DAC0 Low Byte Register ..............................................................................................52
Figure 7.4. DAC0CN: DAC0 Control Register...............................................................................................52
Figure 7.5. DAC1H: DAC1 High Byte Register .............................................................................................53
Figure 7.6. DAC1L: DAC1 Low Byte Register ..............................................................................................53
Figure 7.7. DAC1CN: DAC1 Control Register...............................................................................................53
Table 7.1. DAC Electrical Characteristics.......................................................................................................54
8. COMPARATORS ..............................................................................................................55
Figure 8.1. Comparator Functional Block Diagram ........................................................................................55
Figure 8.2. Comparator Hysteresis Plot...........................................................................................................56
Figure 8.3. CPT0CN: Comparator 0 Control Register ....................................................................................57
Figure 8.4. CPT1CN: Comparator 1 Control Register ....................................................................................58
Table 8.1. Comparator Electrical Characteristics ............................................................................................59
9. VOLTAGE REFERENCE ................................................................................................60
Figure 9.1. Voltage Reference Functional Block Diagram .............................................................................60
Figure 9.2. REF0CN: Reference Control Register ..........................................................................................61
Table 9.1. Reference Electrical Characteristics...............................................................................................61
10. CIP-51 CPU.........................................................................................................................62
Figure 10.1. CIP-51 Block Diagram................................................................................................................62
10.1.
INSTRUCTION SET.........................................................................................................................63
Table 10.1. CIP-51 Instruction Set Summary..................................................................................................65
10.2. MEMORY ORGANIZATION..........................................................................................................68
Figure 10.2. Memory Map...............................................................................................................................69
10.3.
SPECIAL FUNCTION REGISTERS................................................................................................70
Table 10.2. Special Function Register Memory Map......................................................................................70
Table 10.3. Special Function Registers ...........................................................................................................70
Figure 10.3. SP: Stack Pointer.........................................................................................................................74
Figure 10.4. DPL: Data Pointer Low Byte ......................................................................................................74
3
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 10.5. DPH: Data Pointer High Byte.....................................................................................................74
Figure 10.6. PSW: Program Status Word........................................................................................................75
Figure 10.7. ACC: Accumulator......................................................................................................................76
Figure 10.8. B: B Register...............................................................................................................................76
10.4.
INTERRUPT HANDLER .................................................................................................................77
Table 10.4. Interrupt Summary........................................................................................................................78
Figure 10.9. IE: Interrupt Enable.....................................................................................................................79
Figure 10.10. IP: Interrupt Priority..................................................................................................................80
Figure 10.11. EIE1: Extended Interrupt Enable 1 ...........................................................................................81
Figure 10.12. EIE2: Extended Interrupt Enable 2 ...........................................................................................82
Figure 10.13. EIP1: Extended Interrupt Priority 1 ..........................................................................................83
Figure 10.14. EIP2: Extended Interrupt Priority 2 ..........................................................................................84
10.5.
Power Management Modes ...............................................................................................................85
Figure 10.15. PCON: Power Control Register ................................................................................................86
11. FLASH MEMORY.............................................................................................................87
11.1.
Programming The Flash Memory......................................................................................................87
Table 11.1. FLASH Memory Electrical Characteristics..................................................................................87
11.2.
11.3.
Non-volatile Data Storage .................................................................................................................88
Security Options ................................................................................................................................88
Figure 11.1. PSCTL: Program Store RW Control...........................................................................................88
Figure 11.2. Flash Program Memory Security Bytes .......................................................................................89
Figure 11.3. FLACL: Flash Access Limit (C8051F005/06/07/15/16/17 only) ...............................................90
Figure 11.4. FLSCL: Flash Memory Timing Prescaler...................................................................................91
12. EXTERNAL RAM (C8051F005/06/07/15/16/17).............................................................92
Figure 12.1. EMI0CN: External Memory Interface Control ...........................................................................92
13. RESET SOURCES.............................................................................................................93
Figure 13.1. Reset Sources Diagram ...............................................................................................................93
13.1.
13.2.
Power-on Reset..................................................................................................................................94
Software Forced Reset.......................................................................................................................94
Figure 13.2. VDD Monitor Timing Diagram ..................................................................................................94
13.3.
13.4.
13.5.
13.6.
13.7.
13.8.
Power-fail Reset.................................................................................................................................94
External Reset....................................................................................................................................95
Missing Clock Detector Reset ...........................................................................................................95
Comparator 0 Reset ...........................................................................................................................95
External CNVSTR Pin Reset.............................................................................................................95
Watchdog Timer Reset ......................................................................................................................95
Figure 13.3. WDTCN: Watchdog Timer Control Register .............................................................................96
Figure 13.4. RSTSRC: Reset Source Register.................................................................................................97
Table 13.1. Reset Electrical Characteristics ....................................................................................................98
14. OSCILLATOR ...................................................................................................................99
Figure 14.1. Oscillator Diagram......................................................................................................................99
Figure 14.2. OSCICN: Internal Oscillator Control Register .........................................................................100
Table 14.1. Internal Oscillator Electrical Characteristics ..............................................................................100
Figure 14.3. OSCXCN: External Oscillator Control Register.......................................................................101
14.1.
14.2.
14.3.
External Crystal Example................................................................................................................102
External RC Example ......................................................................................................................102
External Capacitor Example............................................................................................................102
15. PORT INPUT/OUTPUT..................................................................................................103
15.1.
15.2.
Priority Cross Bar Decoder..............................................................................................................103
Port I/O Initialization.......................................................................................................................103
Figure 15.1. Port I/O Functional Block Diagram ..........................................................................................104
Figure 15.2. Port I/O Cell Block Diagram.....................................................................................................104
Table 15.1. Crossbar Priority Decode ...........................................................................................................105
Figure 15.3. XBR0: Port I/O CrossBar Register 0 ........................................................................................106
Rev. 1.7
4
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 15.4. XBR1: Port I/O CrossBar Register 1 ........................................................................................107
Figure 15.5. XBR2: Port I/O CrossBar Register 2 ........................................................................................108
15.3.
15.4.
General Purpose Port I/O.................................................................................................................109
Configuring Ports Which are not Pinned Out..................................................................................109
Figure 15.6. P0: Port0 Register .....................................................................................................................109
Figure 15.7. PRT0CF: Port0 Configuration Register ....................................................................................109
Figure 15.8. P1: Port1 Register .....................................................................................................................110
Figure 15.9. PRT1CF: Port1 Configuration Register ....................................................................................110
Figure 15.10. PRT1IF: Port1 Interrupt Flag Register....................................................................................110
Figure 15.11. P2: Port2 Register ...................................................................................................................111
Figure 15.12. PRT2CF: Port2 Configuration Register ..................................................................................111
Figure 15.13. P3: Port3 Register ...................................................................................................................112
Figure 15.14. PRT3CF: Port3 Configuration Register ..................................................................................112
Table 15.2. Port I/O DC Electrical Characteristics........................................................................................112
16. SMBus / I2C Bus...............................................................................................................113
Figure 16.1. SMBus Block Diagram .............................................................................................................113
Figure 16.2. Typical SMBus Configuration ..................................................................................................114
16.1.
16.2.
Supporting Documents ....................................................................................................................114
Operation .........................................................................................................................................115
Figure 16.3. SMBus Transaction...................................................................................................................115
16.3.
16.4.
16.5.
16.6.
Arbitration .......................................................................................................................................116
Clock Low Extension ......................................................................................................................116
Timeouts ..........................................................................................................................................116
SMBus Special Function Registers..................................................................................................116
Figure 16.4. SMB0CN: SMBus Control Register ..........................................................................................118
Figure 16.5. SMB0CR: SMBus Clock Rate Register....................................................................................119
Figure 16.6. SMB0DAT: SMBus Data Register ...........................................................................................120
Figure 16.7. SMB0ADR: SMBus Address Register .....................................................................................120
Figure 16.8. SMB0STA: SMBus Status Register..........................................................................................121
Table 16.1. SMBus Status Codes ..................................................................................................................122
17. SERIAL PERIPHERAL INTERFACE BUS.................................................................123
Figure 17.1. SPI Block Diagram ...................................................................................................................123
Figure 17.2. Typical SPI Interconnection......................................................................................................124
17.1.
17.2.
Signal Descriptions..........................................................................................................................124
Operation .........................................................................................................................................125
Figure 17.3. Full Duplex Operation...............................................................................................................125
17.3.
Serial Clock Timing.........................................................................................................................126
Figure 17.4. Data/Clock Timing Diagram.....................................................................................................126
17.4.
SPI Special Function Registers........................................................................................................127
Figure 17.5. SPI0CFG: SPI Configuration Register......................................................................................127
Figure 17.6. SPI0CN: SPI Control Register..................................................................................................128
Figure 17.7. SPI0CKR: SPI Clock Rate Register..........................................................................................129
Figure 17.8. SPI0DAT: SPI Data Register....................................................................................................129
18. UART.................................................................................................................................130
Figure 18.1. UART Block Diagram ..............................................................................................................130
18.1.
UART Operational Modes...............................................................................................................131
Table 18.1. UART Modes .............................................................................................................................131
Figure 18.2. UART Mode 0 Interconnect......................................................................................................131
Figure 18.3. UART Mode 0 Timing Diagram...............................................................................................131
Figure 18.4. UART Mode 1 Timing Diagram...............................................................................................132
Figure 18.5. UART Modes 1, 2, and 3 Interconnect Diagram ......................................................................133
Figure 18.6. UART Modes 2 and 3 Timing Diagram....................................................................................134
18.2.
Multiprocessor Communications.....................................................................................................135
Figure 18.7. UART Multi-Processor Mode Interconnect Diagram...............................................................135
5
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Table 18.2. Oscillator Frequencies for Standard Baud Rates........................................................................136
Figure 18.8. SBUF: Serial (UART) Data Buffer Register.............................................................................136
Figure 18.9. SCON: Serial Port Control Register..........................................................................................137
19. TIMERS ............................................................................................................................138
19.1.
Timer 0 and Timer 1........................................................................................................................138
Figure 19.1. T0 Mode 0 Block Diagram........................................................................................................139
Figure 19.2. T0 Mode 2 Block Diagram........................................................................................................140
Figure 19.3. T0 Mode 3 Block Diagram........................................................................................................141
Figure 19.4. TCON: Timer Control Register.................................................................................................142
Figure 19.5. TMOD: Timer Mode Register...................................................................................................143
Figure 19.6. CKCON: Clock Control Register..............................................................................................144
Figure 19.7. TL0: Timer 0 Low Byte ............................................................................................................145
Figure 19.8. TL1: Timer 1 Low Byte ............................................................................................................145
Figure 19.9. TH0: Timer 0 High Byte...........................................................................................................145
Figure 19.10. TH1: Timer 1 High Byte.........................................................................................................145
19.2.
Timer 2 ............................................................................................................................................146
Figure 19.11. T2 Mode 0 Block Diagram......................................................................................................147
Figure 19.12. T2 Mode 1 Block Diagram......................................................................................................148
Figure 19.13. T2 Mode 2 Block Diagram......................................................................................................149
Figure 19.14. T2CON: Timer 2 Control Register..........................................................................................150
Figure 19.15. RCAP2L: Timer 2 Capture Register Low Byte ......................................................................151
Figure 19.16. RCAP2H: Timer 2 Capture Register High Byte .....................................................................151
Figure 19.17. TL2: Timer 2 Low Byte ..........................................................................................................151
Figure 19.18. TH2: Timer 2 High Byte.........................................................................................................151
19.3.
Timer 3 ............................................................................................................................................152
Figure 19.19. Timer 3 Block Diagram...........................................................................................................152
Figure 19.20. TMR3CN: Timer 3 Control Register ......................................................................................152
Figure 19.21. TMR3RLL: Timer 3 Reload Register Low Byte ....................................................................153
Figure 19.22. TMR3RLH: Timer 3 Reload Register High Byte ...................................................................153
Figure 19.23. TMR3L: Timer 3 Low Byte....................................................................................................153
Figure 19.24. TMR3H: Timer 3 High Byte...................................................................................................153
20. PROGRAMMABLE COUNTER ARRAY....................................................................154
Figure 20.1. PCA Block Diagram .................................................................................................................154
20.1.
Capture/Compare Modules..............................................................................................................155
Table 20.1. PCA0CPM Register Settings for PCA Capture/Compare Modules ...........................................155
Figure 20.2. PCA Interrupt Block Diagram...................................................................................................155
Figure 20.3. PCA Capture Mode Diagram....................................................................................................156
Figure 20.4. PCA Software Timer Mode Diagram........................................................................................157
Figure 20.5. PCA High Speed Output Mode Diagram..................................................................................157
Figure 20.6. PCA PWM Mode Diagram .......................................................................................................158
20.2.
PCA Counter/Timer.........................................................................................................................159
Table 20.2. PCA Timebase Input Options.....................................................................................................159
Figure 20.7. PCA Counter/Timer Block Diagram.........................................................................................159
20.3.
Register Descriptions for PCA ........................................................................................................160
Figure 20.8. PCA0CN: PCA Control Register ...............................................................................................160
Figure 20.9. PCA0MD: PCA Mode Register ................................................................................................161
Figure 20.10. PCA0CPMn: PCA Capture/Compare Registers......................................................................162
Figure 20.11. PCA0L: PCA Counter/Timer Low Byte .................................................................................163
Figure 20.12. PCA0H: PCA Counter/Timer High Byte................................................................................163
Figure 20.13. PCA0CPLn: PCA Capture Module Low Byte........................................................................163
Figure 20.14. PCA0CPHn: PCA Capture Module High Byte.......................................................................163
21. JTAG (IEEE 1149.1) ........................................................................................................164
Figure 21.1. IR: JTAG Instruction Register ..................................................................................................164
21.1.
Boundary Scan.................................................................................................................................165
Rev. 1.7
6
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Table 21.1. Boundary Data Register Bit Definitions.....................................................................................165
Figure 21.2. DEVICEID: JTAG Device ID Register ....................................................................................166
21.2.
Flash Programming Commands.......................................................................................................167
Figure 21.3. FLASHCON: JTAG Flash Control Register.............................................................................168
Figure 21.4. FLASHADR: JTAG Flash Address Register............................................................................168
Figure 21.5. FLASHDAT: JTAG Flash Data Register..................................................................................169
Figure 21.6. FLASHSCL: JTAG Flash Scale Register .................................................................................169
21.3.
Debug Support.................................................................................................................................170
7
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
1. SYSTEM OVERVIEW
The C8051F000 family are fully integrated mixed-signal System on a Chip MCUs with a true 12-bit multi-channel
ADC (F000/01/02/05/06/07), or a true 10-bit multi-channel ADC (F010/11/12/15/16/17). See the Product Selection
Guide in Table 1.1 for a quick reference of each MCUs’ feature set. Each has a programmable gain pre-amplifier,
two 12-bit DACs, two voltage comparators (except for the F002/07/12/17, which have one), a voltage reference,
and an 8051-compatible microcontroller core with 32kbytes of FLASH memory. There are also I2C/SMBus,
UART, and SPI serial interfaces implemented in hardware (not “bit-banged” in user software) as well as a
Programmable Counter/Timer Array (PCA) with five capture/compare modules. There are also 4 general-purpose
16-bit timers and 4 byte-wide general-purpose digital Port I/O. The C8051F000/01/02/10/11/12 have 256 bytes of
RAM and execute up to 20MIPS, while the C8051F005/06/07/15/16/17 have 2304 bytes of RAM and execute up to
25MIPS.
With an on-board VDD monitor, WDT, and clock oscillator, the MCUs are truly stand-alone System-on-a-Chip
solutions. Each MCU effectively configures and manages the analog and digital peripherals. The FLASH memory
can be reprogrammed even in-circuit, providing non-volatile data storage, and also allowing field upgrades of the
8051 firmware. Each MCU can also individually shut down any or all of the peripherals to conserve power.
On-board JTAG debug support allows non-intrusive (uses no on-chip resources), full speed, in-circuit debug using
the production MCU installed in the final application. This debug system supports inspection and modification of
memory and registers, setting breakpoints, watchpoints, single stepping, and run and halt commands. All analog
and digital peripherals are fully functional when using JTAG debug.
Each MCU is specified for 2.7V-to-3.6V operation over the industrial temperature range (-45C to +85C). The Port
I/Os, /RST, and JTAG pins are tolerant for input signals up to 5V. The C8051F000/05/10/15 are available in the
64-pin TQFP (see block diagram in Figure 1.1). The C8051F001/06/11/16 are available in the 48-pin TQFP (see
block diagram in Figure 1.2). The C8051F002/07/12/17 are available in the 32-pin LQFP (see block diagram in
Figure 1.3).
Table 1.1. Product Selection Guide
C8051F000
C8051F001
C8051F002
C8051F005
C8051F006
C8051F007
C8051F010
C8051F011
C8051F012
C8051F015
C8051F016
C8051F017
20
20
20
25
25
25
20
20
20
25
25
25
32k
32k
32k
32k
32k
32k
32k
32k
32k
32k
32k
32k
256
256
256
2304
2304
2304
256
256
256
2304
2304
2304
4
4
4
4
4
4
4
4
4
4
4
4
32
16
8
32
16
8
32
16
8
32
16
8
12
12
12
12
12
12
10
10
10
10
10
10
100
100
100
100
100
100
100
100
100
100
100
100
8
8
4
8
8
4
8
8
4
8
8
4
12
12
12
12
12
12
12
12
12
12
12
12
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
2
2
1
2
2
1
2
2
1
64TQFP
48TQFP
32LQFP
64TQFP
48TQFP
32LQFP
64TQFP
48TQFP
32LQFP
64TQFP
48TQFP
32LQFP
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
Rev. 1.7
8
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 1.1. C8051F000/05/10/15 Block Diagram
VDD
VDD
VDD
DGND
DGND
DGND
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P
0
Digital Power
Analog Power
C
R
O
S
S
B
A
R
UART
SMBus
SPI Bus
PCA
D
r
AV+
AV+
AGND
v
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
AGND
P
1
Timers
0,1,2
32kbyte
FLASH
TCK
TMS
TDI
TDO
D
r
Boundary Scan
Debug HW
8
0
5
1
JTAG
Logic
Timer 3
v
256 byte
RAM
S
W
I
Port 0
Latch
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
Reset
P
2
/RST
2048 byte
XRAM
Port 1
Latch
VDD
T
C
H
WDT
D
r
(F005/15 only)
Monitor
Port 2
Latch
C
o
r
v
External
Oscillator
Circuit
XTAL1
XTAL2
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P
3
System Clock
SFR Bus
Port 3
Latch
e
Internal
D
r
Oscillator
v
VREF
DAC0
VREF
DAC0
(12-Bit)
DAC1
DAC1
(12-Bit)
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
A
M
U
X
ADC
100ksps
Prog
Gain
TEMP
CP0+
CP0-
CP0
CP1
CP1+
CP1-
9
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 1.2. C8051F001/06/11/16 Block Diagram
VDD
VDD
DGND
DGND
DGND
DGND
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P
0
Digital Power
Analog Power
C
R
O
S
S
B
A
R
UART
SMBus
SPI Bus
PCA
D
r
AV+
AV+
AGND
v
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
AGND
P
1
Timers
0,1,2
32kbyte
FLASH
TCK
TMS
TDI
TDO
D
r
Boundary Scan
Debug HW
8
0
5
1
JTAG
Logic
Timer 3
256 byte
RAM
v
S
W
I
Port 0
Latch
Reset
P
2
/RST
2048 byte
XRAM
Port 1
Latch
T
C
H
VDD
WDT
(F006/16 only)
D
r
Monitor
Port 2
Latch
C
o
r
v
External
Oscillator
Circuit
XTAL1
XTAL2
P
3
SFR Bus
System Clock
Port 3
Latch
e
Internal
D
r
Oscillator
v
VREF
DAC0
VREF
DAC0
(12-Bit)
DAC1
DAC1
(12-Bit)
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
A
ADC
100ksps
Prog
M
Gain
U
X
TEMP
CP0
CP0+
CP0-
CP1+
CP1-
CP1
Rev. 1.7
10
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 1.3. C8051F002/07/12/17 Block Diagram
VDD
VDD
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P
0
Digital Power
C
R
O
S
S
B
A
R
DGND
DGND
UART
SMBus
SPI Bus
PCA
D
r
AV+
AV+
AGND
v
Analog Power
AGND
P
1
Timers
0,1,2
32kbyte
FLASH
TCK
TMS
TDI
TDO
D
r
Boundary Scan
Debug HW
8
0
5
1
JTAG
Logic
Timer 3
256 byte
RAM
v
S
W
I
Port 0
Latch
P
2
Reset
/RST
2048 byte
XRAM
Port 1
Latch
T
C
H
(F007/17 only)
VDD
WDT
D
r
Monitor
Port 2
Latch
C
o
r
v
External
Oscillator
Circuit
XTAL1
XTAL2
P
3
SFR Bus
System Clock
Port 3
Latch
e
Internal
D
r
Oscillator
v
VREF
DAC0
VREF
DAC0
(12-Bit)
DAC1
DAC1
(12-Bit)
AIN0
AIN1
AIN2
AIN3
A
M
U
X
ADC
100ksps
Prog
Gain
TEMP
CP0+
CP0-
CP0
CP1
11
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
1.1.
CIP-51TM CPU
1.1.1. Fully 8051 Compatible
The C8051F000 family utilizes Silicon Laboratories’ proprietary CIP-51 microcontroller core. The CIP-51 is fully
compatible with the MCS-51TM instruction set. Standard 803x/805x assemblers and compilers can be used to
develop software. The core has all the peripherals included with a standard 8052, including four 16-bit
counter/timers, a full-duplex UART, 256 bytes of internal RAM space, 128 byte Special Function Register (SFR)
address space, and four byte-wide I/O Ports.
1.1.2. Improved Throughput
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051
architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to
execute with a maximum system clock of 12-to-24MHz. By contrast, the CIP-51 core executes 70% of its
instructions in one or two system clock cycles, with only four instructions taking more than four system clock
cycles.
The CIP-51 has a total of 109 instructions. The number of instructions versus the system clock cycles to execute
them is as follows:
26
1
50
2
5
2/3
14
3
7
3/4
3
4
1
4/5
2
5
1
8
Instructions
Clocks to Execute
With the CIP-51’s maximum system clock at 25MHz, it has a peak throughput of 25MIPS. Figure 1.4 shows a
comparison of peak throughputs of various 8-bit microcontroller cores with their maximum system clocks.
Figure 1.4. Comparison of Peak MCU Execution Speeds
25
20
15
10
5
Silicon Labs Microchip
Philips
80C51
ADuC812
8051
CIP-51
PIC17C75x
(25MHz clk) (33MHz clk) (33MHz clk) (16MHz clk)
Rev. 1.7
12
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
1.1.3.
Additional Features
The C8051F000 MCU family has several key enhancements both inside and outside the CIP-51 core to improve its
overall performance and ease of use in the end applications.
The extended interrupt handler provides 21 interrupt sources into the CIP-51 (as opposed to 7 for the standard
8051), allowing the numerous analog and digital peripherals to interrupt the controller. An interrupt driven system
requires less intervention by the MCU, giving it more effective throughput. The extra interrupt sources are very
useful when building multi-tasking, real-time systems.
There are up to seven reset sources for the MCU: an on-board VDD monitor, a Watchdog Timer, a missing clock
detector, a voltage level detection from Comparator 0, a forced software reset, the CNVSTR pin, and the /RST pin.
The /RST pin is bi-directional, accommodating an external reset, or allowing the internally generated POR to be
output on the /RST pin. Each reset source except for the VDD monitor and Reset Input Pin may be disabled by the
user in software. The WDT may be permanently enabled in software after a power-on reset during MCU
initialization.
The MCU has an internal, stand alone clock generator which is used by default as the system clock after any reset.
If desired, the clock source may be switched on the fly to the external oscillator, which can use a crystal, ceramic
resonator, capacitor, RC, or external clock source to generate the system clock. This can be extremely useful in low
power applications, allowing the MCU to run from a slow (power saving) external crystal source, while periodically
switching to the fast (up to 16MHz) internal oscillator as needed.
Figure 1.5. On-Board Clock and Reset
VDD
CNVSTR
(Port
I/O)
Crossbar
Supply
Monitor
(CNVSTR
reset
Supply
Reset
+
enable)
/RST
-
(wired-OR)
Timeout
Comparator 0
CP0+
CP0-
+
-
(CP0
reset
enable)
Reset
Funnel
Missing
Clock
Detector
(one-
shot)
WDT
EN
PRE
EN
Internal
Clock
Generator
System
Clock
Software Reset
System Reset
CIP-51
XTAL1
XTAL2
OSC
Microcontroller
Core
Clock Select
Extended Interrupt
Handler
13
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
1.2.
On-Board Memory
The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data RAM, with
the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general purpose RAM, and
direct addressing accesses the 128 byte SFR address space. The lower 128 bytes of RAM are accessible via direct
and indirect addressing. The first 32 bytes are addressable as four banks of general-purpose registers, and the next
16 bytes can be byte addressable or bit addressable.
The CIP-51 in the C8051F005/06/07/15/16/17 MCUs additionally has a 2048 byte RAM block in the external data
memory address space. This 2048 byte block can be addressed over the entire 64k external data memory address
range (see Figure 1.6).
The MCU’s program memory consists of 32k + 128 bytes of FLASH. This memory may be reprogrammed in-
system in 512 byte sectors, and requires no special off-chip programming voltage. The 512 bytes from addresses
0x7E00 to 0x7FFF are reserved for factory use. There is also a single 128-byte sector at address 0x8000 to 0x807F,
which may be useful as a small table for software constants or as additional program space. See Figure 1.6 for the
MCU system memory map.
Figure 1.6. On-Board Memory Map
PROGRAM MEMORY
DATA MEMORY
INTERNAL DATA ADDRESS SPACE
0x807F
0x8000
0x7FFF
0x7E00
0x7DFF
128 Byte ISP FLASH
0xFF
Upper 128 RAM
(Indirect Addressing
Only)
Special Function
Register's
RESERVED
(Direct Addressing Only)
0x80
0x7F
(Direct and Indirect
Addressing)
Lower 128 RAM
(Direct and Indirect
Addressing)
FLASH
0x30
0x2F
Bit Addressable
(In-System
Programmable in 512
Byte Sectors)
0x20
0x1F
General Purpose
Registers
0x00
0x0000
EXTERNAL DATA ADDRESS SPACE
0xFFFF
0xF800
(same 2048 byte RAM block )
The same 2048 byte RAM
0x17FF
0x1000
0x0FFF
0x0800
0x07FF
(same 2048 byte RAM block )
(same 2048 byte RAM block )
block can be addressed on
2k boundaries throughout
the 64k External Data
Memory space.
RAM - 2048 Bytes
(accessable using MOVX
instruction)
0x0000
Rev. 1.7
14
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
1.3.
JTAG Debug and Boundary Scan
The C8051F000 family has on-chip JTAG and debug circuitry that provide non-intrusive, full speed, in-circuit
debug using the production part installed in the end application using the four-pin JTAG I/F. The JTAG port is
fully compliant to IEEE 1149.1, providing full boundary scan for test and manufacturing purposes.
Silicon Labs’ debug system supports inspection and modification of memory and registers, breakpoints,
watchpoints, a stack monitor, and single stepping. No additional target RAM, program memory, timers, or
communications channels are required. All the digital and analog peripherals are functional and work correctly
while debugging. All the peripherals (except for the ADC) are stalled when the MCU is halted, during single
stepping, or at a breakpoint in order to keep them in sync.
The C8051F000DK, C8051F005DK, C8051F010DK, and C8051F015DK are development kits with all the
hardware and software necessary to develop application code and perform in-circuit debug with the C8051F000/1/2,
F005/6/7, F010/1/2, and F015/6/7 MCUs respectively. The kit includes software with a developer’s studio and
debugger, an integrated 8051 assembler, and an RS-232 to JTAG protocol translator module referred to as the EC.
It also has a target application board with the associated MCU installed and a large prototyping area, plus the RS-
232 and JTAG cables, and wall-mount power supply.
The Development Kit requires a Windows
95/98/NT/2000/XP computer with one available RS-232 serial port. As shown in Figure 1.7, the PC is connected
via RS-232 to the EC. A six-inch ribbon cable connects the EC to the user’s application board, picking up the four
JTAG pins and VDD and GND. The EC takes its power from the application board. It requires roughly 20mA at
2.7-3.6V. For applications where there is not sufficient power available from the target board, the provided power
supply can be connected directly to the EC.
This is a vastly superior configuration for developing and debugging embedded applications compared to standard
MCU Emulators, which use on-board “ICE Chips” and target cables and require the MCU in the application board
to be socketed. Silicon Labs’ debug environment both increases ease of use and preserves the performance of the
precision analog peripherals.
Figure 1.7. Debug Environment Diagram
Silicon Labs Integrated
Development Environment
WINDOWS 95/98/NT/2000/XP
RS-232
EC
JTAG (x4), VDD, GND
TARGET PCB
VDD GND
C8051
F005
15
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
1.4.
Programmable Digital I/O and Crossbar
The standard 8051 Ports (0, 1, 2, and 3) are available on the MCUs. All four ports are pinned out on the
F000/05/10/15. Ports 0 and 1 are pinned out on the F001/06/11/16, and only Port 0 is pinned out on the
F002/07/12/17. The Ports not pinned out are still available for software use as general purpose registers. The Port
I/O behave like the standard 8051 with a few enhancements.
Each Port I/O pin can be configured as either a push-pull or open-drain output. Also, the “weak pull-ups” which are
normally fixed on an 8051 can be globally disabled, providing additional power saving capabilities for low power
applications.
Perhaps the most unique enhancement is the Digital Crossbar. This is essentially a large digital switching network
that allows mapping of internal digital system resources to Port I/O pins on P0, P1, and P2. (See Figure 1.8.)
Unlike microcontrollers with standard multiplexed digital I/O, all combinations of functions are supported.
The on-board counter/timers, serial buses, HW interrupts, ADC Start of Conversion input, comparator outputs, and
other digital signals in the controller can be configured to appear on the Port I/O pins specified in the Crossbar
Control registers. This allows the user to select the exact mix of general purpose Port I/O and digital resources
needed for his particular application.
Figure 1.8. Digital Crossbar Diagram
2
XBR0, XBR1,
PRT0CF, PRT1CF,
PRT2CF Registers
Highest
Priority
SMBus
SPI
XBR2 Registers
4
2
6
External
Pins
UART
PCA
Priority
Decoder
P0.0
Highest
Priority
P0
I/O
8
8
8
2
6
Comptr.
Outputs
Cells
P0.7
Digital
Crossbar
T0, T1,
T2
P1.0
P1.7
P1
I/O
Lowest
Priority
SYSCLK
CNVSTR
Cells
8
P2.0
P2.7
P2
I/O
Lowest
Priority
P0
Cells
(P0.0-P0.7)
8
P1
P2
P3
(P1.0-P1.7)
8
PRT3CF
Register
Port
Latches
(P2.0-P2.7)
8
P3.0
P3.7
P3
I/O
Cells
(P3.0-P3.7)
Rev. 1.7
16
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
1.5.
Programmable Counter Array
The C8051F000 MCU family has an on-board Programmable Counter/Timer Array (PCA) in addition to the four
16-bit general-purpose counter/timers. The PCA consists of a dedicated 16-bit counter/timer timebase with 5
programmable capture/compare modules. The timebase gets its clock from one of four sources: the system clock
divided by 12, the system clock divided by 4, Timer 0 overflow, or an External Clock Input (ECI).
Each capture/compare module can be configured to operate in one of four modes: Edge-Triggered Capture,
Software Timer, High Speed Output, or Pulse Width Modulator. The PCA Capture/Compare Module I/O and
External Clock Input are routed to the MCU Port I/O via the Digital Crossbar.
Figure 1.9. PCA Block Diagram
/4
System
Clock
/12
16-Bit Counter/Timer
T0 Overflow
Capture/Compare
Module 0
Capture/Compare
Module 1
Capture/Compare
Module 2
Capture/Compare
Module 3
Capture/Compare
Module 4
Crossbar
Port I/O
1.6.
Serial Ports
The C8051F000 MCU Family includes a Full-Duplex UART, SPI Bus, and I2C/SMBus. Each of the serial buses is
fully implemented in hardware and makes extensive use of the CIP-51’s interrupts, thus requiring very little
intervention by the CPU. The serial buses do not “share” resources such as timers, interrupts, or Port I/O, so any or
all of the serial buses may be used together.
17
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
1.7.
Analog to Digital Converter
The C8051F000/1/2/5/6/7 has an on-chip 12-bit SAR ADC with a 9-channel input multiplexer and programmable
gain amplifier. With a maximum throughput of 100ksps, the ADC offers true 12-bit accuracy with an INL of
±1LSB. The ADC in the C8051F010/1/2/5/6/7 is similar, but with 10-bit resolution. Each ADC has a maximum
throughput of 100ksps. Each ADC has an INL of ±1LSB, offering true 12-bit accuracy with the C8051F00x, and
true 10-bit accuracy with the C8051F01x. There is also an on-board 15ppm voltage reference, or an external
reference may be used via the VREF pin.
The ADC is under full control of the CIP-51 microcontroller via the Special Function Registers. One input channel
is tied to an internal temperature sensor, while the other eight channels are available externally. Each pair of the
eight external input channels can be configured as either two single-ended inputs or a single differential input. The
system controller can also put the ADC into shutdown to save power.
A programmable gain amplifier follows the analog multiplexer. The gain can be set in software from 0.5 to 16 in
powers of 2. The gain stage can be especially useful when different ADC input channels have widely varied input
voltage signals, or when it is necessary to “zoom in” on a signal with a large DC offset (in differential mode, a DAC
could be used to provide the DC offset).
Conversions can be started in four ways; a software command, an overflow on Timer 2, an overflow on Timer 3, or
an external signal input. This flexibility allows the start of conversion to be triggered by software events, external
HW signals, or convert continuously. A completed conversion causes an interrupt, or a status bit can be polled in
software to determine the end of conversion. The resulting 10 or 12-bit data word is latched into two SFRs upon
completion of a conversion. The data can be right or left justified in these registers under software control.
Compare registers for the ADC data can be configured to interrupt the controller when ADC data is within a
specified window. The ADC can monitor a key voltage continuously in background mode, but not interrupt the
controller unless the converted data is within the specified window.
Figure 1.10. ADC Diagram
VREF
+
AIN0
REF
-
AIN1
AIN2
AIN3
AIN4
Programmable
Gain Amp
+
-
9-to-1
AMUX
(SE or
DIFF)
100ksps
SAR
+
+
X
-
AIN5
AIN6
AIN7
-
+
ADC
-
(not bonded out on
F002, F007, F012,
and F017
TEMP
SENSOR
Control & Data
SFR's
SFR Bus
Rev. 1.7
18
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
1.8.
Comparators and DACs
The C8051F000 MCU Family has two 12-bit DACs and two comparators on chip (the second comparator, CP1, is
not bonded out on the F002, F007, F012, and F017). The MCU data and control interface to each comparator and
DAC is via the Special Function Registers. The MCU can place any DAC or comparator in low power shutdown
mode.
The comparators have software programmable hysteresis. Each comparator can generate an interrupt on its rising
edge, falling edge, or both. The comparators’ output state can also be polled in software. These interrupts are
capable of waking up the MCU from idle mode. The comparator outputs can be programmed to appear on the Port
I/O pins via the Crossbar.
The DACs are voltage output mode and use the same voltage reference as the ADC. They are especially useful as
references for the comparators or offsets for the differential inputs of the ADC.
Figure 1.11. Comparator and DAC Diagram
CP0
(Port I/O)
CROSSBAR
CP1
(Port I/O)
CP0+
+
CP0
-
CP0-
(not bonded out on
F002, F007, F012, and
F017)
CP0
CP1
CP1+
+
CP1
SFR's
-
CP1-
CIP-51
and
(Data
and
Interrupt
Handler
Cntrl)
REF
DAC0
DAC1
DAC0
REF
DAC1
19
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
2. ABSOLUTE MAXIMUM RATINGS*
Ambient temperature under bias................................................................................................................. -55 to 125°C
Storage Temperature .................................................................................................................................. -65 to 150°C
Voltage on any Pin (except VDD and Port I/O) with respect to DGND................................... -0.3V to (VDD + 0.3V)
Voltage on any Port I/O Pin or /RST with respect to DGND....................................................................-0.3V to 5.8V
Voltage on VDD with respect to DGND...................................................................................................-0.3V to 4.2V
Maximum Total current through VDD, AV+, DGND and AGND.....................................................................800mA
Maximum output current sunk by any Port pin...................................................................................................100mA
Maximum output current sunk by any other I/O pin .............................................................................................25mA
Maximum output current sourced by any Port pin ..............................................................................................100mA
Maximum output current sourced by any other I/O pin ........................................................................................25mA
*Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the devices at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
3. GLOBAL DC ELECTRICAL CHARACTERISTICS
-40°C to +85°C unless otherwise specified.
PARAMETER
Analog Supply Voltage
Analog Supply Current
CONDITIONS
MIN
TYP
3.0
1
MAX
3.6
UNITS
V
(Note 1)
2.7
Internal REF, ADC, DAC, Comparators
all active
2
mA
Analog Supply Current with
analog sub-systems inactive
Analog-to-Digital Supply
Delta ( | VDD – AV+ | )
Digital Supply Voltage
Digital Supply Current with
CPU active
Internal REF, ADC, DAC, Comparators
all disabled, oscillator disabled
5
20
0.5
3.6
µA
V
2.7
3.0
12.5
0.5
10
V
VDD = 2.7V, Clock=25MHz
VDD = 2.7V, Clock=1MHz
VDD = 2.7V, Clock=32kHz
Oscillator not running
mA
mA
µA
µA
Digital Supply Current
(shutdown)
Digital Supply RAM Data
Retention Voltage
5
1.5
V
Specified Operating
Temperature Range
SYSCLK (System Clock
Frequency)
-40
0
+85
25
°C
C8051F005/6/7, C8051F015/6/7
(Note 2)
C8051F000/1/2, C8051F010/1/2
(Note 2)
MHz
MHz
SYSCLK (System Clock
Frequency)
0
20
Tsysl (SYSCLK Low Time)
Tsysh (SYSCLK High Time)
18
18
ns
ns
Note 1: Analog Supply AV+ must be greater than 1V for VDD monitor to operate.
Note 2: SYSCLK must be at least 32 kHz to enable debugging.
Rev. 1.7
20
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
4. PINOUT AND PACKAGE DEFINITIONS
Table 4.1. Pin Definitions
Pin Numbers
F000
F005
F010
F015
F001
F006
F011
F016
F002
F007
F012
F017
Name
VDD
Type
Description
Digital Voltage Supply.
31, 23, 18,
40,
62
32
20
DGND
Digital Ground.
30, 22, 17,
41, 33,
21
61
27,
19
AV+
Positive Analog Voltage Supply.
Analog Ground.
16, 13,
9,
29
8,
17
5,
43
44,
12
18
17
20
AGND
15
22
21
28
30
14
13
15
TCK
TMS
TDI
D In
D In
D In
JTAG Test Clock with internal pull-up.
JTAG Test-Mode Select with internal pull-up.
JTAG Test Data Input with internal pull-up. TDI is latched on a rising edge of
TCK.
TDO
D Out
A In
JTAG Test Data Output with internal pull-up. Data is shifted out on TDO on
the falling edge of TCK. TDO output is a tri-state driver.
Crystal Input. This pin is the return for the internal oscillator circuit for a
crystal or ceramic resonator. For a precision internal clock, connect a crystal
or ceramic resonator from XTAL1 to XTAL2. If overdriven by an external
CMOS clock, this becomes the system clock.
29
18
21
14
16
10
XTAL1
XTAL2
/RST
A Out
D I/O
Crystal Output. This pin is the excitation driver for a crystal or ceramic
resonator.
19
20
15
16
11
12
Chip Reset. Open-drain output of internal Voltage Supply monitor. Is driven
low when VDD is < 2.7V. An external source can force a system reset by
driving this pin low.
VREF
A I/O
Voltage Reference. When configured as an input, this pin is the voltage
reference for the MCU. Otherwise, the internal reference drives this pin.
Comparator 0 Non-Inverting Input.
6
3
3
CP0+
CP0-
CP1+
CP1-
DAC0
A In
A In
A In
A In
A Out
4
3
2
1
45
46
48
2
1
Comparator 0 Inverting Input.
Comparator 1 Non-Inverting Input.
Comparator 1 Inverting Input.
2
1
Digital to Analog Converter Output 0. The DAC0 voltage output. (See
Section 7 DAC Specification for complete description).
Digital to Analog Converter Output 1. The DAC1 voltage output. (See
Section 7 DAC Specification for complete description).
Analog Mux Channel Input 0. (See ADC Specification for complete
description).
64
32
31
4
DAC1
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
A Out
A In
A In
A In
A In
A In
A In
63
7
47
4
Analog Mux Channel Input 1. (See ADC Specification for complete
description).
8
5
5
Analog Mux Channel Input 2. (See ADC Specification for complete
description).
9
6
6
Analog Mux Channel Input 3. (See ADC Specification for complete
description).
10
11
12
7
7
Analog Mux Channel Input 4. (See ADC Specification for complete
description).
8
Analog Mux Channel Input 5. (See ADC Specification for complete
description).
9
21
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Pin Numbers
F000
F001
F006
F011
F016
F002
Name
Type
Description
F005
F010
F015
F007
F012
F017
AIN6
AIN7
A In
A In
Analog Mux Channel Input 6. (See ADC Specification for complete
description).
13
10
Analog Mux Channel Input 7. (See ADC Specification for complete
description).
14
11
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
D I/O
D I/O
D I/O
D I/O
D I/O
D I/O
D I/O
D I/O
D I/O
D I/O
D I/O
D I/O
D I/O
D I/O
D I/O
D I/O
D I/O
D I/O
D I/O
D I/O
D I/O
D I/O
D I/O
D I/O
D I/O
D I/O
D I/O
D I/O
D I/O
D I/O
D I/O
D I/O
Port0 Bit0. (See the Port I/O Sub-System section for complete description).
39
42
47
48
49
50
55
56
38
37
36
35
34
32
60
59
33
27
54
53
52
51
44
43
26
25
24
23
58
57
46
45
31
34
35
36
37
38
39
40
30
29
28
26
25
24
42
41
19
22
23
24
25
26
27
28
Port0 Bit1. (See the Port I/O Sub-System section for complete description).
Port0 Bit2. (See the Port I/O Sub-System section for complete description).
Port0 Bit3. (See the Port I/O Sub-System section for complete description).
Port0 Bit4. (See the Port I/O Sub-System section for complete description).
Port0 Bit5. (See the Port I/O Sub-System section for complete description).
Port0 Bit6. (See the Port I/O Sub-System section for complete description).
Port0 Bit7. (See the Port I/O Sub-System section for complete description).
Port1 Bit0. (See the Port I/O Sub-System section for complete description).
Port1 Bit1. (See the Port I/O Sub-System section for complete description).
Port1 Bit2. (See the Port I/O Sub-System section for complete description).
Port1 Bit3. (See the Port I/O Sub-System section for complete description).
Port1 Bit4. (See the Port I/O Sub-System section for complete description).
Port1 Bit5. (See the Port I/O Sub-System section for complete description).
Port1 Bit6. (See the Port I/O Sub-System section for complete description).
Port1 Bit7. (See the Port I/O Sub-System section for complete description).
Port2 Bit0. (See the Port I/O Sub-System section for complete description).
Port2 Bit1. (See the Port I/O Sub-System section for complete description).
Port2 Bit2. (See the Port I/O Sub-System section for complete description).
Port2 Bit3. (See the Port I/O Sub-System section for complete description).
Port2 Bit4. (See the Port I/O Sub-System section for complete description).
Port2 Bit5. (See the Port I/O Sub-System section for complete description).
Port2 Bit6. (See the Port I/O Sub-System section for complete description).
Port2 Bit7. (See the Port I/O Sub-System section for complete description).
Port3 Bit0. (See the Port I/O Sub-System section for complete description).
Port3 Bit1. (See the Port I/O Sub-System section for complete description).
Port3 Bit2. (See the Port I/O Sub-System section for complete description).
Port3 Bit3. (See the Port I/O Sub-System section for complete description).
Port3 Bit4. (See the Port I/O Sub-System section for complete description).
Port3 Bit5. (See the Port I/O Sub-System section for complete description).
Port3 Bit6. (See the Port I/O Sub-System section for complete description).
Port3 Bit7. (See the Port I/O Sub-System section for complete description).
Rev. 1.7
22
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 4.1. TQFP-64 Pinout Diagram
48
P0.3
P0.2
P3.6
P3.7
P2.6
P2.7
1
2
CP1-
CP1+
CP0-
47
46
45
44
43
42
41
40
39
38
3
4
CP0+
AGND
VREF
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AGND
AV+
5
6
C8051F000
C8051F005
C8051F010
C8051F015
7
P0.1
DGND
8
VDD
P0.0
P1.0
P1.1
P1.2
P1.3
P1.4
P2.0
9
10
11
12
37
36
35
34
33
13
14
15
16
23
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 4.2. TQFP-64 Package Drawing
D
D1
MIN NOM MAX
(mm) (mm) (mm)
A
-
-
-
-
1.20
0.15
1.05
A1 0.05
A2 0.95
E1
E
b
D
0.17 0.22 0.27
-
-
-
-
-
12.00
10.00
0.50
-
-
-
-
-
64
D1
e
PIN 1
DESIGNATOR
1
e
A2
E
12.00
10.00
A
E1
b
A1
Rev. 1.7
24
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 4.3. TQFP-48 Pinout Diagram
1
2
36
35
34
33
32
31
30
29
28
27
26
25
CP0-
CP0+
VREF
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AGND
P0.3
P0.2
P0.1
DGND
VDD
P0.0
P1.0
P1.1
P1.2
DGND
P1.3
P1.4
3
4
C8051F001
C8051F006
C8051F011
C8051F016
5
6
7
8
9
10
11
12
25
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 4.4. TQFP-48 Package Drawing
D
D1
MIN NOM MAX
(mm) (mm) (mm)
A
-
-
-
1.20
0.15
A1 0.05
E1
E
A2 0.95 1.00 1.05
b 0.17 0.22 0.27
D
D1
e
-
-
-
-
-
9.00
7.00
0.50
9.00
7.00
-
-
-
-
-
48
PIN 1
IDENTIFIER
1
e
A2
E
A
E1
A1
b
Rev. 1.7
26
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 4.5. LQFP-32 Pinout Diagram
CP0-
CP0+
VREF
AIN0
P0.3
23 P0.2
P0.1
21 DGND
VDD
19 P0.0
VDD
17 DGND
1
2
3
4
5
6
7
8
24
22
C8051F002
C8051F007
C8051F012
C8051F017
AIN1
20
AIN2
AIN3
18
AGND
27
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 4.6. LQFP-32 Package Drawing
D
D1
MIN NOM MAX
(mm) (mm) (mm)
A
-
-
-
1.60
0.15
A1 0.05
E1
A2 1.35 1.40 1.45
b 0.30 0.37 0.45
E
D
D1
e
-
-
-
-
-
9.00
7.00
0.80
9.00
7.00
-
-
-
-
-
32
PIN 1
IDENTIFIER
1
A2
A
E
E1
A1
b
e
Rev. 1.7
28
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
5. ADC (12-Bit, C8051F000/1/2/5/6/7 Only)
The ADC subsystem for the C8051F000/1/2/5/6/7 consists of a 9-channel, configurable analog multiplexer
(AMUX), a programmable gain amplifier (PGA), and a 100ksps, 12-bit successive-approximation-register ADC
with integrated track-and-hold and programmable window detector (see block diagram in Figure 5.1). The AMUX,
PGA, Data Conversion Modes, and Window Detector are all configurable under software control via the Special
Function Register’s shown in Figure 5.1. The ADC subsystem (ADC, track-and-hold and PGA) is enabled only
when the ADCEN bit in the ADC Control register (ADC0CN, Figure 5.7) is set to 1. The ADC subsystem is in low
power shutdown when this bit is 0. The Bias Enable bit (BIASE) in the REF0CN register (see Figure 9.2) must be
set to 1 in order to supply bias to the ADC.
Figure 5.1. 12-Bit ADC Functional Block Diagram
ADC0GTH
ADC0GTL
ADC0LTH
ADC0LTL
24
12
COMB
LOGIC
AV+
+
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
ADWINT
ADCEN
AV+
-
+
-
9-to-1
AMUX
(SE or
DIFF)
12-Bit
SAR
ADC
+
+
12
X
-
-
+
AGND
-
TEMP
SENSOR
TMR3 OV
T2 OV
CNVSTR
ADBUSY(w)
AGND
AMX0CF
AMX0SL
ADC0CF
ADC0CN
5.1.
Analog Multiplexer and PGA
Eight of the AMUX channels are available for external measurements while the ninth channel is internally
connected to an on-board temperature sensor (temperature transfer function is shown in Figure 5.3). Note that the
PGA gain is applied to the temperature sensor reading. AMUX input pairs can be programmed to operate in either
the differential or single-ended mode. This allows the user to select the best measurement technique for each input
channel, and even accommodates mode changes “on-the-fly”. The AMUX defaults to all single-ended inputs upon
reset. There are two registers associated with the AMUX: the Channel Selection register AMX0SL (Figure 5.5),
and the Configuration register AMX0CF (Figure 5.4). The table in Figure 5.5 shows AMUX functionality by
channel for each possible configuration. The PGA amplifies the AMUX output signal by an amount determined by
the AMPGN2-0 bits in the ADC Configuration register, ADC0CF (Figure 5.6). The PGA can be software-
programmed for gains of 0.5, 1, 2, 4, 8 or 16. It defaults to unity gain on reset.
29
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
5.2.
ADC Modes of Operation
The ADC uses VREF to determine its full-scale voltage, thus the reference must be properly configured before
performing a conversion (see Section 9). The ADC has a maximum conversion speed of 100ksps. The ADC
conversion clock is derived from the system clock. Conversion clock speed can be reduced by a factor of 2, 4, 8 or
16 via the ADCSC bits in the ADC0CF Register. This is useful to adjust conversion speed to accommodate
different system clock speeds.
A conversion can be initiated in one of four ways, depending on the programmed states of the ADC Start of
Conversion Mode bits (ADSTM1, ADSTM0) in ADC0CN. Conversions may be initiated by:
1. Writing a 1 to the ADBUSY bit of ADC0CN;
2. A Timer 3 overflow (i.e. timed continuous conversions);
3. A rising edge detected on the external ADC convert start signal, CNVSTR;
4. A Timer 2 overflow (i.e. timed continuous conversions).
Writing a 1 to ADBUSY provides software control of the ADC whereby conversions are performed “on-demand”.
During conversion, the ADBUSY bit is set to 1 and restored to 0 when conversion is complete. The falling edge of
ADBUSY triggers an interrupt (when enabled) and sets the ADCINT interrupt flag. Note: When conversions are
performed “on-demand”, the ADCINT flag, not ADBUSY, should be polled to determine when the
conversion has completed. Converted data is available in the ADC data word MSB and LSB registers, ADC0H,
ADC0L. Converted data can be either left or right justified in the ADC0H:ADC0L register pair (see example in
Figure 5.9) depending on the programmed state of the ADLJST bit in the ADC0CN register.
The ADCTM bit in register ADC0CN controls the ADC track-and-hold mode. In its default state, the ADC input is
continuously tracked, except when a conversion is in progress. Setting ADCTM to 1 allows one of four different
low power track-and-hold modes to be specified by states of the ADSTM1-0 bits (also in ADC0CN):
1. Tracking begins with a write of 1 to ADBUSY and lasts for 3 SAR clocks;
2. Tracking starts with an overflow of Timer 3 and lasts for 3 SAR clocks;
3. Tracking is active only when the CNVSTR input is low;
4. Tracking starts with an overflow of Timer 2 and lasts for 3 SAR clocks.
Modes 1, 2 and 4 (above) are useful when the start of conversion is triggered with a software command or when the
ADC is operated continuously. Mode 3 is used when the start of conversion is triggered by external hardware. In
this case, the track-and-hold is in its low power mode at times when the CNVSTR input is high. Tracking can also
be disabled (shutdown) when the entire chip is in low power standby or sleep modes.
Figure 5.2. 12-Bit ADC Track and Conversion Example Timing
A. ADC Timing for External Trigger Source
CNVSTR
(ADSTM[1:0]=10)
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
SAR Clocks
ADCTM=1
ADCTM=0
Low Power or
Convert
Track
Convert
Convert
Low Power Mode
Track
Track Or Convert
B. ADC Timing for Internal Trigger Sources
Timer2, Timer3 Overflow;
Write 1 to ADBUSY
(ADSTM[1:0]=00, 01, 11)
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
SAR Clocks
Low Power or
Convert
ADCTM=1
Track
Convert
Low Power Mode
Track
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
SAR Clocks
ADCTM=0
Track or Convert
Convert
Rev. 1.7
30
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 5.3. Temperature Sensor Transfer Function
(Volts)
1.000
0.900
0.800
0.700
0.600
0.500
VTEMP = 0.00286(TEMPC) + 0.776
for PGA Gain = 1
(Celsius)
-50
0
50
100
Figure 5.4. AMX0CF: AMUX Configuration Register (C8051F00x)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
-
-
-
-
AIN67IC AIN45IC AIN23IC AIN01IC 00000000
SFR Address:
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0xBA
Bits7-4: UNUSED. Read = 0000b; Write = don’t care
Bit3:
Bit2:
Bit1:
Bit0:
AIN67IC: AIN6, AIN7 Input Pair Configuration Bit
0: AIN6 and AIN7 are independent singled-ended inputs
1: AIN6, AIN7 are (respectively) +, - differential input pair
AIN45IC: AIN4, AIN5 Input Pair Configuration Bit
0: AIN4 and AIN5 are independent singled-ended inputs
1: AIN4, AIN5 are (respectively) +, - differential input pair
AIN23IC: AIN2, AIN3 Input Pair Configuration Bit
0: AIN2 and AIN3 are independent singled-ended inputs
1: AIN2, AIN3 are (respectively) +, - differential input pair
AIN01IC: AIN0, AIN1 Input Pair Configuration Bit
0: AIN0 and AIN1 are independent singled-ended inputs
1: AIN0, AIN1 are (respectively) +, - differential input pair
NOTE: The ADC Data Word is in 2’s complement format for channels configured as differential.
31
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 5.5. AMX0SL: AMUX Channel Select Register (C8051F00x)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
AMXAD3 AMXAD2 AMXAD1 AMXAD0
-
-
-
-
00000000
SFR Address:
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0xBB
Bits7-4: UNUSED. Read = 0000b; Write = don’t care
Bits3-0: AMXAD3-0: AMUX Address Bits
0000-1111: ADC Inputs selected per chart below
AMXAD3-0
0000
AIN0
0001
AIN1
0010
AIN2
0011
AIN3
0100
0101
AIN5
0110
0111
AIN7
1xxx
TEMP
A
M
X
0
0000
AIN4
AIN6
AIN6
AIN6
AIN6
AIN6
AIN6
AIN6
AIN6
SENSOR
+(AIN0)
-(AIN1)
TEMP
AIN2
AIN3
AIN4
AIN4
AIN4
AIN5
AIN5
AIN5
AIN7
AIN7
AIN7
AIN7
AIN7
AIN7
AIN7
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
SENSOR
C
F
+(AIN2)
-(AIN3)
+(AIN2)
-(AIN3)
TEMP
AIN0
AIN1
AIN1
AIN1
AIN1
AIN1
AIN1
AIN1
SENSOR
+(AIN0)
-(AIN1)
TEMP
B
I
SENSOR
+(AIN4)
-(AIN5)
+(AIN4)
-(AIN5)
+(AIN4)
-(AIN5)
+(AIN4)
-(AIN5)
TEMP
AIN0
AIN2
AIN2
AIN3
AIN3
T
S
SENSOR
+(AIN0)
-(AIN1)
TEMP
SENSOR
3
-
+(AIN2)
-(AIN3)
+(AIN2)
-(AIN3)
TEMP
AIN0
SENSOR
0
+(AIN0)
-(AIN1)
TEMP
SENSOR
+(AIN6)
-(AIN7)
+(AIN6)
-(AIN7)
+(AIN6)
-(AIN7)
+(AIN6)
-(AIN7)
+(AIN6)
-(AIN7)
+(AIN6)
-(AIN7)
+(AIN6)
-(AIN7)
TEMP
AIN0
AIN2
AIN2
AIN3
AIN3
AIN4
AIN4
AIN4
AIN4
AIN5
AIN5
AIN5
AIN5
SENSOR
+(AIN0)
-(AIN1)
TEMP
SENSOR
+(AIN2)
-(AIN3)
+(AIN2)
-(AIN3)
TEMP
AIN0
SENSOR
+(AIN0)
-(AIN1)
TEMP
SENSOR
+(AIN4)
-(AIN5)
+(AIN4)
-(AIN5)
+(AIN4)
-(AIN5)
TEMP
AIN0
AIN2
AIN2
AIN3
AIN3
SENSOR
+(AIN0)
-(AIN1)
TEMP
SENSOR
+(AIN2)
-(AIN3)
TEMP
AIN0
SENSOR
+(AIN0)
-(AIN1)
+(AIN2)
-(AIN3)
+(AIN4)
-(AIN5)
+(AIN6)
-(AIN7)
TEMP
1111
SENSOR
Rev. 1.7
32
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 5.6. ADC0CF: ADC Configuration Register (C8051F00x)
R/W
ADCSC2
Bit7
R/W
ADCSC1
Bit6
R/W
ADCSC0
Bit5
R/W
-
Bit4
R/W
-
Bit3
R/W
AMPGN2
Bit2
R/W
AMPGN1
Bit1
R/W
AMPGN0
Bit0
Reset Value
01100000
SFR Address:
0xBC
Bits7-5: ADCSC2-0: ADC SAR Conversion Clock Period Bits
000: SAR Conversion Clock = 1 System Clock
001: SAR Conversion Clock = 2 System Clocks
010: SAR Conversion Clock = 4 System Clocks
011: SAR Conversion Clock = 8 System Clocks
1xx: SAR Conversion Clock = 16 Systems Clocks
(Note: the SAR Conversion Clock should be ≤ 2MHz)
Bits4-3: UNUSED. Read = 00b; Write = don’t care
Bits2-0: AMPGN2-0: ADC Internal Amplifier Gain
000: Gain = 1
001: Gain = 2
010: Gain = 4
011: Gain = 8
10x: Gain = 16
11x: Gain = 0.5
33
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 5.7. ADC0CN: ADC Control Register (C8051F00x)
R/W
ADCEN
Bit7
R/W
ADCTM
Bit6
R/W
ADCINT
Bit5
R/W
ADBUSY
Bit4
R/W
ADSTM1
Bit3
R/W
ADSTM0
Bit2
R/W
ADWINT
Bit1
R/W
Reset Value
ADLJST
00000000
SFR Address:
Bit0
(bit addressable)
0xE8
Bit7:
Bit6:
ADCEN: ADC Enable Bit
0: ADC Disabled. ADC is in low power shutdown.
1: ADC Enabled. ADC is active and ready for data conversions.
ADCTM: ADC Track Mode Bit
0: When the ADC is enabled, tracking is always done unless a conversion is in process
1: Tracking Defined by ADSTM1-0 bits
ADSTM1-0:
00: Tracking starts with the write of 1 to ADBUSY and lasts for 3 SAR clocks
01: Tracking started by the overflow of Timer 3 and last for 3 SAR clocks
10: ADC tracks only when CNVSTR input is logic low
11: Tracking started by the overflow of Timer 2 and last for 3 SAR clocks
ADCINT: ADC Conversion Complete Interrupt Flag
(Must be cleared by software)
Bit5:
Bit4:
0: ADC has not completed a data conversion since the last time this flag was cleared
1: ADC has completed a data conversion
ADBUSY: ADC Busy Bit
Read
0: ADC Conversion complete or no valid data has been converted since a reset. The falling
edge of ADBUSY generates an interrupt when enabled.
1: ADC Busy converting data
Write
0: No effect
1: Starts ADC Conversion if ADSTM1-0 = 00b
Bits3-2: ADSTM1-0: ADC Start of Conversion Mode Bits
00: ADC conversion started upon every write of 1 to ADBUSY
01: ADC conversions taken on every overflow of Timer 3
10: ADC conversion started upon every rising edge of CNVSTR
11: ADC conversions taken on every overflow of Timer 2
Bit1:
ADWINT: ADC Window Compare Interrupt Flag
(Must be cleared by software)
0: ADC Window Comparison Data match has not occurred
1: ADC Window Comparison Data match occurred
ADLJST: ADC Left Justify Data Bit
Bit0:
0: Data in ADC0H:ADC0L Registers is right justified
1: Data in ADC0H:ADC0L Registers is left justified
Rev. 1.7
34
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 5.8. ADC0H: ADC Data Word MSB Register (C8051F00x)
R/W
Bit7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
SFR Address:
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0xBF
Bits7-0: ADC Data Word Bits
For ADLJST = 1: Upper 8-bits of the 12-bit ADC Data Word.
For ADLJST = 0: Bits7-4 are the sign extension of Bit3. Bits 3-0 are the upper 4-bits of the
12-bit ADC Data Word.
Figure 5.9. ADC0L: ADC Data Word LSB Register (C8051F00x)
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Bit0
Reset Value
00000000
SFR Address:
0xBE
Bits7-0: ADC Data Word Bits
For ADLJST = 1: Bits7-4 are the lower 4-bits of the 12-bit ADC Data Word. Bits3-0 will
always read 0.
For ADLJST = 0: Bits7-0 are the lower 8-bits of the 12-bit ADC Data Word.
NOTE: Resulting 12-bit ADC Data Word appears in the ADC Data Word Registers as follows:
ADC0H[3:0]:ADC0L[7:0], if ADLJST = 0
(ADC0H[7:4] will be sign extension of ADC0H.3 if a differential reading, otherwise = 0000b)
ADC0H[7:0]:ADC0L[7:4], if ADLJST = 1
(ADC0L[3:0] = 0000b)
EXAMPLE: ADC Data Word Conversion Map, AIN0 Input in Single-Ended Mode
(AMX0CF=0x00, AMX0SL=0x00)
ADC0H:ADC0L
ADC0H:ADC0L
AIN0 – AGND
(ADLJST = 0)
(ADLJST = 1)
(Volts)
REF x (4095/4096)
REF x ½
REF x (2047/4096)
0
0x0FFF
0x0800
0x07FF
0x0000
0xFFF0
0x8000
0x7FF0
0x0000
EXAMPLE: ADC Data Word Conversion Map, AIN0-AIN1 Differential Input Pair
(AMX0CF=0x01, AMX0SL=0x00)
ADC0H:ADC0L
ADC0H:ADC0L
AIN0 – AIN1 (Volts)
(ADLJST = 0)
(ADLJST = 1)
REF x (2047/2048)
0x07FF
0x0000
0xFFFF
0xF800
0x7FF0
0x0000
0xFFF0
0x8000
0
-REF x (1/2048)
-REF
35
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
5.3.
ADC Programmable Window Detector
The ADC programmable window detector is very useful in many applications. It continuously compares the ADC
output to user-programmed limits and notifies the system when an out-of-band condition is detected. This is
especially effective in an interrupt-driven system, saving code space and CPU bandwidth while delivering faster
system response times. The window detector interrupt flag (ADWINT in ADC0CN) can also be used in polled
mode. The high and low bytes of the reference words are loaded into the ADC Greater-Than and ADC Less-Than
registers (ADC0GTH, ADC0GTL, ADC0LTH, and ADC0LTL). Figure 5.14 and Figure 5.15 show example
comparisons for reference. Notice that the window detector flag can be asserted when the measured data is inside
or outside the user-programmed limits, depending on the programming of the ADC0GTx and ADC0LTx registers.
Figure 5.10. ADC0GTH: ADC Greater-Than Data High Byte Register (C8051F00x)
R/W
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Bit0
Reset Value
11111111
SFR Address:
Bit7
0xC5
Bits7-0:
The high byte of the ADC Greater-Than Data Word.
Figure 5.11. ADC0GTL: ADC Greater-Than Data Low Byte Register (C8051F00x)
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Bit0
Reset Value
11111111
SFR Address:
0xC4
Bits7-0:
The low byte of the ADC Greater-Than Data Word.
Definition:
ADC Greater-Than Data Word = ADC0GTH:ADC0GTL
Figure 5.12. ADC0LTH: ADC Less-Than Data High Byte Register (C8051F00x)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
SFR Address:
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0xC7
Bits7-0:
The high byte of the ADC Less-Than Data Word.
Figure 5.13. ADC0LTL: ADC Less-Than Data Low Byte Register (C8051F00x)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
SFR Address:
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0xC6
Bits7-0:
These bits are the low byte of the ADC Less-Than Data Word.
Definition:
ADC Less-Than Data Word = ADC0LTH:ADC0LTL
Rev. 1.7
36
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 5.14. 12-Bit ADC Window Interrupt Examples, Right Justified Data
Input Voltage
(AD0 - AGND)
Input Voltage
(AD0 - AGND)
ADC Data
Word
0x0FFF
ADC Data
Word
0x0FFF
REF x (4095/4096)
REF x (4095/4096)
ADWINT
ADWINT=1
not affected
0x0201
0x0201
REF x (512/4096)
REF x (256/4096)
0x0200
0x01FF
ADC0LTH:ADC0LTL
ADWINT=1
REF x (512/4096)
REF x (256/4096)
0x0200
0x01FF
ADC0GTH:ADC0GTL
ADWINT
not affected
0x0101
0x0100
0x0101
0x0100
ADC0GTH:ADC0GTL
ADC0LTH:ADC0LTL
0x00FF
0x00FF
ADWINT=1
ADWINT
not affected
0x0000
0x0000
0
0
Given:
Given:
AMX0SL = 0x00, AMX0CF = 0x00, ADLJST = 0,
ADC0LTH:ADC0LTL = 0x0200,
AMX0SL = 0x00, AMX0CF = 0x00, ADLJST = 0,
ADC0LTH:ADC0LTL = 0x0100,
ADC0GTH:ADC0GTL = 0x0100.
ADC0GTH:ADC0GTL = 0x0200.
An ADC End of Conversion will cause an ADC Window
Compare Interrupt (ADWINT=1) if the resulting ADC
Data Word is < 0x0200 and > 0x0100.
An ADC End of Conversion will cause an ADC Window
Compare Interrupt (ADWINT=1) if the resulting ADC
Data Word is < 0x0100 or > 0x0200.
ADC Data
Input Voltage
ADC Data
Word
(AD0 - AD1)
Word
REF x (2047/2048)
0x07FF
REF x (2047/2048)
0x07FF
ADWINT
ADWINT=1
not affected
0x0101
0x0101
REF x (256/2048)
REF x (-1/2048)
0x0100
0x00FF
ADC0LTH:ADC0LTL
ADWINT=1
REF x (256/2048)
REF x (-1/2048)
0x0100
0x00FF
ADC0GTH:ADC0GTL
ADWINT
not affected
0x0000
0xFFFF
0x0000
0xFFFF
ADC0GTH:ADC0GTL
ADC0LTH:ADC0LTL
ADWINT=1
0xFFFE
0xFFFE
ADWINT
not affected
0xF800
0xF800
-REF
-REF
Given:
Given:
AMX0SL = 0x00, AMX0CF = 0x01, ADLJST = 0,
ADC0LTH:ADC0LTL = 0x0100,
AMX0SL = 0x00, AMX0CF = 0x01, ADLJST = 0,
ADC0LTH:ADC0LTH = 0xFFFF,
ADC0GTH:ADC0GTL = 0xFFFF.
ADC0GTH:ADC0GTL = 0x0100.
An ADC End of Conversion will cause an ADC Window
Compare Interrupt (ADWINT=1) if the resulting ADC
An ADC End of Conversion will cause an ADC Window
Compare Interrupt (ADWINT=1) if the resulting ADC
Data Word is < 0xFFFF or > 0x0100. (Two’s Complement
math, 0xFFFF = -1.)
Data Word is
<
0x0100 and
>
0xFFFF.
(Two’s
Complement math, 0xFFFF = -1.)
37
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 5.15. 12-Bit ADC Window Interrupt Examples, Left Justified Data
Input Voltage
Input Voltage
(AD0 - AGND)
ADC Data
Word
0xFFF0
ADC Data
Word
0xFFF0
(AD0 - AGND)
REF x (4095/4096)
REF x (4095/4096)
ADWINT
ADWINT=1
not affected
0x2010
0x2010
REF x (512/4096)
REF x (256/4096)
0x2000
0x1FF0
ADC0LTH:ADC0LTL
ADWINT=1
REF x (512/4096)
REF x (256/4096)
0x2000
0x1FF0
ADC0GTH:ADC0GTL
ADWINT
not affected
0x1010
0x1000
0x1010
0x1000
ADC0GTH:ADC0GTL
ADC0LTH:ADC0LTL
0x0FF0
0x0FF0
ADWINT=1
ADWINT
not affected
0x0000
0x0000
0
0
Given:
Given:
AMX0SL = 0x00, AMX0CF = 0x00, ADLJST = 1,
ADC0LTH:ADC0LTL = 0x2000,
AMX0SL = 0x00, AMX0CF = 0x00, ADLJST = 1,
ADC0LTH:ADC0LTL = 0x1000,
ADC0GTH:ADC0GTL = 0x1000.
ADC0GTH:ADC0GTL = 0x2000.
An ADC End of Conversion will cause an ADC Window
Compare Interrupt (ADWINT=1) if the resulting ADC
Data Word is < 0x2000 and > 0x1000.
An ADC End of Conversion will cause an ADC Window
Compare Interrupt (ADWINT=1) if the resulting ADC
Data Word is < 0x1000 or > 0x2000.
Input Voltage
ADC Data
Input Voltage
ADC Data
(AD0 - AD1)
Word
(AD0 - AD1)
Word
REF x (2047/2048)
0x7FF0
REF x (2047/2048)
0x7FF0
ADWINT
ADWINT=1
not affected
0x1010
0x1010
REF x (256/2048)
REF x (-1/2048)
0x1000
0x0FF0
ADC0LTH:ADC0LTL
ADWINT=1
REF x (256/2048)
REF x (-1/2048)
0x1000
0x0FF0
ADC0GTH:ADC0GTL
ADWINT
not affected
0x0000
0xFFF0
0x0000
0xFFF0
ADC0GTH:ADC0GTL
ADC0LTH:ADC0LTL
ADWINT=1
0xFFE0
0xFFE0
ADWINT
not affected
0x8000
0x8000
-REF
-REF
Given:
Given:
AMX0SL = 0x00, AMX0CF = 0x01, ADLJST = 1,
ADC0LTH:ADC0LTL = 0x1000,
AMX0SL = 0x00, AMX0CF = 0x01, ADLJST = 1,
ADC0LTH:ADC0LTH = 0xFFF0,
ADC0GTH:ADC0GTL = 0xFFF0.
ADC0GTH:ADC0GTL = 0x1000.
An ADC End of Conversion will cause an ADC Window
Compare Interrupt (ADWINT=1) if the resulting ADC
An ADC End of Conversion will cause an ADC Window
Compare Interrupt (ADWINT=1) if the resulting ADC
Data Word is < 0xFFF0 or > 0x1000. (Two’s Complement
math.)
Data Word is
<
0x1000 and
>
0xFFF0.
(Two’s
Complement math.)
Rev. 1.7
38
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Table 5.1. 12-Bit ADC Electrical Characteristics
VDD = 3.0V, AV+ = 3.0V, VREF = 2.40V (REFBE=0), PGA Gain = 1, -40°C to +85°C unless otherwise specified.
PARAMETER
DC ACCURACY
Resolution
CONDITIONS
MIN
TYP
MAX
UNITS
12
bits
LSB
Integral Nonlinearity
Differential Nonlinearity
Offset Error
± 1
± 1
Guaranteed Monotonic
Differential mode
LSB
LSB
-3 ± 1
-7 ± 3
± 0.25
Full Scale Error
Offset Temperature
Coefficient
LSB
ppm/°C
DYNAMIC PERFORMANCE (10kHz sine-wave input, 0 to –1dB of full scale, 100ksps)
Signal-to-Noise Plus
Distortion
66
69
dB
Total Harmonic Distortion
Spurious-Free Dynamic
Range
Up to the 5th harmonic
-75
80
dB
dB
CONVERSION RATE
Conversion Time in SAR
Clocks
16
clocks
SAR Clock Frequency
C8051F000, ‘F001, ‘F002
C8051F005, ‘F006, ‘F007
2.0
2.5
MHz
MHz
µs
Track/Hold Acquisition
Time
1.5
Throughput Rate
100
ksps
V
ANALOG INPUTS
Voltage Conversion Range
Single-ended Mode (AINn – AGND)
Differential Mode |(AINn+) – (AINm-)|
Any AINn pin
0
VREF
- 1LSB
AV+
Input Voltage
AGND
V
pF
Input Capacitance
TEMPERATURE SENSOR
Linearity
10
± 0.20
± 3
°C
°C
Absolute Accuracy
Gain
Gain Error (±1σ)
Offset
PGA Gain = 1
PGA Gain = 1
PGA Gain = 1, Temp = 0°C
PGA Gain = 1, Temp = 0°C
2.86
mV/°C
µV/°C
mV
± 33.5
776
mV
Offset Error (±1σ)
POWER SPECIFICATIONS
± 8.51
Power Supply Current (AV+ Operating Mode, 100ksps
supplied to ADC)
450
900
µA
Power Supply Rejection
mV/V
± 0.3
39
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
6. ADC (10-Bit, C8051F010/1/2/5/6/7 Only)
The ADC subsystem for the C8051F010/1/2/5/6/7 consists of a 9-channel, configurable analog multiplexer
(AMUX), a programmable gain amplifier (PGA), and a 100ksps, 10-bit successive-approximation-register ADC
with integrated track-and-hold and programmable window detector (see block diagram in Figure 6.1). The AMUX,
PGA, Data Conversion Modes, and Window Detector are all configurable under software control via the Special
Function Register’s shown in Figure 6.1. The ADC subsystem (ADC, track-and-hold and PGA) is enabled only
when the ADCEN bit in the ADC Control register (ADC0CN, Figure 6.7) is set to 1. The ADC subsystem is in low
power shutdown when this bit is 0. The Bias Enable bit (BIASE) in the REF0CN register (see Figure 9.2) must be
set to 1 in order to supply bias to the ADC.
Figure 6.1. 10-Bit ADC Functional Block Diagram
ADC0GTH
ADC0GTL
ADC0LTH
ADC0LTL
20
10
COMB
LOGIC
AV+
+
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
ADWINT
ADCEN
AV+
-
+
-
9-to-1
AMUX
(SE or
DIFF)
10-Bit
SAR
ADC
+
+
10
X
-
-
+
AGND
-
TEMP
SENSOR
TMR3 OV
T2 OV
CNVSTR
ADBUSY(w)
AGND
AMX0CF
AMX0SL
ADC0CF
ADC0CN
6.1.
Analog Multiplexer and PGA
Eight of the AMUX channels are available for external measurements while the ninth channel is internally
connected to an on-board temperature sensor (temperature transfer function is shown in Figure 6.3). Note that the
PGA gain is applied to the temperature sensor reading. AMUX input pairs can be programmed to operate in either
the differential or single-ended mode. This allows the user to select the best measurement technique for each input
channel, and even accommodates mode changes “on-the-fly”. The AMUX defaults to all single-ended inputs upon
reset. There are two registers associated with the AMUX: the Channel Selection register AMX0SL (Figure 6.5),
and the Configuration register AMX0CF (Figure 6.4). The table in Figure 6.5 shows AMUX functionality by
channel for each possible configuration. The PGA amplifies the AMUX output signal by an amount determined by
the AMPGN2-0 bits in the ADC Configuration register, ADC0CF (Figure 6.6). The PGA can be software-
programmed for gains of 0.5, 1, 2, 4, 8 or 16. It defaults to unity gain on reset.
Rev. 1.7
40
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
6.2.
ADC Modes of Operation
The ADC uses VREF to determine its full-scale voltage, thus the reference must be properly configured before
performing a conversion (see Section 9). The ADC has a maximum conversion speed of 100ksps. The ADC
conversion clock is derived from the system clock. Conversion clock speed can be reduced by a factor of 2, 4, 8 or
16 via the ADCSC bits in the ADC0CF Register. This is useful to adjust conversion speed to accommodate
different system clock speeds.
A conversion can be initiated in one of four ways, depending on the programmed states of the ADC Start of
Conversion Mode bits (ADSTM1, ADSTM0) in ADC0CN. Conversions may be initiated by:
1. Writing a 1 to the ADBUSY bit of ADC0CN;
2. A Timer 3 overflow (i.e. timed continuous conversions);
3. A rising edge detected on the external ADC convert start signal, CNVSTR;
4. A Timer 2 overflow (i.e. timed continuous conversions).
Writing a 1 to ADBUSY provides software control of the ADC whereby conversions are performed “on-demand”.
During conversion, the ADBUSY bit is set to 1 and restored to 0 when conversion is complete. The falling edge of
ADBUSY triggers an interrupt (when enabled) and sets the ADCINT interrupt flag. Note: When conversions are
performed “on-demand”, the ADCINT flag, not ADBUSY, should be polled to determine when the
conversion has completed. Converted data is available in the ADC data word MSB and LSB registers, ADC0H,
ADC0L. Converted data can be either left or right justified in the ADC0H:ADC0L register pair (see example in
Figure 6.9) depending on the programmed state of the ADLJST bit in the ADC0CN register.
The ADCTM bit in register ADC0CN controls the ADC track-and-hold mode. In its default state, the ADC input is
continuously tracked, except when a conversion is in progress. Setting ADCTM to 1 allows one of four different
low power track-and-hold modes to be specified by states of the ADSTM1-0 bits (also in ADC0CN):
1. Tracking begins with a write of 1 to ADBUSY and lasts for 3 SAR clocks;
2. Tracking starts with an overflow of Timer 3 and lasts for 3 SAR clocks;
3. Tracking is active only when the CNVSTR input is low;
4. Tracking starts with an overflow of Timer 2 and lasts for 3 SAR clocks.
Modes 1, 2 and 4 (above) are useful when the start of conversion is triggered with a software command or when the
ADC is operated continuously. Mode 3 is used when the start of conversion is triggered by external hardware. In
this case, the track-and-hold is in its low power mode at times when the CNVSTR input is high. Tracking can also
be disabled (shutdown) when the entire chip is in low power standby or sleep modes.
Figure 6.2. 10-Bit ADC Track and Conversion Example Timing
A. ADC Timing for External Trigger Source
CNVSTR
(ADSTM[1:0]=10)
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
SAR Clocks
ADCTM=1
ADCTM=0
Low Power or
Convert
Track
Convert
Convert
Low Power Mode
Track
Track Or Convert
B. ADC Timing for Internal Trigger Sources
Timer2, Timer3 Overflow;
Write 1 to ADBUSY
(ADSTM[1:0]=00, 01, 11)
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
SAR Clocks
Low Power or
Convert
ADCTM=1
Track
Convert
Low Power Mode
Track
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
SAR Clocks
ADCTM=0
Track or Convert
Convert
41
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 6.3. Temperature Sensor Transfer Function
(Volts)
1.000
0.900
0.800
VTEMP = 0.00286(TEMPC) + 0.776
for PGA Gain = 1
0.700
0.600
0.500
(Celsius)
-50
0
50
100
Figure 6.4. AMX0CF: AMUX Configuration Register (C8051F01x)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
-
-
-
-
AIN67IC AIN45IC AIN23IC AIN01IC 00000000
SFR Address:
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0xBA
Bits7-4: UNUSED. Read = 0000b; Write = don’t care
Bit3:
Bit2:
Bit1:
Bit0:
AIN67IC: AIN6, AIN7 Input Pair Configuration Bit
0: AIN6 and AIN7 are independent singled-ended inputs
1: AIN6, AIN7 are (respectively) +, - differential input pair
AIN45IC: AIN4, AIN5 Input Pair Configuration Bit
0: AIN4 and AIN5 are independent singled-ended inputs
1: AIN4, AIN5 are (respectively) +, - differential input pair
AIN23IC: AIN2, AIN3 Input Pair Configuration Bit
0: AIN2 and AIN3 are independent singled-ended inputs
1: AIN2, AIN3 are (respectively) +, - differential input pair
AIN01IC: AIN0, AIN1 Input Pair Configuration Bit
0: AIN0 and AIN1 are independent singled-ended inputs
1: AIN0, AIN1 are (respectively) +, - differential input pair
NOTE: The ADC Data Word is in 2’s complement format for channels configured as differential.
Rev. 1.7
42
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 6.5. AMX0SL: AMUX Channel Select Register (C8051F01x)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
AMXAD3 AMXAD2 AMXAD1 AMXAD0
-
-
-
-
00000000
SFR Address:
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0xBB
Bits7-4: UNUSED. Read = 0000b; Write = don’t care
Bits3-0: AMXAD3-0: AMUX Address Bits
0000-1111: ADC Inputs selected per chart below
AMXAD3-0
0000
AIN0
0001
AIN1
0010
AIN2
0011
AIN3
0100
0101
AIN5
0110
0111
AIN7
1xxx
A
M
X
0
TEMP
AIN4
AIN6
AIN6
AIN6
AIN6
AIN6
AIN6
AIN6
AIN6
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
SENSOR
+(AIN0)
-(AIN1)
TEMP
AIN2
AIN3
AIN4
AIN4
AIN4
AIN5
AIN5
AIN5
AIN7
AIN7
AIN7
AIN7
AIN7
AIN7
AIN7
SENSOR
C
F
+(AIN2)
-(AIN3)
+(AIN2)
-(AIN3)
TEMP
AIN0
AIN1
AIN1
AIN1
AIN1
AIN1
AIN1
AIN1
SENSOR
+(AIN0)
-(AIN1)
TEMP
B
I
SENSOR
+(AIN4)
-(AIN5)
+(AIN4)
-(AIN5)
+(AIN4)
-(AIN5)
+(AIN4)
-(AIN5)
TEMP
AIN0
AIN2
AIN2
AIN3
AIN3
T
S
SENSOR
+(AIN0)
-(AIN1)
TEMP
SENSOR
3
-
+(AIN2)
-(AIN3)
+(AIN2)
-(AIN3)
TEMP
AIN0
SENSOR
0
+(AIN0)
-(AIN1)
TEMP
SENSOR
+(AIN6)
-(AIN7)
+(AIN6)
-(AIN7)
+(AIN6)
-(AIN7)
+(AIN6)
-(AIN7)
+(AIN6)
-(AIN7)
+(AIN6)
-(AIN7)
+(AIN6)
-(AIN7)
TEMP
AIN0
AIN2
AIN2
AIN3
AIN3
AIN4
AIN4
AIN4
AIN4
AIN5
AIN5
AIN5
AIN5
SENSOR
+(AIN0)
-(AIN1)
TEMP
SENSOR
+(AIN2)
-(AIN3)
+(AIN2)
-(AIN3)
TEMP
AIN0
SENSOR
+(AIN0)
-(AIN1)
TEMP
SENSOR
+(AIN4)
-(AIN5)
+(AIN4)
-(AIN5)
+(AIN4)
-(AIN5)
TEMP
AIN0
AIN2
AIN2
AIN3
AIN3
SENSOR
+(AIN0)
-(AIN1)
TEMP
SENSOR
+(AIN2)
-(AIN3)
TEMP
AIN0
SENSOR
+(AIN0)
-(AIN1)
+(AIN2)
-(AIN3)
+(AIN4)
-(AIN5)
+(AIN6)
-(AIN7)
TEMP
SENSOR
43
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 6.6. ADC0CF: ADC Configuration Register (C8051F01x)
R/W
ADCSC2
Bit7
R/W
ADCSC1
Bit6
R/W
ADCSC0
Bit5
R/W
-
Bit4
R/W
-
Bit3
R/W
AMPGN2
Bit2
R/W
AMPGN1
Bit1
R/W
AMPGN0
Bit0
Reset Value
01100000
SFR Address:
0xBC
Bits7-5: ADCSC2-0: ADC SAR Conversion Clock Period Bits
000: SAR Conversion Clock = 1 System Clock
001: SAR Conversion Clock = 2 System Clocks
010: SAR Conversion Clock = 4 System Clocks
011: SAR Conversion Clock = 8 System Clocks
1xx: SAR Conversion Clock = 16 Systems Clocks
(Note: Conversion clock should be ≤ 2MHz.)
Bits4-3: UNUSED. Read = 00b; Write = don’t care
Bits2-0: AMPGN2-0: ADC Internal Amplifier Gain
000: Gain = 1
001: Gain = 2
010: Gain = 4
011: Gain = 8
10x: Gain = 16
11x: Gain = 0.5
Rev. 1.7
44
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 6.7. ADC0CN: ADC Control Register (C8051F01x)
R/W
ADCEN
Bit7
R/W
ADCTM
Bit6
R/W
ADCINT
Bit5
R/W
ADBUSY
Bit4
R/W
ADSTM1
Bit3
R/W
ADSTM0
Bit2
R/W
ADWINT
Bit1
R/W
Reset Value
ADLJST
00000000
SFR Address:
Bit0
(bit addressable)
0xE8
Bit7:
Bit6:
ADCEN: ADC Enable Bit
0: ADC Disabled. ADC is in low power shutdown.
1: ADC Enabled. ADC is active and ready for data conversions.
ADCTM: ADC Track Mode Bit
0: When the ADC is enabled, tracking is always done unless a conversion is in process
1: Tracking Defined by ADSTM1-0 bits
ADSTM1-0:
00: Tracking starts with the write of 1 to ADBUSY and lasts for 3 SAR clocks
01: Tracking started by the overflow of Timer 3 and last for 3 SAR clocks
10: ADC tracks only when CNVSTR input is logic low
11: Tracking started by the overflow of Timer 2 and last for 3 SAR clocks
ADCINT: ADC Conversion Complete Interrupt Flag
(Must be cleared by software)
Bit5:
Bit4:
0: ADC has not completed a data conversion since the last time this flag was cleared
1: ADC has completed a data conversion
ADBUSY: ADC Busy Bit
Read
0: ADC Conversion complete or no valid data has been converted since a reset. The falling
edge of ADBUSY generates an interrupt when enabled.
1: ADC Busy converting data
Write
0: No effect
1: Starts ADC Conversion if ADSTM1-0 = 00b
Bits3-2: ADSTM1-0: ADC Start of Conversion Mode Bits
00: ADC conversion started upon every write of 1 to ADBUSY
01: ADC conversions taken on every overflow of Timer 3
10: ADC conversion started upon every rising edge of CNVSTR
11: ADC conversions taken on every overflow of Timer 2
Bit1:
ADWINT: ADC Window Compare Interrupt Flag
(Must be cleared by software)
0: ADC Window Comparison Data match has not occurred
1: ADC Window Comparison Data match occurred
ADLJST: ADC Left Justify Data Bit
Bit0:
0: Data in ADC0H:ADC0L Registers is right justified
1: Data in ADC0H:ADC0L Registers is left justified
45
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 6.8. ADC0H: ADC Data Word MSB Register (C8051F01x)
R/W
Bit7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
SFR Address:
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0xBF
Bits7-0: ADC Data Word Bits
For ADLJST = 1: Upper 8-bits of the 10-bit ADC Data Word.
For ADLJST = 0: Bits7-2 are the sign extension of Bit1. Bits 1-0 are the upper 2-bits of the
10-bit ADC Data Word.
Figure 6.9. ADC0L: ADC Data Word LSB Register (C8051F01x)
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Bit0
Reset Value
00000000
SFR Address:
0xBE
Bits7-0: ADC Data Word Bits
For ADLJST = 1: Bits7-6 are the lower 2-bits of the 10-bit ADC Data Word. Bits5-0 will
always read 0.
For ADLJST = 0: Bits7-0 are the lower 8-bits of the 10-bit ADC Data Word.
NOTE: Resulting 10-bit ADC Data Word appears in the ADC Data Word Registers as follows:
ADC0H[1:0]:ADC0L[7:0], if ADLJST = 0
(ADC0H[7:2] will be sign extension of ADC0H.1 if a differential reading, otherwise = 000000b)
ADC0H[7:0]:ADC0L[7:6], if ADLJST = 1
(ADC0L[5:0] = 000000b)
EXAMPLE: ADC Data Word Conversion Map, AIN0 Input in Single-Ended Mode
(AMX0CF=0x00, AMX0SL=0x00)
ADC0H:ADC0L
ADC0H:ADC0L
AIN0 – AGND
(ADLJST = 0)
(ADLJST = 1)
(Volts)
REF x (1023/1024)
REF x ½
REF x (511/1024)
0
0x03FF
0x0200
0x01FF
0x0000
0xFFC0
0x8000
0x7FC0
0x0000
EXAMPLE: ADC Data Word Conversion Map, AIN0-AIN1 Differential Input Pair
(AMX0CF=0x01, AMX0SL=0x00)
ADC0H:ADC0L
ADC0H:ADC0L
AIN0 – AIN1 (Volts)
(ADLJST = 0)
(ADLJST = 1)
REF x (511/512)
0x01FF
0x0000
0xFFFF
0xFE00
0x7FC0
0x0000
0xFFC0
0x8000
0
-REF x (1/512)
-REF
Rev. 1.7
46
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
6.3.
ADC Programmable Window Detector
The ADC programmable window detector is very useful in many applications. It continuously compares the ADC
output to user-programmed limits and notifies the system when an out-of-band condition is detected. This is
especially effective in an interrupt-driven system, saving code space and CPU bandwidth while delivering faster
system response times. The window detector interrupt flag (ADWINT in ADC0CN) can also be used in polled
mode. The high and low bytes of the reference words are loaded into the ADC Greater-Than and ADC Less-Than
registers (ADC0GTH, ADC0GTL, ADC0LTH, and ADC0LTL). Figure 6.14 and Figure 6.15 show example
comparisons for reference. Notice that the window detector flag can be asserted when the measured data is inside
or outside the user-programmed limits, depending on the programming of the ADC0GTx and ADC0LTx registers.
Figure 6.10. ADC0GTH: ADC Greater-Than Data High Byte Register (C8051F01x)
R/W
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Bit0
Reset Value
11111111
SFR Address:
Bit7
0xC5
Bits7-0:
The high byte of the ADC Greater-Than Data Word.
Figure 6.11. ADC0GTL: ADC Greater-Than Data Low Byte Register (C8051F01x)
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Bit0
Reset Value
11111111
SFR Address:
0xC4
Bits7-0:
The low byte of the ADC Greater-Than Data Word.
Definition:
ADC Greater-Than Data Word = ADC0GTH:ADC0GTL
Figure 6.12. ADC0LTH: ADC Less-Than Data High Byte Register (C8051F01x)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
SFR Address:
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0xC7
Bits7-0:
The high byte of the ADC Less-Than Data Word.
Figure 6.13. ADC0LTL: ADC Less-Than Data Low Byte Register (C8051F01x)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
SFR Address:
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0xC6
Bits7-0:
These bits are the low byte of the ADC Less-Than Data Word.
Definition:
ADC Less-Than Data Word = ADC0LTH:ADC0LTL
47
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 6.14. 10-Bit ADC Window Interrupt Examples, Right Justified Data
Input Voltage
(AD0 - AGND)
Input Voltage
(AD0 - AGND)
ADC Data
Word
0x03FF
ADC Data
Word
0x03FF
REF x (1023/1024)
REF x (1023/1024)
ADWINT
ADWINT=1
not affected
0x0201
0x0201
REF x (512/1024)
REF x (256/1024)
0x0200
0x01FF
ADC0LTH:ADC0LTL
ADWINT=1
REF x (512/1024)
REF x (256/1024)
0x0200
0x01FF
ADC0GTH:ADC0GTL
ADWINT
not affected
0x0101
0x0100
0x0101
0x0100
ADC0GTH:ADC0GTL
ADC0LTH:ADC0LTL
ADWINT=1
0x00FF
0x00FF
ADWINT
not affected
0x0000
0x0000
0
0
Given:
Given:
AMX0SL = 0x00, AMX0CF = 0x00, ADLJST = 0,
ADC0LTH:ADC0LTL = 0x0200,
AMX0SL = 0x00, AMX0CF = 0x00, ADLJST = 0,
ADC0LTH:ADC0LTL = 0x0100,
ADC0GTH:ADC0GTL = 0x0100.
ADC0GTH:ADC0GTL = 0x0200.
An ADC End of Conversion will cause an ADC Window
Compare Interrupt (ADWINT=1) if the resulting ADC
Data Word is < 0x0200 and > 0x0100.
An ADC End of Conversion will cause an ADC Window
Compare Interrupt (ADWINT=1) if the resulting ADC
Data Word is < 0x0100 or > 0x0200.
Input Voltage
ADC Data
Input Voltage
ADC Data
(AD0 - AD1)
Word
(AD0 - AD1)
Word
REF x (511/512)
0x01FF
REF x (511/512)
0x01FF
ADWINT
ADWINT=1
not affected
0x0101
0x0101
REF x (256/512)
(-1/512)
0x0100
0x00FF
ADC0LTH:ADC0LTL
ADWINT=1
REF x (256/512)
REF x (-1/512)
0x0100
0x00FF
ADC0GTH:ADC0GTL
ADWINT
not affected
0x0000
0xFFFF
0x0000
0xFFFF
ADC0GTH:ADC0GTL
ADC0LTH:ADC0LTL
0xFFFE
0xFFFE
ADWINT=1
ADWINT
not affected
0xFE00
0xFE00
-REF
-REF
Given:
Given:
AMX0SL = 0x00, AMX0CF = 0x01, ADLJST = 0,
ADC0LTH:ADC0LTL = 0x0100,
AMX0SL = 0x00, AMX0CF = 0x01, ADLJST = 0,
ADC0LTH:ADC0LTH = 0xFFFF,
ADC0GTH:ADC0GTL = 0xFFFF.
ADC0GTH:ADC0GTL = 0x0100.
An ADC End of Conversion will cause an ADC Window
Compare Interrupt (ADWINT=1) if the resulting ADC
An ADC End of Conversion will cause an ADC Window
Compare Interrupt (ADWINT=1) if the resulting ADC
Data Word is < 0xFFFF or > 0x0100. (Two’s Complement
math, 0xFFFF = -1.)
Data Word is
<
0x0100 and
>
0xFFFF.
(Two’s
Complement math, 0xFFFF = -1.)
Rev. 1.7
48
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 6.15. 10-Bit ADC Window Interrupt Examples, Left Justified Data
Input Voltage
(AD0 - AGND)
Input Voltage
(AD0 - AGND)
ADC Data
Word
0xFFC0
ADC Data
Word
0xFFC0
REF x (1023/1024)
REF x (1023/1024)
ADWINT
ADWINT=1
not affected
0x8040
0x8040
REF x (512/1024)
REF x (256/1024)
0x8000
0x7FC0
ADC0LTH:ADC0LTL
ADWINT=1
REF x (512/1024)
REF x (256/1024)
0x8000
0x7FC0
ADC0GTH:ADC0GTL
ADWINT
not affected
0x4040
0x4000
0x4040
0x4000
ADC0GTH:ADC0GTL
ADC0LTH:ADC0LTL
0x3FC0
0x3FC0
ADWINT=1
ADWINT
not affected
0x0000
0x0000
0
0
Given:
Given:
AMX0SL = 0x00, AMX0CF = 0x00, ADLJST = 1,
ADC0LTH:ADC0LTL = 0x8000,
AMX0SL = 0x00, AMX0CF = 0x00, ADLJST = 1,
ADC0LTH:ADC0LTL = 0x4000,
ADC0GTH:ADC0GTL = 0x4000.
ADC0GTH:ADC0GTL = 0x8000.
An ADC End of Conversion will cause an ADC Window
Compare Interrupt (ADWINT=1) if the resulting ADC
Data Word is < 0x8000 and > 0x4000.
An ADC End of Conversion will cause an ADC Window
Compare Interrupt (ADWINT=1) if the resulting ADC
Data Word is < 0x4000 or > 0x8000.
Input Voltage
ADC Data
Input Voltage
ADC Data
(AD0 - AD1)
Word
(AD0 - AD1)
Word
REF x (511/512)
0x7FC0
REF x (511/512)
0x7FC0
ADWINT
ADWINT=1
not affected
0x2040
0x2040
REF x (128/512)
REF x (-1/512)
0x2000
0x1FC0
ADC0LTH:ADC0LTL
ADWINT=1
REF x (128/512)
REF x (-1/512)
0x2000
0x1FC0
ADC0GTH:ADC0GTL
ADWINT
not affected
0x0000
0xFFC0
0x0000
0xFFC0
ADC0GTH:ADC0GTL
ADC0LTH:ADC0LTL
ADWINT=1
0xFF80
0xFF80
ADWINT
not affected
0x8000
0x8000
-REF
-REF
Given:
Given:
AMX0SL = 0x00, AMX0CF = 0x01, ADLJST = 1,
ADC0LTH:ADC0LTL = 0x2000,
AMX0SL = 0x00, AMX0CF = 0x01, ADLJST = 1,
ADC0LTH:ADC0LTH = 0xFFC0,
ADC0GTH:ADC0GTL = 0xFFC0.
ADC0GTH:ADC0GTL = 0x2000.
An ADC End of Conversion will cause an ADC Window
Compare Interrupt (ADWINT=1) if the resulting ADC
An ADC End of Conversion will cause an ADC Window
Compare Interrupt (ADWINT=1) if the resulting ADC
Data Word is < 0xFFC0 or > 0x2000. (Two’s Complement
math.)
Data Word is
<
0x2000 and
>
0xFFC0.
(Two’s
Complement math.)
49
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Table 6.1. 10-Bit ADC Electrical Characteristics
VDD = 3.0V, AV+ = 3.0V, VREF = 2.40V (REFBE=0), PGA Gain = 1, -40°C to +85°C unless otherwise specified.
PARAMETER
DC ACCURACY
Resolution
CONDITIONS
MIN
TYP
MAX
UNITS
10
± ½
± ½
bits
LSB
LSB
LSB
LSB
Integral Nonlinearity
Differential Nonlinearity
Offset Error
± 1
± 1
Guaranteed Monotonic
Differential mode
± 0.5
-1.5 ±
0.5
Full Scale Error
Offset Temperature
Coefficient
± 0.25
ppm/°C
DYNAMIC PERFORMANCE (10kHz sine-wave input, 0 to –1dB of full scale, 100ksps)
Signal-to-Noise Plus
Distortion
59
61
dB
Total Harmonic Distortion
Spurious-Free Dynamic
Range
Up to the 5th harmonic
-70
80
dB
dB
CONVERSION RATE
Conversion Time in SAR
Clocks
16
clocks
SAR Clock Frequency
C8051F000, ‘F001, ‘F002
C8051F005, ‘F006, ‘F007
2.0
2.5
MHz
MHz
µs
Track/Hold Acquisition
Time
1.5
Throughput Rate
100
ksps
V
ANALOG INPUTS
Voltage Conversion Range
Single-ended Mode (AINn – AGND)
Differential Mode |(AINn+) – (AINm-)|
Any AINn pin
0
VREF
- 1LSB
AV+
Input Voltage
AGND
V
pF
Input Capacitance
TEMPERATURE SENSOR
Linearity
10
± 0.20
± 3
°C
°C
Absolute Accuracy
Gain
Gain Error (±1σ)
Offset
PGA Gain = 1
PGA Gain = 1
PGA Gain = 1, Temp = 0°C
PGA Gain = 1, Temp = 0°C
2.86
mV/°C
µV/°C
mV
± 33.5
776
mV
Offset Error (±1σ)
POWER SPECIFICATIONS
± 8.51
Power Supply Current (AV+ Operating Mode, 100ksps
supplied to ADC)
450
900
µA
Power Supply Rejection
mV/V
± 0.3
Rev. 1.7
50
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
7. DACs, 12 BIT VOLTAGE MODE
The C8051F000 MCU family has two 12-bit voltage-mode Digital to Analog Converters. Each DAC has an output
swing of 0V to VREF-1LSB for a corresponding input code range of 0x000 to 0xFFF. Using DAC0 as an example,
the 12-bit data word is written to the low byte (DAC0L) and high byte (DAC0H) data registers. Data is latched into
DAC0 after a write to the corresponding DAC0H register, so the write sequence should be DAC0L followed by
DAC0H if the full 12-bit resolution is required. The DAC can be used in 8-bit mode by initializing DAC0L to the
desired value (typically 0x00), and writing data to only DAC0H with the data shifted to the left. DAC0 Control
Register (DAC0CN) provides a means to enable/disable DAC0 and to modify its input data formatting.
The DAC0 enable/disable function is controlled by the DAC0EN bit (DAC0CN.7). Writing a 1 to DAC0EN
enables DAC0 while writing a 0 to DAC0EN disables DAC0. While disabled, the output of DAC0 is maintained in
a high-impedance state, and the DAC0 supply current falls to 1µA or less. Also, the Bias Enable bit (BIASE) in the
REF0CN register (see Figure 9.2) must be set to 1 in order to supply bias to DAC0. The voltage reference for
DAC0 must also be set properly (see Section 9).
In some instances, input data should be shifted prior to a DAC0 write operation to properly justify data within the
DAC input registers. This action would typically require one or more load and shift operations, adding software
overhead and slowing DAC throughput. To alleviate this problem, the data-formatting feature provides a means for
the user to program the orientation of the DAC0 data word within data registers DAC0H and DAC0L. The three
DAC0DF bits (DAC0CN.[2:0]) allow the user to specify one of five data word orientations as shown in the
DAC0CN register definition.
DAC1 is functionally the same as DAC0 described above. The electrical specifications for both DAC0 and DAC1
are given in Table 7.1.
Figure 7.1. DAC Functional Block Diagram
DAC0EN
REF
DAC0DF2
DAC0DF1
DAC0DF0
AV+
8
+
-
12
DAC0
DAC0
AGND
8
DAC1EN
REF
DAC1DF2
DAC1DF1
DAC1DF0
AV+
8
+
12
DAC1
DAC1
-
AGND
8
51
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 7.2. DAC0H: DAC0 High Byte Register
R/W
Bit7
R/W
Bit6
R/W
R/W
R/W
R/W
R/W
R/W
Bit0
Reset Value
00000000
SFR Address:
Bit5
Bit4
Bit3
Bit2
Bit1
0xD3
Bits7-0: DAC0 Data Word Most Significant Byte.
Figure 7.3. DAC0L: DAC0 Low Byte Register
R/W
Bit7
R/W
Bit6
R/W
R/W
R/W
R/W
R/W
R/W
Bit0
Reset Value
00000000
SFR Address:
Bit5
Bit4
Bit3
Bit2
Bit1
0xD2
Bits7-0: DAC0 Data Word Least Significant Byte.
Figure 7.4. DAC0CN: DAC0 Control Register
R/W
DAC0EN
Bit7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
DAC0DF2 DAC0DF1 DAC0DF0
-
-
-
-
00000000
SFR Address:
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0xD4
Bit7:
DAC0EN: DAC0 Enable Bit
0: DAC0 Disabled. DAC0 Output pin is disabled; DAC0 is in low power shutdown mode.
1: DAC0 Enabled. DAC0 Output is pin active; DAC0 is operational.
Bits6-3: UNUSED. Read = 0000b; Write = don’t care
Bits2-0: DAC0DF2-0: DAC0 Data Format Bits
000: The most significant nybble of the DAC0 Data Word is in DAC0H[3:0], while the least significant
byte is in DAC0L.
DAC0H
DAC0L
MSB
LSB
001: The most significant 5-bits of the DAC0 Data Word is in DAC0H[4:0], while the least significant
7-bits is in DAC0L[7:1].
DAC0H
DAC0L
LSB
010: The most sigMnSiBficant 6-bits of the DAC0 Data Word is in DAC0H[5:0], while the least significant
6-bits is in DAC0L[7:2].
DAC0H
DAC0L
011: The mMosSBt significant 7-bits of the DAC0 Data Word is in DAC0H[6:0], while the least significant
LSB
5-bits is in DAC0L[7:3].
DAC0H
DAC0L
1xx: The most significant byte of the DAC0 Data Word is in DAC0H, whLiSleB the least significant nybble
MSB
is in DAC0L[7:4].
DAC0H
DAC0L
MSB
LSB
Rev. 1.7
52
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 7.5. DAC1H: DAC1 High Byte Register
R/W
Bit7
R/W
Bit6
R/W
R/W
R/W
R/W
R/W
R/W
Bit0
Reset Value
00000000
SFR Address:
Bit5
Bit4
Bit3
Bit2
Bit1
0xD6
Bits7-0: DAC1 Data Word Most Significant Byte.
Figure 7.6. DAC1L: DAC1 Low Byte Register
R/W
Bit7
R/W
Bit6
R/W
R/W
R/W
R/W
R/W
R/W
Bit0
Reset Value
00000000
SFR Address:
Bit5
Bit4
Bit3
Bit2
Bit1
0xD5
Bits7-0: DAC1 Data Word Least Significant Byte.
Figure 7.7. DAC1CN: DAC1 Control Register
R/W
DAC1EN
Bit7
R/W
-
Bit6
R/W
-
R/W
-
R/W
-
R/W
R/W
R/W
Reset Value
DAC1DF2 DAC1DF1 DAC1DF0
00000000
SFR Address:
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0xD7
Bit7:
DAC1EN: DAC1 Enable Bit
0: DAC1 Disabled. DAC1 Output pin is disabled; DAC1 is in low power shutdown mode.
1: DAC1 Enabled. DAC1 Output is pin active; DAC1 is operational.
Bits6-3: UNUSED. Read = 0000b; Write = don’t care
Bits2-0: DAC1DF2-0: DAC1 Data Format Bits
000: The most significant nybble of the DAC1 Data Word is in DAC1H[3:0], while the least
significant byte is in DAC1L.
DAC1H
DAC1L
MSB
LSB
001: The most significant 5-bits of the DAC1 Data Word is in DAC1H[4:0], while the least
significant 7-bits is in DAC1L[7:1].
DAC1H
DAC1L
MSB
LSB
010: The most significant 6-bits of the DAC1 Data Word is in DAC1H[5:0], while the least
significant 6-bits is in DAC1L[7:2].
DAC1H
DAC1L
MSB
LSB
011: The most significant 7-bits of the DAC1 Data Word is in DAC1H[6:0], while the least
significant 5-bits is in DAC1L[7:3].
DAC1H
DAC1L
MSB
LSB
1xx: The most significant byte of the DAC1 Data Word is in DAC1H, while the least
significant nybble is in DAC1L[7:4].
DAC1H
DAC1L
MSB
LSB
53
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Table 7.1. DAC Electrical Characteristics
VDD = 3.0V, AV+ = 3.0V, REF = 2.40V (REFBE=0), No Output Load unless otherwise specified.
PARAMETER
STATIC PERFORMANCE
Resolution
CONDITIONS
MIN
TYP
MAX
UNITS
12
bits
LSB
LSB
Integral Nonlinearity
Differential Nonlinearity
For Data Word Range 0x014 to 0xFEB
Guaranteed Monotonic (codes 0x014 to
0xFEB)
±2
±1
Output Noise
No Output Filter
250
128
41
±3
6
±20
10
-60
µVrms
100kHz Output Filter
10kHz Output Filter
Data Word = 0x014
Offset Error
mV
ppm/°C
mV
ppm/°C
dB
±30
±60
Offset Tempco
Full-Scale Error
Full-Scale Error Tempco
VDD Power-Supply
Rejection Ratio
DACnEN=0
100
kΩ
Output Impedance in
Shutdown Mode
±300
µA
Output Current
Data Word = 0xFFF
15
mA
Output Short Circuit Current
DYNAMIC PERFORMANCE
Voltage Output Slew Rate
Output Settling Time To ½
LSB
Load = 40pF
0.44
10
V/µs
µs
Load = 40pF, Output swing from code
0xFFF to 0x014
Output Voltage Swing
0
REF-
1LSB
V
µs
Startup Time
ANALOG OUTPUTS
Load Regulation
DAC Enable asserted
10
60
IL = 0.01mA to 0.3mA at code 0xFFF
ppm
µA
CURRENT CONSUMPTION (each DAC)
Power Supply Current (AV+ Data Word = 0x7FF
supplied to DAC)
110
400
Rev. 1.7
54
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
8. COMPARATORS
The MCU family has two on-chip analog voltage comparators as shown in Figure 8.1. The inputs of each
Comparator are available at the package pins. The output of each comparator is optionally available at the package
pins via the I/O crossbar (see Section 15.1). When assigned to package pins, each comparator output can be
programmed to operate in open drain or push-pull modes (see section 15.3).
The hysteresis of each comparator is software-programmable via its respective Comparator control register
(CPT0CN, CPT1CN). The user can program both the amount of hysteresis voltage (referred to the input voltage)
and the positive and negative-going symmetry of this hysteresis around the threshold voltage. The output of the
comparator can be polled in software, or can be used as an interrupt source. Each comparator can be individually
enabled or disabled (shutdown). When disabled, the comparator output (if assigned to a Port I/O pin via the
Crossbar) defaults to the logic low state, its interrupt capability is suspended and its supply current falls to less than
1µA. Comparator 0 inputs can be externally driven from -0.25V to (AV+) + 0.25V without damage or upset.
The Comparator 0 hysteresis is programmed using bits 3-0 in the Comparator 0 Control Register CPT0CN (shown
in Figure 8.3). The amount of negative hysteresis voltage is determined by the settings of the CP0HYN bits. As
shown in Figure 8.2, settings of 10, 4 or 2mV of negative hysteresis can be programmed, or negative hysteresis can
be disabled. In a similar way, the amount of positive hysteresis is determined by the setting the CP0HYP bits.
Comparator interrupts can be generated on both rising-edge and falling-edge output transitions. (For Interrupt
enable and priority control, see Section 10.4). The CP0FIF flag is set upon a Comparator 0 falling-edge interrupt,
and the CP0RIF flag is set upon the Comparator 0 rising-edge interrupt. Once set, these bits remain set until cleared
by the CPU. The Output State of Comparator 0 can be obtained at any time by reading the CP0OUT bit. Note the
comparator output and interrupt should be ignored until the comparator settles after power-up. Comparator 0 is
enabled by setting the CP0EN bit, and is disabled by clearing this bit. Note there is a 20usec settling time for the
comparator output to stabilize after setting the CP0EN bit or a power-up. Comparator 0 can also be programmed as
a reset source. For details, see Section 13.
The operation of Comparator 1 is identical to that of Comparator 0, except the Comparator 1 is controlled by the
CPT1CN Register (Figure 8.4). Comparator 1 can not be programmed as a reset source. Also, the input pins for
Comparator 1 are not pinned out on the F002, F007, F012, or F017 devices. The complete electrical specifications
for the Comparators are given in Table 8.1.
Figure 8.1. Comparator Functional Block Diagram
CP0EN
CP0OUT
CP0RIF
CP0FIF
AV+
CP0HYP1
CP0HYP0
CP0HYN1
CP0HYN0
Reset
Decision
Tree
CP0+
CP0-
+
-
SET
SET
CLR
D
Q
Q
D
Q
Q
Crossbar
CLR
Interrupt
Handler
(SYNCHRONIZER)
AGND
CP1EN
CP1OUT
CP1RIF
AV+
CP1FIF
CP1HYP1
CP1HYP0
CP1HYN1
CP1HYN0
CP1+
CP1-
+
-
SET
CLR
SET
CLR
D
Q
Q
D
Q
Q
Crossbar
Interrupt
Handler
not available on F002,
F007, F012, and F017
(SYNCHRONIZER)
AGND
55
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 8.2. Comparator Hysteresis Plot
CP0+
CP0-
VIN+
VIN-
+
CP0
OUT
_
CIRCUIT CONFIGURATION
Positive Hysteresis Voltage
(Programmed with CP0HYSP Bits)
VIN-
Negative Hysteresis Voltage
INPUTS
(Programmed by CP0HYSN Bits)
VIN+
VOH
OUTPUT
VOL
Negative Hysteresis
Disabled
Maximum
Negative Hysteresis
Positive Hysteresis
Disabled
Maximum
Positive Hysteresis
Rev. 1.7
56
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 8.3. CPT0CN: Comparator 0 Control Register
R/W
CP0EN
Bit7
R
R/W
CP0RIF
Bit5
R/W
CP0FIF
Bit4
R/W
CP0HYP1
Bit3
R/W
R/W
R/W
Reset Value
CP0OUT
CP0HYP0 CP0HYN1 CP0HYN0
00000000
SFR Address:
Bit6
Bit2
Bit1
Bit0
0x9E
Bit7:
Bit6:
Bit5:
Bit4:
CP0EN: Comparator 0 Enable Bit
0: Comparator 0 Disabled.
1: Comparator 0 Enabled.
CP0OUT: Comparator 0 Output State Flag
0: Voltage on CP0+ < CP0-
1: Voltage on CP0+ > CP0-
CP0RIF: Comparator 0 Rising-Edge Interrupt Flag
0: No Comparator 0 Rising-Edge Interrupt has occurred since this flag was cleared
1: Comparator 0 Rising-Edge Interrupt has occurred since this flag was cleared
CP0FIF: Comparator 0 Falling-Edge Interrupt Flag
0: No Comparator 0 Falling-Edge Interrupt has occurred since this flag was cleared
1: Comparator 0 Falling-Edge Interrupt has occurred since this flag was cleared
Bit3-2: CP0HYP1-0: Comparator 0 Positive Hysteresis Control Bits
00: Positive Hysteresis Disabled
01: Positive Hysteresis = 2mV
10: Positive Hysteresis = 4mV
11: Positive Hysteresis = 10mV
Bit1-0: CP0HYN1-0: Comparator 0 Negative Hysteresis Control Bits
00: Negative Hysteresis Disabled
01: Negative Hysteresis = 2mV
10: Negative Hysteresis = 4mV
11: Negative Hysteresis = 10mV
57
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 8.4. CPT1CN: Comparator 1 Control Register
R/W
CP1EN
Bit7
R
R/W
CP1RIF
Bit5
R/W
CP1FIF
Bit4
R/W
CP1HYP1
Bit3
R/W
R/W
R/W
Reset Value
CP1OUT
CP1HYP0 CP1HYN1 CP1HYN0
00000000
SFR Address:
Bit6
Bit2
Bit1
Bit0
0x9F
Bit7:
Bit6:
Bit5:
Bit4:
CP1EN: Comparator 1 Enable Bit
0: Comparator 1 Disabled.
1: Comparator 1 Enabled.
CP1OUT: Comparator 1 Output State Flag
0: Voltage on CP1+ < CP1-
1: Voltage on CP1+ > CP1-
CP1RIF: Comparator 1 Rising-Edge Interrupt Flag
0: No Comparator 1 Rising-Edge Interrupt has occurred since this flag was cleared
1: Comparator 1 Rising-Edge Interrupt has occurred since this flag was cleared
CP1FIF: Comparator 1 Falling-Edge Interrupt Flag
0: No Comparator 1 Falling-Edge Interrupt has occurred since this flag was cleared
1: Comparator 1 Falling-Edge Interrupt has occurred since this flag was cleared
Bit3-2: CP1HYP1-0: Comparator 1 Positive Hysteresis Control Bits
00: Positive Hysteresis Disabled
01: Positive Hysteresis = 2mV
10: Positive Hysteresis = 4mV
11: Positive Hysteresis = 10mV
Bit1-0: CP1HYN1-0: Comparator 1 Negative Hysteresis Control Bits
00: Negative Hysteresis Disabled
01: Negative Hysteresis = 2mV
10: Negative Hysteresis = 4mV
11: Negative Hysteresis = 10mV
Rev. 1.7
58
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Table 8.1. Comparator Electrical Characteristics
VDD = 3.0V, AV+ = 3.0V, -40°C to +85°C unless otherwise specified.
PARAMETER
CONDITIONS
(CP+) – (CP-) = 100mV (Note 1)
(CP+) – (CP-) = 10mV (Note 1)
MIN
TYP
4
MAX
UNITS
µs
Response Time1
Response Time2
12
µs
Common Mode Rejection
1.5
4
mV/V
Ratio
Positive Hysteresis1
Positive Hysteresis2
Positive Hysteresis3
Positive Hysteresis4
Negative Hysteresis1
Negative Hysteresis2
Negative Hysteresis3
Negative Hysteresis4
Inverting or Non-inverting
Input Voltage Range
Input Capacitance
Input Bias Current
Input Offset Voltage
POWER SUPPLY
Power-up Time
CPnHYP1-0 = 00
CPnHYP1-0 = 01
CPnHYP1-0 = 10
CPnHYP1-0 = 11
CPnHYN1-0 = 00
CPnHYN1-0 = 01
CPnHYN1-0 = 10
CPnHYN1-0 = 11
0
4.5
9
1
7
mV
mV
mV
mV
mV
mV
mV
mV
V
2
4
10
13
17
0
25
1
2
4
4.5
9
7
13
10
17
25
-0.25
(AV+)
+ 0.25
7
pF
nA
mV
-5
-10
0.001
+5
+10
CPnEN from 0 to 1
20
0.1
1.5
µs
mV/V
µA
Power Supply Rejection
Supply Current
1
10
Operating Mode (each comparator) at DC
Note 1: CPnHYP1-0 = CPnHYN1-0 = 00.
59
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
9. VOLTAGE REFERENCE
The voltage reference circuit consists of a 1.2V, 15ppm/°C (typical) bandgap voltage reference generator and a
gain-of-two output buffer amplifier. The reference voltage on VREF can be connected to external devices in the
system, as long as the maximum load seen by the VREF pin is less than 200µA to AGND (see Figure 9.1).
If a different reference voltage is required, an external reference can be connected to the VREF pin and the internal
bandgap and buffer amplifier disabled in software. The external reference voltage must still be less than AV+ -
0.3V. The Reference Control Register, REF0CN (defined in Figure 9.2), provides the means to enable or disable
the bandgap and buffer amplifier. The BIASE bit in REF0CN enables the bias circuitry for the ADC and DACs
while the REFBE bit enables the bandgap reference and buffer amplifier which drive the VREF pin. When
disabled, the supply current drawn by the bandgap and buffer amplifier falls to less than 1uA (typical) and the
output of the buffer amplifier enters a high impedance state. If the internal bandgap is used as the reference voltage
generator, BIASE and REFBE must both be set to 1. If an external reference is used, REFBE must be set to 0 and
BIASE must be set to 1. If neither the ADC nor the DAC are being used, both of these bits can be set to 0 to
conserve power. The electrical specifications for the Voltage Reference are given in Table 9.1.
The temperature sensor connects to the highest order input of the A/D converter’s input multiplexer (see Figure 5.1
and Figure 5.5 for details). The TEMPE bit within REF0CN enables and disables the temperature sensor. While
disabled, the temperature sensor defaults to a high impedance state and any A/D measurements performed on the
sensor while disabled result in meaningless data.
Figure 9.1. Voltage Reference Functional Block Diagram
AV+
External
Voltage
EN
Temp
(to Analog Mux)
Sensor
Reference
Circuit
R1
EN
(Bias to ADC
and DAC)
Bias
TEMPE
BIASE
Generator
REFBE
AGND
AGND
VREF
EN
2.4V
(to ADC
Reference
and DAC)
External Equivalent
Load Circuit
AGND
RLOAD
AGND
Rev. 1.7
60
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 9.2. REF0CN: Reference Control Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
-
-
-
-
-
TEMPE
BIASE
REFBE
00000000
SFR Address:
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0xD1
Bits7-3: UNUSED. Read = 00000b; Write = don’t care
Bit2:
Bit1:
Bit0:
TEMPE: Temperature Sensor Enable Bit
0: Internal Temperature Sensor Off.
1: Internal Temperature Sensor On.
BIASE: Bias Enable Bit for ADC and DAC’s
0: Internal Bias Off.
1: Internal Bias On (required for use of ADC or DAC’s).
REFBE: Internal Voltage Reference Buffer Enable Bit
0: Internal Reference Buffer Off. System reference can be driven from external source on
VREF pin.
1: Internal Reference Buffer On. System reference provided by internal voltage reference.
Table 9.1. Reference Electrical Characteristics
VDD = 3.0V, AV+ = 3.0V, -40°C to +85°C unless otherwise specified.
PARAMETER
CONDITIONS
MIN
TYP
2.43
50
MAX
UNITS
INTERNAL REFERENCE (REFBE = 1)
Output Voltage
2.34
2.50
30
V
mA
µA
25°C ambient
VREF Short Circuit Current
VREF Power Supply
Current (supplied by AV+)
VREF Temperature
Coefficient
15
ppm/°C
Load Regulation
0.5
2
20
10
Load = (0-to-200µA) to AGND (Note 1)
4.7µF tantalum, 0.1µF ceramic bypass
0.1µF ceramic bypass
ppm/µA
ms
VREF Turn-on Time1
VREF Turn-on Time2
VREF Turn-on Time3
µs
µs
no bypass cap
EXTERNAL REFERENCE (REFBE = 0)
Input Voltage Range
1.00
(AV+)
– 0.3V
1
V
Input Current
0
µA
Note 1: The reference can only source current. When driving an external load, it is recommended to add a load
resistor to AGND.
61
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
10. CIP-51 CPU
The MCUs’ system CPU is the CIP-51. The CIP-51 is fully compatible with the MCS-51TM instruction set.
Standard 803x/805x assemblers and compilers can be used to develop software. The MCU family has a superset of
all the peripherals included with a standard 8051. Included are four 16-bit counter/timers (see description in Section
19), a full-duplex UART (see description in Section 18), 256 bytes of internal RAM, 128 byte Special Function
Register (SFR) address space (see Section 10.3), and four byte-wide I/O Ports (see description in Section 14). The
CIP-51 also includes on-chip debug hardware (see description in Section 21), and interfaces directly with the
MCUs’ analog and digital subsystems providing a complete data acquisition or control-system solution in a single
integrated circuit.
Features
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as additional
custom peripherals and functions to extend its capability (see Figure 10.1 for a block diagram). The CIP-51
includes the following features:
-
-
-
-
-
Fully Compatible with MCS-51 Instruction Set
25 MIPS Peak Throughput with 25MHz Clock
0 to 25MHz Clock Frequency (on ‘F0x5/6/7)
Four Byte-Wide I/O Ports
-
-
-
-
Reset Input
Power Management Modes
On-chip Debug Circuitry
Program and Data Memory Security
Extended Interrupt Handler
Figure 10.1. CIP-51 Block Diagram
DATA BUS
ACCUMULATOR
B REGISTER
STACK POINTER
TMP1
TMP2
SRAM
SRAM
PSW
ADDRESS
REGISTER
(256 X 8)
ALU
DATA BUS
SFR_ADDRESS
D8
BUFFER
SFR_CONTROL
SFR_WRITE_DATA
SFR_READ_DATA
SFR
BUS
D8
D8
DATA POINTER
INTERFACE
PC INCREMENTER
D8
MEM_ADDRESS
MEM_CONTROL
PROGRAM COUNTER (PC)
PRGM. ADDRESS REG.
PIPELINE
MEMORY
A16
D8
MEM_WRITE_DATA
MEM_READ_DATA
INTERFACE
CONTROL
LOGIC
RESET
CLOCK
SYSTEM_IRQs
INTERRUPT
INTERFACE
EMULATION_IRQ
D8
STOP
IDLE
POWER CONTROL
REGISTER
D8
Rev. 1.7
62
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Performance
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051
architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to
execute, and usually have a maximum system clock of 12MHz. By contrast, the CIP-51 core executes 70% of its
instructions in one or two system clock cycles, with no instructions taking more than eight system clock cycles.
With the CIP-51’s maximum system clock at 25MHz, it has a peak throughput of 25MIPS. The CIP-51 has a total
of 109 instructions. The number of instructions versus the system clock cycles required to execute them is as
follows:
26
1
50
2
5
2/3
14
3
7
3/4
3
4
1
4/5
2
5
1
8
Instructions
Clocks to Execute
Programming and Debugging Support
A JTAG-based serial interface is provided for in-system programming of the Flash program memory and
communication with on-chip debug support circuitry. The reprogrammable Flash can also be read and changed a
single byte at a time by the application software using the MOVC and MOVX instructions. This feature allows
program memory to be used for non-volatile data storage as well as updating program code under software control.
The on-chip debug support circuitry facilitates full speed in-circuit debugging, allowing the setting of hardware
breakpoints and watch points, starting, stopping and single stepping through program execution (including interrupt
service routines), examination of the program’s call stack, and reading/writing the contents of registers and memory.
This method of on-chip debugging is completely non-intrusive and non-invasive, requiring no RAM, Stack, timers,
or other on-chip resources.
The CIP-51 is supported by development tools from Silicon Laboratories and third party vendors. Silicon Labs
provides an integrated development environment (IDE) including editor, macro assembler, debugger and
programmer. The IDE’s debugger and programmer interface to the CIP-51 via its JTAG interface to provide fast
and efficient in-system device programming and debugging. Third party macro assemblers and C compilers are also
available.
10.1. INSTRUCTION SET
The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ instruction set.
Standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51 instructions are the
binary and functional equivalent of their MCS-51™ counterparts, including opcodes, addressing modes and effect
on PSW flags. However, instruction timing is different than that of the standard 8051.
10.1.1. Instruction and CPU Timing
In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with machine cycles
varying from 2 to 12 clock cycles in length. However, the CIP-51 implementation is based solely on clock cycle
timing. All instruction timings are specified in terms of clock cycles.
Due to the pipelined architecture of the CIP-51, most instructions execute in the same number of clock cycles as
there are program bytes in the instruction. Conditional branch instructions take one less clock cycle to complete
when the branch is not taken as opposed to when the branch is taken. Table 10.1 is the CIP-51 Instruction Set
Summary, which includes the mnemonic, number of bytes, and number of clock cycles for each instruction.
10.1.2. MOVX Instruction and Program Memory
The MOVX instruction is typically used to access external data memory. In the CIP-51, the MOVX instruction can
access the on-chip program memory space implemented as reprogrammable Flash memory using the control bits in
the PSCTL register (see Figure 11.1). This feature provides a mechanism for the CIP-51 to update program code
and use the program memory space for non-volatile data storage. For the products with RAM mapped into external
data memory space (C8051F005/06/07/15/16/17), MOVX is still used to read/write this memory with the PSCTL
63
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
register configured for accessing the external data memory space. Refer to Section 11 (Flash Memory) for further
details.
Rev. 1.7
64
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Table 10.1. CIP-51 Instruction Set Summary
Clock
Mnemonic
Description
Bytes
Cycles
ARITHMETIC OPERATIONS
ADD A,Rn
ADD A,direct
ADD A,@Ri
ADD A,#data
ADDC A,Rn
ADDC A,direct
ADDC A,@Ri
ADDC A,#data
SUBB A,Rn
SUBB A,direct
SUBB A,@Ri
SUBB A,#data
INC A
Add register to A
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
1
1
2
1
1
1
1
1
1
2
2
2
1
2
2
2
1
2
2
2
1
1
2
2
1
1
2
2
1
4
8
1
Add direct byte to A
Add indirect RAM to A
Add immediate to A
Add register to A with carry
Add direct byte to A with carry
Add indirect RAM to A with carry
Add immediate to A with carry
Subtract register from A with borrow
Subtract direct byte from A with borrow
Subtract indirect RAM from A with borrow
Subtract immediate from A with borrow
Increment A
INC Rn
Increment register
INC direct
INC @Ri
Increment direct byte
Increment indirect RAM
Decrement A
DEC A
DEC Rn
Decrement register
DEC direct
DEC @Ri
Decrement direct byte
Decrement indirect RAM
Increment Data Pointer
Multiply A and B
INC DPTR
MUL AB
DIV AB
Divide A by B
Decimal Adjust A
DA A
LOGICAL OPERATIONS
AND Register to A
ANL A,Rn
ANL A,direct
ANL A,@Ri
ANL A,#data
ANL direct,A
ANL direct,#data
ORL A,Rn
ORL A,direct
ORL A,@Ri
ORL A,#data
ORL direct,A
ORL direct,#data
XRL A,Rn
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
2
3
1
1
1
1
1
1
2
2
2
2
3
1
2
2
2
2
3
1
2
2
2
2
3
1
1
1
1
1
AND direct byte to A
AND indirect RAM to A
AND immediate to A
AND A to direct byte
AND immediate to direct byte
OR Register to A
OR direct byte to A
OR indirect RAM to A
OR immediate to A
OR A to direct byte
OR immediate to direct byte
Exclusive-OR Register to A
Exclusive-OR direct byte to A
Exclusive-OR indirect RAM to A
Exclusive-OR immediate to A
Exclusive-OR A to direct byte
Exclusive-OR immediate to direct byte
Clear A
XRL A,direct
XRL A,@Ri
XRL A,#data
XRL direct,A
XRL direct,#data
CLR A
CPL A
Complement A
Rotate A left
Rotate A left through carry
Rotate A right
RL A
RLC A
RR A
65
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Clock
Bytes
Mnemonic
Description
Cycles
RRC A
Rotate A right through carry
Swap nibbles of A
1
1
1
SWAP A
1
DATA TRANSFER
MOV A,Rn
Move register to A
1
2
1
2
1
2
2
2
2
3
2
3
1
2
2
3
1
1
1
1
1
1
2
2
1
2
1
1
1
2
2
2
1
2
2
2
2
3
2
3
2
2
2
3
3
3
3
3
3
3
2
2
1
2
2
2
MOV A,direct
MOV A,@Ri
Move direct byte to A
Move indirect RAM to A
Move immediate to A
MOV A,#data
MOV Rn,A
Move A to register
MOV Rn,direct
MOV Rn,#data
MOV direct,A
MOV direct,Rn
MOV direct,direct
MOV direct,@Ri
MOV direct,#data
MOV @Ri,A
Move direct byte to register
Move immediate to register
Move A to direct byte
Move register to direct byte
Move direct byte to direct
Move indirect RAM to direct byte
Move immediate to direct byte
Move A to indirect RAM
Move direct byte to indirect RAM
Move immediate to indirect RAM
Load data pointer with 16-bit constant
Move code byte relative DPTR to A
Move code byte relative PC to A
Move external data (8-bit address) to A
Move A to external data (8-bit address)
Move external data (16-bit address) to A
Move A to external data (16-bit address)
Push direct byte onto stack
Pop direct byte from stack
Exchange register with A
Exchange direct byte with A
Exchange indirect RAM with A
Exchange low nibble of indirect RAM with A
BOOLEAN MANIPULATION
Clear carry
MOV @Ri,direct
MOV @Ri,#data
MOV DPTR,#data16
MOVC A,@A+DPTR
MOVC A,@A+PC
MOVX A,@Ri
MOVX @Ri,A
MOVX A,@DPTR
MOVX @DPTR,A
PUSH direct
POP direct
XCH A,Rn
XCH A,direct
XCH A,@Ri
XCHD A,@Ri
CLR C
1
2
1
2
1
2
2
2
2
2
2
2
2
2
3
3
3
1
2
CLR bit
Clear direct bit
SETB C
Set carry
1
SETB bit
CPL C
Set direct bit
2
Complement carry
1
CPL bit
Complement direct bit
2
ANL C,bit
ANL C,/bit
ORL C,bit
ORL C,/bit
MOV C,bit
MOV bit,C
JC rel
AND direct bit to carry
2
AND complement of direct bit to carry
OR direct bit to carry
2
2
OR complement of direct bit to carry
Move direct bit to carry
2
2
Move carry to direct bit
2
Jump if carry is set
2/3
2/3
3/4
3/4
3/4
JNC rel
Jump if carry not set
JB bit,rel
JNB bit,rel
JBC bit,rel
Jump if direct bit is set
Jump if direct bit is not set
Jump if direct bit is set and clear bit
PROGRAM BRANCHING
Rev. 1.7
66
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Clock
Mnemonic
Description
Bytes
Cycles
ACALL addr11
LCALL addr16
RET
Absolute subroutine call
Long subroutine call
Return from subroutine
Return from interrupt
Absolute jump
2
3
1
1
2
3
4
5
5
3
RETI
AJMP addr11
LJMP addr16
Long jump
3
2
1
2
2
3
3
4
SJMP rel
Short jump (relative address)
Jump indirect relative to DPTR
Jump if A equals zero
3
JMP @A+DPTR
JZ rel
3
2/3
2/3
3/4
3/4
JNZ rel
Jump if A does not equal zero
Compare direct byte to A and jump if not equal
Compare immediate to A and jump if not equal
CJNE A,direct,rel
CJNE A,#data,rel
CJNE Rn,#data,rel
Compare immediate to register and jump if not
3
3/4
equal
CJNE @Ri,#data,rel
Compare immediate to indirect and jump if not
equal
Decrement register and jump if not zero
Decrement direct byte and jump if not zero
No operation
3
4/5
DJNZ Rn,rel
DJNZ direct,rel
NOP
2
3
1
2/3
3/4
1
Notes on Registers, Operands and Addressing Modes:
Rn - Register R0-R7 of the currently selected register bank.
@Ri - Data RAM location addressed indirectly through register R0-R1
rel - 8-bit, signed (two’s compliment) offset relative to the first byte of the following instruction. Used by SJMP
and all conditional jumps.
direct - 8-bit internal data location’s address. This could be a direct-access Data RAM location (0x00-0x7F) or an
SFR (0x80-0xFF).
#data - 8-bit constant
#data 16 - 16-bit constant
bit - Direct-addressed bit in Data RAM or SFR.
addr 11 - 11-bit destination address used by ACALL and AJMP. The destination must be within the same 2K-
byte page of program memory as the first byte of the following instruction.
addr 16 - 16-bit destination address used by LCALL and LJMP. The destination may be anywhere within the
64K-byte program memory space.
There is one unused opcode (0xA5) that performs the same function as NOP.
All mnemonics copyrighted © Intel Corporation 1980.
67
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
10.2. MEMORY ORGANIZATION
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two
separate memory spaces: program memory and data memory. Program and data memory share the same address
space but are accessed via different instruction types. There are 256 bytes of internal data memory and 64K bytes of
internal program memory address space implemented within the CIP-51. The CIP-51 memory organization is
shown in Figure 10.2.
10.2.1. Program Memory
The CIP-51 has a 64K-byte program memory space. The MCU implements 32896 bytes of this program memory
space as in-system, reprogrammable Flash memory, organized in a contiguous block from addresses 0x0000 to
0x807F. Note: 512 bytes (0x7E00 – 0x7FFF) of this memory are reserved for factory use and are not available for
user program storage.
Program memory is normally assumed to be read-only. However, the CIP-51 can write to program memory by
setting the Program Store Write Enable bit (PSCTL.0) and using the MOVX instruction. This feature provides a
mechanism for the CIP-51 to update program code and use the program memory space for non-volatile data storage.
Refer to Section 11 (Flash Memory) for further details.
10.2.2. Data Memory
The CIP-51 implements 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF.
The lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either direct
or indirect addressing may be used to access the lower 128 bytes of data memory. Locations 0x00 through 0x1F are
addressable as four banks of general purpose registers, each bank consisting of eight byte-wide registers. The next
16 bytes, locations 0x20 through 0x2F, may be addressed as bytes or as 128 bit locations accessible with the direct-
bit addressing mode.
The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the same
address space as the Special Function Registers (SFR) but is physically separate from the SFR space. The
addressing mode used by an instruction when accessing locations above 0x7F determines whether the CPU accesses
the upper 128 bytes of data memory space or the SFRs. Instructions that use direct addressing will access the SFR
space. Instructions using indirect addressing above 0x7F will access the upper 128 bytes of data memory. Figure
10.2 illustrates the data memory organization of the CIP-51.
The C8051F005/06/07/15/16/17 also have 2048 bytes of RAM in the external data memory space of the CIP-51,
accessible using the MOVX instruction. Refer to Section 12 (External RAM) for details.
10.2.3. General Purpose Registers
The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of general-
purpose registers. Each bank consists of eight byte-wide registers designated R0 through R7. Only one of these
banks may be enabled at a time. Two bits in the program status word, RS0 (PSW.3) and RS1 (PSW.4), select the
active register bank (see description of the PSW in Figure 10.6). This allows fast context switching when entering
subroutines and interrupt service routines. Indirect addressing modes use registers R0 and R1 as index registers.
10.2.4. Bit Addressable Locations
In addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20 through
0x2F are also accessible as 128 individually addressable bits. Each bit has a bit address from 0x00 to 0x7F. Bit 0
of the byte at 0x20 has bit address 0x00 while bit 7 of the byte at 0x20 has bit address 0x07. Bit 7 of the byte at
0x2F has bit address 0x7F. A bit access is distinguished from a full byte access by the type of instruction used (bit
source or destination operands as opposed to a byte source or destination).
The MCS-51™ assembly language allows an alternate notation for bit addressing of the form XX.Bwhere XXis the
byte address and Bis the bit position within the byte. For example, the instruction:
MOV
C, 22h.3
moves the Boolean value at 0x13 (bit 3 of the byte at location 0x22) into the user Carry flag.
Rev. 1.7
68
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 10.2. Memory Map
PROGRAM MEMORY
DATA MEMORY
INTERNAL DATA ADDRESS SPACE
0x807F
0x8000
0x7FFF
0x7E00
128 Byte ISP FLASH
0xFF
Upper 128 RAM
(Indirect Addressing
Only)
Special Function
Register's
RESERVED
(Direct Addressing Only)
0x80
0x7F
0x7DFF
(Direct and Indirect
Addressing)
Lower 128 RAM
(Direct and Indirect
Addressing)
FLASH
0x30
0x2F
Bit Addressable
(In-System
Programmable in 512
Byte Sectors)
0x20
0x1F
General Purpose
Registers
0x00
0x0000
EXTERNAL DATA ADDRESS SPACE
0xFFFF
0xF800
(same 2048 byte RAM block )
The same 2048 byte RAM
0x17FF
0x1000
0x0FFF
0x0800
0x07FF
(same 2048 byte RAM block )
(same 2048 byte RAM block )
block can be addressed on
2k boundaries throughout
the 64k External Data
Memory space.
RAM - 2048 Bytes
(accessable using MOVX
command)
0x0000
10.2.5. Stack
A programmer’s stack can be located anywhere in the 256-byte data memory. The stack area is designated using
the Stack Pointer (SP, 0x81) SFR. The SP will point to the last location used. The next value pushed on the stack is
placed at SP+1 and then SP is incremented. A reset initializes the stack pointer to location 0x07. Therefore, the
first value pushed on the stack is placed at location 0x08, which is also the first register (R0) of register bank 1.
Thus, if more than one register bank is to be used, the SP should be initialized to a location in the data memory not
being used for data storage. The stack depth can extend up to 256 bytes.
The MCUs also have built-in hardware for a stack record. The stack record is a 32-bit shift register, where each
Push or increment SP pushes one record bit onto the register, and each Call or interrupt pushes two record bits onto
the register. (A Pop or decrement SP pops one record bit, and a Return pops two record bits, also.) The stack
record circuitry can also detect an overflow or underflow on the Stack, and can notify the debug software even with
the MCU running full-speed debug.
69
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
10.3.
SPECIAL FUNCTION REGISTERS
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFRs). The
SFRs provide control and data exchange with the CIP-51’s resources and peripherals. The CIP-51 duplicates the
SFRs found in a typical 8051 implementation as well as implementing additional SFRs used to configure and access
the sub-systems unique to the MCU. This allows the addition of new functionality while retaining compatibility
with the MCS-51™ instruction set. Table 10.3 lists the SFRs implemented in the CIP-51 System Controller.
The SFR registers are accessed any time the direct addressing mode is used to access memory locations from 0x80
to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, P1, SCON, IE, etc.) are bit-addressable as well
as byte-addressable. All other SFRs are byte-addressable only. Unoccupied addresses in the SFR space are
reserved for future use. Accessing these areas will have an indeterminate effect and should be avoided. Refer to the
corresponding pages of the datasheet, as indicated in Table 10.3, for a detailed description of each register.
Table 10.2. Special Function Register Memory Map
SPI0CN
B
PCA0H
PCA0CPH0
PCA0CPH1
PCA0CPH2
PCA0CPH3
PCA0CPH4
EIP1
PCA0CPL4
EIE1
PCA0CPM4
DAC1H
WDTCN
EIP2
RSTSRC
EIE2
F8
F0
E8
E0
D8
D0
C8
C0
B8
B0
A8
A0
98
ADC0CN
ACC
PCA0CN
PSW
T2CON
SMB0CN
IP
P3
IE
P2
SCON
P1
PCA0L
XBR0
PCA0MD
REF0CN
PCA0CPL0
XBR1
PCA0CPM0
DAC0L
RCAP2L
SMB0DAT
AMX0CF
OSCICN
PCA0CPL1
XBR2
PCA0CPM1
DAC0H
RCAP2H
SMB0ADR
AMX0SL
PCA0CPL2
PCA0CPL3
PCA0CPM2
DAC0CN
TL2
ADC0GTL
ADC0CF
PCA0CPM3
DAC1L
TH2
DAC1CN
SMB0CR
ADC0LTH
ADC0H
FLACL***
EMI0CN***
PRT3CF
SMB0STA
OSCXCN
ADC0GTH
ADC0LTL
ADC0L
FLSCL
PRT1IF
PRT1CF
SPI0CKR
TMR3H
TH1
PRT0CF
PRT2CF
CPT0CN
SBUF
TMR3CN
TMOD
SP
SPI0CFG
TMR3RLL
TL0
SPI0DAT
TMR3RLH
TL1
CPT1CN
TMR3L
TH0
90
TCON
P0
CKCON
PSCTL
PCON
7(F)
88
80
DPL
DPH
0(8)
1(9)
2(A)
3(B)
4(C)
5(D)
6(E)
Bit Addressable
Table 10.3. Special Function Registers
SFRs are listed in alphabetical order. All undefined SFR locations are reserved.
* Refers to a register in the C8051F000/1/2/5/6/7 only.
** Refers to a register in the C8051F010/1/2/5/6/7 only.
*** Refers to a register in the C8051F005/06/07/15/16/17 only.
Description
Page No.
Address Register
0xE0
0xBC
0xE8
0xC5
0xC4
0xBF
0xBE
ACC
Accumulator
ADC Configuration
ADC Control
ADC Greater-Than Data Word (High Byte)
ADC Greater-Than Data Word (Low Byte)
ADC Data Word (High Byte)
ADC Data Word (Low Byte)
76
ADC0CF
ADC0CN
ADC0GTH
ADC0GTL
ADC0H
ADC0L
33*, 42**
34*, 45**
36*, 47**
36*, 47**
35*, 46**
35*, 46**
Rev. 1.7
70
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Description
Page No.
Address Register
0xC7
0xC6
0xBA
0xBB
0xF0
0x8E
0x9E
0x9F
0xD4
0xD3
0xD2
0xD7
0xD6
0xD5
0x83
0x82
0xE6
0xE7
0xF6
0xF7
0xAF
0xB7
0xB6
0xA8
0xB8
0xB2
0xB1
0x80
0x90
0xA0
0xB0
0xD8
0xFA
0xFB
0xFC
0xFD
0xFE
0xEA
0xEB
0xEC
0xED
ADC0LTH
ADC0LTL
AMX0CF
AMX0SL
B
CKCON
CPT0CN
CPT1CN
DAC0CN
DAC0H
DAC0L
DAC1CN
DAC1H
DAC1L
DPH
ADC Less-Than Data Word (High Byte)
ADC Less-Than Data Word (Low Byte)
ADC MUX Configuration
ADC MUX Channel Selection
B Register
Clock Control
Comparator 0 Control
Comparator 1 Control
DAC 0 Control
DAC 0 Data Word (High Byte)
DAC 0 Data Word (Low Byte)
DAC 1 Control
DAC 1 Data Word (High Byte)
DAC 1 Data Word (Low Byte)
Data Pointer (High Byte)
36*, 47**
36*, 47**
31*, 42**
32*, 43**
76
144
56
58
52
52
52
53
53
53
74
74
81
82
83
84
92***
90***
91
DPL
EIE1
EIE2
EIP1
Data Pointer (Low Byte)
Extended Interrupt Enable 1
Extended Interrupt Enable 2
External Interrupt Priority 1
External Interrupt Priority 2
External Memory Interface Control
Flash Access Limit
Flash Memory Timing Prescaler
Interrupt Enable
Interrupt Priority Control
Internal Oscillator Control
External Oscillator Control
Port 0 Latch
Port 1 Latch
Port 2 Latch
EIP2
EMI0CN
FLACL
FLSCL
IE
79
80
IP
OSCICN
OSCXCN
P0
P1
P2
100
101
109
110
111
112
160
163
163
163
163
163
163
163
163
163
P3
Port 3 Latch
PCA0CN
PCA0CPH0
PCA0CPH1
PCA0CPH2
PCA0CPH3
PCA0CPH4
PCA0CPL0
PCA0CPL1
PCA0CPL2
PCA0CPL3
Programmable Counter Array 0 Control
PCA Capture Module 0 Data Word (High Byte)
PCA Capture Module 1 Data Word (High Byte)
PCA Capture Module 2 Data Word (High Byte)
PCA Capture Module 3 Data Word (High Byte)
PCA Capture Module 4 Data Word (High Byte)
PCA Capture Module 0 Data Word (Low Byte)
PCA Capture Module 1 Data Word (Low Byte)
PCA Capture Module 2 Data Word (Low Byte)
PCA Capture Module 3 Data Word (Low Byte)
71
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Description
Page No.
Address Register
0xEE
0xDA
0xDB
0xDC
0xDD
0xDE
0xF9
0xE9
0xD9
0x87
PCA0CPL4
PCA Capture Module 4 Data Word (Low Byte)
Programmable Counter Array 0 Capture/Compare 0
Programmable Counter Array 0 Capture/Compare 1
Programmable Counter Array 0 Capture/Compare 2
Programmable Counter Array 0 Capture/Compare 3
Programmable Counter Array 0 Capture/Compare 4
PCA Counter/Timer Data Word (High Byte)
PCA Counter/Timer Data Word (Low Byte)
Programmable Counter Array 0 Mode
Power Control
163
162
162
162
162
162
163
163
161
86
PCA0CPM0
PCA0CPM1
PCA0CPM2
PCA0CPM3
PCA0CPM4
PCA0H
PCA0L
PCA0MD
PCON
0xA4
0xA5
0xAD
0xA6
0xA7
0x8F
0xD0
0xCB
0xCA
0xD1
0xEF
0x99
PRT0CF
PRT1CF
PRT1IF
PRT2CF
PRT3CF
PSCTL
Port 0 Configuration
Port 1 Configuration
Port 1 Interrupt Flags
Port 2 Configuration
Port 3 Configuration
Program Store RW Control
Program Status Word
Counter/Timer 2 Capture (High Byte)
Counter/Timer 2 Capture (Low Byte)
Voltage Reference Control Register
Reset Source Register
Serial Data Buffer (UART)
Serial Port Control (UART)
SMBus 0 Address
SMBus 0 Control
SMBus 0 Clock Rate
SMBus 0 Data
109
110
110
111
112
88
PSW
75
RCAP2H
RCAP2L
REF0CN
RSTSRC
SBUF
151
151
61
97
136
137
120
118
119
120
121
74
0x98
SCON
0xC3
0xC0
0xCF
0xC2
0xC1
0x81
SMB0ADR
SMB0CN
SMB0CR
SMB0DAT
SMB0STA
SP
SMBus 0 Status
Stack Pointer
0x9A
0x9D
0xF8
0x9B
0xC8
0x88
0x8C
0x8D
0xCD
0x8A
0x8B
0xCC
SPI0CFG
SPI0CKR
SPI0CN
SPI0DAT
T2CON
TCON
TH0
TH1
TH2
TL0
Serial Peripheral Interface Configuration
SPI Clock Rate
SPI Bus Control
SPI Port 1Data
Counter/Timer 2 Control
127
129
128
129
150
142
145
145
151
145
145
151
Counter/Timer Control
Counter/Timer 0 Data Word (High Byte)
Counter/Timer 1 Data Word (High Byte)
Counter/Timer 2 Data Word (High Byte)
Counter/Timer 0 Data Word (Low Byte)
Counter/Timer 1 Data Word (Low Byte)
Counter/Timer 2 Data Word (Low Byte)
TL1
TL2
Rev. 1.7
72
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Description
Page No.
Address Register
0x89
0x91
0x95
0x94
0x93
0x92
0xFF
0xE1
0xE2
0xE3
TMOD
Counter/Timer Mode
Timer 3 Control
Timer 3 High
Timer 3 Low
Timer 3 Reload High
Timer 3 Reload Low
Watchdog Timer Control
Port I/O Crossbar Configuration 1
Port I/O Crossbar Configuration 2
Port I/O Crossbar Configuration 3
143
152
153
153
153
153
96
105
107
108
TMR3CN
TMR3H
TMR3L
TMR3RLH
TMR3RLL
WDTCN
XBR0
XBR1
XBR2
0x84-86, 0x96-97, 0x9C,
0xA1-A3, 0xA9-AC,
0xAE, 0xB3-B5, 0xB9,
0xBD, 0xC9, 0xCE,
Reserved
0xDF, 0xE4-E5, 0xF1-F5
* Refers to a register in the C8051F000/1/2/5/6/7 only.
** Refers to a register in the C8051F010/1/2/5/6/7 only.
*** Refers to a register in the C8051F005/06/07/15/16/17 only.
73
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
10.3.1. Register Descriptions
Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits should
not be set to logic l. Future product versions may use these bits to implement new features in which case the reset
value of the bit will be logic 0, selecting the feature’s default state. Detailed descriptions of the remaining SFRs are
included in the sections of the datasheet associated with their corresponding system function.
Figure 10.3. SP: Stack Pointer
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Bit0
Reset Value
00000111
SFR Address:
0x81
Bits 7-0:SP: Stack Pointer.
The stack pointer holds the location of the top of the stack. The stack pointer is
incremented before every PUSH operation. The SP register defaults to 0x07 after reset.
Figure 10.4. DPL: Data Pointer Low Byte
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Bit0
Reset Value
00000000
SFR Address:
0x82
Bits 7-0:DPL: Data Pointer Low.
The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed RAM and Flash Memory.
Figure 10.5. DPH: Data Pointer High Byte
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Bit0
Reset Value
00000000
SFR Address:
0x83
Bits 7-0:DPH: Data Pointer High.
The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed RAM and Flash Memory.
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Figure 10.6. PSW: Program Status Word
R/W
CY
R/W
AC
R/W
F0
R/W
RS1
Bit4
R/W
RS0
Bit3
R/W
OV
Bit2
R/W
F1
R/W
Reset Value
PARITY
00000000
SFR Address:
Bit7
Bit6
Bit5
Bit1
Bit0
(bit addressable)
0xD0
Bit7:
Bit6:
CY: Carry Flag.
This bit is set when the last arithmetic operation results in a carry (addition) or a borrow
(subtraction). It is cleared to 0 by all other arithmetic operations.
AC: Auxiliary Carry Flag.
This bit is set when the last arithmetic operation results in a carry into (addition) or a
borrow from (subtraction) the high order nibble. It is cleared to 0 by all other arithmetic
operations.
Bit5:
F0: User Flag 0.
This is a bit-addressable, general purpose flag for use under software control.
Bits4-3: RS1-RS0: Register Bank Select.
These bits select which register bank is used during register accesses.
RS1
RS0
Register Bank
Address
0
0
1
1
0
1
0
1
0
1
2
3
0x00-0x07
0x08-0x0F
0x10-0x17
0x18-0x1F
Note: Any instruction which changes the RS1-RS0 bits must not be immediately followed
by the “MOV Rn, A” instruction.
Bit2:
OV: Overflow Flag.
This bit is set to 1 under the following circumstances:
• An ADD, ADDC, or SUBB instruction causes a sign-change overflow.
• A MUL instruction results in an overflow (result is greater than 255) .
• A DIV instruction causes a divide-by-zero condition.
The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all
other cases.
Bit1:
Bit0:
F1: User Flag 1.
This is a bit-addressable, general purpose flag for use under software control.
PARITY: Parity Flag.
(Read only)
This bit is set to 1 if the sum of the eight bits in the accumulator is odd and cleared if the
sum is even.
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Figure 10.7. ACC: Accumulator
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
ACC.7
Bit7
ACC.6
Bit6
ACC.5
Bit5
ACC.4
Bit4
ACC.3
Bit3
ACC.2
Bit2
ACC.1
Bit1
ACC.0
00000000
SFR Address:
Bit0
(bit addressable)
0xE0
Bits 7-0:ACC: Accumulator
This register is the accumulator for arithmetic operations.
Figure 10.8. B: B Register
R/W
B.7
Bit7
R/W
B.6
Bit6
R/W
B.5
Bit5
R/W
B.4
Bit4
R/W
B.3
Bit3
R/W
B.2
Bit2
R/W
B.1
Bit1
R/W
B.0
Reset Value
00000000
SFR Address:
Bit0
(bit addressable)
0xF0
Bits 7-0:B: B Register
This register serves as a second accumulator for certain arithmetic operations.
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10.4. INTERRUPT HANDLER
The CIP-51 includes an extended interrupt system supporting a total of 22 interrupt sources with two priority levels.
The allocation of interrupt sources between on-chip peripherals and external inputs pins varies according to the
specific version of the device. Each interrupt source has one or more associated interrupt-pending flag(s) located in
an SFR. When a peripheral or external source meets a valid interrupt condition, the associated interrupt-pending
flag is set to logic 1.
If interrupts are enabled for the source, an interrupt request is generated when the interrupt-pending flag is set. As
soon as execution of the current instruction is complete, the CPU generates an LCALL to a predetermined address
to begin execution of an interrupt service routine (ISR). Each ISR must end with an RETI instruction, which
returns program execution to the next instruction that would have been executed if the interrupt request had not
occurred. If interrupts are not enabled, the interrupt-pending flag is ignored by the hardware and program execution
continues as normal. (The interrupt-pending flag is set to logic 1 regardless of the interrupt’s enable/disable state.)
Each interrupt source can be individually enabled or disabled through the use of an associated interrupt enable bit in
an SFR (IE-EIE2). However, interrupts must first be globally enabled by setting the EA bit (IE.7) to logic 1 before
the individual interrupt enables are recognized. Setting the EA bit to logic 0 disables all interrupt sources regardless
of the individual interrupt-enable settings.
Some interrupt-pending flags are automatically cleared by the hardware when the CPU vectors to the ISR.
However, most are not cleared by the hardware and must be cleared by software before returning from the ISR. If
an interrupt-pending flag remains set after the CPU completes the return-from-interrupt (RETI) instruction, a new
interrupt request will be generated immediately and the CPU will re-enter the ISR after the completion of the next
instruction.
10.4.1. MCU Interrupt Sources and Vectors
The MCUs allocate 12 interrupt sources to on-chip peripherals. Up to 10 additional external interrupt sources are
available depending on the I/O pin configuration of the device. Software can simulate an interrupt by setting any
interrupt-pending flag to logic 1. If interrupts are enabled for the flag, an interrupt request will be generated and the
CPU will vector to the ISR address associated with the interrupt-pending flag. MCU interrupt sources, associated
vector addresses, priority order and control bits are summarized in Table 10.4. Refer to the datasheet section
associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral
and the behavior of its interrupt-pending flag(s).
10.4.2. External Interrupts
Two of the external interrupt sources (/INT0 and /INT1) are configurable as active-low level-sensitive or active-low
edge-sensitive inputs depending on the setting of IT0 (TCON.0) and IT1 (TCON.2). IE0 (TCON.1) and IE1
(TCON.3) serve as the interrupt-pending flag for the /INT0 and /INT1 external interrupts, respectively. If an /INT0
or /INT1 external interrupt is configured as edge-sensitive, the corresponding interrupt-pending flag is automatically
cleared by the hardware when the CPU vectors to the ISR. When configured as level sensitive, the interrupt-
pending flag follows the state of the external interrupt’s input pin. The external interrupt source must hold the input
active until the interrupt request is recognized. It must then deactivate the interrupt request before execution of the
ISR completes or another interrupt request will be generated.
The remaining four external interrupts (External Interrupts 4-7) are active-low, edge-sensitive inputs. The interrupt-
pending flags for these interrupts are in the Port 1 Interrupt Flag Register shown in Figure 15.10.
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Table 10.4. Interrupt Summary
Interrupt
Vector
Priority
Order
Interrupt Source
Interrupt-Pending Flag
Enable
Reset
0x0000
0x0003
0x000B
0x0013
0x001B
0x0023
Top
None
Always enabled
EX0 (IE.0)
ET0 (IE.1)
EX1 (IE.2)
ET1 (IE.3)
ES (IE.4)
External Interrupt 0 (/INT0)
Timer 0 Overflow
0
IE0 (TCON.1)
1
TF0 (TCON.5)
External Interrupt 1 (/INT1)
Timer 1 Overflow
Serial Port (UART)
2
IE1 (TCON.3)
3
TF1 (TCON.7)
4
RI (SCON.0)
TI (SCON.1)
Timer 2 Overflow (or EXF2)
Serial Peripheral Interface
0x002B
0x0033
5
6
TF2 (T2CON.7)
SPIF (SPI0CN.7)
WCOL (SPI0CN.6)
MODF (SPI0CN.5)
RXOVRN (SPI0CN.4)
SI (SMB0CN.3)
ADWINT (ADC0CN.2)
CF (PCA0CN.7)
CCFn (PCA0CN.n)
CP0FIF (CPT0CN.4)
CP0RIF (CPT0CN.5)
CP1FIF (CPT1CN.4)
CP1RIF (CPT1CN.5)
TF3 (TMR3CN.7)
ADCINT (ADC0CN.5)
IE4 (PRT1IF.4)
IE5 (PRT1IF.5)
IE6 (PRT1IF.6)
IE7 (PRT1IF.7)
None
ET2 (IE.5)
ESPI0 (EIE1.0)
SMBus Interface
ADC0 Window Comparison
Programmable Counter Array 0
0x003B
0x0043
0x004B
7
8
9
ESMB0 (EIE1.1)
EWADC0 (EIE1.2)
EPCA0 (EIE1.3)
Comparator 0 Falling Edge
Comparator 0 Rising Edge
Comparator 1 Falling Edge
Comparator 1 Rising Edge
Timer 3 Overflow
0x0053
0x005B
0x0063
0x006B
0x0073
0x007B
0x0083
0x008B
0x0093
0x009B
0x00A3
0x00AB
10
11
12
13
14
15
16
17
18
19
20
21
ECP0F (EIE1.4)
ECP0R (EIE1.5)
ECP1F (EIE1.6)
ECP1R (EIE1.7)
ET3 (EIE2.0)
ADC0 End of Conversion
External Interrupt 4
EADC0 (EIE2.1)
EX4 (EIE2.2)
External Interrupt 5
EX5 (EIE2.3)
External Interrupt 6
EX6 (EIE2.4)
External Interrupt 7
EX7 (EIE2.5)
Unused Interrupt Location
External Crystal OSC Ready
Reserved (EIE2.6)
EXVLD (EIE2.7)
XTLVLD (OSCXCN.7)
10.4.3. Interrupt Priorities
Each interrupt source can be individually programmed to one of two priority levels: low or high. A low priority
interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be
preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP-EIP2) used to configure its priority
level. Low priority is the default. If two interrupts are recognized simultaneously, the interrupt with the higher
priority is serviced first. If both interrupts have the same priority level, a fixed priority order is used to arbitrate.
10.4.4. Interrupt Latency
Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are sampled
and priority decoded each system clock cycle. Therefore, the fastest possible response time is 5 system clock
cycles: 1 clock cycle to detect the interrupt and 4 clock cycles to complete the LCALL to the ISR. If an interrupt is
pending when a RETI is executed, a single instruction is executed before an LCALL is made to service the pending
interrupt. Therefore, the maximum response time for an interrupt (when no other interrupt is currently being
serviced or the new interrupt is of greater priority) occurs when the CPU is performing an RETI instruction
followed by a DIV as the next instruction. In this case, the response time is 18 system clock cycles: 1 clock cycle
to detect the interrupt, 5 clock cycles to execute the RETI, 8 clock cycles to complete the DIV instruction and 4
clock cycles to execute the LCALL to the ISR. If the CPU is executing an ISR for an interrupt with equal or higher
priority, the new interrupt will not be serviced until the current ISR completes, including the RETI and following
instruction.
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10.4.5. Interrupt Register Descriptions
The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the datasheet
section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the
peripheral and the behavior of its interrupt-pending flag(s).
Figure 10.9. IE: Interrupt Enable
R/W
EA
R/W
IEGF0
Bit6
R/W
ET2
Bit5
R/W
ES
R/W
ET1
Bit3
R/W
EX1
Bit2
R/W
ET0
Bit1
R/W
EX0
Reset Value
00000000
SFR Address:
Bit7
Bit4
Bit0
(bit addressable)
0xA8
Bit7:
EA: Enable All Interrupts.
This bit globally enables/disables all interrupts. It overrides the individual interrupt mask
settings.
0: Disable all interrupt sources.
1: Enable each interrupt according to its individual mask setting.
Bit6:
Bit5:
IEGF0: General Purpose Flag 0.
This is a general purpose flag for use under software control.
ET2: Enable Timer 2 Interrupt.
This bit sets the masking of the Timer 2 interrupt.
0: Disable all Timer 2 interrupts.
1: Enable interrupt requests generated by the TF2 flag (T2CON.7)
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
ES: Enable Serial Port (UART) Interrupt.
This bit sets the masking of the Serial Port (UART) interrupt.
0: Disable all UART interrupts.
1: Enable interrupt requests generated by the R1 flag (SCON.0) or T1 flag (SCON.1).
ET1: Enable Timer 1 Interrupt.
This bit sets the masking of the Timer 1 interrupt.
0: Disable all Timer 1 interrupts.
1: Enable interrupt requests generated by the TF1 flag (TCON.7).
EX1: Enable External Interrupt 1.
This bit sets the masking of external interrupt 1.
0: Disable external interrupt 1.
1: Enable interrupt requests generated by the /INT1 pin.
ET0: Enable Timer 0 Interrupt.
This bit sets the masking of the Timer 0 interrupt.
0: Disable all Timer 0 interrupts.
1: Enable interrupt requests generated by the TF0 flag (TCON.5).
EX0: Enable External Interrupt 0.
This bit sets the masking of external interrupt 0.
0: Disable external interrupt 0.
1: Enable interrupt requests generated by the /INT0 pin.
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Figure 10.10. IP: Interrupt Priority
R/W
-
R/W
-
R/W
PT2
Bit5
R/W
PS
R/W
PT1
Bit3
R/W
PX1
Bit2
R/W
PT0
Bit1
R/W
PX0
Reset Value
00000000
SFR Address:
Bit7
Bit6
Bit4
Bit0
(bit addressable)
0xB8
Bits7-6: UNUSED. Read = 11b, Write = don’t care.
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
PT2 Timer 2 Interrupt Priority Control.
This bit sets the priority of the Timer 2 interrupts.
0: Timer 2 interrupts set to low priority level.
1: Timer 2 interrupts set to high priority level.
PS: Serial Port (UART) Interrupt Priority Control.
This bit sets the priority of the Serial Port (UART) interrupts.
0: UART interrupts set to low priority level.
1: UART interrupts set to high priority level.
PT1: Timer 1 Interrupt Priority Control.
This bit sets the priority of the Timer 1 interrupts.
0: Timer 1 interrupts set to low priority level.
1: Timer 1 interrupts set to high priority level.
PX1: External Interrupt 1 Priority Control.
This bit sets the priority of the External Interrupt 1 interrupts.
0: External Interrupt 1 set to low priority level.
1: External Interrupt 1 set to high priority level.
PT0: Timer 0 Interrupt Priority Control.
This bit sets the priority of the Timer 0 interrupts.
0: Timer 0 interrupt set to low priority level.
1: Timer 0 interrupt set to high priority level.
PX0: External Interrupt 0 Priority Control.
This bit sets the priority of the External Interrupt 0 interrupts.
0: External Interrupt 0 set to low priority level.
1: External Interrupt 0 set to high priority level.
Rev. 1.7
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Figure 10.11. EIE1: Extended Interrupt Enable 1
R/W
ECP1R
Bit7
R/W
ECP1F
Bit6
R/W
ECP0R
Bit5
R/W
ECP0F
Bit4
R/W
EPCA0
Bit3
R/W
EWADC0
Bit2
R/W
ESMB0
Bit1
R/W
ESPI0
Bit0
Reset Value
00000000
SFR Address:
0xE6
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
ECP1R: Enable Comparator 1 (CP1) Rising Edge Interrupt.
This bit sets the masking of the CP1 interrupt.
0: Disable CP1 Rising Edge interrupt.
1: Enable interrupt requests generated by the CP1RIF flag (CPT1CN.5).
ECP1F: Enable Comparator 1 (CP1) Falling Edge Interrupt.
This bit sets the masking of the CP1 interrupt.
0: Disable CP1 Falling Edge interrupt.
1: Enable interrupt requests generated by the CP1FIF flag (CPT1CN.4).
ECP0R: Enable Comparator 0 (CP0) Rising Edge Interrupt.
This bit sets the masking of the CP0 interrupt.
0: Disable CP0 Rising Edge interrupt.
1: Enable interrupt requests generated by the CP0RIF flag (CPT0CN.5).
ECP0F: Enable Comparator 0 (CP0) Falling Edge Interrupt.
This bit sets the masking of the CP0 interrupt.
0: Disable CP0 Falling Edge interrupt.
1: Enable interrupt requests generated by the CP0FIF flag (CPT0CN.4).
EPCA0: Enable Programmable Counter Array (PCA0) Interrupt.
This bit sets the masking of the PCA0 interrupts.
0: Disable all PCA0 interrupts.
1: Enable interrupt requests generated by PCA0.
EWADC0: Enable Window Comparison ADC0 Interrupt.
This bit sets the masking of ADC0 Window Comparison interrupt.
0: Disable ADC0 Window Comparison Interrupt.
1: Enable Interrupt requests generated by ADC0 Window Comparisons.
ESMB0: Enable SMBus 0 Interrupt.
This bit sets the masking of the SMBus interrupt.
0: Disable all SMBus interrupts.
1: Enable interrupt requests generated by the SI flag (SMB0CN.3).
ESPI0: Enable Serial Peripheral Interface 0 Interrupt.
This bit sets the masking of SPI0 interrupt.
0: Disable all SPI0 interrupts.
1: Enable Interrupt requests generated by SPI0.
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Figure 10.12. EIE2: Extended Interrupt Enable 2
R/W
EXVLD
Bit7
R/W
-
R/W
EX7
Bit5
R/W
EX6
Bit4
R/W
EX5
Bit3
R/W
EX4
Bit2
R/W
EADC0
Bit1
R/W
ET3
Bit0
Reset Value
00000000
SFR Address:
Bit6
0xE7
Bit7:
EXVLD: Enable External Clock Source Valid (XTLVLD) Interrupt.
This bit sets the masking of the XTLVLD interrupt.
0: Disable all XTLVLD interrupts.
1: Enable interrupt requests generated by the XTLVLD flag (OSCXCN.7)
Bit6:
Bit5:
Reserved. Must Write 0. Reads 0.
EX7: Enable External Interrupt 7.
This bit sets the masking of External Interrupt 7.
0: Disable External Interrupt 7.
1: Enable interrupt requests generated by the External Interrupt 7 input pin.
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
EX6: Enable External Interrupt 6.
This bit sets the masking of External Interrupt 6.
0: Disable External Interrupt 6.
1: Enable interrupt requests generated by the External Interrupt 6 input pin.
EX5: Enable External Interrupt 5.
This bit sets the masking of External Interrupt 5.
0: Disable External Interrupt 5.
1: Enable interrupt requests generated by the External Interrupt 5 input pin.
EX4: Enable External Interrupt 4.
This bit sets the masking of External Interrupt 4.
0: Disable External Interrupt 4.
1: Enable interrupt requests generated by the External Interrupt 4 input pin.
EADC0: Enable ADC0 End of Conversion Interrupt.
This bit sets the masking of the ADC0 End of Conversion Interrupt.
0: Disable ADC0 Conversion Interrupt.
1: Enable interrupt requests generated by the ADC0 Conversion Interrupt.
ET3: Enable Timer 3 Interrupt.
This bit sets the masking of the Timer 3 interrupt.
0: Disable all Timer 3 interrupts.
1: Enable interrupt requests generated by the TF3 flag (TMR3CN.7)
Rev. 1.7
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Figure 10.13. EIP1: Extended Interrupt Priority 1
R/W
PCP1R
Bit7
R/W
PCP1F
Bit6
R/W
PCP0R
Bit5
R/W
PCP0F
Bit4
R/W
PPCA0
Bit3
R/W
PWADC0
Bit2
R/W
PSMB0
Bit1
R/W
PSPI0
Bit0
Reset Value
00000000
SFR Address:
0xF6
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
PCP1R: Comparator 1 (CP1) Rising Interrupt Priority Control.
This bit sets the priority of the CP1 interrupt.
0: CP1 rising interrupt set to low priority level.
1: CP1 rising interrupt set to high priority level.
PCP1F: Comparator 1 (CP1) Falling Interrupt Priority Control.
This bit sets the priority of the CP1 interrupt.
0: CP1 falling interrupt set to low priority level.
1: CP1 falling interrupt set to high priority level.
PCP0R: Comparator 0 (CP0) Rising Interrupt Priority Control.
This bit sets the priority of the CP0 interrupt.
0: CP0 rising interrupt set to low priority level.
1: CP0 rising interrupt set to high priority level.
PCP0F: Comparator 0 (CP0) Falling Interrupt Priority Control.
This bit sets the priority of the CP0 interrupt.
0: CP0 falling interrupt set to low priority level.
1: CP0 falling interrupt set to high priority level.
PPCA0: Programmable Counter Array (PCA0) Interrupt Priority Control.
This bit sets the priority of the PCA0 interrupt.
0: PCA0 interrupt set to low priority level.
1: PCA0 interrupt set to high priority level.
PWADC0: ADC0 Window Comparator Interrupt Priority Control.
This bit sets the priority of the ADC0 Window interrupt.
0: ADC0 Window interrupt set to low priority level.
1: ADC0 Window interrupt set to high priority level.
PSMB0: SMBus 0 Interrupt Priority Control.
This bit sets the priority of the SMBus interrupt.
0: SMBus interrupt set to low priority level.
1: SMBus interrupt set to high priority level.
PSPI0: Serial Peripheral Interface 0 Interrupt Priority Control.
This bit sets the priority of the SPI0 interrupt.
0: SPI0 interrupt set to low priority level.
1: SPI0 interrupt set to high priority level.
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Figure 10.14. EIP2: Extended Interrupt Priority 2
R/W
PXVLD
Bit7
R/W
-
R/W
PX7
Bit5
R/W
PX6
Bit4
R/W
PX5
Bit3
R/W
PX4
Bit2
R/W
PADC0
Bit1
R/W
PT3
Bit0
Reset Value
00000000
SFR Address:
Bit6
0xF7
Bit7:
PXVLD: External Clock Source Valid (XTLVLD) Interrupt Priority Control.
This bit sets the priority of the XTLVLD interrupt.
0: XTLVLD interrupt set to low priority level.
1: XTLVLD interrupt set to high priority level.
Bit6:
Bit5:
Reserved: Must write 0. Reads 0.
PX7: External Interrupt 7 Priority Control.
This bit sets the priority of the External Interrupt 7.
0: External Interrupt 7 set to low priority level.
1: External Interrupt 7 set to high priority level.
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
PX6: External Interrupt 6 Priority Control.
This bit sets the priority of the External Interrupt 6.
0: External Interrupt 6 set to low priority level.
1: External Interrupt 6 set to high priority level.
PX5: External Interrupt 5 Priority Control.
This bit sets the priority of the External Interrupt 5.
0: External Interrupt 5 set to low priority level.
1: External Interrupt 5 set to high priority level.
PX4: External Interrupt 4 Priority Control.
This bit sets the priority of the External Interrupt 4.
0: External Interrupt 4 set to low priority level.
1: External Interrupt 4 set to high priority level.
PADC0: ADC End of Conversion Interrupt Priority Control.
This bit sets the priority of the ADC0 End of Conversion Interrupt.
0: ADC0 End of Conversion interrupt set to low priority level.
1: ADC0 End of Conversion interrupt set to high priority level.
PT3: Timer 3 Interrupt Priority Control.
This bit sets the priority of the Timer 3 interrupts.
0: Timer 3 interrupt set to low priority level.
1: Timer 3 interrupt set to high priority level.
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10.5. Power Management Modes
The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode halts the
CPU while leaving the external peripherals and internal clocks active. In Stop mode, the CPU is halted, all
interrupts and timers (except the Missing Clock Detector) are inactive, and the system clock is stopped. Since
clocks are running in Idle mode, power consumption is dependent upon the system clock frequency and the number
of peripherals left in active mode before entering Idle. Stop mode consumes the least power. Figure 10.15
describes the Power Control Register (PCON) used to control the CIP-51’s power management modes.
Although the CIP-51 has Idle and Stop modes built in (as with any standard 8051 architecture), power management
of the entire MCU is better accomplished by enabling/disabling individual peripherals as needed. Each analog
peripheral can be disabled when not in use and put into low power mode. Digital peripherals, such as timers or
serial buses, draw little power whenever they are not in use. Turning off the oscillator saves even more power, but
requires a reset to restart the MCU.
10.5.1. Idle Mode
Setting the Idle Mode Select bit (PCON.0) causes the CIP-51 to halt the CPU and enter Idle mode as soon as the
instruction that sets the bit completes. All internal registers and memory maintain their original data. All analog
and digital peripherals can remain active during Idle mode.
Idle mode is terminated when an enabled interrupt or /RST is asserted. The assertion of an enabled interrupt will
cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU will resume operation. The pending
interrupt will be serviced and the next instruction to be executed after the return from interrupt (RETI) will be the
instruction immediately following the one that set the Idle Mode Select bit. If Idle mode is terminated by an internal
or external reset, the CIP-51 performs a normal reset sequence and begins program execution at address 0x0000.
Note: If the instruction following the write of the IDLE bit is a single-byte instruction and an interrupt occurs during
the execution phase of the instruction that sets the IDLE bit, the CPU may not wake from Idle mode when a future
interrupt occurs. Any instructions that set the IDLE bit should be followed by an instruction that has 2 or more op-
code bytes, for example:
// in ‘C’:
PCON |= 0x01;
// set IDLE bit
PCON = PCON;
// ... followed by a 3-cycle dummy instruction
; in assembly:
ORL PCON, #01h
MOV PCON, PCON
; set IDLE bit
; ... followed by a 3-cycle dummy instruction
If enabled, the WDT will eventually cause an internal watchdog reset and thereby terminate the Idle mode. This
feature protects the system from an unintended permanent shutdown in the event of an inadvertent write to the
PCON register. If this behavior is not desired, the WDT may be disabled by software prior to entering the Idle
mode if the WDT was initially configured to allow this operation. This provides the opportunity for additional
power savings, allowing the system to remain in the Idle mode indefinitely, waiting for an external stimulus to wake
up the system. Refer to Section 13.8 Watchdog Timer for more information on the use and configuration of the
WDT.
10.5.2. Stop Mode
Setting the Stop Mode Select bit (PCON.1) causes the CIP-51 to enter Stop mode as soon as the instruction that sets
the bit completes. In Stop mode, the CPU and oscillators are stopped, effectively shutting down all digital
peripherals. Each analog peripheral must be shut down individually prior to entering Stop Mode. Stop mode can
only be terminated by an internal or external reset. On reset, the CIP-51 performs the normal reset sequence and
begins program execution at address 0x0000.
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If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode. The
Missing Clock Detector should be disabled if the CPU is to be put to sleep for longer than the MCD timeout of
100µsec.
Figure 10.15. PCON: Power Control Register
R/W
SMOD
Bit7
R/W
GF4
Bit6
R/W
GF3
Bit5
R/W
GF2
Bit4
R/W
GF1
Bit3
R/W
GF0
Bit2
R/W
STOP
Bit1
R/W
IDLE
Bit0
Reset Value
00000000
SFR Address:
0x87
Bit7:
SMOD: Serial Port Baud Rate Doubler Enable.
0: Serial Port baud rate is that defined by Serial Port Mode in SCON.
1: Serial Port baud rate is double that defined by Serial Port Mode in SCON.
Bits6-2: GF4-GF0: General Purpose Flags 4-0.
These are general purpose flags for use under software control.
Bit1:
Bit0:
STOP: Stop Mode Select.
Setting this bit will place the CIP-51 in Stop mode. This bit will always be read as 0.
1: Goes into power down mode. (Turns off internal oscillator).
IDLE: Idle Mode Select.
Setting this bit will place the CIP-51 in Idle mode. This bit will always be read as 0.
1: Goes into idle mode. (Shuts off clock to CPU, but clock to Timers, Interrupts, Serial
Ports, and Analog Peripherals are still active.)
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11. FLASH MEMORY
These devices include 32k + 128 bytes of on-chip, reprogrammable Flash memory for program code and non-
volatile data storage. The Flash memory can be programmed in-system, a single byte at a time, through the JTAG
interface or by software using the MOVX instruction. Once cleared to 0, a Flash bit must be erased to set it back to
1. The bytes would typically be erased (set to 0xFF) before being reprogrammed. The write and erase operations
are automatically timed by hardware for proper execution. Data polling to determine the end of the write/erase
operation is not required. The Flash memory is designed to withstand at least 20,000 write/erase cycles. Refer to
Table 11.1 for the electrical characteristics of the Flash memory.
11.1. Programming The Flash Memory
The simplest means of programming the Flash memory is through the JTAG interface using programming tools
provided by Silicon Labs or a third party vendor. This is the only means for programming a non-initialized device.
For details on the JTAG commands to program Flash memory, see Section 21.2.
The Flash memory can be programmed by software using the MOVX instruction with the address and data byte to
be programmed provided as normal operands. Before writing to Flash memory using MOVX, Flash write
operations must be enabled by setting the PSWE Program Store Write Enable bit (PSCTL.0) to logic 1. Writing to
Flash remains enabled until the PSWE bit is cleared by software.
Writes to Flash memory can clear bits but cannot set them. Only an erase operation can set bits in Flash. Therefore,
the byte location to be programmed must be erased before a new value can be written. The 32kbyte Flash memory
is organized in 512-byte sectors. The erase operation applies to an entire sector (setting all bytes in the sector to
0xFF). Setting the PSEE Program Store Erase Enable bit (PSCTL.1) and PSWE (PSCTL.0) bit to logic 1 and then
using the MOVX command to write a data byte to any byte location within the sector will erase an entire 512-byte
sector. The data byte written can be of any value because it is not actually written to the Flash. Flash erasure
remains enabled until the PSEE bit is cleared by software. The following sequence illustrates the algorithm for
programming the Flash memory by software:
1. Enable Flash Memory write/erase in FLSCL Register using FLASCL bits.
2. Set PSEE (PSCTL.1) to enable Flash sector erase.
3. Set PSWE (PSCTL.0) to enable Flash writes.
4. Use MOVX to write a data byte to any location within the 512-byte sector to be erased.
5. Clear PSEE to disable Flash sector erase.
6. Use MOVX to write a data byte to the desired byte location within the erased 512-byte sector. Repeat until
finished. (Any number of bytes can be written from a single byte to and entire sector.)
7. Clear the PSWE bit to disable Flash writes.
Write/Erase timing is automatically controlled by hardware based on the prescaler value held in the Flash Memory
Timing Prescaler register (FLSCL). The 4-bit prescaler value FLASCL determines the time interval for write/erase
operations. The FLASCL value required for a given system clock is shown in Figure 11.4, along with the formula
used to derive the FLASCL values. When FLASCL is set to 1111b, the write/erase operations are disabled. Note
that code execution in the 8051 is stalled while the Flash is being programmed or erased.
Table 11.1. FLASH Memory Electrical Characteristics
VDD = 2.7 to 3.6V, -40°C to +85°C unless otherwise specified.
PARAMETER
CONDITIONS
MIN
20k
10
TYP
100k
MAX
UNITS
Erase/Wr
ms
Endurance
Erase Cycle Time
Write Cycle Time
40
µs
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11.2. Non-volatile Data Storage
The Flash memory can be used for non-volatile data storage as well as program code. This allows data such as
calibration coefficients to be calculated and stored at run time. Data is written using the MOVX instruction and
read using the MOVC instruction.
The MCU incorporates an additional 128-byte sector of Flash memory located at 0x8000 – 0x807F. This sector can
be used for program code or data storage. However, its smaller sector size makes it particularly well suited as
general purpose, non-volatile scratchpad memory. Even though Flash memory can be written a single byte at a
time, an entire sector must be erased first. In order to change a single byte of a multi-byte data set, the data must be
moved to temporary storage. Next, the sector is erased, the data set updated and the data set returned to the original
sector. The 128-byte sector-size facilitates updating data without wasting program memory space by allowing the
use of internal data RAM for temporary storage. (A normal 512-byte sector is too large to be stored in the 256-byte
internal data memory.)
11.3. Security Options
The CIP-51 provides security options to protect the Flash memory from inadvertent modification by software as
well as prevent the viewing of proprietary program code and constants. The Program Store Write Enable
(PSCTL.0) and the Program Store Erase Enable (PSCTL.1) bits protect the Flash memory from accidental
modification by software. These bits must be explicitly set to logic 1 before software can modify the Flash memory.
Additional security features prevent proprietary program code and data constants from being read or altered across
the JTAG interface or by software running on the system controller.
A set of security lock bytes stored at 0x7DFE and 0x7DFF protect the Flash program memory from being read or
altered across the JTAG interface. Each bit in a security lock-byte protects one 4kbyte block of memory. Clearing
a bit to logic 0 in a Read lock byte prevents the corresponding block of Flash memory from being read across the
JTAG interface. Clearing a bit in the Write/Erase lock byte protects the block from JTAG erasures and/or writes.
The Read lock byte is at location 0x7DFF. The Write/Erase lock byte is located at 0x7DFE. Figure 11.2 shows the
location and bit definitions of the security bytes. The 512-byte sector containing the lock bytes can be written to,
but not erased by software. Writing to the reserved area should not be performed.
Figure 11.1. PSCTL: Program Store RW Control
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
PSEE
Bit1
R/W
PSWE
Bit0
Reset Value
00000000
SFR Address:
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
0x8F
Bits7-2: UNUSED. Read = 000000b, Write = don’t care.
Bit1:
Bit0:
PSEE: Program Store Erase Enable.
Setting this bit allows an entire page of the Flash program memory to be erased provided
the PSWE bit is also set. After setting this bit, a write to Flash memory using the MOVX
instruction will erase the entire page that contains the location addressed by the MOVX
instruction. The value of the data byte written does not matter.
0: Flash program memory erasure disabled.
1: Flash program memory erasure enabled.
PSWE: Program Store Write Enable.
Setting this bit allows writing a byte of data to the Flash program memory using the
MOVX instruction. The location must be erased before writing data.
0: Write to Flash program memory disabled.
1: Write to Flash program memory enabled.
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Figure 11.2. Flash Program Memory Security Bytes
(This Block locked only if all
other blocks are locked)
0x807F
0x8000
0x7FFF
Reserved
0x7E00
0x7DFF
Read Lock Byte
0x7DFE
0x7DFD
Write/Erase Lock Byte
Read and Write/Erase Security Bits.
(Bit 7 is MSB.)
Program Memory
Space
Bit Memory Block
7
6
5
4
3
2
1
0
0x7000 - 0x7DFD
0x6000 - 0x6FFF
0x5000 - 0x5FFF
0x4000 - 0x4FFF
0x3000 - 0x3FFF
0x2000 - 0x2FFF
0x1000 - 0x1FFF
0x0000 - 0x0FFF
Software Read Limit
0x0000
FLASH Read Lock Byte
Bits7-0: Each bit locks a corresponding block of memory. (Bit 7 is MSB.)
0: Read operations are locked (disabled) for corresponding block across the JTAG interface.
1: Read operations are unlocked (enabled) for corresponding block across the JTAG interface.
FLASH Write/Erase Lock Byte
Bits7-0: Each bit locks a corresponding block of memory.
0: Write/Erase operations are locked (disabled) for corresponding block across the JTAG interface.
1: Write/Erase operations are unlocked (enabled) for corresponding block across the JTAG interface.
FLASH Access Limit Register (FLACL)
The content of this register is used as the high byte of the 16-bit software read limit address. The 16-
bit read limit address value is calculated as 0xNN00 where NN is replaced by the contents of this
register. Software running at or above this address is prohibited from using the MOVX or MOVC
instructions to read, write, or erase, locations below this address. Any attempts to read locations
below this limit will return the value 0x00.
The lock bits can always be read and cleared to logic 0 regardless of the security setting applied to the block
containing the security bytes. This allows additional blocks to be protected after the block containing the security
bytes has been locked. However, the only means of removing a lock once set is to erase the entire program memory
space by performing a JTAG erase operation (i.e. cannot be done in user firmware). NOTE: Addressing either
security byte while performing a JTAG erase operation will automatically initiate erasure of the entire
program memory space (except for the reserved area). This erasure can only be performed via JTAG. If a
non-security byte in the 0x7C00-0x7DFF page is addressed during erasure, only that page (including the
security bytes) will be erased.
The Flash Access Limit security feature (see Figure 11.3) protects proprietary program code and data from being
read by software running on the C8051F005/06/07/15/16/17 MCUs. This feature provides support for OEMs that
wish to program the MCU with proprietary value-added firmware before distribution. The value-added firmware
can be protected while allowing additional code to be programmed in remaining program memory space later.
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The Software Read Limit (SRL) is a 16-bit address that establishes two logical partitions in the program memory
space. The first is an upper partition consisting of all the program memory locations at or above the SRL address,
and the second is a lower partition consisting of all the program memory locations starting at 0x0000 up to (but
excluding) the SRL address. Software in the upper partition can execute code in the lower partition, but is
prohibited from reading locations in the lower partition using the MOVC instruction. (Executing a MOVC
instruction from the upper partition with a source address in the lower partition will always return a data value of
0x00.) Software running in the lower partition can access locations in both the upper and lower partition without
restriction.
The Value-added firmware should be placed in the lower partition. On reset, control is passed to the value-added
firmware via the reset vector. Once the value-added firmware completes its initial execution, it branches to a
predetermined location in the upper partition. If entry points are published, software running in the upper partition
may execute program code in the lower partition, but it cannot read the contents of the lower partition. Parameters
may be passed to the program code running in the lower partition either through the typical method of placing them
on the stack or in registers before the call or by placing them in prescribed memory locations in the upper partition.
The SRL address is specified using the contents of the Flash Access Register. The 16-bit SRL address is calculated
as 0xNN00, where NN is the contents of the SRL Security Register. Thus, the SRL can be located on 256-byte
boundaries anywhere in program memory space. However, the 512-byte erase sector size essentially requires that a
512 boundary be used. The contents of a non-initialized SRL security byte is 0x00, thereby setting the SRL address
to 0x0000 and allowing read access to all locations in program memory space by default.
Figure 11.3. FLACL: Flash Access Limit (C8051F005/06/07/15/16/17 only)
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Bit0
Reset Value
00000000
SFR Address:
0xB7
Bits 7-0:FLACL: Flash Access Limit.
This register holds the high byte of the 16-bit program memory read/write/erase limit
address. The entire 16-bit access limit address value is calculated as 0xNN00 where NN is
replaced by contents of FLACL. A write to this register sets the Flash Access Limit. This
register can only be written once after any reset. Any subsequent writes are ignored
until the next reset.
Rev. 1.7
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Figure 11.4. FLSCL: Flash Memory Timing Prescaler
R/W
R/W
R/W
R/W
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Bit0
Reset Value
10001111
SFR Address:
0xB6
FOSE
FRAE
-
-
FLASCL
Bit7
Bit6
Bit5
Bit4
Bit7:
Bit6:
FOSE: Flash One-Shot Timer Enable
0: Flash One-shot timer disabled.
1: Flash One-shot timer enabled
FRAE: Flash Read Always Enable
0: Flash reads per one-shot timer
1: Flash always in read mode
Bits5-4: UNUSED. Read = 00b, Write = don’t care.
Bits3-0: FLASCL: Flash Memory Timing Prescaler.
This register specifies the prescaler value for a given system clock required to generate the
correct timing for Flash write/erase operations. If the prescaler is set to 1111b, Flash
write/erase operations are disabled.
0000: System Clock < 50kHz
0001: 50kHz ≤ System Clock < 100kHz
0010: 100kHz ≤ System Clock < 200kHz
0011: 200kHz ≤ System Clock < 400kHz
0100: 400kHz ≤ System Clock < 800kHz
0101: 800kHz ≤ System Clock < 1.6MHz
0110: 1.6MHz ≤ System Clock < 3.2MHz
0111: 3.2MHz ≤ System Clock < 6.4MHz
1000: 6.4MHz ≤ System Clock < 12.8MHz
1001: 12.8MHz ≤ System Clock < 25.6MHz
1010: 25.6MHz ≤ System Clock < 51.2MHz *
1011, 1100, 1101, 1110: Reserved Values
1111: Flash Memory Write/Erase Disabled
The prescaler value is the smallest value satisfying the following equation:
FLASCL > log2(System Clock / 50kHz)
* For test purposes. The C8051F000 family is not guaranteed for operation over 25MHz.
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12. EXTERNAL RAM (C8051F005/06/07/15/16/17)
The C8051F005/06/07/15/16/17 MCUs include 2048 bytes of RAM mapped into the external data memory space.
All of these address locations may be accessed using the external move instruction (MOVX) and the data pointer
(DPTR), or using MOVX indirect addressing mode. If the MOVX instruction is used with an 8-bit address operand
(such as @R1), then the high byte of the 16-bit address is provided by the External Memory Interface Control
Register (EMI0CN as shown in Figure 12.1). Note: the MOVX instruction is also used for writes to the Flash
memory. See Section 11 for details. The MOVX instruction accesses XRAM by default (i.e. PSTCL.0 = 0).
For any of the addressing modes the upper 5-bits of the 16-bit external data memory address word are “don’t cares”.
As a result, the 2048-byte RAM is mapped modulo style over the entire 64k external data memory address range.
For example, the XRAM byte at address 0x0000 is also at address 0x0800, 0x1000, 0x1800, 0x2000, etc. This is a
useful feature when doing a linear memory fill, as the address pointer doesn’t have to be reset when reaching the
RAM block boundary.
Figure 12.1. EMI0CN: External Memory Interface Control
R
R
R
R
R
R/W
R/W
R/W
Reset Value
-
-
-
-
-
PGSEL2
PGSEL1
PGSEL0
00000000
SFR Address:
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0xAF
Bits 7-3:Not Used – reads 00000b
Bits 2-0:PGSEL[2:0]: XRAM Page Select Bits
The XRAM Page Select Bits provide the high byte of the 16-bit external data memory
address when using an 8-bit MOVX command, effectively selecting a 256-byte page of
RAM. The upper 5-bits are “don’t cares”, so the 2k address blocks are repeated modulo
over the entire 64k external data memory address space.
000: xxxxx000b
001: xxxxx001b
010: xxxxx010b
011: xxxxx011b
100: xxxxx100b
101: xxxxx101b
110: xxxxx110b
111: xxxxx111b
Rev. 1.7
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13. RESET SOURCES
The reset circuitry of the MCUs allows the controller to be easily placed in a predefined default condition. On entry
to this reset state, the CIP-51 halts program execution, forces the external port pins to a known state and initializes
the SFRs to their defined reset values. Interrupts and timers are disabled. On exit, the program counter (PC) is
reset, and program execution starts at location 0x0000.
All of the SFRs are reset to predefined values. The reset values of the SFR bits are defined in the SFR detailed
descriptions. The contents of internal data memory are not changed during a reset and any previously stored data is
preserved. However, since the stack pointer SFR is reset, the stack is effectively lost even though the data on the
stack are not altered.
The I/O port latches are reset to 0xFF (all logic ones), activating internal weak pull-ups which take the external I/O
pins to a high state. The weak pull-ups are enabled during and after the reset. If the source of reset is from the VDD
Monitor or writing a 1 to PORSF, the /RST pin is driven low until the end of the VDD reset timeout.
On exit from the reset state, the MCU uses the internal oscillator running at 2MHz as the system clock by default.
Refer to Section 14 for information on selecting and configuring the system clock source. The Watchdog Timer is
enabled using its longest timeout interval. (Section 13.8 details the use of the Watchdog Timer.)
There are seven sources for putting the MCU into the reset state: power-on/power-fail, external /RST pin, external
CNVSTR signal, software commanded, Comparator 0, Missing Clock Detector, and Watchdog Timer. Each reset
source is described below:
Figure 13.1. Reset Sources Diagram
VDD
CNVSTR
(Port
I/O)
Crossbar
Supply
Monitor
CNVRSEF
Supply
Reset
+
/RST
-
(wired-OR)
Timeout
Comparator 0
CP0+
CP0-
+
-
C0RSEF
Reset
Funnel
Missing
Clock
Detector
(one-
shot)
System
Clock
WDT
EN
(Software Reset)
SWRSF
EN PRE
System Reset
CIP-51
Core
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13.1. Power-on Reset
The C8051F000 family incorporates a power supply monitor that holds the MCU in the reset state until VDD rises
above the VRST level during power-up. (See Figure 13.2 for timing diagram, and refer to Table 13.1 for the
Electrical Characteristics of the power supply monitor circuit.) The /RST pin is asserted (low) until the end of the
100ms VDD Monitor timeout in order to allow the VDD supply to become stable.
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. All of the other reset
flags in the RSTSRC Register are indeterminate. PORSF is cleared by a reset from any other source. Since all
resets cause program execution to begin at the same location (0x0000), software can read the PORSF flag to
determine if a power-up was the cause of reset. The content of internal data memory should be assumed to be
undefined after a power-on reset.
13.2. Software Forced Reset
Writing a 1 to the PORSF bit forces a Power-On Reset as described in Section 13.1.
Figure 13.2. VDD Monitor Timing Diagram
2.70
2.40
VRST
2.0
1.0
t
/RST
Logic HIGH
100ms
100ms
Logic LOW
13.3. Power-fail Reset
When a power-down transition or power irregularity causes VDD to drop below VRST, the power supply monitor
will drive the /RST pin low and return the CIP-51 to the reset state (see Figure 13.2). When VDD returns to a level
above VRST, the CIP-51 will leave the reset state in the same manner as that for the power-on reset. Note that even
though internal data memory contents are not altered by the power-fail reset, it is impossible to determine if VDD
dropped below the level required for data retention. If the PORSF flag is set, the data may no longer be valid.
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13.4. External Reset
The external /RST pin provides a means for external circuitry to force the MCU into a reset state. Asserting an
active-low signal on the /RST pin will cause the MCU to enter the reset state. Although there is a weak internal
pullup, it may be desirable to provide an external pull-up and/or decoupling of the /RST pin to avoid erroneous
noise-induced resets. The MCU will remain in reset until at least 12 clock cycles after the active-low /RST signal is
removed. The PINRSF flag (RSTSRC.0) is set on exit from an external reset. The /RST pin is also 5V tolerant.
13.5. Missing Clock Detector Reset
The Missing Clock Detector is essentially a one-shot circuit that is triggered by the MCU system clock. If the
system clock goes away for more than 100µs, the one-shot will time out and generate a reset. After a Missing Clock
Detector reset, the MCDRSF flag (RSTSRC.2) will be set, signifying the MSD as the reset source; otherwise, this
bit reads 0. The state of the /RST pin is unaffected by this reset. Setting the MSCLKE bit in the OSCICN register
(see Figure 14.2) enables the Missing Clock Detector.
13.6. Comparator 0 Reset
Comparator 0 can be configured as an active-low reset input by writing a 1 to the C0RSEF flag (RSTSRC.5).
Comparator 0 should be enabled using CPT0CN.7 (see Figure 8.3) at least 20µs prior to writing to C0RSEF to
prevent any turn-on chatter on the output from generating an unwanted reset. When configured as a reset, if the
non-inverting input voltage (on CP0+) is less than the inverting input voltage (on CP0-), the MCU is put into the
reset state. After a Comparator 0 Reset, the C0RSEF flag (RSTSRC.5) will read 1 signifying Comparator 0 as the
reset source; otherwise, this bit reads 0. The state of the /RST pin is unaffected by this reset. Also, Comparator 0
can generate a reset with or without the system clock.
13.7. External CNVSTR Pin Reset
The external CNVSTR signal can be configured as an active-low reset input by writing a 1 to the CNVRSEF flag
(RSTSRC.6). The CNVSTR signal can appear on any of the P0, P1, or P2 I/O pins as described in Section 15.1.
(Note that the Crossbar must be configured for the CNVSTR signal to be routed to the appropriate Port I/O.) The
Crossbar should be configured and enabled before the CNVRSEF is set to configure CNVSTR as a reset source.
When configured as a reset, CNVSTR is active-low and level sensitive. After a CNVSTR reset, the CNVRSEF flag
(RSTSRC.6) will read 1 signifying CNVSTR as the reset source; otherwise, this bit reads 0. The state of the /RST
pin is unaffected by this reset.
13.8. Watchdog Timer Reset
The MCU includes a programmable Watchdog Timer (WDT) running off the system clock. The WDT will force
the MCU into the reset state when the watchdog timer overflows. To prevent the reset, the WDT must be restarted
by application software before the overflow occurs. If the system experiences a software/hardware malfunction
preventing the software from restarting the WDT, the WDT will overflow and cause a reset. This should prevent
the system from running out of control.
The WDT is automatically enabled and started with the default maximum time interval on exit from all resets. If
desired the WDT can be disabled by system software or locked on to prevent accidental disabling. Once locked, the
WDT cannot be disabled until the next system reset. The state of the /RST pin is unaffected by this reset.
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13.8.1. Watchdog Usage
The WDT consists of a 21-bit timer running from the programmed system clock. The timer measures the period
between specific writes to its control register. If this period exceeds the programmed limit, a WDT reset is
generated. The WDT can be enabled and disabled as needed in software, or can be permanently enabled if desired.
Watchdog features are controlled via the Watchdog Timer Control Register (WDTCN) shown in Figure 13.3.
Enable/Reset WDT
The watchdog timer is both enabled and the countdown restarted by writing 0xA5 to the WDTCN register. The
user’s application software should include periodic writes of 0xA5 to WDTCN as needed to prevent a watchdog
timer overflow. The WDT is enabled and restarted as a result of any system reset.
Disable WDT
Writing 0xDE followed by 0xAD to the WDTCN register disables the WDT. The following code segment
illustrates disabling the WDT.
CLR
MOV
MOV
EA
; disable all interrupts
WDTCN,#0DEh ; disable software
WDTCN,#0ADh ; watchdog timer
SETB EA
; re-enable interrupts
The writes of 0xDE and 0xAD must occur within 4 clock cycles of each other, or the disable operation is ignored.
Interrupts should be disabled during this procedure to avoid delay between the two writes.
Disable WDT Lockout
Writing 0xFF to WDTCN locks out the disable feature. Once locked out, the disable operation is ignored until the
next system reset. Writing 0xFF does not enable or reset the watchdog timer. Applications always intending to use
the watchdog should write 0xFF to WDTCN in their initialization code.
Setting WDT Interval
WDTCN.[2:0] control the watchdog timeout interval. The interval is given by the following equation:
43+WDTCN[2:0] x TSYSCLK , (where TSYSCLK is the system clock period).
For a 2MHz system clock, this provides an interval range of 0.032msec to 524msec. WDTCN.7 must be a 0 when
setting this interval. Reading WDTCN returns the programmed interval. WDTCN.[2:0] is 111b after a system
reset.
Figure 13.3. WDTCN: Watchdog Timer Control Register
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Bit0
Reset Value
xxxxx111
SFR Address:
0xFF
Bits7-0: WDT Control
Writing 0xA5 both enables and reloads the WDT.
Writing 0xDE followed within 4 clocks by 0xAD disables the WDT.
Writing 0xFF locks out the disable feature.
Watchdog Status Bit (when Read)
Bit4:
Reading the WDTCN.[4] bit indicates the Watchdog Timer Status.
0: WDT is inactive
1: WDT is active
Bits2-0: Watchdog Timeout Interval Bits
The WDTCN.[2:0] bits set the Watchdog Timeout Interval. When writing these bits,
WDTCN.7 must be set to 0.
Rev. 1.7
96
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 13.4. RSTSRC: Reset Source Register
R
R/W
R/W
C0RSEF
Bit5
R/W
SWRSEF
Bit4
R
R
R/W
PORSF
Bit1
R
Reset Value
JTAGRST CNVRSEF
WDTRSF
MCDRSF
PINRSF
xxxxxxxx
SFR Address:
Bit7
Bit6
Bit3
Bit2
Bit0
0xEF
(Note: Do not use read-modify-write operations on this register.)
Bit7:
Bit6:
JTAGRST. JTAG Reset Flag.
0: JTAG is not currently in reset state.
1: JTAG is in reset state.
CNVRSEF: Convert Start Reset Source Enable and Flag
Write
0: CNVSTR is not a reset source
1: CNVSTR is a reset source (active low)
Read
0: Source of prior reset was not from CNVSTR
1: Source of prior reset was from CNVSTR
C0RSEF: Comparator 0 Reset Enable and Flag
Write
Bit5:
Bit4:
0: Comparator 0 is not a reset source
1: Comparator 0 is a reset source (active low)
Read
Note: The value read from C0RSEF is not defined if Comparator 0 has not been enabled as
a reset source.
0: Source of prior reset was not from Comparator 0
1: Source of prior reset was from Comparator 0
SWRSF: Software Reset Force and Flag
Write
0: No Effect
1: Forces an internal reset. /RST pin is not effected.
Read
0: Prior reset source was not from write to the SWRSF bit.
1: Prior reset source was from write to the SWRSF bit.
WDTRSF: Watchdog Timer Reset Flag
0: Source of prior reset was not from WDT timeout.
1: Source of prior reset was from WDT timeout.
MCDRSF: Missing Clock Detector Flag
0: Source of prior reset was not from Missing Clock Detector timeout.
1: Source of prior reset was from Missing Clock Detector timeout.
PORSF: Power-On Reset Force and Flag
Write
Bit3:
Bit2:
Bit1:
0: No effect
1: Forces a Power-On Reset. /RST is driven low.
Read
0: Source of prior reset was not from POR.
1: Source of prior reset was from POR.
PINRSF: HW Pin Reset Flag
Bit0:
0: Source of prior reset was not from /RST pin.
1: Source of prior reset was from /RST pin.
97
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Table 13.1. Reset Electrical Characteristics
-40°C to +85°C unless otherwise specified.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
/RST Output Low Voltage
/RST Input High Voltage
IOL = 8.5mA, VDD = 2.7 to 3.6V
0.6
V
V
0.7 x
VDD
/RST Input Low Voltage
0.3 x
VDD
V
/RST Input Leakage Current /RST = 0.0V
VDD for /RST Output Valid
AV+ for /RST Output Valid
20
µA
V
1.0
1.0
2.40
80
V
VDD POR Threshold (VRST
Reset Time Delay
)
2.55
100
2.70
120
V
/RST rising edge after crossing reset
threshold
Time from last system clock to reset
generation
ms
Missing Clock Detector
Timeout
100
220
500
µs
Rev. 1.7
98
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
14. OSCILLATOR
Each MCU includes an internal oscillator and an external oscillator drive circuit, either of which can generate the
system clock. The MCUs boot from the internal oscillator after any reset. The internal oscillator starts up instantly.
It can be enabled/disabled and its frequency can be changed using the Internal Oscillator Control Register
(OSCICN) as shown in Figure 14.2. The internal oscillator’s electrical specifications are given in Table 14.1.
Both oscillators are disabled when the /RST pin is held low. The MCUs can run from the internal oscillator or
external oscillator, and switch between the two at will using the CLKSL bit in the OSCICN Register. The external
oscillator requires an external resonator, parallel-mode crystal, capacitor, or RC network connected to the
XTAL1/XTAL2 pins (see Figure 14.1). The oscillator circuit must be configured for one of these sources in the
OSCXCN register. An external CMOS clock can also provide the system clock via overdriving the XTAL1 pin.
The XTAL1 and XTAL2 pins are 3.6V (not 5V) tolerant. The external oscillator can be left enabled and running
even when the MCU has switched to using the internal oscillator.
Figure 14.1. Oscillator Diagram
OSCICN
VDD
EN
Internal Clock
Generator
opt. 2
AV+
SYSCLK
AV+
opt. 1
opt. 4
opt. 3
XTAL1
XTAL1
XTAL1
XTAL1
XTAL2
Input
Circuit
OSC
XTAL2
AGND
OSCXCN
99
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 14.2. OSCICN: Internal Oscillator Control Register
R/W
MSCLKE
Bit7
R/W
-
R/W
-
R
R/W
CLKSL
Bit3
R/W
IOSCEN
Bit2
R/W
IFCN1
Bit1
R/W
IFCN0
Bit0
Reset Value
IFRDY
00000100
SFR Address:
Bit6
Bit5
Bit4
0xB2
Bit7:
MSCLKE: Missing Clock Enable Bit
0: Missing Clock Detector Disabled
1: Missing Clock Detector Enabled; triggers a reset if a missing clock is detected
Bits6-5: UNUSED. Read = 00b, Write = don’t care
Bit4:
Bit3:
Bit2:
IFRDY: Internal Oscillator Frequency Ready Flag
0: Internal Oscillator Frequency not running at speed specified by the IFCN bits.
1: Internal Oscillator Frequency running at speed specified by the IFCN bits.
CLKSL: System Clock Source Select Bit
0: Uses Internal Oscillator as System Clock.
1: Uses External Oscillator as System Clock.
IOSCEN: Internal Oscillator Enable Bit
0: Internal Oscillator Disabled
1: Internal Oscillator Enabled
Bits1-0: IFCN1-0: Internal Oscillator Frequency Control Bits
00: Internal Oscillator typical frequency is 2MHz.
01: Internal Oscillator typical frequency is 4MHz.
10: Internal Oscillator typical frequency is 8MHz.
11: Internal Oscillator typical frequency is 16MHz.
Table 14.1. Internal Oscillator Electrical Characteristics
-40°C to +85°C unless otherwise specified.
PARAMETER
CONDITIONS
OSCICN.[1:0] = 00
MIN
1.5
TYP
2
MAX
UNITS
Internal Oscillator
Frequency
2.4
4.8
MHz
OSCICN.[1:0] = 01
3.1
4
OSCICN.[1:0] = 10
OSCICN.[1:0] = 11
OSCICN.2 = 1
6.2
8
9.6
12.3
16
200
19.2
Internal Oscillator Current
Consumption (from VDD)
Internal Oscillator
µA
ppm/°C
%/V
4
Temperature Stability
Internal Oscillator Power
Supply (VDD) Stability
6.4
Rev. 1.7
100
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 14.3. OSCXCN: External Oscillator Control Register
R
R/W
XOSCMD2
Bit6
R/W
XOSCMD1
Bit5
R/W
XOSCMD0
Bit4
R/W
-
R/W
XFCN2
Bit2
R/W
XFCN1
Bit1
R/W
XFCN0
Bit0
Reset Value
XTLVLD
00110000
SFR Address:
Bit7
Bit3
0xB1
Bit7:
XTLVLD: Crystal Oscillator Valid Flag
(Valid only when XOSCMD = 1xx.)
0: Crystal Oscillator is unused or not yet stable
1: Crystal Oscillator is running and stable (should read 1ms after Crystal Oscillator is
enabled to avoid transient condition).
Bits6-4: XOSCMD2-0: External Oscillator Mode Bits
00x: Off. XTAL1 pin is grounded internally.
010: System Clock from External CMOS Clock on XTAL1 pin.
011: System Clock from External CMOS Clock on XTAL1 pin divided by 2.
10x: RC/C Oscillator Mode with divide by 2 stage.
110: Crystal Oscillator Mode
111: Crystal Oscillator Mode with divide by 2 stage.
Bit3:
RESERVED. Read = undefined, Write = don’t care
Bits2-0: XFCN2-0: External Oscillator Frequency Control Bits
000-111: see table below
XFCN Crystal (XOSCMD =
11x)
RC (XOSCMD = 10x)
C (XOSCMD = 10x)
000
001
010
011
100
101
110
111
K Factor = 0.44
K Factor = 1.4
K Factor = 4.4
K Factor = 13
K Factor = 38
K Factor = 100
K Factor = 420
K Factor = 1400
f ≤ 12.5kHz
f ≤ 25kHz
12.5kHz < f ≤ 30.3kHz
30.35kHz < f ≤ 93.8kHz
93.8kHz < f ≤ 267kHz
267kHz < f ≤ 722kHz
722kHz < f ≤ 2.23MHz
2.23MHz < f ≤ 6.74MHz 800kHz < f ≤ 1.6MHz
f > 6.74MHz
25kHz < f ≤ 50kHz
50kHz < f ≤ 100kHz
100kHz < f ≤ 200kHz
200kHz < f ≤ 400kHz
400kHz < f ≤ 800kHz
1.6MHz < f ≤ 3.2MHz
CRYSTAL MODE (Circuit from Figure 14.1, Option 1; XOSCMD = 11x)
Choose XFCN value to match the crystal or ceramic resonator frequency.
RC MODE (Circuit from Figure 14.1, Option 2; XOSCMD = 10x)
Choose oscillation frequency range where:
f = 1.23(103) / (R * C), where
f = frequency of oscillation in MHz
C = capacitor value in pF
R = Pull-up resistor value in kΩ
C MODE (Circuit from Figure 14.1, Option 3; XOSCMD = 10x)
Choose K Factor (KF) for the oscillation frequency desired:
f = KF / (C * AV+), where
f = frequency of oscillation in MHz
C = capacitor value on XTAL1, XTAL2 pins in pF
AV+ = Analog Power Supply on MCU in volts
101
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
14.1. External Crystal Example
If a crystal or ceramic resonator were used to generate the system clock for the MCU, the circuit would be as shown
in Figure 14.1, Option 1. For an ECS-110.5-20-4 crystal, the resonate frequency is 11.0592MHz, the intrinsic
capacitance is 7pF, and the ESR is 60Ω. The compensation capacitors should be 33pF each, and the PWB parasitic
capacitance is estimated to be 2pF. The appropriate External Oscillator Frequency Control value (XFCN) from the
Crystal column in the table in Figure 14.3 (OSCXCN Register) should be 111b.
Because the oscillator detect circuitry needs time to settle after the crystal oscillator is enabled, software should wait
at least 1ms between enabling the crystal oscillator and polling the XTLVLD bit. The recommend procedure is:
1. Enable the external oscillator
2. Wait at least 1 ms
3. Poll for XTLVLD '0' ==> '1'
4. Switch to the external oscillator
Switching to the external oscillator before the crystal oscillator has stabilized could result in unpredictable behavior.
NOTE: Crystal oscillator circuits are quite sensitive to PCB layout. The crystal should be placed as close as possible
to the XTAL pins on the device, keeping the traces as short as possible and shielded with ground plane from any
other traces which could introduce noise or interference.
14.2. External RC Example
If an external RC network were used to generate the system clock for the MCU, the circuit would be as shown in
Figure 14.1, Option 2. The capacitor must be no greater than 100pF, but using a very small capacitor will increase
the frequency drift due to the PWB parasitic capacitance. To determine the required External Oscillator Frequency
Control value (XFCN) in the OSCXCN Register, first select the RC network value to produce the desired frequency
of oscillation. If the frequency desired is 100kHz, let R = 246kΩ and C = 50pF:
f = 1.23(103)/RC = 1.23(103) / [246 * 50] = 0.1MHz = 100kHz
XFCN ≥ log2(f/25kHz)
XFCN ≥ log2(100kHz/25kHz) = log2(4)
XFCN ≥ 2, or code 010
14.3. External Capacitor Example
If an external capacitor were used to generate the system clock for the MCU, the circuit would be as shown in
Figure 14.1, Option 3. The capacitor must be no greater than 100pF, but using a very small capacitor will increase
the frequency inaccuracy due to the PWB parasitic capacitance. To determine the required External Oscillator
Frequency Control value (XFCN) in the OSCXCN Register, select the capacitor to be used and find the frequency
of oscillation from the equations below. Assume AV+ = 3.0V and C = 50pF:
f = KF / (C * VDD) = KF / (50 * 3)
f = KF / 150
If a frequency of roughly 90kHz is desired, select the K Factor from the table in Figure 14.3 as KF = 13:
f = 13 /150 = 0.087MHz, or 87kHz
Therefore, the XFCN value to use in this example is 011.
Rev. 1.7
102
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
15. PORT INPUT/OUTPUT
The MCUs have a wide array of digital resources, which are available through four digital I/O ports, P0, P1, P2 and
P3. Each of the pins on Ports 0, 1, and 2 can be defined as either its corresponding port I/O or one of the internal
digital resources assigned as shown in Figure 15.1. The designer has complete control over which functions are
assigned, limited only by the number of physical I/O pins available on the selected package (the
C8051F000/05/10/15 have all four ports pinned out, the F001/06/11/16 have P0 and P1, and the F002/07/12/17
have P0). This resource assignment flexibility is achieved through the use of a Priority CrossBar Decoder. (Note
that the state of a Port I/O pin can always be read in the corresponding Port latch regardless of the Crossbar
settings).
The CrossBar assigns the selected internal digital resources to the I/O pins based on the Priority Decode Table 15.1.
The registers XBR0, XBR1, and XBR2, defined in Figure 15.3, Figure 15.4, and Figure 15.5 are used to select an
internal digital function or let an I/O pin default to being a Port I/O. The crossbar functions identically for each
MCU, with the caveat that P2 is not pinned out on the F001/06/11/16, and both P1 and P2 are not pinned out on the
F002/07/12/17. Digital resources assigned to port pins that are not pinned out cannot be accessed.
All Port I/Os are 5V tolerant (Refer to Figure 15.2 for the port cell circuit.) The Port I/O cells are configured as
either push-pull or open-drain in the Port Configuration Registers (PRT0CF, PRT1CF, PRT2CF, PRT3CF).
Complete Electrical Specifications for Port I/O are given in Table 15.2.
15.1. Priority Cross Bar Decoder
One of the design goals of this MCU family was to make the entire palette of digital resources available to the
designer even on reduced pin count packages. The Priority CrossBar Decoder provides an elegant solution to the
problem of connecting the internal digital resources to the physical I/O pins.
The Priority CrossBar Decode (Table 15.1) assigns a priority to each I/O function, starting at the top with the
SMBus. As the table illustrates, when selected, its two signals will be assigned to Pin 0 and 1 of I/O Port 0. The
decoder always fills I/O bits from LSB to MSB starting with Port 0, then Port 1, finishing if necessary with Port 2.
If you choose not to use a resource, the next function down on the table will fill the priority slot. In this way it is
possible to choose only the functions required by the design, making full use of the available I/O pins. Also, any
extra Port I/O are grouped together for more convenient use in application code.
Registers XBR0, XBR1 and XBR2 are used to assign the digital I/O resources to the physical I/O Port pins. It is
important to understand that when the SMBus, SPI Bus, or UART is selected, the crossbar assigns all pins
associated with the selected bus. It would be impossible for instance to assign the RX pin from the UART function
without also assigning the TX function. Standard Port I/Os appear contiguously after the prioritized functions have
been assigned. For example, if you choose functions that take the first 14 Port I/O (P0.[7:0], P1.[5:0]), you would
have 18 Port I/O left unused by the crossbar (P1.[7:6], P2 and P3).
15.2. Port I/O Initialization
Port I/O initialization is straightforward. Registers XBR0, XBR1 and XBR2 must be loaded with the appropriate
values to select the digital I/O functions required by the design. Setting the XBARE bit in XBR2 to 1 enables the
CrossBar. Until the Crossbar is enabled, the external pins remain as standard Ports in input mode regardless
of the XBRn Register settings. For given XBRn Register settings, one can determine the I/O pin-out using the
Priority Decode Table; as an alternative, the Code Configuration Wizard function of the IDE software will
determine the Port I/O pin-assignments based on the XBRn Register settings.
The output driver characteristics of the I/O pins are defined using the Port Configuration Registers PRT0CF,
PRT1CF, PRT2CF and PRT3CF (see Figure 15.7, Figure 15.9, Figure 15.12, and Figure 15.14). Each Port Output
driver can be configured as either Open Drain or Push-Pull. This is required even for the digital resources selected
in the XBRn registers and is not automatic. The only exception to this is the SMBus (SDA, SCL) and UART
Receive (RX, when in mode 0) pins which are Open-drain regardless of the PRTnCF settings. When the
WEAKPUD bit in XBR2 is 0, a weak pullup is enabled for all Port I/O configured as open-drain. WEAKPUD does
103
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
not affect the push-pull Port I/O. Furthermore, the weak pullup is turned off on an open-drain output that is driving
a 0 to avoid unnecessary power dissipation.
The third and final step is to initialize the individual resources selected using the appropriate setup registers.
Initialization procedures for the various digital resources may be found in the detailed explanation of each available
function. The reset state of each register is shown in the figures that describe each individual register.
Figure 15.1. Port I/O Functional Block Diagram
2
SMBus
SPI
XBR0, XBR1,
PRT0CF, PRT1CF,
PRT2CF Registers
Highest
Priority
XBR2 Registers
4
2
6
External
Pins
UART
PCA
Priority
Decoder
2
Comptr.
Outputs
P0.0
Highest
Priority
P0
I/O
8
8
8
Cells
P0.7
T0, T1, T2,
T2EX,
Digital
Crossbar
/INT0,
6
/INT1
P1.0
P1.7
P1
I/O
Lowest
Priority
/SYSCLK
CNVSTR
Cells
8
P2.0
P2.7
P2
I/O
Lowest
Priority
P0
Cells
(P0.0-P0.7)
8
P1
P2
P3
(P1.0-P1.7)
8
PRT3CF
Register
Port
Latches
(P2.0-P2.7)
8
P3.0
P3.7
P3
I/O
Cells
(P3.0-P3.7)
Figure 15.2. Port I/O Cell Block Diagram
WEAKPUD
VDD
VDD
PUSH-PULL
/PORT-OUTENABLE
(WEAK)
PORT
PAD
PORT-OUTPUT
VDD
DGND
PORT-INPUT
Rev. 1.7
104
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Table 15.1. Crossbar Priority Decode
P0
P1
P2
PIN I/O
SDA
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
●
SCL
●
SCK
MISO
MOSI
NSS
TX
● ●
● ●
● ●
● ●
● ● ● ●
● ● ● ●
● ● ● ● ●
● ● ● ● ●
● ● ● ● ●
● ● ● ● ●
● ● ● ● ●
●●●●●●●●●●●●●●
●●●●●●●●●●●●●●●
●●●●●●●●●●●●●●●●
●●●●●●●●●●●●●●●●●
●●●●●●●●●●●●●●●●●●
●●●●●●●●●●●●●●●●●●●
●●●●●●●●●●●●●●●●●●●●
●●●●●●●●●●●●●●●●●●●●●
RX
CEX0
CEX1
CEX2
CEX3
CEX4
ECI
CP0
CP1
T0
/INT0
T1
/INT1
T2
T2EX
/SYSCLK
CNVSTR
●●●●●●●●●●●●●●●●●●●●●●
●●●●●●●●●●●●●●●●●●●●●●●
●●●●●●●●●●●●●●●●●●●●●●●●
In the Priority Decode Table, a dot (•) is used to show the external Port I/O pin (column) to which each signal (row)
can be assigned by the user application code via programming registers XBR2, XBR1, and XBR0.
105
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 15.3. XBR0: Port I/O CrossBar Register 0
R/W
R/W
R/W
Bit5
R/W
R/W
Bit3
R/W
R/W
R/W
Reset Value
00000000
SFR Address:
0xE1
CP0OEN
ECIE
PCA0ME
UARTEN SPI0OEN SMB0OEN
Bit7
Bit6
Bit4
Bit2
Bit1
Bit0
Bit7:
Bit6:
CP0OEN: Comparator 0 Output Enable Bit
0: CP0 unavailable at Port pin.
1: CP0 routed to Port Pin.
ECIE: PCA0 Counter Input Enable Bit
0: ECI unavailable at Port pin.
1: ECI routed to Port Pin.
Bits3-5: PCA0ME: PCA Module I/O Enable Bits
000: All PCA I/O unavailable at Port pins.
001: CEX0 routed to Port Pin.
010: CEX0, CEX1 routed to 2 Port Pins.
011: CEX0, CEX1, CEX2 routed to 3 Port Pins.
100: CEX0, CEX1, CEX2, CEX3 routed to 4 Port Pins.
101: CEX0, CEX1, CEX2, CEX3, CEX4 routed to 5 Port Pins.
110: RESERVED
111: RESERVED
Bit2:
Bit1:
Bit0:
UARTEN: UART I/O Enable Bit
0: UART I/O unavailable at Port pins.
1: RX, TX routed to 2 Port Pins.
SPI0OEN: SPI Bus I/O Enable Bit
0: SPI I/O unavailable at Port pins.
1: MISO, MOSI, SCK, and NSS routed to 4 Port Pins.
SMB0OEN: SMBus Bus I/O Enable Bit
0: SMBus I/O unavailable at P0.0, P0.1.
1: SDA routed to P0.0, SCL routed to P0.1.
Rev. 1.7
106
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 15.4. XBR1: Port I/O CrossBar Register 1
R/W
SYSCKE
Bit7
R/W
T2EXE
Bit6
R/W
T2E
Bit5
R/W
INT1E
Bit4
R/W
T1E
Bit3
R/W
INT0E
Bit2
R/W
T0E
Bit1
R/W
CP1OEN
Bit0
Reset Value
00000000
SFR Address:
0xE2
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
SYSCKE: SYSCLK Output Enable Bit
0: SYSCLK unavailable at Port pin.
1: SYSCLK output routed to Port Pin.
T2EXE: T2EX Enable Bit
0: T2EX unavailable at Port pin.
1: T2EX routed to Port Pin.
T2E: T2 Enable Bit
0: T2 unavailable at Port pin.
1: T2 routed to Port Pin.
INT1E: /INT1 Enable Bit
0: /INT1 unavailable at Port pin.
1: /INT1 routed to Port Pin.
T1E: T1 Enable Bit
0: T1 unavailable at Port pin.
1: T1 routed to Port Pin.
INT0E: /INT0 Enable Bit
0: /INT0 unavailable at Port pin.
1: /INT0 routed to Port Pin.
T0E: T0 Enable Bit
0: T0 unavailable at Port pin.
1: T0 routed to Port Pin.
CP1OEN: Comparator 1 Output Enable Bit
0: CP1 unavailable at Port pin.
1: CP1 routed to Port Pin.
107
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 15.5. XBR2: Port I/O CrossBar Register 2
R/W
WEAKPUD
Bit7
R/W
XBARE
Bit6
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
CNVSTE
Bit0
Reset Value
00000000
SFR Address:
Bit5
Bit4
Bit3
Bit2
Bit1
0xE3
Bit7:
Bit6:
WEAKPUD: Port I/O Weak Pull-up Disable Bit
0: Weak Pull-ups Enabled (except for Ports whose I/O are configured as push-pull)
1: Weak Pull-ups Disabled
XBARE: Crossbar Enable Bit
0: Crossbar Disabled
1: Crossbar Enabled
Bits5-1: UNUSED. Read = 00000b, Write = don’t care.
Bit0:
CNVSTE: ADC Convert Start Input Enable Bit
0: CNVSTR unavailable at Port pin.
1: CNVSTR routed to Port Pin.
Example Usage of XBR0, XBR1, XBR2:
When selected, the digital resources fill the Port I/O pins in order (top to bottom as shown in
Table 15.1) starting with P0.0 through P0.7, and then P1.0 through P1.7, and finally P2.0
through P2.7. If the digital resources are not mapped to the Port I/O pins, they default to their
matching internal Port Register bits.
Example1: If XBR0 = 0x11, XBR1 = 0x00, and XBR2 = 0x40:
P0.0=SDA, P0.1=SCL, P0.2=CEX0, P0.3=CEX1, P0.4 … P2.7 map to corresponding Port I/O.
Example2: If XBR0 = 0x80, XBR1 = 0x04, and XBR2 = 0x41:
P0.0=CP0, P0.1=/INT0, P0.2 = CNVSTR, P0.3 … P2.7 map to corresponding Port I/O.
Rev. 1.7
108
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
15.3. General Purpose Port I/O
Each MCU has four byte-wide, bi-directional parallel ports that can be used general purpose I/O. Each port is
accessed through a corresponding special function register (SFR) that is both byte addressable and bit addressable.
When writing to a port, the value written to the SFR is latched to maintain the output data value at each pin. When
reading, the logic levels of the port’s input pins are returned regardless of the XBRn settings (i.e. even when the pin
is assigned to another signal by the Crossbar, the Port Register can always still read its corresponding Port I/O pin).
The exception to this is the execution of the read-modify-write instructions. The read-modify-write instructions
when operating on a port SFR are the following: ANL, ORL, XRL, JBC, CPL, INC, DEC, DJNZ and MOV, CLR
or SET, when the destination is an individual bit in a port SFR. For these instructions, the value of the port register
(not the pin) is read, modified, and written back to the SFR.
15.4. Configuring Ports Which are not Pinned Out
P2 and P3 are not pinned out on the F001/06/11/16. P1, P2, and P3 are not pinned out on the F002/07/12/17. These
port registers (and corresponding interrupts, where applicable) are still available for software use in these reduced
pin count MCUs. Whether used or not in software, it is recommended not to let these port drivers go to high
impedance state. This is prevented after reset by having the weak pull-ups enabled as described in the XBR2
register. It is recommended that each output driver for ports not pinned out should be configured as push-pull using
the corresponding PRTnCF register. This will inhibit a high impedance state even if the weak pull-up is disabled.
Figure 15.6. P0: Port0 Register
R/W
P0.7
Bit7
R/W
P0.6
Bit6
R/W
P0.5
Bit5
R/W
P0.4
Bit4
R/W
P0.3
Bit3
R/W
P0.2
Bit2
R/W
P0.1
Bit1
R/W
P0.0
Reset Value
11111111
SFR Address:
Bit0
(bit addressable)
0x80
Bits7-0: P0.[7:0]
(Write – Output appears on I/O pins per XBR0, XBR1, and XBR2 Registers)
0: Logic Low Output.
1: Logic High Output (high-impedance if corresponding PRT0CF.n bit = 0)
(Read – Regardless of XBR0, XBR1, and XBR2 Register settings).
0: P0.n pin is logic low.
1: P0.n pin is logic high.
Figure 15.7. PRT0CF: Port0 Configuration Register
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Bit0
Reset Value
00000000
SFR Address:
0xA4
Bits7-0: PRT0CF.[7:0]: Output Configuration Bits for P0.7-P0.0 (respectively)
0: Corresponding P0.n Output mode is Open-Drain.
1: Corresponding P0.n Output mode is Push-Pull.
(Note: When SDA, SCL, and RX appear on any of the P0 I/O, each are open-drain
regardless of the value of PRT0CF).
109
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 15.8. P1: Port1 Register
R/W
P1.7
Bit7
R/W
P1.6
Bit6
R/W
P1.5
Bit5
R/W
P1.4
Bit4
R/W
P1.3
Bit3
R/W
P1.2
Bit2
R/W
P1.1
Bit1
R/W
P1.0
Reset Value
11111111
SFR Address:
Bit0
(bit addressable)
0x90
Bits7-0: P1.[7:0]
(Write – Output appears on I/O pins per XBR0, XBR1, and XBR2 registers)
0: Logic Low Output.
1: Logic High Output (high-impedance if corresponding PRT1CF.n bit = 0)
(Read – Regardless of XBR0, XBR1, and XBR2 Register settings).
0: P1.n pin is logic low.
1: P1.n pin is logic high.
Figure 15.9. PRT1CF: Port1 Configuration Register
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Bit0
Reset Value
00000000
SFR Address:
0xA5
Bits7-0: PRT1CF.[7:0]: Output Configuration Bits for P1.7-P1.0 (respectively)
0: Corresponding P1.n Output mode is Open-Drain.
1: Corresponding P1.n Output mode is Push-Pull.
Figure 15.10. PRT1IF: Port1 Interrupt Flag Register
R/W
IE7
Bit7
R/W
IE6
Bit6
R/W
IE5
Bit5
R/W
IE4
Bit4
R/W
-
R/W
-
R/W
-
R/W
-
Reset Value
00000000
SFR Address:
Bit3
Bit2
Bit1
Bit0
0xAD
Bit7:
Bit6:
Bit5:
Bit4:
IE7: External Interrupt 7 Pending Flag.
0: No falling edge detected on P1.7.
1: This flag is set by hardware when a falling edge on P1.7 is detected.
IE6: External Interrupt 6 Pending Flag.
0: No falling edge detected on P1.6.
1: This flag is set by hardware when a falling edge on P1.6 is detected.
IE5: External Interrupt 5 Pending Flag.
0: No falling edge detected on P1.5.
1: This flag is set by hardware when a falling edge on P1.5 is detected.
IE4: External Interrupt 4 Pending Flag.
0: No falling edge detected on P1.4.
1: This flag is set by hardware when a falling edge on P1.4 is detected.
Bits3-0: UNUSED. Read = 0000b, Write = don’t care.
Rev. 1.7
110
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 15.11. P2: Port2 Register
R/W
P2.7
Bit7
R/W
P2.6
Bit6
R/W
P2.5
Bit
R/W
P2.4
Bit4
R/W
P2.3
Bit3
R/W
P2.2
Bit2
R/W
P2.1
Bit1
R/W
P2.0
Reset Value
11111111
SFR Address:
Bit0
(bit addressable)
0xA0
Bits7-0: P2.[7:0]
(Write – Output appears on I/O pins per XBR0, XBR1, and XBR2 registers)
0: Logic Low Output.
1: Logic High Output (high-impedance if corresponding PRT2CF.n bit = 0)
(Read – Regardless of XBR0, XBR1, and XBR2 Register settings).
0: P2.n is logic low.
1: P2.n is logic high.
Figure 15.12. PRT2CF: Port2 Configuration Register
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Bit0
Reset Value
00000000
SFR Address:
0xA6
Bits7-0: PRT2CF.[7:0]: Output Configuration Bits for P2.7-P2.0 (respectively)
0: Corresponding P2.n Output mode is Open-Drain.
1: Corresponding P2.n Output mode is Push-Pull.
111
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 15.13. P3: Port3 Register
R/W
P3.7
Bit7
R/W
P3.6
Bit6
R/W
P3.5
Bit5
R/W
P3.4
Bit4
R/W
P3.3
Bit3
R/W
P3.2
Bit2
R/W
P3.1
Bit1
R/W
P3.0
Reset Value
11111111
SFR Address:
Bit0
(bit addressable)
0xB0
Bits7-0: P3.[7:0]
(Write)
0: Logic Low Output.
1: Logic High Output (high-impedance if corresponding PRT3CF.n bit = 0)
(Read)
0: P3.n is logic low.
1: P3.n is logic high.
Figure 15.14. PRT3CF: Port3 Configuration Register
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Bit0
Reset Value
00000000
SFR Address:
0xA7
Bits7-0: PRT3CF.[7:0]: Output Configuration Bits for P3.7-P3.0 (respectively)
0: Corresponding P3.n Output mode is Open-Drain.
1: Corresponding P3.n Output mode is Push-Pull.
Table 15.2. Port I/O DC Electrical Characteristics
VDD = 2.7 to 3.6V, -40°C to +85°C unless otherwise specified.
PARAMETER
CONDITIONS
MIN
VDD –
0.1
TYP
MAX
UNITS
Output High Voltage
IOH = -10uA, Port I/O push-pull
V
IOH = -3mA, Port I/O push-pull
IOH = -10mA, Port I/O push-pull
VDD –
0.7
VDD –
0.8
Output Low Voltage
IOL = 10uA
IOL = 8.5mA
IOL = 25mA
0.1
0.6
V
1.0
Input High Voltage
Input Low Voltage
Input Leakage Current
0.7 x
VDD
V
V
0.3 x
VDD
DGND < Port Pin < VDD, Pin Tri-state
Weak Pull-up Off
µA
±1
Weak Pull-up On
30
5
Capacitive Loading
pF
Rev. 1.7
112
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
16. SMBus / I2C Bus
The SMBus serial I/O interface is compliant with the System Management Bus Specification, version 1.1. It is a
two-wire, bi-directional serial bus, which is also compatible with the I2C serial bus. Reads and writes to the
interface by the system controller are byte oriented with the SMBus interface autonomously controlling the serial
transfer of the data. Data can be transferred at up to 1/8th of the system clock if desired (this can be faster than
allowed by the SMBus specification, depending on the system clock used). A method of extending the clock-low
duration is used to accommodate devices with different speed capabilities on the same bus.
Two types of data transfers are possible: data transfers from a master transmitter to an addressed slave receiver, and
data transfers from an addressed slave transmitter to a master receiver. The master device initiates both types of
data transfers and provides the serial clock pulses. The SMBus interface may operate as a master or a slave.
Multiple master devices on the same bus are also supported. If two or more masters attempt to initiate a data
transfer simultaneously, an arbitration scheme is employed with a single master always winning the arbitration.
Figure 16.1. SMBus Block Diagram
SFR Bus
SMB0CN
SMB0STA
SMB0CR
B
U
S
Y
E
N
S
M
B
S
T
A
S
T
S
I
A
A
F
T
E
T
O
E
S
T
A
7
S
T
A
6
S
T
A
5
S
T
A
4
S
T
A
3
S
T
A
2
S
T
A
1
S
T
A
0
C
R
7
C
R
6
C
R
5
C
R
4
C
R
3
C
R
2
C
R
1
C
R
0
O
Clock Divide
Logic
SYSCLK
SCL
FILTER
SMBUS CONTROL LOGIC
Arbitration
SMBUS
IRQ
Interrupt
Request
SCL Synchronization
Status Generation
SCL Generation (Master Mode)
IRQ Generation
SCL
Control
N
SDA
Data Path
Control
Control
C
R
O
S
S
B
A
R
Port I/O
B
A
B
A
0000000b
7 MSBs
8
7
SMB0DAT
7 6 5 4 3 2 1 0
SDA
FILTER
8
8
1
0
S
L
V
6
S
L
V
5
S
L
V
4
S
L
V
3
S
L
V
2
S
L
V
1
S
L
V
0
N
G
C
Read
SMB0DAT
Write to
SMB0ADR
SMB0DAT
SFR Bus
113
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 16.2 shows a typical SMBus configuration. The SMBus interface will work at any voltage between 3.0V
and 5.0V and different devices on the bus may operate at different voltage levels. The SCL (serial clock) and SDA
(serial data) lines are bi-directional. They must be connected to a positive power supply voltage through a pull-up
resistor or similar circuit. When the bus is free, both lines are pulled high. Every device connected to the bus must
have an open-drain or open-collector output for both the SCL and SDA lines. The maximum number of devices on
the bus is limited only by the requirement that the rise and fall times on the bus will not exceed 300ns and 1000ns,
respectively.
Figure 16.2. Typical SMBus Configuration
VDD = 5V
VDD = 3V
VDD = 5V
VDD = 3V
Master
Device
Slave
Slave
Device 1
Device 2
SDA
SCL
16.1. Supporting Documents
It is assumed the reader is familiar with or has access to the following supporting documents:
1. The I2C-bus and how to use it (including specifications), Philips Semiconductor.
2. The I2C-Bus Specification -- Version 2.0, Philips Semiconductor.
3. System Management Bus Specification -- Version 1.1, SBS Implementers Forum.
Rev. 1.7
114
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
16.2. Operation
A typical SMBus transaction consists of a START condition, followed by an address byte, one or more bytes of
data, and a STOP condition. The address byte and each of the data bytes are followed by an ACKNOWLEDGE bit
from the receiver. The address byte consists of a 7-bit address plus a direction bit. The direction bit (R/W)
occupies the least-significant bit position of the address. The direction bit is set to logic 1 to indicate a “READ”
operation and cleared to logic 0 to indicate a “WRITE” operation. A general call address (0x00 +R/W) is
recognized by all slave devices allowing a master to address multiple slave devices simultaneously.
All transactions are initiated by the master, with one or more addressed slave devices as the target. The master
generates the START condition and then transmits the address and direction bit. If the transaction is a WRITE
operation from the master to the slave, the master transmits the data a byte at a time waiting for an
ACKNOWLEDGE from the slave at the end of each byte. If it is a READ operation, the slave transmits the data
waiting for an ACKNOWLEDGE from the master at the end of each byte. At the end of the data transfer, the
master generates a STOP condition to terminate the transaction and free the bus. Figure 16.3 illustrates a typical
SMBus transaction.
Figure 16.3. SMBus Transaction
START
SLAVE ADDR R/W
ACK
DATA
ACK
DATA
NACK
STOP
The SMBus interface may be configured to operate as either a master or a slave. At any particular time, it will be
operating in one of the following four modes:
16.2.1. Master Transmitter Mode
Serial data is transmitted on SDA while the serial clock is output on SCL. The first byte transmitted contains the
address of the target slave device and the data direction bit. In this case the data direction bit (R/W) will be logic 0
to indicate a “WRITE” operation. The master then transmits one or more bytes of serial data. After each byte is
transmitted, an acknowledge bit is generated by the slave. To indicate the beginning and the end of the serial
transfer, the master device outputs START and STOP conditions.
16.2.2. Master Receiver Mode
Serial data is received on SDA while the serial clock is output on SCL. The first byte is transmitted by the master
and contains the address of the target slave and the data direction bit. In this case the data direction bit (R/W) will
be logic 1 to indicate a “READ” operation. Serial data is then received from the slave on SDA while the master
outputs the serial clock. The slave transmits one or more bytes of serial data. After each byte is received, an
acknowledge bit is transmitted by the master. The master outputs START and STOP conditions to indicate the
beginning and end of the serial transfer.
16.2.3. Slave Transmitter Mode
Serial data is transmitted on SDA while the serial clock is received on SCL. First, a byte is received that contains an
address and data direction bit. In this case the data direction bit (R/W) will be logic 1 to indicate a “READ”
operation. If the received address matches the slave’s assigned address (or a general call address is received) one or
more bytes of serial data are transmitted to the master. After each byte is received, an acknowledge bit is
transmitted by the master. The master outputs START and STOP conditions to indicate the beginning and end of
the serial transfer.
115
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
16.2.4. Slave Receiver Mode
Serial data is received on SDA while the serial clock is received on SCL. First, a byte is received that contains an
address and data direction bit. In this case the data direction bit (R/W) will be logic 0 to indicate a “WRITE”
operation. If the received address matches the slave’s assigned address (or a general call address is received) one or
more bytes of serial data are received from the master. After each byte is received, an acknowledge bit is
transmitted by the slave. The master outputs START and STOP conditions to indicate the beginning and end of the
serial transfer.
16.3. Arbitration
A master may start a transfer only if the bus is free. The bus is free after a STOP condition or after the SCL and
SDA lines remains high for a specified time. Two or more master devices may attempt to generate a START
condition at the same time. Since the devices that generated the START condition may not be aware that other
masters are contending for the bus, an arbitration scheme is employed. The master devices continue to transmit
until one of the masters transmits a HIGH level, while the other(s) master transmits a LOW level on SDA. The first
master(s) transmitting the HIGH level on SDA looses the arbitration and is required to give up the bus.
16.4. Clock Low Extension
SMBus provides a clock synchronization mechanism, similar to I2C, which allows devices with different speed
capabilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow slower slave
devices to communicate with faster masters. The slave can hold the SCL line LOW to extend the clock low period,
effectively decreasing the serial clock frequency.
16.5. Timeouts
16.5.1. SCL Low Timeout
If the SCL line is held low by a slave device on the bus, no further communication is possible. Furthermore, the
master cannot force the SCL line high to correct the error condition. To solve this problem, the SMBus protocol
specifies that devices participating in a transfer must detect any clock cycle held low longer than 25ms as a
“timeout” condition. Devices that have detected the timeout condition must reset the communication no later than
10ms after detecting the timeout condition.
One of the MCU’s general-purpose timers, operating in 16-bit auto-reload mode, can be used to monitor the SCL
line for this timeout condition. Timer 3 is specifically designed for this purpose. (Refer to the Timer 3 Section
19.3. for detailed information on Timer 3 operation.)
16.5.2. SCL High (SMBus Free) Timeout
The SMBus specification stipulates that if a device holds the SCL and SDA lines high for more that 50usec, the bus
is designated as free. The SMB0CR register is used to detect this condition when the FTE bit in SMB0CN is set.
16.6. SMBus Special Function Registers
The SMBus serial interface is accessed and controlled through five SFRs: SMB0CN Control Register, SMB0CR
Clock Rate Register, SMB0ADR Address Register, SMB0DAT Data Register and SMB0STA Status Register. The
system device may have one or more SMBus serial interfaces implemented. The five special function registers
related to the operation of the SMBus interface are described in the following section.
Rev. 1.7
116
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
16.6.1. Control Register
The SMBus Control register SMB0CN is used to configure and control the SMBus interface. All of the bits in the
register can be read or written by software. Two of the control bits are also affected by the SMBus hardware. The
Serial Interrupt flag (SI, SMB0CN.3) is set to logic 1 by the hardware when a valid serial interrupt condition occurs.
It can only be cleared by software. The Stop flag (STO, SMB0CN.4) is cleared to logic 0 by hardware when a
STOP condition is present on the bus.
Setting the ENSMB flag to logic 1 enables the SMBus interface. Clearing the ENSMB flag to logic 0 disables the
SMBus interface and removes it from the bus. Momentarily clearing the ENSMB flag and then resetting it to logic
1 will reset a SMBus communication. However, ENSMB should not be used to temporarily remove a device from
the bus since the bus state information will be lost. Instead, the Assert Acknowledge (AA) flag should be used to
temporarily remove the device from the bus (see description of AA flag below).
Setting the Start flag (STA, SMB0CN.5) to logic 1 will put the SMBus in a master mode. If the bus is free, the
SMBus hardware will generate a START condition. If the bus is not free, the SMBus hardware waits for a STOP
condition to free the bus and then generates a START condition after a 5µs delay per the SMB0CR value. (In
accordance with the SMBus protocol, the SMBus interface also considers the bus free if the bus is idle for 50µs and
no STOP condition was recognized.) If STA is set to logic 1 while the SMBus is in master mode and one or more
bytes have been transferred, a repeated START condition will be generated. To ensure proper operation, the STO
flag should be explicitly cleared before setting STA to a logic 1.
When the Stop flag (STO, SMB0CN.4) is set to logic 1 while the SMBus interface is in master mode, the hardware
generates a STOP condition on the SMBus. In a slave mode, the STO flag may be used to recover from an error
condition. In this case, a STOP condition is not generated on the SMBus, but the SMBus hardware behaves as if a
STOP condition has been received and enters the “not addressed” slave receiver mode. The SMBus hardware
automatically clears the STO flag to logic 0 when a STOP condition is detected on the bus.
The Serial Interrupt flag (SI, SMB0CN.3) is set to logic 1 by hardware when the SMBus interface enters one of 27
possible states. If interrupts are enabled for the SMBus interface, an interrupt request is generated when the SI flag
is set. The SI flag must be cleared by software. While SI is set to logic 1, the clock-low period of the serial clock
will be stretched and the serial transfer is suspended.
The Assert Acknowledge flag (AA, SMB0CN.2) is used to set the level of the SDA line during the acknowledge
clock cycle on the SCL line. Setting the AA flag to logic 1 will cause an ACKNOWLEDGE (low level on SDA) to
be sent during the acknowledge cycle if the device has been addressed. Setting the AA flag to logic 0 will cause a
NOT ACKNOWLEDGE (high level on SDA) to be sent during acknowledge cycle. After the transmission of a
byte in slave mode, the slave can be temporarily removed from the bus by clearing the AA flag. The slave’s own
address and general call address will be ignored. To resume operation on the bus, the AA flag must be reset to logic
1 to allow the slave’s address to be recognized.
Setting the SMBus Free Timer Enable bit (FTE, SMB0CN.1) to logic 1 enables the SMBus Free Timeout feature. If
SCL and SDA remain high for the SMBus Free Timeout given in the SMBus Clock Rate Register (Figure 16.5), the
bus will be considered free and a Start will be generated if pending. The bus free period should be greater than
50µs.
Setting the SMBus timeout enable bit (TOE, SMB0CN.0) to logic 1 enables Timer 3 to count up when the SCL line
is low and Timer 3 is enabled. If Timer 3 overflows, a Timer 3 interrupt will be generated, which will alert the CPU
that a SMBus SCL low timeout has occurred.
117
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 16.4. SMB0CN: SMBus Control Register
R
R/W
ENSMB
Bit6
R/W
STA
Bit5
R/W
STO
Bit4
R/W
SI
R/W
AA
Bit2
R/W
FTE
Bit1
R/W
Reset Value
BUSY
TOE
00000000
SFR Address:
Bit7
Bit3
Bit0
(bit addressable)
0xC0
Bit7:
Bit6:
BUSY: Busy Status Flag.
0: SMBus is free
1: SMBus is busy
ENSMB: SMBus Enable.
This bit enables/disables the SMBus serial interface.
0: SMBus disabled.
1: SMBus enabled.
Bit5:
STA: SMBus Start Flag.
0: No START condition is transmitted.
1: When operating as a master, a START condition is transmitted if the bus is free. (If the
bus is not free, the START is transmitted after a STOP is received.) If STA is set after one
or more bytes have been transmitted or received and before a STOP is received, a repeated
START condition is transmitted. STO should be explicitly cleared before setting STA to
logic 1.
Bit4:
STO: SMBus Stop Flag.
0: No STOP condition is transmitted.
1: Setting STO to logic 1 causes a STOP condition to be transmitted. When a STOP
condition is received, hardware clears STO to logic 0. If both STA and STO are set, a
STOP condition is transmitted followed by a START condition. In slave mode, setting the
STO flag causes SMBus to behave as if a STOP condition was received.
SI: SMBus Serial Interrupt Flag.
Bit3:
Bit2:
This bit is set by hardware when one of 27 possible SMBus states is entered. (Status code
0xF8 does not cause SI to be set.) When the SI interrupt is enabled, setting this bit causes
the CPU to vector to the SMBus interrupt service routine. This bit is not automatically
cleared by hardware and must be cleared by software.
AA: SMBus Assert Acknowledge Flag.
This bit defines the type of acknowledge returned during the acknowledge cycle on the
SCL line.
0: A “not acknowledge” (high level on SDA) is returned during the acknowledge cycle.
1: An “acknowledge” (low level on SDA) is returned during the acknowledge cycle.
FTE: SMBus Free Timer Enable Bit
Bit1:
Bit0:
0: No timeout when SCL is high
1: Timeout when SCL high time exceeds limit specified by the SMB0CR value.
TOE: SMBus Timeout Enable Bit
0: No timeout when SCL is low.
1: Timeout when SCL low time exceeds limit specified by Timer 3, if enabled.
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16.6.2. Clock Rate Register
Figure 16.5. SMB0CR: SMBus Clock Rate Register
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Bit0
Reset Value
00000000
SFR Address:
0xCF
Bits7-0: SMB0CR.[7:0]: SMBus Clock Rate Preset
The SMB0CR Clock Rate register controls the frequency of the serial clock SCL in master
mode. The 8-bit word stored in the SMB0CR Register preloads a dedicated 8-bit timer.
The timer counts up, and when it rolls over to 0x00, the SCL logic state toggles.
The SMB0CR setting should be bounded by the following equation, where SMB0CR is the
unsigned 8-bit value in register SMB0CR, and SYSCLK is the system clock frequency in
Hz:
SMB0CR < ((288 - 0.85 * SYSCLK) / 1.125E6)
The resulting SCL signal high and low times are given by the following equations:
TLOW = (256 – SMB0CR) / SYSCLK
THIGH ≅ (258 – SMB0CR) / SYSCLK + 625 ns
Using the same value of SMB0CR from above, the Bus Free Timeout period is given in the
following equation:
TBFT ≅ 10 * [(256 – SMB0CR) + 1] / SYSCLK
119
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16.6.3. Data Register
The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been received.
Data remains stable in the register as long as SI is set to logic 1. Software can safely read or write to the data
register when the SI flag is set. Software should not attempt to access the SMB0DAT register when the SMBus is
enabled and the SI flag is cleared to logic 0 since the hardware may be in the process of shifting a byte of data in or
out of the register.
Data in SMB0DAT is always shifted out MSB first. After a byte has been received, the first bit of received data is
located at the MSB of SMB0DAT. While data is being shifted out, data on the bus is simultaneously being shifted
in. Therefore, SMB0DAT always contains the last data byte present on the bus. Thus, in the event of lost arbitration,
the transition from master transmitter to slave receiver is made with the correct data in SMB0DAT.
Figure 16.6. SMB0DAT: SMBus Data Register
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Bit0
Reset Value
00000000
SFR Address:
0xC2
Bits7-0: SMB0DAT: SMBus Data.
The SMB0DAT register contains a byte of data to be transmitted on the SMBus serial
interface or a byte that has just been received on the SMBus serial interface. The CPU can
read from or write to this register whenever the SI serial interrupt flag (SMB0CN.3) is set
to logic one. The serial data in the register remains stable as long as the SI flag is set.
When the SI flag is not set, the system may be in the process of shifting data in/out and the
CPU should not attempt to access this register.
16.6.4. Address Register
The SMB0ADR Address register holds the slave address for the SMBus interface. In slave mode, the seven most-
significant bits hold the 7-bit slave address. The least significant bit, bit 0, is used to enable the recognition of the
general call address (0x00). If bit 0 is set to logic 1, the general call address will be recognized. Otherwise, the
general call address is ignored. The contents of this register are ignored when the SMBus hardware is operating in
master mode.
Figure 16.7. SMB0ADR: SMBus Address Register
R/W
SLV6
Bit7
R/W
SLV5
Bit6
R/W
SLV4
Bit5
R/W
SLV3
Bit4
R/W
SLV2
Bit3
R/W
SLV1
Bit2
R/W
SLV0
Bit1
R/W
GC
Reset Value
00000000
SFR Address:
Bit0
0xC3
Bits7-1: SLV6-SLV0: SMBus Slave Address.
These bits are loaded with the 7-bit slave address to which the SMBus will respond when
operating as a slave transmitter or slave receiver. SLV6 is the most significant bit of the
address and corresponds to the first bit of the address byte received on the SMBus.
Bit0:
GC: General Call Address Enable.
This bit is used to enable general call address (0x00) recognition.
0: General call address is ignored.
1: General call address is recognized.
Rev. 1.7
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16.6.5. Status Register
The SMB0STA Status register holds an 8-bit status code indicating the current state of the SMBus. There are 28
possible SMBus states, each with a corresponding unique status code. The five most significant bits of the status
code vary while the three least-significant bits of a valid status code are fixed at zero when SI = 1. Therefore, all
possible status codes are multiples of eight. This facilitates the use of status codes in software as an index used to
branch to appropriate service routines (allowing 8 bytes of code to service the state or jump to a more extensive
service routine).
For the purposes of user software, the contents of the SMB0STA register is only defined when the SI flag is logic 1.
Software should never write to the SMB0STA register. Doing so will yield indeterminate results. The 28 SMBus
states, along with their corresponding status codes, are given in Table 16.1.
Figure 16.8. SMB0STA: SMBus Status Register
R/W
STA7
Bit7
R/W
STA6
Bit6
R/W
STA5
Bit5
R/W
STA4
Bit4
R/W
STA3
Bit3
R/W
STA2
Bit2
R/W
STA1
Bit1
R/W
STA0
Bit0
Reset Value
11111000
SFR Address:
0xC1
Bits7-3: STA7-STA3: SMBus Status Code.
These bits contain the SMBus Status Code. There are 28 possible status codes. Each
status code corresponds to a single SMBus state. A valid status code is present in
SMB0STA when the SI flag (SMB0CN.3) is set. The content of SMB0STA is not defined
when the SI flag is logic 0. Writing to the SMB0STA register at any time will yield
indeterminate results.
Bits2-0: STA2-STA0: The three least significant bits of SMB0STA are always read as logic 0 when
the SI flag is logic 1.
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Table 16.1. SMBus Status Codes
Status Code
(SMB0STA)
Mode
All
SMBus State
0x00
0x08
0x10
0x18
0x20
0x28
0x30
0x38
0x40
0x48
0x50
0x58
0x60
0x68
Bus Error (i.e. illegal START, illegal STOP, …)
Master Transmitter/Receiver START condition transmitted.
Master Transmitter/Receiver Repeated START condition transmitted.
Master Transmitter
Master Transmitter
Master Transmitter
Master Transmitter
Master Transmitter
Master Receiver
Master Receiver
Master Receiver
Master Receiver
Slave Receiver
Slave address + W transmitted. ACK received.
Slave address + W transmitted. NACK received.
Data byte transmitted. ACK received.
Data byte transmitted. NACK received.
Arbitration lost
Slave address + R transmitted. ACK received.
Slave address + R transmitted. NACK received
Data byte received. ACK transmitted.
Data byte received. NACK transmitted.
SMB0’s own slave address + W received. ACK transmitted.
Arbitration lost in transmitting slave address + R/W as master.
Own slave address + W received. ACK transmitted.
General call address (0x00) received. ACK returned.
Arbitration lost in transmitting slave address + R/W as master.
General call address received. ACK transmitted.
SMB0’s own slave address + W received. Data byte received.
ACK transmitted.
Slave Receiver
0x70
0x78
Slave Receiver
Slave Receiver
0x80
0x88
0x90
0x98
Slave Receiver
Slave Receiver
Slave Receiver
Slave Receiver
SMB0’s own slave address + W received. Data byte received.
NACK transmitted.
General call address (0x00) received. Data byte received. ACK
transmitted.
General call address (0x00) received. Data byte received.
NACK transmitted.
0xA0
0xA8
0xB0
Slave Receiver
Slave Transmitter
Slave Transmitter
A STOP or repeated START received while addressed as a slave.
SMB0’s own slave address + R received. ACK transmitted.
Arbitration lost in transmitting slave address + R/W as master.
Own slave address + R received. ACK transmitted.
Data byte transmitted. ACK received.
0xB8
0xC0
0xC8
0xD0
0xF8
Slave Transmitter
Slave Transmitter
Slave Transmitter
Slave Transmitter/Receiver
All
Data byte transmitted. NACK received.
Last data byte transmitted (AA=0). ACK received.
SCL Clock High Timer per SMB0CR timed out (FTE=1)
Idle
Rev. 1.7
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17. SERIAL PERIPHERAL INTERFACE BUS
The Serial Peripheral Interface (SPI) provides access to a four-wire, full-duplex, serial bus. SPI supports the
connection of multiple slave devices to a master device on the same bus. A separate slave-select signal (NSS) is
used to select a slave device and enable a data transfer between the master and the selected slave. Multiple masters
on the same bus are also supported. Collision detection is provided when two or more masters attempt a data
transfer at the same time. The SPI can operate as either a master or a slave. When the SPI is configured as a
master, the maximum data transfer rate (bits/sec) is one-half the system clock frequency.
When the SPI is configured as a slave, the maximum data transfer rate (bits/sec) for full-duplex operation is 1/10 the
system clock frequency, provided that the master issues SCK, NSS, and the serial input data synchronously with the
system clock. If the master issues SCK, NSS, and the serial input data asynchronously, the maximum data transfer
rate (bits/sec) must be less that 1/10 the system clock frequency. In the special case where the master only wants to
transmit data to the slave and does not need to receive data from the slave (i.e. half-duplex operation), the SPI slave
can receive data at a maximum data transfer rate (bits/sec) of ¼ the system clock frequency. This is provided that
the master issues SCK, NSS, and the serial input data synchronously with the system clock.
Figure 17.1. SPI Block Diagram
SFR Bus
SPI0CKR
SPI0CFG
SPI0CN
S
C
R
7
S
C
R
6
S
C
R
5
S
C
R
4
S
C
R
3
S
C
R
2
S
C
R
1
S
C
R
0
C
K
P
H
A
C
K
P
O
L
B
C
2
B
C
1
B
C
0
F
R
S
2
F
R
S
1
F
R
S
0
S
P
I
W
C
O
L
M
O
D
F
R
X
O
V
R
N
T
X
B
S
Y
S
L
M
S
T
S
P
I
V
S
E
L
F
E
N
E
N
Clock Divide
Logic
Bit Count
Logic
SYSCLK
SPI CONTROL LOGIC
SPI IRQ
Data Path
Control
SPI Clock
Pin Control
Interface
(Master Mode)
SCK
C
R
O
S
S
B
A
R
MOSI
MISO
NSS
Tx Data
Pin
SPI0DAT
Control
Logic
Port I/O
Shift Register
7 6 5 4 3 2 1 0
Rx Data
Receive Data Register
Read
Write to
SPI0DAT
SPI0DAT
SFR Bus
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Figure 17.2. Typical SPI Interconnection
NSS
NSS
NSS
Slave
Slave
Slave
Device
Device
Device
VDD
MISO
MOSI
SCK
Master
Device
17.1. Signal Descriptions
The four signals used by the SPI (MOSI, MISO, SCK, NSS) are described below.
17.1.1. Master Out, Slave In
The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices. It is used to
serially transfer data from the master to the slave. Data is transferred most-significant bit first.
17.1.2. Master In, Slave Out
The master-in, slave-out (MISO) signal is an output from a slave device and an input to the master device. It is used
to serially transfer data from the slave to the master. Data is transferred most-significant bit first. A SPI slave
places the MISO pin in a high-impedance state when the slave is not selected.
17.1.3. Serial Clock
The serial clock (SCK) signal is an output from the master device and an input to slave devices. It is used to
synchronize the transfer of data between the master and slave on the MOSI and MISO lines.
17.1.4. Slave Select
The slave select (NSS) signal is an input used to select the SPI module when in slave mode by a master, or to
disable the SPI module when in master mode. When in slave mode, it is pulled low to initiate a data transfer and
remains low for the duration of the transfer.
Rev. 1.7
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17.2. Operation
Only a SPI master device can initiate a data transfer. The SPI is placed in master mode by setting the Master Enable
flag (MSTEN, SPI0CN.1). Writing a byte of data to the SPI data register (SPI0DAT) when in Master Mode starts a
data transfer. The SPI master immediately shifts out the data serially on the MOSI line while providing the serial
clock on SCK. The SPIF (SPI0CN.7) flag is set to logic 1 at the end of the transfer. If interrupts are enabled, an
interrupt request is generated when the SPIF flag is set. The SPI master can be configured to shift in/out from one
to eight bits in a transfer operation in order to accommodate slave devices with different word lengths. The SPIFRS
bits in the SPI Configuration Register (SPI0CFG.[2:0]) are used to select the number of bits to shift in/out in a
transfer operation.
While the SPI master transfers data to a slave on the MOSI line, the addressed SPI slave device simultaneously
transfers the contents of its shift register to the SPI master on the MISO line in a full-duplex operation. The data
byte received from the slave replaces the data in the master’s data register. Therefore, the SPIF flag serves as both a
transmit-complete and receive-data-ready flag. The data transfer in both directions is synchronized with the serial
clock generated by the master. Figure 17.3 illustrates the full-duplex operation of an SPI master and an addressed
slave.
Figure 17.3. Full Duplex Operation
MASTER DEVICE
SLAVE DEVICE
MOSI
MISO
NSS
SCK
Px.y
MOSI
MISO
NSS
SPI SHIFT REGISTER
7 6 5 4 3 2 1 0
SPI SHIFT REGISTER
7 6 5 4 3 2 1 0
VDD
Receive Buffer
Receive Buffer
SCK
Baud Rate
Generator
The SPI data register is double buffered on reads, but not on a write. If a write to SPI0DAT is attempted during a
data transfer, the WCOL flag (SPI0CN.6) will be set to logic 1 and the write is ignored. The current data transfer
will continue uninterrupted. A read of the SPI data register by the system controller actually reads the receive
buffer. If the receive buffer still holds unread data from a previous transfer when the last bit of the current transfer
is shifted into the SPI shift register, a receive overrun occurs and the RXOVRN flag (SPI0CN.4) is set to logic 1.
The new data is not transferred to the receive buffer, allowing the previously received data byte to be read. The data
byte causing the overrun is lost.
When the SPI is enabled and not configured as a master, it will operate as an SPI slave. Another SPI device acting
as a master will initiate a transfer by driving the NSS signal low. The master then shifts data out of the shift register
on the MOSI pin using the its serial clock. The SPIF flag is set to logic 1 at the end of a data transfer (when the
NSS signal goes high). The slave can load its shift register for the next data transfer by writing to the SPI data
register. The slave must make the write to the data register at least one SPI serial clock cycle before the master
starts the next transmission. Otherwise, the byte of data already in the slave’s shift register will be transferred.
Multiple masters may reside on the same bus. A Mode Fault flag (MODF, SPI0CN.5) is set to logic 1 when the SPI
is configured as a master (MSTEN = 1) and its slave select signal NSS is pulled low. When the Mode Fault flag is
set, the MSTEN and SPIEN bits of the SPI control register are cleared by hardware, thereby placing the SPI module
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in an “off-line” state. In a multiple-master environment, the system controller should check the state of the
SLVSEL flag (SPI0CN.2) to ensure the bus is free before setting the MSTEN bit and initiating a data transfer.
17.3. Serial Clock Timing
As shown in Figure 17.4, four combinations of serial clock phase and polarity can be selected using the clock
control bits in the SPI Configuration Register (SPI0CFG). The CKPHA bit (SPI0CFG.7) selects one of two clock
phases (edge used to latch the data). The CKPOL bit (SPI0CFG.6) selects between an active-high or active-low
clock. Both master and slave devices must be configured to use the same clock phase and polarity. Note: the SPI
should be disabled (by clearing the SPIEN bit, SPI0CN.0) while changing the clock phase and polarity.
The SPI Clock Rate Register (SPI0CKR) as shown in Figure 17.7 controls the master mode serial clock frequency.
This register is ignored when operating in slave mode.
Figure 17.4. Data/Clock Timing Diagram
SCK
(CKPOL = 0, CKPHA = 0)
SCK
(CKPOL = 0, CKPHA = 1)
SCK
(CKPOL = 1, CKPHA = 0)
SCK
(CKPOL = 1, CKPHA = 1)
MSB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
LSB
MISO/MOSI
NSS
Rev. 1.7
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17.4. SPI Special Function Registers
The SPI is accessed and controlled through four special function registers in the system controller: SPI0CN Control
Register, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate Register. The four
special function registers related to the operation of the SPI Bus are described in the following section.
Figure 17.5. SPI0CFG: SPI Configuration Register
R/W
CKPHA
Bit7
R/W
CKPOL
Bit6
R
R
R
R/W
SPIFRS2
Bit2
R/W
SPIFRS1
Bit1
R/W
SPIFRS0
Bit0
Reset Value
BC2
BC1
BC0
00000111
SFR Address:
Bit5
Bit4
Bit3
0x9A
Bit7:
CKPHA: SPI Clock Phase.
This bit controls the SPI clock phase.
0: Data sampled on first edge of SCK period.
1: Data sampled on second edge of SCK period.
Bit6:
CKPOL: SPI Clock Polarity.
This bit controls the SPI clock polarity.
0: SCK line low in idle state.
1: SCK line high in idle state.
Bits5-3: BC2-BC0: SPI Bit Count.
Indicates which of the up to 8 bits of the SPI word have been transmitted.
BC2-BC0
Bit Transmitted
Bit 0 (LSB)
Bit 1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7 (MSB)
Bits2-0: SPIFRS2-SPIFRS0: SPI Frame Size.
These three bits determine the number of bits to shift in/out of the SPI shift register
during a data transfer in master mode. They are ignored in slave mode.
SPIFRS
Bits Shifted
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
3
4
5
6
7
8
.
127
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C8051F010/1/2/5/6/7
Figure 17.6. SPI0CN: SPI Control Register
R/W
SPIF
Bit7
R/W
WCOL
Bit6
R/W
MODF
Bit5
R/W
RXOVRN
Bit4
R
R
R/W
MSTEN
Bit1
R/W
Reset Value
TXBSY
SLVSEL
SPIEN
00000000
SFR Address:
Bit3
Bit2
Bit0
(bit addressable)
0xF8
Bit7:
SPIF: SPI Interrupt Flag.
This bit is set to logic 1 by hardware at the end of a data transfer. If interrupts are enabled,
setting this bit causes the CPU to vector to the SPI0 interrupt service routine. This bit is
not automatically cleared by hardware. It must be cleared by software.
Bit6:
Bit5:
Bit4:
WCOL: Write Collision Flag.
This bit is set to logic 1 by hardware (and generates a SPI interrupt) to indicate a write to
the SPI data register was attempted while a data transfer was in progress. It is cleared by
software.
MODF: Mode Fault Flag.
This bit is set to logic 1 by hardware (and generates a SPI interrupt) when a master mode
collision is detected (NSS is low and MSTEN = 1). This bit is not automatically cleared by
hardware. It must be cleared by software.
RXOVRN: Receive Overrun Flag.
This bit is set to logic 1 by hardware (and generates a SPI interrupt) when the receive
buffer still holds unread data from a previous transfer and the last bit of the current transfer
is shifted into the SPI shift register. This bit is not automatically cleared by hardware. It
must be cleared by software.
Bit3:
Bit2:
Bit1:
Bit0:
TXBSY: Transmit Busy Flag.
This bit is set to logic 1 by hardware while a master mode transfer is in progress. It is
cleared by hardware at the end of the transfer.
SLVSEL: Slave Selected Flag.
This bit is set to logic 1 whenever the NSS pin is low indicating it is enabled as a slave. It
is cleared to logic 0 when NSS is high (slave disabled).
MSTEN: Master Mode Enable.
0: Disable master mode. Operate in slave mode.
1: Enable master mode. Operate as a master.
SPIEN: SPI Enable.
This bit enables/disables the SPI.
0: SPI disabled.
1: SPI enabled.
Rev. 1.7
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C8051F010/1/2/5/6/7
Figure 17.7. SPI0CKR: SPI Clock Rate Register
R/W
SCR7
Bit7
R/W
SCR6
Bit6
R/W
SCR5
Bit5
R/W
SCR4
Bit4
R/W
SCR3
Bit3
R/W
SCR2
Bit2
R/W
SCR1
Bit1
R/W
SCR0
Bit0
Reset Value
00000000
SFR Address:
0x9D
Bits7-0: SCR7-SCR0: SPI Clock Rate
These bits determine the frequency of the SCK output when the SPI module is
configured for master mode operation. The SCK clock frequency is a divided down
version of the system clock, and is given in the following equations:
fSCK = 0.5 * fSYSCLK / (SPI0CKR + 1),
for 0 ≤ SPI0CKR ≤ 255,
Figure 17.8. SPI0DAT: SPI Data Register
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Bit0
Reset Value
00000000
SFR Address:
0x9B
Bits7-0: SPI0DAT: SPI0 Transmit and Receive Data.
The SPI0DAT register is used to transmit and receive SPI data. Writing data to SPI0DAT
places the data immediately into the shift register and initiates a transfer when in Master
Mode. A read of SPI0DAT returns the contents of the receive buffer.
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18. UART
The UART is a serial port capable of asynchronous transmission. The UART can function in full duplex mode. In
all modes, receive data is buffered in a holding register. This allows the UART to start reception of a second
incoming data byte before software has finished reading the previous data byte.
The UART has an associated Serial Control Register (SCON) and a Serial Data Buffer (SBUF) in the SFRs. The
single SBUF location provides access to both transmit and receive registers. Reads access the Receive register and
writes access the Transmit register automatically.
The UART is capable of generating interrupts if enabled. The UART has two sources of interrupts: a Transmit
Interrupt flag, TI (SCON.1) set when transmission of a data byte is complete, and a Receive Interrupt flag, RI
(SCON.0) set when reception of a data byte is complete. The UART interrupt flags are not cleared by hardware
when the CPU vectors to the interrupt service routine. They must be cleared manually by software. This allows
software to determine the cause of the UART interrupt (transmit complete or receive complete).
Figure 18.1. UART Block Diagram
SFR Bus
Write to
SBUF
PCON
SCON
T2CON
TB8
S
M
O
D
S
M
0
S
M
1
S
M
2
R
E
N
T
B
8
R
B
8
T
I
R
I
R
T
C
L
C
L
K
K
SET
D
Q
SBUF
TX
CLR
Crossbar
Zero Detector
Baud Rate Generation Logic
Shift
Stop Bit
Gen.
Start
Data
Timer 1
1
Overflow
Tx Control
Tx IRQ
0
00
01
10
11
0
2
16
Tx Clock
Send
1
SMOD
TI
Serial
Port
TCLK
SM0, SM1
{MODE}
REN
RB8
Interrupt
RI
0
00
01
10
11
Rx IRQ
Enable
MSB
16
Rx Clock
Start
Timer 2
Load
1
Overflow
SBUF
Rx Control
RCLK
Shift
0x1FF
1
32
Port I/O
Bit Detector
0
64
Input Shift Register
(9 bits)
SYSCLK
SMOD
12
Shift
Load SBUF
SBUF
Read
SBUF
SFR Bus
RX
Crossbar
Rev. 1.7
130
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
18.1. UART Operational Modes
The UART provides four operating modes (one synchronous and three asynchronous) selected by setting
configuration bits in the SCON register. These four modes offer different baud rates and communication protocols.
The four modes are summarized in Table 18.1 below. Detailed descriptions follow.
Table 18.1. UART Modes
Mode
Synchronization
Synchronous
Asynchronous
Asynchronous
Asynchronous
Baud Clock
Data Bits
Start/Stop Bits
None
1 Start, 1 Stop
1 Start, 1 Stop
1 Start, 1 Stop
0
1
2
3
SYSCLK/12
8
8
9
9
Timer 1 or Timer 2 Overflow
SYSCLK/32 or SYSCLK/64
Timer 1 or Timer 2 Overflow
18.1.1. Mode 0: Synchronous Mode
Mode 0 provides synchronous, half-duplex communication. Serial data is transmitted and received on the RX pin.
The TX pin provides the shift clock for both transmit and receive. The MCU must be the master since it generates
the shift clock for transmission in both directions (see the interconnect diagram in Figure 18.2).
Eight data bits are transmitted/received, LSB first (see the timing diagram in Figure 18.3). Data transmission begins
when an instruction writes a data byte to the SBUF register. The TI Transmit Interrupt Flag (SCON.1) is set at the
end of the eighth bit time. Data reception begins when the REN Receive Enable bit (SCON.4) is set to logic 1 and
the RI Receive Interrupt Flag (SCON.0) is cleared. One cycle after the eighth bit is shifted in, the RI flag is set and
reception stops until software clears the RI bit. An interrupt will occur if enabled when either TI or RI is set.
The Mode 0 baud rate is the system clock frequency divided by twelve. RX is forced to open-drain in mode 0, and
an external pull-up will typically be required.
Figure 18.2. UART Mode 0 Interconnect
CLK
C8051FxxxTX
Shift
Reg.
RX
DATA
8 Extra Outputs
Figure 18.3. UART Mode 0 Timing Diagram
MODE 0 TRANSMIT
D0
D1
D2
D3
D4
D5
D6
D7
RX (data out)
TX (clk out)
MODE 0 RECEIVE
D0
D1
D2
D3
D4
D5
D6
D7
RX (data in)
131
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Mode 1 provides standard asynchronous, full duplex communication using a total of 10 bits per data byte: one start
bit, eight data bits (LSB first), and one stop bit (see the timing diagram in Figure 18.4). Data are transmitted from
the TX pin and received at the RX pin (see the interconnection diagram in Figure 18.5). On receive, the eight data
bits are stored in SBUF and the stop bit goes into RB8 (SCON.2).
Data transmission begins when an instruction writes a data byte to the SBUF register. The TI Transmit Interrupt
Flag (SCON.1) is set at the end of the transmission (the beginning of the stop-bit time). Data reception can begin
any time after the REN Receive Enable bit (SCON.4) is set to logic 1. After the stop bit is received, the data byte
will be loaded into the SBUF receive register if the following conditions are met: RI must be logic 0, and if SM2 is
logic 1, the stop bit must be logic 1.
If these conditions are met, the eight bits of data are stored in SBUF, the stop bit is stored in RB8, and the RI flag is
set. If these conditions are not met, SBUF and RB8 will not be loaded and the RI flag will not be set. An interrupt
will occur if enabled when either TI or RI is set.
Figure 18.4. UART Mode 1 Timing Diagram
MARK
START
BIT
STOP
BIT
D0
D1
D2
D3
D4
D5
D6
D7
SPACE
BIT TIMES
BIT SAMPLING
The baud rate generated in Mode 1 is a function of timer overflow. The UART can use Timer 1 operating in 8-bit
Counter/Timer with Auto-Reload Mode, or Timer 2 operating in Baud Rate Generator Mode to generate the baud
rate (note that the TX and RX clock sources are selected separately). On each timer overflow event (a rollover from
all ones (0xFF for Timer 1, 0xFFFF for Timer 2) to zero), a clock is sent to the baud rate logic.
When Timer 1 is selected as a baud rate source, the SMOD bit (PCON.7) selects whether or not to divide the
Timer 1 overflow rate by two. On reset, the SMOD bit is logic 0, thus selecting the lower speed baud rate by
default. The SMOD bit affects the baud rate generated by Timer 1 as follows:
Mode 1 Baud Rate = (1 / 32) * T1_OVERFLOWRATE (when the SMOD bit is set to logic 0).
Mode 1 Baud Rate = (1 / 16) * T1_OVERFLOWRATE (when the SMOD bit is set to logic 1).
When Timer 2 is selected as a baud rate source, the baud rate generated by Timer 2 is as follows:
Mode 1 Baud Rate = (1 / 16) * T2_OVERFLOWRATE.
The Timer 1 overflow rate is determined by the Timer 1 clock source (T1CLK) and reload value (TH1). The
frequency of T1CLK can be selected as SYSCLK, SYSCLK/12, or an external clock source. The Timer 1 overflow
rate can be calculated as follows:
T1_OVERFLOWRATE = T1CLK / (256 – TH1).
For example, assume TMOD = 0x20.
If T1M (CKCON.4) is logic 1, then the above equation becomes:
T1_OVERFLOWRATE = (SYSCLK) / (256 – TH1).
If T1M (CKCON.4) is logic 0, then the above equation becomes:
T1_OVERFLOWRATE = (SYSCLK/12) / (256 – TH1).
Rev. 1.7
132
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
The Timer 2 overflow rate, when in Baud Rate Generator Mode and using an internal clock source, is determined
solely by the Timer 2 16-bit reload value (RCAP2H:RCAP2L). The Timer 2 clock source is fixed at SYSCLK/2.
The Timer 2 overflow rate can be calculated as follows:
T2_OVERFLOWRATE = (SYSCLK/2) / (65536 – [RCAP2H:RCAP2L]).
Timer 2 can be selected as the baud rate generator for RX and/or TX by setting RCLK (T2CON.5) and/or TCLK
(T2CON.4), respectively. When either RCLK or TCLK is set to logic 1, Timer 2 interrupts are automatically
disabled and the timer is forced into Baud Rate Generator Mode with SYSCLK/2 as its clock source. If a different
timebase is required, setting the C/T2 bit (T2CON.1) to logic 1 will allow Timer 2 to be clocked from the external
input pin T2. See the Timers section for complete timer configuration details.
Figure 18.5. UART Modes 1, 2, and 3 Interconnect Diagram
TX
RS-232
RS-232
LEVEL
C8051Fxxx
RX
XLTR
OR
TX
MCU
TXC8051Fxxx
RX
RX
133
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
18.1.3. Mode 2: 9-Bit UART, Fixed Baud Rate
Mode 2 provides asynchronous, full-duplex communication using a total of eleven bits per data byte: a start bit, 8
data bits (LSB first), a programmable ninth data bit, and a stop bit (see timing diagram in Figure 18.6). On transmit,
the ninth data bit is determined by the value in TB8 (SCON.3). It can be assigned the value of the parity flag P in
the PSW or used in multiprocessor communications. On receive, the ninth data bit goes into RB8 (SCON.2) and the
stop bit is ignored.
Data transmission begins when an instruction writes a data byte to the SBUF register. The TI Transmit Interrupt
Flag (SCON.1) is set at the end of the transmission (the beginning of the stop-bit time). Data reception can begin
any time after the REN Receive Enable bit (SCON.4) is set to logic 1. After the stop bit is received, the data byte
will be loaded into the SBUF receive register if the following conditions are met: RI must be logic 0, and if SM2 is
logic 1, the 9th bit must be logic 1.
If these conditions are met, the eight bits of data are stored in SBUF, the ninth bit is stored in RB8 and the RI flag is
set. If these conditions are not met, SBUF and RB8 will not be loaded and the RI flag will not be set. An interrupt
will occur if enabled when either TI or RI are set.
The baud rate in Mode 2 is a direct function of the system clock frequency as follows:
Mode 2 Baud Rate = 2SMOD * (SYSCLK / 64).
The SMOD bit (PCON.7) selects whether to divide SYSCLK by 32 or 64. In the formula, 2 is raised to the power
SMOD, resulting in a baud rate of either 1/32 or 1/64 of the system clock frequency. On reset, the SMOD bit is
logic 0, thus selecting the lower speed baud rate by default.
Figure 18.6. UART Modes 2 and 3 Timing Diagram
MARK
START
BIT
STOP
BIT
D0
D1
D2
D3
D4
D5
D6
D7
D8
SPACE
BIT TIMES
BIT SAMPLING
18.1.4. Mode 3: 9-Bit UART, Variable Baud Rate
Mode 3 is the same as Mode 2 in all respects except the baud rate is variable. The baud rate is determined in the
same manner as for Mode 1. Mode 3 operation transmits 11 bits: a start bit, 8 data bits (LSB first), a programmable
ninth data bit, and a stop bit. Timer 1 or Timer 2 overflows generate the baud rate just as with Mode 1. In
summary, Mode 3 transmits using the same protocol as Mode 2 but with Mode 1 baud rate generation.
Rev. 1.7
134
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
18.2. Multiprocessor Communications
Modes 2 and 3 support multiprocessor communication between a master processor and one or more slave processors
by special use of the ninth data bit. When a master processor wants to transmit to one or more slaves, it first sends
an address byte to select the target(s). An address byte differs from a data byte in that its ninth bit is logic 1; in a
data byte, the ninth bit is always set to logic 0.
Setting the SM2 bit (SCON.5) of a slave processor configures its UART such that when a stop bit is received, the
UART will generate an interrupt only if the ninth bit is logic one (RB8 = 1) signifying an address byte has been
received. In the UART’s interrupt handler, software will compare the received address with the slave’s own
assigned 8-bit address. If the addresses match, the slave will clear its SM2 bit to enable interrupts on the reception
of the following data byte(s). Slaves that weren’t addressed leave their SM2 bits set and do not generate interrupts
on the reception of the following data bytes, thereby ignoring the data. Once the entire message is received, the
addressed slave resets its SM2 bit to ignore all transmissions until it receives the next address byte.
Multiple addresses can be assigned to a single slave and/or a single address can be assigned to multiple slaves,
thereby enabling “broadcast” transmissions to more than one slave simultaneously. The master processor can be
configured to receive all transmissions or a protocol can be implemented such that the master/slave role is
temporarily reversed to enable half-duplex transmission between the original master and slave(s).
Figure 18.7. UART Multi-Processor Mode Interconnect Diagram
Master
Device
Slave
Slave
Slave
Device
Device
Device
VDD
RX
TX
RX
TX
RX
TX
RX
TX
135
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Table 18.2. Oscillator Frequencies for Standard Baud Rates
Oscillator Frequency (MHz) Divide Factor Timer 1 Load Value* Resulting Baud Rate**
24.0
208
205
192
160
144
128
112
96
0xF3
0xF3
0xF4
0xF6
0xF7
0xF8
0xF9
0xFA
0xFB
0xFC
0xFD
0xFE
0xFF
0xEC
0xE5
0xCA
0xCB
0xCC
0xCD
0xD0
0xD8
0xDC
0xE0
0xE4
0xE8
0xEC
0xF0
0xF4
0xF8
0xFC
115200 (115384)
115200 (113423)
115200
23.592
22.1184
18.432
16.5888
14.7456
12.9024
11.0592
9.216
115200
115200
115200
115200
115200
80
115200
7.3728
5.5296
3.6864
1.8432
24.576
25.0
25.0
24.576
24.0
23.592
22.1184
18.432
16.5888
14.7456
12.9024
11.0592
9.216
7.3728
5.5296
3.6864
1.8432
64
115200
48
115200
32
115200
16
115200
320
434
868
848
833
819
768
640
576
512
448
384
320
256
192
128
64
76800
57600 (57870)
28800
28800 (28921)
28800 (28846)
28800 (28911)
28800
28800
28800
28800
28800
28800
28800
28800
28800
28800
28800
* Assumes SMOD=1 and T1M=1.
** Numbers in parenthesis show the actual baud rate.
Figure 18.8. SBUF: Serial (UART) Data Buffer Register
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Bit0
Reset Value
00000000
SFR Address:
0x99
Bits7-0: SBUF.[7:0]: Serial Data Buffer Bits 7-0 (MSB-LSB)
This is actually two registers; a transmit and a receive buffer register. When data is moved to
SBUF, it goes to the transmit buffer and is held for serial transmission. Moving a byte to
SBUF is what initiates the transmission. When data is moved from SBUF, it comes from the
receive buffer.
Rev. 1.7
136
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 18.9. SCON: Serial Port Control Register
R/W
SM0
Bit7
R/W
SM1
Bit6
R/W
SM2
Bit5
R/W
REN
Bit4
R/W
TB8
Bit3
R/W
RB8
Bit2
R/W
TI
R/W
RI
Reset Value
00000000
SFR Address:
Bit1
Bit0
(bit addressable)
0x98
Bits7-6: SM0-SM1: Serial Port Operation Mode.
These bits select the Serial Port Operation Mode.
SM0
SM1
Mode
0
0
1
1
0
1
0
1
Mode 0: Synchronous Mode
Mode 1: 8-Bit UART, Variable Baud Rate
Mode 2: 9-Bit UART, Fixed Baud Rate
Mode 3: 9-Bit UART, Variable Baud Rate
Bit5:
SM2: Multiprocessor Communication Enable.
The function of this bit is dependent on the Serial Port Operation Mode.
Mode 0: No effect
Mode 1: Checks for valid stop bit.
0: Logic level of stop bit is ignored.
1: RI will only be activated if stop bit is logic level 1.
Mode 2 and 3: Multiprocessor Communications Enable.
0: Logic level of ninth bit is ignored.
1: RI is set and an interrupt is generated only when the ninth bit is logic 1.
Bit4:
REN: Receive Enable.
This bit enables/disables the UART receiver.
0: UART reception disabled.
1: UART reception enabled.
Bit3:
Bit2:
TB8: Ninth Transmission Bit.
The logic level of this bit will be assigned to the ninth transmission bit in Modes 2 and 3. It
is not used in Modes 0 and 1. Set or cleared by software as required.
RB8: Ninth Receive Bit.
The bit is assigned the logic level of the ninth bit received in Modes 2 and 3. In Mode 1, if
SM2 is logic 0, RB8 is assigned the logic level of the received stop bit. RB8 is not used in
Mode 0.
Bit1:
Bit0:
TI: Transmit Interrupt Flag.
Set by hardware when a byte of data has been transmitted by the UART (after the 8th bit in
Mode 0, or at the beginning of the stop bit in other modes). When the UART interrupt is
enabled, setting this bit causes the CPU to vector to the UART interrupt service routine.
This bit must be cleared manually by software
RI: Receive Interrupt Flag.
Set by hardware when a byte of data has been received by the UART (after the 8th bit in
Mode 0, or after the stop bit in other modes – see SM2 bit for exception). When the
UART interrupt is enabled, setting this bit causes the CPU to vector to the UART interrupt
service routine. This bit must be cleared manually by software.
137
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
19. TIMERS
Each MCU implements four counter/timers: three are 16-bit counter/timers compatible with those found in the
standard 8051, and one is a 16-bit timer for use with the ADC, SMBus, or for general purpose use. These can be
used to measure time intervals, count external events and generate periodic interrupt requests. Timer 0 and Timer 1
are nearly identical and have four primary modes of operation. Timer 2 offers additional capabilities not available
in Timers 0 and 1. Timer 3 is similar to Timer 2, but without the capture or Baud Rate Generator modes.
Timer 3:
Timer 0 and Timer 1:
Timer 2:
13-bit counter/timer
16-bit counter/timer with auto-reload 16-bit timer with auto-reload
16-bit counter/timer
16-bit counter/timer with capture
8-bit counter/timer with auto-reload
Two 8-bit counter/timers (Timer 0 only)
Baud rate generator
When functioning as a timer, the counter/timer registers are incremented on each clock tick. Clock ticks are derived
from the system clock divided by either one or twelve as specified by the Timer Clock Select bits (T2M-T0M) in
CKCON. The twelve-clocks-per-tick option provides compatibility with the older generation of the 8051 family.
Applications that require a faster timer can use the one-clock-per-tick option.
When functioning as a counter, a counter/timer register is incremented on each high-to-low transition at the selected
input pin for T0, T1, or T2. Events with a frequency of up to one-fourth the system clock’s frequency can be
counted. The input signal need not be periodic, but it should be held at a given level for at least two full system
clock cycles to ensure the level is sampled.
19.1. Timer 0 and Timer 1
Timer 0 and Timer 1 are accessed and controlled through SFRs. Each counter/timer is implemented as a 16-bit
register accessed as two separate bytes: a low byte (TL0 or TL1) and a high byte (TH0 or TH1). The
Counter/Timer Control (TCON) register is used to enable Timer 0 and Timer 1 as well as indicate their status. Both
counter/timers operate in one of four primary modes selected by setting the Mode Select bits M1-M0 in the
Counter/Timer Mode (TMOD) register. Each timer can be configured independently. Following is a detailed
description of each operating mode.
19.1.1. Mode 0: 13-bit Counter/Timer
Timer 0 and Timer 1 operate as a 13-bit counter/timer in Mode 0. The following describes the configuration and
operation of Timer 0. However, both timers operate identically and Timer 1 is configured in the same manner as
described for Timer 0.
The TH0 register holds the eight MSBs of the 13-bit counter/timer. TL0 holds the five LSBs in bit positions TL0.4-
TL0.0. The three upper bits of TL0 (TL0.7-TL0.5) are indeterminate and should be masked out or ignored when
reading. As the 13-bit timer register increments and overflows from 0x1FFF (all ones) to 0x0000, the timer
overflow flag TF0 (TCON.5) is set and an interrupt will occur if enabled.
The C/T0 bit (TMOD.2) selects the counter/timer’s clock source. Clearing C/T selects the system clock as the input
for the timer. When C/T0 is set to logic 1, high-to-low transitions at the selected input pin increment the timer
register. (Refer to Port I/O Section 15.1 for information on selecting and configuring external I/O pins.)
Rev. 1.7
138
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Setting the TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is 0 or the input signal /INT0 is
logic-level one. Setting GATE0 to logic 1 allows the timer to be controlled by the external input signal /INT0,
facilitating pulse width measurements.
TR0
GATE0
/INT0
Counter/Timer
Disabled
0
1
1
1
X
0
X
X
0
Enabled
1
1
Disabled
Enabled
1
X = Don’t Care
Setting TR0 does not reset the timer register. The timer register should be initialized to the desired value before
enabling the timer.
TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as described above for TL0 and TH0. Timer
1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0.
Figure 19.1. T0 Mode 0 Block Diagram
TMOD
CKCON
T T T
2 1 0
M M M
G
A
T
E
1
G
A
T
C T T
C T T
/
1 1
/ 0 0
T M M T M M
E
0
1 1 0
0 1 0
12
0
1
SYSCLK
T0
0
1
TF1
TR1
TF0
TR0
IE1
Interrupt
Crossbar
TCLK
TL0
TH0
(5 bits)
(8 bits)
IT1
TR0
IE0
IT0
GATE0
Crossbar
/INT0
19.1.2. Mode 1: 16-bit Counter/Timer
Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The counter/timers
are enabled and configured in Mode 1 in the same manner as for Mode 0.
139
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
19.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload
Mode 2 configures Timer 0 and Timer 1 to operate as 8-bit counter/timers with automatic reload of the start value.
The TL0 holds the count and TH0 holds the reload value. When the count in TL0 overflows from all ones to 0x00,
the timer overflow flag TF0 (TCON.5) is set and the counter in TL0 is reloaded from TH0. If enabled, an interrupt
will occur when the TF0 flag is set. The reload value in TH0 is not changed. TL0 must be initialized to the desired
value before enabling the timer for the first count to be correct. When in Mode 2, Timer 1 operates identically to
Timer 0. Both counter/timers are enabled and configured in Mode 2 in the same manner as Mode 0.
Figure 19.2. T0 Mode 2 Block Diagram
CKCON
T T T
2 1 0
M M M
TMOD
G
A
T
E
1
G
C T T
C T T
A
T
/
1 1
/ 0 0
T M M T M M
E
0
1 1 0
0 1 0
12
0
1
SYSCLK
T0
0
1
TF1
TR1
TF0
TR0
IE1
Crossbar
TR0
TCLK
TL0
Interrupt
(8 bits)
IT1
IE0
IT0
GATE0
Crossbar
TH0
Reload
(8 bits)
/INT0
Rev. 1.7
140
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
19.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)
Timer 0 and Timer 1 behave differently in Mode 3. Timer 0 is configured as two separate 8-bit counter/timers held
in TL0 and TH0. The counter/timer in TL0 is controlled using the Timer 0 control/status bits in TCON and TMOD:
TR0, C/T0, GATE0 and TF0. It can use either the system clock or an external input signal as its timebase. The
TH0 register is restricted to a timer function sourced by the system clock. TH0 is enabled using the Timer 1 run
control bit TR1. TH0 sets the Timer 1 overflow flag TF1 on overflow and thus controls the Timer 1 interrupt.
Timer 1 is inactive in Mode 3, so with Timer 0 in Mode 3, Timer 1 can be turned off and on by switching it into and
out of its Mode 3. When Timer 0 is in Mode 3, Timer 1 can be operated in Modes 0, 1 or 2, but cannot be clocked
by external signals nor set the TF1 flag and generate an interrupt. However, the Timer 1 overflow can be used for
baud rate generation. Refer to Section 18 (UART) for information on configuring Timer 1 for baud rate generation.
Figure 19.3. T0 Mode 3 Block Diagram
CKCON
T T T
2 1 0
M M M
TMOD
G
A
T
E
1
G
C T T
C T T
A
T
/
1 1
/ 0 0
T M M T M M
E
0
1 1 0
0 1 0
TR1
TH0
Interrupt
Interrupt
TF1
TR1
TF0
TR0
IE1
12
(8 bits)
0
SYSCLK
T0
C/T0
1
0
1
IT1
IE0
IT0
Crossbar
TL0
(8 bits)
TR0
GATE0
Crossbar
/INT0
141
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 19.4. TCON: Timer Control Register
R/W
TF1
Bit7
R/W
TR1
Bit6
R/W
TF0
Bit5
R/W
TR0
Bit4
R/W
IE1
Bit3
R/W
IT1
Bit2
R/W
IE0
Bit1
R/W
IT0
Reset Value
00000000
SFR Address:
Bit0
(bit addressable)
0x88
Bit7:
TF1: Timer 1 Overflow Flag.
Set by hardware when Timer 1 overflows. This flag can be cleared by software but is
automatically cleared when the CPU vectors to the Timer 1 interrupt service routine.
0: No Timer 1 overflow detected.
1: Timer 1 has overflowed.
Bit6:
Bit5:
TR1: Timer 1 Run Control.
0: Timer 1 disabled.
1: Timer 1 enabled.
TF0: Timer 0 Overflow Flag.
Set by hardware when Timer 0 overflows. This flag can be cleared by software but is
automatically cleared when the CPU vectors to the Timer 0 interrupt service routine.
0: No Timer 0 overflow detected.
1: Timer 0 has overflowed.
Bit4:
Bit3:
TR0: Timer 0 Run Control.
0: Timer 0 disabled.
1: Timer 0 enabled.
IE1: External Interrupt 1.
This flag is set by hardware when an edge/level of type defined by IT1 is detected. It can
be cleared by software but is automatically cleared when the CPU vectors to the External
Interrupt 1 service routine if IT1 = 1. This flag is the inverse of the /INT1 input signal’s
logic level when IT1 = 0.
Bit2:
Bit1:
Bit0:
IT1: Interrupt 1 Type Select.
This bit selects whether the configured /INT1 signal will detect falling edge or active-low
level-sensitive interrupts.
0: /INT1 is level triggered.
1: /INT1 is edge triggered.
IE0: External Interrupt 0.
This flag is set by hardware when an edge/level of type defined by IT0 is detected. It can
be cleared by software but is automatically cleared when the CPU vectors to the External
Interrupt 0 service routine if IT0 = 1. This flag is the inverse of the /INT0 input signal’s
logic level when IT0 = 0.
IT0: Interrupt 0 Type Select.
This bit selects whether the configured /INT0 signal will detect falling edge or active-low
level-sensitive interrupts.
0: /INT0 is level triggered.
1: /INT0 is edge triggered.
Rev. 1.7
142
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 19.5. TMOD: Timer Mode Register
R/W
GATE1
Bit7
R/W
C/T1
Bit6
R/W
T1M1
Bit5
R/W
T1M0
Bit4
R/W
GATE0
Bit3
R/W
C/T0
Bit2
R/W
T0M1
Bit1
R/W
T0M0
Bit0
Reset Value
00000000
SFR Address:
0x89
Bit7:
Bit6:
GATE1: Timer 1 Gate Control.
0: Timer 1 enabled when TR1 = 1 irrespective of /INT1 logic level.
1: Timer 1 enabled only when TR1 = 1 AND /INT1 = logic level one.
C/T1: Counter/Timer 1 Select.
0: Timer Function: Timer 1 incremented by clock defined by T1M bit (CKCON.4).
1: Counter Function: Timer 1 incremented by high-to-low transitions on external input pin
(T1).
Bits5-4: T1M1-T1M0: Timer 1 Mode Select.
These bits select the Timer 1 operation mode.
T1M1 T1M0 Mode
0
0
1
1
0
1
0
1
Mode 0: 13-bit counter/timer
Mode 1: 16-bit counter/timer
Mode 2: 8-bit counter/timer with auto-reload
Mode 3: Timer 1 Inactive/stopped
Bit3:
Bit2:
GATE0: Timer 0 Gate Control.
0: Timer 0 enabled when TR0 = 1 irrespective of /INT0 logic level.
1: Timer 0 enabled only when TR0 = 1 AND /INT0 = logic level one.
C/T0: Counter/Timer Select.
0: Timer Function: Timer 0 incremented by clock defined by T0M bit (CKCON.3).
1: Counter Function: Timer 0 incremented by high-to-low transitions on external input pin
(T0).
Bits1-0: T0M1-T0M0: Timer 0 Mode Select.
These bits select the Timer 0 operation mode.
T0M1 T0M0 Mode
0
0
1
1
0
1
0
1
Mode 0: 13-bit counter/timer
Mode 1: 16-bit counter/timer
Mode 2: 8-bit counter/timer with auto-reload
Mode 3: Two 8-bit counter/timers
143
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 19.6. CKCON: Clock Control Register
R/W
-
R/W
-
R/W
T2M
Bit5
R/W
T1M
Bit4
R/W
T0M
Bit3
R/W
Reserved
Bit2
R/W
Reserved
Bit1
R/W
Reserved
Bit0
Reset Value
00000000
SFR Address:
Bit7
Bit6
0x8E
Bits7-6: UNUSED. Read = 00b, Write = don’t care.
Bit5:
T2M: Timer 2 Clock Select.
This bit controls the division of the system clock supplied to Timer 2. This bit is ignored
when the timer is in baud rate generator mode or counter mode (i.e. C/T2 = 1).
0: Timer 2 uses the system clock divided by 12.
1: Timer 2 uses the system clock.
Bit4:
Bit3:
T1M: Timer 1 Clock Select.
This bit controls the division of the system clock supplied to Timer 1.
0: Timer 1 uses the system clock divided by 12.
1: Timer 1 uses the system clock.
T0M: Timer 0 Clock Select.
This bit controls the division of the system clock supplied to Counter/Timer 0.
0: Counter/Timer uses the system clock divided by 12.
1: Counter/Timer uses the system clock.
Bits2-0: Reserved. Read = 000b, Must Write = 000.
Rev. 1.7
144
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 19.7. TL0: Timer 0 Low Byte
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Bit0
Reset Value
00000000
SFR Address:
0x8A
Bits 7-0:TL0: Timer 0 Low Byte.
The TL0 register is the low byte of the 16-bit Timer 0.
Figure 19.8. TL1: Timer 1 Low Byte
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Bit0
Reset Value
00000000
SFR Address:
0x8B
Bits 7-0:TL1: Timer 1 Low Byte.
The TL1 register is the low byte of the 16-bit Timer 1.
Figure 19.9. TH0: Timer 0 High Byte
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Bit0
Reset Value
00000000
SFR Address:
0x8C
Bits 7-0:TH0: Timer 0 High Byte.
The TH0 register is the high byte of the 16-bit Timer 0.
Figure 19.10. TH1: Timer 1 High Byte
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Bit0
Reset Value
00000000
SFR Address:
0x8D
Bits 7-0:TH1: Timer 1 High Byte.
The TH1 register is the high byte of the 16-bit Timer 1.
145
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
19.2. Timer 2
Timer 2 is a 16-bit counter/timer formed by the two 8-bit SFRs: TL2 (low byte) and TH2 (high byte). As with
Timers 0 and 1, Timer 2 can use either the system clock or transitions on an external input pin as its clock source.
The Counter/Timer Select bit C/T2 bit (T2CON.1) selects the clock source for Timer 2. Clearing C/T2 selects the
system clock as the input for the timer (divided by either one or twelve as specified by the Timer Clock Select bit
T2M in CKCON). When C/T2 is set to 1, high-to-low transitions at the T2 input pin increment the counter/timer
register. (Refer to Section 14 for information on selecting and configuring external I/O pins.) Timer 2 can also be
used to start an ADC Data Conversion.
Timer 2 offers capabilities not found in Timer 0 and Timer 1. It operates in one of three modes: 16-bit
Counter/Timer with Capture, 16-bit Counter/Timer with Auto-Reload or Baud Rate Generator Mode. Timer 2’s
operating mode is selected by setting configuration bits in the Timer 2 Control (T2CON) register. Below is a
summary of the Timer 2 operating modes and the T2CON bits used to configure the counter/timer. Detailed
descriptions of each mode follow.
RCLK TCLK CP/RL2
TR2
Mode
0
0
0
0
1
0
1
1
1
1
1
0
16-bit Counter/Timer with Capture
16-bit Counter/Timer with Auto-Reload
Baud Rate Generator for TX
Baud Rate Generator for RX
Baud Rate Generator for TX and RX
Off
0
1
0
X
X
X
X
1
1
1
X
X
Rev. 1.7
146
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
19.2.1. Mode 0: 16-bit Counter/Timer with Capture
In this mode, Timer 2 operates as a 16-bit counter/timer with capture facility. A high-to-low transition on the T2EX
input pin causes the 16-bit value in Timer 2 (TH2, TL2) to be loaded into the capture registers (RCAP2H,
RCAP2L).
Timer 2 can use either SYSCLK, SYSCLK divided by 12, or high-to-low transitions on the external T2 pin as its
clock source when operating in Counter/Timer with Capture mode. Clearing the C/T2 bit (T2CON.1) selects the
system clock as the input for the timer (divided by one or twelve as specified by the Timer Clock Select bit T2M in
CKCON). When C/T2 is set to logic 1, a high-to-low transition at the T2 input pin increments the counter/timer
register. As the 16-bit counter/timer register increments and overflows from 0xFFFF to 0x0000, the TF2 timer
overflow flag (T2CON.7) is set and an interrupt will occur if the interrupt is enabled.
Counter/Timer with Capture mode is selected by setting the Capture/Reload Select bit CP/RL2 (T2CON.0) and the
Timer 2 Run Control bit TR2 (T2CON.2) to logic 1. The Timer 2 External Enable EXEN2 (T2CON.3) must also be
set to logic 1 to enable a capture. If EXEN2 is cleared, transitions on T2EX will be ignored.
Figure 19.11. T2 Mode 0 Block Diagram
CKCON
T T T
2 1 0
M M M
12
0
SYSCLK
0
1
T2 Crossbar
1
TCLK
TL2
TH2
CP/RL2
C/T2
TR2
TR2
EXEN2
TCLK
RCLK
EXF2
TF2
Interrupt
Capture
EXEN2
Crossbar
RCAP2L RCAP2H
T2EX
147
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
19.2.2. Mode 1: 16-bit Counter/Timer with Auto-Reload
The Counter/Timer with Auto-Reload mode sets the TF2 timer overflow flag when the counter/timer register
overflows from 0xFFFF to 0x0000. An interrupt is generated if enabled. On overflow, the 16-bit value held in the
two capture registers (RCAP2H, RCAP2L) is automatically loaded into the counter/timer register and the timer is
restarted.
Counter/Timer with Auto-Reload mode is selected by clearing the CP/RL2 bit. Setting TR2 to logic 1 enables and
starts the timer. Timer 2 can use either the system clock or transitions on an external input pin as its clock source, as
specified by the C/T2 bit. If EXEN2 is set to logic 1, a high-to-low transition on T2EX will also cause Timer 2 to
be reloaded. If EXEN2 is cleared, transitions on T2EX will be ignored.
Figure 19.12. T2 Mode 1 Block Diagram
CKCON
T T T
2 1 0
M M M
12
0
SYSCLK
1
0
1
TL2
TH2
T2
Crossbar
TCLK
CP/RL2
C/T2
TR2
EXEN2
TCLK
RCLK
EXF2
TF2
TR2
EXEN2
Interrupt
Reload
RCAP2L RCAP2H
Crossbar
T2EX
Rev. 1.7
148
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
19.2.3. Mode 2: Baud Rate Generator
Timer 2 can be used as a baud rate generator for the serial port (UART) when the UART is operated in modes 1 or 3
(refer to Section 18.1 for more information on UART operational modes). In Baud Rate Generator mode, Timer 2
works similarly to the auto-reload mode. On overflow, the 16-bit value held in the two capture registers (RCAP2H,
RCAP2L) is automatically loaded into the counter/timer register. However, the TF2 overflow flag is not set and no
interrupt is generated. Instead, the overflow event is used as the input to the UART’s shift clock. Timer 2
overflows can be used to generate baud rates for transmit and/or receive independently.
The Baud Rate Generator mode is selected by setting RCLK (T2CON.5) and/or TCLK (T2CON.4) to logic one.
When RCLK or TCLK is set to logic 1, Timer 2 operates in the auto-reload mode regardless of the state of the
CP/RL2 bit. The baud rate for the UART, when operating in mode 1 or 3, is determined by the Timer 2 overflow
rate:
Baud Rate = Timer 2 Overflow Rate / 16.
Note, in all other modes, the timebase for the timer is the system clock divided by one or twelve as selected by the
T2M bit in CKCON. However, in Baud Rate Generator mode, the timebase is the system clock divided by two. No
other divisor selection is possible. If a different time base is required, setting the C/T2 bit to logic 1 will allow the
timebase to be derived from the external input pin T2. In this case, the baud rate for the UART is calculated as:
Baud Rate = FCLK / [32 * (65536 – [RCAP2H:RCAP2L]) ]
Where FCLK is the frequency of the signal supplied to T2 and [RCAP2H:RCAP2L] is the 16-bit value held in the
capture registers.
As explained above, in Baud Rate Generator mode, Timer 2 does not set the TF2 overflow flag and therefore cannot
generate an interrupt. However, if EXEN2 is set to logic 1, a high-to-low transition on the T2EX input pin will set
the EXF2 flag and a Timer 2 interrupt will occur if enabled. Therefore, the T2EX input may be used as an
additional external interrupt source.
Figure 19.13. T2 Mode 2 Block Diagram
SYSCLK
T2
2
C/T2
0
1
Timer 2
Overflow
TL2
TH2
Crossbar
TCLK
1
0
TR2
RX Clock
TX Clock
16
16
Reload
PCON
RCLK
TCLK
RCAP2L RCAP2H
S
M
O
D
S I
G G
F F
1 0
T D
O L
P E
2
1
0
0
1
Timer 1
Overflow
CP/RL2
C/T2
TR2
EXEN2
TCLK
RCLK
EXEN2
Interrupt
EXF2
TF2
Crossbar
T2EX
149
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 19.14. T2CON: Timer 2 Control Register
R/W
TF2
Bit7
R/W
EXF2
Bit6
R/W
RCLK
Bit5
R/W
TCLK
Bit4
R/W
EXEN2
Bit3
R/W
TR2
Bit2
R/W
C/T2
Bit1
R/W
Reset Value
CP/RL2
00000000
SFR Address:
Bit0
(bit addressable)
0xC8
Bit7:
Bit6:
TF2: Timer 2 Overflow Flag.
Set by hardware when Timer 2 overflows from 0xFFFF to 0x0000 or reload value. When
the Timer 2 interrupt is enabled, setting this bit causes the CPU to vector to the Timer 2
interrupt service routine. This bit is not automatically cleared by hardware and must be
cleared by software. TF2 will not be set when RCLK and/or TCLK are logic 1.
EXF2: Timer 2 External Flag.
Set by hardware when either a capture or reload is caused by a high-to-low transition on
the T2EX input pin and EXEN2 is logic 1. When the Timer 2 interrupt is enabled, setting
this bit causes the CPU to vector to the Timer 2 Interrupt service routine. This bit is not
automatically cleared by hardware and must be cleared by software.
Bit5:
Bit4:
Bit3:
RCLK: Receive Clock Flag.
Selects which timer is used for the UART’s receive clock in modes 1 or 3.
0: Timer 1 overflows used for receive clock.
1: Timer 2 overflows used for receive clock.
TCLK: Transmit Clock Flag.
Selects which timer is used for the UART’s transmit clock in modes 1 or 3.
0: Timer 1 overflows used for transmit clock.
1: Timer 2 overflows used for transmit clock.
EXEN2: Timer 2 External Enable.
Enables high-to-low transitions on T2EX to trigger captures or reloads when Timer 2 is not
operating in Baud Rate Generator mode.
0: High-to-low transitions on T2EX ignored.
1: High-to-low transitions on T2EX cause a capture or reload.
Bit2:
Bit1:
Bit0:
TR2: Timer 2 Run Control.
This bit enables/disables Timer 2.
0: Timer 2 disabled.
1: Timer 2 enabled.
C/T2: Counter/Timer Select.
0: Timer Function: Timer 2 incremented by clock defined by T2M (CKCON.5).
1: Counter Function: Timer 2 incremented by high-to-low transitions on external input pin
(T2).
CP/RL2: Capture/Reload Select.
This bit selects whether Timer 2 functions in capture or auto-reload mode. EXEN2 must
be logic 1 for high-to-low transitions on T2EX to be recognized and used to trigger
captures or reloads. If RCLK or TCLK is set, this bit is ignored and Timer 2 will function
in auto-reload mode.
0: Auto-reload on Timer 2 overflow or high-to-low transition at T2EX (EXEN2 = 1).
1: Capture on high-to-low transition at T2EX (EXEN2 = 1).
Rev. 1.7
150
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 19.15. RCAP2L: Timer 2 Capture Register Low Byte
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Bit0
Reset Value
00000000
SFR Address:
0xCA
Bits 7-0:RCAP2L: Timer 2 Capture Register Low Byte.
The RCAP2L register captures the low byte of Timer 2 when Timer 2 is configured in
capture mode. When Timer 2 is configured in auto-reload mode, it holds the low byte of
the reload value.
Figure 19.16. RCAP2H: Timer 2 Capture Register High Byte
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Bit0
Reset Value
00000000
SFR Address:
0xCB
Bits 7-0:RCAP2H: Timer 2 Capture Register High Byte.
The RCAP2H register captures the high byte of Timer 2 when Timer 2 is configured in
capture mode. When Timer 2 is configured in auto-reload mode, it holds the high byte of
the reload value.
Figure 19.17. TL2: Timer 2 Low Byte
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Bit0
Reset Value
00000000
SFR Address:
0xCC
Bits 7-0:TL2: Timer 2 Low Byte.
The TL2 register contains the low byte of the 16-bit Timer 2.
Figure 19.18. TH2: Timer 2 High Byte
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Bit0
Reset Value
00000000
SFR Address:
0xCD
Bits 7-0:TH2: Timer 2 High Byte.
The TH2 register contains the high byte of the 16-bit Timer 2.
151
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
19.3. Timer 3
Timer 3 is a 16-bit timer formed by the two 8-bit SFRs, TMR3L (low byte) and TMR3H (high byte). The input for
Timer 3 is the system clock (divided by either one or twelve as specified by the Timer 3 Clock Select bit T3M in the
Timer 3 Control Register TMR3CN). Timer 3 is always configured as an auto-reload timer, with the reload value
held in the TMR3RLL (low byte) and TMR3RLH (high byte) registers. Timer 3 can be used to start an ADC Data
Conversion, for SMBus timing (see Section 16.5), or as a general-purpose timer. Timer 3 does not have a counter
mode.
Figure 19.19. Timer 3 Block Diagram
T3M
12
0
1
(to ADC)
SYSCLK
TMR3L
TMR3H
TCLK
Interrupt
TF3
TR3
TR3
T3M
(from SMBus)
TOE
Reload
TMR3RLL TMR3RLH
SCL
Crossbar
Figure 19.20. TMR3CN: Timer 3 Control Register
R/W
TF3
Bit7
R/W
R/W
-
R/W
-
R/W
-
R/W
TR3
Bit2
R/W
T3M
Bit1
R/W
Reset Value
-
-
00000000
SFR Address:
Bit6
Bit5
Bit4
Bit3
Bit0
0x91
Bit7:
TF3: Timer3 Overflow Flag.
Set by hardware when Timer 3 overflows from 0xFFFF to 0x0000. When the Timer 3
interrupt is enabled, setting this bit causes the CPU to vector to the Timer 3 Interrupt
service routine. This bit is not automatically cleared by hardware and must be cleared by
software.
Bits6-3: UNUSED. Read = 0000b, Write = don’t care.
Bit2:
Bit1:
Bit0:
TR3: Timer 3 Run Control.
This bit enables/disables Timer 3.
0: Timer 3 disabled.
1: Timer 3 enabled.
T3M: Timer 3 Clock Select.
This bit controls the division of the system clock supplied to Counter/Timer 3.
0: Counter/Timer 3 uses the system clock divided by 12.
1: Counter/Timer 3 uses the system clock.
UNUSED. Read = 0, Write = don’t care.
Rev. 1.7
152
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 19.21. TMR3RLL: Timer 3 Reload Register Low Byte
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Bit0
Reset Value
00000000
SFR Address:
0x92
Bits 7-0:TMR3RLL: Timer 3 Reload Register Low Byte.
Timer 3 is configured as an auto-reload timer. This register holds the low byte of the
reload value.
Figure 19.22. TMR3RLH: Timer 3 Reload Register High Byte
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Bit0
Reset Value
00000000
SFR Address:
0x93
Bits 7-0:TMR3RLH: Timer 3 Reload Register High Byte.
Timer 3 is configured as an auto-reload timer. This register holds the high byte of the
reload value.
Figure 19.23. TMR3L: Timer 3 Low Byte
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Bit0
Reset Value
00000000
SFR Address:
0x94
Bits 7-0:TMR3L: Timer 3 Low Byte.
The TMR3L register is the low byte of Timer 3.
Figure 19.24. TMR3H: Timer 3 High Byte
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Bit0
Reset Value
00000000
SFR Address:
0x95
Bits 7-0:TMR3H: Timer 3 High Byte.
The TMR3H register is the high byte of Timer 3.
153
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
20. PROGRAMMABLE COUNTER ARRAY
The Programmable Counter Array (PCA) provides enhanced timer functionality while requiring less CPU
intervention than the standard 8051 counter/timers. The PCA consists of a dedicated 16-bit counter/timer and five
16-bit capture/compare modules. Each capture/compare module has its own associated I/O line (CEXn) which is
routed through the Crossbar to Port I/O when enabled (see Section 15.1 for details on configuring the Crossbar).
The counter/timer is driven by a configurable timebase that can select between four inputs as its source: system
clock divided by twelve, system clock divided by four, Timer 0 overflow, or an external clock signal on the ECI
line. The PCA is configured and controlled through the system controller’s Special Function Registers. The basic
PCA block diagram is shown in Figure 20.1.
Figure 20.1. PCA Block Diagram
00
/12
/4
System
Clock
01
16-Bit Counter/Timer
10
CPS=11
T0 Overflow
Capture/Compare
Module 0
Capture/Compare
Module 1
Capture/Compare
Module 2
Capture/Compare
Module 3
Capture/Compare
Module 4
Crossbar
Port I/O
Rev. 1.7
154
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
20.1. Capture/Compare Modules
Each module can be configured to operate independently in one of four operation modes: Edge-triggered Capture,
Software Timer, High Speed Output, or Pulse Width Modulator. Each module has Special Function Registers
(SFRs) associated with it in the CIP-51 system controller. These registers are used to exchange data with a module
and configure the module’s mode of operation.
Table 20.1 summarizes the bit settings in the PCA0CPMn registers used to place the PCA capture/compare modules
into different operating modes. Setting the ECCFn bit in a PCA0CPMn register enables the module’s CCFn
interrupt. Note: PCA0 interrupts must be globally enabled before individual CCFn interrupts are recognized. PCA0
interrupts are globally enabled by setting the EA bit (IE.7) and the EPCA0 bit (EIE1.3) to logic 1. See Figure 20.2
for details on the PCA interrupt configuration.
Table 20.1. PCA0CPM Register Settings for PCA Capture/Compare Modules
ECOM
CAPP
CAPN
MAT
TOG
PWM
ECCF
Operation Mode
X
1
0
0
0
0
X
Capture triggered by positive edge on
CEXn
X
0
1
0
0
0
X
Capture triggered by negative edge on
CEXn
X
1
1
0
0
0
1
0
0
0
0
1
0
0
1
0
0
0
0
1
X
X
X
X
Capture triggered by transition on CEXn
Software Timer
1
1
High Speed Output
Pulse Width Modulator
1
X
X = Don’t Care
Figure 20.2. PCA Interrupt Block Diagram
(for n = 0 to 4)
PCA0CPMn
PCA0CN
PCA0MD
E C C M T
C A A A O
O P P T G
M P N n n
n n n
P
W
M
n
E
C
C
F
n
C C C C C C C
F R C C C C C
F F F F F
C
I
C C E
P P C
S S F
1 0
D
L
4 3 2 1 0
0
1
PCA Counter/
Timer Overflow
ECCF0
ECCF1
ECCF2
ECCF3
ECCF4
EPCA0
EA
0
1
(EIE1.3)
(IE.7)
PCA Module 0
PCA Module 1
PCA Module 2
PCA Module 3
PCA Module 4
Interrupt
Priority
0
1
0
1
Decoder
0
1
0
1
0
1
0
1
155
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
20.1.1. Edge-triggered Capture Mode
In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA counter/timer and
load it into the corresponding module’s 16-bit capture/compare register (PCA0CPLn and PCA0CPHn). The CAPPn
and CAPNn bits in the PCA0CPMn register are used to select the type of transition that triggers the capture: low-to-
high transition (positive edge), high-to-low transition (negative edge), or either transition (positive or negative
edge). When a capture occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1 and an interrupt
request is generated if CCF interrupts are enabled. The CCFn bit is not automatically cleared by hardware when the
CPU vectors to the interrupt service routine, and must be cleared by software.
Figure 20.3. PCA Capture Mode Diagram
PCA Interrupt
PCA0CPMn
PCA0CN
E C C M T
C A A A O
O P P T G
M P N n n
n n n
P
W
M
n
E
C
C
F
n
C C C C C C C
F R C C C C C
F F F F F
4 3 2 1 0
0
0 0 0
PCA0CPLn
PCA0CPHn
PCA0H
0
1
CEXn
Capture
Port I/O
Crossbar
0
1
PCA
PCA0L
Timebase
Rev. 1.7
156
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
20.1.2. Software Timer (Compare) Mode
In Software Timer mode, the PCA counter/timer is compared to the module’s 16-bit capture/compare register
(PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to
logic 1 and an interrupt request is generated if CCF interrupts are enabled. The CCFn bit is not automatically
cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by software.
Setting the ECOMn and MATn bits in the PCA0CPMn register enables Software Timer mode.
Figure 20.4. PCA Software Timer Mode Diagram
Write to
0
PCA0CPLn
Reset
ENB
Write to
PCA0CPHn
PCA Interrupt
ENB
1
PCA0CPMn
PCA0CN
E C C M T
C A A A O
O P P T G
M P N n n
n n n
P
W
M
n
E
C
C
F
n
C C C C C C C
F R C C C C C
F F F F F
PCA0CPLn
PCA0CPHn
4 3 2 1 0
0
0
0
0
x
0
1
Enable
Match
16-bit Comparator
PCA
PCA0L
PCA0H
Timebase
20.1.3. High Speed Output Mode
In this mode, each time a match occurs between the PCA Timer Counter and a module’s 16-bit capture/compare
register (PCA0CPHn and PCA0CPLn) the logic level on the module’s associated CEXn pin will toggle. Setting the
TOGn, MATn, and ECOMn bits in the PCA0CPMn register enables the High-Speed Output mode.
Figure 20.5. PCA High Speed Output Mode Diagram
Write to
0
PCA0CPLn
Reset
ENB
Write to
PCA0CPHn
PCA0CPMn
ENB
E C C M T
C A A A O
O P P T G
M P N n n
n n n
P
W
M
n
E
C
C
F
n
1
PCA Interrupt
0
0
0
x
PCA0CN
C C C C C C C
F R C C C C C
F F F F F
PCA0CPLn
PCA0CPHn
4 3 2 1 0
0
1
Enable
Match
16-bit Comparator
TOGn
0
Toggle
CEXn
Crossbar
Port I/O
1
PCA
Timebase
PCA0L
PCA0H
157
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
20.1.4. Pulse Width Modulator Mode
All of the modules can be used independently to generate pulse width modulated (PWM) outputs on their respective
CEXn pin. The frequency of the output is dependent on the timebase for the PCA counter/timer. The duty cycle of
the PWM output signal is varied using the module’s PCA0CPLn capture/compare register. When the value in the
low byte of the PCA counter/timer (PCA0L) is equal to the value in PCA0CPLn, the output on the CEXn pin will
be set. When the count value in PCA0L overflows, the CEXn output will be reset (see Figure 20.6). Also, when
the counter/timer low byte (PCA0L) overflows from 0xFF to 0x00, PCA0CPLn is reloaded automatically with the
value stored in the PCA0CPHn without software intervention. It is good practice to write to PCA0CPHn instead of
PCA0CPLn to avoid glitches in the digital comparator. Setting the ECOMn and PWMn bits in the PCA0CPMn
register enables Pulse Width Modulator mode.
Figure 20.6. PCA PWM Mode Diagram
PCA0CPHn
Write to
0
PCA0CPLn
Reset
ENB
PCA0CPMn
Write to
PCA0CPHn
E C C M T P E
C A A A O W C
O P P T G M C
M P N n n n F
ENB
1
PCA0CPLn
n n n
n
0
0 x 0
x
SET
CLR
8-bit
match
CEXn
Enable
S
R
Q
Q
Crossbar
Port I/O
Comparator
PCA Timebase
PCA0L
Overflow
Rev. 1.7
158
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
20.2. PCA Counter/Timer
The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte (MSB) of
the 16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches the value of
PCA0H at the same time. By reading the PCA0L Register first, this allows the PCA0H value to be held (at the time
PCA0L was read) until the user reads the PCA0H Register. Reading PCA0H or PCA0L does not disturb the
counter operation. The CPS1 and CPS0 bits in the PCA0MD register select the timebase for the counter/timer as
shown in Table 20.2.
When the counter/timer overflows from 0xFFFF to 0x0000, the Counter Overflow Flag (CF) in PCA0MD is set to
logic 1 and an interrupt request is generated if CF interrupts are enabled. Setting the ECF bit in PCA0MD to logic 1
enables the CF flag to generate an interrupt request. The CF bit is not automatically cleared by hardware when the
CPU vectors to the interrupt service routine, and must be cleared by software. (Note: PCA0 interrupts must be
globally enabled before CF interrupts are recognized. PCA0 interrupts are globally enabled by setting the EA bit
(IE.7) and the EPCA0 bit in EIE1 to logic 1.) Clearing the CIDL bit in the PCA0MD register allows the PCA to
continue normal operation while the microcontroller core is in Idle mode.
Table 20.2. PCA Timebase Input Options
CPS1
CPS0
Timebase
0
0
1
1
0
1
0
1
System clock divided by 12
System clock divided by 4
Timer 0 overflow
High-to-low transitions on ECI (max rate = system clock divided by 4)
Figure 20.7. PCA Counter/Timer Block Diagram
IDLE
PCA0MD
PCA0CN
C
I
C C E
P P C
S S F
1 0
C C C C C C C
PCA0L
F R C C C C C
F F F F F
To SFR Bus
read or
write
D
L
4 3 2 1 0
Snapshot
Register
SYSCLK/12
SYSCLK/4
00
01
10
11
0
1
Overflow
To PCA Interrupt System
PCA0H
PCA0L
Timer 0 Overflow
ECI
CF
To PCA Modules
159
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
20.3. Register Descriptions for PCA
The system device may implement one or more Programmable Counter Arrays. Following are detailed descriptions
of the special function registers related to the operation of the PCA. The CIP-51 System Controller section of the
datasheet provides additional information on the SFRs and their use.
Figure 20.8. PCA0CN: PCA Control Register
R/W
CF
R/W
CR
R/W
-
R/W
CCF4
Bit4
R/W
CCF3
Bit3
R/W
CCF2
Bit2
R/W
CCF1
Bit1
R/W
Reset Value
CCF0
00000000
SFR Address:
Bit7
Bit6
Bit5
Bit0
(bit addressable)
0xD8
Bit7:
Bit6:
CF: PCA Counter/Timer Overflow Flag.
Set by hardware when the PCA Counter/Timer overflows from 0xFFFF to 0x0000. When
the Counter/Timer Overflow (CF) interrupt is enabled, setting this bit causes the CPU to
vector to the CF interrupt service routine. This bit is not automatically cleared by
hardware and must be cleared by software.
CR: PCA Counter/Timer Run Control.
This bit enables/disables the PCA Counter/Timer.
0: PCA Counter/Timer disabled.
1: PCA Counter/Timer enabled.
Bit5:
Bit4:
UNUSED. Read = 0, Write = don’t care.
CCF4: PCA Module 4 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is
enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
Bit3:
Bit2:
Bit1:
Bit0:
CCF3: PCA Module 3 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is
enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
CCF2: PCA Module 2 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is
enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
CCF1: PCA Module 1 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is
enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
CCF0: PCA Module 0 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is
enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
Rev. 1.7
160
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 20.9. PCA0MD: PCA Mode Register
R/W
CIDL
Bit7
R/W
-
R/W
-
R/W
-
R/W
-
R/W
CPS1
Bit2
R/W
CPS0
Bit1
R/W
ECF
Bit0
Reset Value
00000000
SFR Address:
Bit6
Bit5
Bit4
Bit3
0xD9
Bit7:
CIDL: PCA Counter/Timer Idle Control.
Specifies PCA behavior when CPU is in Idle Mode.
0: PCA continues to function normally while the system controller is in Idle Mode.
1: PCA operation is suspended while the system controller is in Idle Mode.
Bits6-3: UNUSED. Read = 0000b, Write = don’t care.
Bits2-1: CPS1-CPS0: PCA Counter/Timer Pulse Select.
These bits select the timebase source for the PCA counter.
CPS1
CPS0
Timebase
0
0
1
1
0
1
0
1
System clock divided by 12
System clock divided by 4
Timer 0 overflow
High-to-low transitions on ECI (max rate = system clock divided by 4)
Bit0:
ECF: PCA Counter/Timer Overflow Interrupt Enable.
This bit sets the masking of the PCA Counter/Timer Overflow (CF) interrupt.
0: Disable the CF interrupt.
1: Enable a PCA Counter/Timer Overflow interrupt request when CF (PCA0CN.7) is set.
161
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 20.10. PCA0CPMn: PCA Capture/Compare Registers
R/W
-
R/W
ECOMn
Bit6
R/W
CAPPn
Bit5
R/W
CAPNn
Bit4
R/W
MATn
Bit3
R/W
TOGn
Bit2
R/W
PWMn
Bit1
R/W
ECCFn
Bit0
Reset Value
00000000
SFR Address:
0xDA-0xDE
Bit7
PCA0CPMn Address: PCA0CPM0 = 0xDA (n = 0)
PCA0CPM1 = 0xDB (n = 1)
PCA0CPM2 = 0xDC (n = 2)
PCA0CPM3 = 0xDD (n = 3)
PCA0CPM4 = 0xDE (n = 4)
Bit7:
UNUSED. Read = 0, Write = don’t care.
Bit6: ECOMn: Comparator Function Enable.
This bit enables/disables the comparator function for PCA module n.
0: Disabled.
1: Enabled.
Bit5:
Bit4:
Bit3:
CAPPn: Capture Positive Function Enable.
This bit enables/disables the positive edge capture for PCA module n.
0: Disabled.
1: Enabled.
CAPNn: Capture Negative Function Enable.
This bit enables/disables the negative edge capture for PCA module n.
0: Disabled.
1: Enabled.
MATn: Match Function Enable.
This bit enables/disables the match function for PCA module n. When enabled, matches of
the PCA counter with a module’s capture/compare register cause the CCFn bit in
PCA0MD register to be set.
0: Disabled.
1: Enabled.
Bit2:
TOGn: Toggle Function Enable.
This bit enables/disables the toggle function for PCA module n. When enabled, matches
of the PCA counter with a module’s capture/compare register cause the logic level on the
CEXn pin to toggle.
0: Disabled.
1: Enabled.
Bit1:
Bit0:
PWMn: Pulse Width Modulation Mode Enable.
This bit enables/disables the comparator function for PCA module n. When enabled, a
pulse width modulated signal is output on the CEXn pin.
0: Disabled.
1: Enabled.
ECCFn: Capture/Compare Flag Interrupt Enable.
This bit sets the masking of the Capture/Compare Flag (CCFn) interrupt.
0: Disable CCFn interrupts.
1: Enable a Capture/Compare Flag interrupt request when CCFn is set.
Rev. 1.7
162
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 20.11. PCA0L: PCA Counter/Timer Low Byte
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Bit0
Reset Value
00000000
SFR Address:
0xE9
Bits 7-0:PCA0L: PCA Counter/Timer Low Byte.
The PCA0L register holds the low byte (LSB) of the 16-bit PCA Counter/Timer.
Figure 20.12. PCA0H: PCA Counter/Timer High Byte
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Bit0
Reset Value
00000000
SFR Address:
0xF9
Bits 7-0:PCA0H: PCA Counter/Timer High Byte.
The PCA0H register holds the high byte (MSB) of the 16-bit PCA Counter/Timer. Note
the value read is actually from the snapshot register in order to synchronize it with PCA0L.
Figure 20.13. PCA0CPLn: PCA Capture Module Low Byte
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Bit0
Reset Value
00000000
SFR Address:
0xEA-0xEE
PCA0CPLn Address: PCA0CPL0 = 0xEA (n = 0)
PCA0CPL1 = 0xEB (n = 1)
PCA0CPL2 = 0xEC (n = 2)
PCA0CPL3 = 0xED (n = 3)
PCA0CPL4 = 0xEE (n = 4)
Bits7-6: PCA0CPLn: PCA Capture Module Low Byte.
The PCA0CPLn register holds the low byte (LSB) of the 16-bit capture module n.
Figure 20.14. PCA0CPHn: PCA Capture Module High Byte
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Bit0
Reset Value
00000000
SFR Address:
0xFA-0xFE
PCA0CPHn Address:
PCA0CPH0 = 0xFA (n = 0)
PCA0CPH1 = 0xFB (n = 1)
PCA0CPH2 = 0xFC (n = 2)
PCA0CPH3 = 0xFD (n = 3)
PCA0CPH4 = 0xFE (n = 4)
Bits7-0: PCA0CPHn: PCA Capture Module High Byte.
163
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
21. JTAG (IEEE 1149.1)
Each MCU has an on-chip JTAG interface and logic to support boundary scan for production and in-system testing,
Flash read and write operations, and non-intrusive in-circuit debug. The JTAG interface is fully compliant with the
IEEE 1149.1 specification. Refer to this specification for detailed descriptions of the Test Interface and Boundary-
Scan Architecture. Access of the JTAG Instruction Register (IR) and Data Registers (DR) are as described in the
Test Access Port and Operation of the IEEE 1149.1 specification.
The JTAG interface is via four dedicated pins on the MCU, which are TCK, TMS, TDI, and TDO. These pins are
all 5V tolerant.
Through the 16-bit JTAG Instruction Register (IR), any of the eight instructions shown in Figure 21.1 can be
commanded. There are three Data Registers (DR’s) associated with JTAG Boundary-Scan, and four associated with
Flash read/write operations on the MCU.
Figure 21.1. IR: JTAG Instruction Register
Reset Value
0x0004
Bit15
Bit0
IR value
0x0000
Instruction
EXTEST
Description
Selects the Boundary Data Register for control and observability of all
device pins
0x0002
SAMPLE/
PRELOAD
IDCODE
Selects the Boundary Data Register for observability and presetting the
scan-path latches
Selects device ID Register
Selects Bypass Data Register
Selects FLASHCON Register to control how the interface logic responds to
reads and writes to the FLASHDAT Register
Selects FLASHDAT Register for reads and writes to the Flash memory
Selects FLASHADR Register which holds the address of all Flash read,
write, and erase operations
Selects FLASHSCL Register which controls the prescaler used to generate
timing signals for Flash operations
0x0004
0xFFFF
0x0082
BYPASS
Flash Control
0x0083
0x0084
Flash Data
Flash Address
0x0085
Flash Scale
Rev. 1.7
164
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
21.1. Boundary Scan
The Data Register in the Boundary Scan path is an 87-bit shift register. The Boundary DR provides control and
observability of all the device pins as well as the SFR bus and Weak Pullup feature via the EXTEST and SAMPLE
commands.
Table 21.1. Boundary Data Register Bit Definitions
EXTEST provides access to both capture and update actions, while Sample only performs a capture.
Bit
Action
Capture Reset Enable from MCU
Update Reset Enable to /RST pin
Capture Reset input from /RST pin
Update Reset output to /RST pin
Capture External Clock from XTAL1 pin
Update Not used
Capture Weak pullup enable from MCU
Update Weak pullup enable to Port Pins
Capture SFR Address Bus bit from CIP-51 (e.g. Bit4=SFRA0, Bit5=SFRA1…)
Update SFR Address Bus bit to SFR Address Bus (e.g. Bit4=XSFRA0, Bit5=XSFRA1)
Capture SFR Data Bus bit read from SFR (e.g. Bit12=SFRD0, Bit13=SFRD1…)
Update SFR Data Bus bit written to SFR (e.g. Bit12=SFRD0, Bit13=SFRD1…)
Capture SFR Write Strobe from CIP-51
Update SFR Write Strobe to SFR Bus
Capture SFR Read Strobe from CIP-51
Update SFR Read Strobe to SFR Bus
Capture SFR Read/Modify/Write Strobe from CIP-51
Update SFR Read/Modify/Write Strobe to SFR Bus
Capture P0.n output enable from MCU (e.g. Bit23=P0.0, Bit25=P0.1, etc.)
Update P0.n output enable to pin (e.g. Bit23=P0.0oe, Bit25=P0.1oe, etc.)
Capture P0.n input from pin (e.g. Bit24=P0.0, Bit26=P0.1, etc.)
Update P0.n output to pin (e.g. Bit24=P0.0, Bit26=P0.1, etc.)
Capture P1.n output enable from MCU (e.g. Bit39=P1.0, Bit41=P1.1, etc.)
Update P1.n output enable to pin (e.g. Bit39=P1.0oe, Bit41=P1.1oe, etc.)
Capture P1.n input from pin (e.g. Bit40=P1.0, Bit42=P1.1, etc.)
Update P1.n output to pin (e.g. Bit40=P1.0, Bit42=P1.1, etc.)
Capture P2.n output enable from MCU (e.g. Bit55=P2.0, Bit57=P2.1, etc.)
Update P2.n output enable to pin (e.g. Bit55=P2.0oe, Bit57=P2.1oe, etc.)
Capture P2.n input from pin (e.g. Bit56=P2.0, Bit58=P2.1, etc.)
Update P2.n output to pin (e.g. Bit56=P2.0, Bit58=P2.1, etc.)
Capture P3.n output enable from MCU (e.g. Bit71=P3.0, Bit73=P3.1, etc.)
Update P3.n output enable to pin (e.g. Bit71=P3.0oe, Bit73=P3.1oe, etc.)
Capture P3.n input from pin (e.g. Bit72=P3.0, Bit74=P3.1, etc.)
Update P3.n output to pin (e.g. Bit72=P3.0, Bit74=P3.1, etc.)
Target
0
1
2
3
4-11
12-19
20
21
22
23,25,27,29,
31,33,35,37
24,26,28,30,
32,34,36,38
39,41,43,45,
47,49,51,53
40,42,44,46,
48,50,52,54
55,57,59,61,
63,65,67,69
56,58,60,62,
64,66,68,70
71,73,75,77,
79,81,83,85
72,74,76,78,
80,82,84,86
165
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
21.1.1. EXTEST Instruction
The EXTEST instruction is accessed via the IR. The Boundary DR provides control and observability of all the
device pins as well as the SFR bus and Weak Pullup feature. All inputs to on-chip logic are set to one.
21.1.2. SAMPLE Instruction
The SAMPLE instruction is accessed via the IR. The Boundary DR provides observability and presetting of the
scan-path latches.
21.1.3. BYPASS Instruction
The BYPASS instruction is accessed via the IR. It provides access to the standard 1-bit JTAG Bypass data register.
21.1.4. IDCODE Instruction
The IDCODE instruction is accessed via the IR. It provides access to the 32-bit Device ID register.
Figure 21.2. DEVICEID: JTAG Device ID Register
Reset Value
(Varies)
Version
Part Number
Manufacturer ID
1
Bit31
Bit28 Bit27
Bit12 Bit11
Bit1 Bit0
Version = 0000b (Revision A) or
= 0001b (Revision B)
Part Number = 0000 0000 0000 0000b or
= 0000 0000 0000 0010b
Manufacturer ID = 0010 0100 001b (Silicon Laboratories)
Rev. 1.7
166
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
21.2. Flash Programming Commands
The Flash memory can be programmed directly over the JTAG interface using the Flash Control, Flash Data, Flash
Address, and Flash Scale registers. These Indirect Data Registers are accessed via the JTAG Instruction Register.
Read and write operations on indirect data registers are performed by first setting the appropriate DR address in the
IR register. Each read or write is then initiated by writing the appropriate Indirect Operation Code (IndOpCode) to
the selected data register. Incoming commands to this register have the following format:
19:18
IndOpCode
17:0
WriteData
IndOpCode: These bit set the operation to perform according to the following table:
IndOpCode
Operation
Poll
0x
10
11
Read
Write
The Poll operation is used to check the Busy bit as described below. Although a Capture-DR is performed, no
Update-DR is allowed for the Poll operation. Since updates are disabled, polling can be accomplished by shifting
in/out a single bit.
The Read operation initiates a read from the register addressed by the IR. Reads can be initiated by shifting only 2
bits into the indirect register. After the read operation is initiated, polling of the Busy bit must be performed to
determine when the operation is complete.
The write operation initiates a write of WriteData to the register addressed by the IR. Registers of any width up to
18 bits can be written. If the register to be written contains fewer than 18 bits, the data in WriteData should be left-
justified, i.e. its MSB should occupy bit 17 above. This allows shorter registers to be written in fewer JTAG clock
cycles. For example, an 8-bit register could be written by shifting only 10 bits. After a Write is initiated, the Busy
bit should be polled to determine when the next operation can be initiated. The contents of the Instruction Register
should not be altered while either a read or write operation is in progress.
Outgoing data from the indirect Data Register has the following format:
19
0
18:1
ReadData
0
Busy
The Busy bit indicates that the current operation is not complete. It goes high when an operation is initiated and
returns low when complete. Read and Write commands are ignored while Busy is high. In fact, if polling for Busy
to be low will be followed by another read or write operation, JTAG writes of the next operation can be made while
checking for Busy to be low. They will be ignored until Busy is read low, at which time the new operation will
initiate. This bit is placed at bit 0 to allow polling by single-bit shifts. When waiting for a Read to complete and
Busy is 0, the following 18 bits can be shifted out to obtain the resulting data. ReadData is always right-justified.
This allows registers shorter than 18 bits to be read using a reduced number of shifts. For example, the result from a
byte-read requires 9 bit shifts (Busy + 8 bits).
167
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Figure 21.3. FLASHCON: JTAG Flash Control Register
Reset Value
00000000
WRMD3
Bit7
WRMD2
Bit6
WRMD1
Bit5
WRMD0
Bit4
RDMD3
Bit3
RDMD2
Bit2
RDMD1
Bit1
RDMD0
Bit0
This register determines how the Flash interface logic will respond to reads and writes to the
FLASHDAT Register.
Bits7-4: WRMD3-0: Write Mode Select Bits.
The Write Mode Select Bits control how the interface logic responds to writes to the
FLASHDAT Register per the following values:
0000: A FLASHDAT write replaces the data in the FLASHDAT register, but is otherwise
ignored.
0001: A FLASHDAT write initiates a write of FLASHDAT into the memory location
addressed by the FLASHADR register. FLASHADR is incremented by one when
complete.
0010: A FLASHDAT write initiates an erasure (sets all bytes to 0xFF) of the Flash page
containing the address in FLASHADR. FLASHDAT must be 0xA5 for the erase to
occur. FLASHADR is not affected. If FLASHADR = 0x7DFE – 0x7DFF, the entire
user space will be erased (i.e. entire Flash memory except for Reserved area 0x7E00 –
0x7FFF).
(All other values for WRMD3-0 are reserved.)
Bits3-0: RDMD3-0: Read Mode Select Bits.
The Read Mode Select Bits control how the interface logic responds to reads to the
FLASHDAT Register per the following values:
0000: A FLASHDAT read provides the data in the FASHDAT register, but is otherwise
ignored.
0001: A FLASHDAT read initiates a read of the byte addressed by the FLASHADR register
if no operation is currently active. This mode is used for block reads.
0010: A FLASHDAT read initiates a read of the byte addressed by FLASHADR only if no
operation is active and any data from a previous read has already been read from
FLASHDAT. This mode allows single bytes to be read (or the last byte of a block)
without initiating an extra read.
(All other values for RDMD3-0 are reserved.)
Figure 21.4. FLASHADR: JTAG Flash Address Register
Reset Value
0x0000
Bit15
Bit0
This register holds the address for all JTAG Flash read, write, and erase operations. This register
autoincrements after each read or write, regardless of whether the operation succeeded or failed.
Bits15-0: Flash Operation 16-bit Address.
Rev. 1.7
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C8051F010/1/2/5/6/7
Figure 21.5. FLASHDAT: JTAG Flash Data Register
Reset Value
0000000000
DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
FAIL
Bit1
FBUSY
Bit0
Bit9
Bit8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
This register is used to read or write data to the Flash memory across the JTAG interface.
Bits9-2: DATA7-0: Flash Data Byte.
Bit1:
FAIL: Flash Fail Bit.
0:
1:
Previous Flash memory operation was successful.
Previous Flash memory operation failed. Usually indicates the associated memory
location was locked.
Bit0:
FBUSY: Flash Busy Bit.
0:
1:
Flash interface logic is not busy.
Flash interface logic is processing a request. Reads or writes while FBUSY = 1 will
not initiate another operation
Figure 21.6. FLASHSCL: JTAG Flash Scale Register
Reset Value
00000000
FOSE
Bit7
FRAE
Bit6
-
-
FLSCL3
Bit3
FLSCL2
Bit2
FLSCL1
Bit1
FLSCL0
Bit0
Bit5
Bit4
This register controls the Flash read timing circuit and the prescaler required to generate the correct
timing for Flash operations.
Bit7:
FOSE: Flash One-Shot Enable Bit.
0: Flash read strobe is a full clock-cycle wide.
1: Flash read strobe is 50nsec.
Bit6:
FRAE: Flash Read Always Bit.
0: The Flash output enable and sense amplifier enable are on only when needed to read the
Flash memory.
1: The Flash output enable and sense amplifier enable are always on. This can be used to
limit the variations in digital supply current due to switching the sense amplifiers, thereby
reducing digitally induced noise.
Bits5-4: UNUSED. Read = 00b, Write = don’t care.
Bits3-0: FLSCL3-0: Flash Prescaler Control Bits.
The FLSCL3-0 bits control the prescaler used to generate timing signals for Flash
operations. Its value should be written before any Flash operations are initiated. The value
written should be the smallest integer for which:
FLSCL[3:0] > log2(fSYSCLK / 50kHz)
Where fSYSCLK is the system clock frequency. All Flash read/write/erase operations are
disallowed when FLSCL[3:0] = 1111b.
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C8051F010/1/2/5/6/7
21.3. Debug Support
Each MCU has on-chip JTAG and debug circuitry that provide non-intrusive, full speed, in-circuit debug using the
production part installed in the end application using the four pin JTAG I/F. Silicon Labs’ debug system supports
inspection and modification of memory and registers, setting breakpoints, watchpoints, single stepping, and run and
halt commands. No additional target RAM, program memory, or communications channels are required. All the
digital and analog peripherals are functional and work correctly (remain in sync) while debugging. The WDT is
disabled when the MCU is halted during single stepping or at a breakpoint.
The C8051F000DK, C8051F005DK, C8051F010DK, and C8051F015DK are development kits with all the
hardware and software necessary to develop application code and perform in-circuit debugging with each MCU in
the C8051F000 family. Each kit includes an Integrated Development Environment (IDE) which has a debugger and
integrated 8051 assembler. It has an RS-232 to JTAG protocol translator module referred to as the EC. There is
also a target application board with a C8051F000, F005, F010, or F015 installed and with a large prototyping area.
The kit also includes RS-232 and JTAG cables, and wall-mount power supply.
Rev. 1.7
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C8051F010/1/2/5/6/7
Contact Information
Silicon Laboratories Inc.
4635 Boston Lane
Austin, TX 78735
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Email: productinfo@silabs.com
Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without
notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences
resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning
of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon
Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor
does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims
any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed,
intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of
the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use
Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon
Laboratories harmless against all claims and damages.
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders
171
Rev. 1.7
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