C8051F808-GM [SILICON]
Mixed Signal ISP Flash MCU Family; 混合信号ISP功能的Flash MCU系列
| 型号： | C8051F808-GM |
| 厂家： | 
SILICON |
| 描述： | Mixed Signal ISP Flash MCU Family |
| 文件： | 总250页 (文件大小：1302K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
C8051F80x-83x
Mixed Signal ISP Flash MCU Family
High-Speed 8051 µC Core
Capacitance to Digital Converter
-
Supports buttons, sliders, wheels, and capacitive
proximity sensing
-
Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
-
-
-
-
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Fast 40 µs per channel conversion time
16-bit resolution
Up to 16 input channels
Auto-scan and wake-on-touch
Auto-accumulate 4x, 8x, 16, 32x, and 64x samples
-
-
Up to 25 MIPS throughput with 25 MHz clock
Expanded interrupt handler
Memory
-
-
Up to 512 bytes internal data RAM (256 + 256)
Up to 16 kB Flash; In-system programmable in
512-byte sectors
Analog Peripherals
-
Digital Peripherals
-
10-Bit ADC
17 or 13 Port I/O with high sink current
Hardware enhanced UART, SMBus™ (I2C compati-
ble), and enhanced SPI™ serial ports
Three general purpose 16-bit counter/timers
16-Bit programmable counter array (PCA) with 3
capture/compare modules and enhanced PWM
functionality
•
•
•
•
•
Up to 500 ksps
Up to 16 external single-ended inputs
VREF from on-chip VREF, external pin or VDD
Internal or external start of conversion source
Built-in temperature sensor
-
-
-
-
Comparator
•
•
Programmable hysteresis and response time
Configurable as interrupt or reset source
-
Real time clock mode using timer and crystal
On-Chip Debug
Clock Sources
-
-
-
-
On-chip debug circuitry facilitates full speed, non-
intrusive in-system debug (no emulator required)
Provides breakpoints, single stepping,
inspect/modify memory and registers
Superior performance to emulation systems using
ICE-chips, target pods, and sockets
-
-
-
24.5 MHz ±2% Oscillator
•
Supports crystal-less UART operation
External oscillator: Crystal, RC, C, or clock
(1 or 2 pin modes)
Can switch between clock sources on-the-fly; useful
in power saving modes
Low cost, complete development kit
Supply Voltage 1.8 to 3.6 V
Built-in voltage supply monitor
-
24-Pin QSOP, 20-Pin QFN, 16-Pin SOIC
Temperature Range: –40 to +85 °C
ANALOG
PERIPHERALS
DIGITAL I/O
Port 0
UART
SMBus
SPI
P1.0-
P1.3
A
10-bit
TEMP
M
U
X
500 ksps
ADC
SENSOR
PCA
P1.4-
P1.7
Timer 0
Timer 1
Timer 2
+
–
Capacitive
Sense
P2.0
VOLTAGE
COMPARATOR
24.5 MHz PRECISION INTERNAL OSCILLATOR
HIGH-SPEED CONTROLLER CORE
16 kB
ISP FLASH
FLEXIBLE
INTERRUPTS
8051 CPU
(25 MIPS)
DEBUG
512 B RAM
POR WDT
CIRCUITRY
Rev. 1.0 7/10
Copyright © 2010 by Silicon Laboratories
C8051F80x-83x
C8051F80x-83x
2
Rev. 1.0
C8051F80x-83x
Table of Contents
1. System Overview ..................................................................................................... 15
2. Ordering Information............................................................................................... 25
3. Pin Definitions.......................................................................................................... 28
4. QFN-20 Package Specifications ............................................................................. 33
5. QSOP-24 Package Specifications .......................................................................... 35
6. SOIC-16 Package Specifications............................................................................ 37
7. Electrical Characteristics........................................................................................ 39
7.1. Absolute Maximum Specifications..................................................................... 39
7.2. Electrical Characteristics ................................................................................... 40
8. 10-Bit ADC (ADC0)................................................................................................... 46
8.1. Output Code Formatting.................................................................................... 47
8.2. 8-Bit Mode ......................................................................................................... 47
8.3. Modes of Operation........................................................................................... 47
8.3.1. Starting a Conversion................................................................................ 47
8.3.2. Tracking Modes......................................................................................... 48
8.3.3. Settling Time Requirements...................................................................... 49
8.4. Programmable Window Detector....................................................................... 53
8.4.1. Window Detector Example........................................................................ 55
8.5. ADC0 Analog Multiplexer .................................................................................. 56
9. Temperature Sensor................................................................................................ 58
9.1. Calibration ......................................................................................................... 58
10. Voltage and Ground Reference Options.............................................................. 60
10.1. External Voltage References........................................................................... 61
10.2. Internal Voltage Reference Options ................................................................ 61
10.3. Analog Ground Reference............................................................................... 61
10.4. Temperature Sensor Enable ........................................................................... 61
11. Voltage Regulator (REG0)..................................................................................... 63
12. Comparator0........................................................................................................... 65
12.1. Comparator Multiplexer ................................................................................... 69
13. Capacitive Sense (CS0)......................................................................................... 71
13.1. Configuring Port Pins as Capacitive Sense Inputs.......................................... 72
13.2. Capacitive Sense Start-Of-Conversion Sources ............................................. 72
13.3. Automatic Scanning......................................................................................... 72
13.4. CS0 Comparator.............................................................................................. 73
13.5. CS0 Conversion Accumulator ......................................................................... 74
13.6. Capacitive Sense Multiplexer .......................................................................... 80
14. CIP-51 Microcontroller........................................................................................... 82
14.1. Instruction Set.................................................................................................. 83
14.1.1. Instruction and CPU Timing .................................................................... 83
14.2. CIP-51 Register Descriptions .......................................................................... 88
15. Memory Organization ............................................................................................ 92
15.1. Program Memory............................................................................................. 93
15.1.1. MOVX Instruction and Program Memory ................................................ 93
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C8051F80x-83x
15.2. Data Memory................................................................................................... 93
15.2.1. Internal RAM ........................................................................................... 93
15.2.1.1. General Purpose Registers ............................................................ 94
15.2.1.2. Bit Addressable Locations .............................................................. 94
15.2.1.3. Stack ............................................................................................ 94
16. In-System Device Identification............................................................................ 95
17. Special Function Registers................................................................................... 97
18. Interrupts .............................................................................................................. 102
18.1. MCU Interrupt Sources and Vectors.............................................................. 103
18.1.1. Interrupt Priorities.................................................................................. 103
18.1.2. Interrupt Latency ................................................................................... 103
18.2. Interrupt Register Descriptions...................................................................... 104
18.3. INT0 and INT1 External Interrupts................................................................. 111
19. Flash Memory....................................................................................................... 113
19.1. Programming The Flash Memory.................................................................. 113
19.1.1. Flash Lock and Key Functions.............................................................. 113
19.1.2. Flash Erase Procedure ......................................................................... 113
19.1.3. Flash Write Procedure .......................................................................... 114
19.2. Non-volatile Data Storage ............................................................................. 114
19.3. Security Options ............................................................................................ 114
19.4. Flash Write and Erase Guidelines................................................................. 115
19.4.1. VDD Maintenance and the VDD Monitor .............................................. 116
19.4.2. PSWE Maintenance.............................................................................. 116
19.4.3. System Clock ........................................................................................ 117
20. Power Management Modes................................................................................. 120
20.1. Idle Mode....................................................................................................... 120
20.2. Stop Mode ..................................................................................................... 121
20.3. Suspend Mode .............................................................................................. 121
21. Reset Sources...................................................................................................... 123
21.1. Power-On Reset............................................................................................ 124
21.2. Power-Fail Reset / VDD Monitor ................................................................... 125
21.3. External Reset............................................................................................... 126
21.4. Missing Clock Detector Reset ....................................................................... 126
21.5. Comparator0 Reset ....................................................................................... 127
21.6. PCA Watchdog Timer Reset ......................................................................... 127
21.7. Flash Error Reset .......................................................................................... 127
21.8. Software Reset.............................................................................................. 127
22. Oscillators and Clock Selection ......................................................................... 129
22.1. System Clock Selection................................................................................. 129
22.2. Programmable Internal High-Frequency (H-F) Oscillator.............................. 131
22.3. External Oscillator Drive Circuit..................................................................... 133
22.3.1. External Crystal Example...................................................................... 135
22.3.2. External RC Example............................................................................ 136
22.3.3. External Capacitor Example.................................................................. 137
23. Port Input/Output ................................................................................................. 138
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C8051F80x-83x
23.1. Port I/O Modes of Operation.......................................................................... 139
23.1.1. Port Pins Configured for Analog I/O...................................................... 139
23.1.2. Port Pins Configured For Digital I/O...................................................... 139
23.1.3. Interfacing Port I/O to 5 V Logic............................................................ 140
23.2. Assigning Port I/O Pins to Analog and Digital Functions............................... 140
23.2.1. Assigning Port I/O Pins to Analog Functions ........................................ 140
23.2.2. Assigning Port I/O Pins to Digital Functions.......................................... 141
23.2.3. Assigning Port I/O Pins to External Digital Event Capture Functions ... 142
23.3. Priority Crossbar Decoder ............................................................................. 143
23.4. Port I/O Initialization ...................................................................................... 147
23.5. Port Match ..................................................................................................... 150
23.6. Special Function Registers for Accessing and Configuring Port I/O ............. 152
24. Cyclic Redundancy Check Unit (CRC0)............................................................. 159
24.1. 16-bit CRC Algorithm..................................................................................... 160
24.2. 32-bit CRC Algorithm..................................................................................... 161
24.3. Preparing for a CRC Calculation ................................................................... 162
24.4. Performing a CRC Calculation ...................................................................... 162
24.5. Accessing the CRC0 Result .......................................................................... 162
24.6. CRC0 Bit Reverse Feature............................................................................ 166
25. Enhanced Serial Peripheral Interface (SPI0) ..................................................... 167
25.1. Signal Descriptions........................................................................................ 168
25.1.1. Master Out, Slave In (MOSI)................................................................. 168
25.1.2. Master In, Slave Out (MISO)................................................................. 168
25.1.3. Serial Clock (SCK) ................................................................................ 168
25.1.4. Slave Select (NSS) ............................................................................... 168
25.2. SPI0 Master Mode Operation........................................................................ 168
25.3. SPI0 Slave Mode Operation.......................................................................... 170
25.4. SPI0 Interrupt Sources .................................................................................. 171
25.5. Serial Clock Phase and Polarity .................................................................... 171
25.6. SPI Special Function Registers..................................................................... 173
26. SMBus................................................................................................................... 180
26.1. Supporting Documents.................................................................................. 181
26.2. SMBus Configuration..................................................................................... 181
26.3. SMBus Operation .......................................................................................... 181
26.3.1. Transmitter Vs. Receiver....................................................................... 182
26.3.2. Arbitration.............................................................................................. 182
26.3.3. Clock Low Extension............................................................................. 182
26.3.4. SCL Low Timeout.................................................................................. 182
26.3.5. SCL High (SMBus Free) Timeout ......................................................... 183
26.4. Using the SMBus........................................................................................... 183
26.4.1. SMBus Configuration Register.............................................................. 183
26.4.2. SMB0CN Control Register .................................................................... 187
26.4.2.1. Software ACK Generation ............................................................ 187
26.4.2.2. Hardware ACK Generation........................................................... 187
26.4.3. Hardware Slave Address Recognition .................................................. 189
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5
C8051F80x-83x
26.4.4. Data Register ........................................................................................ 192
26.5. SMBus Transfer Modes................................................................................. 193
26.5.1. Write Sequence (Master) ...................................................................... 193
26.5.2. Read Sequence (Master)...................................................................... 194
26.5.3. Write Sequence (Slave) ........................................................................ 195
26.5.4. Read Sequence (Slave)........................................................................ 196
26.6. SMBus Status Decoding................................................................................ 196
27. UART0................................................................................................................... 201
27.1. Enhanced Baud Rate Generation.................................................................. 202
27.2. Operational Modes ........................................................................................ 203
27.2.1. 8-Bit UART............................................................................................ 203
27.2.2. 9-Bit UART............................................................................................ 204
27.3. Multiprocessor Communications ................................................................... 205
28. Timers ................................................................................................................... 209
28.1. Timer 0 and Timer 1 ...................................................................................... 211
28.1.1. Mode 0: 13-bit Counter/Timer ............................................................... 211
28.1.2. Mode 1: 16-bit Counter/Timer ............................................................... 212
28.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload..................................... 212
28.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................ 213
28.2. Timer 2 .......................................................................................................... 219
28.2.1. 16-bit Timer with Auto-Reload............................................................... 219
28.2.2. 8-bit Timers with Auto-Reload............................................................... 220
29. Programmable Counter Array............................................................................. 225
29.1. PCA Counter/Timer ....................................................................................... 226
29.2. PCA0 Interrupt Sources................................................................................. 227
29.3. Capture/Compare Modules ........................................................................... 228
29.3.1. Edge-Triggered Capture Mode ............................................................. 229
29.3.2. Software Timer (Compare) Mode.......................................................... 230
29.3.3. High-Speed Output Mode ..................................................................... 231
29.3.4. Frequency Output Mode ....................................................................... 232
29.3.5. 8-bit through 15-bit Pulse Width Modulator Modes.............................. 232
29.3.5.1. 8-bit Pulse Width Modulator Mode............................................... 233
29.3.5.2. 9-bit through 15-bit Pulse Width Modulator Mode ....................... 234
29.3.6. 16-Bit Pulse Width Modulator Mode..................................................... 235
29.4. Watchdog Timer Mode .................................................................................. 236
29.4.1. Watchdog Timer Operation................................................................... 236
29.4.2. Watchdog Timer Usage ........................................................................ 237
29.5. Register Descriptions for PCA0..................................................................... 237
30. C2 Interface .......................................................................................................... 244
30.1. C2 Interface Registers................................................................................... 244
30.2. C2CK Pin Sharing ......................................................................................... 247
Document Change List.............................................................................................. 248
Contact Information................................................................................................... 250
6
Rev. 1.0
C8051F80x-83x
List of Tables
1. System Overview
2. Ordering Information
Table 2.1. Product Selection Guide ......................................................................... 26
3. Pin Definitions
Table 3.1. Pin Definitions for the C8051F80x-83x ................................................... 28
4. QFN-20 Package Specifications
Table 4.1. QFN-20 Package Dimensions ................................................................ 33
Table 4.2. QFN-20 PCB Land Pattern Dimensions ................................................. 34
5. QSOP-24 Package Specifications
Table 5.1. QSOP-24 Package Dimensions ............................................................. 35
Table 5.2. QSOP-24 PCB Land Pattern Dimensions .............................................. 36
6. SOIC-16 Package Specifications
Table 6.1. SOIC-16 Package Dimensions ............................................................... 37
Table 6.2. SOIC-16 PCB Land Pattern Dimensions ................................................ 38
7. Electrical Characteristics
Table 7.1. Absolute Maximum Ratings .................................................................... 39
Table 7.2. Global Electrical Characteristics ............................................................. 40
Table 7.3. Port I/O DC Electrical Characteristics ..................................................... 41
Table 7.4. Reset Electrical Characteristics .............................................................. 41
Table 7.5. Internal Voltage Regulator Electrical Characteristics ............................. 41
Table 7.6. Flash Electrical Characteristics .............................................................. 42
Table 7.7. Internal High-Frequency Oscillator Electrical Characteristics ................. 42
Table 7.8. Capacitive Sense Electrical Characteristics ........................................... 42
Table 7.9. ADC0 Electrical Characteristics .............................................................. 43
Table 7.10. Power Management Electrical Characteristics ..................................... 44
Table 7.11. Temperature Sensor Electrical Characteristics .................................... 44
Table 7.12. Voltage Reference Electrical Characteristics ....................................... 44
Table 7.13. Comparator Electrical Characteristics .................................................. 45
8. 10-Bit ADC (ADC0)
9. Temperature Sensor
10. Voltage and Ground Reference Options
11. Voltage Regulator (REG0)
12. Comparator0
13. Capacitive Sense (CS0)
Table 13.1. Operation with Auto-scan and Accumulate .......................................... 74
14. CIP-51 Microcontroller
Table 14.1. CIP-51 Instruction Set Summary .......................................................... 84
15. Memory Organization
16. In-System Device Identification
17. Special Function Registers
Table 17.1. Special Function Register (SFR) Memory Map .................................... 97
Table 17.2. Special Function Registers ................................................................... 98
18. Interrupts
Rev. 1.0
7
C8051F80x-83x
Table 18.1. Interrupt Summary .............................................................................. 104
19. Flash Memory
Table 19.1. Flash Security Summary .................................................................... 115
20. Power Management Modes
21. Reset Sources
22. Oscillators and Clock Selection
23. Port Input/Output
Table 23.1. Port I/O Assignment for Analog Functions ......................................... 141
Table 23.2. Port I/O Assignment for Digital Functions ........................................... 142
Table 23.3. Port I/O Assignment for External Digital Event Capture Functions .... 142
24. Cyclic Redundancy Check Unit (CRC0)
Table 24.1. Example 16-bit CRC Outputs ............................................................. 160
Table 24.2. Example 32-bit CRC Outputs ............................................................. 161
25. Enhanced Serial Peripheral Interface (SPI0)
Table 25.1. SPI Slave Timing Parameters ............................................................ 179
26. SMBus
Table 26.1. SMBus Clock Source Selection .......................................................... 184
Table 26.2. Minimum SDA Setup and Hold Times ................................................ 185
Table 26.3. Sources for Hardware Changes to SMB0CN ..................................... 189
Table 26.4. Hardware Address Recognition Examples (EHACK = 1) ................... 190
Table 26.5. SMBus Status Decoding With Hardware ACK Generation Disabled
(EHACK = 0) ....................................................................................... 197
Table 26.6. SMBus Status Decoding With Hardware ACK Generation Enabled
(EHACK = 1) ....................................................................................... 199
27. UART0
Table 27.1. Timer Settings for Standard Baud Rates
Using The Internal 24.5 MHz Oscillator .............................................. 208
Table 27.2. Timer Settings for Standard Baud Rates
Using an External 22.1184 MHz Oscillator ......................................... 208
28. Timers
29. Programmable Counter Array
Table 29.1. PCA Timebase Input Options ............................................................. 226
Table 29.2. PCA0CPM and PCA0PWM Bit Settings for PCA Capture/Compare
1,2,3,4,5,6
Modules
................................................................................. 228
Table 29.3. Watchdog Timer Timeout Intervals1 ................................................... 237
30. C2 Interface
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Rev. 1.0
C8051F80x-83x
List of Figures
1. System Overview
Figure 1.1. C8051F800, C8051F806, C8051F812, C8051F818 Block Diagram ..... 16
Figure 1.2. C8051F801, C8051F807, C8051F813, C8051F819 Block Diagram ..... 17
Figure 1.3. C8051F802, C8051F808, C8051F814, C8051F820 Block Diagram ..... 18
Figure 1.4. C8051F803, C8051F809, C8051F815, C8051F821 Block Diagram ..... 19
Figure 1.5. C8051F804, C8051F810, C8051F816, C8051F822 Block Diagram ..... 20
Figure 1.6. C8051F805, C8051F811, C8051F817, C8051F823 Block Diagram ..... 21
Figure 1.7. C8051F824, C8051F827, C8051F830, C8051F833 Block Diagram ..... 22
Figure 1.8. C8051F825, C8051F828, C8051F831, C8051F834 Block Diagram ..... 23
Figure 1.9. C8051F826, C8051F829, C8051F832, C8051F835 Block Diagram ..... 24
2. Ordering Information
3. Pin Definitions
Figure 3.1. QFN-20 Pinout Diagram (Top View) ..................................................... 30
Figure 3.2. QSOP-24 Pinout Diagram (Top View) ................................................... 31
Figure 3.3. SOIC-16 Pinout Diagram (Top View) .................................................... 32
4. QFN-20 Package Specifications
Figure 4.1. QFN-20 Package Drawing .................................................................... 33
Figure 4.2. QFN-20 Recommended PCB Land Pattern .......................................... 34
5. QSOP-24 Package Specifications
Figure 5.1. QSOP-24 Package Drawing .................................................................. 35
Figure 5.2. QSOP-24 PCB Land Pattern ................................................................. 36
6. SOIC-16 Package Specifications
Figure 6.1. SOIC-16 Package Drawing ................................................................... 37
Figure 6.2. SOIC-16 PCB Land Pattern .................................................................. 38
7. Electrical Characteristics
8. 10-Bit ADC (ADC0)
Figure 8.1. ADC0 Functional Block Diagram ........................................................... 46
Figure 8.2. 10-Bit ADC Track and Conversion Example Timing ............................. 48
Figure 8.3. ADC0 Equivalent Input Circuits ............................................................. 49
Figure 8.4. ADC Window Compare Example: Right-Justified Data ......................... 55
Figure 8.5. ADC Window Compare Example: Left-Justified Data ........................... 55
Figure 8.6. ADC0 Multiplexer Block Diagram .......................................................... 56
9. Temperature Sensor
Figure 9.1. Temperature Sensor Transfer Function ................................................ 58
Figure 9.2. Temperature Sensor Error with 1-Point Calibration at 0 °C .................. 59
10. Voltage and Ground Reference Options
Figure 10.1. Voltage Reference Functional Block Diagram ..................................... 60
11. Voltage Regulator (REG0)
12. Comparator0
Figure 12.1. Comparator0 Functional Block Diagram ............................................. 65
Figure 12.2. Comparator Hysteresis Plot ................................................................ 66
Figure 12.3. Comparator Input Multiplexer Block Diagram ...................................... 69
13. Capacitive Sense (CS0)
Rev. 1.0
9
C8051F80x-83x
Figure 13.1. CS0 Block Diagram ............................................................................. 71
Figure 13.2. Auto-Scan Example ............................................................................. 73
Figure 13.3. CS0 Multiplexer Block Diagram ........................................................... 80
14. CIP-51 Microcontroller
Figure 14.1. CIP-51 Block Diagram ......................................................................... 82
15. Memory Organization
Figure 15.1. C8051F80x-83x Memory Map ............................................................. 92
Figure 15.2. Flash Program Memory Map ............................................................... 93
16. In-System Device Identification
17. Special Function Registers
18. Interrupts
19. Flash Memory
20. Power Management Modes
21. Reset Sources
Figure 21.1. Reset Sources ................................................................................... 123
Figure 21.2. Power-On and VDD Monitor Reset Timing ....................................... 124
22. Oscillators and Clock Selection
Figure 22.1. Oscillator Options .............................................................................. 129
Figure 22.2. External 32.768 kHz Quartz Crystal Oscillator Connection Diagram 136
23. Port Input/Output
Figure 23.1. Port I/O Functional Block Diagram .................................................... 138
Figure 23.2. Port I/O Cell Block Diagram .............................................................. 139
Figure 23.3. Port I/O Overdrive Current ................................................................ 140
Figure 23.4. Priority Crossbar Decoder Potential Pin Assignments ...................... 144
Figure 23.5. Priority Crossbar Decoder Example 1—No Skipped Pins ................. 145
Figure 23.6. Priority Crossbar Decoder Example 2—Skipping Pins ...................... 146
24. Cyclic Redundancy Check Unit (CRC0)
Figure 24.1. CRC0 Block Diagram ........................................................................ 159
25. Enhanced Serial Peripheral Interface (SPI0)
Figure 25.1. SPI Block Diagram ............................................................................ 167
Figure 25.2. Multiple-Master Mode Connection Diagram ...................................... 169
Figure 25.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram
169
Figure 25.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram
170
Figure 25.5. Master Mode Data/Clock Timing ....................................................... 172
Figure 25.6. Slave Mode Data/Clock Timing (CKPHA = 0) ................................... 172
Figure 25.7. Slave Mode Data/Clock Timing (CKPHA = 1) ................................... 173
Figure 25.8. SPI Master Timing (CKPHA = 0) ....................................................... 177
Figure 25.9. SPI Master Timing (CKPHA = 1) ....................................................... 177
Figure 25.10. SPI Slave Timing (CKPHA = 0) ....................................................... 178
Figure 25.11. SPI Slave Timing (CKPHA = 1) ....................................................... 178
26. SMBus
Figure 26.1. SMBus Block Diagram ...................................................................... 180
Figure 26.2. Typical SMBus Configuration ............................................................ 181
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Rev. 1.0
C8051F80x-83x
Figure 26.3. SMBus Transaction ........................................................................... 182
Figure 26.4. Typical SMBus SCL Generation ........................................................ 184
Figure 26.5. Typical Master Write Sequence ........................................................ 193
Figure 26.6. Typical Master Read Sequence ........................................................ 194
Figure 26.7. Typical Slave Write Sequence .......................................................... 195
Figure 26.8. Typical Slave Read Sequence .......................................................... 196
27. UART0
Figure 27.1. UART0 Block Diagram ...................................................................... 201
Figure 27.2. UART0 Baud Rate Logic ................................................................... 202
Figure 27.3. UART Interconnect Diagram ............................................................. 203
Figure 27.4. 8-Bit UART Timing Diagram .............................................................. 203
Figure 27.5. 9-Bit UART Timing Diagram .............................................................. 204
Figure 27.6. UART Multi-Processor Mode Interconnect Diagram ......................... 205
28. Timers
Figure 28.1. T0 Mode 0 Block Diagram ................................................................. 212
Figure 28.2. T0 Mode 2 Block Diagram ................................................................. 213
Figure 28.3. T0 Mode 3 Block Diagram ................................................................. 214
Figure 28.4. Timer 2 16-Bit Mode Block Diagram ................................................. 219
Figure 28.5. Timer 2 8-Bit Mode Block Diagram ................................................... 220
29. Programmable Counter Array
Figure 29.1. PCA Block Diagram ........................................................................... 225
Figure 29.2. PCA Counter/Timer Block Diagram ................................................... 226
Figure 29.3. PCA Interrupt Block Diagram ............................................................ 227
Figure 29.4. PCA Capture Mode Diagram ............................................................. 229
Figure 29.5. PCA Software Timer Mode Diagram ................................................. 230
Figure 29.6. PCA High-Speed Output Mode Diagram ........................................... 231
Figure 29.7. PCA Frequency Output Mode ........................................................... 232
Figure 29.8. PCA 8-Bit PWM Mode Diagram ........................................................ 233
Figure 29.9. PCA 9-bit through 15-Bit PWM Mode Diagram ................................. 234
Figure 29.10. PCA 16-Bit PWM Mode ................................................................... 235
Figure 29.11. PCA Module 2 with Watchdog Timer Enabled ................................ 236
30. C2 Interface
Figure 30.1. Typical C2 Pin Sharing ...................................................................... 247
Rev. 1.0
11
C8051F80x-83x
List of Registers
SFR Definition 8.1. ADC0CF: ADC0 Configuration ...................................................... 50
SFR Definition 8.2. ADC0H: ADC0 Data Word MSB .................................................... 51
SFR Definition 8.3. ADC0L: ADC0 Data Word LSB ...................................................... 51
SFR Definition 8.4. ADC0CN: ADC0 Control ................................................................ 52
SFR Definition 8.5. ADC0GTH: ADC0 Greater-Than Data High Byte .......................... 53
SFR Definition 8.6. ADC0GTL: ADC0 Greater-Than Data Low Byte ............................ 53
SFR Definition 8.7. ADC0LTH: ADC0 Less-Than Data High Byte ................................ 54
SFR Definition 8.8. ADC0LTL: ADC0 Less-Than Data Low Byte ................................. 54
SFR Definition 8.9. ADC0MX: AMUX0 Channel Select ................................................ 57
SFR Definition 10.1. REF0CN: Voltage Reference Control .......................................... 62
SFR Definition 11.1. REG0CN: Voltage Regulator Control .......................................... 64
SFR Definition 12.1. CPT0CN: Comparator0 Control ................................................... 67
SFR Definition 12.2. CPT0MD: Comparator0 Mode Selection ..................................... 68
SFR Definition 12.3. CPT0MX: Comparator0 MUX Selection ...................................... 70
SFR Definition 13.1. CS0CN: Capacitive Sense Control .............................................. 75
SFR Definition 13.2. CS0CF: Capacitive Sense Configuration ..................................... 76
SFR Definition 13.3. CS0DH: Capacitive Sense Data High Byte ................................. 77
SFR Definition 13.4. CS0DL: Capacitive Sense Data Low Byte ................................... 77
SFR Definition 13.5. CS0SS: Capacitive Sense Auto-Scan Start Channel .................. 78
SFR Definition 13.6. CS0SE: Capacitive Sense Auto-Scan End Channel ................... 78
SFR Definition 13.7. CS0THH: Capacitive Sense Comparator Threshold High Byte ... 79
SFR Definition 13.8. CS0THL: Capacitive Sense Comparator Threshold Low Byte .... 79
SFR Definition 13.9. CS0MX: Capacitive Sense Mux Channel Select ......................... 81
SFR Definition 14.1. DPL: Data Pointer Low Byte ........................................................ 88
SFR Definition 14.2. DPH: Data Pointer High Byte ....................................................... 88
SFR Definition 14.3. SP: Stack Pointer ......................................................................... 89
SFR Definition 14.4. ACC: Accumulator ....................................................................... 89
SFR Definition 14.5. B: B Register ................................................................................ 90
SFR Definition 14.6. PSW: Program Status Word ........................................................ 91
SFR Definition 16.1. HWID: Hardware Identification Byte ............................................ 95
SFR Definition 16.2. DERIVID: Derivative Identification Byte ....................................... 96
SFR Definition 16.3. REVID: Hardware Revision Identification Byte ............................ 96
SFR Definition 18.1. IE: Interrupt Enable .................................................................... 105
SFR Definition 18.2. IP: Interrupt Priority .................................................................... 106
SFR Definition 18.3. EIE1: Extended Interrupt Enable 1 ............................................ 107
SFR Definition 18.4. EIE2: Extended Interrupt Enable 2 ............................................ 108
SFR Definition 18.5. EIP1: Extended Interrupt Priority 1 ............................................ 109
SFR Definition 18.6. EIP2: Extended Interrupt Priority 2 ............................................ 110
SFR Definition 18.7. IT01CF: INT0/INT1 Configuration .............................................. 112
SFR Definition 19.1. PSCTL: Program Store R/W Control ......................................... 118
SFR Definition 19.2. FLKEY: Flash Lock and Key ...................................................... 119
SFR Definition 20.1. PCON: Power Control ................................................................ 122
SFR Definition 21.1. VDM0CN: VDD Monitor Control ................................................ 126
12
Rev. 1.0
C8051F80x-83x
SFR Definition 21.2. RSTSRC: Reset Source ............................................................ 128
SFR Definition 22.1. CLKSEL: Clock Select ............................................................... 130
SFR Definition 22.2. OSCICL: Internal H-F Oscillator Calibration .............................. 131
SFR Definition 22.3. OSCICN: Internal H-F Oscillator Control ................................... 132
SFR Definition 22.4. OSCXCN: External Oscillator Control ........................................ 134
SFR Definition 23.1. XBR0: Port I/O Crossbar Register 0 .......................................... 148
SFR Definition 23.2. XBR1: Port I/O Crossbar Register 1 .......................................... 149
SFR Definition 23.3. P0MASK: Port 0 Mask Register ................................................. 151
SFR Definition 23.4. P0MAT: Port 0 Match Register .................................................. 151
SFR Definition 23.5. P1MASK: Port 1 Mask Register ................................................. 152
SFR Definition 23.6. P1MAT: Port 1 Match Register .................................................. 152
SFR Definition 23.7. P0: Port 0 ................................................................................... 153
SFR Definition 23.8. P0MDIN: Port 0 Input Mode ....................................................... 154
SFR Definition 23.9. P0MDOUT: Port 0 Output Mode ................................................ 154
SFR Definition 23.10. P0SKIP: Port 0 Skip ................................................................. 155
SFR Definition 23.11. P1: Port 1 ................................................................................. 155
SFR Definition 23.12. P1MDIN: Port 1 Input Mode ..................................................... 156
SFR Definition 23.13. P1MDOUT: Port 1 Output Mode .............................................. 156
SFR Definition 23.14. P1SKIP: Port 1 Skip ................................................................. 157
SFR Definition 23.15. P2: Port 2 ................................................................................. 157
SFR Definition 23.16. P2MDOUT: Port 2 Output Mode .............................................. 158
SFR Definition 24.1. CRC0CN: CRC0 Control ........................................................... 163
SFR Definition 24.2. CRC0IN: CRC Data Input .......................................................... 164
SFR Definition 24.3. CRC0DATA: CRC Data Output ................................................. 164
SFR Definition 24.4. CRC0AUTO: CRC Automatic Control ........................................ 165
SFR Definition 24.5. CRC0CNT: CRC Automatic Flash Sector Count ....................... 165
SFR Definition 24.6. CRC0FLIP: CRC Bit Flip ............................................................ 166
SFR Definition 25.1. SPI0CFG: SPI0 Configuration ................................................... 174
SFR Definition 25.2. SPI0CN: SPI0 Control ............................................................... 175
SFR Definition 25.3. SPI0CKR: SPI0 Clock Rate ....................................................... 176
SFR Definition 25.4. SPI0DAT: SPI0 Data ................................................................. 176
SFR Definition 26.1. SMB0CF: SMBus Clock/Configuration ...................................... 186
SFR Definition 26.2. SMB0CN: SMBus Control .......................................................... 188
SFR Definition 26.3. SMB0ADR: SMBus Slave Address ............................................ 191
SFR Definition 26.4. SMB0ADM: SMBus Slave Address Mask .................................. 191
SFR Definition 26.5. SMB0DAT: SMBus Data ............................................................ 192
SFR Definition 27.1. SCON0: Serial Port 0 Control .................................................... 206
SFR Definition 27.2. SBUF0: Serial (UART0) Port Data Buffer .................................. 207
SFR Definition 28.1. CKCON: Clock Control .............................................................. 210
SFR Definition 28.2. TCON: Timer Control ................................................................. 215
SFR Definition 28.3. TMOD: Timer Mode ................................................................... 216
SFR Definition 28.4. TL0: Timer 0 Low Byte ............................................................... 217
SFR Definition 28.5. TL1: Timer 1 Low Byte ............................................................... 217
SFR Definition 28.6. TH0: Timer 0 High Byte ............................................................. 218
SFR Definition 28.7. TH1: Timer 1 High Byte ............................................................. 218
Rev. 1.0
13
C8051F80x-83x
SFR Definition 28.8. TMR2CN: Timer 2 Control ......................................................... 222
SFR Definition 28.9. TMR2RLL: Timer 2 Reload Register Low Byte .......................... 223
SFR Definition 28.10. TMR2RLH: Timer 2 Reload Register High Byte ...................... 223
SFR Definition 28.11. TMR2L: Timer 2 Low Byte ....................................................... 224
SFR Definition 28.12. TMR2H Timer 2 High Byte ....................................................... 224
SFR Definition 29.1. PCA0CN: PCA0 Control ............................................................ 238
SFR Definition 29.2. PCA0MD: PCA0 Mode .............................................................. 239
SFR Definition 29.3. PCA0PWM: PCA0 PWM Configuration ..................................... 240
SFR Definition 29.4. PCA0CPMn: PCA0 Capture/Compare Mode ............................ 241
SFR Definition 29.5. PCA0L: PCA0 Counter/Timer Low Byte .................................... 242
SFR Definition 29.6. PCA0H: PCA0 Counter/Timer High Byte ................................... 242
SFR Definition 29.7. PCA0CPLn: PCA0 Capture Module Low Byte ........................... 243
SFR Definition 29.8. PCA0CPHn: PCA0 Capture Module High Byte ......................... 243
C2 Register Definition 30.1. C2ADD: C2 Address ...................................................... 244
C2 Register Definition 30.3. REVID: C2 Revision ID .................................................. 245
C2 Register Definition 30.2. DEVICEID: C2 Device ID ............................................... 245
C2 Register Definition 30.4. FPCTL: C2 Flash Programming Control ........................ 246
C2 Register Definition 30.5. FPDAT: C2 Flash Programming Data ............................ 246
14
Rev. 1.0
C8051F80x-83x
1. System Overview
C8051F80x-83x devices are fully integrated, mixed-signal, system-on-a-chip capacitive sensing MCUs.
Highlighted features are listed below. Refer to Table 2.1 for specific product feature selection and part
ordering numbers.
High-speed pipelined 8051-compatible microcontroller core (up to 25 MIPS)
In-system, full-speed, non-intrusive debug interface (on-chip)
Capacitive sense interface with 16 input channels
10-bit 500 ksps single-ended ADC with 16-channel analog multiplexer and integrated temperature sensor
Precision calibrated 24.5 MHz internal oscillator
16 kb of on-chip Flash memory
512 bytes of on-chip RAM
SMBus/I2C, Enhanced UART, and Enhanced SPI serial interfaces implemented in hardware
Three general-purpose 16-bit timers
Programmable counter/timer array (PCA) with three capture/compare modules
On-chip internal voltage reference
On-chip Watchdog timer
On-chip power-on reset and supply monitor
On-chip voltage comparator
17 general purpose I/O
With on-chip power-on reset, V
monitor, watchdog timer, and clock oscillator, the C8051F80x-83x
DD
devices are truly stand-alone, system-on-a-chip solutions. The Flash memory can be reprogrammed even
in-circuit, providing non-volatile data storage, and also allowing field upgrades of the 8051 firmware. User
software has complete control of all peripherals, and may individually shut down any or all peripherals for
power savings.
The C8051F80x-83x processors include Silicon Laboratories’ 2-Wire C2 Debug and Programming inter-
face, which allows non-intrusive (uses no on-chip resources), full speed, in-circuit debugging using the pro-
duction MCU installed in the final application. This debug logic supports inspection of memory, viewing and
modification of special function registers, setting breakpoints, single stepping, and run and halt commands.
All analog and digital peripherals are fully functional while debugging using C2. The two C2 interface pins
can be shared with user functions, allowing in-system debugging without occupying package pins.
Each device is specified for 1.8–3.6 V operation over the industrial temperature range (–45 to +85 °C). An
internal LDO regulator is used to supply the processor core voltage at 1.8 V. The Port I/O and RST pins are
tolerant of input signals up to 5 V. See Table 2.1 for ordering information. Block diagrams of the devices in
the C8051F80x-83x family are shown in Figure 1.1 through Figure 1.9.
Rev. 1.0
15
C8051F80x-83x
CIP-51 8051
Port I/O Configuration
Controller Core
Power On
Reset
P0.0/VREF
P0.1/AGND
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7
Digital Peripherals
Flash Memory
‘F800/6: 16 kB
‘F812/8: 8 kB
UART
Reset
Port 0
Drivers
Timers
0, 1
256 Byte RAM
Debug /
Programming
Hardware
RST/C2CK
256 Byte XRAM
Timer 2 /
Priority
RTC
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
Crossbar
P2.0/C2D
Decoder
PCA/
WDT
Port 1
Drivers
SMBus
Peripheral
Power
SFR
Bus
SPI
Core Power
P2.0/C2D
VDD
GND
Regulator
Crossbar Control
Port 2
Drivers
Analog
Peripherals
SYSCLK
16 Channels
Capacitive
Sense
A
M
U
X
Precision
Internal
Oscillator
+
-
VREG Output
Comparator
VDD
External
Clock
Circuit
XTAL1
XTAL2
(‘F800, ‘F812 Only)
VREG Output
VREF
A
M
U
X
10-bit
VDD
16 Channels
500 ksps
ADC
System Clock
Configuration
Temp Sensor
Figure 1.1. C8051F800, C8051F806, C8051F812, C8051F818 Block Diagram
16
Rev. 1.0
C8051F80x-83x
CIP-51 8051
Port I/O Configuration
Controller Core
Power On
Reset
P0.0/VREF
P0.1/AGND
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7
Digital Peripherals
Flash Memory
‘F801/7: 16 kB
‘F813/9: 8 kB
UART
Reset
Port 0
Drivers
Timers
0, 1
256 Byte RAM
Debug /
Programming
Hardware
RST/C2CK
256 Byte XRAM
Timer 2 /
Priority
RTC
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
Crossbar
P2.0/C2D
Decoder
PCA/
WDT
Port 1
Drivers
SMBus
Peripheral
Power
SFR
Bus
SPI
Core Power
P2.0/C2D
VDD
GND
Regulator
Crossbar Control
Port 2
Drivers
Analog
Peripherals
SYSCLK
8 Channels
Capacitive
Sense
A
M
U
X
Precision
Internal
Oscillator
+
-
VREG Output
Comparator
VDD
External
Clock
Circuit
XTAL1
XTAL2
(‘F801, ‘F813 Only)
VREG Output
VREF
A
M
U
X
10-bit
VDD
16 Channels
500 ksps
ADC
System Clock
Configuration
Temp Sensor
Figure 1.2. C8051F801, C8051F807, C8051F813, C8051F819 Block Diagram
Rev. 1.0
17
C8051F80x-83x
CIP-51 8051
Port I/O Configuration
Controller Core
Power On
Reset
P0.0/VREF
P0.1/AGND
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7
Digital Peripherals
Flash Memory
‘F802/8: 16 kB
‘F814, ‘F820: 8 kB
UART
Reset
Port 0
Drivers
Timers
0, 1
256 Byte RAM
Debug /
Programming
Hardware
RST/C2CK
256 Byte XRAM
Timer 2 /
Priority
RTC
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
Crossbar
P2.0/C2D
Decoder
PCA/
WDT
Port 1
Drivers
SMBus
Peripheral
Power
SFR
Bus
SPI
Core Power
P2.0/C2D
VDD
GND
Regulator
Crossbar Control
Port 2
Drivers
SYSCLK
Analog Peripherals
A
M
U
X
Precision
Internal
Oscillator
+
-
VREG Output
Comparator
External
Clock
Circuit
XTAL1
XTAL2
VDD
(‘F802, ‘F814 Only)
VREG Output
VREF
A
M
U
X
10-bit
500 ksps
ADC
VDD
16 Channels
System Clock
Configuration
Temp Sensor
Figure 1.3. C8051F802, C8051F808, C8051F814, C8051F820 Block Diagram
18
Rev. 1.0
C8051F80x-83x
CIP-51 8051
Port I/O Configuration
Controller Core
Power On
Reset
P0.0/VREF
P0.1/AGND
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7
Digital Peripherals
Flash Memory
‘F803/9: 16 kB
‘F815, ‘F821: 8 kB
UART
Reset
Port 0
Drivers
Timers
0, 1
256 Byte RAM
Debug /
Programming
Hardware
RST/C2CK
256 Byte XRAM
Timer 2 /
Priority
RTC
P1.0
P1.1
P1.2
P1.3
Crossbar
P2.0/C2D
Decoder
PCA/
WDT
Port 1
Drivers
SMBus
Peripheral
Power
SFR
Bus
SPI
Core Power
P2.0/C2D
VDD
GND
Regulator
Crossbar Control
Port 2
Drivers
Analog
SYSCLK
12 Channels
Capacitive
Sense
Peripherals
A
M
U
X
Precision
Internal
Oscillator
+
-
VREG Output
Comparator
VDD
External
Clock
Circuit
XTAL1
XTAL2
(‘F803, ‘F815 Only)
VREG Output
VREF
A
M
U
X
10-bit
VDD
12 Channels
500 ksps
ADC
System Clock
Configuration
Temp Sensor
Figure 1.4. C8051F803, C8051F809, C8051F815, C8051F821 Block Diagram
Rev. 1.0
19
C8051F80x-83x
CIP-51 8051
Port I/O Configuration
Controller Core
Power On
Reset
P0.0/VREF
P0.1/AGND
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7
Digital Peripherals
Flash Memory
‘F804, ‘F810: 16 kB
‘F816, ‘F822: 8 kB
UART
Reset
Port 0
Drivers
Timers
0, 1
256 Byte RAM
Debug /
Programming
Hardware
RST/C2CK
256 Byte XRAM
Timer 2 /
Priority
RTC
P1.0
P1.1
P1.2
P1.3
Crossbar
P2.0/C2D
Decoder
PCA/
WDT
Port 1
Drivers
SMBus
Peripheral
Power
SFR
Bus
SPI
Core Power
P2.0/C2D
VDD
GND
Regulator
Crossbar Control
Port 2
Drivers
Analog
SYSCLK
8 Channels
Capacitive
Sense
Peripherals
A
M
U
X
Precision
Internal
Oscillator
+
-
VREG Output
Comparator
VDD
External
Clock
Circuit
XTAL1
XTAL2
(‘F804, ‘F816 Only)
VREG Output
VREF
A
M
U
X
10-bit
VDD
12 Channels
500 ksps
ADC
System Clock
Configuration
Temp Sensor
Figure 1.5. C8051F804, C8051F810, C8051F816, C8051F822 Block Diagram
20
Rev. 1.0
C8051F80x-83x
CIP-51 8051
Port I/O Configuration
Controller Core
Power On
Reset
P0.0/VREF
P0.1/AGND
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7
Digital Peripherals
Flash Memory
‘F805, ‘F811: 16 kB
‘F817, ‘F823: 8 kB
UART
Reset
Port 0
Drivers
Timers
0, 1
256 Byte RAM
Debug /
Programming
Hardware
RST/C2CK
256 Byte XRAM
Timer 2 /
Priority
RTC
P1.0
P1.1
P1.2
P1.3
Crossbar
P2.0/C2D
Decoder
PCA/
WDT
Port 1
Drivers
SMBus
Peripheral
Power
SFR
Bus
SPI
Core Power
P2.0/C2D
VDD
GND
Regulator
Crossbar Control
Port 2
Drivers
SYSCLK
Analog Peripherals
A
M
U
X
Precision
Internal
Oscillator
+
-
VREG Output
Comparator
External
Clock
Circuit
XTAL1
XTAL2
VDD
(‘F805, ‘F817 Only)
VREG Output
VREF
A
M
U
X
10-bit
500 ksps
ADC
VDD
12 Channels
System Clock
Configuration
Temp Sensor
Figure 1.6. C8051F805, C8051F811, C8051F817, C8051F823 Block Diagram
Rev. 1.0
21
C8051F80x-83x
CIP-51 8051
Port I/O Configuration
Controller Core
Power On
Reset
P0.0/VREF
P0.1/AGND
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7
Digital Peripherals
Flash Memory
‘F824, ‘F827: 8 kB
‘F830, ‘F833: 4 kB
UART
Reset
Port 0
Drivers
Timers
0, 1
256 Byte RAM
Debug /
Programming
Hardware
RST/C2CK
Timer 2 /
Priority
RTC
P1.0
P1.1
P1.2
P1.3
Crossbar
P2.0/C2D
Decoder
PCA/
WDT
Port 1
Drivers
SMBus
Peripheral
Power
SFR
Bus
SPI
Core Power
P2.0/C2D
VDD
GND
Regulator
Crossbar Control
Port 2
Drivers
Analog
SYSCLK
12 Channels
Capacitive
Sense
Peripherals
A
M
U
X
Precision
Internal
Oscillator
+
-
VREG Output
Comparator
VDD
External
Clock
Circuit
XTAL1
XTAL2
(‘F824, ‘F830 Only)
VREG Output
VREF
A
M
U
X
10-bit
VDD
12 Channels
500 ksps
ADC
System Clock
Configuration
Temp Sensor
Figure 1.7. C8051F824, C8051F827, C8051F830, C8051F833 Block Diagram
22
Rev. 1.0
C8051F80x-83x
CIP-51 8051
Port I/O Configuration
Controller Core
Power On
Reset
P0.0/VREF
P0.1/AGND
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7
Digital Peripherals
Flash Memory
‘F825, ‘F828: 8 kB
‘F831, ‘F834: 4 kB
UART
Reset
Port 0
Drivers
Timers
0, 1
256 Byte RAM
Debug /
Programming
Hardware
RST/C2CK
Timer 2 /
Priority
RTC
P1.0
P1.1
P1.2
P1.3
Crossbar
P2.0/C2D
Decoder
PCA/
WDT
Port 1
Drivers
SMBus
Peripheral
Power
SFR
Bus
SPI
Core Power
P2.0/C2D
VDD
GND
Regulator
Crossbar Control
Port 2
Drivers
Analog
SYSCLK
8 Channels
Capacitive
Sense
Peripherals
A
M
U
X
Precision
Internal
Oscillator
+
-
VREG Output
Comparator
VDD
External
Clock
Circuit
XTAL1
XTAL2
(‘F825, ‘F831 Only)
VREG Output
VREF
A
M
U
X
10-bit
VDD
12 Channels
500 ksps
ADC
System Clock
Configuration
Temp Sensor
Figure 1.8. C8051F825, C8051F828, C8051F831, C8051F834 Block Diagram
Rev. 1.0
23
C8051F80x-83x
CIP-51 8051
Port I/O Configuration
Controller Core
Power On
Reset
P0.0/VREF
P0.1/AGND
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7
Digital Peripherals
Flash Memory
‘F826, ‘F829: 8 kB
‘F832, ‘F835: 4 kB
UART
Reset
Port 0
Drivers
Timers
0, 1
256 Byte RAM
Debug /
Programming
Hardware
RST/C2CK
Timer 2 /
Priority
RTC
P1.0
P1.1
P1.2
P1.3
Crossbar
P2.0/C2D
Decoder
PCA/
WDT
Port 1
Drivers
SMBus
Peripheral
Power
SFR
Bus
SPI
Core Power
P2.0/C2D
VDD
GND
Regulator
Crossbar Control
Port 2
Drivers
SYSCLK
Analog Peripherals
A
M
U
X
Precision
Internal
Oscillator
+
-
VREG Output
Comparator
External
Clock
Circuit
XTAL1
XTAL2
VDD
(‘F826, ‘F832 Only)
VREG Output
VREF
A
M
U
X
10-bit
500 ksps
ADC
VDD
12 Channels
System Clock
Configuration
Temp Sensor
Figure 1.9. C8051F826, C8051F829, C8051F832, C8051F835 Block Diagram
24
Rev. 1.0
C8051F80x-83x
2. Ordering Information
All C8051F80x-83x devices have the following features:
25 MIPS (Peak)
Calibrated Internal Oscillator
SMBus/I2C
Enhanced SPI
UART
Programmable counter array (3 channels)
3 Timers (16-bit)
1 Comparator
Pb-Free (RoHS compliant) package
In addition to the features listed above, each device in the C8051F80x-83x family has a set of features that
vary across the product line. See Table 2.1 for a complete list of the unique feature sets for each device in
the family.
Rev. 1.0
25
C8051F80x-83x
Table 2.1. Product Selection Guide
C8051F800-GU
C8051F801-GU
C8051F802-GU
C8051F800-GM
C8051F801-GM
C8051F802-GM
C8051F803-GS
C8051F804-GS
C8051F805-GS
C8051F806-GU
C8051F807-GU
C8051F808-GU
C8051F806-GM
C8051F807-GM
C8051F808-GM
C8051F809-GS
C8051F810-GS
C8051F811-GS
C8051F812-GU
C8051F813-GU
C8051F814-GU
C8051F812-GM
C8051F813-GM
C8051F814-GM
C8051F815-GS
C8051F816-GS
C8051F817-GS
C8051F818-GU
C8051F819-GU
C8051F820-GU
C8051F818-GM
C8051F819-GM
C8051F820-GM
17
17
17
17
17
17
13
13
13
17
17
17
17
17
17
13
13
13
17
17
17
17
17
17
13
13
13
17
17
17
17
17
17
16
8
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
8
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
16
16
16
16
16
16
12
12
12
—
—
—
—
—
—
—
—
—
16
16
16
16
16
16
12
12
12
—
—
—
—
—
—
QSOP-24
QSOP-24
QSOP-24
QFN-20
—
16
8
QFN-20
—
12
8
QFN-20
SOIC-16
SOIC-16
SOIC-16
QSOP-24
QSOP-24
QSOP-24
QFN-20
—
16
8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
16
8
QFN-20
—
12
8
QFN-20
SOIC-16
SOIC-16
SOIC-16
QSOP-24
QSOP-24
QSOP-24
QFN-20
—
16
8
8
—
16
8
8
8
8
QFN-20
—
12
8
8
QFN-20
8
SOIC-16
SOIC-16
SOIC-16
QSOP-24
QSOP-24
QSOP-24
QFN-20
8
—
16
8
8
8
—
—
—
—
—
—
—
—
—
—
—
—
8
—
16
8
8
8
8
QFN-20
—
8
QFN-20
26
Rev. 1.0
C8051F80x-83x
Table 2.1. Product Selection Guide (Continued)
C8051F821-GS
C8051F822-GS
C8051F823-GS
C8051F824-GS
C8051F825-GS
C8051F826-GS
C8051F827-GS
C8051F828-GS
C8051F829-GS
C8051F830-GS
C8051F831-GS
C8051F832-GS
C8051F833-GS
C8051F834-GS
C8051F835-GS
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
12
8
8
8
8
8
8
8
8
8
8
4
4
4
4
4
4
512
512
512
256
256
256
256
256
256
256
256
256
256
256
256
—
—
—
—
—
—
12
12
12
—
—
—
12
12
12
—
—
—
—
—
—
SOIC-16
SOIC-16
SOIC-16
SOIC-16
SOIC-16
SOIC-16
SOIC-16
SOIC-16
SOIC-16
SOIC-16
SOIC-16
SOIC-16
SOIC-16
SOIC-16
SOIC-16
—
12
8
—
12
8
—
—
—
—
—
—
—
12
8
—
12
8
—
—
—
—
—
—
—
Lead finish material on all devices is 100% matte tin (Sn).
Rev. 1.0
27
C8051F80x-83x
3. Pin Definitions
Table 3.1. Pin Definitions for the C8051F80x-83x
Name
Pin
Pin
Pin
Type Description
QSOP-24 QFN-20 SOIC-16
GND
5
2
4
Ground.
This ground connection is required. The center
pad may optionally be connected to ground as
well on the QFN-20 packages.
V
6
7
3
4
5
6
Power Supply Voltage.
DD
RST/
D I/O Device Reset. Open-drain output of internal
POR or V monitor. An external source can ini-
DD
tiate a system reset by driving this pin low for at
least 10 µs.
C2CK
P2.0/
D I/O Clock signal for the C2 Debug Interface.
8
5
7
D I/O Bi-directional data signal for the C2 Debug Inter-
face. Shared with P2.0 on 20-pin packaging and
P2.4 on 24-pin packaging.
C2D
D I/O Bi-directional data signal for the C2 Debug Inter-
face. Shared with P2.0 on 20-pin packaging and
P2.4 on 24-pin packaging.
P0.0/
4
1
3
D I/O or Port 0.0.
A In
VREF
P0.1
A In
External VREF input.
3
2
20
19
2
1
D I/O or Port 0.1.
A In
P0.2/
XTAL1
P0.3/
D I/O or Port 0.2.
A In
A In
External Clock Input. This pin is the external
oscillator return for a crystal or resonator.
23
22
18
17
16
15
D I/O or Port 0.3.
A In
XTAL2
A I/O or External Clock Output. For an external crystal or
D In
resonator, this pin is the excitation driver. This
pin is the external clock input for CMOS, capaci-
tor, or RC oscillator configurations.
P0.4
D I/O or Port 0.4.
A In
28
Rev. 1.0
C8051F80x-83x
Table 3.1. Pin Definitions for the C8051F80x-83x (Continued)
Name
Pin
Pin
Pin
Type Description
QSOP-24 QFN-20 SOIC-16
P0.5
P0.6/
CNVSTR
P0.7
21
20
16
15
14
13
D I/O or Port 0.5.
A In
D I/O or Port 0.6.
A In
D In
ADC0 External Convert Start or IDA0 Update
Source Input.
19
18
17
16
15
14
11
10
9
14
13
12
11
10
9
12
11
10
9
D I/O or Port 0.7.
A In
P1.0
D I/O or Port 1.0.
A In
P1.1
D I/O or Port 1.1.
A In
P1.2
D I/O or Port 1.2.
A In
P1.3
8
D I/O or Port 1.3.
A In
P1.4
D I/O or Port 1.4.
A In
P1.5
8
D I/O or Port 1.5.
A In
P1.6
7
D I/O or Port 1.6.
A In
P1.7
6
D I/O or Port 1.7.
A In
NC
1, 12, 13,
24
No Connection.
Rev. 1.0
29
C8051F80x-83x
P0.0
GND
VDD
1
2
3
4
5
15
14
13
12
11
P0.6
P0.7
P1.0
P1.1
P1.2
C8051F80x-GM
C8051F81x-GM
C8051F82x-GM
Top View
RST/C2CK
P2.0/C2D
GND
Figure 3.1. QFN-20 Pinout Diagram (Top View)
30
Rev. 1.0
C8051F80x-83x
TOP VIEW
1
2
24
23
22
21
20
19
18
17
16
15
14
13
NC
P0.2
NC
P0.3
P0.4
P0.5
P0.6
3
P0.1
4
P0.0
5
GND
6
C8051F80x-GU
C8051F81x-GU
C8051F82x-GU
VDD
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
NC
7
RST / C2CK
P2.0/C2D
P1.7
8
9
10
11
12
P1.6
P1.5
NC
Figure 3.2. QSOP-24 Pinout Diagram (Top View)
Rev. 1.0
31
C8051F80x-83x
TOP VIEW
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
P0.2
P0.1
P0.3
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
P0.0
C8051F80x-GS
C8051F81x-GS
C8051F82x-GS
C8051F83x-GS
GND
VDD
RST / C2CK
P2.0/C2D
P1.3
Figure 3.3. SOIC-16 Pinout Diagram (Top View)
32
Rev. 1.0
C8051F80x-83x
4. QFN-20 Package Specifications
Figure 4.1. QFN-20 Package Drawing
Table 4.1. QFN-20 Package Dimensions
Dimension
Min
Typ
Max
Dimension
Min
Typ
Max
A
0.80
0.00
0.18
0.90
0.02
1.00
0.05
0.30
L
0.45
0.00
—
0.55
—
0.65
0.15
0.15
0.10
0.05
0.08
—
A1
L1
b
0.25
aaa
bbb
ddd
eee
Z
—
D
D2
4.00 BSC.
2.15
—
—
2.00
2.00
2.25
2.25
—
—
e
0.50 BSC.
4.00 BSC.
2.15
—
—
E
—
0.43
0.18
E2
Y
—
—
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220, variation VGGD except for
custom features D2, E2, Z, Y, and L which are toleranced per supplier designation.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
Rev. 1.0
33
C8051F80x-83x
Figure 4.2. QFN-20 Recommended PCB Land Pattern
Table 4.2. QFN-20 PCB Land Pattern Dimensions
Dimension
Min
Max
Dimension
Min
Max
C1
C2
E
3.70
3.70
0.50
X2
Y1
Y2
2.15
0.90
2.15
2.25
1.00
2.25
X1
0.20
0.30
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design
4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Stencil Design
5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used
to assure good solder paste release.
6. The stencil thickness should be 0.125 mm (5 mils).
7. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.
8. A 2x2 array of 0.95 mm openings on a 1.1 mm pitch should be used for the center pad to
assure the proper paste volume.
Card Assembly
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small
Body Components.
34
Rev. 1.0
C8051F80x-83x
5. QSOP-24 Package Specifications
Figure 5.1. QSOP-24 Package Drawing
Table 5.1. QSOP-24 Package Dimensions
Dimension
Min
Nom
Max
Dimension
Min
Nom
Max
A
—
—
—
—
1.75
0.25
0.30
L
0.40
—
0.25 BSC
—
1.27
A1
0.10
0.20
0.10
L2
b
0º
8º
c
aaa
bbb
ccc
ddd
0.20
—
0.25
D
8.65 BSC
6.00 BSC
3.90 BSC
0.635 BSC
0.18
E
E1
0.10
0.10
e
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-137, variation AE.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
Rev. 1.0
35
C8051F80x-83x
Figure 5.2. QSOP-24 PCB Land Pattern
Table 5.2. QSOP-24 PCB Land Pattern Dimensions
Dimension
Min
Max
C
E
X
Y
5.20
5.30
0.635 BSC
0.30
1.50
0.40
1.60
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This land pattern design is based on the IPC-7351 guidelines.
Solder Mask Design
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal
pad is to be 60 µm minimum, all the way around the pad.
Stencil Design
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good
solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
Card Assembly
7. A No-Clean, Type-3 solder paste is recommended.
8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
36
Rev. 1.0
C8051F80x-83x
6. SOIC-16 Package Specifications
Figure 6.1. SOIC-16 Package Drawing
Table 6.1. SOIC-16 Package Dimensions
Dimension
Min
Nom
Max
Dimension
Min
Nom
Max
A
—
1.75
0.25
—
L
L2
0.40
1.27
A1
0.10
1.25
0.31
0.17
0.25 BSC
A2
h
0.25
0º
0.50
8º
b
0.51
c
aaa
bbb
ccc
ddd
0.10
0.20
0.10
0.25
0.25
D
9.90 BSC
6.00 BSC
3.90 BSC
1.27 BSC
E
E1
e
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MS-012, Variation AC.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
Rev. 1.0
37
C8051F80x-83x
Figure 6.2. SOIC-16 PCB Land Pattern
Table 6.2. SOIC-16 PCB Land Pattern Dimensions
Dimension
Feature
Pad Column Spacing
Pad Row Pitch
Pad Width
(mm)
5.40
1.27
0.60
1.55
C1
E
X1
Y1
Pad Length
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X165-16N for Density Level B (Median
Land Protrusion).
3. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of
0.05 mm is assumed.
38
Rev. 1.0
C8051F80x-83x
7. Electrical Characteristics
7.1. Absolute Maximum Specifications
Table 7.1. Absolute Maximum Ratings
Parameter
Conditions
Min
Typ
Max
Units
Ambient temperature under bias
Storage Temperature
–55
–65
–0.3
—
—
—
125
150
5.8
°C
°C
V
Voltage on RST or any Port I/O Pin
with respect to GND
Voltage on V with respect to GND
–0.3
—
—
—
4.2
V
DD
Maximum Total current through V
and GND
500
mA
DD
Maximum output current sunk by RST
or any Port pin
—
—
100
mA
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the devices at those or any other conditions above
those indicated in the operation listings of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
Rev. 1.0
39
C8051F80x-83x
7.2. Electrical Characteristics
Table 7.2. Global Electrical Characteristics
–40 to +85 °C, 25 MHz system clock unless otherwise specified.
Parameter
Conditions
Min
Typ
Max Units
Supply Voltage
1.8
3.0
3.6
V
Digital Supply Current with
CPU Active (Normal Mode )
V
V
V
V
V
V
= 1.8 V, Clock = 25 MHz
= 1.8 V, Clock = 1 MHz
= 1.8 V, Clock = 32 kHz
= 3.0 V, Clock = 25 MHz
= 3.0 V, Clock = 1 MHz
= 3.0 V, Clock = 32 kHz
—
—
—
—
—
—
4.6
1.2
135
5.5
1.3
150
6.0
—
—
6.5
—
—
mA
mA
µA
mA
mA
µA
DD
DD
DD
DD
DD
DD
1
Digital Supply Current with
CPU Inactive (Idle Mode )
V
V
V
V
V
V
= 1.8 V, Clock = 25 MHz
= 1.8 V, Clock = 1 MHz
= 1.8 V, Clock = 32 kHz
= 3.0 V, Clock = 25 MHz
= 3.0 V, Clock = 1 MHz
= 3.0 V, Clock = 32 kHz
—
—
—
—
—
—
2
2.6
—
—
2.8
—
—
mA
µA
µA
mA
µA
µA
DD
DD
DD
DD
DD
DD
1
190
100
2.3
335
115
Digital Supply Current
(shutdown)
Oscillator not running (stop mode),
Internal Regulator Off, 25 °C
—
0.5
105
1.3
—
2
µA
µA
V
Oscillator not running (stop or suspend
mode), Internal Regulator On, 25 °C
—
140
—
Digital Supply RAM Data
Retention Voltage
—
Specified Operating Tempera-
ture Range
–40
0
+85
25
°C
SYSCLK (system clock
frequency)
See Note 2
—
MHz
Tsysl (SYSCLK low time)
Tsysh (SYSCLK high time)
Notes:
18
18
—
—
—
—
ns
ns
1. Includes bias current for internal voltage regulator.
2. SYSCLK must be at least 32 kHz to enable debugging.
40
Rev. 1.0
C8051F80x-83x
Table 7.3. Port I/O DC Electrical Characteristics
VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified.
Parameters
Conditions
Min
– 0.7
DD
Typ
Max
Units
Output High Voltage
I
I
I
I
I
I
= –3 mA, Port I/O push-pull
= –10 µA, Port I/O push-pull
= –10 mA, Port I/O push-pull
= 8.5 mA
V
—
—
—
—
—
0.6
0.1
—
—
0.6
1
V
V
V
V
V
V
V
V
µA
µA
OH
OH
OH
OL
OL
OL
V
- 0.1
DD
—
V
- 0.8
DD
Output Low Voltage
—
—
—
—
—
1.0
—
—
—
= 10 µA
= 25 mA
Input High Voltage
Input Low Voltage
Input Leakage
Current
0.75 x V
DD
—
–1
—
Weak Pullup Off
Weak Pullup On, V = 0 V
15
50
IN
Table 7.4. Reset Electrical Characteristics
VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified.
Parameter
Conditions
= 8.5 mA,
Min
Typ
Max
Units
RST Output Low Voltage
I
—
—
0.6
V
OL
V
= 1.8 V to 3.6 V
DD
RST Input High Voltage
RST Input Low Voltage
RST Input Pullup Current
0.75 x V
—
—
—
—
0.3 x V
50
V
DD
V
DD
DD
RST = 0.0 V
—
25
µA
V
V
POR Ramp Time
—
—
1
ms
V
DD
DD
Monitor Threshold (V
)
1.7
1.75
500
1.8
RST
Missing Clock Detector
Timeout
Time from last system clock
rising edge to reset initiation
100
1000
µs
Reset Time Delay
Delay between release of any
reset source and code
execution at location 0x0000
—
—
—
30
µs
µs
Minimum RST Low Time to
Generate a System Reset
15
—
V
V
Monitor Turn-on Time
Monitor Supply Current
V
= V – 0.1 V
RST
—
—
50
20
—
µs
DD
DD
DD
30
µA
Table 7.5. Internal Voltage Regulator Electrical Characteristics
V
= 3.0 V, –40 to +85 °C unless otherwise specified.
DD
Parameter
Conditions
Min
Typ
Max
Units
Input Voltage Range
Bias Current
1.8
—
—
3.6
65
V
50
µA
Rev. 1.0
41
C8051F80x-83x
Table 7.6. Flash Electrical Characteristics
Parameter
Conditions
Min
Typ Max Units
Flash Size (Note 1)
C8051F80x and C8051F810/1
C8051F812/3/4/5/6/7/8/9 and C8051F82x
C8051F830/1/2/3/4/5
16384
8192
4096
bytes
bytes
bytes
Endurance (Erase/Write)
Erase Cycle Time
10000
15
—
20
20
—
—
26
26
—
cycles
ms
25 MHz Clock
25 MHz Clock
Write Cycle Time
15
µs
Clock Speed during Flash
Write/Erase Operations
1
MHz
Note: Includes Security Lock Byte.
Table 7.7. Internal High-Frequency Oscillator Electrical Characteristics
VDD = 1.8 to 3.6 V; TA = –40 to +85 °C unless otherwise specified. Use factory-calibrated settings.
Parameter
Conditions
Min
Typ
Max Units
Oscillator Frequency
Oscillator Supply Current 25 °C, V = 3.0 V,
IFCN = 11b
24
—
24.5
350
25
650
MHz
µA
DD
OSCICN.7 = 1,
OCSICN.5 = 0
Table 7.8. Capacitive Sense Electrical Characteristics
VDD = 1.8 to 3.6 V; TA = –40 to +85 °C unless otherwise specified.
Parameter
Conditions
Single Conversion
Min
Typ
Max
Units
Conversion Time
26
—
—
—
—
—
—
38
1
50
—
µs
fF
Capacitance per Code
External Capacitive Load
—
3
20
40
75
45
—
—
pF
fF
fF
1
Quantization Noise
RMS
Peak-to-Peak
Supply Current
CS module bias current, 25 °C
CS module alone, maximum code
output, 25 °C
60
105
µA
µA
2
Wake-on-CS Threshold , 25 °C
—
150
165
µA
Notes:
1. RMS Noise is equivalent to one standard deviation. Peak-to-peak noise encompasses ±3.3 standard
deviations.
2. Includes only current from regulator, CS module, and MCU in suspend mode.
42
Rev. 1.0
C8051F80x-83x
Table 7.9. ADC0 Electrical Characteristics
V
= 3.0 V, VREF = 2.40 V (REFSL=0), –40 to +85 °C unless otherwise specified.
DD
Parameter
Conditions
Min
Typ
Max
Units
DC Accuracy
Resolution
10
±0.5
±0.5
0
bits
LSB
Integral Nonlinearity
Differential Nonlinearity
Offset Error
—
—
–2
–2
—
±1
±1
2
Guaranteed Monotonic
LSB
LSB
Full Scale Error
0
2
LSB
Offset Temperature Coefficient
45
—
ppm/°C
Dynamic performance (10 kHz sine-wave single-ended input, 1 dB below Full Scale, 200 ksps)
Signal-to-Noise Plus Distortion
Total Harmonic Distortion
54
—
—
60
75
—
—
—
dB
dB
dB
Up to the 5th harmonic
Spurious-Free Dynamic Range
–90
Conversion Rate
SAR Conversion Clock
—
13
11
—
—
—
—
—
—
8.33
—
—
MHz
clocks
clocks
ns
Conversion Time in SAR Clocks 10-bit Mode
8-bit Mode
Track/Hold Acquisition Time
V
V
>= 2.0 V
< 2.0 V
300
2.0
—
—
—
DD
DD
µs
Throughput Rate
500
ksps
Analog Inputs
ADC Input Voltage Range
Sampling Capacitance
0
—
5
3
VREF
—
—
V
1x Gain
0.5x Gain
—
—
—
pF
pF
k
Input Multiplexer Impedance
5
—
Power Specifications
Power Supply Current
Power Supply Rejection
Operating Mode, 500 ksps
—
—
630
–70
1000
—
µA
dB
Rev. 1.0
43
C8051F80x-83x
Table 7.10. Power Management Electrical Characteristics
VDD = 1.8 to 3.6 V; TA = –40 to +85 °C unless otherwise specified. Use factory-calibrated settings.
Parameter
Conditions
Min
Typ
Max
Units
Idle Mode Wake-Up Time
Suspend Mode Wake-up Time
2
—
—
500
3
—
SYSCLKs
ns
Table 7.11. Temperature Sensor Electrical Characteristics
V
= 3.0 V, –40 to +85 °C unless otherwise specified.
DD
Parameter
Conditions
Min
Typ
Max
Units
Linearity
Slope
—
—
—
—
—
1
—
—
—
—
—
°C
mV/°C
µV/°C
mV
2.43
±45
873
14.5
Slope Error*
Offset
Temp = 0 °C
Temp = 0 °C
Offset Error*
mV
*Note: Represents one standard deviation from the mean.
Table 7.12. Voltage Reference Electrical Characteristics
V
= 1.8 to 3.6 V; –40 to +85 °C unless otherwise specified.
DD
Parameter
Conditions
Min
Typ
Max
Units
Internal High Speed Reference (REFSL[1:0] = 11)
Output Voltage
Turn-on Time
Supply Current
25 °C ambient
1.55
—
1.65
—
1.75
V
1.7
—
µs
µA
—
180
External Reference (REF0E = 0)
Input Voltage Range
Input Current
0
—
7
V
DD
Sample Rate = 500 ksps; VREF = 3.0 V
—
—
µA
44
Rev. 1.0
C8051F80x-83x
Table 7.13. Comparator Electrical Characteristics
VDD = 3.0 V, –40 to +85 °C unless otherwise noted.
Parameter
Conditions
Min
Typ
Max
Units
Response Time:
Mode 0, Vcm = 1.5 V
CP0+ – CP0– = 100 mV
CP0+ – CP0– = –100 mV
CP0+ – CP0– = 100 mV
CP0+ – CP0– = –100 mV
CP0+ – CP0– = 100 mV
CP0+ – CP0– = –100 mV
CP0+ – CP0– = 100 mV
CP0+ – CP0– = –100 mV
—
—
—
—
—
—
—
—
—
—
2
220
225
340
380
510
945
1500
5000
1
—
—
—
—
—
—
—
—
4
ns
ns
*
Response Time:
ns
*
Mode 1, Vcm = 1.5 V
ns
Response Time:
ns
*
Mode 2, Vcm = 1.5 V
ns
Response Time:
ns
*
Mode 3, Vcm = 1.5 V
ns
Common-Mode Rejection Ratio
Positive Hysteresis 1
Positive Hysteresis 2
Positive Hysteresis 3
Positive Hysteresis 4
Negative Hysteresis 1
Negative Hysteresis 2
Negative Hysteresis 3
Negative Hysteresis 4
mV/V
mV
mV
mV
mV
mV
mV
mV
mV
V
Mode 2, CP0HYP1–0 = 00b
Mode 2, CP0HYP1–0 = 01b
Mode 2, CP0HYP1–0 = 10b
Mode 2, CP0HYP1–0 = 11b
Mode 2, CP0HYN1–0 = 00b
Mode 2, CP0HYN1–0 = 01b
Mode 2, CP0HYN1–0 = 10b
Mode 2, CP0HYN1–0 = 11b
0
1
5
10
20
30
1
7
10
10
—
2
20
0
5
10
20
30
7
10
10
–0.25
20
Inverting or Non-Inverting Input
Voltage Range
—
V
+ 0.25
DD
Input Offset Voltage
–7.5
—
7.5
mV
Power Specifications
Power Supply Rejection
Powerup Time
—
—
—
—
—
—
0.1
10
20
8
—
—
—
—
—
—
mV/V
µs
Supply Current at DC
Mode 0
Mode 1
Mode 2
Mode 3
µA
µA
3
µA
0.5
µA
Note: Vcm is the common-mode voltage on CP0+ and CP0–.
Rev. 1.0
45
C8051F80x-83x
8. 10-Bit ADC (ADC0)
ADC0 on the C8051F800/1/2/3/4/5, C8051F812/3/4/5/6/7, C8051F824/5/6, and C8051F830/1/2 is a
500 ksps, 10-bit successive-approximation-register (SAR) ADC with integrated track-and-hold, a gain
stage programmable to 1x or 0.5x, and a programmable window detector. The ADC is fully configurable
under software control via Special Function Registers. The ADC may be configured to measure various dif-
ferent signals using the analog multiplexer described in Section “8.5. ADC0 Analog Multiplexer” on
page 56. The voltage reference for the ADC is selected as described in Section “9. Temperature Sensor”
on page 58. The ADC0 subsystem is enabled only when the AD0EN bit in the ADC0 Control register
(ADC0CN) is set to logic 1. The ADC0 subsystem is in low power shutdown when this bit is logic 0.
ADC0CN
VDD
000
001
010
011
100
AD0BUSY (W)
Timer 0 Overflow
Timer 2 Overflow
Timer 1 Overflow
CNVSTR Input
Start
Conversion
10-Bit
SAR
AIN
X1 or
X0.5
From
AMUX0
ADC
AMP0GN0
AD0WINT
Window
Compare
Logic
32
ADC0LTH ADC0LTL
ADC0GTH ADC0GTL
ADC0CF
Figure 8.1. ADC0 Functional Block Diagram
46
Rev. 1.0
C8051F80x-83x
8.1. Output Code Formatting
The ADC measures the input voltage with reference to GND. The registers ADC0H and ADC0L contain the
high and low bytes of the output conversion code from the ADC at the completion of each conversion. Data
can be right-justified or left-justified, depending on the setting of the AD0LJST bit. Conversion codes are
represented as 10-bit unsigned integers. Inputs are measured from 0 to VREF x 1023/1024. Example
codes are shown below for both right-justified and left-justified data. Unused bits in the ADC0H and ADC0L
registers are set to 0.
Input Voltage
Right-Justified ADC0H:ADC0L
(AD0LJST = 0)
Left-Justified ADC0H:ADC0L
(AD0LJST = 1)
VREF x 1023/1024
VREF x 512/1024
VREF x 256/1024
0
0x03FF
0x0200
0x0100
0x0000
0xFFC0
0x8000
0x4000
0x0000
8.2. 8-Bit Mode
Setting the ADC08BE bit in register ADC0CF to 1 will put the ADC in 8-bit mode. In 8-bit mode, only the 8
MSBs of data are converted, and the ADC0H register holds the results. The AD0LJST bit is ignored for 8-
bit mode. 8-bit conversions take two fewer SAR clock cycles than 10-bit conversions, so the conversion is
completed faster, and a 500 ksps sampling rate can be achieved with a slower SAR clock.
8.3. Modes of Operation
ADC0 has a maximum conversion speed of 500 ksps. The ADC0 conversion clock is a divided version of
the system clock, determined by the AD0SC bits in the ADC0CF register.
8.3.1. Starting a Conversion
A conversion can be initiated in one of six ways, depending on the programmed states of the ADC0 Start of
Conversion Mode bits (AD0CM2–0) in register ADC0CN. Conversions may be initiated by one of the fol-
lowing:
1. Writing a 1 to the AD0BUSY bit of register ADC0CN
2. A Timer 0 overflow (i.e., timed continuous conversions)
3. A Timer 2 overflow
4. A Timer 1 overflow
5. A rising edge on the CNVSTR input signal
Writing a 1 to AD0BUSY provides software control of ADC0 whereby conversions are performed "on-
demand". During conversion, the AD0BUSY bit is set to logic 1 and reset to logic 0 when the conversion is
complete. The falling edge of AD0BUSY triggers an interrupt (when enabled) and sets the ADC0 interrupt
flag (AD0INT). When polling for ADC conversion completions, the ADC0 interrupt flag (AD0INT) should be
used. Converted data is available in the ADC0 data registers, ADC0H:ADC0L, when bit AD0INT is logic 1.
When Timer 2 overflows are used as the conversion source, Low Byte overflows are used if Timer 2/3 is in
8-bit mode; High byte overflows are used if Timer 2 is in 16-bit mode. See Section “28. Timers” on
page 209 for timer configuration.
Important Note About Using CNVSTR: The CNVSTR input pin also functions as a Port I/O pin. When the
CNVSTR input is used as the ADC0 conversion source, the associated pin should be skipped by the Digi-
tal Crossbar. See Section “23. Port Input/Output” on page 138 for details on Port I/O configuration.
Rev. 1.0
47
C8051F80x-83x
8.3.2. Tracking Modes
The AD0TM bit in register ADC0CN enables "delayed conversions", and will delay the actual conversion
start by three SAR clock cycles, during which time the ADC will continue to track the input. If AD0TM is left
at logic 0, a conversion will begin immediately, without the extra tracking time. For internal start-of-conver-
sion sources, the ADC will track anytime it is not performing a conversion. When the CNVSTR signal is
used to initiate conversions, ADC0 will track either when AD0TM is logic 1, or when AD0TM is logic 0 and
CNVSTR is held low. See Figure 8.2 for track and convert timing details. Delayed conversion mode is use-
ful when AMUX settings are frequently changed, due to the settling time requirements described in Section
“8.3.3. Settling Time Requirements” on page 49.
A. ADC Timing for External Trigger Source
CNVSTR
(AD0CM[2:0]=1xx)
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15* 16 17
SAR
Clocks
AD0TM=1
Track
Convert
Track
*Conversion Ends at rising edge of 15th clock in 8-bit Mode
1
2 3 4 5 6 7 8 9 10 11 12* 13 14
SAR Clocks
AD0TM=0 N/C
Track
Convert
N/C
*Conversion Ends at rising edge of 12th clock in 8-bit Mode
B. ADC Timing for Internal Trigger Source
Write '1' to AD0BUSY,
Timer 0, Timer 2, Timer 1 Overflow
(AD0CM[2:0]=000, 001, 010, 011)
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15* 16 17
SAR
Clocks
Track
Convert
Track
AD0TM=1
*Conversion Ends at rising edge of 15th clock in 8-bit Mode
1
2 3 4 5 6 7 8 9 10 11 12* 13 14
SAR
Clocks
Track or
Convert
AD0TM=0
Convert
Track
*Conversion Ends at rising edge of 12th clock in 8-bit Mode
Figure 8.2. 10-Bit ADC Track and Conversion Example Timing
48
Rev. 1.0
C8051F80x-83x
8.3.3. Settling Time Requirements
A minimum tracking time is required before each conversion to ensure that an accurate conversion is per-
formed. This tracking time is determined by any series impedance, including the AMUX0 resistance, the
the ADC0 sampling capacitance, and the accuracy required for the conversion. In delayed tracking mode,
three SAR clocks are used for tracking at the start of every conversion. For many applications, these three
SAR clocks will meet the minimum tracking time requirements.
Figure 8.3 shows the equivalent ADC0 input circuit. The required ADC0 settling time for a given settling
accuracy (SA) may be approximated by Equation 8.1. See Table 7.9 for ADC0 minimum settling time
requirements as well as the mux impedance and sampling capacitor values.
2n
SA
------
t = ln
RTOTALCSAMPLE
Equation 8.1. ADC0 Settling Time Requirements
Where:
SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB)
t is the required settling time in seconds
R
is the sum of the AMUX0 resistance and any external source resistance.
TOTAL
n is the ADC resolution in bits (10).
MUX Select
Input Pin
RMUX
CSAMPLE
RCInput= RMUX * CSAMPLE
Note: See electrical specification tables for RMUX and CSAMPLE parameters.
Figure 8.3. ADC0 Equivalent Input Circuits
Rev. 1.0
49
C8051F80x-83x
SFR Definition 8.1. ADC0CF: ADC0 Configuration
Bit
7
6
5
4
3
2
1
0
AD0SC[4:0]
AD0LJST AD08BE AMP0GN0
Name
Type
Reset
R/W
1
R/W
0
R/W
0
R/W
1
1
1
1
1
SFR Address = 0xBC
Bit Name
7:3 AD0SC[4:0]
Function
ADC0 SAR Conversion Clock Period Bits.
SAR Conversion clock is derived from system clock by the following equation, where
AD0SC refers to the 5-bit value held in bits AD0SC4–0. SAR Conversion clock
requirements are given in the ADC specification table.
SYSCLK
AD0SC = ---------------------- – 1
CLKSAR
2
1
0
AD0LJST
AD08BE
ADC0 Left Justify Select.
0: Data in ADC0H:ADC0L registers are right-justified.
1: Data in ADC0H:ADC0L registers are left-justified.
Note: The AD0LJST bit is only valid for 10-bit mode (AD08BE = 0).
8-Bit Mode Enable.
0: ADC operates in 10-bit mode (normal).
1: ADC operates in 8-bit mode.
Note: When AD08BE is set to 1, the AD0LJST bit is ignored.
AMP0GN0
ADC Gain Control Bit.
0: Gain = 0.5
1: Gain = 1
50
Rev. 1.0
C8051F80x-83x
SFR Definition 8.2. ADC0H: ADC0 Data Word MSB
Bit
7
6
5
4
3
2
1
0
ADC0H[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xBE
Bit Name
7:0 ADC0H[7:0]
Function
ADC0 Data Word High-Order Bits.
For AD0LJST = 0: Bits 7–2 will read 000000b. Bits 1–0 are the upper 2 bits of the 10-
bit ADC0 Data Word.
For AD0LJST = 1: Bits 7–0 are the most-significant bits of the 10-bit ADC0 Data
Word.
Note: In 8-bit mode AD0LJST is ignored, and ADC0H holds the 8-bit data word.
SFR Definition 8.3. ADC0L: ADC0 Data Word LSB
Bit
7
6
5
4
3
2
1
0
ADC0L[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xBD
Bit Name
7:0 ADC0L[7:0]
Function
ADC0 Data Word Low-Order Bits.
For AD0LJST = 0: Bits 7–0 are the lower 8 bits of the 10-bit Data Word.
For AD0LJST = 1: Bits 7–6 are the lower 2 bits of the 10-bit Data Word. Bits 5–0 will
always read 0.
Note: In 8-bit mode AD0LJST is ignored, and ADC0L will read back 00000000b.
Rev. 1.0
51
C8051F80x-83x
SFR Definition 8.4. ADC0CN: ADC0 Control
Bit
7
6
5
4
3
2
1
0
AD0EN
AD0TM
AD0INT AD0BUSY AD0WINT
AD0CM[2:0]
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
0
SFR Address = 0xE8; Bit-Addressable
Bit
Name
Function
7
AD0EN
ADC0 Enable Bit.
0: ADC0 Disabled. ADC0 is in low-power shutdown.
1: ADC0 Enabled. ADC0 is active and ready for data conversions.
6
AD0TM
ADC0 Track Mode Bit.
0: Normal Track Mode: When ADC0 is enabled, tracking is continuous unless a con-
version is in progress. Conversion begins immediately on start-of-conversion event,
as defined by AD0CM[2:0].
1: Delayed Track Mode: When ADC0 is enabled, input is tracked when a conversion
is not in progress. A start-of-conversion signal initiates three SAR clocks of additional
tracking, and then begins the conversion.
5
4
AD0INT
ADC0 Conversion Complete Interrupt Flag.
0: ADC0 has not completed a data conversion since AD0INT was last cleared.
1: ADC0 has completed a data conversion.
AD0BUSY ADC0 Busy Bit.
Read:
0: ADC0 conversion is not 0: No Effect.
in progress.
1: ADC0 conversion is in sion if AD0CM[2:0] =
progress. 000b
AD0WINT ADC0 Window Compare Interrupt Flag.
Write:
1: Initiates ADC0 Conver-
3
0: ADC0 Window Comparison Data match has not occurred since this flag was last
cleared.
1: ADC0 Window Comparison Data match has occurred.
2:0 AD0CM[2:0] ADC0 Start of Conversion Mode Select.
000: ADC0 start-of-conversion source is write of 1 to AD0BUSY.
001: ADC0 start-of-conversion source is overflow of Timer 0.
010: ADC0 start-of-conversion source is overflow of Timer 2.
011: ADC0 start-of-conversion source is overflow of Timer 1.
100: ADC0 start-of-conversion source is rising edge of external CNVSTR.
101–111: Reserved.
52
Rev. 1.0
C8051F80x-83x
8.4. Programmable Window Detector
The ADC Programmable Window Detector continuously compares the ADC0 output registers to user-pro-
grammed limits, and notifies the system when a desired condition is detected. This is especially effective in
an interrupt-driven system, saving code space and CPU bandwidth while delivering faster system
response times. The window detector interrupt flag (AD0WINT in register ADC0CN) can also be used in
polled mode. The ADC0 Greater-Than (ADC0GTH, ADC0GTL) and Less-Than (ADC0LTH, ADC0LTL)
registers hold the comparison values. The window detector flag can be programmed to indicate when mea-
sured data is inside or outside of the user-programmed limits, depending on the contents of the ADC0
Less-Than and ADC0 Greater-Than registers.
SFR Definition 8.5. ADC0GTH: ADC0 Greater-Than Data High Byte
Bit
7
6
5
4
3
2
1
0
ADC0GTH[7:0]
R/W
Name
Type
Reset
1
1
1
1
1
1
1
1
SFR Address = 0xC4
Bit Name
Function
7:0 ADC0GTH[7:0] ADC0 Greater-Than Data Word High-Order Bits.
SFR Definition 8.6. ADC0GTL: ADC0 Greater-Than Data Low Byte
Bit
7
6
5
4
3
2
1
0
ADC0GTL[7:0]
R/W
Name
Type
Reset
1
1
1
1
1
1
1
1
SFR Address = 0xC3
Bit Name
Function
7:0 ADC0GTL[7:0] ADC0 Greater-Than Data Word Low-Order Bits.
Rev. 1.0
53
C8051F80x-83x
SFR Definition 8.7. ADC0LTH: ADC0 Less-Than Data High Byte
Bit
7
6
5
4
3
2
1
0
ADC0LTH[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xC6
Bit Name
Function
7:0 ADC0LTH[7:0] ADC0 Less-Than Data Word High-Order Bits.
SFR Definition 8.8. ADC0LTL: ADC0 Less-Than Data Low Byte
Bit
7
6
5
4
3
2
1
0
ADC0LTL[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xC5
Bit Name
Function
7:0 ADC0LTL[7:0] ADC0 Less-Than Data Word Low-Order Bits.
54
Rev. 1.0
C8051F80x-83x
8.4.1. Window Detector Example
Figure 8.4 shows two example
window
comparisons
for
right-justified
data,
with
ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). The input voltage can
range from 0 to VREF x (1023/1024) with respect to GND, and is represented by a 10-bit unsigned integer
value. In the left example, an AD0WINT interrupt will be generated if the ADC0 conversion word
(ADC0H:ADC0L) is within the range defined by ADC0GTH:ADC0GTL and ADC0LTH:ADC0LTL
(if 0x0040 < ADC0H:ADC0L < 0x0080). In the right example, and AD0WINT interrupt will be generated if
the ADC0 conversion word is outside of the range defined by the ADC0GT and ADC0LT registers
(if ADC0H:ADC0L < 0x0040 or ADC0H:ADC0L > 0x0080). Figure 8.5 shows an example using left-justi-
fied data with the same comparison values.
ADC0H:ADC0L
0x03FF
ADC0H:ADC0L
0x03FF
Input Voltage
(AIN - GND)
Input Voltage
(AIN - GND)
VREF x (1023/
1024)
VREF x (1023/
1024)
AD0WINT
not affected
AD0WINT=1
0x0081
0x0081
VREF x (128/1024)
VREF x (64/1024)
0x0080
0x007F
ADC0LTH:ADC0LTL
VREF x (128/1024)
VREF x (64/1024)
0x0080
0x007F
ADC0GTH:ADC0GTL
AD0WINT
not affected
AD0WINT=1
0x0041
0x0040
0x0041
0x0040
ADC0GTH:ADC0GTL
ADC0LTH:ADC0LTL
0x003F
0x003F
AD0WINT=1
AD0WINT
not affected
0x0000
0x0000
0
0
Figure 8.4. ADC Window Compare Example: Right-Justified Data
ADC0H:ADC0L
0xFFC0
ADC0H:ADC0L
0xFFC0
Input Voltage
(AIN - GND)
Input Voltage
(AIN - GND)
VREF x (1023/
1024)
VREF x (1023/
1024)
AD0WINT
not affected
AD0WINT=1
0x2040
0x2040
VREF x (128/1024)
VREF x (64/1024)
0x2000
0x1FC0
ADC0LTH:ADC0LTL
VREF x (128/1024)
VREF x (64/1024)
0x2000
0x1FC0
ADC0GTH:ADC0GTL
AD0WINT
not affected
AD0WINT=1
0x1040
0x1000
0x1040
0x1000
ADC0GTH:ADC0GTL
ADC0LTH:ADC0LTL
0x0FC0
0x0FC0
AD0WINT=1
AD0WINT
not affected
0x0000
0x0000
0
0
Figure 8.5. ADC Window Compare Example: Left-Justified Data
Rev. 1.0
55
C8051F80x-83x
8.5. ADC0 Analog Multiplexer
ADC0 on the C8051F800/1/2/3/4/5, C8051F812/3/4/5/6/7, C8051F824/5/6, and C8051F830/1/2 uses an
analog input multiplexer to select the positive input to the ADC. Any of the following may be selected as the
positive input: Port 0 or Port 1 I/O pins, the on-chip temperature sensor, or the positive power supply (V ).
DD
The ADC0 input channel is selected in the ADC0MX register described in SFR Definition 8.9.
ADC0MX
P0.0
Note: P1.4-P1.7
are not available
on the 16-pin
packages.
P1.7
AMUX
ADC0
Temp
Sensor
VREG Output
VDD
GND
Figure 8.6. ADC0 Multiplexer Block Diagram
Important Note About ADC0 Input Configuration: Port pins selected as ADC0 inputs should be config-
ured as analog inputs, and should be skipped by the Digital Crossbar. To configure a Port pin for analog
input, set the corresponding bit in register PnMDIN to 0. To force the Crossbar to skip a Port pin, set the
corresponding bit in register PnSKIP to 1. See Section “23. Port Input/Output” on page 138 for more Port
I/O configuration details.
56
Rev. 1.0
C8051F80x-83x
SFR Definition 8.9. ADC0MX: AMUX0 Channel Select
Bit
7
6
5
4
3
2
1
0
AMX0P[3:0]
Name
Type
Reset
R
0
R
0
R
0
R/W
1
1
1
1
1
SFR Address = 0xBB
Bit
Name
Function
7:5
Unused
Read = 000b; Write = Don’t Care.
4:0 AMX0P[4:0] AMUX0 Positive Input Selection.
20-Pin and 24-Pin Devices 16-Pin Devices
00000:
00001:
00010:
00011:
00100:
00101:
00110:
00111:
01000
P0.0
P0.0
P0.1
P0.1
P0.2
P0.2
P0.3
P0.3
P0.4
P0.4
P0.5
P0.5
P0.6
P0.6
P0.7
P0.7
P1.0
P1.0
01001
P1.1
P1.1
01010
P1.2
P1.2
01011
P1.3
P1.3
01100
P1.4
Reserved.
Reserved.
Reserved.
Reserved.
Temp Sensor
VREG Output
VDD
01101
P1.5
01110
P1.6
01111
P1.7
10000:
10001:
10010:
10011:
10100 – 11111:
Temp Sensor
VREG Output
VDD
GND
GND
no input selected
Rev. 1.0
57
C8051F80x-83x
9. Temperature Sensor
An on-chip temperature sensor is included on the C8051F800/1/2/3/4/5, C8051F812/3/4/5/6/7,
C8051F824/5/6, and C8051F830/1/2 which can be directly accessed via the ADC multiplexer in single-
ended configuration. To use the ADC to measure the temperature sensor, the ADC mux channel should be
configured to connect to the temperature sensor. The temperature sensor transfer function is shown in
Figure 9.1. The output voltage (V
) is the positive ADC input when the ADC multiplexer is set correctly.
TEMP
The TEMPE bit in register REF0CN enables/disables the temperature sensor, as described in SFR Defini-
tion 10.1. While disabled, the temperature sensor defaults to a high impedance state and any ADC mea-
surements performed on the sensor will result in meaningless data. Refer to Table 7.11 for the slope and
offset parameters of the temperature sensor.
VTEMP = (Slope x TempC) + Offset
TempC = (VTEMP - Offset) / Slope
Slope (V / deg C)
Offset (V at 0 Celsius)
Temperature
Figure 9.1. Temperature Sensor Transfer Function
9.1. Calibration
The uncalibrated temperature sensor output is extremely linear and suitable for relative temperature mea-
surements (see Table 5.1 for linearity specifications). For absolute temperature measurements, offset
and/or gain calibration is recommended. Typically a 1-point (offset) calibration includes the following steps:
1. Control/measure the ambient temperature (this temperature must be known).
2. Power the device, and delay for a few seconds to allow for self-heating.
3. Perform an ADC conversion with the temperature sensor selected as the ADC’s input.
4. Calculate the offset characteristics, and store this value in non-volatile memory for use with subsequent
temperature sensor measurements.
Figure 5.3 shows the typical temperature sensor error assuming a 1-point calibration at 0 °C.
Parameters that affect ADC measurement, in particular the voltage reference value, will also affect temper-
ature measurement.
58
Rev. 1.0
C8051F80x-83x
5.00
4.00
3.00
2.00
1.00
0.00
5.00
4.00
3.00
2.00
1.00
0.00
-40.00
-20.00
0.00
20.00
40.00
60.00
80.00
-1.00
-2.00
-3.00
-4.00
-5.00
-1.00
-2.00
-3.00
-4.00
-5.00
Temperature (degrees C)
Figure 9.2. Temperature Sensor Error with 1-Point Calibration at 0 °C
Rev. 1.0
59
C8051F80x-83x
10. Voltage and Ground Reference Options
The voltage reference MUX is configurable to use an externally connected voltage reference, the on-chip
voltage reference, or one of two power supply voltages (see Figure 10.1). The ground reference MUX
allows the ground reference for ADC0 to be selected between the ground pin (GND) or a port pin dedi-
cated to analog ground (P0.1/AGND).
The voltage and ground reference options are configured using the REF0CN SFR described on page 62.
Electrical specifications are can be found in the Electrical Specifications Chapter.
Important Note About the V
and AGND Inputs: Port pins are used as the external V
and AGND
REF
REF
inputs. When using an external voltage reference, P0.0/VREF should be configured as an analog input and
skipped by the Digital Crossbar. When using AGND as the ground reference to ADC0, P0.1/AGND should
be configured as an analog input and skipped by the Digital Crossbar. Refer to Section “23. Port Input/Out-
put” on page 138 for complete Port I/O configuration details. The external reference voltage must be within
the range 0 V
V and the external ground reference must be at the same DC voltage potential as
REF
DD
GND.
REF0CN
To ADC, Internal
Oscillator,
Reference,
TempSensor
EN
EN
Bias Generator
Temp Sensor
IOSCEN
To Analog Mux
VDD
External
Voltage
Reference
Circuit
R1
P0.0/VREF
VDD
00
01
10
11
Internal 1.8V
Regulated Digital Supply
GND
+
Internal 1.65V
High Speed Reference
4.7F
0.1F
GND
0
1
Recommended
Bypass Capacitors
P0.1/AGND
REFGND
Figure 10.1. Voltage Reference Functional Block Diagram
60
Rev. 1.0
C8051F80x-83x
10.1. External Voltage References
To use an external voltage reference, REFSL[1:0] should be set to 00. Bypass capacitors should be added
as recommended by the manufacturer of the external voltage reference.
10.2. Internal Voltage Reference Options
A 1.65 V high-speed reference is included on-chip. The high speed internal reference is selected by setting
REFSL[1:0] to 11. When selected, the high speed internal reference will be automatically enabled on an
as-needed basis by ADC0.
For applications with a non-varying power supply voltage, using the power supply as the voltage reference
can provide ADC0 with added dynamic range at the cost of reduced power supply noise rejection. To use
the 1.8 to 3.6 V power supply voltage (V ) or the 1.8 V regulated digital supply voltage as the reference
DD
source, REFSL[1:0] should be set to 01 or 10, respectively.
10.3. Analog Ground Reference
To prevent ground noise generated by switching digital logic from affecting sensitive analog measure-
ments, a separate analog ground reference option is available. When enabled, the ground reference for
ADC0 is taken from the P0.1/AGND pin. Any external sensors sampled by ADC0 should be referenced to
the P0.1/AGND pin. The separate analog ground reference option is enabled by setting REFGND to 1.
Note that when using this option, P0.1/AGND must be connected to the same potential as GND.
10.4. Temperature Sensor Enable
The TEMPE bit in register REF0CN enables the temperature sensor. While disabled, the temperature sen-
sor defaults to a high impedance state and any ADC0 measurements performed on the sensor result in
meaningless data.
Rev. 1.0
61
C8051F80x-83x
SFR Definition 10.1. REF0CN: Voltage Reference Control
Bit
7
6
5
4
3
2
1
0
REFGND
REFSL
TEMPE
BIASE
Name
Type
Reset
R
0
R
0
R/W
0
R/W
1
R/W
0
R/W
0
R/W
0
R
0
SFR Address = 0xD1
Bit
7:6
5
Name
Function
Unused Read = 00b; Write = Don’t Care.
REFGND Analog Ground Reference.
Selects the ADC0 ground reference.
0: The ADC0 ground reference is the GND pin.
1: The ADC0 ground reference is the P0.1/AGND pin.
REFSL Voltage Reference Select.
4:3
Selects the ADC0 voltage reference.
00: The ADC0 voltage reference is the P0.0/VREF pin.
01: The ADC0 voltage reference is the VDD pin.
10: The ADC0 voltage reference is the internal 1.8 V digital supply voltage.
11: The ADC0 voltage reference is the internal 1.65 V high speed voltage reference.
TEMPE Temperature Sensor Enable.
2
Enables/Disables the internal temperature sensor.
0: Temperature Sensor Disabled.
1: Temperature Sensor Enabled.
1
0
BIASE
Internal Analog Bias Generator Enable Bit.
0: Internal Bias Generator off.
1: Internal Bias Generator on.
Unused Read = 0b; Write = Don’t Care.
62
Rev. 1.0
C8051F80x-83x
11. Voltage Regulator (REG0)
C8051F80x-83x devices include an internal voltage regulator (REG0) to regulate the internal core supply
to 1.8 V from a V supply of 1.8 to 3.6 V. A power-saving mode is built into the regulator to help reduce
DD
current consumption in low-power applications. This mode is accessed through the REG0CN register
(SFR Definition 11.1). Electrical characteristics for the on-chip regulator are specified in Table 7.5 on
page 41
Under default conditions, when the device enters STOP mode the internal regulator will remain on. This
allows any enabled reset source to generate a reset for the device and bring the device out of STOP mode.
For additional power savings, the STOPCF bit can be used to shut down the regulator and the internal
power network of the device when the part enters STOP mode. When STOPCF is set to 1, the RST pin or
a full power cycle of the device are the only methods of generating a reset.
Rev. 1.0
63
C8051F80x-83x
SFR Definition 11.1. REG0CN: Voltage Regulator Control
Bit
7
6
5
4
3
2
1
0
STOPCF
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Address = 0xC9
Bit
Name
Function
7
STOPCF Stop Mode Configuration.
This bit configures the regulator’s behavior when the device enters STOP mode.
0: Regulator is still active in STOP mode. Any enabled reset source will reset the
device.
1: Regulator is shut down in STOP mode. Only the RST pin or power cycle can reset
the device.
6:0 Reserved Must write to 0000000b.
64
Rev. 1.0
C8051F80x-83x
12. Comparator0
C8051F80x-83x devices include an on-chip programmable voltage comparator, Comparator0, shown in
Figure 12.1.
The Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two
outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0), or an asyn-
chronous “raw” output (CP0A). The asynchronous CP0A signal is available even when the system clock is
not active. This allows the Comparator to operate and generate an output with the device in STOP mode.
When assigned to a Port pin, the Comparator output may be configured as open drain or push-pull (see
Section “23.4. Port I/O Initialization” on page 147). Comparator0 may also be used as a reset source (see
Section “21.5. Comparator0 Reset” on page 127).
The Comparator0 inputs are selected by the comparator input multiplexer, as detailed in Section
“12.1. Comparator Multiplexer” on page 69.
CPT0CN
VDD
CP0 +
+
CP0
Comparator
Input Mux
SET
CLR
SET
CLR
D
Q
Q
D
Q
Q
CP0 -
-
Crossbar
(SYNCHRONIZER)
CP0A
GND
Reset
Decision
Tree
CPT0MD
0
1
CP0
Interrupt
CP0EN
EA
CP0RIF
CP0FIF
0
0
1
1
0
1
Figure 12.1. Comparator0 Functional Block Diagram
The Comparator output can be polled in software, used as an interrupt source, and/or routed to a Port pin.
When routed to a Port pin, the Comparator output is available asynchronous or synchronous to the system
clock; the asynchronous output is available even in STOP mode (with no system clock active). When dis-
abled, the Comparator output (if assigned to a Port I/O pin via the Crossbar) defaults to the logic low state,
and the power supply to the comparator is turned off. See Section “23.3. Priority Crossbar Decoder” on
page 143 for details on configuring Comparator outputs via the digital Crossbar. Comparator inputs can be
externally driven from –0.25 V to (V ) + 0.25 V without damage or upset. The complete Comparator elec-
DD
trical specifications are given in Section “7. Electrical Characteristics” on page 39.
Rev. 1.0
65
C8051F80x-83x
The Comparator response time may be configured in software via the CPT0MD register (see SFR Defini-
tion 12.2). Selecting a longer response time reduces the Comparator supply current.
CP0+
VIN+
VIN-
+
CP0
_
OUT
CP0-
CIRCUIT CONFIGURATION
Positive Hysteresis Voltage
(Programmed with CP0HYP Bits)
VIN-
Negative Hysteresis Voltage
INPUTS
(Programmed by CP0HYN Bits)
VIN+
VOH
OUTPUT
VOL
Negative Hysteresis
Disabled
Maximum
Negative Hysteresis
Positive Hysteresis
Disabled
Maximum
Positive Hysteresis
Figure 12.2. Comparator Hysteresis Plot
The Comparator hysteresis is software-programmable via its Comparator Control register CPT0CN. The
user can program both the amount of hysteresis voltage (referred to the input voltage) and the positive and
negative-going symmetry of this hysteresis around the threshold voltage.
The Comparator hysteresis is programmed using bits 3:0 in the Comparator Control Register CPT0CN
(shown in SFR Definition 12.1). The amount of negative hysteresis voltage is determined by the settings of
the CP0HYN bits. As shown in Figure 12.2, settings of 20, 10 or 5 mV of negative hysteresis can be pro-
grammed, or negative hysteresis can be disabled. In a similar way, the amount of positive hysteresis is
determined by the setting the CP0HYP bits.
Comparator interrupts can be generated on both rising-edge and falling-edge output transitions. (For Inter-
rupt enable and priority control, see Section “18.1. MCU Interrupt Sources and Vectors” on page 103). The
CP0FIF flag is set to logic 1 upon a Comparator falling-edge occurrence, and the CP0RIF flag is set to
logic 1 upon the Comparator rising-edge occurrence. Once set, these bits remain set until cleared by soft-
ware. The Comparator rising-edge interrupt mask is enabled by setting CP0RIE to a logic 1. The
Comparator0 falling-edge interrupt mask is enabled by setting CP0FIE to a logic 1.
The output state of the Comparator can be obtained at any time by reading the CP0OUT bit. The Compar-
ator is enabled by setting the CP0EN bit to logic 1, and is disabled by clearing this bit to logic 0.
Note that false rising edges and falling edges can be detected when the comparator is first powered on or
if changes are made to the hysteresis or response time control bits. Therefore, it is recommended that the
rising-edge and falling-edge flags be explicitly cleared to logic 0 a short time after the comparator is
enabled or its mode bits have been changed.
66
Rev. 1.0
C8051F80x-83x
SFR Definition 12.1. CPT0CN: Comparator0 Control
Bit
7
6
5
4
3
2
1
0
CP0EN
CP0OUT
CP0RIF
CP0FIF
CP0HYP[1:0]
R/W
CP0HYN[1:0]
R/W
Name
Type
Reset
R/W
0
R
0
R/W
0
R/W
0
0
0
0
0
SFR Address = 0x9B
Bit
Name
Function
7
CP0EN
Comparator0 Enable Bit.
0: Comparator0 Disabled.
1: Comparator0 Enabled.
6
5
4
CP0OUT
CP0RIF
CP0FIF
Comparator0 Output State Flag.
0: Voltage on CP0+ < CP0–.
1: Voltage on CP0+ > CP0–.
Comparator0 Rising-Edge Flag. Must be cleared by software.
0: No Comparator0 Rising Edge has occurred since this flag was last cleared.
1: Comparator0 Rising Edge has occurred.
Comparator0 Falling-Edge Flag. Must be cleared by software.
0: No Comparator0 Falling-Edge has occurred since this flag was last cleared.
1: Comparator0 Falling-Edge has occurred.
3:2 CP0HYP[1:0] Comparator0 Positive Hysteresis Control Bits.
00: Positive Hysteresis Disabled.
01: Positive Hysteresis = 5 mV.
10: Positive Hysteresis = 10 mV.
11: Positive Hysteresis = 20 mV.
1:0 CP0HYN[1:0] Comparator0 Negative Hysteresis Control Bits.
00: Negative Hysteresis Disabled.
01: Negative Hysteresis = 5 mV.
10: Negative Hysteresis = 10 mV.
11: Negative Hysteresis = 20 mV.
Rev. 1.0
67
C8051F80x-83x
SFR Definition 12.2. CPT0MD: Comparator0 Mode Selection
Bit
7
6
5
4
3
2
1
0
CP0RIE
CP0FIE
CP0MD[1:0]
R/W
Name
Type
Reset
R
0
R
0
R/W
0
R/W
0
R
0
R
0
1
0
SFR Address = 0x9D
Bit
7:6
5
Name
Unused
CP0RIE
Function
Read = 00b, Write = Don’t Care.
Comparator0 Rising-Edge Interrupt Enable.
0: Comparator0 Rising-edge interrupt disabled.
1: Comparator0 Rising-edge interrupt enabled.
4
CP0FIE
Comparator0 Falling-Edge Interrupt Enable.
0: Comparator0 Falling-edge interrupt disabled.
1: Comparator0 Falling-edge interrupt enabled.
3:2
Unused
Read = 00b, Write = don’t care.
1:0 CP0MD[1:0] Comparator0 Mode Select.
These bits affect the response time and power consumption for Comparator0.
00: Mode 0 (Fastest Response Time, Highest Power Consumption)
01: Mode 1
10: Mode 2
11: Mode 3 (Slowest Response Time, Lowest Power Consumption)
68
Rev. 1.0
C8051F80x-83x
12.1. Comparator Multiplexer
C8051F80x-83x devices include an analog input multiplexer to connect Port I/O pins to the comparator
inputs. The Comparator0 inputs are selected in the CPT0MX register (SFR Definition 12.3). The CMX0P3–
CMX0P0 bits select the Comparator0 positive input; the CMX0N3–CMX0N0 bits select the Comparator0
negative input. Important Note About Comparator Inputs: The Port pins selected as comparator inputs
should be configured as analog inputs in their associated Port configuration register, and configured to be
skipped by the Crossbar (for details on Port configuration, see Section “23.6. Special Function Registers
for Accessing and Configuring Port I/O” on page 152).
CPT0MX
P0.0
P0.2
P0.4
VDD
P0.6
P1.0
P1.2
P1.4
P1.6
CP0 +
CP0 -
+
-
VREG Output
GND
P0.1
P0.3
P0.5
P0.7
P1.1
P1.3
P1.5
P1.7
Note: P1.4-P1.7
are not available
on the 16-pin
packages.
VREG Output
Figure 12.3. Comparator Input Multiplexer Block Diagram
Rev. 1.0
69
C8051F80x-83x
SFR Definition 12.3. CPT0MX: Comparator0 MUX Selection
Bit
7
6
5
4
3
2
1
0
CMX0N[3:0]
R/W
CMX0P[3:0]
R/W
Name
Type
Reset
1
1
1
1
1
1
1
1
SFR Address = 0x9F
Bit Name
7:4 CMX0N[3:0]
Function
Comparator0 Negative Input MUX Selection.
20-Pin and 24-Pin Devices
16-Pin Devices
P0.1
0000
0001
0010
P0.1
P0.3
P0.3
P0.5
P0.5
0011
P0.7
P0.7
0100
0101
0110
0111
1000
P1.1
P1.1
P1.3
P1.3
P1.5
Reserved.
Reserved.
VREG Output.
No input selected.
P1.7
VREG Output.
1001–1111 No input selected.
3:0 CMX0P[3:0]
Comparator0 Positive Input MUX Selection.
20-Pin and 24-Pin Devices
16-Pin Devices
P0.0
0000
0001
0010
0011
0100
0101
0110
0111
1000
P0.0
P0.2
P0.2
P0.4
P0.4
P0.6
P0.6
P1.0
P1.0
P1.2
P1.2
P1.4
Reserved.
Reserved.
VREG Output.
No input selected.
P1.6
VREG Output.
1001–1111 No input selected.
70
Rev. 1.0
C8051F80x-83x
13. Capacitive Sense (CS0)
The Capacitive Sense subsystem included on the C8051F800/1/3/4/6/7/9, C8051F810/2/3/5/6/8/9,
C8051F821/2/4/5/7/8, C8051F830/1/3/4 uses a capacitance-to-digital circuit to determine the capacitance
on a port pin. The module can take measurements from different port pins using the module’s analog mul-
tiplexer. The multiplexer supports up to 16 channels. See SFR Definition 13.9. “CS0MX: Capacitive Sense
Mux Channel Select” on page 81 for channel availability for specific part numbers. The module is enabled
only when the CS0EN bit (CS0CN) is set to 1. Otherwise the module is in a low-power shutdown state. The
module can be configured to take measurements on one port pin or a group of port pins, using auto-scan.
An accumulator can be configured to accumulate multiple conversions on an input channel. Interrupts can
be generated when CS0 completes a conversion or when the measured value crosses a threshold defined
in CS0THH:L.
CS0CF
CS0CN
CS0SS
CS0SE
000
001
010
011
100
101
110
111
CS0BUSY (W)
Auto-Scan
Logic
Timer 0 Overflow
Timer 2 Overflow
Timer 1 Overflow
Reserved
Start
Conversion
Reserved
CS0MX
Initiated continuously
Initiated continuously
when auto-scan
enabled
16-Bit
Capacitance to
22-Bit Accumulator
CS0DH:L
. . .
Digital Converter
Greater Than
Compare Logic
CS0CMPF
CS0THH:L
Figure 13.1. CS0 Block Diagram
Rev. 1.0
71
C8051F80x-83x
13.1. Configuring Port Pins as Capacitive Sense Inputs
In order for a port pin to be measured by CS0, that port pin must be configured as an analog input (see “23.
Port Input/Output” ). Configuring the input multiplexer to a port pin not configured as an analog input will
cause the capacitive sense comparator to output incorrect measurements.
13.2. Capacitive Sense Start-Of-Conversion Sources
A capacitive sense conversion can be initiated in one of seven ways, depending on the programmed state
of the CS0 start of conversion bits (CS0CF6:4). Conversions may be initiated by one of the following:
1. Writing a 1 to the CS0BUSY bit of register CS0CN
2. Timer 0 overflow
3. Timer 2 overflow
4. Timer 1 overflow
5. Convert continuously
6. Convert continuously with auto-scan enabled
Conversions can be configured to be initiated continuously through one of two methods. CS0 can be con-
figured to convert at a single channel continuously or it can be configured to convert continuously with
auto-scan enabled. When configured to convert continuously, conversions will begin after the CS0BUSY
bit in CS0CF has been set.
An interrupt will be generated if CS0 conversion complete interrupts are enabled by setting the ECSCPT
bit (EIE2.0).
Note: CS0 conversion complete interrupt behavior depends on the settings of the CS0 accumulator. If CS0 is
configured to accumulate multiple conversions on an input channel, a CS0 conversion complete interrupt will
be generated only after the last conversion completes.
13.3. Automatic Scanning
CS0 can be configured to automatically scan a sequence of contiguous CS0 input channels by configuring
and enabling auto-scan. Using auto-scan with the CS0 comparator interrupt enabled allows a system to
detect a change in measured capacitance without requiring any additional dedicated MCU resources.
Auto-scan is enabled by setting the CS0 start-of-conversion bits (CS0CF6:4) to 111b. After enabling auto-
scan, the starting and ending channels should be set to appropriate values in CS0SS and CS0SE, respec-
tively. Writing to CS0SS when auto-scan is enabled will cause the value written to CS0SS to be copied into
CS0MX. After being enabled, writing a 1 to CS0BUSY will start auto-scan conversions. When auto-scan
completes the number of conversions defined in the CS0 accumulator bits (CS0CF1:0) (see “13.5. CS0
Conversion Accumulator” ), auto-scan configures CS0MX to the next highest port pin configured as an
analog input and begins a conversion on that channel. This scan sequence continues until CS0MX
reaches the ending input channel value defined in CS0SE. After one or more conversions have been taken
at this channel, auto-scan configures CS0MX back to the starting input channel. For an example system
configured to use auto-scan, please see Figure “13.2 Auto-Scan Example” on page 73.
Note: Auto-scan attempts one conversion on a CS0MX channel regardless of whether that channel’s port pin has
been configured as an analog input.
If auto-scan is enabled when the device enters suspend mode, auto-scan will remain enabled and running.
This feature allows the device to wake from suspend through CS0 greater-than comparator event on any
configured capacitive sense input included in the auto-scan sequence of inputs.
72
Rev. 1.0
C8051F80x-83x
SFR Configuration:
Enables Capsense0
CS0CN = 0x80
CS0CF = 0x70
Enables Auto-scan
as start-of-
A
D
A
A
D
D
D
D
A
A
D
A
A
A
A
A
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
0
1
conversion source
Sets P0.2 as Auto-
scan starting channel
CS0SS = 0x02
CS0SE = 0x0D
2
3
Sets P1.5 as Auto-
scan ending channel
Scans on channels
not configured as
analog inputs result
in indeterminate
values that cannot
trigger a CS0
4
Configures P0.3,
P0.2, P0.0 as analog
inputs
5
P0MDIN = 0xF2
P1MDIN = 0x04
6
7
Greater Than
Interrupt event
Configures P1.0-P1.1
and P1.3-P1.7 as
analog inputs
8
9
10
11
12
13
14
15
. . .
Figure 13.2. Auto-Scan Example
13.4. CS0 Comparator
The CS0 comparator compares the latest capacitive sense conversion result with the value stored in
CS0THH:CS0THL. If the result is less than or equal to the stored value, the CS0CMPF bit(CS0CN:0) is set
to 0. If the result is greater than the stored value, CS0CMPF is set to 1.
If the CS0 conversion accumulator is configured to accumulate multiple conversions, a comparison will not
be made until the last conversion has been accumulated.
An interrupt will be generated if CS0 greater-than comparator interrupts are enabled by setting the ECS-
GRT bit (EIE2.1) when the comparator sets CS0CMPF to 1.
If auto-scan is running when the comparator sets the CS0CMPF bit, no further auto-scan initiated conver-
sions will start until firmware sets CS0BUSY to 1.
A CS0 greater-than comparator event can wake a device from suspend mode. This feature is useful in sys-
tems configured to continuously sample one or more capacitive sense channels. The device will remain in
the low-power suspend state until the captured value of one of the scanned channels causes a CS0
greater-than comparator event to occur. It is not necessary to have CS0 comparator interrupts enabled in
order to wake a device from suspend with a greater-than event.
Note: On waking from suspend mode due to a CS0 greater-than comparator event, the CS0CN register
should be accessed only after at least two system clock cycles have elapsed.
For a summary of behavior with different CS0 comparator, auto-scan, and auto accumulator settings,
please see Table 13.1.
Rev. 1.0
73
C8051F80x-83x
13.5. CS0 Conversion Accumulator
CS0 can be configured to accumulate multiple conversions on an input channel. The number of samples to
be accumulated is configured using the CS0ACU2:0 bits (CS0CF2:0). The accumulator can accumulate 1,
4, 8, 16, 32, or 64 samples. After the defined number of samples have been accumulated, the result is con-
verted to a 16-bit value by dividing the 22-bit accumulator by either 1, 4, 8, 16, 32, or 64 (depending on the
CS0ACU[2:0] setting) and copied to the CS0DH:CS0DL SFRs.
Table 13.1. Operation with Auto-scan and Accumulate
CS0 Conversion CS0 Greater Than Interrupt
CS0MX Behavior
Complete
Interrupt
Behavior
Behavior
N
N
Y
N
Y
N
CS0INT Interrupt Interrupt serviced after 1 con-
serviced after 1 version completes if value in
conversion com- CS0DH:CS0DL is greater than
pletes CS0THH:CS0THL
CS0MX unchanged.
CS0MX unchanged.
CS0INT Interrupt Interrupt serviced after M con-
serviced after M versions complete if value in
conversions com- 16-bit accumulator is greater
plete
than CS0THH:CS0THL
CS0INT Interrupt
serviced after 1
Interrupt serviced after con- If greater-than comparator detects conver-
version completes if value in
sion value is greater than
conversion com- CS0DH:CS0DL is greater than
CS0THH:CS0THL, CMUX0 is left
pletes
CS0THH:CS0THL;
Auto-Scan stopped
unchanged; otherwise, CMUX0 updates to
the next channel (CS0MX + 1) and wraps
back to CS0SS after passing CS0SE
Y
Y
CS0INT Interrupt Interrupt serviced after M con- If greater-than comparator detects conver-
serviced after M
conversions com- 16-bit accumulator is greater
plete
versions complete if value in
sion value is greater than
CS0THH:CS0THL, CS0MX is left
than CS0THH:CS0THL; Auto- unchanged; otherwise, CS0MX updates to
Scan stopped
the next channel (CS0MX + 1) and wraps
back to CS0SS after passing CS0SE
M = Accumulator setting (1x, 4x, 8x, 16x, 32x, 64x)
74
Rev. 1.0
C8051F80x-83x
SFR Definition 13.1. CS0CN: Capacitive Sense Control
Bit
7
6
5
4
3
2
1
0
CS0EN
CS0INT CS0BUSY CS0CMPEN
CS0CMPF
Name
Type
Reset
R/W
0
R
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R
0
SFR Address = 0xB0; Bit-Addressable
Bit
Name
Description
7
CS0EN
CS0 Enable.
0: CS0 disabled and in low-power mode.
1: CS0 enabled and ready to convert.
Read = 0b; Write = Don’t care
6
5
Unused
CS0INT
CS0 Interrupt Flag.
0: CS0 has not completed a data conversion since the last time CS0INT was
cleared.
1: CS0 has completed a data conversion.
This bit is not automatically cleared by hardware.
4
3
CS0BUSY
CS0 Busy.
Read:
0: CS0 conversion is complete or a conversion is not currently in progress.
1: CS0 conversion is in progress.
Write:
0: No effect.
1: Initiates CS0 conversion if CS0CM[2:0] = 000b, 110b, or 111b.
CS0CMPEN CS0 Digital Comparator Enable Bit.
Enables the digital comparator, which compares accumulated CS0 conversion
output to the value stored in CS0THH:CS0THL.
0: CS0 digital comparator disabled.
1: CS0 digital comparator enabled.
2:1
0
Unused
Read = 00b; Write = Don’t care
CS0CMPF
CS0 Digital Comparator Interrupt Flag.
0: CS0 result is smaller than the value set by CS0THH and CS0THL since the last
time CS0CMPF was cleared.
1: CS0 result is greater than the value set by CS0THH and CS0THL since the last
time CS0CMPF was cleared.
Note: On waking from suspend mode due to a CS0 greater-than comparator event, the CS0CN register
should be accessed only after at least two system clock cycles have elapsed.
Rev. 1.0
75
C8051F80x-83x
SFR Definition 13.2. CS0CF: Capacitive Sense Configuration
Bit
7
6
5
4
3
2
1
0
CS0CM[2:0]
CS0ACU[2:0]
Name
Type
Reset
R
0
R/W
0
R/W
0
R/W
0
R
0
R/W
0
R/W
0
R/W
0
SFR Address = 0x9E
Bit
Name
Description
7
Unused
Read = 0b; Write = Don’t care
6:4
CS0CM[2:0] CS0 Start of Conversion Mode Select.
000: Conversion initiated on every write of 1 to CS0BUSY.
001: Conversion initiated on overflow of Timer 0.
010: Conversion initiated on overflow of Timer 2.
011: Conversion initiated on overflow of Timer 1.
100: Reserved.
101: Reserved.
110: Conversion initiated continuously after writing 1 to CS0BUSY.
111: Auto-scan enabled, conversions initiated continuously after writing 1 to
CS0BUSY.
3
Unused
Read = 0b; Write = Don’t care
2:0 CS0ACU[2:0] CS0 Accumulator Mode Select.
000: Accumulate 1 sample.
001: Accumulate 4 samples.
010: Accumulate 8 samples.
011: Accumulate 16 samples
100: Accumulate 32 samples.
101: Accumulate 64 samples.
11x: Reserved.
76
Rev. 1.0
C8051F80x-83x
SFR Definition 13.3. CS0DH: Capacitive Sense Data High Byte
Bit
7
6
5
4
3
2
1
0
CS0DH[7:0]
Name
Type
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
SFR Address = 0xAC
Bit
Name
Description
7:0
CS0DH
CS0 Data High Byte.
Stores the high byte of the last completed 16-bit Capacitive Sense conversion.
SFR Definition 13.4. CS0DL: Capacitive Sense Data Low Byte
Bit
7
6
5
4
3
2
1
0
CS0DL[7:0]
Name
Type
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
SFR Address = 0xAB
Bit
Name
Description
7:0
CS0DL
CS0 Data Low Byte.
Stores the low byte of the last completed 16-bit Capacitive Sense conversion.
Rev. 1.0
77
C8051F80x-83x
SFR Definition 13.5. CS0SS: Capacitive Sense Auto-Scan Start Channel
Bit
7
6
5
4
3
2
1
0
CS0SS[4:0]
Name
Type
Reset
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Address = 0xB9
Bit
7:5
4:0
Name
Description
Unused
Read = 000b; Write = Don’t care
CS0SS[4:0]
Starting Channel for Auto-Scan.
Sets the first CS0 channel to be selected by the mux for Capacitive Sense conver-
sion when auto-scan is enabled and active.
When auto-scan is enabled, a write to CS0SS will also update CS0MX.
SFR Definition 13.6. CS0SE: Capacitive Sense Auto-Scan End Channel
Bit
7
6
5
4
3
2
1
0
CS0SE[4:0]
Name
Type
Reset
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Address = 0xBA
Bit
7:5
4:0
Name
Description
Unused
Read = 000b; Write = Don’t care
CS0SE[4:0]
Ending Channel for Auto-Scan.
Sets the last CS0 channel to be selected by the mux for Capacitive Sense conver-
sion when auto-scan is enabled and active.
78
Rev. 1.0
C8051F80x-83x
SFR Definition 13.7. CS0THH: Capacitive Sense Comparator Threshold High Byte
Bit
7
6
5
4
3
2
1
0
CS0THH[7:0]
R/W R/W
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
0
SFR Address = 0x97
Bit Name
7:0 CS0THH[7:0] CS0 Comparator Threshold High Byte.
Description
High byte of the 16-bit value compared to the Capacitive Sense conversion result.
SFR Definition 13.8. CS0THL: Capacitive Sense Comparator Threshold Low Byte
Bit
7
6
5
4
3
2
1
0
CS0THL[7:0]
R/W R/W
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
0
SFR Address = 0x96
Bit
Name
CS0THL[7:0] CS0 Comparator Threshold Low Byte.
Low byte of the 16-bit value compared to the Capacitive Sense conversion result.
Description
7:0
Rev. 1.0
79
C8051F80x-83x
13.6. Capacitive Sense Multiplexer
The input multiplexer can be controlled through two methods. The CS0MX register can be written to
through firmware, or the register can be configured automatically using the modules auto-scan functionality
(see “13.3. Automatic Scanning” ).
CS0MX
Note: See the CS0MX
SFR definition for
channel availability for
specific part numbers.
P0.0
(Up to 16
Channels)
CS0MUX
Capsense0
P1.7
Figure 13.3. CS0 Multiplexer Block Diagram
80
Rev. 1.0
C8051F80x-83x
SFR Definition 13.9. CS0MX: Capacitive Sense Mux Channel Select
Bit
7
6
5
4
3
2
1
0
CS0UC
CS0MX[3:0]
Name
R/W
1
R
0
R
0
R
1
R/W
1
R/W
1
R/W
1
R/W
1
Type
Reset
SFR Address = 0x9C
Bit
Name
Description
7
CS0UC
CS0 Unconnected.
Disconnects CS0 from all port pins, regardless of the selected channel.
0: CS0 connected to port pins
1: CS0 disconnected from port pins
6:4
3:0
Reserved
Read = 000b; Write = 000b
CS0MX[3:0] CS0 Mux Channel Select.
Selects one of the 16 input channels for Capacitive Sense conversion.
Value
C8051F800/6,
C8051F812/8
C8051F803/9,
C8051F815,
C8051F801/4/7,
C8051F810/3/6/9,
C8051F821/4/7, C8051F822/5/8,
C8051F830/3
C8051F831/4
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P0.0
P0.0
P0.1
P0.1
P0.2
P0.2
P0.3
P0.3
P0.4
P0.4
P0.5
P0.5
P0.6
P0.6
P0.7
P0.7
P1.0
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
P1.1
P1.2
P1.3
Reserved.
Reserved.
Reserved.
Reserved.
Note: CS0MX is Reserved on all the devices that are not listed in the above table.
Rev. 1.0
81
C8051F80x-83x
14. CIP-51 Microcontroller
The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the
MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft-
ware. The MCU family has a superset of all the peripherals included with a standard 8051. The CIP-51
also includes on-chip debug hardware (see description in Section 30), and interfaces directly with the ana-
log and digital subsystems providing a complete data acquisition or control-system solution in a single inte-
grated circuit.
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as
additional custom peripherals and functions to extend its capability (see Figure 14.1 for a block diagram).
The CIP-51 includes the following features:
Fully Compatible with MCS-51 Instruction Set
25 MIPS Peak Throughput with 25 MHz Clock
0 to 25 MHz Clock Frequency
Reset Input
Power Management Modes
On-chip Debug Logic
Extended Interrupt Handler
Program and Data Memory Security
Performance
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan-
dard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51
core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more
than eight system clock cycles.
DATA BUS
ACCUMULATOR
B
REGISTER
STACK POINTER
TMP1
TMP2
SRAM
ADDRESS
REGISTER
PSW
SRAM
ALU
DATA BUS
SFR_ADDRESS
SFR_CONTROL
D8
BUFFER
SFR
BUS
INTERFACE
D8
SFR_WRITE_DATA
SFR_READ_DATA
D8
DATA POINTER
PC INCREMENTER
D8
MEM_ADDRESS
MEM_CONTROL
PROGRAM COUNTER (PC)
PRGM. ADDRESS REG.
PIPELINE
MEMORY
INTERFACE
A16
D8
MEM_WRITE_DATA
MEM_READ_DATA
CONTROL
LOGIC
RESET
CLOCK
SYSTEM_IRQs
INTERRUPT
INTERFACE
EMULATION_IRQ
D8
STOP
IDLE
POWER CONTROL
REGISTER
D8
Figure 14.1. CIP-51 Block Diagram
82
Rev. 1.0
C8051F80x-83x
With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. The CIP-51 has
a total of 109 instructions. The table below shows the total number of instructions that require each execu-
tion time.
Clocks to Execute
1
2
2/3
5
3
3/4
6
4
3
4/5
2
5
2
8
1
Number of Instructions
26
50
14
14.1. Instruction Set
The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ instruc-
tion set. Standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51
instructions are the binary and functional equivalent of their MCS-51™ counterparts, including opcodes,
addressing modes and effect on PSW flags. However, instruction timing is different than that of the stan-
dard 8051.
14.1.1. Instruction and CPU Timing
In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with
machine cycles varying from 2 to 12 clock cycles in length. However, the CIP-51 implementation is based
solely on clock cycle timing. All instruction timings are specified in terms of clock cycles.
Due to the pipelined architecture of the CIP-51, most instructions execute in the same number of clock
cycles as there are program bytes in the instruction. Conditional branch instructions take one less clock
cycle to complete when the branch is not taken as opposed to when the branch is taken. Table 14.1 is the
CIP-51 Instruction Set Summary, which includes the mnemonic, number of bytes, and number of clock
cycles for each instruction.
Rev. 1.0
83
C8051F80x-83x
Table 14.1. CIP-51 Instruction Set Summary
Mnemonic
Description
Bytes
Clock
Cycles
Arithmetic Operations
ADD A, Rn
ADD A, direct
ADD A, @Ri
ADD A, #data
ADDC A, Rn
ADDC A, direct
ADDC A, @Ri
ADDC A, #data
SUBB A, Rn
SUBB A, direct
SUBB A, @Ri
SUBB A, #data
INC A
INC Rn
INC direct
INC @Ri
DEC A
DEC Rn
DEC direct
DEC @Ri
INC DPTR
MUL AB
DIV AB
Add register to A
Add direct byte to A
Add indirect RAM to A
Add immediate to A
Add register to A with carry
Add direct byte to A with carry
Add indirect RAM to A with carry
Add immediate to A with carry
Subtract register from A with borrow
Subtract direct byte from A with borrow
Subtract indirect RAM from A with borrow
Subtract immediate from A with borrow
Increment A
Increment register
Increment direct byte
Increment indirect RAM
Decrement A
Decrement register
Decrement direct byte
Decrement indirect RAM
Increment Data Pointer
Multiply A and B
Divide A by B
Decimal adjust A
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
1
1
2
1
1
1
1
1
1
2
2
2
1
2
2
2
1
2
2
2
1
1
2
2
1
1
2
2
1
4
8
1
DA A
Logical Operations
ANL A, Rn
AND Register to A
AND direct byte to A
AND indirect RAM to A
AND immediate to A
AND A to direct byte
AND immediate to direct byte
OR Register to A
OR direct byte to A
OR indirect RAM to A
OR immediate to A
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
2
1
2
2
2
2
3
1
2
2
2
2
3
1
2
2
2
2
ANL A, direct
ANL A, @Ri
ANL A, #data
ANL direct, A
ANL direct, #data
ORL A, Rn
ORL A, direct
ORL A, @Ri
ORL A, #data
ORL direct, A
ORL direct, #data
XRL A, Rn
OR A to direct byte
OR immediate to direct byte
Exclusive-OR Register to A
Exclusive-OR direct byte to A
Exclusive-OR indirect RAM to A
Exclusive-OR immediate to A
Exclusive-OR A to direct byte
XRL A, direct
XRL A, @Ri
XRL A, #data
XRL direct, A
84
Rev. 1.0
C8051F80x-83x
Table 14.1. CIP-51 Instruction Set Summary (Continued)
Mnemonic
Description
Bytes
Clock
Cycles
XRL direct, #data
CLR A
CPL A
RL A
RLC A
RR A
RRC A
SWAP A
Exclusive-OR immediate to direct byte
Clear A
Complement A
Rotate A left
Rotate A left through Carry
Rotate A right
3
1
1
1
1
1
1
1
3
1
1
1
1
1
1
1
Rotate A right through Carry
Swap nibbles of A
Data Transfer
MOV A, Rn
MOV A, direct
MOV A, @Ri
MOV A, #data
MOV Rn, A
Move Register to A
Move direct byte to A
Move indirect RAM to A
Move immediate to A
1
2
1
2
1
2
2
2
2
3
2
3
1
2
2
3
1
1
1
1
1
1
2
2
1
2
1
1
1
2
2
2
1
2
2
2
2
3
2
3
2
2
2
3
3
3
3
3
3
3
2
2
1
2
2
2
Move A to Register
MOV Rn, direct
MOV Rn, #data
MOV direct, A
MOV direct, Rn
MOV direct, direct
MOV direct, @Ri
MOV direct, #data
MOV @Ri, A
MOV @Ri, direct
MOV @Ri, #data
MOV DPTR, #data16
MOVC A, @A+DPTR
MOVC A, @A+PC
MOVX A, @Ri
MOVX @Ri, A
MOVX A, @DPTR
MOVX @DPTR, A
PUSH direct
Move direct byte to Register
Move immediate to Register
Move A to direct byte
Move Register to direct byte
Move direct byte to direct byte
Move indirect RAM to direct byte
Move immediate to direct byte
Move A to indirect RAM
Move direct byte to indirect RAM
Move immediate to indirect RAM
Load DPTR with 16-bit constant
Move code byte relative DPTR to A
Move code byte relative PC to A
Move external data (8-bit address) to A
Move A to external data (8-bit address)
Move external data (16-bit address) to A
Move A to external data (16-bit address)
Push direct byte onto stack
Pop direct byte from stack
POP direct
XCH A, Rn
XCH A, direct
XCH A, @Ri
Exchange Register with A
Exchange direct byte with A
Exchange indirect RAM with A
Exchange low nibble of indirect RAM with A
XCHD A, @Ri
Boolean Manipulation
CLR C
Clear Carry
Clear direct bit
Set Carry
Set direct bit
Complement Carry
Complement direct bit
1
2
1
2
1
2
1
2
1
2
1
2
CLR bit
SETB C
SETB bit
CPL C
CPL bit
Rev. 1.0
85
C8051F80x-83x
Table 14.1. CIP-51 Instruction Set Summary (Continued)
Mnemonic
Description
Bytes
Clock
Cycles
ANL C, bit
ANL C, /bit
ORL C, bit
ORL C, /bit
MOV C, bit
MOV bit, C
JC rel
AND direct bit to Carry
AND complement of direct bit to Carry
OR direct bit to carry
OR complement of direct bit to Carry
Move direct bit to Carry
Move Carry to direct bit
Jump if Carry is set
Jump if Carry is not set
Jump if direct bit is set
Jump if direct bit is not set
Jump if direct bit is set and clear bit
2
2
2
2
2
2
2
2
3
3
3
2
2
2
2
2
2
2/3
2/3
3/4
3/4
3/4
JNC rel
JB bit, rel
JNB bit, rel
JBC bit, rel
Program Branching
ACALL addr11
LCALL addr16
RET
Absolute subroutine call
Long subroutine call
Return from subroutine
Return from interrupt
Absolute jump
Long jump
Short jump (relative address)
Jump indirect relative to DPTR
Jump if A equals zero
Jump if A does not equal zero
Compare direct byte to A and jump if not equal
Compare immediate to A and jump if not equal
Compare immediate to Register and jump if not
equal
2
3
1
1
2
3
2
1
2
2
3
3
3
3
4
5
5
3
4
3
3
2/3
2/3
4/5
3/4
3/4
RETI
AJMP addr11
LJMP addr16
SJMP rel
JMP @A+DPTR
JZ rel
JNZ rel
CJNE A, direct, rel
CJNE A, #data, rel
CJNE Rn, #data, rel
CJNE @Ri, #data, rel
Compare immediate to indirect and jump if not
equal
3
4/5
DJNZ Rn, rel
DJNZ direct, rel
NOP
Decrement Register and jump if not zero
Decrement direct byte and jump if not zero
No operation
2
3
1
2/3
3/4
1
86
Rev. 1.0
C8051F80x-83x
Notes on Registers, Operands and Addressing Modes:
Rn—Register R0–R7 of the currently selected register bank.
@Ri—Data RAM location addressed indirectly through R0 or R1.
rel—8-bit, signed (twos complement) offset relative to the first byte of the following instruction. Used by
SJMP and all conditional jumps.
direct—8-bit internal data location’s address. This could be a direct-access Data RAM location (0x00–
0x7F) or an SFR (0x80–0xFF).
#data—8-bit constant
#data16—16-bit constant
bit—Direct-accessed bit in Data RAM or SFR
addr11—11-bit destination address used by ACALL and AJMP. The destination must be within the
same 2 kB page of program memory as the first byte of the following instruction.
addr16—16-bit destination address used by LCALL and LJMP. The destination may be anywhere within
the 8 kB program memory space.
There is one unused opcode (0xA5) that performs the same function as NOP.
All mnemonics copyrighted © Intel Corporation 1980.
Rev. 1.0
87
C8051F80x-83x
14.2. CIP-51 Register Descriptions
Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits
should always be written to the value indicated in the SFR description. Future product versions may use
these bits to implement new features in which case the reset value of the bit will be the indicated value,
selecting the feature's default state. Detailed descriptions of the remaining SFRs are included in the sec-
tions of the data sheet associated with their corresponding system function.
SFR Definition 14.1. DPL: Data Pointer Low Byte
Bit
7
6
5
4
3
2
1
0
DPL[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Address = 0x82
Bit
Name
DPL[7:0] Data Pointer Low.
The DPL register is the low byte of the 16-bit DPTR.
Function
7:0
SFR Definition 14.2. DPH: Data Pointer High Byte
Bit
7
6
5
4
3
2
1
0
DPH[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Address = 0x83
Bit
Name
Function
7:0
DPH[7:0] Data Pointer High.
The DPH register is the high byte of the 16-bit DPTR.
88
Rev. 1.0
C8051F80x-83x
SFR Definition 14.3. SP: Stack Pointer
Bit
7
6
5
4
3
2
1
0
SP[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
1
1
1
SFR Address = 0x81
Bit
Name
Function
7:0
SP[7:0]
Stack Pointer.
The Stack Pointer holds the location of the top of the stack. The stack pointer is incre-
mented before every PUSH operation. The SP register defaults to 0x07 after reset.
SFR Definition 14.4. ACC: Accumulator
Bit
7
6
5
4
3
2
1
0
ACC[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xE0; Bit-Addressable
Bit
Name
Function
7:0
ACC[7:0] Accumulator.
This register is the accumulator for arithmetic operations.
Rev. 1.0
89
C8051F80x-83x
SFR Definition 14.5. B: B Register
Bit
7
6
5
4
3
2
1
0
B[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xF0; Bit-Addressable
Bit
Name
Function
7:0
B[7:0]
B Register.
This register serves as a second accumulator for certain arithmetic operations.
90
Rev. 1.0
C8051F80x-83x
SFR Definition 14.6. PSW: Program Status Word
Bit
7
6
5
4
3
2
1
0
CY
AC
F0
RS[1:0]
R/W
OV
F1
PARITY
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
0
0
SFR Address = 0xD0; Bit-Addressable
Bit
Name
Function
7
CY
Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry (addition) or a bor-
row (subtraction). It is cleared to logic 0 by all other arithmetic operations.
6
AC
Auxiliary Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry into (addition) or a
borrow from (subtraction) the high order nibble. It is cleared to logic 0 by all other arith-
metic operations.
5
F0
User Flag 0.
This is a bit-addressable, general purpose flag for use under software control.
4:3
RS[1:0] Register Bank Select.
These bits select which register bank is used during register accesses.
00: Bank 0, Addresses 0x00-0x07
01: Bank 1, Addresses 0x08-0x0F
10: Bank 2, Addresses 0x10-0x17
11: Bank 3, Addresses 0x18-0x1F
2
OV
Overflow Flag.
This bit is set to 1 under the following circumstances:
An ADD, ADDC, or SUBB instruction causes a sign-change overflow.
A MUL instruction results in an overflow (result is greater than 255).
A DIV instruction causes a divide-by-zero condition.
The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all
other cases.
1
0
F1
User Flag 1.
This is a bit-addressable, general purpose flag for use under software control.
PARITY Parity Flag.
This bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared
if the sum is even.
Rev. 1.0
91
C8051F80x-83x
15. Memory Organization
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are
two separate memory spaces: program memory and data memory. Program and data memory share the
same address space but are accessed via different instruction types. The memory organization of the
C8051F80x-83x device family is shown in Figure 15.1
PROGRAM/DATA MEMORY
(FLASH)
DATA MEMORY (RAM)
INTERNAL DATA ADDRESS SPACE
0xFF
C8051F80x and C8051F810/1
Upper 128 RAM
(Indirect Addressing
Only)
Special Function
Register's
(Direct Addressing Only)
0x3FFF
Lock Byte
0x3FFE
0x80
0x7F
16 kB Flash
(Direct and Indirect
Addressing)
(In-System
Programmable in 512
Byte Sectors)
Lower 128 RAM
(Direct and Indirect
Addressing)
0x30
0x2F
Bit Addressable
0x0000
0x20
0x1F
General Purpose
Registers
C8051F812/3/4/5/6/7/8/9
and C8051F82x
0x00
0x1FFF
0x1FFE
Lock Byte
EXTERNAL DATA ADDRESS SPACE
8 kB Flash
C8051F80x, C8051F81x, and
C8051F820/1/2/3 Only
(In-System
Programmable in 512
Byte Sectors)
0xFFFF
0x0000
Same 256 bytes as from
0x0000 to 0x01FF, wrapped
on 256-byte boundaries
C8051F830/1/2/3/4/5
0x0FFF
0x0FFE
Lock Byte
4 kB Flash
0x0100
0x00FF
(In-System
Programmable in 512
Byte Sectors)
XRAM - 256 Bytes
(accessable using MOVX
instruction)
0x0000
0x0000
Figure 15.1. C8051F80x-83x Memory Map
92
Rev. 1.0
C8051F80x-83x
15.1. Program Memory
The members of the C8051F80x-83x device family contain 16 kB (C8051F80x and C8051F810/1), 8 kB
(C8051F812/3/4/5/6/7/8/9 and C8051F82x), or 4 kB (C8051F830/1/2/3/4/5) of re-programmable Flash
memory that can be used as non-volatile program or data storage. The last byte of user code space is
used as the security lock byte (0x3FFF on 16 kB devices, 0x1FFF on 8 kB devices and 0x0FFF on 4 kB
devices).
C8051F80x and
C8051F810/1 (16kB)
0x3FFF
Lock Byte
C8051F812/3/4/5/6/7/8/9
and C8051F82x (8 kB)
0x3FFE
Lock Byte Page
0x3E00
0x1FFF
0x1FFE
Lock Byte
Lock Byte Page
C8051F830/1/2/3/4/5 (4 kB)
Lock Byte
0x1E00
0x0FFF
0x0FFE
Flash Memory Space
Lock Byte Page
0x0E00
Flash Memory Space
Flash Memory Space
0x0000
0x0000
0x0000
Figure 15.2. Flash Program Memory Map
15.1.1. MOVX Instruction and Program Memory
The MOVX instruction in an 8051 device is typically used to access external data memory. On the
C8051F80x-83x devices, the MOVX instruction is normally used to read and write on-chip XRAM, but can
be re-configured to write and erase on-chip Flash memory space. MOVC instructions are always used to
read Flash memory, while MOVX write instructions are used to erase and write Flash. This Flash access
feature provides a mechanism for the C8051F80x-83x to update program code and use the program mem-
ory space for non-volatile data storage. Refer to Section “19. Flash Memory” on page 113 for further
details.
15.2. Data Memory
The members of the C8051F80x-83x device family contain 512 bytes (C8051F80x, C8051F81x, and
C8051F820/1/2/3) or 256 bytes (C8051F824/5/6/7/8/9 and C8051F830/1/2/3/4/5) of RAM data memory.
For all C8051F80x-83x devices, 256 bytes of this memory is mapped into the internal RAM space of the
8051. For the devices with 512 bytes of RAM, the remaining 256 bytes of this memory is on-chip “external”
memory. The data memory map is shown in Figure 15.1 for reference.
15.2.1. Internal RAM
There are 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The
lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either
direct or indirect addressing may be used to access the lower 128 bytes of data memory. Locations 0x00
through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight
byte-wide registers. The next 16 bytes, locations 0x20 through 0x2F, may either be addressed as bytes or
as 128 bit locations accessible with the direct addressing mode.
The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the
same address space as the Special Function Registers (SFR) but is physically separate from the SFR
space. The addressing mode used by an instruction when accessing locations above 0x7F determines
Rev. 1.0
93
C8051F80x-83x
whether the CPU accesses the upper 128 bytes of data memory space or the SFRs. Instructions that use
direct addressing will access the SFR space. Instructions using indirect addressing above 0x7F access the
upper 128 bytes of data memory. Figure 15.1 illustrates the data memory organization of the C8051F80x-
83x.
15.2.1.1. General Purpose Registers
The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of gen-
eral-purpose registers. Each bank consists of eight byte-wide registers designated R0 through R7. Only
one of these banks may be enabled at a time. Two bits in the program status word, RS0 (PSW.3) and RS1
(PSW.4), select the active register bank (see description of the PSW in SFR Definition 14.6). This allows
fast context switching when entering subroutines and interrupt service routines. Indirect addressing modes
use registers R0 and R1 as index registers.
15.2.1.2. Bit Addressable Locations
In addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20
through 0x2F are also accessible as 128 individually addressable bits. Each bit has a bit address from
0x00 to 0x7F. Bit 0 of the byte at 0x20 has bit address 0x00 while bit7 of the byte at 0x20 has bit address
0x07. Bit 7 of the byte at 0x2F has bit address 0x7F. A bit access is distinguished from a full byte access by
the type of instruction used (bit source or destination operands as opposed to a byte source or destina-
tion).
The MCS-51™ assembly language allows an alternate notation for bit addressing of the form XX.B where
XX is the byte address and B is the bit position within the byte. For example, the instruction:
MOV
C, 22.3h
moves the Boolean value at 0x13 (bit 3 of the byte at location 0x22) into the Carry flag.
15.2.1.3. Stack
A programmer's stack can be located anywhere in the 256-byte data memory. The stack area is desig-
nated using the Stack Pointer (SP) SFR. The SP will point to the last location used. The next value pushed
on the stack is placed at SP+1 and then SP is incremented. A reset initializes the stack pointer to location
0x07. Therefore, the first value pushed on the stack is placed at location 0x08, which is also the first regis-
ter (R0) of register bank 1. Thus, if more than one register bank is to be used, the SP should be initialized
to a location in the data memory not being used for data storage. The stack depth can extend up to
256 bytes.
94
Rev. 1.0
C8051F80x-83x
16. In-System Device Identification
The C8051F80x-83x has SFRs that identify the device family and derivative. These SFRs can be read by
firmware at runtime to determine the capabilities of the MCU that is executing code. This allows the same
firmware image to run on MCUs with different memory sizes and peripherals, and dynamically changing
functionality to suit the capabilities of that MCU.
In order for firmware to identify the MCU, it must read three SFRs. HWID describes the MCU’s family,
DERIVID describes the specific derivative within that device family, and REVID describes the hardware
revision of the MCU.
SFR Definition 16.1. HWID: Hardware Identification Byte
Bit
7
6
5
4
3
2
1
0
HWID[7:0]
Name
Type
Reset
R
0
R
0
R
1
R
0
R
0
R
0
R
1
R
1
SFR Address = 0xB5
Bit
Name
Description
HWID[7:0]
7:0
Hardware Identification Byte.
Describes the MCU family.
0x23: Devices covered in this document (C8051F80x-83x)
Rev. 1.0
95
C8051F80x-83x
SFR Definition 16.2. DERIVID: Derivative Identification Byte
Bit
7
6
5
4
3
2
1
0
DERIVID[7:0]
Name
Type
Reset
R
R
R
R
R
R
R
R
Varies
Varies
Varies
Varies
Varies
Varies
Varies
Varies
SFR Address = 0xAD
Bit
Name
Description
DERIVID[7:0]
7:0
Derivative Identification Byte.
Shows the C8051F80x-83x derivative being used.
0xD0: C8051F800; 0xD1: C8051F801; 0xD2: C8051F802; 0xD3: C8051F803
0xD4: C8051F804; 0xD5: C8051F805; 0xD6: C8051F806; 0xD7: C8051F807
0xD8: C8051F808; 0xD9: C8051F809; 0xDA: C8051F810; 0xDB: C8051F811
0xDC: C8051F812; 0xDD: C8051F813; 0xDE: C8051F814; 0xDF: C8051F815
0xE0: C8051F816; 0xE1: C8051F817; 0xE2: C8051F818; 0xE3: C8051F819
0xE4: C8051F820; 0xE5: C8051F821; 0xE6: C8051F822; 0xE7: C8051F823
0xE8: C8051F824; 0xE9: C8051F825; 0xEA: C8051F826; 0xEB: C8051F827
0xEC: C8051F828; 0xED: C8051F829; 0xEE: C8051F830; 0xEF: C8051F831
0xF0: C8051F832; 0xF1: C8051F833; 0xF2: C8051F834; 0xF3: C8051F835
SFR Definition 16.3. REVID: Hardware Revision Identification Byte
Bit
7
6
5
4
3
2
1
0
REVID[7:0]
Name
Type
Reset
R
R
R
R
R
R
R
R
Varies
Varies
Varies
Varies
Varies
Varies
Varies
Varies
SFR Address = 0xB6
Bit
Name
Description
REVID[7:0]
7:0
Hardware Revision Identification Byte.
Shows the C8051F80x-83x hardware revision being used.
For example, 0x00 = Revision A.
96
Rev. 1.0
C8051F80x-83x
17. Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFRs). The SFRs provide control and data exchange with the C8051F80x-83x's resources and peripher-
als. The CIP-51 controller core duplicates the SFRs found in a typical 8051 implementation as well as
implementing additional SFRs used to configure and access the sub-systems unique to the C8051F80x-
83x. This allows the addition of new functionality while retaining compatibility with the MCS-51™ instruc-
tion set. Table 17.1 lists the SFRs implemented in the C8051F80x-83x device family.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations
from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g., P0, TCON, SCON0, IE, etc.) are bit-
addressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied
addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate
effect and should be avoided. Refer to the corresponding pages of the data sheet, as indicated in
Table 17.2, for a detailed description of each register.
Table 17.1. Special Function Register (SFR) Memory Map
F8 SPI0CN
F0
PCA0L
PCA0H PCA0CPL0 PCA0CPH0 P0MAT
P1MDIN EIP1 EIP2
P0MASK
VDM0CN
PCA0PWM
RSTSRC
EIE2
B
P0MDIN
E8 ADC0CN PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2 P1MAT
E0 ACC XBR0 XBR1 IT01CF
P1MASK
EIE1
D8 PCA0CN PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2 CRC0IN CRC0DATA
D0
PSW
REF0CN CRC0AUTO CRC0CNT
P0SKIP
TMR2L
P1SKIP
TMR2H
SMB0ADM SMB0ADR
CRC0CN CRC0FLIP
C8 TMR2CN REG0CN TMR2RLL TMR2RLH
C0 SMB0CN SMB0CF SMB0DAT ADC0GTL ADC0GTH ADC0LTL ADC0LTH
B8
IP
CS0SS
CS0SE
ADC0MX
OSCICL
CS0DL
ADC0CF
ADC0L
HWID
ADC0H
REVID
B0 CS0CN OSCXCN
OSCICN
FLKEY
A8
A0
IE
CLKSEL
CS0DH
DERVID
P2
SPI0CFG SPI0CKR
SBUF0
SPI0DAT P0MDOUT P1MDOUT P2MDOUT
98 SCON0
90 P1
88 TCON
CPT0CN
CS0MX
CPT0MD
CS0CF
CS0THL
CKCON
CPT0MX
CS0THH
PSCTL
PCON
TMOD
SP
TL0
DPL
2(A)
TL1
DPH
3(B)
TH0
TH1
80
P0
0(8)
1(9)
4(C)
5(D)
6(E)
7(F)
Note: SFR Addresses ending in 0x0 or 0x8 are bit-addressable locations, and can be used with bitwise instructions.
Rev. 1.0
97
C8051F80x-83x
Table 17.2. Special Function Registers
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
ACC
Address
Description
Page
0xE0
Accumulator
89
0xBC
0xE8
0xC4
0xC3
0xBE
0xBD
0xC6
0xC5
0xBB
0xF0
0x8E
0xA9
0x9B
0x9D
0x9F
0xD2
0xCE
0xD3
0xDE
0xCF
0xDD
0x97
0x96
0xB0
0xAC
0xAB
ADC0 Configuration
50
52
ADC0CF
ADC0CN
ADC0GTH
ADC0GTL
ADC0H
ADC0 Control
ADC0 Greater-Than Compare High
ADC0 Greater-Than Compare Low
ADC0 High
53
53
51
ADC0 Low
51
ADC0L
ADC0 Less-Than Compare Word High
ADC0 Less-Than Compare Word Low
AMUX0 Multiplexer Channel Select
B Register
54
ADC0LTH
ADC0LTL
ADC0MX
B
54
57
90
Clock Control
210
210
67
CKCON
CLKSEL
CPT0CN
CPT0MD
CPT0MX
CRC0AUTO
CRC0CN
CRC0CNT
CRC0DATA
CRC0FLIP
CRC0IN
CS0THH
CS0THL
CS0CN
Clock Select
Comparator0 Control
Comparator0 Mode Selection
Comparator0 MUX Selection
CRC0 Automatic Control Register
CRC0 Control
68
70
165
163
165
164
166
164
79
CRC0 Automatic Flash Sector Count
CRC0 Data Output
CRC0 Bit Flip
CRC Data Input
CS0 Digital Compare Threshold High
CS0 Digital Compare Threshold High
CS0 Control
79
75
CS0 Data High
77
CS0DH
CS0 Data Low
77
CS0DL
98
Rev. 1.0
C8051F80x-83x
Table 17.2. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
CS0CF
Address
Description
Page
0x9E
CS0 Configuration
CS0 Mux
76
0x9C
0xBA
0xB9
0xAD
0x83
0x82
0xE6
0xE7
0xF3
0xF4
0xB7
0xB5
0xA8
0xB8
0xE4
0xB3
0xB2
0xB1
0x80
0xFE
0xFD
0xF1
0xA4
0xD4
0x90
0xEE
81
78
CS0MX
CS0SE
CS0SS
DERIVID
DPH
Auto Scan End Channel
Auto Scan Start Channel
Derivative Identification
Data Pointer High
78
96
88
Data Pointer Low
88
DPL
Extended Interrupt Enable 1
Extended Interrupt Enable 2
Extended Interrupt Priority 1
Extended Interrupt Priority 2
Flash Lock And Key
Hardware Identification
Interrupt Enable
107
108
109
110
119
95
EIE1
EIE2
EIP1
EIP2
FLKEY
HWID
105
106
112
131
132
134
153
151
151
154
154
155
155
152
IE
Interrupt Priority
IP
INT0/INT1 Configuration
Internal Oscillator Calibration
Internal Oscillator Control
External Oscillator Control
Port 0 Latch
IT01CF
OSCICL
OSCICN
OSCXCN
P0
Port 0 Mask
P0MASK
P0MAT
P0MDIN
P0MDOUT
P0SKIP
P1
Port 0 Match
Port 0 Input Mode Configuration
Port 0 Output Mode Configuration
Port 0 Skip
Port 1 Latch
P0 Mask
P1MASK
Rev. 1.0
99
C8051F80x-83x
Table 17.2. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
P1MAT
Address
Description
Page
0xED
P1 Match
152
0xF2
0xA5
0xD5
0xA0
0xA6
0xD8
0xFC
0xEA
0xEC
0xFB
0xE9
0xEB
0xDA
0xDB
0xDC
0xFA
0xF9
0xD9
0xF7
0x87
0x8F
0xD0
0xD1
0xC9
0xB6
0xEF
Port 1 Input Mode Configuration
Port 1 Output Mode Configuration
Port 1 Skip
156
156
157
157
158
238
243
243
243
243
243
243
241
241
241
242
242
239
240
122
118
91
P1MDIN
P1MDOUT
P1SKIP
Port 2 Latch
P2
Port 2 Output Mode Configuration
PCA Control
P2MDOUT
PCA0CN
PCA0CPH0
PCA0CPH1
PCA0CPH2
PCA0CPL0
PCA0CPL1
PCA0CPL2
PCA0CPM0
PCA0CPM1
PCA0CPM2
PCA0H
PCA Capture 0 High
PCA Capture 1 High
PCA Capture 2 High
PCA Capture 0 Low
PCA Capture 1 Low
PCA Capture 2 Low
PCA Module 0 Mode Register
PCA Module 1 Mode Register
PCA Module 2 Mode Register
PCA Counter High
PCA Counter Low
PCA0L
PCA Mode
PCA0MD
PCA0PWM
PCON
PCA PWM Configuration
Power Control
Program Store R/W Control
Program Status Word
Voltage Reference Control
Voltage Regulator Control
Revision ID
PSCTL
PSW
62
REF0CN
REG0CN
REVID
64
96
Reset Source Configuration/Status
128
RSTSRC
100
Rev. 1.0
C8051F80x-83x
Table 17.2. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
SBUF0
Address
Description
Page
0x99
UART0 Data Buffer
UART0 Control
207
0x98
0xD6
0xD7
0xC1
0xC0
0xC2
0x81
0xA1
0xA2
0xF8
0xA3
0x88
0x8C
0x8D
0x8A
0x8B
0x89
0xC8
0xCD
0xCC
0xCB
0xCA
0xFF
0xE1
0xE2
206
191
191
186
188
192
89
SCON0
SMB0ADM
SMB0ADR
SMB0CF
SMB0CN
SMB0DAT
SP
SMBus Slave Address mask
SMBus Slave Address
SMBus Configuration
SMBus Control
SMBus Data
Stack Pointer
SPI0 Configuration
SPI0 Clock Rate Control
SPI0 Control
174
176
175
176
215
218
218
217
217
216
222
224
224
223
223
126
148
149
SPI0CFG
SPI0CKR
SPI0CN
SPI0DAT
TCON
SPI0 Data
Timer/Counter Control
Timer/Counter 0 High
Timer/Counter 1 High
Timer/Counter 0 Low
Timer/Counter 1 Low
Timer/Counter Mode
Timer/Counter 2 Control
Timer/Counter 2 High
Timer/Counter 2 Low
Timer/Counter 2 Reload High
Timer/Counter 2 Reload Low
VDD Monitor Control
Port I/O Crossbar Control 0
Port I/O Crossbar Control 1
Reserved
TH0
TH1
TL0
TL1
TMOD
TMR2CN
TMR2H
TMR2L
TMR2RLH
TMR2RLL
VDM0CN
XBR0
XBR1
All other SFR Locations
Rev. 1.0
101
C8051F80x-83x
18. Interrupts
The C8051F80x-83x includes an extended interrupt system supporting a total of 15 interrupt sources with
two priority levels. The allocation of interrupt sources between on-chip peripherals and external input pins
varies according to the specific version of the device. Each interrupt source has one or more associated
interrupt-pending flag(s) located in an SFR. When a peripheral or external source meets a valid interrupt
condition, the associated interrupt-pending flag is set to logic 1.
If interrupts are enabled for the source, an interrupt request is generated when the interrupt-pending flag is
set. As soon as execution of the current instruction is complete, the CPU generates an LCALL to a prede-
termined address to begin execution of an interrupt service routine (ISR). Each ISR must end with an RETI
instruction, which returns program execution to the next instruction that would have been executed if the
interrupt request had not occurred. If interrupts are not enabled, the interrupt-pending flag is ignored by the
hardware and program execution continues as normal. (The interrupt-pending flag is set to logic 1 regard-
less of the interrupt's enable/disable state.)
Each interrupt source can be individually enabled or disabled through the use of an associated interrupt
enable bit in an SFR (IE–EIE1). However, interrupts must first be globally enabled by setting the EA bit
(IE.7) to logic 1 before the individual interrupt enables are recognized. Setting the EA bit to logic 0 disables
all interrupt sources regardless of the individual interrupt-enable settings.
Some interrupt-pending flags are automatically cleared by the hardware when the CPU vectors to the ISR.
However, most are not cleared by the hardware and must be cleared by software before returning from the
ISR. If an interrupt-pending flag remains set after the CPU completes the return-from-interrupt (RETI)
instruction, a new interrupt request will be generated immediately and the CPU will re-enter the ISR after
the completion of the next instruction.
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18.1. MCU Interrupt Sources and Vectors
The C8051F80x-83x MCUs support 15 interrupt sources. Software can simulate an interrupt by setting an
interrupt-pending flag to logic 1. If interrupts are enabled for the flag, an interrupt request will be generated
and the CPU will vector to the ISR address associated with the interrupt-pending flag. MCU interrupt
sources, associated vector addresses, priority order and control bits are summarized in Table 18.1. Refer
to the datasheet section associated with a particular on-chip peripheral for information regarding valid
interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s).
18.1.1. Interrupt Priorities
Each interrupt source can be individually programmed to one of two priority levels: low or high. A low prior-
ity interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be
preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP or EIP1) used to configure
its priority level. Low priority is the default. If two interrupts are recognized simultaneously, the interrupt with
the higher priority is serviced first. If both interrupts have the same priority level, a fixed priority order is
used to arbitrate, given in Table 18.1.
18.1.2. Interrupt Latency
Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are
sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is 5
system clock cycles: 1 clock cycle to detect the interrupt and 4 clock cycles to complete the LCALL to the
ISR. If an interrupt is pending when a RETI is executed, a single instruction is executed before an LCALL
is made to service the pending interrupt. Therefore, the maximum response time for an interrupt (when no
other interrupt is currently being serviced or the new interrupt is of greater priority) occurs when the CPU is
performing an RETI instruction followed by a DIV as the next instruction. In this case, the response time is
18 system clock cycles: 1 clock cycle to detect the interrupt, 5 clock cycles to execute the RETI, 8 clock
cycles to complete the DIV instruction and 4 clock cycles to execute the LCALL to the ISR. If the CPU is
executing an ISR for an interrupt with equal or higher priority, the new interrupt will not be serviced until the
current ISR completes, including the RETI and following instruction.
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Table 18.1. Interrupt Summary
Order
Interrupt Source
Interrupt Priority Pending Flag
Vector
Enable
Flag
Priority
Control
Reset
0x0000
0x0003
Top
0
None
N/A N/A Always
Enabled
Always
Highest
External Interrupt 0
(INT0)
IE0 (TCON.1)
Y
Y
EX0 (IE.0) PX0 (IP.0)
Timer 0 Overflow
External Interrupt 1
(INT1)
0x000B
0x0013
1
2
TF0 (TCON.5)
IE1 (TCON.3)
Y
Y
Y
Y
ET0 (IE.1) PT0 (IP.1)
EX1 (IE.2) PX1 (IP.2)
Timer 1 Overflow
UART0
0x001B
0x0023
3
4
TF1 (TCON.7)
RI0 (SCON0.0)
Y
Y
Y
N
ET1 (IE.3) PT1 (IP.3)
ES0 (IE.4) PS0 (IP.4)
TI0 (SCON0.1)
Timer 2 Overflow
SPI0
0x002B
0x0033
5
6
TF2H (TMR2CN.7)
TF2L (TMR2CN.6)
SPIF (SPI0CN.7)
WCOL (SPI0CN.6)
MODF (SPI0CN.5)
RXOVRN (SPI0CN.4)
SI (SMB0CN.0)
Y
Y
N
ET2 (IE.5) PT2 (IP.5)
ESPI0
(IE.6)
PSPI0
(IP.6)
SMB0
0x003B
0x0043
0x004B
0x0053
7
Y
N
ESMB0
(EIE1.0)
PSMB0
(EIP1.0)
PMAT
Port Match
8
None
N/A N/A EMAT
(EIE1.1)
(EIP1.1)
EWADC0 PWADC0
ADC0
Window Compare
ADC0
Conversion Complete
Programmable
Counter Array
Comparator0
9
AD0WINT (ADC0CN.3) Y
N
N
N
N
(EIE1.2)
(EIP1.2)
10
AD0INT (ADC0CN.5)
Y
Y
N
EADC0
(EIE1.3)
PADC0
(EIP1.3)
0x005B 11
0x0063 12
CF (PCA0CN.7)
EPCA0
PPCA0
(EIE1.4)
(EIP1.4)
CCFn (PCA0CN.n)
CP0FIF (CPT0CN.4)
CP0RIF (CPT0CN.5)
ECP0
PCP0
(EIE1.5)
(EIP1.5)
RESERVED
RESERVED
CS0 Conversion Com- 0x007B 15
plete
CS0INT (CS0CN.5)
N
N
N
N
ECSCPT PSCCPT
(EIE2.0) (EIP2.0)
ECSGRT PSCGRT
(EIE2.1) (EIP2.1)
CS0 Greater Than
0x0083
16
CS0CMPF (CS0CN.0)
18.2. Interrupt Register Descriptions
The SFRs used to enable the interrupt sources and set their priority level are described in this section.
Refer to the data sheet section associated with a particular on-chip peripheral for information regarding
valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s).
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SFR Definition 18.1. IE: Interrupt Enable
Bit
7
6
5
4
3
2
1
0
EA
ESPI0
ET2
ES0
ET1
EX1
ET0
EX0
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Address = 0xA8; Bit-Addressable
Bit
Name
Function
7
EA
Enable All Interrupts.
Globally enables/disables all interrupts. It overrides individual interrupt mask settings.
0: Disable all interrupt sources.
1: Enable each interrupt according to its individual mask setting.
6
5
4
3
2
1
0
ESPI0 Enable Serial Peripheral Interface (SPI0) Interrupt.
This bit sets the masking of the SPI0 interrupts.
0: Disable all SPI0 interrupts.
1: Enable interrupt requests generated by SPI0.
ET2
ES0
ET1
EX1
ET0
EX0
Enable Timer 2 Interrupt.
This bit sets the masking of the Timer 2 interrupt.
0: Disable Timer 2 interrupt.
1: Enable interrupt requests generated by the TF2L or TF2H flags.
Enable UART0 Interrupt.
This bit sets the masking of the UART0 interrupt.
0: Disable UART0 interrupt.
1: Enable UART0 interrupt.
Enable Timer 1 Interrupt.
This bit sets the masking of the Timer 1 interrupt.
0: Disable all Timer 1 interrupt.
1: Enable interrupt requests generated by the TF1 flag.
Enable External Interrupt 1.
This bit sets the masking of External Interrupt 1.
0: Disable external interrupt 1.
1: Enable interrupt requests generated by the INT1 input.
Enable Timer 0 Interrupt.
This bit sets the masking of the Timer 0 interrupt.
0: Disable all Timer 0 interrupt.
1: Enable interrupt requests generated by the TF0 flag.
Enable External Interrupt 0.
This bit sets the masking of External Interrupt 0.
0: Disable external interrupt 0.
1: Enable interrupt requests generated by the INT0 input.
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SFR Definition 18.2. IP: Interrupt Priority
Bit
7
6
5
4
3
2
1
0
PSPI0
PT2
PS0
PT1
PX1
PT0
PX0
Name
Type
Reset
R
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Address = 0xB8; Bit-Addressable
Bit
Name
Function
7
Unused Read = 1b, Write = Don't Care.
6
PSPI0
PT2
PS0
PT1
PX1
PT0
PX0
Serial Peripheral Interface (SPI0) Interrupt Priority Control.
This bit sets the priority of the SPI0 interrupt.
0: SPI0 interrupt set to low priority level.
1: SPI0 interrupt set to high priority level.
5
4
3
2
1
0
Timer 2 Interrupt Priority Control.
This bit sets the priority of the Timer 2 interrupt.
0: Timer 2 interrupt set to low priority level.
1: Timer 2 interrupt set to high priority level.
UART0 Interrupt Priority Control.
This bit sets the priority of the UART0 interrupt.
0: UART0 interrupt set to low priority level.
1: UART0 interrupt set to high priority level.
Timer 1 Interrupt Priority Control.
This bit sets the priority of the Timer 1 interrupt.
0: Timer 1 interrupt set to low priority level.
1: Timer 1 interrupt set to high priority level.
External Interrupt 1 Priority Control.
This bit sets the priority of the External Interrupt 1 interrupt.
0: External Interrupt 1 set to low priority level.
1: External Interrupt 1 set to high priority level.
Timer 0 Interrupt Priority Control.
This bit sets the priority of the Timer 0 interrupt.
0: Timer 0 interrupt set to low priority level.
1: Timer 0 interrupt set to high priority level.
External Interrupt 0 Priority Control.
This bit sets the priority of the External Interrupt 0 interrupt.
0: External Interrupt 0 set to low priority level.
1: External Interrupt 0 set to high priority level.
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SFR Definition 18.3. EIE1: Extended Interrupt Enable 1
Bit
7
6
5
4
3
2
1
0
Reserved Reserved
ECP0
EADC0
EPCA0
EWADC0
EMAT
ESMB0
Name
Type
Reset
W
0
W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Address = 0xE6
Bit
Name
Function
7
Reserved Must write 0.
Reserved Reserved.
Must write 0.
6
5
4
3
2
1
0
ECP0
Enable Comparator0 (CP0) Interrupt.
This bit sets the masking of the CP0 rising edge or falling edge interrupt.
0: Disable CP0 interrupts.
1: Enable interrupt requests generated by the CP0RIF and CP0FIF flags.
EADC0 Enable ADC0 Conversion Complete Interrupt.
This bit sets the masking of the ADC0 Conversion Complete interrupt.
0: Disable ADC0 Conversion Complete interrupt.
1: Enable interrupt requests generated by the AD0INT flag.
EPCA0 Enable Programmable Counter Array (PCA0) Interrupt.
This bit sets the masking of the PCA0 interrupts.
0: Disable all PCA0 interrupts.
1: Enable interrupt requests generated by PCA0.
EWADC0 Enable Window Comparison ADC0 interrupt.
This bit sets the masking of ADC0 Window Comparison interrupt.
0: Disable ADC0 Window Comparison interrupt.
1: Enable interrupt requests generated by ADC0 Window Compare flag (AD0WINT).
EMAT
Enable Port Match Interrupts.
This bit sets the masking of the Port Match event interrupt.
0: Disable all Port Match interrupts.
1: Enable interrupt requests generated by a Port Match.
ESMB0 Enable SMBus (SMB0) Interrupt.
This bit sets the masking of the SMB0 interrupt.
0: Disable all SMB0 interrupts.
1: Enable interrupt requests generated by SMB0.
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SFR Definition 18.4. EIE2: Extended Interrupt Enable 2
Bit
7
6
5
4
3
2
1
0
ECSGRT ECSCPT
Name
Type
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
SFR Address = 0xE7
Bit
7:2
1
Name
Function
Unused Read = 000000b; Write = don’t care.
ECSGRT Enable Capacitive Sense Greater Than Comparator Interrupt.
0: Disable Capacitive Sense Greater Than Comparator interrupt.
1: Enable interrupt requests generated by CS0CMPF.
0
ECSCPT Enable Capacitive Sense Conversion Complete Interrupt.
0: Disable Capacitive Sense Conversion Complete interrupt.
1: Enable interrupt requests generated by CS0INT.
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SFR Definition 18.5. EIP1: Extended Interrupt Priority 1
Bit
7
6
5
4
3
2
1
0
Reserved Reserved
PCP0
PPCA0
PADC0
PWADC0
PMAT
PSMB0
Name
Type
Reset
W
0
W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Address = 0xF3
Bit Name
7:6 Reserved Must write 0.
PCP0 Comparator0 (CP0) Interrupt Priority Control.
Function
5
4
3
2
1
0
This bit sets the priority of the CP0 rising edge or falling edge interrupt.
0: CP0 interrupt set to low priority level.
1: CP0 interrupt set to high priority level.
PPCA0 Programmable Counter Array (PCA0) Interrupt Priority Control.
This bit sets the priority of the PCA0 interrupt.
0: PCA0 interrupt set to low priority level.
1: PCA0 interrupt set to high priority level.
PADC0 ADC0 Conversion Complete Interrupt Priority Control.
This bit sets the priority of the ADC0 Conversion Complete interrupt.
0: ADC0 Conversion Complete interrupt set to low priority level.
1: ADC0 Conversion Complete interrupt set to high priority level.
PWADC0 ADC0 Window Comparator Interrupt Priority Control.
This bit sets the priority of the ADC0 Window interrupt.
0: ADC0 Window interrupt set to low priority level.
1: ADC0 Window interrupt set to high priority level.
PMAT
Port Match Interrupt Priority Control.
This bit sets the priority of the Port Match Event interrupt.
0: Port Match interrupt set to low priority level.
1: Port Match interrupt set to high priority level.
PSMB0 SMBus (SMB0) Interrupt Priority Control.
This bit sets the priority of the SMB0 interrupt.
0: SMB0 interrupt set to low priority level.
1: SMB0 interrupt set to high priority level.
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SFR Definition 18.6. EIP2: Extended Interrupt Priority 2
Bit
7
6
5
4
3
2
1
0
Reserved Reserved Reserved Reserved Reserved Reserved PSCGRT PSCCPT
Name
Type
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
SFR Address = 0xF4
Bit Name
7:2 Reserved
Function
1
PSCGRT Capacitive Sense Greater Than Comparator Priority Control.
This bit sets the priority of the Capacitive Sense Greater Than Comparator interrupt.
0: CS0 Greater Than Comparator interrupt set to low priority level.
1: CS0 Greater Than Comparator set to high priority level.
0
PSCCPT Capacitive Sense Conversion Complete Priority Control.
This bit sets the priority of the Capacitive Sense Conversion Complete interrupt.
0: CS0 Conversion Complete set to low priority level.
1: CS0 Conversion Complete set to high priority level.
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18.3. INT0 and INT1 External Interrupts
The INT0 and INT1 external interrupt sources are configurable as active high or low, edge or level sensi-
tive. The IN0PL (INT0 Polarity) and IN1PL (INT1 Polarity) bits in the IT01CF register select active high or
active low; the IT0 and IT1 bits in TCON (Section “28.1. Timer 0 and Timer 1” on page 211) select level or
edge sensitive. The table below lists the possible configurations.
IT0
IN0PL
INT0 Interrupt
IT1
IN1PL
INT1 Interrupt
1
1
0
0
0
1
0
1
Active low, edge sensitive
Active high, edge sensitive
Active low, level sensitive
Active high, level sensitive
1
1
0
0
0
1
0
1
Active low, edge sensitive
Active high, edge sensitive
Active low, level sensitive
Active high, level sensitive
INT0 and INT1 are assigned to Port pins as defined in the IT01CF register (see SFR Definition 18.7). Note
that INT0 and INT0 Port pin assignments are independent of any Crossbar assignments. INT0 and INT1
will monitor their assigned Port pins without disturbing the peripheral that was assigned the Port pin via the
Crossbar. To assign a Port pin only to INT0 and/or INT1, configure the Crossbar to skip the selected pin(s).
This is accomplished by setting the associated bit in register XBR0 (see Section “23.3. Priority Crossbar
Decoder” on page 143 for complete details on configuring the Crossbar).
IE0 (TCON.1) and IE1 (TCON.3) serve as the interrupt-pending flags for the INT0 and INT1 external inter-
rupts, respectively. If an INT0 or INT1 external interrupt is configured as edge-sensitive, the corresponding
interrupt-pending flag is automatically cleared by the hardware when the CPU vectors to the ISR. When
configured as level sensitive, the interrupt-pending flag remains logic 1 while the input is active as defined
by the corresponding polarity bit (IN0PL or IN1PL); the flag remains logic 0 while the input is inactive. The
external interrupt source must hold the input active until the interrupt request is recognized. It must then
deactivate the interrupt request before execution of the ISR completes or another interrupt request will be
generated.
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C8051F80x-83x
SFR Definition 18.7. IT01CF: INT0/INT1 Configuration
Bit
7
6
5
4
3
2
1
0
IN1PL
IN1SL[2:0]
IN0PL
IN0SL[2:0]
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
0
0
0
1
SFR Address = 0xE4
Bit
Name
Function
7
IN1PL
INT1 Polarity.
0: INT1 input is active low.
1: INT1 input is active high.
6:4 IN1SL[2:0]
INT1 Port Pin Selection Bits.
These bits select which Port pin is assigned to INT1. Note that this pin assignment is
independent of the Crossbar; INT1 will monitor the assigned Port pin without disturb-
ing the peripheral that has been assigned the Port pin via the Crossbar. The Crossbar
will not assign the Port pin to a peripheral if it is configured to skip the selected pin.
000: Select P0.0
001: Select P0.1
010: Select P0.2
011: Select P0.3
100: Select P0.4
101: Select P0.5
110: Select P0.6
111: Select P0.7
3
IN0PL
INT0 Polarity.
0: INT0 input is active low.
1: INT0 input is active high.
2:0 IN0SL[2:0]
INT0 Port Pin Selection Bits.
These bits select which Port pin is assigned to INT0. Note that this pin assignment is
independent of the Crossbar; INT0 will monitor the assigned Port pin without disturb-
ing the peripheral that has been assigned the Port pin via the Crossbar. The Crossbar
will not assign the Port pin to a peripheral if it is configured to skip the selected pin.
000: Select P0.0
001: Select P0.1
010: Select P0.2
011: Select P0.3
100: Select P0.4
101: Select P0.5
110: Select P0.6
111: Select P0.7
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19. Flash Memory
On-chip, re-programmable Flash memory is included for program code and non-volatile data storage. The
Flash memory can be programmed in-system through the C2 interface or by software using the MOVX
write instruction. Once cleared to logic 0, a Flash bit must be erased to set it back to logic 1. Flash bytes
would typically be erased (set to 0xFF) before being reprogrammed. The write and erase operations are
automatically timed by hardware for proper execution; data polling to determine the end of the write/erase
operations is not required. Code execution is stalled during Flash write/erase operations. Refer to
Table 7.6 for complete Flash memory electrical characteristics.
19.1. Programming The Flash Memory
The simplest means of programming the Flash memory is through the C2 interface using programming
tools provided by Silicon Laboratories or a third party vendor. This is the only means for programming a
non-initialized device. For details on the C2 commands to program Flash memory, see Section “30. C2
Interface” on page 244.
The Flash memory can be programmed by software using the MOVX write instruction with the address and
data byte to be programmed provided as normal operands. Before programming Flash memory using
MOVX, Flash programming operations must be enabled by: (1) setting the PSWE Program Store Write
Enable bit (PSCTL.0) to logic 1 (this directs the MOVX writes to target Flash memory); and (2) Writing the
Flash key codes in sequence to the Flash Lock register (FLKEY). The PSWE bit remains set until cleared
by software. For detailed guidelines on programming Flash from firmware, please see Section “19.4. Flash
Write and Erase Guidelines” on page 115.
Note: A minimum SYSCLK frequency is required for writing or erasing Flash memory, as detailed in “7. Electrical
Characteristics” on page 39.
To ensure the integrity of the Flash contents, the on-chip VDD Monitor must be enabled and enabled as a
reset source in any system that includes code that writes and/or erases Flash memory from software. Fur-
thermore, there should be no delay between enabling the V Monitor and enabling the V Monitor as a
DD
DD
reset source. Any attempt to write or erase Flash memory while the V
Monitor is disabled, or not
DD
enabled as a reset source, will cause a Flash Error device reset.
19.1.1. Flash Lock and Key Functions
Flash writes and erases by user software are protected with a lock and key function. The Flash Lock and
Key Register (FLKEY) must be written with the correct key codes, in sequence, before Flash operations
may be performed. The key codes are: 0xA5, 0xF1. The timing does not matter, but the codes must be
written in order. If the key codes are written out of order, or the wrong codes are written, Flash writes and
erases will be disabled until the next system reset. Flash writes and erases will also be disabled if a Flash
write or erase is attempted before the key codes have been written properly. The Flash lock resets after
each write or erase; the key codes must be written again before a following Flash operation can be per-
formed. The FLKEY register is detailed in SFR Definition 19.2.
19.1.2. Flash Erase Procedure
The Flash memory is organized in 512-byte pages. The erase operation applies to an entire page (setting
all bytes in the page to 0xFF). To erase an entire 512-byte page, perform the following steps:
1. Save current interrupt state and disable interrupts.
2. Set the PSEE bit (register PSCTL).
3. Set the PSWE bit (register PSCTL).
4. Write the first key code to FLKEY: 0xA5.
5. Write the second key code to FLKEY: 0xF1.
6. Using the MOVX instruction, write a data byte to any location within the 512-byte page to be erased.
7. Clear the PSWE and PSEE bits.
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8. Restore previous interrupt state.
Steps 4–6 must be repeated for each 512-byte page to be erased.
Note: Flash security settings may prevent erasure of some Flash pages, such as the reserved area and the page
containing the lock bytes. For a summary of Flash security settings and restrictions affecting Flash erase
operations, please see Section “19.3. Security Options” on page 114.
19.1.3. Flash Write Procedure
A write to Flash memory can clear bits to logic 0 but cannot set them; only an erase operation can set bits
to logic 1 in Flash. A byte location to be programmed should be erased before a new value is written.
The recommended procedure for writing a single byte in Flash is as follows:
1. Save current interrupt state and disable interrupts.
2. Ensure that the Flash byte has been erased (has a value of 0xFF).
3. Set the PSWE bit (register PSCTL).
4. Clear the PSEE bit (register PSCTL).
5. Write the first key code to FLKEY: 0xA5.
6. Write the second key code to FLKEY: 0xF1.
7. Using the MOVX instruction, write a single data byte to the desired location within the 512-byte sector.
8. Clear the PSWE bit.
9. Restore previous interrupt state.
Steps 5–7 must be repeated for each byte to be written.
Note: Flash security settings may prevent writes to some areas of Flash, such as the reserved area. For a summary
of Flash security settings and restrictions affecting Flash write operations, please see Section “19.3. Security
Options” on page 114.
19.2. Non-volatile Data Storage
The Flash memory can be used for non-volatile data storage as well as program code. This allows data
such as calibration coefficients to be calculated and stored at run time. Data is written using the MOVX
write instruction and read using the MOVC instruction.
Note: MOVX read instructions always target XRAM.
19.3. Security Options
The CIP-51 provides security options to protect the Flash memory from inadvertent modification by soft-
ware as well as to prevent the viewing of proprietary program code and constants. The Program Store
Write Enable (bit PSWE in register PSCTL) and the Program Store Erase Enable (bit PSEE in register
PSCTL) bits protect the Flash memory from accidental modification by software. PSWE must be explicitly
set to 1 before software can modify the Flash memory; both PSWE and PSEE must be set to 1 before soft-
ware can erase Flash memory. Additional security features prevent proprietary program code and data
constants from being read or altered across the C2 interface.
A Security Lock Byte located at the last byte of Flash user space offers protection of the Flash program
memory from access (reads, writes, and erases) by unprotected code or the C2 interface. The Flash secu-
rity mechanism allows the user to lock all Flash pages, starting at page 0, by writing a non-0xFF value to
the lock byte. Note that writing a non-0xFF value to the lock byte will lock all pages of FLASH from
reads, writes, and erases, including the page containing the lock byte.
The level of Flash security depends on the Flash access method. The three Flash access methods that
can be restricted are reads, writes, and erases from the C2 debug interface, user firmware executing on
114
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unlocked pages, and user firmware executing on locked pages. Table 19.1 summarizes the Flash security
features of the C8051F80x-83x devices.
Table 19.1. Flash Security Summary
Action
C2 Debug
Interface
User Firmware executing from:
an unlocked page a locked page
Read, Write or Erase unlocked pages
(except page with Lock Byte)
Permitted
Permitted
Permitted
Permitted
Permitted
Permitted
Permitted
Permitted
FEDR
Read, Write or Erase locked pages
(except page with Lock Byte)
Not Permitted FEDR
Read or Write page containing Lock Byte
(if no pages are locked)
Permitted
Permitted
Read or Write page containing Lock Byte
(if any page is locked)
Not Permitted FEDR
Read contents of Lock Byte
(if no pages are locked)
Permitted
Permitted
Read contents of Lock Byte
(if any page is locked)
Not Permitted FEDR
Erase page containing Lock Byte
(if no pages are locked)
Permitted
FEDR
Erase page containing Lock Byte—Unlock all
pages (if any page is locked)
Only by C2DE FEDR
Not Permitted FEDR
Not Permitted FEDR
Not Permitted FEDR
FEDR
Lock additional pages
(change 1s to 0s in the Lock Byte)
FEDR
Unlock individual pages
(change 0s to 1s in the Lock Byte)
FEDR
Read, Write or Erase Reserved Area
FEDR
C2DE—C2 Device Erase (Erases all Flash pages including the page containing the Lock Byte)
FEDR—Not permitted; Causes Flash Error Device Reset (FERROR bit in RSTSRC is 1 after reset)
All prohibited operations that are performed via the C2 interface are ignored (do not cause device
reset).
Locking any Flash page also locks the page containing the Lock Byte.
Once written to, the Lock Byte cannot be modified except by performing a C2 Device Erase.
If user code writes to the Lock Byte, the Lock does not take effect until the next device reset.
19.4. Flash Write and Erase Guidelines
Any system which contains routines which write or erase Flash memory from software involves some risk
that the write or erase routines will execute unintentionally if the CPU is operating outside its specified
operating range of VDD, system clock frequency, or temperature. This accidental execution of Flash modi-
fying code can result in alteration of Flash memory contents causing a system failure that is only recover-
able by re-Flashing the code in the device.
To help prevent the accidental modification of Flash by firmware, the VDD Monitor must be enabled and
enabled as a reset source on C8051F80x-83x devices for the Flash to be successfully modified. If either
Rev. 1.0
115
C8051F80x-83x
the VDD Monitor or the VDD Monitor reset source is not enabled, a Flash Error Device Reset will be
generated when the firmware attempts to modify the Flash.
The following guidelines are recommended for any system that contains routines which write or erase
Flash from code.
19.4.1. VDD Maintenance and the VDD Monitor
1. If the system power supply is subject to voltage or current "spikes," add sufficient transient protection
devices to the power supply to ensure that the supply voltages listed in the Absolute Maximum Ratings
table are not exceeded.
2. Make certain that the minimum VDD rise time specification of 1 ms is met. If the system cannot meet
this rise time specification, then add an external VDD brownout circuit to the RST pin of the device that
holds the device in reset until VDD reaches the minimum device operating voltage and re-asserts RST
if VDD drops below the minimum device operating voltage.
3. Keep the on-chip VDD Monitor enabled and enable the VDD Monitor as a reset source as early in code
as possible. This should be the first set of instructions executed after the Reset Vector. For C-based
systems, this will involve modifying the startup code added by the C compiler. See your compiler
documentation for more details. Make certain that there are no delays in software between enabling the
VDD Monitor and enabling the VDD Monitor as a reset source. Code examples showing this can be
found in “AN201: Writing to Flash from Firmware," available from the Silicon Laboratories website.
Note: On C8051F80x-83x devices, both the VDD Monitor and the VDD Monitor reset source must be enabled to write
or erase Flash without generating a Flash Error Device Reset.
On C8051F80x-83x devices, both the VDD Monitor and the VDD Monitor reset source are enabled by hardware
after a power-on reset.
4. As an added precaution, explicitly enable the VDD Monitor and enable the VDD Monitor as a reset
source inside the functions that write and erase Flash memory. The VDD Monitor enable instructions
should be placed just after the instruction to set PSWE to a 1, but before the Flash write or erase
operation instruction.
5. Make certain that all writes to the RSTSRC (Reset Sources) register use direct assignment operators
and explicitly DO NOT use the bit-wise operators (such as AND or OR). For example, "RSTSRC =
0x02" is correct, but "RSTSRC |= 0x02" is incorrect.
6. Make certain that all writes to the RSTSRC register explicitly set the PORSF bit to a 1. Areas to check
are initialization code which enables other reset sources, such as the Missing Clock Detector or
Comparator, for example, and instructions which force a Software Reset. A global search on "RSTSRC"
can quickly verify this.
19.4.2. PSWE Maintenance
1. Reduce the number of places in code where the PSWE bit (b0 in PSCTL) is set to a 1. There should be
exactly one routine in code that sets PSWE to a 1 to write Flash bytes and one routine in code that sets
both PSWE and PSEE both to a 1 to erase Flash pages.
2. Minimize the number of variable accesses while PSWE is set to a 1. Handle pointer address updates
and loop maintenance outside the "PSWE = 1;... PSWE = 0;" area. Code examples showing this can be
found in “AN201: Writing to Flash from Firmware," available from the Silicon Laboratories website.
3. Disable interrupts prior to setting PSWE to a 1 and leave them disabled until after PSWE has been
reset to 0. Any interrupts posted during the Flash write or erase operation will be serviced in priority
order after the Flash operation has been completed and interrupts have been re-enabled by software.
4. Make certain that the Flash write and erase pointer variables are not located in XRAM. See your
compiler documentation for instructions regarding how to explicitly locate variables in different memory
areas.
116
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5. Add address bounds checking to the routines that write or erase Flash memory to ensure that a routine
called with an illegal address does not result in modification of the Flash.
19.4.3. System Clock
1. If operating from an external crystal, be advised that crystal performance is susceptible to electrical
interference and is sensitive to layout and to changes in temperature. If the system is operating in an
electrically noisy environment, use the internal oscillator or use an external CMOS clock.
2. If operating from the external oscillator, switch to the internal oscillator during Flash write or erase
operations. The external oscillator can continue to run, and the CPU can switch back to the external
oscillator after the Flash operation has completed.
Additional Flash recommendations and example code can be found in “AN201: Writing to Flash from Firm-
ware," available from the Silicon Laboratories website.
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C8051F80x-83x
SFR Definition 19.1. PSCTL: Program Store R/W Control
Bit
7
6
5
4
3
2
1
0
PSEE
PSWE
Name
Type
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
SFR Address =0x8F
Bit
7:2
1
Name
Unused Read = 000000b, Write = don’t care.
PSEE Program Store Erase Enable.
Function
Setting this bit (in combination with PSWE) allows an entire page of Flash program
memory to be erased. If this bit is logic 1 and Flash writes are enabled (PSWE is logic
1), a write to Flash memory using the MOVX instruction will erase the entire page that
contains the location addressed by the MOVX instruction. The value of the data byte
written does not matter.
0: Flash program memory erasure disabled.
1: Flash program memory erasure enabled.
0
PSWE Program Store Write Enable.
Setting this bit allows writing a byte of data to the Flash program memory using the
MOVX write instruction. The Flash location should be erased before writing data.
0: Writes to Flash program memory disabled.
1: Writes to Flash program memory enabled; the MOVX write instruction targets Flash
memory.
118
Rev. 1.0
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SFR Definition 19.2. FLKEY: Flash Lock and Key
Bit
7
6
5
4
3
2
1
0
FLKEY[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xB7
Bit Name
Function
7:0 FLKEY[7:0] Flash Lock and Key Register.
Write:
This register provides a lock and key function for Flash erasures and writes. Flash
writes and erases are enabled by writing 0xA5 followed by 0xF1 to the FLKEY regis-
ter. Flash writes and erases are automatically disabled after the next write or erase is
complete. If any writes to FLKEY are performed incorrectly, or if a Flash write or erase
operation is attempted while these operations are disabled, the Flash will be perma-
nently
locked from writes or erasures until the next device reset. If an application never
writes to Flash, it can intentionally lock the Flash by writing a non-0xA5 value to
FLKEY from software.
Read:
When read, bits 1–0 indicate the current Flash lock state.
00: Flash is write/erase locked.
01: The first key code has been written (0xA5).
10: Flash is unlocked (writes/erases allowed).
11: Flash writes/erases disabled until the next reset.
Rev. 1.0
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C8051F80x-83x
20. Power Management Modes
The C8051F80x-83x devices have three software programmable power management modes: Idle, Stop,
and Suspend. Idle mode and Stop mode are part of the standard 8051 architecture, while Suspend mode
is an enhanced power-saving mode implemented by the high-speed oscillator peripheral.
Idle mode halts the CPU while leaving the peripherals and clocks active. In Stop mode, the CPU is halted,
all interrupts and timers (except the Missing Clock Detector) are inactive, and the internal oscillator is
stopped (analog peripherals remain in their selected states; the external oscillator is not affected). Sus-
pend mode is similar to Stop mode in that the internal oscillator and CPU are halted, but the device can
wake on events such as a Port Mismatch, Comparator low output, or a Timer 3 overflow. Since clocks are
running in Idle mode, power consumption is dependent upon the system clock frequency and the number
of peripherals left in active mode before entering Idle. Stop mode and Suspend mode consume the least
power because the majority of the device is shut down with no clocks active. SFR Definition 20.1 describes
the Power Control Register (PCON) used to control the C8051F80x-83x's Stop and Idle power manage-
ment modes. Suspend mode is controlled by the SUSPEND bit in the OSCICN register (SFR Definition
22.3).
Although the C8051F80x-83x has Idle, Stop, and Suspend modes available, more control over the device
power can be achieved by enabling/disabling individual peripherals as needed. Each analog peripheral
can be disabled when not in use and placed in low power mode. Digital peripherals, such as timers or
serial buses, draw little power when they are not in use. Turning off oscillators lowers power consumption
considerably, at the expense of reduced functionality.
20.1. Idle Mode
Setting the Idle Mode Select bit (PCON.0) causes the hardware to halt the CPU and enter Idle mode as
soon as the instruction that sets the bit completes execution. All internal registers and memory maintain
their original data. All analog and digital peripherals can remain active during Idle mode.
Idle mode is terminated when an enabled interrupt is asserted or a reset occurs. The assertion of an
enabled interrupt will cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU to resume
operation. The pending interrupt will be serviced and the next instruction to be executed after the return
from interrupt (RETI) will be the instruction immediately following the one that set the Idle Mode Select bit.
If Idle mode is terminated by an internal or external reset, the CIP-51 performs a normal reset sequence
and begins program execution at address 0x0000.
Note: If the instruction following the write of the IDLE bit is a single-byte instruction and an interrupt occurs during the
execution phase of the instruction that sets the IDLE bit, the CPU may not wake from Idle mode when a future
interrupt occurs. Therefore, instructions that set the IDLE bit should be followed by an instruction that has two
or more opcode bytes, for example:
// in ‘C’:
PCON |= 0x01;
PCON = PCON;
// set IDLE bit
// ... followed by a 3-cycle dummy instruction
; in assembly:
ORL PCON, #01h
MOV PCON, PCON
; set IDLE bit
; ... followed by a 3-cycle dummy instruction
If enabled, the Watchdog Timer (WDT) will eventually cause an internal watchdog reset and thereby termi-
nate the Idle mode. This feature protects the system from an unintended permanent shutdown in the event
of an inadvertent write to the PCON register. If this behavior is not desired, the WDT may be disabled by
software prior to entering the Idle mode if the WDT was initially configured to allow this operation. This pro-
vides the opportunity for additional power savings, allowing the system to remain in the Idle mode indefi-
nitely, waiting for an external stimulus to wake up the system. Refer to Section “29.4. Watchdog Timer
Mode” on page 236 for more information on the use and configuration of the WDT.
120
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C8051F80x-83x
20.2. Stop Mode
Setting the Stop Mode Select bit (PCON.1) causes the controller core to enter Stop mode as soon as the
instruction that sets the bit completes execution. In Stop mode the internal oscillator, CPU, and all digital
peripherals are stopped; the state of the external oscillator circuit is not affected. Each analog peripheral
(including the external oscillator circuit) may be shut down individually prior to entering Stop Mode. Stop
mode can only be terminated by an internal or external reset. On reset, the device performs the normal
reset sequence and begins program execution at address 0x0000.
If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode.
The Missing Clock Detector should be disabled if the CPU is to be put to in STOP mode for longer than the
MCD timeout of 100 µs.
20.3. Suspend Mode
Suspend mode allows a system running from the internal oscillator to go to a very low power state similar
to Stop mode, but the processor can be awakened by certain events without requiring a reset of the device.
Setting the SUSPEND bit (OSCICN.5) causes the hardware to halt the CPU and the high-frequency inter-
nal oscillator, and go into Suspend mode as soon as the instruction that sets the bit completes execution.
All internal registers and memory maintain their original data. Most digital peripherals are not active in Sus-
pend mode. The exception to this is the Port Match feature and Timer 3, when it is run from an external
oscillator source.
The clock divider bits CLKDIV[2:0] in register CLKSEL must be set to "divide by 1" when entering suspend
mode.
Suspend mode can be terminated by five types of events, a port match (described in Section “23.5. Port
Match” on page 150), a Timer 2 overflow (described in Section “28.2. Timer 2” on page 219), a comparator
low output (if enabled), a capacitive sense greater-than comparator event, or a device reset event. In order
to run Timer 3 in suspend mode, the timer must be configured to clock from the external clock source.
When suspend mode is terminated, the device will continue execution on the instruction following the one
that set the SUSPEND bit. If the wake event (port match or Timer 2 overflow) was configured to generate
an interrupt, the interrupt will be serviced upon waking the device. If suspend mode is terminated by an
internal or external reset, the CIP-51 performs a normal reset sequence and begins program execution at
address 0x0000.
Note: The device will still enter suspend mode if a wake source is "pending", and the device will not wake on such
pending sources. It is important to ensure that the intended wake source will trigger after the device enters
suspend mode. For example, if a CS0 conversion completes and the interrupt fires before the device is in
suspend mode, that interrupt cannot trigger the wake event. Because port match events are level-sensitive,
pre-existing port match events will trigger a wake, as long as the match condition is still present when the
device enters suspend.
Rev. 1.0
121
C8051F80x-83x
SFR Definition 20.1. PCON: Power Control
Bit
7
6
5
4
3
2
1
0
GF[5:0]
R/W
STOP
IDLE
Name
Type
Reset
R/W
0
R/W
0
0
0
0
0
0
0
SFR Address = 0x87
Bit
Name
Function
7:2
GF[5:0]
General Purpose Flags 5–0.
These are general purpose flags for use under software control.
1
0
STOP
IDLE
Stop Mode Select.
Setting this bit will place the CIP-51 in Stop mode. This bit will always be read as 0.
1: CPU goes into Stop mode (internal oscillator stopped).
IDLE: Idle Mode Select.
Setting this bit will place the CIP-51 in Idle mode. This bit will always be read as 0.
1: CPU goes into Idle mode. (Shuts off clock to CPU, but clock to Timers, Interrupts,
Serial Ports, and Analog Peripherals are still active.)
122
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C8051F80x-83x
21. Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this
reset state, the following occur:
CIP-51 halts program execution
Special Function Registers (SFRs) are initialized to their defined reset values
External Port pins are forced to a known state
Interrupts and timers are disabled.
All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal
data memory are unaffected during a reset; any previously stored data is preserved. However, since the
stack pointer SFR is reset, the stack is effectively lost, even though the data on the stack is not altered.
The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pullups are enabled dur-
ing and after the reset. For V
Monitor and power-on resets, the RST pin is driven low until the device
DD
exits the reset state.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the inter-
nal oscillator. The Watchdog Timer is enabled with the system clock divided by 12 as its clock source. Pro-
gram execution begins at location 0x0000.
VDD
Power On
Reset
Supply
Monitor
+
-
'0'
RST
Enable
Comparator 0
(wired-OR)
Px.x
Px.x
+
-
C0RSEF
Missing
Clock
Detector
(one-
shot)
Reset
Funnel
PCA
WDT
(Software Reset)
EN
SWRSF
EN
Errant
FLASH
Operation
System
Clock
CIP-51
System Reset
Microcontroller
Core
Extended Interrupt
Handler
Figure 21.1. Reset Sources
Rev. 1.0
123
C8051F80x-83x
21.1. Power-On Reset
During power-up, the device is held in a reset state and the RST pin is driven low until V settles above
DD
V
. A delay occurs before the device is released from reset; the delay decreases as the V ramp time
DD
RST
increases (V
ramp time is defined as how fast V
ramps from 0 V to V ). Figure 21.2. plots the
RST
DD
DD
power-on and V
monitor reset timing. The maximum V
ramp time is 1 ms; slower ramp times may
DD
DD
cause the device to be released from reset before V reaches the V
level. For ramp times less than
DD
RST
1 ms, the power-on reset delay (T
) is typically less than 10 ms.
PORDelay
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000) software can
read the PORSF flag to determine if a power-up was the cause of reset. The content of internal data mem-
ory should be assumed to be undefined after a power-on reset. The V monitor is enabled and selected
DD
as a reset source following a power-on reset.
VDD
VRST
t
RST
Logic HIGH
TPORDelay
Logic LOW
VDD
Power-On
Reset
Monitor
Reset
Figure 21.2. Power-On and VDD Monitor Reset Timing
124
Rev. 1.0
C8051F80x-83x
21.2. Power-Fail Reset / V Monitor
DD
When a power-down transition or power irregularity causes V
to drop below V , the power supply
RST
DD
monitor will drive the RST pin low and hold the CIP-51 in a reset state (see Figure 21.2). When V returns
DD
to a level above V
, the CIP-51 will be released from the reset state. Even though internal data memory
RST
contents are not altered by the power-fail reset, it is impossible to determine if V dropped below the level
DD
required for data retention. If the PORSF flag reads 1, the data may no longer be valid. The V monitor is
DD
enabled and selected as a reset source after power-on resets. Its defined state (enabled/disabled) is not
altered by any other reset source. For example, if the V monitor is disabled by code and a software reset
DD
is performed, the V monitor will still be disabled after the reset.
DD
Important Note: If the V monitor is being turned on from a disabled state, it should be enabled before it
DD
is selected as a reset source. Selecting the V monitor as a reset source before it is enabled and stabi-
DD
lized may cause a system reset. In some applications, this reset may be undesirable. If this is not desirable
in the application, a delay should be introduced between enabling the monitor and selecting it as a reset
source. The procedure for enabling the V monitor and configuring it as a reset source from a disabled
DD
state is shown below:
1. Enable the V monitor (VDMEN bit in VDM0CN = 1).
DD
2. If necessary, wait for the V monitor to stabilize.
DD
3. Select the V monitor as a reset source (PORSF bit in RSTSRC = 1).
DD
See Figure 21.2 for V
monitor timing; note that the power-on-reset delay is not incurred after a V
DD
DD
monitor reset. See Section “7. Electrical Characteristics” on page 39 for complete electrical characteristics
of the V monitor.
DD
Rev. 1.0
125
C8051F80x-83x
SFR Definition 21.1. VDM0CN: V Monitor Control
DD
Bit
7
6
5
4
3
2
1
0
Name VDMEN VDDSTAT
Type
R/W
R
R
R
R
R
R
R
Reset
Varies
Varies
Varies
Varies
Varies
Varies
Varies
Varies
SFR Address = 0xFF
Bit
Name
Function
7
VDMEN
V
Monitor Enable.
DD
This bit turns the V monitor circuit on/off. The V Monitor cannot generate sys-
DD
DD
tem resets until it is also selected as a reset source in register RSTSRC (SFR Def-
inition 21.2). Selecting the V monitor as a reset source before it has stabilized
DD
may generate a system reset. In systems where this reset would be undesirable, a
delay should be introduced between enabling the V Monitor and selecting it as a
DD
reset source. After a power-on reset, the VDD monitor is enabled, and this bit will
read 1. The state of this bit is sticky through any other reset source.
0: V Monitor Disabled.
DD
1: V Monitor Enabled.
DD
6
VDDSTAT
Unused
V
Status.
DD
This bit indicates the current power supply status (V Monitor output).
0: V is at or below the V monitor threshold.
1: V is above the V monitor threshold.
DD
DD
DD
DD
DD
5:0
Read = Varies; Write = Don’t care.
21.3. External Reset
The external RST pin provides a means for external circuitry to force the device into a reset state. Assert-
ing an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST
pin may be necessary to avoid erroneous noise-induced resets. See Section “7. Electrical Characteristics”
on page 39 for complete RST pin specifications. The PINRSF flag (RSTSRC.0) is set on exit from an exter-
nal reset.
21.4. Missing Clock Detector Reset
The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system
clock remains high or low for more than the MCD timeout, the one-shot will time out and generate a reset.
After a MCD reset, the MCDRSF flag (RSTSRC.2) will read 1, signifying the MCD as the reset source; oth-
erwise, this bit reads 0. Writing a 1 to the MCDRSF bit enables the Missing Clock Detector; writing a 0 dis-
ables it. The state of the RST pin is unaffected by this reset.
126
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C8051F80x-83x
21.5. Comparator0 Reset
Comparator0 can be configured as a reset source by writing a 1 to the C0RSEF flag (RSTSRC.5).
Comparator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on
chatter on the output from generating an unwanted reset. The Comparator0 reset is active-low: if the non-
inverting input voltage (on CP0+) is less than the inverting input voltage (on CP0-), the device is put into
the reset state. After a Comparator0 reset, the C0RSEF flag (RSTSRC.5) will read 1 signifying
Comparator0 as the reset source; otherwise, this bit reads 0. The state of the RST pin is unaffected by this
reset.
21.6. PCA Watchdog Timer Reset
The programmable Watchdog Timer (WDT) function of the Programmable Counter Array (PCA) can be
used to prevent software from running out of control during a system malfunction. The PCA WDT function
can be enabled or disabled by software as described in Section “29.4. Watchdog Timer Mode” on
page 236; the WDT is enabled and clocked by SYSCLK / 12 following any reset. If a system malfunction
prevents user software from updating the WDT, a reset is generated and the WDTRSF bit (RSTSRC.5) is
set to ‘1’. The state of the RST pin is unaffected by this reset.
21.7. Flash Error Reset
If a Flash read/write/erase or program read targets an illegal address, a system reset is generated. This
may occur due to any of the following:
A Flash write or erase is attempted above user code space. This occurs when PSWE is set to 1 and a
MOVX write operation targets an address above address 0x3DFF.
A Flash read is attempted above user code space. This occurs when a MOVC operation targets an
address above address 0x3DFF.
A Program read is attempted above user code space. This occurs when user code attempts to branch
to an address above 0x3DFF.
A Flash read, write or erase attempt is restricted due to a Flash security setting (see Section
“19.3. Security Options” on page 114).
The FERROR bit (RSTSRC.6) is set following a Flash error reset. The state of the RST pin is unaffected by
this reset.
21.8. Software Reset
Software may force a reset by writing a 1 to the SWRSF bit (RSTSRC.4). The SWRSF bit will read 1 fol-
lowing a software forced reset. The state of the RST pin is unaffected by this reset.
Rev. 1.0
127
C8051F80x-83x
SFR Definition 21.2. RSTSRC: Reset Source
Bit
7
6
5
4
3
2
1
0
FERROR C0RSEF
SWRSF WDTRSF MCDRSF
PORSF
PINRSF
Name
Type
Reset
R
0
R
R/W
R/W
R
R/W
R/W
R
Varies
Varies
Varies
Varies
Varies
Varies
Varies
SFR Address = 0xEF
Bit
Name
Unused Unused.
FERROR Flash Error Reset Flag.
Description
Write
Read
7
Don’t care.
N/A
0
6
Set to 1 if Flash
read/write/erase error
caused the last reset.
5
4
3
2
C0RSEF Comparator0 Reset Enable Writing a 1 enables
Set to 1 if Comparator0
caused the last reset.
and Flag.
Comparator0 as a reset
source (active-low).
SWRSF Software Reset Force and
Writing a 1 forces a sys-
tem reset.
Set to 1 if last reset was
caused by a write to
SWRSF.
Flag.
WDTRSF Watchdog Timer Reset Flag. N/A
Set to 1 if Watchdog Timer
overflow caused the last
reset.
MCDRSF Missing Clock Detector
Writing a 1 enables the
Missing Clock Detector.
Set to 1 if Missing Clock
Detector timeout caused
Enable and Flag.
The MCD triggers a reset the last reset.
if a missing clock condition
is detected.
1
PORSF Power-On / V Monitor
Writing a 1 enables the
monitor as a reset
source.
Set to 1 anytime a power-
DD
V
on or V monitor reset
Reset Flag, and V monitor
DD
DD
DD
occurs.
When set to 1 all other
Reset Enable.
Writing 1 to this bit
before the V monitor RSTSRC flags are inde-
DD
is enabled and stabilized terminate.
may cause a system
reset.
0
PINRSF HW Pin Reset Flag.
N/A
Set to 1 if RST pin caused
the last reset.
Note: Do not use read-modify-write operations on this register
128
Rev. 1.0
C8051F80x-83x
22. Oscillators and Clock Selection
C8051F80x-83x devices include a programmable internal high-frequency oscillator and an external oscilla-
tor drive circuit. The internal high-frequency oscillator can be enabled/disabled and calibrated using the
OSCICN and OSCICL registers, as shown in Figure 22.1. The system clock can be sourced by the exter-
nal oscillator circuit or the internal oscillator (default). The internal oscillator offers a selectable post-scaling
feature, which is initially set to divide the clock by 8.
Option 2 – RC Mode
OSCICL
OSCICN
CLKSEL
VDD
XTAL2
ProgrammableEN
Internal Clock
Generator
Option 4 – CMOS Mode
XTAL2
CLKRDY
SYSCLK
n
Clock Divider
n
Option 1 – Crystal Mode
XTAL1
Clock Divider
Input
Circuit
10M
OSC
XTAL2
Option 3 – C Mode
XTAL2
OSCXCN
Figure 22.1. Oscillator Options
22.1. System Clock Selection
The system clock source for the MCU can be selected using the CLKSEL register. The clock selected as
the system clock can be divided by 1, 2, 4, 8, 16, 32, 64, or 128. When switching between two clock divide
values, the transition may take up to 128 cycles of the undivided clock source. The CLKRDY flag can be
polled to determine when the new clock divide value has been applied. The clock divider must be set to
"divide by 1" when entering Suspend mode. The system clock source may also be switched on-the-fly. The
switchover takes effect after one clock period of the slower oscillator.
Rev. 1.0
129
C8051F80x-83x
SFR Definition 22.1. CLKSEL: Clock Select
Bit
7
6
5
4
3
2
1
0
Name CLKRDY
CLKDIV[2:0]
CLKSEL[2:0]
Type
R
0
R/W
0
R/W
0
R/W
0
R
0
R/W
0
R/W
0
R/W
0
Reset
SFR Address = 0xA9
Bit
Name
Function
7
CLKRDY
System Clock Divider Clock Ready Flag.
0: The selected clock divide setting has not been applied to the system clock.
1: The selected clock divide setting has been applied to the system clock.
6:4
CLKDIV
System Clock Divider Bits.
Selects the clock division to be applied to the selected source (internal or external).
000: Selected clock is divided by 1.
001: Selected clock is divided by 2.
010: Selected clock is divided by 4.
011: Selected clock is divided by 8.
100: Selected clock is divided by 16.
101: Selected clock is divided by 32.
110: Selected clock is divided by 64.
111: Selected clock is divided by 128.
3
Unused
Read = 0b. Must write 0b.
2:0 CLKSEL[2:0] System Clock Select.
Selects the oscillator to be used as the undivided system clock source.
000: Internal Oscillator
001: External Oscillator
All other values reserved.
130
Rev. 1.0
C8051F80x-83x
22.2. Programmable Internal High-Frequency (H-F) Oscillator
All C8051F80x-83x devices include a programmable internal high-frequency oscillator that defaults as the
system clock after a system reset. The internal oscillator period can be adjusted via the OSCICL register
as defined by SFR Definition 22.2.
On C8051F80x-83x devices, OSCICL is factory calibrated to obtain a 24.5 MHz base frequency.
The internal oscillator output frequency may be divided by 1, 2, 4, or 8, as defined by the IFCN bits in reg-
ister OSCICN. The divide value defaults to 8 following a reset.
The precision oscillator supports a spread spectrum mode which modulates the output frequency in order
to reduce the EMI generated by the system. When enabled (SSE = 1), the oscillator output frequency is
modulated by a stepped triangle wave whose frequency is equal to the oscillator frequency divided by 384
(63.8 kHz using the factory calibration). The maximum deviation from the center frequency is ±0.75%. The
output frequency updates occur every 32 cycles and the step size is typically 0.25% of the center fre-
quency.
SFR Definition 22.2. OSCICL: Internal H-F Oscillator Calibration
Bit
7
6
5
4
3
2
1
0
OSCICL[6:0]
R/W
Name
Type
Reset
Varies
Varies
Varies
Varies
Varies
Varies
Varies
Varies
SFR Address = 0xB3
Bit Name
6:0 OSCICL[7:0] Internal Oscillator Calibration Bits.
Function
These bits determine the internal oscillator period. When set to 00000000b, the H-F
oscillator operates at its fastest setting. When set to 11111111b, the H-F oscillator
operates at its slowest setting. The reset value is factory calibrated to generate an
internal oscillator frequency of 24.5 MHz.
Rev. 1.0
131
C8051F80x-83x
SFR Definition 22.3. OSCICN: Internal H-F Oscillator Control
Bit
7
6
5
4
3
2
1
0
IOSCEN
IFRDY
SUSPEND STSYNC
SSE
IFCN[1:0]
R/W
Name
Type
Reset
R/W
1
R
1
R/W
0
R
0
R/W
0
R
0
0
0
SFR Address = 0xB2
Bit
Name
Function
7
IOSCEN
Internal H-F Oscillator Enable Bit.
0: Internal H-F Oscillator Disabled.
1: Internal H-F Oscillator Enabled.
6
5
IFRDY
Internal H-F Oscillator Frequency Ready Flag.
0: Internal H-F Oscillator is not running at programmed frequency.
1: Internal H-F Oscillator is running at programmed frequency.
SUSPEND Internal Oscillator Suspend Enable Bit.
Setting this bit to logic 1 places the internal oscillator in SUSPEND mode. The inter-
nal oscillator resumes operation when one of the SUSPEND mode awakening
events occurs.
4
3
STSYNC
Suspend Timer Synchronization Bit.
This bit is used to indicate when it is safe to read and write the registers associated
with the suspend wake-up timer. If a suspend wake-up source other than Timer 2
has brought the oscillator out of suspend mode, it make take up to three timer clocks
before the timer can be read or written.
0: Timer 2 registers can be read safely.
1: Timer 2 register reads and writes should not be performed.
SSE
Spread Spectrum Enable.
Spread spectrum enable bit.
0: Spread Spectrum clock dithering disabled.
1: Spread Spectrum clock dithering enabled.
2
Unused
Read = 0b; Write = Don’t Care
1:0
IFCN[1:0] Internal H-F Oscillator Frequency Divider Control Bits.
00: SYSCLK derived from Internal H-F Oscillator divided by 8.
01: SYSCLK derived from Internal H-F Oscillator divided by 4.
10: SYSCLK derived from Internal H-F Oscillator divided by 2.
11: SYSCLK derived from Internal H-F Oscillator divided by 1.
132
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C8051F80x-83x
22.3. External Oscillator Drive Circuit
The external oscillator circuit may drive an external crystal, ceramic resonator, capacitor, or RC network. A
CMOS clock may also provide a clock input. For a crystal or ceramic resonator configuration, the crys-
tal/resonator must be wired across the XTAL1 and XTAL2 pins as shown in Option 1 of Figure 22.1. A
10 Mresistor also must be wired across the XTAL2 and XTAL1 pins for the crystal/resonator configura-
tion. In RC, capacitor, or CMOS clock configuration, the clock source should be wired to the XTAL2 pin as
shown in Option 2, 3, or 4 of Figure 22.1. The type of external oscillator must be selected in the OSCXCN
register, and the frequency control bits (XFCN) must be selected appropriately (see SFR Definition 22.4).
Important Note on External Oscillator Usage: Port pins must be configured when using the external
oscillator circuit. When the external oscillator drive circuit is enabled in crystal/resonator mode, Port pins
P0.2 and P0.3 are used as XTAL1 and XTAL2 respectively. When the external oscillator drive circuit is
enabled in capacitor, RC, or CMOS clock mode, Port pin P0.3 is used as XTAL2. The Port I/O Crossbar
should be configured to skip the Port pins used by the oscillator circuit; see Section “23.3. Priority Crossbar
Decoder” on page 143 for Crossbar configuration. Additionally, when using the external oscillator circuit in
crystal/resonator, capacitor, or RC mode, the associated Port pins should be configured as analog inputs.
In CMOS clock mode, the associated pin should be configured as a digital input. See Section “23.4. Port
I/O Initialization” on page 147 for details on Port input mode selection.
Rev. 1.0
133
C8051F80x-83x
SFR Definition 22.4. OSCXCN: External Oscillator Control
Bit
7
6
5
4
3
2
1
0
XTLVLD
XOSCMD[2:0]
XFCN[2:0]
Name
Type
Reset
R
0
R/W
0
R
0
R/W
0
0
0
0
0
SFR Address = 0xB1
Bit
Name
Function
7
XTLVLD
Crystal Oscillator Valid Flag.
(Read only when XOSCMD = 11x.)
0: Crystal Oscillator is unused or not yet stable.
1: Crystal Oscillator is running and stable.
6:4 XOSCMD[2:0] External Oscillator Mode Select.
00x: External Oscillator circuit off.
010: External CMOS Clock Mode.
011: External CMOS Clock Mode with divide by 2 stage.
100: RC Oscillator Mode.
101: Capacitor Oscillator Mode.
110: Crystal Oscillator Mode.
111: Crystal Oscillator Mode with divide by 2 stage.
3
Unused
Read = 0; Write = Don’t Care
2:0
XFCN[2:0]
External Oscillator Frequency Control Bits.
Set according to the desired frequency for Crystal or RC mode.
Set according to the desired K Factor for C mode.
XFCN
000
001
010
011
100
101
110
111
Crystal Mode
f 32 kHz
RC Mode
f 25 kHz
C Mode
K Factor = 0.87
K Factor = 2.6
K Factor = 7.7
K Factor = 22
K Factor = 65
K Factor = 180
K Factor = 664
K Factor = 1590
32 kHz f 84 kHz
84 kHz f 225 kHz
25 kHz f 50 kHz
50 kHz f 100 kHz
225 kHz f 590 kHz 100 kHz f 200 kHz
590 kHz f 1.5 MHz 200 kHz f 400 kHz
1.5 MHz f 4 MHz 400 kHz f 800 kHz
4 MHz f 10 MHz
800 kHz f 1.6 MHz
10 MHz f 30 MHz 1.6 MHz f 3.2 MHz
134
Rev. 1.0
C8051F80x-83x
22.3.1. External Crystal Example
If a crystal or ceramic resonator is used as an external oscillator source for the MCU, the circuit should be
configured as shown in Figure 22.1, Option 1. The External Oscillator Frequency Control value (XFCN)
should be chosen from the Crystal column of the table in SFR Definition 22.4 (OSCXCN register). For
example, an 11.0592 MHz crystal requires an XFCN setting of 111b and a 32.768 kHz Watch Crystal
requires an XFCN setting of 001b. After an external 32.768 kHz oscillator is stabilized, the XFCN setting
can be switched to 000 to save power. It is recommended to enable the missing clock detector before
switching the system clock to any external oscillator source.
When the crystal oscillator is first enabled, the oscillator amplitude detection circuit requires a settling time
to achieve proper bias. Introducing a delay of 1 ms between enabling the oscillator and checking the
XTLVLD bit will prevent a premature switch to the external oscillator as the system clock. Switching to the
external oscillator before the crystal oscillator has stabilized can result in unpredictable behavior. The rec-
ommended procedure is as follows:
1. Force XTAL1 and XTAL2 to a low state. This involves enabling the Crossbar and writing 0 to the port
pins associated with XTAL1 and XTAL2.
2. Configure XTAL1 and XTAL2 as analog inputs.
3. Enable the external oscillator.
4. Wait at least 1 ms.
5. Poll for XTLVLD = 1.
6. If desired, enable the Missing Clock Detector.
7. Switch the system clock to the external oscillator.
Important Note on External Crystals: Crystal oscillator circuits are quite sensitive to PCB layout. The
crystal should be placed as close as possible to the XTAL pins on the device. The traces should be as
short as possible and shielded with ground plane from any other traces which could introduce noise or
interference.
The capacitors shown in the external crystal configuration provide the load capacitance required by the
crystal for correct oscillation. These capacitors are "in series" as seen by the crystal and "in parallel" with
the stray capacitance of the XTAL1 and XTAL2 pins.
Note: The desired load capacitance depends upon the crystal and the manufacturer. Please refer to the crystal data
sheet when completing these calculations.
For example, a tuning-fork crystal of 32.768 kHz with a recommended load capacitance of 12.5 pF should
use the configuration shown in Figure 22.1, Option 1. The total value of the capacitors and the stray capac-
itance of the XTAL pins should equal 25 pF. With a stray capacitance of 3 pF per pin, the 22 pF capacitors
yield an equivalent capacitance of 12.5 pF across the crystal, as shown in Figure 22.2.
Rev. 1.0
135
C8051F80x-83x
XTAL1
XTAL2
10M
32.768 kHz
22pF*
22pF*
* Capacitor values depend on
crystal specifications
Figure 22.2. External 32.768 kHz Quartz Crystal Oscillator Connection Diagram
22.3.2. External RC Example
If an RC network is used as an external oscillator source for the MCU, the circuit should be configured as
shown in Figure 22.1, Option 2. The capacitor should be no greater than 100 pF; however for very small
capacitors, the total capacitance may be dominated by parasitic capacitance in the PCB layout. To deter-
mine the required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register, first
select the RC network value to produce the desired frequency of oscillation, according to Equation 22.1,
where f = the frequency of oscillation in MHz, C = the capacitor value in pF, and R = the pull-up resistor
value in k.
Equation 22.1. RC Mode Oscillator Frequency
f = 1.23 103 R C
For example: If the frequency desired is 100 kHz, let R = 246 k and C = 50 pF:
3
3
f = 1.23( 10 ) / RC = 1.23 ( 10 ) / [ 246 x 50 ] = 0.1 MHz = 100 kHz
Referring to the table in SFR Definition 22.4, the required XFCN setting is 010b.
136
Rev. 1.0
C8051F80x-83x
22.3.3. External Capacitor Example
If a capacitor is used as an external oscillator for the MCU, the circuit should be configured as shown in
Figure 22.1, Option 3. The capacitor should be no greater than 100 pF; however for very small capacitors,
the total capacitance may be dominated by parasitic capacitance in the PCB layout. To determine the
required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register, select the capaci-
tor to be used and find the frequency of oscillation according to Equation 22.2, where f = the frequency of
oscillation in MHz, C = the capacitor value in pF, and V = the MCU power supply in volts.
DD
Equation 22.2. C Mode Oscillator Frequency
f = KF R VDD
For example: Assume V = 3.0 V and f = 150 kHz:
DD
f = KF / (C x VDD)
0.150 MHz = KF / (C x 3.0)
Since the frequency of roughly 150 kHz is desired, select the K Factor from the table in SFR Definition 22.4
(OSCXCN) as KF = 22:
0.150 MHz = 22 / (C x 3.0)
C x 3.0 = 22 / 0.150 MHz
C = 146.6 / 3.0 pF = 48.8 pF
Therefore, the XFCN value to use in this example is 011b and C = 50 pF.
Rev. 1.0
137
C8051F80x-83x
23. Port Input/Output
Digital and analog resources are available through 17 I/O pins (24-pin and 20-pin packages) or 13 I/O pins
(16-pin packages). Port pins P0.0–P1.7 can be defined as general-purpose I/O (GPIO) or assigned to one
of the internal digital resources as shown in Figure 23.4. Port pin P2.0 can be used as GPIO and is shared
with the C2 Interface Data signal (C2D). The designer has complete control over which functions are
assigned, limited only by the number of physical I/O pins. This resource assignment flexibility is achieved
through the use of a Priority Crossbar Decoder. Note that the state of a Port I/O pin can always be read in
the corresponding Port latch, regardless of the Crossbar settings.
The Crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder
(Figure 23.5). The registers XBR0 and XBR1, defined in SFR Definition 23.1 and SFR Definition 23.2, are
used to select internal digital functions.
All Port I/Os are 5 V tolerant (refer to Figure 23.2 for the Port cell circuit). The Port I/O cells are configured
as either push-pull or open-drain in the Port Output Mode registers (PnMDOUT, where n = 0,1). Complete
Electrical Specifications for Port I/O are given in Section “7. Electrical Characteristics” on page 39.
Port Match
XBR0, XBR1,
P0MASK, P0MAT
P1MASK, P1MAT
PnSKIP Registers
External Interrupts
EX0 and EX1
Priority
Decoder
PnMDOUT,
PnMDIN Registers
2
UART
SPI
Highest
Priority
4
2
P0.0
P0.7
P0
I/O
Cells
8
8
SMBus
Digital
Crossbar
P1.0
P1
I/O
Cells
2
CP0
Outputs
P1.7*
SYSCLK
PCA
P2.0
P2
I/O
Cells
4
2
Lowest
Priority
T0, T1
*Note: P1.4-P1.7
are not available
on the 16-pin
packages.
8
P0
P1
(P0.0-P0.7)
8
(P1.0-P1.7)
To Analog Peripherals
(ADC0, CP0, VREF, XTAL)
To CS0
Figure 23.1. Port I/O Functional Block Diagram
138
Rev. 1.0
C8051F80x-83x
23.1. Port I/O Modes of Operation
Port pins P0.0–P1.7 use the Port I/O cell shown in Figure 23.2. Each Port I/O cell can be configured by
software for analog I/O or digital I/O using the PnMDIN and PnMDOUT registers. Port pin P2.0 can be con-
figured by software for digital I/O using the P2MDOUT register. On reset, all Port I/O cells default to a high
impedance state with weak pull-ups enabled. Until the crossbar is enabled (XBARE = 1), both the high and
low port I/O drive circuits are explicitly disabled on all crossbar pins.
23.1.1. Port Pins Configured for Analog I/O
Any pins to be used as Comparator or ADC input, Capacitive Sense input, external oscillator input/output,
VREF output, or AGND connection should be configured for analog I/O (PnMDIN.n = 0, Pn.n = 1). When a
pin is configured for analog I/O, its weak pullup, digital driver, and digital receiver are disabled. To prevent
the low port I/o drive circuit from pulling the pin low, a ‘1’ should be written to the corresponding port latch
(Pn.n = 1). Port pins configured for analog I/O will always read back a value of 0 regardless of the actual
voltage on the pin.
Configuring pins as analog I/O saves power and isolates the Port pin from digital interference. Port pins
configured as digital I/O may still be used by analog peripherals; however, this practice is not recom-
mended and may result in measurement errors.
23.1.2. Port Pins Configured For Digital I/O
Any pins to be used by digital peripherals (UART, SPI, SMBus, etc.), external digital event capture func-
tions, or as GPIO should be configured as digital I/O (PnMDIN.n = 1). For digital I/O pins, one of two output
modes (push-pull or open-drain) must be selected using the PnMDOUT registers.
Push-pull outputs (PnMDOUT.n = 1) drive the Port pad to the VDD or GND supply rails based on the out-
put logic value of the Port pin. Open-drain outputs have the high side driver disabled; therefore, they only
drive the Port pad to GND when the output logic value is 0 and become high impedance inputs (both high
and low drivers turned off) when the output logic value is 1.
When a digital I/O cell is placed in the high impedance state, a weak pull-up transistor pulls the Port pad to
the VDD supply voltage to ensure the digital input is at a defined logic state. Weak pull-ups are disabled
when the I/O cell is driven to GND to minimize power consumption and may be globally disabled by setting
WEAKPUD to 1. The user should ensure that digital I/O are always internally or externally pulled or driven
to a valid logic state to minimize power consumption. Port pins configured for digital I/O always read back
the logic state of the Port pad, regardless of the output logic value of the Port pin.
WEAKPUD
(Weak Pull-Up Disable)
PxMDOUT.x
(1 for push-pull)
(0 for open-drain)
VIO
VIO
XBARE
(Crossbar
Enable)
(WEAK)
PORT
PAD
Px.x – Output
Logic Value
(Port Latch or
Crossbar)
PxMDIN.x
(1 for digital)
(0 for analog)
GND
To/From Analog
Peripheral
Px.x – Input Logic Value
(Reads 0 when pin is configured as an analog I/O)
Figure 23.2. Port I/O Cell Block Diagram
Rev. 1.0
139
C8051F80x-83x
23.1.3. Interfacing Port I/O to 5 V Logic
All Port I/O configured for digital, open-drain operation are capable of interfacing to digital logic operating at
a supply voltage up to 2 V higher than VDD and less than 5.25 V. An external pull-up resistor to the higher
supply voltage is typically required for most systems.
Important Note: In a multi-voltage interface, the external pull-up resistor should be sized to allow a current
of at least 150 µA to flow into the Port pin when the supply voltage is between (VDD + 0. 6V) and
(VDD + 1.0V). Once the Port pin voltage increases beyond this range, the current flowing into the Port pin
is minimal. Figure 23.3 shows the input current characteristics of port pins driven above VDD. The port pin
requires 150 µA peak overdrive current when its voltage reaches approximately (VDD + 0.7 V).
VDD
V
test (V)
VDD VDD+0.7
0
IVtest
I/O
Cell
-10
IVtest
(µA)
+
-
Vtest
-150
Port I/O Overdrive Test Circuit
Port I/O Overdrive Current vs. Voltage
Figure 23.3. Port I/O Overdrive Current
23.2. Assigning Port I/O Pins to Analog and Digital Functions
Port I/O pins P0.0–P1.7 can be assigned to various analog, digital, and external interrupt functions. The
Port pins assigned to analog functions should be configured for analog I/O, and Port pins assigned to digi-
tal or external interrupt functions should be configured for digital I/O.
23.2.1. Assigning Port I/O Pins to Analog Functions
Table 23.1 shows all available analog functions that require Port I/O assignments. Port pins selected for
these analog functions should have their corresponding bit in PnSKIP set to 1. This reserves the pin
for use by the analog function and does not allow it to be claimed by the Crossbar. Any selected pins
should also have their corresponding bit in the Port Latch set to 1 (Pn.n = 1). This prevents the low
port I/O drive circuit from pulling the pin low. Table 23.1 shows the potential mapping of Port I/O to each
analog function.
140
Rev. 1.0
C8051F80x-83x
Table 23.1. Port I/O Assignment for Analog Functions
Analog Function
PotentiallyAssignable
Port Pins
SFR(s) used for
Assignment
ADC Input
P0.0–P1.7
P0.0–P1.7
P0.0–P1.7
P0.0
ADC0MX, PnSKIP,
PnMDIN
Comparator0 Input
CS0 Input
CPT0MX, PnSKIP,
PnMDIN
CS0MX, CS0SS,
CS0SE, PnMDIN
Voltage Reference (VREF0)
REF0CN, P0SKIP,
PnMDIN
Ground Reference (AGND)
P0.1
P0.2
REF0CN, P0SKIP
External Oscillator in Crystal Mode (XTAL1)
OSCXCN, P0SKIP,
P0MDIN
External Oscillator in RC, C, or Crystal Mode (XTAL2)
P0.3
OSCXCN, P0SKIP,
P0MDIN
23.2.2. Assigning Port I/O Pins to Digital Functions
Any Port pins not assigned to analog functions may be assigned to digital functions or used as GPIO. Most
digital functions rely on the Crossbar for pin assignment; however, some digital functions bypass the
Crossbar in a manner similar to the analog functions listed above. Port pins used by these digital func-
tions and any Port pins selected for use as GPIO should have their corresponding bit in PnSKIP set
to 1. Table 23.2 shows all available digital functions and the potential mapping of Port I/O to each digital
function.
Rev. 1.0
141
C8051F80x-83x
Table 23.2. Port I/O Assignment for Digital Functions
Digital Function
Potentially Assignable Port Pins
SFR(s) used for
Assignment
UART0, SPI0, SMBus,
SYSCLK, PCA0 (CEX0-2
and ECI), T0, or T1.
Any Port pin available for assignment by the
XBR0, XBR1
2
Crossbar. This includes P0.0 - P1.7 pins which
1
have their PnSKIP bit set to 0.
2
Any pin used for GPIO
P0.0–P2.0
PnSKIP
Notes:
1. The Crossbar will always assign UART0 pins to P0.4 and P0.5.
2. Port pins P1.4–P1.7 are not available on the 16-pin packages.
23.2.3. Assigning Port I/O Pins to External Digital Event Capture Functions
External digital event capture functions can be used to trigger an interrupt or wake the device from a low
power mode when a transition occurs on a digital I/O pin. The digital event capture functions do not require
dedicated pins and will function on both GPIO pins (PnSKIP = 1) and pins in use by the Crossbar (PnSKIP
= 0). External digital event capture functions cannot be used on pins configured for analog I/O. Table 23.3
shows all available external digital event capture functions.
Table 23.3. Port I/O Assignment for External Digital Event Capture Functions
Digital Function
Potentially Assignable Port Pins
SFR(s) used for
Assignment
External Interrupt 0
External Interrupt 1
Port Match
P0.0–P0.7
P0.0–P0.7
IT01CF
IT01CF
*
P0.0–P1.7
P0MASK, P0MAT
P1MASK, P1MAT
Note: Port pins P1.4–P1.7 are not available on the 16-pin packages.
142
Rev. 1.0
C8051F80x-83x
23.3. Priority Crossbar Decoder
The Priority Crossbar Decoder assigns a priority to each I/O function, starting at the top with UART0. When
a digital resource is selected, the least-significant unassigned Port pin is assigned to that resource (exclud-
ing UART0, which is always at pins 4 and 5). If a Port pin is assigned, the Crossbar skips that pin when
assigning the next selected resource. Additionally, the Crossbar will skip Port pins whose associated bits in
the PnSKIP registers are set. The PnSKIP registers allow software to skip Port pins that are to be used for
analog input, dedicated functions, or GPIO.
Because of the nature of the Priority Crossbar Decoder, not all peripherals can be located on all port pins.
Figure 23.4 maps peripherals to the potential port pins on which the peripheral I/O can appear.
Important Note on Crossbar Configuration: If a Port pin is claimed by a peripheral without use of the
Crossbar, its corresponding PnSKIP bit should be set. This applies to P0.0 if VREF is used, P0.1 if AGND
is used, P0.3 and/or P0.2 if the external oscillator circuit is enabled, P0.6 if the ADC is configured to use
the external conversion start signal (CNVSTR), and any selected ADC, Comparator, or Capacitive Sense
inputs. The Crossbar skips selected pins as if they were already assigned, and moves to the next unas-
signed pin.
Registers XBR0, XBR1, and XBR2 are used to assign the digital I/O resources to the physical I/O Port
pins. Note that when the SMBus is selected, the Crossbar assigns both pins associated with the SMBus
(SDA and SCL); when a UART is selected, the Crossbar assigns both pins associated with the UART (TX
and RX). UART0 pin assignments are fixed for bootloading purposes: UART TX0 is always assigned to
P0.4; UART RX0 is always assigned to P0.5. Standard Port I/Os appear contiguously after the prioritized
functions have been assigned.
Important Note: The SPI can be operated in either 3-wire or 4-wire modes, depending on the state of the
NSSMD1–NSSMD0 bits in register SPI0CN. According to the SPI mode, the NSS signal may or may not
be routed to a Port pin.
Rev. 1.0
143
C8051F80x-83x
Port
P0
4
P1
Pin Number 0
1
2
3
5
6
7
0
1
2
3 41 51 61 71
0
Special
Function
Signals
TX0
RX0
SCK
MISO
MOSI
NSS2
SDA
SCL
CP0
CP0A
SYSCLK
CEX0
CEX1
CEX2
ECI
T0
T1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Pin Skip
Settings
P0SKIP
P1SKIP
Pins P0.0-P1.71 are capable of being assigned to crossbar peripherals.
The crossbar peripherals are assigned in priority order from top to bottom,
according to this diagram.
These boxes represent Port pins which can potentially be assigned to
a peripheral.
Special Function Signals are not assigned by the crossbar. When
these signals are enabled, the Crossbar should be manually configured to
skip the corresponding port pins.
Pins can be “skipped” by setting the corresponding bit in PnSKIP to ‘1’.
Notes:
1. P1.4-P1.7 are not available on 16-pin packages.
2. NSS is only pinned out when the SPI is in 4-wire mode.
Figure 23.4. Priority Crossbar Decoder Potential Pin Assignments
144
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Port
P0
4
P1
41 51 61 71
0
Pin Number 0
1
2
3
5
6
7
0
1
2
3
Special
Function
Signals
TX0
RX0
SCK
MISO
MOSI
NSS2
SDA
SCL
CP0
CP0A
SYSCLK
CEX0
CEX1
CEX2
ECI
T0
T1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Pin Skip
Settings
P0SKIP
P1SKIP
In this example, the crossbar is configured to assign the UART TX0 and
RX0 signals, the SPI signals, and the PCA signals. Note that the SPI
signals are assigned as multiple signals, and there are no pins skipped
using the P0SKIP or P1SKIP registers.
These boxes represent the port pins which are used by the peripherals
in this configuration.
1st TX0 is assigned to P0.4
2
nd RX0 is assigned to P0.5
3rd SCK, MISO, MOSI, and NSS are assigned to P0.0, P0.1, P0.2, and
P0.3, respectively.
4th CEX0, CEX1, and CEX2 are assigned to P0.6, P0.7, and P1.0,
respectively.
All unassigned pins can be used as GPIO or for other non-crossbar
functions.
Notes:
1. P1.4-P1.7 are not available on 16-pin packages.
2. NSS is only pinned out when the SPI is in 4-wire mode.
Figure 23.5. Priority Crossbar Decoder Example 1—No Skipped Pins
Rev. 1.0
145
C8051F80x-83x
Port
P0
4
P1
41 51 61 71
0
Pin Number 0
1
2
3
5
6
7
0
1
2
3
Special
Function
Signals
TX0
RX0
SCK
MISO
MOSI
NSS2
SDA
SCL
CP0
CP0A
SYSCLK
CEX0
CEX1
CEX2
ECI
T0
T1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
Pin Skip
Settings
P0SKIP
P1SKIP
In this example, the crossbar is configured to assign the UART TX0 and
RX0 signals, the SPI signals, and the PCA signals. Note that the SPI
signals are assigned as multiple signals. Additionally, pins P0.0, P0.2, and
P0.3 are configured to be skipped using the P0SKIP register.
These boxes represent the port pins which are used by the peripherals
in this configuration.
1st TX0 is assigned to P0.4
2
nd RX0 is assigned to P0.5
3rd SCK, MISO, MOSI, and NSS are assigned to P0.1, P0.6, P0.7, and
P1.0, respectively.
4th CEX0, CEX1, and CEX2 are assigned to P1.1, P1.2, and P1.3,
respectively.
All unassigned pins, including those skipped by XBR0 can be used as
GPIO or for other non-crossbar functions.
Notes:
1. P1.4-P1.7 are not available on 16-pin packages.
2. NSS is only pinned out when the SPI is in 4-wire mode.
Figure 23.6. Priority Crossbar Decoder Example 2—Skipping Pins
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23.4. Port I/O Initialization
Port I/O initialization consists of the following steps:
1. Select the input mode (analog or digital) for all Port pins, using the Port Input Mode register (PnMDIN).
If the pin is in analog mode, a ‘1’ must also be written to the corresponding Port Latch (Pn).
2. Select the output mode (open-drain or push-pull) for all Port pins, using the Port Output Mode register
(PnMDOUT).
3. Select any pins to be skipped by the I/O Crossbar using the Port Skip registers (PnSKIP).
4. Assign Port pins to desired peripherals (XBR0, XBR1).
5. Enable the Crossbar (XBARE = 1).
All Port pins must be configured as either analog or digital inputs. When a pin is configured as an analog
input, its weak pullup, digital driver, and digital receiver are disabled. This process saves power and
reduces noise on the analog input. Pins configured as digital inputs may still be used by analog peripher-
als; however this practice is not recommended.
Additionally, all analog input pins should be configured to be skipped by the Crossbar (accomplished by
setting the associated bits in PnSKIP). Port input mode is set in the PnMDIN register, where a 1 indicates a
digital input, and a 0 indicates an analog input. All port pins in analog mode must have a ‘1’ set in the cor-
responding Port Latch register. All pins default to digital inputs on reset. See SFR Definition 23.8 and SFR
Definition 23.12 for the PnMDIN register details.
The output driver characteristics of the I/O pins are defined using the Port Output Mode registers (PnMD-
OUT). Each Port Output driver can be configured as either open drain or push-pull. This selection is
required even for the digital resources selected in the XBRn registers, and is not automatic. The only
exception to this is the SMBus (SDA, SCL) pins, which are configured as open-drain regardless of the
PnMDOUT settings. When the WEAKPUD bit in XBR1 is 0, a weak pullup is enabled for all Port I/O config-
ured as open-drain. WEAKPUD does not affect the push-pull Port I/O. Furthermore, the weak pullup is
turned off on an output that is driving a 0 to avoid unnecessary power dissipation.
Registers XBR0 and XBR1 must be loaded with the appropriate values to select the digital I/O functions
required by the design. Setting the XBARE bit in XBR1 to 1 enables the Crossbar. Until the Crossbar is
enabled, the external pins remain as standard Port I/O (in input mode), regardless of the XBRn Register
settings. For given XBRn Register settings, one can determine the I/O pin-out using the Priority Decode
Table; as an alternative, the Configuration Wizard utility will determine the Port I/O pin-assignments based
on the XBRn Register settings.
The Crossbar must be enabled to use Port pins as standard Port I/O in output mode. Port output drivers
are disabled while the Crossbar is disabled.
Rev. 1.0
147
C8051F80x-83x
SFR Definition 23.1. XBR0: Port I/O Crossbar Register 0
Bit
7
6
5
4
3
2
1
0
CP0AE
CP0E
SYSCKE
SMB0E
SPI0E
URT0E
Name
Type
Reset
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Address = 0xE1
Bit
7:6
5
Name
Function
Unused Read = 00b. Write = don’t care.
CP0AE Comparator0 Asynchronous Output Enable.
0: Asynchronous CP0 unavailable at Port pin.
1: Asynchronous CP0 routed to Port pin.
4
3
2
1
CP0E
Comparator0 Output Enable.
0: CP0 unavailable at Port pin.
1: CP0 routed to Port pin.
SYSCKE SYSCLK Output Enable.
0: SYSCLK unavailable at Port pin.
1: SYSCLK output routed to Port pin.
SMB0E SMBus I/O Enable.
0: SMBus I/O unavailable at Port pins.
1: SMBus I/O routed to Port pins.
SPI0E
SPI I/O Enable.
0: SPI I/O unavailable at Port pins.
1: SPI I/O routed to Port pins. Note that the SPI can be assigned either 3 or 4 GPIO
pins.
0
URT0E UART I/O Output Enable.
0: UART I/O unavailable at Port pin.
1: UART TX0, RX0 routed to Port pins P0.4 and P0.5.
148
Rev. 1.0
C8051F80x-83x
SFR Definition 23.2. XBR1: Port I/O Crossbar Register 1
Bit
7
6
5
4
3
2
1
0
WEAKPUD XBARE
T1E
T0E
ECIE
PCA0ME[1:0]
R/W R/W
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
0
0
SFR Address = 0xE2
Bit
Name
Function
7
WEAKPUD Port I/O Weak Pullup Disable.
0: Weak Pullups enabled (except for Ports whose I/O are configured for analog
mode).
1: Weak Pullups disabled.
6
5
4
3
2
XBARE
T1E
Crossbar Enable.
0: Crossbar disabled.
1: Crossbar enabled.
T1 Enable.
0: T1 unavailable at Port pin.
1: T1 routed to Port pin.
T0E
T0 Enable.
0: T0 unavailable at Port pin.
1: T0 routed to Port pin.
ECIE
PCA0 External Counter Input Enable.
0: ECI unavailable at Port pin.
1: ECI routed to Port pin.
Unused
Read = 0b; Write = Don’t Care.
1:0 PCA0ME[1:0] PCA Module I/O Enable Bits.
00: All PCA I/O unavailable at Port pins.
01: CEX0 routed to Port pin.
10: CEX0, CEX1 routed to Port pins.
11: CEX0, CEX1, CEX2 routed to Port pins.
Rev. 1.0
149
C8051F80x-83x
23.5. Port Match
Port match functionality allows system events to be triggered by a logic value change on P0 or P1. A soft-
ware controlled value stored in the PnMATCH registers specifies the expected or normal logic values of P0
and P1. A Port mismatch event occurs if the logic levels of the Port’s input pins no longer match the soft-
ware controlled value. This allows Software to be notified if a certain change or pattern occurs on P0 or P1
input pins regardless of the XBRn settings.
The PnMASK registers can be used to individually select which P0 and P1 pins should be compared
against the PnMATCH registers. A Port mismatch event is generated if (P0 & P0MASK) does not equal
(P0MATCH & P0MASK) or if (P1 & P1MASK) does not equal (P1MATCH & P1MASK).
A Port mismatch event may be used to generate an interrupt or wake the device from a low power mode,
such as IDLE or SUSPEND. See the Interrupts and Power Options chapters for more details on interrupt
and wake-up sources.
150
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C8051F80x-83x
SFR Definition 23.3. P0MASK: Port 0 Mask Register
Bit
7
6
5
4
3
2
1
0
P0MASK[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xFE
Bit Name
7:0 P0MASK[7:0] Port 0 Mask Value.
Function
Selects P0 pins to be compared to the corresponding bits in P0MAT.
0: P0.n pin logic value is ignored and cannot cause a Port Mismatch event.
1: P0.n pin logic value is compared to P0MAT.n.
SFR Definition 23.4. P0MAT: Port 0 Match Register
Bit
7
6
5
4
3
2
1
0
P0MAT[7:0]
R/W
Name
Type
Reset
1
1
1
1
1
1
1
1
SFR Address = 0xFD
Bit
Name
Function
7:0
P0MAT[7:0]
Port 0 Match Value.
Match comparison value used on Port 0 for bits in P0MASK which are set to 1.
0: P0.n pin logic value is compared with logic LOW.
1: P0.n pin logic value is compared with logic HIGH.
Rev. 1.0
151
C8051F80x-83x
SFR Definition 23.5. P1MASK: Port 1 Mask Register
Bit
7
6
5
4
3
2
1
0
P1MASK[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xEE
Bit Name
7:0 P1MASK[7:0] Port 1 Mask Value.
Function
Selects P1 pins to be compared to the corresponding bits in P1MAT.
0: P1.n pin logic value is ignored and cannot cause a Port Mismatch event.
1: P1.n pin logic value is compared to P1MAT.n.
Note: P1.4–P1.7 are not available on 16-pin packages.
SFR Definition 23.6. P1MAT: Port 1 Match Register
Bit
7
6
5
4
3
2
1
0
P1MAT[7:0]
R/W
Name
Type
Reset
1
1
1
1
1
1
1
1
SFR Address = 0xED
Bit
Name
Function
7:0
P1MAT[7:0]
Port 1 Match Value.
Match comparison value used on Port 1 for bits in P1MASK which are set to 1.
0: P1.n pin logic value is compared with logic LOW.
1: P1.n pin logic value is compared with logic HIGH.
Note: P1.4–P1.7 are not available on 16-pin packages.
23.6. Special Function Registers for Accessing and Configuring Port I/O
All Port I/O are accessed through corresponding special function registers (SFRs) that are both byte
addressable and bit addressable. When writing to a Port, the value written to the SFR is latched to main-
tain the output data value at each pin. When reading, the logic levels of the Port's input pins are returned
regardless of the XBRn settings (i.e., even when the pin is assigned to another signal by the Crossbar, the
Port register can always read its corresponding Port I/O pin). The exception to this is the execution of the
read-modify-write instructions that target a Port Latch register as the destination. The read-modify-write
instructions when operating on a Port SFR are the following: ANL, ORL, XRL, JBC, CPL, INC, DEC, DJNZ
and MOV, CLR or SETB, when the destination is an individual bit in a Port SFR. For these instructions, the
value of the latch register (not the pin) is read, modified, and written back to the SFR.
152
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Each Port has a corresponding PnSKIP register which allows its individual Port pins to be assigned to dig-
ital functions or skipped by the Crossbar. All Port pins used for analog functions or GPIO should have their
PnSKIP bit set to 1.
The Port input mode of the I/O pins is defined using the Port Input Mode registers (PnMDIN). Each Port
cell can be configured for analog or digital I/O. This selection is required even for the digital resources
selected in the XBRn registers, and is not automatic. The only exception to this is P2.0, which can only be
used for digital I/O.
The output driver characteristics of the I/O pins are defined using the Port Output Mode registers (PnMD-
OUT). Each Port Output driver can be configured as either open drain or push-pull. This selection is
required even for the digital resources selected in the XBRn registers, and is not automatic. The only
exception to this is the SMBus (SDA, SCL) pins, which are configured as open-drain regardless of the
PnMDOUT settings.
SFR Definition 23.7. P0: Port 0
Bit
7
6
5
4
3
2
1
0
P0[7:0]
R/W
Name
Type
Reset
1
1
1
1
1
1
1
1
SFR Address = 0x80; Bit-Addressable
Bit
Name
P0[7:0] Port 0 Data.
Sets the Port latch logic
Description
Write
0: Set output latch to logic 0: P0.n Port pin is logic
LOW. LOW.
1: Set output latch to logic 1: P0.n Port pin is logic
Read
7:0
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
HIGH.
HIGH.
Rev. 1.0
153
C8051F80x-83x
SFR Definition 23.8. P0MDIN: Port 0 Input Mode
Bit
7
6
5
4
3
2
1
0
P0MDIN[7:0]
R/W
Name
Type
Reset
1
1
1
1
1
1
1
1
SFR Address = 0xF1
Bit
Name
Function
7:0
P0MDIN[7:0] Analog Configuration Bits for P0.7–P0.0 (respectively).
Port pins configured for analog mode have their weak pullup, digital driver, and
digital receiver disabled. In order for the P0.n pin to be in analog mode, there
MUST be a ‘1’ in the Port Latch register corresponding to that pin.
0: Corresponding P0.n pin is configured for analog mode.
1: Corresponding P0.n pin is not configured for analog mode.
SFR Definition 23.9. P0MDOUT: Port 0 Output Mode
Bit
7
6
5
4
3
2
1
0
P0MDOUT[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xA4
Bit Name
Function
7:0 P0MDOUT[7:0] Output Configuration Bits for P0.7–P0.0 (respectively).
These bits are ignored if the corresponding bit in register P0MDIN is logic 0.
0: Corresponding P0.n Output is open-drain.
1: Corresponding P0.n Output is push-pull.
154
Rev. 1.0
C8051F80x-83x
SFR Definition 23.10. P0SKIP: Port 0 Skip
Bit
7
6
5
4
3
2
1
0
P0SKIP[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xD4
Bit
Name
Function
7:0
P0SKIP[7:0] Port 0 Crossbar Skip Enable Bits.
These bits select Port 0 pins to be skipped by the Crossbar Decoder. Port pins
used for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P0.n pin is not skipped by the Crossbar.
1: Corresponding P0.n pin is skipped by the Crossbar.
SFR Definition 23.11. P1: Port 1
Bit
7
6
5
4
3
2
1
0
P1[7:0]
R/W
Name
Type
Reset
1
1
1
1
1
1
1
1
SFR Address = 0x90; Bit-Addressable
Bit
Name
P1[7:0] Port 1 Data.
Sets the Port latch logic
Description
Write
0: Set output latch to logic 0: P1.n Port pin is logic
LOW. LOW.
1: Set output latch to logic 1: P1.n Port pin is logic
Read
7:0
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
HIGH.
HIGH.
Note: P1.4–P1.7 are not
available on 16-pin
packages.
Rev. 1.0
155
C8051F80x-83x
SFR Definition 23.12. P1MDIN: Port 1 Input Mode
Bit
7
6
5
4
3
2
1
0
P1MDIN[7:0]
R/W
Name
Type
Reset
1*
1*
1*
1*
1
1
1
1
SFR Address = 0xF2
Bit
Name
Function
7:0
P1MDIN[7:0] Analog Configuration Bits for P1.7–P1.0 (respectively).
Port pins configured for analog mode have their weak pullup, digital driver, and
digital receiver disabled. In order for the P1.n pin to be in analog mode, there
MUST be a 1 in the Port Latch register corresponding to that pin.
0: Corresponding P1.n pin is configured for analog mode.
1: Corresponding P1.n pin is not configured for analog mode.
Note: P1.4–P1.7 are not available on 16-pin packages, with the reset value of 0000b for
P1MDIN[7:4].
SFR Definition 23.13. P1MDOUT: Port 1 Output Mode
Bit
7
6
5
4
3
2
1
0
P1MDOUT[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xA5
Bit Name
Function
7:0 P1MDOUT[7:0] Output Configuration Bits for P1.7–P1.0 (respectively).
These bits are ignored if the corresponding bit in register P1MDIN is logic 0.
0: Corresponding P1.n Output is open-drain.
1: Corresponding P1.n Output is push-pull.
Note: P1.4–P1.7 are not available on 16-pin packages.
156
Rev. 1.0
C8051F80x-83x
SFR Definition 23.14. P1SKIP: Port 1 Skip
Bit
7
6
5
4
3
2
1
0
P1SKIP[7:0]
R/W
Name
Type
Reset
0*
0*
0*
0*
0
0
0
0
SFR Address = 0xD5
Bit
Name
Function
7:0
P1SKIP[7:0]
Port 1 Crossbar Skip Enable Bits.
These bits select Port 1 pins to be skipped by the Crossbar Decoder. Port pins
used for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P1.n pin is not skipped by the Crossbar.
1: Corresponding P1.n pin is skipped by the Crossbar.
Note: P1.4–P1.7 are not available on 16-pin packages, with the reset value of 1111b for
P1SKIP[7:4].
SFR Definition 23.15. P2: Port 2
Bit
7
6
5
4
3
2
1
0
P2[0]
Name
Type
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
1
SFR Address = 0xA0; Bit-Addressable
Bit
7:1
0
Name
Description
Write
Read
Unused Unused.
Don’t Care
0000000b
P2[0]
Port 2 Data.
0: Set output latch to logic 0: P2.0 Port pin is logic
LOW. LOW.
1: Set output latch to logic 1: P2.0 Port pin is logic
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
HIGH.
HIGH.
Rev. 1.0
157
C8051F80x-83x
SFR Definition 23.16. P2MDOUT: Port 2 Output Mode
Bit
7
6
5
4
3
2
1
0
P2MDOUT[0]
Name
Type
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
SFR Address = 0xA6
Bit
7:1
0
Name
Function
Unused
Read = 0000000b; Write = Don’t Care
P2MDOUT[0] Output Configuration Bits for P2.0.
0: P2.0 Output is open-drain.
1: P2.0 Output is push-pull.
158
Rev. 1.0
C8051F80x-83x
24. Cyclic Redundancy Check Unit (CRC0)
C8051F80x-83x devices include a cyclic redundancy check unit (CRC0) that can perform a CRC using a
16-bit or 32-bit polynomial. CRC0 accepts a stream of 8-bit data written to the CRC0IN register. CRC0
posts the 16-bit or 32-bit result to an internal register. The internal result register may be accessed indi-
rectly using the CRC0PNT bits and CRC0DAT register, as shown in Figure 24.1. CRC0 also has a bit
reverse register for quick data manipulation.
8
8
Automatic CRC
Controller
Flash
Memory
CRC0IN
CRC0AUTO
CRC0CNT
CRC0SEL
CRC0INIT
CRC0VAL
CRC0PNT1
CRC0PNT0
CRC Engine
32
RESULT
CRC0FLIP
Write
8
8
8
8
4 to 1 MUX
8
CRC0DAT
CRC0FLIP
Read
Figure 24.1. CRC0 Block Diagram
Rev. 1.0
159
C8051F80x-83x
24.1. 16-bit CRC Algorithm
The C8051F80x-83x CRC unit calculates the 16-bit CRC MSB-first, using a poly of 0x1021. The following
describes the 16-bit CRC algorithm performed by the hardware:
1. XOR the most-significant byte of the current CRC result with the input byte. If this is the first iteration of
the CRC unit, the current CRC result will be the set initial value (0x0000 or 0xFFFF).
2. If the MSB of the CRC result is set, left-shift the CRC result, and then XOR the CRC result with the
polynomial (0x1021).
3. If the MSB of the CRC result is not set, left-shift the CRC result.
4. Repeat at Step 2 for the number of input bits (8).
For example, the 16-bit C8051F80x-83x CRC algorithm can be described by the following code:
unsigned short UpdateCRC (unsigned short CRC_acc, unsigned char CRC_input){
unsigned char i;
// loop counter
#define POLY 0x1021
// Create the CRC "dividend" for polynomial arithmetic (binary arithmetic
// with no carries)
CRC_acc = CRC_acc ^ (CRC_input << 8);
// "Divide" the poly into the dividend using CRC XOR subtraction
// CRC_acc holds the "remainder" of each divide
// Only complete this division for 8 bits since input is 1 byte
for (i = 0; i < 8; i++)
{
// Check if the MSB is set (if MSB is 1, then the POLY can "divide"
// into the "dividend")
if ((CRC_acc & 0x8000) == 0x8000)
{
// if so, shift the CRC value, and XOR "subtract" the poly
CRC_acc = CRC_acc << 1;
CRC_acc ^= POLY;
}
else
{
// if not, just shift the CRC value
CRC_acc = CRC_acc << 1;
}
}
return CRC_acc; // Return the final remainder (CRC value)
}
Table 24.1 lists example input values and the associated outputs using the 16-bit C8051F80x-83x CRC
algorithm (an initial value of 0xFFFF is used):
Table 24.1. Example 16-bit CRC Outputs
Input
Output
0x63
0xAA, 0xBB, 0xCC
0x00, 0x00, 0xAA, 0xBB, 0xCC
0xBD35
0x6CF6
0xB166
160
Rev. 1.0
C8051F80x-83x
24.2. 32-bit CRC Algorithm
The C8051F80x-83x CRC unit calculates the 32-bit CRC using a poly of 0x04C11DB7. The CRC-32 algo-
rithm is "reflected", meaning that all of the input bytes and the final 32-bit output are bit-reversed in the pro-
cessing engine. The following is a description of a simplified CRC algorithm that produces results identical
to the hardware:
1. XOR the least-significant byte of the current CRC result with the input byte. If this is the first iteration of
the CRC unit, the current CRC result will be the set initial value (0x00000000 or 0xFFFFFFFF).
2. Right-shift the CRC result.
3. If the LSB of the CRC result is set, XOR the CRC result with the reflected polynomial (0xEDB88320).
4. Repeat at Step 2 for the number of input bits (8).
For example, the 32-bit C8051F80x-83x CRC algorithm can be described by the following code:
unsigned long UpdateCRC (unsigned long CRC_acc, unsigned char CRC_input){
unsigned char i; // loop counter
#define POLY 0xEDB88320 // bit-reversed version of the poly 0x04C11DB7
// Create the CRC "dividend" for polynomial arithmetic (binary arithmetic
// with no carries)
CRC_acc = CRC_acc ^ CRC_input;
// "Divide" the poly into the dividend using CRC XOR subtraction
// CRC_acc holds the "remainder" of each divide
// Only complete this division for 8 bits since input is 1 byte
for (i = 0; i < 8; i++)
{
// Check if the MSB is set (if MSB is 1, then the POLY can "divide"
// into the "dividend")
if ((CRC_acc & 0x00000001) == 0x00000001)
{
// if so, shift the CRC value, and XOR "subtract" the poly
CRC_acc = CRC_acc >> 1;
CRC_acc ^= POLY;
}
else
{
// if not, just shift the CRC value
CRC_acc = CRC_acc >> 1;
}
}
return CRC_acc; // Return the final remainder (CRC value)
}
Table 24.2 lists example input values and the associated outputs using the 32-bit C8051F80x-83x CRC
algorithm (an initial value of 0xFFFFFFFF is used):
Table 24.2. Example 32-bit CRC Outputs
Input
Output
0x63
0xAA, 0xBB, 0xCC
0x00, 0x00, 0xAA, 0xBB, 0xCC
0xF9462090
0x41B207B3
0x78D129BC
Rev. 1.0
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24.3. Preparing for a CRC Calculation
To prepare CRC0 for a CRC calculation, software should select the desired polynomial and set the initial
value of the result. Two polynomials are available: 0x1021 (16-bit) and 0x04C11DB7 (32-bit). The CRC0
result may be initialized to one of two values: 0x00000000 or 0xFFFFFFFF. The following steps can be
used to initialize CRC0.
1. Select a polynomial (Set CRC0SEL to 0 for 32-bit or 1 for 16-bit).
2. Select the initial result value (Set CRC0VAL to 0 for 0x00000000 or 1 for 0xFFFFFFFF).
3. Set the result to its initial value (Write 1 to CRC0INIT).
24.4. Performing a CRC Calculation
Once CRC0 is initialized, the input data stream is sequentially written to CRC0IN, one byte at a time. The
CRC0 result is automatically updated after each byte is written. The CRC engine may also be configured to
automatically perform a CRC on one or more Flash sectors. The following steps can be used to automati-
cally perform a CRC on Flash memory.
1. Prepare CRC0 for a CRC calculation as shown above.
2. Write the index of the starting page to CRC0AUTO.
3. Set the AUTOEN bit in CRC0AUTO.
4. Write the number of Flash sectors to perform in the CRC calculation to CRC0CNT.
Note: Each Flash sector is 512 bytes.
5. Write any value to CRC0CN (or OR its contents with 0x00) to initiate the CRC calculation. The CPU will
not execute code any additional code until the CRC operation completes.
6. Clear the AUTOEN bit in CRC0AUTO.
7. Read the CRC result using the procedure below.
24.5. Accessing the CRC0 Result
The internal CRC0 result is 32-bits (CRC0SEL = 0b) or 16-bits (CRC0SEL = 1b). The CRC0PNT bits
select the byte that is targeted by read and write operations on CRC0DAT and increment after each read or
write. The calculation result will remain in the internal CR0 result register until it is set, overwritten, or addi-
tional data is written to CRC0IN.
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SFR Definition 24.1. CRC0CN: CRC0 Control
Bit
7
6
5
4
3
2
1
0
CRC0SEL CRC0INIT CRC0VAL
CRC0PNT[1:0]
R/W
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
0
SFR Address = 0xCE
Bit
7:5
4
Name
Function
Unused
Read = 000b; Write = Don’t Care.
CRC0SEL
CRC0 Polynomial Select Bit.
This bit selects the CRC0 polynomial and result length (32-bit or 16-bit).
0: CRC0 uses the 32-bit polynomial 0x04C11DB7 for calculating the CRC result.
1: CRC0 uses the 16-bit polynomial 0x1021 for calculating the CRC result.
3
2
CRC0INIT
CRC0VAL
CRC0 Result Initialization Bit.
Writing a 1 to this bit initializes the entire CRC result based on CRC0VAL.
CRC0 Set Value Initialization Bit.
This bit selects the set value of the CRC result.
0: CRC result is set to 0x00000000 on write of 1 to CRC0INIT.
1: CRC result is set to 0xFFFFFFFF on write of 1 to CRC0INIT.
1:0 CRC0PNT[1:0] CRC0 Result Pointer.
Specifies the byte of the CRC result to be read/written on the next access to
CRC0DAT. The value of these bits will auto-increment upon each read or write.
For CRC0SEL = 0:
00: CRC0DAT accesses bits 7–0 of the 32-bit CRC result.
01: CRC0DAT accesses bits 15–8 of the 32-bit CRC result.
10: CRC0DAT accesses bits 23–16 of the 32-bit CRC result.
11: CRC0DAT accesses bits 31–24 of the 32-bit CRC result.
For CRC0SEL = 1:
00: CRC0DAT accesses bits 7–0 of the 16-bit CRC result.
01: CRC0DAT accesses bits 15–8 of the 16-bit CRC result.
10: CRC0DAT accesses bits 7–0 of the 16-bit CRC result.
11: CRC0DAT accesses bits 15–8 of the 16-bit CRC result.
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C8051F80x-83x
SFR Definition 24.2. CRC0IN: CRC Data Input
Bit
7
6
5
4
3
2
1
0
CRC0IN[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xDD
Bit Name
7:0 CRC0IN[7:0] CRC0 Data Input.
Function
Each write to CRC0IN results in the written data being computed into the existing
CRC result according to the CRC algorithm described in Section 24.1
SFR Definition 24.3. CRC0DATA: CRC Data Output
Bit
7
6
5
4
3
2
1
0
CRC0DAT[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xDE
Bit Name
7:0 CRC0DAT[7:0] CRC0 Data Output.
Function
Each read or write performed on CRC0DAT targets the CRC result bits pointed to
by the CRC0 Result Pointer (CRC0PNT bits in CRC0CN).
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SFR Definition 24.4. CRC0AUTO: CRC Automatic Control
Bit
7
6
5
4
3
2
1
0
AUTOEN CRCCPT Reserved
CRC0ST[4:0]
Name
Type
Reset
R/W
0
1
0
0
0
0
0
0
SFR Address = 0xD2
Bit
Name
Function
Automatic CRC Calculation Enable.
7
AUTOEN
When AUTOEN is set to 1, any write to CRC0CN will initiate an automatic CRC
starting at Flash sector CRC0ST and continuing for CRC0CNT sectors.
6
5
CRCCPT
Reserved
Automatic CRC Calculation Complete.
Set to 0 when a CRC calculation is in progress. Code execution is stopped during
a CRC calculation, therefore reads from firmware will always return 1.
Must write 0.
4:0 CRC0ST[4:0] Automatic CRC Calculation Starting Flash Sector.
These bits specify the Flash sector to start the automatic CRC calculation. The
starting address of the first Flash sector included in the automatic CRC calculation
is CRC0ST x 512.
SFR Definition 24.5. CRC0CNT: CRC Automatic Flash Sector Count
Bit
7
6
5
4
3
2
1
0
CRC0CNT[5:0]
R/W
Name
Type
Reset
R
0
R
0
0
0
0
0
0
0
SFR Address = 0xD3
Bit
Name
Function
7:6
Unused
Read = 00b; Write = Don’t Care.
5:0 CRC0CNT[5:0] Automatic CRC Calculation Flash Sector Count.
These bits specify the number of Flash sectors to include when performing an
automatic CRC calculation. The base address of the last flash sector included in
the automatic CRC calculation is equal to (CRC0ST + CRC0CNT) x 512.
Rev. 1.0
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C8051F80x-83x
24.6. CRC0 Bit Reverse Feature
CRC0 includes hardware to reverse the bit order of each bit in a byte as shown in Figure 24.1. Each byte
of data written to CRC0FLIP is read back bit reversed. For example, if 0xC0 is written to CRC0FLIP, the
data read back is 0x03. Bit reversal is a useful mathematical function used in algorithms such as the FFT.
SFR Definition 24.6. CRC0FLIP: CRC Bit Flip
Bit
7
6
5
4
3
2
1
0
CRC0FLIP[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xCF
Bit Name
7:0 CRC0FLIP[7:0] CRC0 Bit Flip.
Function
Any byte written to CRC0FLIP is read back in a bit-reversed order, i.e. the written
LSB becomes the MSB. For example:
If 0xC0 is written to CRC0FLIP, the data read back will be 0x03.
If 0x05 is written to CRC0FLIP, the data read back will be 0xA0.
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25. Enhanced Serial Peripheral Interface (SPI0)
The Enhanced Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous
serial bus. SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports mul-
tiple masters and slaves on a single SPI bus. The slave-select (NSS) signal can be configured as an input
to select SPI0 in slave mode, or to disable Master Mode operation in a multi-master environment, avoiding
contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS can
also be configured as a chip-select output in master mode, or disabled for 3-wire operation. Additional gen-
eral purpose port I/O pins can be used to select multiple slave devices in master mode.
SFR Bus
SPI0CKR
SPI0CFG
SPI0CN
Clock Divide
Logic
SYSCLK
SPI CONTROL LOGIC
SPI IRQ
Data Path
Control
Pin Interface
Control
MOSI
Tx Data
C
R
O
S
S
B
A
R
SPI0DAT
SCK
MISO
NSS
Transmit Data Buffer
Pin
Control
Logic
Port I/O
Shift Register
Rx Data
7 6 5 4 3 2 1 0
Receive Data Buffer
Read
SPI0DAT
Write
SPI0DAT
SFR Bus
Figure 25.1. SPI Block Diagram
Rev. 1.0
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C8051F80x-83x
25.1. Signal Descriptions
The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below.
25.1.1. Master Out, Slave In (MOSI)
The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices. It
is used to serially transfer data from the master to the slave. This signal is an output when SPI0 is operat-
ing as a master and an input when SPI0 is operating as a slave. Data is transferred most-significant bit
first. When configured as a master, MOSI is driven by the MSB of the shift register in both 3- and 4-wire
mode.
25.1.2. Master In, Slave Out (MISO)
The master-in, slave-out (MISO) signal is an output from a slave device and an input to the master device.
It is used to serially transfer data from the slave to the master. This signal is an input when SPI0 is operat-
ing as a master and an output when SPI0 is operating as a slave. Data is transferred most-significant bit
first. The MISO pin is placed in a high-impedance state when the SPI module is disabled and when the SPI
operates in 4-wire mode as a slave that is not selected. When acting as a slave in 3-wire mode, MISO is
always driven by the MSB of the shift register.
25.1.3. Serial Clock (SCK)
The serial clock (SCK) signal is an output from the master device and an input to slave devices. It is used
to synchronize the transfer of data between the master and slave on the MOSI and MISO lines. SPI0 gen-
erates this signal when operating as a master. The SCK signal is ignored by a SPI slave when the slave is
not selected (NSS = 1) in 4-wire slave mode.
25.1.4. Slave Select (NSS)
The function of the slave-select (NSS) signal is dependent on the setting of the NSSMD1 and NSSMD0
bits in the SPI0CN register. There are three possible modes that can be selected with these bits:
1. NSSMD[1:0] = 00: 3-Wire Master or 3-Wire Slave Mode: SPI0 operates in 3-wire mode, and NSS is
disabled. When operating as a slave device, SPI0 is always selected in 3-wire mode. Since no select
signal is present, SPI0 must be the only slave on the bus in 3-wire mode. This is intended for point-to-
point communication between a master and one slave.
2. NSSMD[1:0] = 01: 4-Wire Slave or Multi-Master Mode: SPI0 operates in 4-wire mode, and NSS is
enabled as an input. When operating as a slave, NSS selects the SPI0 device. When operating as a
master, a 1-to-0 transition of the NSS signal disables the master function of SPI0 so that multiple
master devices can be used on the same SPI bus.
3. NSSMD[1:0] = 1x: 4-Wire Master Mode: SPI0 operates in 4-wire mode, and NSS is enabled as an
output. The setting of NSSMD0 determines what logic level the NSS pin will output. This configuration
should only be used when operating SPI0 as a master device.
See Figure 25.2, Figure 25.3, and Figure 25.4 for typical connection diagrams of the various operational
modes. Note that the setting of NSSMD bits affects the pinout of the device. When in 3-wire master or
3-wire slave mode, the NSS pin will not be mapped by the crossbar. In all other modes, the NSS signal will
be mapped to a pin on the device. See Section “23. Port Input/Output” on page 138 for general purpose
port I/O and crossbar information.
25.2. SPI0 Master Mode Operation
A SPI master device initiates all data transfers on a SPI bus. SPI0 is placed in master mode by setting the
Master Enable flag (MSTEN, SPI0CN.6). Writing a byte of data to the SPI0 data register (SPI0DAT) when
in master mode writes to the transmit buffer. If the SPI shift register is empty, the byte in the transmit buffer
is moved to the shift register, and a data transfer begins. The SPI0 master immediately shifts out the data
serially on the MOSI line while providing the serial clock on SCK. The SPIF (SPI0CN.7) flag is set to logic
1 at the end of the transfer. If interrupts are enabled, an interrupt request is generated when the SPIF flag
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is set. While the SPI0 master transfers data to a slave on the MOSI line, the addressed SPI slave device
simultaneously transfers the contents of its shift register to the SPI master on the MISO line in a full-duplex
operation. Therefore, the SPIF flag serves as both a transmit-complete and receive-data-ready flag. The
data byte received from the slave is transferred MSB-first into the master's shift register. When a byte is
fully shifted into the register, it is moved to the receive buffer where it can be read by the processor by
reading SPI0DAT.
When configured as a master, SPI0 can operate in one of three different modes: multi-master mode, 3-wire
single-master mode, and 4-wire single-master mode. The default, multi-master mode is active when
NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In this mode, NSS is an input to the device, and
is used to disable the master SPI0 when another master is accessing the bus. When NSS is pulled low in
this mode, MSTEN (SPI0CN.6) and SPIEN (SPI0CN.0) are set to 0 to disable the SPI master device, and
a Mode Fault is generated (MODF, SPI0CN.5 = 1). Mode Fault will generate an interrupt if enabled. SPI0
must be manually re-enabled in software under these circumstances. In multi-master systems, devices will
typically default to being slave devices while they are not acting as the system master device. In multi-mas-
ter mode, slave devices can be addressed individually (if needed) using general-purpose I/O pins.
Figure 25.2 shows a connection diagram between two master devices in multiple-master mode.
3-wire single-master mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 0. In this
mode, NSS is not used, and is not mapped to an external port pin through the crossbar. Any slave devices
that must be addressed in this mode should be selected using general-purpose I/O pins. Figure 25.3
shows a connection diagram between a master device in 3-wire master mode and a slave device.
4-wire single-master mode is active when NSSMD1 (SPI0CN.3) = 1. In this mode, NSS is configured as an
output pin, and can be used as a slave-select signal for a single SPI device. In this mode, the output value
of NSS is controlled (in software) with the bit NSSMD0 (SPI0CN.2). Additional slave devices can be
addressed using general-purpose I/O pins. Figure 25.4 shows a connection diagram for a master device in
4-wire master mode and two slave devices.
NSS
MISO
MOSI
SCK
GPIO
MISO
MOSI
SCK
Master
Device 1
Master
Device 2
GPIO
NSS
Figure 25.2. Multiple-Master Mode Connection Diagram
Master
Device
Slave
Device
MISO
MOSI
SCK
MISO
MOSI
SCK
Figure 25.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram
Rev. 1.0
169
C8051F80x-83x
MISO
MOSI
SCK
MISO
MOSI
SCK
Master
Device
Slave
Device
NSS
NSS
GPIO
MISO
MOSI
SCK
Slave
Device
NSS
Figure 25.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram
25.3. SPI0 Slave Mode Operation
When SPI0 is enabled and not configured as a master, it will operate as a SPI slave. As a slave, bytes are
shifted in through the MOSI pin and out through the MISO pin by a master device controlling the SCK sig-
nal. A bit counter in the SPI0 logic counts SCK edges. When 8 bits have been shifted through the shift reg-
ister, the SPIF flag is set to logic 1, and the byte is copied into the receive buffer. Data is read from the
receive buffer by reading SPI0DAT. A slave device cannot initiate transfers. Data to be transferred to the
master device is pre-loaded into the shift register by writing to SPI0DAT. Writes to SPI0DAT are double-
buffered, and are placed in the transmit buffer first. If the shift register is empty, the contents of the transmit
buffer will immediately be transferred into the shift register. When the shift register already contains data,
the SPI will load the shift register with the transmit buffer’s contents after the last SCK edge of the next (or
current) SPI transfer.
When configured as a slave, SPI0 can be configured for 4-wire or 3-wire operation. The default, 4-wire
slave mode, is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In 4-wire mode, the
NSS signal is routed to a port pin and configured as a digital input. SPI0 is enabled when NSS is logic 0,
and disabled when NSS is logic 1. The bit counter is reset on a falling edge of NSS. Note that the NSS sig-
nal must be driven low at least 2 system clocks before the first active edge of SCK for each byte transfer.
Figure 25.4 shows a connection diagram between two slave devices in 4-wire slave mode and a master
device.
3-wire slave mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 0. NSS is not
used in this mode, and is not mapped to an external port pin through the crossbar. Since there is no way of
uniquely addressing the device in 3-wire slave mode, SPI0 must be the only slave device present on the
bus. It is important to note that in 3-wire slave mode there is no external means of resetting the bit counter
that determines when a full byte has been received. The bit counter can only be reset by disabling and re-
enabling SPI0 with the SPIEN bit. Figure 25.3 shows a connection diagram between a slave device in 3-
wire slave mode and a master device.
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25.4. SPI0 Interrupt Sources
When SPI0 interrupts are enabled, the following four flags will generate an interrupt when they are set to
logic 1:
All of the following bits must be cleared by software.
The SPI Interrupt Flag, SPIF (SPI0CN.7) is set to logic 1 at the end of each byte transfer. This flag can
occur in all SPI0 modes.
The Write Collision Flag, WCOL (SPI0CN.6) is set to logic 1 if a write to SPI0DAT is attempted when
the transmit buffer has not been emptied to the SPI shift register. When this occurs, the write to
SPI0DAT will be ignored, and the transmit buffer will not be written.This flag can occur in all SPI0
modes.
The Mode Fault Flag MODF (SPI0CN.5) is set to logic 1 when SPI0 is configured as a master, and for
multi-master mode and the NSS pin is pulled low. When a Mode Fault occurs, the MSTEN and SPIEN
bits in SPI0CN are set to logic 0 to disable SPI0 and allow another master device to access the bus.
The Receive Overrun Flag RXOVRN (SPI0CN.4) is set to logic 1 when configured as a slave, and a
transfer is completed and the receive buffer still holds an unread byte from a previous transfer. The new
byte is not transferred to the receive buffer, allowing the previously received data byte to be read. The
data byte which caused the overrun is lost.
25.5. Serial Clock Phase and Polarity
Four combinations of serial clock phase and polarity can be selected using the clock control bits in the
SPI0 Configuration Register (SPI0CFG). The CKPHA bit (SPI0CFG.5) selects one of two clock phases
(edge used to latch the data). The CKPOL bit (SPI0CFG.4) selects between an active-high or active-low
clock. Both master and slave devices must be configured to use the same clock phase and polarity. SPI0
should be disabled (by clearing the SPIEN bit, SPI0CN.0) when changing the clock phase or polarity. The
clock and data line relationships for master mode are shown in Figure 25.5. For slave mode, the clock and
data relationships are shown in Figure 25.6 and Figure 25.7. Note that CKPHA should be set to 0 on both
the master and slave SPI when communicating between two Silicon Labs C8051 devices.
The SPI0 Clock Rate Register (SPI0CKR) as shown in SFR Definition 25.3 controls the master mode
serial clock frequency. This register is ignored when operating in slave mode. When the SPI is configured
as a master, the maximum data transfer rate (bits/sec) is one-half the system clock frequency or 12.5 MHz,
whichever is slower. When the SPI is configured as a slave, the maximum data transfer rate (bits/sec) for
full-duplex operation is 1/10 the system clock frequency, provided that the master issues SCK, NSS (in 4-
wire slave mode), and the serial input data synchronously with the slave’s system clock. If the master
issues SCK, NSS, and the serial input data asynchronously, the maximum data transfer rate (bits/sec)
must be less than 1/10 the system clock frequency. In the special case where the master only wants to
transmit data to the slave and does not need to receive data from the slave (i.e. half-duplex operation), the
SPI slave can receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency.
This is provided that the master issues SCK, NSS, and the serial input data synchronously with the slave’s
system clock.
Rev. 1.0
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SCK
(CKPOL=0, CKPHA=0)
SCK
(CKPOL=0, CKPHA=1)
SCK
(CKPOL=1, CKPHA=0)
SCK
(CKPOL=1, CKPHA=1)
MISO/MOSI
MSB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
NSS (Must Remain High
in Multi-Master Mode)
Figure 25.5. Master Mode Data/Clock Timing
SCK
(CKPOL=0, CKPHA=0)
SCK
(CKPOL=1, CKPHA=0)
MOSI
MSB
MSB
Bit 6
Bit 6
Bit 5
Bit 5
Bit 4
Bit 4
Bit 3
Bit 3
Bit 2
Bit 2
Bit 1
Bit 0
MISO
Bit 1
Bit 0
NSS (4-Wire Mode)
Figure 25.6. Slave Mode Data/Clock Timing (CKPHA = 0)
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SCK
(CKPOL=0, CKPHA=1)
SCK
(CKPOL=1, CKPHA=1)
MOSI
MSB
MSB
Bit 6
Bit 6
Bit 5
Bit 5
Bit 4
Bit 4
Bit 3
Bit 3
Bit 2
Bit 2
Bit 1
Bit 1
Bit 0
MISO
Bit 0
NSS (4-Wire Mode)
Figure 25.7. Slave Mode Data/Clock Timing (CKPHA = 1)
25.6. SPI Special Function Registers
SPI0 is accessed and controlled through four special function registers in the system controller: SPI0CN
Control Register, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate
Register. The four special function registers related to the operation of the SPI0 Bus are described in the
following figures.
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SFR Definition 25.1. SPI0CFG: SPI0 Configuration
Bit
7
6
5
4
3
2
1
0
SPIBSY
MSTEN
CKPHA
CKPOL
SLVSEL
NSSIN
SRMT
RXBMT
Name
Type
Reset
R
0
R/W
0
R/W
0
R/W
0
R
0
R
1
R
1
R
1
SFR Address = 0xA1
Bit
Name
Function
7
SPIBSY
SPI Busy.
This bit is set to logic 1 when a SPI transfer is in progress (master or slave mode).
6
5
4
3
MSTEN
CKPHA
CKPOL
SLVSEL
Master Mode Enable.
0: Disable master mode. Operate in slave mode.
1: Enable master mode. Operate as a master.
SPI0 Clock Phase.
*
0: Data centered on first edge of SCK period.
1: Data centered on second edge of SCK period.
*
SPI0 Clock Polarity.
0: SCK line low in idle state.
1: SCK line high in idle state.
Slave Selected Flag.
This bit is set to logic 1 whenever the NSS pin is low indicating SPI0 is the selected
slave. It is cleared to logic 0 when NSS is high (slave not selected). This bit does
not indicate the instantaneous value at the NSS pin, but rather a de-glitched ver-
sion of the pin input.
2
1
NSSIN
SRMT
NSS Instantaneous Pin Input.
This bit mimics the instantaneous value that is present on the NSS port pin at the
time that the register is read. This input is not de-glitched.
Shift Register Empty (valid in slave mode only).
This bit will be set to logic 1 when all data has been transferred in/out of the shift
register, and there is no new information available to read from the transmit buffer
or write to the receive buffer. It returns to logic 0 when a data byte is transferred to
the shift register from the transmit buffer or by a transition on SCK. SRMT = 1 when
in Master Mode.
0
RXBMT
Receive Buffer Empty (valid in slave mode only).
This bit will be set to logic 1 when the receive buffer has been read and contains no
new information. If there is new information available in the receive buffer that has
not been read, this bit will return to logic 0. RXBMT = 1 when in Master Mode.
Note: In slave mode, data on MOSI is sampled in the center of each data bit. In master mode, data on MISO is
sampled one SYSCLK before the end of each data bit, to provide maximum settling time for the slave device.
See Table 25.1 for timing parameters.
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SFR Definition 25.2. SPI0CN: SPI0 Control
Bit
7
6
5
4
3
2
1
0
SPIF
WCOL
MODF
RXOVRN
NSSMD[1:0]
R/W
TXBMT
SPIEN
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R
1
R/W
0
0
1
SFR Address = 0xF8; Bit-Addressable
Bit
Name
Function
7
SPIF
SPI0 Interrupt Flag.
This bit is set to logic 1 by hardware at the end of a data transfer. If SPI interrupts
are enabled, an interrupt will be generated. This bit is not automatically cleared by
hardware, and must be cleared by software.
6
5
4
WCOL
MODF
Write Collision Flag.
This bit is set to logic 1 if a write to SPI0DAT is attempted when TXBMT is 0. When
this occurs, the write to SPI0DAT will be ignored, and the transmit buffer will not be
written. If SPI interrupts are enabled, an interrupt will be generated. This bit is not
automatically cleared by hardware, and must be cleared by software.
Mode Fault Flag.
This bit is set to logic 1 by hardware when a master mode collision is detected
(NSS is low, MSTEN = 1, and NSSMD[1:0] = 01). If SPI interrupts are enabled, an
interrupt will be generated. This bit is not automatically cleared by hardware, and
must be cleared by software.
RXOVRN
Receive Overrun Flag (valid in slave mode only).
This bit is set to logic 1 by hardware when the receive buffer still holds unread data
from a previous transfer and the last bit of the current transfer is shifted into the
SPI0 shift register. If SPI interrupts are enabled, an interrupt will be generated. This
bit is not automatically cleared by hardware, and must be cleared by software.
3:2 NSSMD[1:0] Slave Select Mode.
Selects between the following NSS operation modes:
(See Section 25.2 and Section 25.3).
00: 3-Wire Slave or 3-Wire Master Mode. NSS signal is not routed to a port pin.
01: 4-Wire Slave or Multi-Master Mode (Default). NSS is an input to the device.
1x: 4-Wire Single-Master Mode. NSS signal is mapped as an output from the
device and will assume the value of NSSMD0.
1
0
TXBMT
SPIEN
Transmit Buffer Empty.
This bit will be set to logic 0 when new data has been written to the transmit buffer.
When data in the transmit buffer is transferred to the SPI shift register, this bit will
be set to logic 1, indicating that it is safe to write a new byte to the transmit buffer.
SPI0 Enable.
0: SPI disabled.
1: SPI enabled.
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SFR Definition 25.3. SPI0CKR: SPI0 Clock Rate
Bit
7
6
5
4
3
2
1
0
SCR[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xA2
Bit
Name
Function
7:0
SCR[7:0]
SPI0 Clock Rate.
These bits determine the frequency of the SCK output when the SPI0 module is
configured for master mode operation. The SCK clock frequency is a divided ver-
sion of the system clock, and is given in the following equation, where SYSCLK is
the system clock frequency and SPI0CKR is the 8-bit value held in the SPI0CKR
register.
SYSCLK
fSCK = ----------------------------------------------------------
2 SPI0CKR[7:0] + 1
for 0 <= SPI0CKR <= 255
Example: If SYSCLK = 2 MHz and SPI0CKR = 0x04,
2000000
fSCK = -------------------------
2 4 + 1
fSCK = 200kHz
SFR Definition 25.4. SPI0DAT: SPI0 Data
Bit
7
6
5
4
3
2
1
0
SPI0DAT[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xA3
Bit Name
7:0 SPI0DAT[7:0] SPI0 Transmit and Receive Data.
Function
The SPI0DAT register is used to transmit and receive SPI0 data. Writing data to
SPI0DAT places the data into the transmit buffer and initiates a transfer when in
Master Mode. A read of SPI0DAT returns the contents of the receive buffer.
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SCK*
T
T
MCKL
MCKH
T
T
MIS
MIH
MISO
MOSI
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
Figure 25.8. SPI Master Timing (CKPHA = 0)
SCK*
T
T
MCKH
MCKL
T
T
MIH
MIS
MISO
MOSI
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
Figure 25.9. SPI Master Timing (CKPHA = 1)
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NSS
T
T
T
SD
SE
CKL
SCK*
T
CKH
T
T
SIH
SIS
MOSI
T
T
T
SDZ
SEZ
SOH
MISO
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
Figure 25.10. SPI Slave Timing (CKPHA = 0)
NSS
T
T
T
SD
SE
CKL
SCK*
T
CKH
T
T
SIH
SIS
MOSI
T
T
T
SDZ
T
SOH
SLH
SEZ
MISO
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
Figure 25.11. SPI Slave Timing (CKPHA = 1)
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Table 25.1. SPI Slave Timing Parameters
Parameter
Description
Min
Max
Units
Master Mode Timing (See Figure 25.8 and Figure 25.9)
T
T
T
T
SCK High Time
1 x T
—
—
—
—
ns
ns
ns
ns
MCKH
MCKL
MIS
SYSCLK
SYSCLK
SCK Low Time
1 x T
1 x T
MISO Valid to SCK Shift Edge
SCK Shift Edge to MISO Change
+ 20
SYSCLK
0
MIH
Slave Mode Timing (See Figure 25.10 and Figure 25.11)
T
T
T
T
T
T
T
T
T
T
NSS Falling to First SCK Edge
Last SCK Edge to NSS Rising
NSS Falling to MISO Valid
NSS Rising to MISO High-Z
SCK High Time
2 x T
2 x T
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SE
SYSCLK
SD
SYSCLK
—
4 x T
SYSCLK
SEZ
SDZ
CKH
CKL
SIS
—
4 x T
SYSCLK
5 x T
5 x T
2 x T
2 x T
—
SYSCLK
SYSCLK
SYSCLK
SCK Low Time
—
—
—
MOSI Valid to SCK Sample Edge
SCK Sample Edge to MOSI Change
SCK Shift Edge to MISO Change
SIH
SOH
SLH
SYSCLK
—
4 x T
8 x T
SYSCLK
SYSCLK
Last SCK Edge to MISO Change
(CKPHA = 1 ONLY)
6 x T
SYSCLK
Note: T
is equal to one period of the device system clock (SYSCLK).
SYSCLK
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26. SMBus
The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System
2
Management Bus Specification, version 1.1, and compatible with the I C serial bus. Reads and writes to
the interface by the system controller are byte oriented with the SMBus interface autonomously controlling
the serial transfer of the data. Data can be transferred at up to 1/20th of the system clock as a master or
slave (this can be faster than allowed by the SMBus specification, depending on the system clock used). A
method of extending the clock-low duration is available to accommodate devices with different speed
capabilities on the same bus.
The SMBus interface may operate as a master and/or slave, and may function on a bus with multiple mas-
ters. The SMBus provides control of SDA (serial data), SCL (serial clock) generation and synchronization,
arbitration logic, and START/STOP control and generation. The SMBus peripheral can be fully driven by
software (i.e., software accepts/rejects slave addresses, and generates ACKs), or hardware slave address
recognition and automatic ACK generation can be enabled to minimize software overhead. A block dia-
gram of the SMBus peripheral and the associated SFRs is shown in Figure 26.1.
SMB0CN
SMB0CF
M T S S A A A S
E
I
B E S S S S
A X T T C R C
S M A O K B K
I
N N U X M M M M
S H S T B B B B
T O
E D
R E
R L
Q O
S
M
B
Y H T F C C
O O T S S
L E E 1 0
D
T
00
01
10
11
T0 Overflow
T1 Overflow
TMR2H Overflow
TMR2L Overflow
SCL
SMBUS CONTROL LOGIC
Arbitration
FILTER
Interrupt
Request
SCL Synchronization
SCL Generation (Master Mode)
SDA Control
SCL
Control
C
R
O
S
S
B
A
R
N
Hardware Slave Address Recognition
Hardware ACK Generation
Port I/O
Data Path
SDA
Control
IRQ Generation
Control
SMB0DAT
7 6 5 4 3 2 1 0
SDA
FILTER
S S S S S S S G S S S S S S S E
L L L L L L L C L L L L L L L H
V V V V V V V
6 5 4 3 2 1 0
V V V V V V V A
M M M M M M M C
6 5 4 3 2 1 0 K
SMB0ADR
SMB0ADM
N
Figure 26.1. SMBus Block Diagram
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26.1. Supporting Documents
It is assumed the reader is familiar with or has access to the following supporting documents:
2
1. The I C-Bus and How to Use It (including specifications), Philips Semiconductor.
2
2. The I C-Bus Specification—Version 2.0, Philips Semiconductor.
3. System Management Bus Specification—Version 1.1, SBS Implementers Forum.
26.2. SMBus Configuration
Figure 26.2 shows a typical SMBus configuration. The SMBus specification allows any recessive voltage
between 3.0 V and 5.0 V; different devices on the bus may operate at different voltage levels. The bi-direc-
tional SCL (serial clock) and SDA (serial data) lines must be connected to a positive power supply voltage
through a pullup resistor or similar circuit. Every device connected to the bus must have an open-drain or
open-collector output for both the SCL and SDA lines, so that both are pulled high (recessive state) when
the bus is free. The maximum number of devices on the bus is limited only by the requirement that the rise
and fall times on the bus not exceed 300 ns and 1000 ns, respectively.
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
Master
Device
Slave
Device 1
Slave
Device 2
SDA
SCL
Figure 26.2. Typical SMBus Configuration
26.3. SMBus Operation
Two types of data transfers are possible: data transfers from a master transmitter to an addressed slave
receiver (WRITE), and data transfers from an addressed slave transmitter to a master receiver (READ).
The master device initiates both types of data transfers and provides the serial clock pulses on SCL. The
SMBus interface may operate as a master or a slave, and multiple master devices on the same bus are
supported. If two or more masters attempt to initiate a data transfer simultaneously, an arbitration scheme
is employed with a single master always winning the arbitration. Note that it is not necessary to specify one
device as the Master in a system; any device who transmits a START and a slave address becomes the
master for the duration of that transfer.
A typical SMBus transaction consists of a START condition followed by an address byte (Bits7–1: 7-bit
slave address; Bit0: R/W direction bit), one or more bytes of data, and a STOP condition. Bytes that are
received (by a master or slave) are acknowledged (ACK) with a low SDA during a high SCL (see
Figure 26.3). If the receiving device does not ACK, the transmitting device will read a NACK (not acknowl-
edge), which is a high SDA during a high SCL.
The direction bit (R/W) occupies the least-significant bit position of the address byte. The direction bit is set
to logic 1 to indicate a "READ" operation and cleared to logic 0 to indicate a "WRITE" operation.
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All transactions are initiated by a master, with one or more addressed slave devices as the target. The
master generates the START condition and then transmits the slave address and direction bit. If the trans-
action is a WRITE operation from the master to the slave, the master transmits the data a byte at a time
waiting for an ACK from the slave at the end of each byte. For READ operations, the slave transmits the
data waiting for an ACK from the master at the end of each byte. At the end of the data transfer, the master
generates a STOP condition to terminate the transaction and free the bus. Figure 26.3 illustrates a typical
SMBus transaction.
SCL
SDA
SLA6
SLA5-0
R/W
D7
D6-0
START
Slave Address + R/W
ACK
Data Byte
NACK
STOP
Figure 26.3. SMBus Transaction
26.3.1. Transmitter Vs. Receiver
On the SMBus communications interface, a device is the “transmitter” when it is sending an address or
data byte to another device on the bus. A device is a “receiver” when an address or data byte is being sent
to it from another device on the bus. The transmitter controls the SDA line during the address or data byte.
After each byte of address or data information is sent by the transmitter, the receiver sends an ACK or
NACK bit during the ACK phase of the transfer, during which time the receiver controls the SDA line.
26.3.2. Arbitration
A master may start a transfer only if the bus is free. The bus is free after a STOP condition or after the SCL
and SDA lines remain high for a specified time (see Section “26.3.5. SCL High (SMBus Free) Timeout” on
page 183). In the event that two or more devices attempt to begin a transfer at the same time, an arbitra-
tion scheme is employed to force one master to give up the bus. The master devices continue transmitting
until one attempts a HIGH while the other transmits a LOW. Since the bus is open-drain, the bus will be
pulled LOW. The master attempting the HIGH will detect a LOW SDA and lose the arbitration. The winning
master continues its transmission without interruption; the losing master becomes a slave and receives the
rest of the transfer if addressed. This arbitration scheme is non-destructive: one device always wins, and
no data is lost.
26.3.3. Clock Low Extension
SMBus provides a clock synchronization mechanism, similar to I2C, which allows devices with different
speed capabilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow
slower slave devices to communicate with faster masters. The slave may temporarily hold the SCL line
LOW to extend the clock low period, effectively decreasing the serial clock frequency.
26.3.4. SCL Low Timeout
If the SCL line is held low by a slave device on the bus, no further communication is possible. Furthermore,
the master cannot force the SCL line high to correct the error condition. To solve this problem, the SMBus
protocol specifies that devices participating in a transfer must detect any clock cycle held low longer than
25 ms as a “timeout” condition. Devices that have detected the timeout condition must reset the communi-
cation no later than 10 ms after detecting the timeout condition.
When the SMBTOE bit in SMB0CF is set, Timer 3 is used to detect SCL low timeouts. Timer 3 is forced to
reload when SCL is high, and allowed to count when SCL is low. With Timer 3 enabled and configured to
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overflow after 25 ms (and SMBTOE set), the Timer 3 interrupt service routine can be used to reset (disable
and re-enable) the SMBus in the event of an SCL low timeout.
26.3.5. SCL High (SMBus Free) Timeout
The SMBus specification stipulates that if the SCL and SDA lines remain high for more that 50 µs, the bus
is designated as free. When the SMBFTE bit in SMB0CF is set, the bus will be considered free if SCL and
SDA remain high for more than 10 SMBus clock source periods (as defined by the timer configured for the
SMBus clock source). If the SMBus is waiting to generate a Master START, the START will be generated
following this timeout. A clock source is required for free timeout detection, even in a slave-only implemen-
tation.
26.4. Using the SMBus
The SMBus can operate in both Master and Slave modes. The interface provides timing and shifting con-
trol for serial transfers; higher level protocol is determined by user software. The SMBus interface provides
the following application-independent features:
Byte-wise serial data transfers
Clock signal generation on SCL (Master Mode only) and SDA data synchronization
Timeout/bus error recognition, as defined by the SMB0CF configuration register
START/STOP timing, detection, and generation
Bus arbitration
Interrupt generation
Status information
Optional hardware recognition of slave address and automatic acknowledgement of address/data
SMBus interrupts are generated for each data byte or slave address that is transferred. When hardware
acknowledgement is disabled, the point at which the interrupt is generated depends on whether the hard-
ware is acting as a data transmitter or receiver. When a transmitter (i.e., sending address/data, receiving
an ACK), this interrupt is generated after the ACK cycle so that software may read the received ACK value;
when receiving data (i.e., receiving address/data, sending an ACK), this interrupt is generated before the
ACK cycle so that software may define the outgoing ACK value. If hardware acknowledgement is enabled,
these interrupts are always generated after the ACK cycle. See Section 26.5 for more details on transmis-
sion sequences.
Interrupts are also generated to indicate the beginning of a transfer when a master (START generated), or
the end of a transfer when a slave (STOP detected). Software should read the SMB0CN (SMBus Control
register) to find the cause of the SMBus interrupt. The SMB0CN register is described in Section 26.4.2;
Table 26.5 provides a quick SMB0CN decoding reference.
26.4.1. SMBus Configuration Register
The SMBus Configuration register (SMB0CF) is used to enable the SMBus Master and/or Slave modes,
select the SMBus clock source, and select the SMBus timing and timeout options. When the ENSMB bit is
set, the SMBus is enabled for all master and slave events. Slave events may be disabled by setting the
INH bit. With slave events inhibited, the SMBus interface will still monitor the SCL and SDA pins; however,
the interface will NACK all received addresses and will not generate any slave interrupts. When the INH bit
is set, all slave events will be inhibited following the next START (interrupts will continue for the duration of
the current transfer).
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Table 26.1. SMBus Clock Source Selection
SMBCS1 SMBCS0
SMBus Clock Source
0
0
1
1
0
1
0
1
Timer 0 Overflow
Timer 1 Overflow
Timer 2 High Byte Overflow
Timer 2 Low Byte Overflow
The SMBCS1–0 bits select the SMBus clock source, which is used only when operating as a master or
when the Free Timeout detection is enabled. When operating as a master, overflows from the selected
source determine the absolute minimum SCL low and high times as defined in Equation 26.1. Note that the
selected clock source may be shared by other peripherals so long as the timer is left running at all times.
For example, Timer 1 overflows may generate the SMBus and UART baud rates simultaneously. Timer
configuration is covered in Section “28. Timers” on page 209.
1
THighMin = TLowMin = ---------------------------------------------
fClockSourceOverflow
Equation 26.1. Minimum SCL High and Low Times
The selected clock source should be configured to establish the minimum SCL High and Low times as per
Equation 26.1. When the interface is operating as a master (and SCL is not driven or extended by any
other devices on the bus), the typical SMBus bit rate is approximated by Equation 26.2.
fClockSourceOverflow
BitRate = ---------------------------------------------
3
Equation 26.2. Typical SMBus Bit Rate
Figure 26.4 shows the typical SCL generation described by Equation 26.2. Notice that T
is typically
HIGH
twice as large as T
. The actual SCL output may vary due to other devices on the bus (SCL may be
LOW
extended low by slower slave devices, or driven low by contending master devices). The bit rate when
operating as a master will never exceed the limits defined by equation Equation 26.1.
Timer Source
Overflows
SCL
TLow
THigh
SCL High Timeout
Figure 26.4. Typical SMBus SCL Generation
Setting the EXTHOLD bit extends the minimum setup and hold times for the SDA line. The minimum SDA
setup time defines the absolute minimum time that SDA is stable before SCL transitions from low-to-high.
The minimum SDA hold time defines the absolute minimum time that the current SDA value remains stable
after SCL transitions from high-to-low. EXTHOLD should be set so that the minimum setup and hold times
meet the SMBus Specification requirements of 250 ns and 300 ns, respectively. Table 26.2 shows the min-
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imum setup and hold times for the two EXTHOLD settings. Setup and hold time extensions are typically
necessary when SYSCLK is above 10 MHz.
Table 26.2. Minimum SDA Setup and Hold Times
EXTHOLD
Minimum SDA Setup Time
Minimum SDA Hold Time
T
– 4 system clocks
or
low
0
1
3 system clocks
12 system clocks
*
1 system clock + s/w delay
11 system clocks
Note: Setup Time for ACK bit transmissions and the MSB of all data transfers. When using
software acknowledgement, the s/w delay occurs between the time SMB0DAT or
ACK is written and when SI is cleared. Note that if SI is cleared in the same write
that defines the outgoing ACK value, s/w delay is zero.
With the SMBTOE bit set, Timer 3 should be configured to overflow after 25 ms in order to detect SCL low
timeouts (see Section “26.3.4. SCL Low Timeout” on page 182). The SMBus interface will force Timer 3 to
reload while SCL is high, and allow Timer 3 to count when SCL is low. The Timer 3 interrupt service routine
should be used to reset SMBus communication by disabling and re-enabling the SMBus.
SMBus Free Timeout detection can be enabled by setting the SMBFTE bit. When this bit is set, the bus will
be considered free if SDA and SCL remain high for more than 10 SMBus clock source periods (see
Figure 26.4).
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SFR Definition 26.1. SMB0CF: SMBus Clock/Configuration
Bit
7
6
5
4
3
2
1
0
ENSMB
INH
BUSY
EXTHOLD SMBTOE SMBFTE
SMBCS[1:0]
R/W
Name
Type
Reset
R/W
0
R/W
0
R
0
R/W
0
R/W
0
R/W
0
0
0
SFR Address = 0xC1
Bit
Name
Function
7
ENSMB
SMBus Enable.
This bit enables the SMBus interface when set to 1. When enabled, the interface
constantly monitors the SDA and SCL pins.
6
INH
SMBus Slave Inhibit.
When this bit is set to logic 1, the SMBus does not generate an interrupt when slave
events occur. This effectively removes the SMBus slave from the bus. Master Mode
interrupts are not affected.
5
4
BUSY
SMBus Busy Indicator.
This bit is set to logic 1 by hardware when a transfer is in progress. It is cleared to
logic 0 when a STOP or free-timeout is sensed.
EXTHOLD SMBus Setup and Hold Time Extension Enable.
This bit controls the SDA setup and hold times according to Table 26.2.
0: SDA Extended Setup and Hold Times disabled.
1: SDA Extended Setup and Hold Times enabled.
3
SMBTOE SMBus SCL Timeout Detection Enable.
This bit enables SCL low timeout detection. If set to logic 1, the SMBus forces
Timer 3 to reload while SCL is high and allows Timer 3 to count when SCL goes low.
If Timer 3 is configured to Split Mode, only the High Byte of the timer is held in reload
while SCL is high. Timer 3 should be programmed to generate interrupts at 25 ms,
and the Timer 3 interrupt service routine should reset SMBus communication.
2
SMBFTE SMBus Free Timeout Detection Enable.
When this bit is set to logic 1, the bus will be considered free if SCL and SDA remain
high for more than 10 SMBus clock source periods.
1:0 SMBCS[1:0] SMBus Clock Source Selection.
These two bits select the SMBus clock source, which is used to generate the SMBus
bit rate. The selected device should be configured according to Equation 26.1.
00: Timer 0 Overflow
01: Timer 1 Overflow
10: Timer 2 High Byte Overflow
11: Timer 2 Low Byte Overflow
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26.4.2. SMB0CN Control Register
SMB0CN is used to control the interface and to provide status information (see SFR Definition 26.2). The
higher four bits of SMB0CN (MASTER, TXMODE, STA, and STO) form a status vector that can be used to
jump to service routines. MASTER indicates whether a device is the master or slave during the current
transfer. TXMODE indicates whether the device is transmitting or receiving data for the current byte.
STA and STO indicate that a START and/or STOP has been detected or generated since the last SMBus
interrupt. STA and STO are also used to generate START and STOP conditions when operating as a mas-
ter. Writing a 1 to STA will cause the SMBus interface to enter Master Mode and generate a START when
the bus becomes free (STA is not cleared by hardware after the START is generated). Writing a 1 to STO
while in Master Mode will cause the interface to generate a STOP and end the current transfer after the
next ACK cycle. If STO and STA are both set (while in Master Mode), a STOP followed by a START will be
generated.
The ARBLOST bit indicates that the interface has lost an arbitration. This may occur anytime the interface
is transmitting (master or slave). A lost arbitration while operating as a slave indicates a bus error condi-
tion. ARBLOST is cleared by hardware each time SI is cleared.
The SI bit (SMBus Interrupt Flag) is set at the beginning and end of each transfer, after each byte frame, or
when an arbitration is lost; see Table 26.3 for more details.
Important Note About the SI Bit: The SMBus interface is stalled while SI is set; thus SCL is held low, and
the bus is stalled until software clears SI.
26.4.2.1. Software ACK Generation
When the EHACK bit in register SMB0ADM is cleared to 0, the firmware on the device must detect incom-
ing slave addresses and ACK or NACK the slave address and incoming data bytes. As a receiver, writing
the ACK bit defines the outgoing ACK value; as a transmitter, reading the ACK bit indicates the value
received during the last ACK cycle. ACKRQ is set each time a byte is received, indicating that an outgoing
ACK value is needed. When ACKRQ is set, software should write the desired outgoing value to the ACK
bit before clearing SI. A NACK will be generated if software does not write the ACK bit before clearing SI.
SDA will reflect the defined ACK value immediately following a write to the ACK bit; however SCL will
remain low until SI is cleared. If a received slave address is not acknowledged, further slave events will be
ignored until the next START is detected.
26.4.2.2. Hardware ACK Generation
When the EHACK bit in register SMB0ADM is set to 1, automatic slave address recognition and ACK gen-
eration is enabled. More detail about automatic slave address recognition can be found in Section 26.4.3.
As a receiver, the value currently specified by the ACK bit will be automatically sent on the bus during the
ACK cycle of an incoming data byte. As a transmitter, reading the ACK bit indicates the value received on
the last ACK cycle. The ACKRQ bit is not used when hardware ACK generation is enabled. If a received
slave address is NACKed by hardware, further slave events will be ignored until the next START is
detected, and no interrupt will be generated.
Table 26.3 lists all sources for hardware changes to the SMB0CN bits. Refer to Table 26.5 for SMBus sta-
tus decoding using the SMB0CN register.
Rev. 1.0
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SFR Definition 26.2. SMB0CN: SMBus Control
Bit
7
6
5
4
3
2
1
0
MASTER TXMODE
STA
STO
ACKRQ ARBLOST
ACK
SI
Name
Type
Reset
R
0
R
0
R/W
0
R/W
0
R
0
R
0
R/W
0
R/W
0
SFR Address = 0xC0; Bit-Addressable
Bit
Name
Description
Read
Write
7
MASTER
0: SMBus operating in
slave mode.
1: SMBus operating in
master mode.
N/A
N/A
SMBus Master/Slave
Indicator. This read-only bit
indicates when the SMBus is
operating as a master.
6
TXMODE
0: SMBus in Receiver
Mode.
1: SMBus in Transmitter
Mode.
SMBus Transmit Mode
Indicator. This read-only bit
indicates when the SMBus is
operating as a transmitter.
5
4
STA
STO
0: No Start or repeated
Start detected.
1: Start or repeated Start
detected.
0: No Start generated.
1: When Configured as a
Master, initiates a START
or repeated START.
SMBus Start Flag.
0: No Stop condition
detected.
0: No STOP condition is
transmitted.
SMBus Stop Flag.
1: Stop condition detected 1: When configured as a
(if in Slave Mode) or pend- Master, causes a STOP
ing (if in Master Mode).
condition to be transmit-
ted after the next ACK
cycle.
Cleared by Hardware.
3
2
1
0
ACKRQ
ARBLOST
ACK
0: No Ack requested
1: ACK requested
N/A
SMBus Acknowledge
Request.
0: No arbitration error.
1: Arbitration Lost
N/A
SMBus Arbitration Lost
Indicator.
0: NACK received.
1: ACK received.
0: Send NACK
1: Send ACK
SMBus Acknowledge.
SI
0: Clear interrupt, and initi-
ate next state machine
event.
SMBus Interrupt Flag.
This bit is set by hardware
under the conditions listed in
Table 15.3. SI must be cleared
by software. While SI is set,
SCL is held low and the
SMBus is stalled.
0: No interrupt pending
1: Interrupt Pending
1: Force interrupt.
188
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Table 26.3. Sources for Hardware Changes to SMB0CN
Bit
Set by Hardware When:
A START is generated.
Cleared by Hardware When:
A STOP is generated.
Arbitration is lost.
A START is detected.
Arbitration is lost.
MASTER
START is generated.
SMB0DAT is written before the start of an
SMBus frame.
TXMODE
SMB0DAT is not written before the
start of an SMBus frame.
A START followed by an address byte is
received.
A STOP is detected while addressed as a
slave.
Must be cleared by software.
STA
STO
A pending STOP is generated.
Arbitration is lost due to a detected STOP.
A byte has been received and an ACK
response value is needed (only when
hardware ACK is not enabled).
A repeated START is detected as a
MASTER when STA is low (unwanted
repeated START).
After each ACK cycle.
Each time SI is cleared.
ACKRQ
SCL is sensed low while attempting to
generate a STOP or repeated START
condition.
ARBLOST
ACK
SDA is sensed low while transmitting a 1
(excluding ACK bits).
The incoming ACK value is low
(ACKNOWLEDGE).
The incoming ACK value is high
(NOT ACKNOWLEDGE).
Must be cleared by software.
A START has been generated.
Lost arbitration.
A byte has been transmitted and an
ACK/NACK received.
SI
A byte has been received.
A START or repeated START followed by a
slave address + R/W has been received.
A STOP has been received.
26.4.3. Hardware Slave Address Recognition
The SMBus hardware has the capability to automatically recognize incoming slave addresses and send an
ACK without software intervention. Automatic slave address recognition is enabled by setting the EHACK
bit in register SMB0ADM to 1. This will enable both automatic slave address recognition and automatic
hardware ACK generation for received bytes (as a master or slave). More detail on automatic hardware
ACK generation can be found in Section 26.4.2.2.
The registers used to define which address(es) are recognized by the hardware are the SMBus Slave
Address register (SFR Definition 26.3) and the SMBus Slave Address Mask register (SFR Definition 26.4).
A single address or range of addresses (including the General Call Address 0x00) can be specified using
these two registers. The most-significant seven bits of the two registers are used to define which
addresses will be ACKed. A 1 in bit positions of the slave address mask SLVM[6:0] enable a comparison
between the received slave address and the hardware’s slave address SLV[6:0] for those bits. A 0 in a bit
of the slave address mask means that bit will be treated as a “don’t care” for comparison purposes. In this
Rev. 1.0
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C8051F80x-83x
case, either a 1 or a 0 value are acceptable on the incoming slave address. Additionally, if the GC bit in
register SMB0ADR is set to 1, hardware will recognize the General Call Address (0x00). Table 26.4 shows
some example parameter settings and the slave addresses that will be recognized by hardware under
those conditions.
Table 26.4. Hardware Address Recognition Examples (EHACK = 1)
Hardware Slave Address Slave Address Mask
GC bit Slave Addresses Recognized by
Hardware
SLV[6:0]
SLVM[6:0]
0x34
0x34
0x34
0x34
0x70
0x7F
0x7F
0x7E
0x7E
0x73
0
1
0
1
0
0x34
0x34, 0x00 (General Call)
0x34, 0x35
0x34, 0x35, 0x00 (General Call)
0x70, 0x74, 0x78, 0x7C
190
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SFR Definition 26.3. SMB0ADR: SMBus Slave Address
Bit
7
6
5
4
3
2
1
0
SLV[6:0]
GC
Name
Type
Reset
R/W
0
R/W
0
0
0
0
0
0
0
SFR Address = 0xD7
Bit
Name
Function
7:1
SLV[6:0]
SMBus Hardware Slave Address.
Defines the SMBus Slave Address(es) for automatic hardware acknowledgement.
Only address bits which have a 1 in the corresponding bit position in SLVM[6:0]
are checked against the incoming address. This allows multiple addresses to be
recognized.
0
GC
General Call Address Enable.
When hardware address recognition is enabled (EHACK = 1), this bit will deter-
mine whether the General Call Address (0x00) is also recognized by hardware.
0: General Call Address is ignored.
1: General Call Address is recognized.
SFR Definition 26.4. SMB0ADM: SMBus Slave Address Mask
Bit
7
6
5
4
3
2
1
0
SLVM[6:0]
EHACK
Name
Type
Reset
R/W
1
R/W
0
1
1
1
1
1
1
SFR Address = 0xD6
Bit
Name
Function
7:1
SLVM[6:0]
SMBus Slave Address Mask.
Defines which bits of register SMB0ADR are compared with an incoming address
byte, and which bits are ignored. Any bit set to 1 in SLVM[6:0] enables compari-
sons with the corresponding bit in SLV[6:0]. Bits set to 0 are ignored (can be either
0 or 1 in the incoming address).
0
EHACK
Hardware Acknowledge Enable.
Enables hardware acknowledgement of slave address and received data bytes.
0: Firmware must manually acknowledge all incoming address and data bytes.
1: Automatic Slave Address Recognition and Hardware Acknowledge is Enabled.
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26.4.4. Data Register
The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been
received. Software may safely read or write to the data register when the SI flag is set. Software should not
attempt to access the SMB0DAT register when the SMBus is enabled and the SI flag is cleared to logic 0,
as the interface may be in the process of shifting a byte of data into or out of the register.
Data in SMB0DAT is always shifted out MSB first. After a byte has been received, the first bit of received
data is located at the MSB of SMB0DAT. While data is being shifted out, data on the bus is simultaneously
being shifted in. SMB0DAT always contains the last data byte present on the bus. In the event of lost arbi-
tration, the transition from master transmitter to slave receiver is made with the correct data or address in
SMB0DAT.
SFR Definition 26.5. SMB0DAT: SMBus Data
Bit
7
6
5
4
3
2
1
0
SMB0DAT[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xC2
Bit Name
7:0 SMB0DAT[7:0] SMBus Data.
Function
The SMB0DAT register contains a byte of data to be transmitted on the SMBus
serial interface or a byte that has just been received on the SMBus serial interface.
The CPU can read from or write to this register whenever the SI serial interrupt flag
(SMB0CN.0) is set to logic 1. The serial data in the register remains stable as long
as the SI flag is set. When the SI flag is not set, the system may be in the process
of shifting data in/out and the CPU should not attempt to access this register.
192
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26.5. SMBus Transfer Modes
The SMBus interface may be configured to operate as master and/or slave. At any particular time, it will be
operating in one of the following four modes: Master Transmitter, Master Receiver, Slave Transmitter, or
Slave Receiver. The SMBus interface enters Master Mode any time a START is generated, and remains in
Master Mode until it loses an arbitration or generates a STOP. An SMBus interrupt is generated at the end
of all SMBus byte frames. Note that the position of the ACK interrupt when operating as a receiver
depends on whether hardware ACK generation is enabled. As a receiver, the interrupt for an ACK occurs
before the ACK with hardware ACK generation disabled, and after the ACK when hardware ACK genera-
tion is enabled. As a transmitter, interrupts occur after the ACK, regardless of whether hardware ACK gen-
eration is enabled or not.
26.5.1. Write Sequence (Master)
During a write sequence, an SMBus master writes data to a slave device. The master in this transfer will be
a transmitter during the address byte, and a transmitter during all data bytes. The SMBus interface gener-
ates the START condition and transmits the first byte containing the address of the target slave and the
data direction bit. In this case the data direction bit (R/W) will be logic 0 (WRITE). The master then trans-
mits one or more bytes of serial data. After each byte is transmitted, an acknowledge bit is generated by
the slave. The transfer is ended when the STO bit is set and a STOP is generated. Note that the interface
will switch to Master Receiver Mode if SMB0DAT is not written following a Master Transmitter interrupt.
Figure 26.5 shows a typical master write sequence. Two transmit data bytes are shown, though any num-
ber of bytes may be transmitted. Notice that all of the “data byte transferred” interrupts occur after the ACK
cycle in this mode, regardless of whether hardware ACK generation is enabled.
Interrupts with Hardware ACK Enabled (EHACK = 1)
S
SLA
W
A
Data Byte
A
Data Byte
A
P
Interrupts with Hardware ACK Disabled (EHACK = 0)
S = START
P = STOP
A = ACK
Received by SMBus
Interface
W = WRITE
Transmitted by
SLA = Slave Address
SMBus Interface
Figure 26.5. Typical Master Write Sequence
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26.5.2. Read Sequence (Master)
During a read sequence, an SMBus master reads data from a slave device. The master in this transfer will
be a transmitter during the address byte, and a receiver during all data bytes. The SMBus interface gener-
ates the START condition and transmits the first byte containing the address of the target slave and the
data direction bit. In this case the data direction bit (R/W) will be logic 1 (READ). Serial data is then
received from the slave on SDA while the SMBus outputs the serial clock. The slave transmits one or more
bytes of serial data.
If hardware ACK generation is disabled, the ACKRQ is set to 1 and an interrupt is generated after each
received byte. Software must write the ACK bit at that time to ACK or NACK the received byte.
With hardware ACK generation enabled, the SMBus hardware will automatically generate the ACK/NACK,
and then post the interrupt. It is important to note that the appropriate ACK or NACK value should be
set up by the software prior to receiving the byte when hardware ACK generation is enabled.
Writing a 1 to the ACK bit generates an ACK; writing a 0 generates a NACK. Software should write a 0 to
the ACK bit for the last data transfer, to transmit a NACK. The interface exits Master Receiver Mode after
the STO bit is set and a STOP is generated. The interface will switch to Master Transmitter Mode if
SMB0DAT is written while an active Master Receiver. Figure 26.6 shows a typical master read sequence.
Two received data bytes are shown, though any number of bytes may be received. Notice that the ‘data
byte transferred’ interrupts occur at different places in the sequence, depending on whether hardware ACK
generation is enabled. The interrupt occurs before the ACK with hardware ACK generation disabled, and
after the ACK when hardware ACK generation is enabled.
Interrupts with Hardware ACK Enabled (EHACK = 1)
S
SLA
R
A
Data Byte
A
Data Byte
N
P
Interrupts with Hardware ACK Disabled (EHACK = 0)
S = START
P = STOP
A = ACK
Received by SMBus
Interface
N = NACK
R = READ
SLA = Slave Address
Transmitted by
SMBus Interface
Figure 26.6. Typical Master Read Sequence
194
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26.5.3. Write Sequence (Slave)
During a write sequence, an SMBus master writes data to a slave device. The slave in this transfer will be
a receiver during the address byte, and a receiver during all data bytes. When slave events are enabled
(INH = 0), the interface enters Slave Receiver Mode when a START followed by a slave address and direc-
tion bit (WRITE in this case) is received. If hardware ACK generation is disabled, upon entering Slave
Receiver Mode, an interrupt is generated and the ACKRQ bit is set. The software must respond to the
received slave address with an ACK, or ignore the received slave address with a NACK. If hardware ACK
generation is enabled, the hardware will apply the ACK for a slave address which matches the criteria set
up by SMB0ADR and SMB0ADM. The interrupt will occur after the ACK cycle.
If the received slave address is ignored (by software or hardware), slave interrupts will be inhibited until the
next START is detected. If the received slave address is acknowledged, zero or more data bytes are
received.
If hardware ACK generation is disabled, the ACKRQ is set to 1 and an interrupt is generated after each
received byte. Software must write the ACK bit at that time to ACK or NACK the received byte.
With hardware ACK generation enabled, the SMBus hardware will automatically generate the ACK/NACK,
and then post the interrupt. It is important to note that the appropriate ACK or NACK value should be
set up by the software prior to receiving the byte when hardware ACK generation is enabled.
The interface exits Slave Receiver Mode after receiving a STOP. Note that the interface will switch to Slave
Transmitter Mode if SMB0DAT is written while an active Slave Receiver. Figure 26.7 shows a typical slave
write sequence. Two received data bytes are shown, though any number of bytes may be received. Notice
that the “data byte transferred” interrupts occur at different places in the sequence, depending on whether
hardware ACK generation is enabled. The interrupt occurs before the ACK with hardware ACK generation
disabled, and after the ACK when hardware ACK generation is enabled.
Interrupts with Hardware ACK Enabled (EHACK = 1)
S
SLA
W
A
Data Byte
A
Data Byte
A
P
Interrupts with Hardware ACK Disabled (EHACK = 0)
S = START
P = STOP
A = ACK
Received by SMBus
Interface
W = WRITE
SLA = Slave Address
Transmitted by
SMBus Interface
Figure 26.7. Typical Slave Write Sequence
Rev. 1.0
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26.5.4. Read Sequence (Slave)
During a read sequence, an SMBus master reads data from a slave device. The slave in this transfer will
be a receiver during the address byte, and a transmitter during all data bytes. When slave events are
enabled (INH = 0), the interface enters Slave Receiver Mode (to receive the slave address) when a START
followed by a slave address and direction bit (READ in this case) is received. If hardware ACK generation
is disabled, upon entering Slave Receiver Mode, an interrupt is generated and the ACKRQ bit is set. The
software must respond to the received slave address with an ACK, or ignore the received slave address
with a NACK. If hardware ACK generation is enabled, the hardware will apply the ACK for a slave address
which matches the criteria set up by SMB0ADR and SMB0ADM. The interrupt will occur after the ACK
cycle.
If the received slave address is ignored (by software or hardware), slave interrupts will be inhibited until the
next START is detected. If the received slave address is acknowledged, zero or more data bytes are trans-
mitted. If the received slave address is acknowledged, data should be written to SMB0DAT to be transmit-
ted. The interface enters slave transmitter mode, and transmits one or more bytes of data. After each byte
is transmitted, the master sends an acknowledge bit; if the acknowledge bit is an ACK, SMB0DAT should
be written with the next data byte. If the acknowledge bit is a NACK, SMB0DAT should not be written to
before SI is cleared (an error condition may be generated if SMB0DAT is written following a received
NACK while in slave transmitter mode). The interface exits slave transmitter mode after receiving a STOP.
Note that the interface will switch to slave receiver mode if SMB0DAT is not written following a Slave
Transmitter interrupt. Figure 26.8 shows a typical slave read sequence. Two transmitted data bytes are
shown, though any number of bytes may be transmitted. Notice that all of the “data byte transferred” inter-
rupts occur after the ACK cycle in this mode, regardless of whether hardware ACK generation is enabled.
Interrupts with Hardware ACK Enabled (EHACK = 1)
S
SLA
R
A
Data Byte
A
Data Byte
N
P
Interrupts with Hardware ACK Disabled (EHACK = 0)
S = START
P = STOP
N = NACK
Received by SMBus
Interface
R = READ
SLA = Slave Address
Transmitted by
SMBus Interface
Figure 26.8. Typical Slave Read Sequence
26.6. SMBus Status Decoding
The current SMBus status can be easily decoded using the SMB0CN register. The appropriate actions to
take in response to an SMBus event depend on whether hardware slave address recognition and ACK
generation is enabled or disabled. Table 26.5 describes the typical actions when hardware slave address
recognition and ACK generation is disabled. Table 26.6 describes the typical actions when hardware slave
address recognition and ACK generation is enabled. In the tables, STATUS VECTOR refers to the four
upper bits of SMB0CN: MASTER, TXMODE, STA, and STO. The shown response options are only the typ-
ical responses; application-specific procedures are allowed as long as they conform to the SMBus specifi-
cation. Highlighted responses are allowed by hardware but do not conform to the SMBus specification.
196
Rev. 1.0
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Table 26.5. SMBus Status Decoding With Hardware ACK Generation Disabled (EHACK = 0)
Values to
Write
Values Read
Current SMbus State
Typical Response Options
A master START was gener- Load slave address + R/W into
0
0
X
1100
1110
1100
0
0
0
0
X
ated.
SMB0DAT.
A master data or address byte Set STA to restart transfer.
1
0
0
1
X
X
1110
—
0 was transmitted; NACK
received.
Abort transfer.
Load next data byte into
SMB0DAT.
0
0
X
1100
End transfer with STOP.
0
1
1
1
X
X
—
—
A master data or address byte End transfer with STOP and start
0
0
1 was transmitted; ACK
received.
another transfer.
Send repeated START.
1
0
0
0
X
X
1110
1000
Switch to Master Receiver Mode
(clear SI without writing new data
to SMB0DAT).
Acknowledge received byte;
Read SMB0DAT.
0
0
1
0
1
1
1
0
0
1000
—
Send NACK to indicate last byte,
and send STOP.
Send NACK to indicate last byte,
and send STOP followed by
START.
1110
Send ACK followed by repeated
START.
1
1
0
0
0
0
1
0
1
1110
1110
1100
A master data byte was
0 X
1000
1
received; ACK requested.
Send NACK to indicate last byte,
and send repeated START.
Send ACK and switch to Master
Transmitter Mode (write to
SMB0DAT before clearing SI).
Send NACK and switch to Mas-
ter Transmitter Mode (write to
SMB0DAT before clearing SI).
0
0
0
1100
Rev. 1.0
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Table 26.5. SMBus Status Decoding With Hardware ACK Generation Disabled (EHACK = 0)
(Continued)
Values to
Write
Values Read
Current SMbus State
Typical Response Options
A slave byte was transmitted; No action required (expecting
0
0
0
0
0
0
0
0
X
X
X
X
0001
0100
0001
—
0
0
0
0
0
1
0
1
NACK received.
A slave byte was transmitted; Load SMB0DAT with next data
ACK received. byte to transmit.
A Slave byte was transmitted; No action required (expecting
STOP condition).
0100
0101
X
error detected.
Master to end transfer).
An illegal STOP or bus error
0
1
X
0
X was detected while a Slave
Transmission was in progress.
Clear STO.
If Write, Acknowledge received
address
0
0
0
0
1
1
0000
0100
A slave address + R/W was
X
If Read, Load SMB0DAT with
data byte; ACK received address
received; ACK requested.
NACK received address.
0
0
0
0
0
1
—
If Write, Acknowledge received
address
0000
0010
If Read, Load SMB0DAT with
data byte; ACK received address
0
0
1
0100
Lost arbitration as master;
X slave address + R/W received;
ACK requested.
1
1
NACK received address.
0
1
0
0
0
0
—
Reschedule failed transfer;
NACK received address.
1110
A STOP was detected while
0
0
X
—
0
1
0
1
X addressed as a Slave Trans- Clear STO.
mitter or Slave Receiver.
0001
0000
Lost arbitration while attempt- No action required (transfer
X
0
0
0
0
0
1
—
ing a STOP.
complete/aborted).
Acknowledge received byte;
Read SMB0DAT.
0000
A slave byte was received;
ACK requested.
1
0
X
NACK received byte.
Abort failed transfer.
0
0
1
0
1
0
1
0
0
0
0
0
0
0
0
X
X
X
X
0
—
—
Lost arbitration while attempt-
ing a repeated START.
0010
0001
0
0
1
1
X
X
Reschedule failed transfer.
Abort failed transfer.
1110
—
Lost arbitration due to a
detected STOP.
Reschedule failed transfer.
Abort failed transfer.
1110
—
Lost arbitration while transmit-
ting a data byte as master.
0000
1
1
X
0
1110
Reschedule failed transfer.
198
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Table 26.6. SMBus Status Decoding With Hardware ACK Generation Enabled (EHACK = 1)
Values to
Write
Values Read
Current SMbus State
Typical Response Options
A master START was gener- Load slave address + R/W into
0
0
X
1100
1110
0
0
0
0
X
ated.
SMB0DAT.
A master data or address byte Set STA to restart transfer.
1
0
0
1
X
X
1110
—
0 was transmitted; NACK
received.
Abort transfer.
Load next data byte into
SMB0DAT.
0
0
X
1100
End transfer with STOP.
0
1
1
1
X
X
—
—
1100
End transfer with STOP and start
another transfer.
A master data or address byte
1 was transmitted; ACK
received.
0
0
Send repeated START.
1
0
0
0
X
1
1110
1000
Switch to Master Receiver Mode
(clear SI without writing new data
to SMB0DAT). Set ACK for initial
data byte.
Set ACK for next data byte;
Read SMB0DAT.
0
0
0
0
1
0
1000
1000
Set NACK to indicate next data
byte as the last data byte;
Read SMB0DAT.
A master data byte was
received; ACK sent.
0
0
1
Initiate repeated START.
1
0
0
0
0
1110
1100
Switch to Master Transmitter
Mode (write to SMB0DAT before
clearing SI).
X
1000
Read SMB0DAT; send STOP.
0
1
1
1
0
0
—
Read SMB0DAT; Send STOP
followed by START.
1110
A master data byte was
0 received; NACK sent (last
byte).
0
0
Initiate repeated START.
1
0
0
0
0
1110
1100
Switch to Master Transmitter
Mode (write to SMB0DAT before
clearing SI).
X
Rev. 1.0
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Table 26.6. SMBus Status Decoding With Hardware ACK Generation Enabled (EHACK = 1)
(Continued)
Values to
Write
Values Read
Current SMbus State
Typical Response Options
A slave byte was transmitted; No action required (expecting
0
0
0
0
0
0
0
0
X
X
X
X
0001
0100
0001
—
0
0
0
0
0
1
0
1
NACK received.
A slave byte was transmitted; Load SMB0DAT with next data
ACK received. byte to transmit.
A Slave byte was transmitted; No action required (expecting
STOP condition).
0100
0101
X
error detected.
Master to end transfer).
An illegal STOP or bus error
0
0
X
0
X was detected while a Slave
Transmission was in progress.
Clear STO.
If Write, Set ACK for first data
byte.
0
0
0
0
0
0
0
0
1
X
1
0000
0100
0000
0100
A slave address + R/W was
X
received; ACK sent.
If Read, Load SMB0DAT with
data byte
0010
If Write, Set ACK for first data
byte.
Lost arbitration as master;
0
1
X slave address + R/W received; If Read, Load SMB0DAT with
X
ACK sent.
data byte
Reschedule failed transfer
1
0
0
0
X
X
1110
—
A STOP was detected while
0
0
0
1
X addressed as a Slave Trans- Clear STO.
mitter or Slave Receiver.
0001
0000
Lost arbitration while attempt- No action required (transfer
X
0
0
0
0
0
0
0
1
0
—
ing a STOP.
complete/aborted).
Set ACK for next data byte;
Read SMB0DAT.
0000
0000
0
0
X A slave byte was received.
Set NACK for next data byte;
Read SMB0DAT.
Abort failed transfer.
0
1
0
1
0
1
0
0
0
0
0
0
X
X
X
X
X
X
—
1110
—
Lost arbitration while attempt-
ing a repeated START.
0010
0001
0
0
1
1
X
Reschedule failed transfer.
Abort failed transfer.
Lost arbitration due to a
detected STOP.
X
Reschedule failed transfer.
Abort failed transfer.
1110
—
Lost arbitration while transmit-
ting a data byte as master.
0000
0
1
X
1110
Reschedule failed transfer.
200
Rev. 1.0
C8051F80x-83x
27. UART0
UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART.
Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details
in Section “27.1. Enhanced Baud Rate Generation” on page 202). Received data buffering allows UART0
to start reception of a second incoming data byte before software has finished reading the previous data
byte.
UART0 has two associated SFRs: Serial Control Register 0 (SCON0) and Serial Data Buffer 0 (SBUF0).
The single SBUF0 location provides access to both transmit and receive registers. Writes to SBUF0
always access the Transmit register. Reads of SBUF0 always access the buffered Receive register;
it is not possible to read data from the Transmit register.
With UART0 interrupts enabled, an interrupt is generated each time a transmit is completed (TI0 is set in
SCON0), or a data byte has been received (RI0 is set in SCON0). The UART0 interrupt flags are not
cleared by hardware when the CPU vectors to the interrupt service routine. They must be cleared manually
by software, allowing software to determine the cause of the UART0 interrupt (transmit complete or receive
complete).
SFR Bus
Write to
SBUF
TB8
SBUF
SET
(TX Shift)
D
Q
TX
CLR
Crossbar
Zero Detector
Stop Bit
Shift
Data
Start
Tx Control
Tx Clock
Send
Tx IRQ
SCON
TI
UART Baud
Rate Generator
Serial
Port
Interrupt
Port I/O
RI
Rx IRQ
Rx Clock
Rx Control
Load
SBUF
Start
Shift
0x1FF
RB8
Input Shift Register
(9 bits)
Load SBUF
SBUF
(RX Latch)
Read
SBUF
SFR Bus
RX
Crossbar
Figure 27.1. UART0 Block Diagram
Rev. 1.0
201
C8051F80x-83x
27.1. Enhanced Baud Rate Generation
The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by
TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer in Figure 27.2), which is not user-
accessible. Both TX and RX Timer overflows are divided by two to generate the TX and RX baud rates.
The RX Timer runs when Timer 1 is enabled, and uses the same reload value (TH1). However, an
RX Timer reload is forced when a START condition is detected on the RX pin. This allows a receive to
begin any time a START is detected, independent of the TX Timer state.
Timer 1
TL1
UART
Overflow
TX Clock
2
2
TH1
Start
Detected
Overflow
RX Clock
RX Timer
Figure 27.2. UART0 Baud Rate Logic
Timer 1 should be configured for Mode 2, 8-bit auto-reload (see Section “28.1.3. Mode 2: 8-bit Coun-
ter/Timer with Auto-Reload” on page 212). The Timer 1 reload value should be set so that overflows will
occur at two times the desired UART baud rate frequency. Note that Timer 1 may be clocked by one of six
sources: SYSCLK, SYSCLK/4, SYSCLK/12, SYSCLK/48, the external oscillator clock/8, or an external
input T1. For any given Timer 1 clock source, the UART0 baud rate is determined by Equation 27.1-A and
Equation 27.1-B.
1
2
A)
B)
--
UartBaudRate = T1_Overflow_Rate
T1CLK
T1_Overflow_Rate = -------------------------
256 – TH1
Equation 27.1. UART0 Baud Rate
Where T1
is the frequency of the clock supplied to Timer 1, and T1H is the high byte of Timer 1 (reload
CLK
value). Timer 1 clock frequency is selected as described in Section “28. Timers” on page 209. A quick ref-
erence for typical baud rates and system clock frequencies is given in Table 27.1 through Table 27.2. The
internal oscillator may still generate the system clock when the external oscillator is driving Timer 1.
202
Rev. 1.0
C8051F80x-83x
27.2. Operational Modes
UART0 provides standard asynchronous, full duplex communication. The UART mode (8-bit or 9-bit) is
selected by the S0MODE bit (SCON0.7). Typical UART connection options are shown in Figure 27.3.
TX
RS-232
RS-232
LEVEL
C8051xxxx
RX
XLTR
OR
TX
RX
TX
RX
MCU
C8051xxxx
Figure 27.3. UART Interconnect Diagram
27.2.1. 8-Bit UART
8-Bit UART mode uses a total of 10 bits per data byte: one start bit, eight data bits (LSB first), and one stop
bit. Data are transmitted LSB first from the TX0 pin and received at the RX0 pin. On receive, the eight data
bits are stored in SBUF0 and the stop bit goes into RB80 (SCON0.2).
Data transmission begins when software writes a data byte to the SBUF0 register. The TI0 Transmit Inter-
rupt Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data recep-
tion can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to logic 1. After the stop bit is
received, the data byte will be loaded into the SBUF0 receive register if the following conditions are met:
RI0 must be logic 0, and if MCE0 is logic 1, the stop bit must be logic 1. In the event of a receive data over-
run, the first received 8 bits are latched into the SBUF0 receive register and the following overrun data bits
are lost.
If these conditions are met, the eight bits of data is stored in SBUF0, the stop bit is stored in RB80 and the
RI0 flag is set. If these conditions are not met, SBUF0 and RB80 will not be loaded and the RI0 flag will not
be set. An interrupt will occur if enabled when either TI0 or RI0 is set.
MARK
START
BIT
STOP
BIT
D0
D1
D2
D3
D4
D5
D6
D7
SPACE
BIT TIMES
BIT SAMPLING
Figure 27.4. 8-Bit UART Timing Diagram
Rev. 1.0
203
C8051F80x-83x
27.2.2. 9-Bit UART
9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programma-
ble ninth data bit, and a stop bit. The state of the ninth transmit data bit is determined by the value in TB80
(SCON0.3), which is assigned by user software. It can be assigned the value of the parity flag (bit P in reg-
ister PSW) for error detection, or used in multiprocessor communications. On receive, the ninth data bit
goes into RB80 (SCON0.2) and the stop bit is ignored.
Data transmission begins when an instruction writes a data byte to the SBUF0 register. The TI0 Transmit
Interrupt Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data
reception can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to 1. After the stop bit is
received, the data byte will be loaded into the SBUF0 receive register if the following conditions are met:
(1) RI0 must be logic 0, and (2) if MCE0 is logic 1, the 9th bit must be logic 1 (when MCE0 is logic 0, the
state of the ninth data bit is unimportant). If these conditions are met, the eight bits of data are stored in
SBUF0, the ninth bit is stored in RB80, and the RI0 flag is set to 1. If the above conditions are not met,
SBUF0 and RB80 will not be loaded and the RI0 flag will not be set to 1. A UART0 interrupt will occur if
enabled when either TI0 or RI0 is set to 1.
MARK
START
BIT
STOP
BIT
D0
D1
D2
D3
D4
D5
D6
D7
D8
SPACE
BIT TIMES
BIT SAMPLING
Figure 27.5. 9-Bit UART Timing Diagram
204
Rev. 1.0
C8051F80x-83x
27.3. Multiprocessor Communications
9-Bit UART mode supports multiprocessor communication between a master processor and one or more
slave processors by special use of the ninth data bit. When a master processor wants to transmit to one or
more slaves, it first sends an address byte to select the target(s). An address byte differs from a data byte
in that its ninth bit is logic 1; in a data byte, the ninth bit is always set to logic 0.
Setting the MCE0 bit (SCON0.5) of a slave processor configures its UART such that when a stop bit is
received, the UART will generate an interrupt only if the ninth bit is logic 1 (RB80 = 1) signifying an address
byte has been received. In the UART interrupt handler, software will compare the received address with
the slave's own assigned 8-bit address. If the addresses match, the slave will clear its MCE0 bit to enable
interrupts on the reception of the following data byte(s). Slaves that weren't addressed leave their MCE0
bits set and do not generate interrupts on the reception of the following data bytes, thereby ignoring the
data. Once the entire message is received, the addressed slave resets its MCE0 bit to ignore all transmis-
sions until it receives the next address byte.
Multiple addresses can be assigned to a single slave and/or a single address can be assigned to multiple
slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. The master
processor can be configured to receive all transmissions or a protocol can be implemented such that the
master/slave role is temporarily reversed to enable half-duplex transmission between the original master
and slave(s).
Master
Device
Slave
Device
Slave
Device
Slave
Device
V+
RX
TX
RX
TX
RX
TX
RX
TX
Figure 27.6. UART Multi-Processor Mode Interconnect Diagram
Rev. 1.0
205
C8051F80x-83x
SFR Definition 27.1. SCON0: Serial Port 0 Control
Bit
7
6
5
4
3
2
1
0
S0MODE
MCE0
REN0
TB80
RB80
TI0
RI0
Name
Type
Reset
R/W
0
R
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Address = 0x98; Bit-Addressable
Bit
Name
Function
7
S0MODE Serial Port 0 Operation Mode.
Selects the UART0 Operation Mode.
0: 8-bit UART with Variable Baud Rate.
1: 9-bit UART with Variable Baud Rate.
6
5
Unused Read = 1b, Write = Don’t Care.
MCE0
Multiprocessor Communication Enable.
The function of this bit is dependent on the Serial Port 0 Operation Mode:
Mode 0: Checks for valid stop bit.
0: Logic level of stop bit is ignored.
1: RI0 will only be activated if stop bit is logic level 1.
Mode 1: Multiprocessor Communications Enable.
0: Logic level of ninth bit is ignored.
1: RI0 is set and an interrupt is generated only when the ninth bit is logic 1.
4
3
2
1
REN0
TB80
RB80
TI0
Receive Enable.
0: UART0 reception disabled.
1: UART0 reception enabled.
Ninth Transmission Bit.
The logic level of this bit will be sent as the ninth transmission bit in 9-bit UART Mode
(Mode 1). Unused in 8-bit mode (Mode 0).
Ninth Receive Bit.
RB80 is assigned the value of the STOP bit in Mode 0; it is assigned the value of the
9th data bit in Mode 1.
Transmit Interrupt Flag.
Set by hardware when a byte of data has been transmitted by UART0 (after the 8th bit
in 8-bit UART Mode, or at the beginning of the STOP bit in 9-bit UART Mode). When
the UART0 interrupt is enabled, setting this bit causes the CPU to vector to the UART0
interrupt service routine. This bit must be cleared manually by software.
0
RI0
Receive Interrupt Flag.
Set to 1 by hardware when a byte of data has been received by UART0 (set at the
STOP bit sampling time). When the UART0 interrupt is enabled, setting this bit to 1
causes the CPU to vector to the UART0 interrupt service routine. This bit must be
cleared manually by software.
206
Rev. 1.0
C8051F80x-83x
SFR Definition 27.2. SBUF0: Serial (UART0) Port Data Buffer
Bit
7
6
5
4
3
2
1
0
SBUF0[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Address = 0x99
Bit Name
7:0 SBUF0[7:0] Serial Data Buffer Bits 7–0 (MSB–LSB).
Function
This SFR accesses two registers; a transmit shift register and a receive latch register.
When data is written to SBUF0, it goes to the transmit shift register and is held for
serial transmission. Writing a byte to SBUF0 initiates the transmission. A read of
SBUF0 returns the contents of the receive latch.
Rev. 1.0
207
C8051F80x-83x
Table 27.1. Timer Settings for Standard Baud Rates
Using The Internal 24.5 MHz Oscillator
Frequency: 24.5 MHz
1
Target
Baud Rate Oscillator Timer Clock
SCA1–SCA0
Timer 1
Reload
Value (hex)
T1M
% Error
Divide
Factor
Source
Baud Rate
(bps)
(pre-scale
1
select)
2
230400
115200
57600
28800
14400
9600
–0.32%
–0.32%
0.15%
–0.32%
0.15%
–0.32%
–0.32%
0.15%
106
212
426
SYSCLK
SYSCLK
SYSCLK
SYSCLK/4
SYSCLK/12
SYSCLK/12
SYSCLK/48
SYSCLK/48
XX
1
1
1
0
0
0
0
0
0xCB
0x96
0x2B
0x96
0xB9
0x96
0x96
0x2B
XX
XX
01
00
00
10
10
848
1704
2544
10176
20448
2400
1200
Notes:
1. SCA1–SCA0 and T1M bit definitions can be found in Section 28.1.
2. X = Don’t care.
Table 27.2. Timer Settings for Standard Baud Rates
Using an External 22.1184 MHz Oscillator
Frequency: 22.1184 MHz
1
Target
Baud Rate Oscillator Timer Clock
SCA1–SCA0
(pre-scale
Timer 1
Reload
Value (hex)
T1M
% Error
Divide
Factor
Source
Baud Rate
(bps)
1
select)
2
230400
115200
57600
28800
14400
9600
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
96
192
384
SYSCLK
SYSCLK
SYSCLK
XX
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0xD0
0xA0
0x40
0xE0
0xC0
0xA0
0xA0
0x40
0xFA
0xF4
0xE8
0xD0
0xA0
0x70
XX
XX
00
00
00
10
10
11
11
11
11
11
11
768
SYSCLK / 12
SYSCLK / 12
SYSCLK / 12
SYSCLK / 48
SYSCLK / 48
EXTCLK / 8
EXTCLK / 8
EXTCLK / 8
EXTCLK / 8
EXTCLK / 8
EXTCLK / 8
1536
2304
9216
18432
96
192
384
768
1536
2304
2400
1200
230400
115200
57600
28800
14400
9600
Notes:
1. SCA1–SCA0 and T1M bit definitions can be found in Section 28.1.
2. X = Don’t care.
208
Rev. 1.0
C8051F80x-83x
28. Timers
Each MCU includes three counter/timers: two are 16-bit counter/timers compatible with those found in the
standard 8051, and one is a 16-bit auto-reload timer for use with the ADC, SMBus, or for general purpose
use. These timers can be used to measure time intervals, count external events and generate periodic
interrupt requests. Timer 0 and Timer 1 are nearly identical and have four primary modes of operation.
Timer 2 offers 16-bit and split 8-bit timer functionality with auto-reload. Additionally, Timer 2 offers the abil-
ity to be clocked from the external oscillator while the device is in Suspend mode, and can be used as a
wake-up source. This allows for implementation of a very low-power system, including RTC capability.
Timer 0 and Timer 1 Modes
Timer 2 Modes
13-bit counter/timer
16-bit counter/timer
16-bit timer with auto-reload
8-bit counter/timer with
auto-reload
Two 8-bit timers with auto-reload
Two 8-bit counter/timers
(Timer 0 only)
Timers 0 and 1 may be clocked by one of five sources, determined by the Timer Mode Select bits (T1M–
T0M) and the Clock Scale bits (SCA1–SCA0). The Clock Scale bits define a pre-scaled clock from which
Timer 0 and/or Timer 1 may be clocked (See SFR Definition 28.1 for pre-scaled clock selection).
Timer 0/1 may then be configured to use this pre-scaled clock signal or the system clock. Timer 2 may be
clocked by the system clock, the system clock divided by 12, or the external oscillator clock source divided
by 8.
Timer 0 and Timer 1 may also be operated as counters. When functioning as a counter, a counter/timer
register is incremented on each high-to-low transition at the selected input pin (T0 or T1). Events with a fre-
quency of up to one-fourth the system clock frequency can be counted. The input signal need not be peri-
odic, but it should be held at a given level for at least two full system clock cycles to ensure the level is
properly sampled.
Rev. 1.0
209
C8051F80x-83x
SFR Definition 28.1. CKCON: Clock Control
Bit
7
6
5
4
3
2
1
0
T2MH
T2ML
T1M
T0M
SCA[1:0]
R/W
Name
Type
Reset
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
0
0
SFR Address = 0x8E
Bit Name
7:6 Unused Read = 0b; Write = Don’t care
Function
5
T2MH Timer 2 High Byte Clock Select.
Selects the clock supplied to the Timer 2 high byte (split 8-bit timer mode only).
0: Timer 2 high byte uses the clock defined by the T2XCLK bit in TMR2CN.
1: Timer 2 high byte uses the system clock.
4
T2ML
Timer 2 Low Byte Clock Select.
Selects the clock supplied to Timer 2. If Timer 2 is configured in split 8-bit timer mode,
this bit selects the clock supplied to the lower 8-bit timer.
0: Timer 2 low byte uses the clock defined by the T2XCLK bit in TMR2CN.
1: Timer 2 low byte uses the system clock.
3
2
T1
T0
Timer 1 Clock Select.
Selects the clock source supplied to Timer 1. Ignored when C/T1 is set to 1.
0: Timer 1 uses the clock defined by the prescale bits SCA[1:0].
1: Timer 1 uses the system clock.
Timer 0 Clock Select.
Selects the clock source supplied to Timer 0. Ignored when C/T0 is set to 1.
0: Counter/Timer 0 uses the clock defined by the prescale bits SCA[1:0].
1: Counter/Timer 0 uses the system clock.
1:0 SCA[1:0] Timer 0/1 Prescale Bits.
These bits control the Timer 0/1 Clock Prescaler:
00: System clock divided by 12
01: System clock divided by 4
10: System clock divided by 48
11: External clock divided by 8 (synchronized with the system clock)
210
Rev. 1.0
C8051F80x-83x
28.1. Timer 0 and Timer 1
Each timer is implemented as a 16-bit register accessed as two separate bytes: a low byte (TL0 or TL1)
and a high byte (TH0 or TH1). The Counter/Timer Control register (TCON) is used to enable Timer 0 and
Timer 1 as well as indicate status. Timer 0 interrupts can be enabled by setting the ET0 bit in the IE regis-
ter (Section “18.2. Interrupt Register Descriptions” on page 104); Timer 1 interrupts can be enabled by set-
ting the ET1 bit in the IE register (Section “18.2. Interrupt Register Descriptions” on page 104). Both
counter/timers operate in one of four primary modes selected by setting the Mode Select bits T1M1–T0M0
in the Counter/Timer Mode register (TMOD). Each timer can be configured independently. Each operating
mode is described below.
28.1.1. Mode 0: 13-bit Counter/Timer
Timer 0 and Timer 1 operate as 13-bit counter/timers in Mode 0. The following describes the configuration
and operation of Timer 0. However, both timers operate identically, and Timer 1 is configured in the same
manner as described for Timer 0.
The TH0 register holds the eight MSBs of the 13-bit counter/timer. TL0 holds the five LSBs in bit positions
TL0.4–TL0.0. The three upper bits of TL0 (TL0.7–TL0.5) are indeterminate and should be masked out or
ignored when reading. As the 13-bit timer register increments and overflows from 0x1FFF (all ones) to
0x0000, the timer overflow flag TF0 in TCON is set and an interrupt will occur if Timer 0 interrupts are
enabled.
The C/T0 bit in the TMOD register selects the counter/timer's clock source. When C/T0 is set to logic 1,
high-to-low transitions at the selected Timer 0 input pin (T0) increment the timer register (Refer to Section
“23.3. Priority Crossbar Decoder” on page 143 for information on selecting and configuring external I/O
pins). Clearing C/T selects the clock defined by the T0M bit in register CKCON. When T0M is set, Timer 0
is clocked by the system clock. When T0M is cleared, Timer 0 is clocked by the source selected by the
Clock Scale bits in CKCON (see SFR Definition 28.1).
Setting the TR0 bit (TCON.4) enables the timer when either GATE0 in the TMOD register is logic 0 or the
input signal INT0 is active as defined by bit IN0PL in register IT01CF (see SFR Definition 18.7). Setting
GATE0 to 1 allows the timer to be controlled by the external input signal INT0 (see Section “18.2. Interrupt
Register Descriptions” on page 104), facilitating pulse width measurements
TR0
GATE0
INT0
Counter/Timer
0
1
1
1
X
0
1
1
X
X
0
1
Disabled
Enabled
Disabled
Enabled
Note: X = Don't Care
Setting TR0 does not force the timer to reset. The timer registers should be loaded with the desired initial
value before the timer is enabled.
TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as described above for TL0 and TH0.
Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0. The
input signal INT1 is used with Timer 1; the INT1 polarity is defined by bit IN1PL in register IT01CF (see
SFR Definition 18.7).
Rev. 1.0
211
C8051F80x-83x
TMOD
IT01CF
G C T T G C T T
I I I I I I I I
A
/
1
1 A
/
0
0
N N N N N N N N
T0M
T T M M T T M M
1
1 1 1 0 0 0 0
E
1
1
1
0 E 0
0
1
0
P S S S P S S S
L
L
2
L
1
L
0
L
L
2
L
1
L
0
Pre-scaled Clock
SYSCLK
0
1
0
1
TF1
TR1
TF0
TR0
IE1
T0
Interrupt
TCLK
TL0
(5 bits)
TH0
(8 bits)
TR0
IT1
GATE0
IE0
IT0
Crossbar
IN0PL
XOR
INT0
Figure 28.1. T0 Mode 0 Block Diagram
28.1.2. Mode 1: 16-bit Counter/Timer
Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The coun-
ter/timers are enabled and configured in Mode 1 in the same manner as for Mode 0.
28.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload
Mode 2 configures Timer 0 and Timer 1 to operate as 8-bit counter/timers with automatic reload of the start
value. TL0 holds the count and TH0 holds the reload value. When the counter in TL0 overflows from all
ones to 0x00, the timer overflow flag TF0 in the TCON register is set and the counter in TL0 is reloaded
from TH0. If Timer 0 interrupts are enabled, an interrupt will occur when the TF0 flag is set. The reload
value in TH0 is not changed. TL0 must be initialized to the desired value before enabling the timer for the
first count to be correct. When in Mode 2, Timer 1 operates identically to Timer 0.
Both counter/timers are enabled and configured in Mode 2 in the same manner as Mode 0. Setting the
TR0 bit (TCON.4) enables the timer when either GATE0 in the TMOD register is logic 0 or when the input
signal INT0 is active as defined by bit IN0PL in register IT01CF (see Section “18.3. INT0 and INT1 External
Interrupts” on page 111 for details on the external input signals INT0 and INT1).
212
Rev. 1.0
C8051F80x-83x
TMOD
IT01CF
G C T T G C T T
I I I I I I I I
A
/
1 1 A
/
0 0
N N N N N N N N
1 1 1 1 0 0 0 0
P S S S P S S S
L L L L L L L L
T T M M T T M M
E 1 1 0 E 0 1 0
1
T0M
0
2 1 0
2 1 0
Pre-scaled Clock
SYSCLK
0
1
0
1
T0
TF1
TR1
TF0
TR0
IE1
TCLK
TL0
(8 bits)
Interrupt
TR0
IT1
IE0
IT0
Crossbar
GATE0
TH0
Reload
(8 bits)
IN0PL
XOR
INT0
Figure 28.2. T0 Mode 2 Block Diagram
28.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)
In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The coun-
ter/timer in TL0 is controlled using the Timer 0 control/status bits in TCON and TMOD: TR0, C/T0, GATE0
and TF0. TL0 can use either the system clock or an external input signal as its timebase. The TH0 register
is restricted to a timer function sourced by the system clock or prescaled clock. TH0 is enabled using the
Timer 1 run control bit TR1. TH0 sets the Timer 1 overflow flag TF1 on overflow and thus controls the
Timer 1 interrupt.
Timer 1 is inactive in Mode 3. When Timer 0 is operating in Mode 3, Timer 1 can be operated in Modes 0,
1 or 2, but cannot be clocked by external signals nor set the TF1 flag and generate an interrupt. However,
the Timer 1 overflow can be used to generate baud rates or overflow conditions for other peripherals.
While Timer 0 is operating in Mode 3, Timer 1 run control is handled through its mode settings. To run
Timer 1 while Timer 0 is in Mode 3, set the Timer 1 Mode as 0, 1, or 2. To disable Timer 1, configure it for
Mode 3.
Rev. 1.0
213
C8051F80x-83x
TMOD
G C T T G C T T
A
/
1
1 A
/ 0 0
T0M
T T M M T T M M
E 1
1
1
0 E 0
0
1 0
Pre-scaled Clock
SYSCLK
0
1
TH0
(8 bits)
TR1
Interrupt
Interrupt
TF1
TR1
TF0
TR0
IE1
0
1
IT1
IE0
IT0
T0
TL0
(8 bits)
TR0
Crossbar
GATE0
IN0PL
XOR
INT0
Figure 28.3. T0 Mode 3 Block Diagram
214
Rev. 1.0
C8051F80x-83x
SFR Definition 28.2. TCON: Timer Control
Bit
7
6
5
4
3
2
1
0
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Address = 0x88; Bit-Addressable
Bit
Name
Function
7
TF1
Timer 1 Overflow Flag.
Set to 1 by hardware when Timer 1 overflows. This flag can be cleared by software
but is automatically cleared when the CPU vectors to the Timer 1 interrupt service
routine.
6
5
TR1
TF0
Timer 1 Run Control.
Timer 1 is enabled by setting this bit to 1.
Timer 0 Overflow Flag.
Set to 1 by hardware when Timer 0 overflows. This flag can be cleared by software
but is automatically cleared when the CPU vectors to the Timer 0 interrupt service
routine.
4
3
TR0
IE1
Timer 0 Run Control.
Timer 0 is enabled by setting this bit to 1.
External Interrupt 1.
This flag is set by hardware when an edge/level of type defined by IT1 is detected. It
can be cleared by software but is automatically cleared when the CPU vectors to the
External Interrupt 1 service routine in edge-triggered mode.
2
IT1
Interrupt 1 Type Select.
This bit selects whether the configured /INT1 interrupt will be edge or level sensitive.
/INT1 is configured active low or high by the IN1PL bit in the IT01CF register (see
SFR Definition 18.7).
0: /INT1 is level triggered.
1: /INT1 is edge triggered.
1
0
IE0
IT0
External Interrupt 0.
This flag is set by hardware when an edge/level of type defined by IT1 is detected. It
can be cleared by software but is automatically cleared when the CPU vectors to the
External Interrupt 0 service routine in edge-triggered mode.
Interrupt 0 Type Select.
This bit selects whether the configured INT0 interrupt will be edge or level sensitive.
INT0 is configured active low or high by the IN0PL bit in register IT01CF (see SFR
Definition 18.7).
0: INT0 is level triggered.
1: INT0 is edge triggered.
Rev. 1.0
215
C8051F80x-83x
SFR Definition 28.3. TMOD: Timer Mode
Bit
7
6
5
4
3
2
1
0
GATE1
C/T1
T1M[1:0]
R/W
GATE0
C/T0
T0M[1:0]
R/W
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
0
0
0
0
SFR Address = 0x89
Bit
Name
Function
7
GATE1
Timer 1 Gate Control.
0: Timer 1 enabled when TR1 = 1 irrespective of INT1 logic level.
1: Timer 1 enabled only when TR1 = 1 AND INT1 is active as defined by bit IN1PL in
register IT01CF (see SFR Definition 18.7).
6
C/T1
Counter/Timer 1 Select.
0: Timer: Timer 1 incremented by clock defined by T1M bit in register CKCON.
1: Counter: Timer 1 incremented by high-to-low transitions on external pin (T1).
5:4
T1M[1:0] Timer 1 Mode Select.
These bits select the Timer 1 operation mode.
00: Mode 0, 13-bit Counter/Timer
01: Mode 1, 16-bit Counter/Timer
10: Mode 2, 8-bit Counter/Timer with Auto-Reload
11: Mode 3, Timer 1 Inactive
3
GATE0
C/T0
Timer 0 Gate Control.
0: Timer 0 enabled when TR0 = 1 irrespective of INT0 logic level.
1: Timer 0 enabled only when TR0 = 1 AND INT0 is active as defined by bit IN0PL in
register IT01CF (see SFR Definition 18.7).
2
Counter/Timer 0 Select.
0: Timer: Timer 0 incremented by clock defined by T0M bit in register CKCON.
1: Counter: Timer 0 incremented by high-to-low transitions on external pin (T0).
1:0
T0M[1:0] Timer 0 Mode Select.
These bits select the Timer 0 operation mode.
00: Mode 0, 13-bit Counter/Timer
01: Mode 1, 16-bit Counter/Timer
10: Mode 2, 8-bit Counter/Timer with Auto-Reload
11: Mode 3, Two 8-bit Counter/Timers
216
Rev. 1.0
C8051F80x-83x
SFR Definition 28.4. TL0: Timer 0 Low Byte
Bit
7
6
5
4
3
2
1
0
TL0[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Address = 0x8A
Bit
Name
Function
7:0
TL0[7:0]
Timer 0 Low Byte.
The TL0 register is the low byte of the 16-bit Timer 0.
SFR Definition 28.5. TL1: Timer 1 Low Byte
Bit
7
6
5
4
3
2
1
0
TL1[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Address = 0x8B
Bit
Name
Function
7:0
TL1[7:0]
Timer 1 Low Byte.
The TL1 register is the low byte of the 16-bit Timer 1.
Rev. 1.0
217
C8051F80x-83x
SFR Definition 28.6. TH0: Timer 0 High Byte
Bit
7
6
5
4
3
2
1
0
TH0[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Address = 0x8C
Bit
Name
Function
7:0
TH0[7:0]
Timer 0 High Byte.
The TH0 register is the high byte of the 16-bit Timer 0.
SFR Definition 28.7. TH1: Timer 1 High Byte
Bit
7
6
5
4
3
2
1
0
TH1[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Address = 0x8D
Bit
Name
Function
7:0
TH1[7:0]
Timer 1 High Byte.
The TH1 register is the high byte of the 16-bit Timer 1.
218
Rev. 1.0
C8051F80x-83x
28.2. Timer 2
Timer 2 is a 16-bit timer formed by two 8-bit SFRs: TMR2L (low byte) and TMR2H (high byte). Timer 2 may
operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T2SPLIT bit (TMR2CN.3) defines
the Timer 2 operation mode. Timer 2 can also be used in capture mode to capture rising edges of the
Comparator 0 output.
Timer 2 may be clocked by the system clock, the system clock divided by 12, or the external oscillator
source divided by 8. The external clock mode is ideal for real-time clock (RTC) functionality, where the
internal oscillator drives the system clock while Timer 2 (and/or the PCA) is clocked by an external oscilla-
tor source. The external oscillator source divided by 8 is synchronized with the system clock when in all
operating modes except suspend. When the internal oscillator is placed in suspend mode, The external
clock/8 signal can directly drive the timer. This allows the use of an external clock to wake up the device
from suspend mode. The timer will continue to run in suspend mode and count up. When the timer over-
flow occurs, the device will wake from suspend mode, and begin executing code again. The timer value
may be set prior to entering suspend, to overflow in the desired amount of time (number of clocks) to wake
the device. If a wake-up source other than the timer wakes the device from suspend mode, it may take up
to three timer clocks before the timer registers can be read or written. During this time, the STSYNC bit in
register OSCICN will be set to 1, to indicate that it is not safe to read or write the timer registers.
28.2.1. 16-bit Timer with Auto-Reload
When T2SPLIT (TMR2CN.3) is zero, Timer 2 operates as a 16-bit timer with auto-reload. Timer 2 can be
clocked by SYSCLK, SYSCLK divided by 12, or the external oscillator clock source divided by 8. As the
16-bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in the Timer 2
reload registers (TMR2RLH and TMR2RLL) is loaded into the Timer 2 register as shown in Figure 28.4,
and the Timer 2 High Byte Overflow Flag (TMR2CN.7) is set. If Timer 2 interrupts are enabled (if IE.5 is
set), an interrupt will be generated on each Timer 2 overflow. Additionally, if Timer 2 interrupts are enabled
and the TF2LEN bit is set (TMR2CN.5), an interrupt will be generated each time the lower 8 bits (TMR2L)
overflow from 0xFF to 0x00.
CKCON
T T T T T T S S
3 3 2 2 1 0 C C
T2XCLK
M M M M M M A A
H L H L
1 0
To ADC,
SMBus
To SMBus
TMR2H
SYSCLK / 12
0
1
TL2
Overflow
0
1
TCLK
TR2
TF2H
TMR2L
Interrupt
External Clock / 8
SYSCLK
TF2L
TF2LEN
TF2CEN
T2SPLIT
TR2
T2XCLK
TMR2RLL TMR2RLH
Reload
Figure 28.4. Timer 2 16-Bit Mode Block Diagram
Rev. 1.0
219
C8051F80x-83x
28.2.2. 8-bit Timers with Auto-Reload
When T2SPLIT is set, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers oper-
ate in auto-reload mode as shown in Figure 28.5. TMR2RLL holds the reload value for TMR2L; TMR2RLH
holds the reload value for TMR2H. The TR2 bit in TMR2CN handles the run control for TMR2H. TMR2L is
always running when configured for 8-bit Mode. Timer 2 can also be used in capture mode to capture rising
edges of the Comparator 0 output.
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, or the external oscillator clock
source divided by 8. The Timer 2 Clock Select bits (T2MH and T2ML in CKCON) select either SYSCLK or
the clock defined by the Timer 2 External Clock Select bit (T2XCLK in TMR2CN), as follows:
T2MH
T2XCLK TMR2H Clock Source
T2ML
T2XCLK TMR2L Clock Source
0
0
1
0
1
X
SYSCLK / 12
External Clock / 8
SYSCLK
0
0
1
0
1
X
SYSCLK / 12
External Clock / 8
SYSCLK
The TF2H bit is set when TMR2H overflows from 0xFF to 0x00; the TF2L bit is set when TMR2L overflows
from 0xFF to 0x00. When Timer 2 interrupts are enabled (IE.5), an interrupt is generated each time
TMR2H overflows. If Timer 2 interrupts are enabled and TF2LEN (TMR2CN.5) is set, an interrupt is gener-
ated each time either TMR2L or TMR2H overflows. When TF2LEN is enabled, software must check the
TF2H and TF2L flags to determine the source of the Timer 2 interrupt. The TF2H and TF2L interrupt flags
are not cleared by hardware and must be manually cleared by software.
CKCON
T T T T T T S S
3 3 2 2 1 0 C C
T2XCLK
M M M M M M A A
Reload
TMR2RLH
To SMBus
H L H L
1 0
SYSCLK / 12
0
1
0
External Clock / 8
TCLK
TF2H
TF2L
TMR2H
Interrupt
TR2
1
TF2LEN
TF2CEN
T2SPLIT
TR2
Reload
TMR2RLL
T2XCLK
SYSCLK
1
0
To ADC,
SMBus
TCLK
TMR2L
Figure 28.5. Timer 2 8-Bit Mode Block Diagram
220
Rev. 1.0
C8051F80x-83x
28.2.3. Comparator 0 Capture Mode
The capture mode in Timer 2 allows Comparator 0 rising edges to be captured with the timer clocking from
the system clock or the system clock divided by 12. Timer 2 capture mode is enabled by setting TF2CEN
to 1 and T2SPLIT to 0.
When capture mode is enabled, a capture event will be generated on every Comparator 0 rising edge.
When the capture event occurs, the contents of Timer 2 (TMR2H:TMR2L) are loaded into the Timer 2
reload registers (TMR2RLH:TMR2RLL) and the TF2H flag is set (triggering an interrupt if Timer 2 inter-
rupts are enabled). By recording the difference between two successive timer capture values, the
Comparator 0 period can be determined with respect to the Timer 2 clock. The Timer 2 clock should be
much faster than the capture clock to achieve an accurate reading.
This mode allows software to determine the time between consecutive Comparator 0 rising edges, which
can be used for detecting changes in the capacitance of a capacitive switch, or measuring the frequency of
a low-level analog signal.
CKCON
T2XCLK
T T T T T T S S
3 3 2 2 1 0 C C
MMMMMM A A
H L H L
1 0
SYSCLK / 12
0
1
External Clock / 8
0
1
TCLK
TR2
TMR2L
TMR2H
Capture
SYSCLK
TF2CEN
Comparator 0
Output
TF2H
TF2L
TF2LEN
TF2CEN
T2SPLIT
TR2
Interrupt
TMR2RLL TMR2RLH
T2XCLK
Figure 28.6. Timer 2 Capture Mode Block Diagram
Rev. 1.0
221
C8051F80x-83x
SFR Definition 28.8. TMR2CN: Timer 2 Control
Bit
7
6
5
4
3
2
1
0
TF2H
TF2L
TF2LEN
TF2CEN T2SPLIT
TR2
T2XCLK
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R/W
0
SFR Address = 0xC8; Bit-Addressable
Bit
Name
Function
7
TF2H
Timer 2 High Byte Overflow Flag.
Set by hardware when the Timer 2 high byte overflows from 0xFF to 0x00. In 16 bit
mode, this will occur when Timer 2 overflows from 0xFFFF to 0x0000. When the
Timer 2 interrupt is enabled, setting this bit causes the CPU to vector to the Timer 2
interrupt service routine. This bit is not automatically cleared by hardware.
6
TF2L
Timer 2 Low Byte Overflow Flag.
Set by hardware when the Timer 2 low byte overflows from 0xFF to 0x00. TF2L will
be set when the low byte overflows regardless of the Timer 2 mode. This bit is not
automatically cleared by hardware.
5
4
TF2LEN
TF2CEN
Timer 2 Low Byte Interrupt Enable.
When set to 1, this bit enables Timer 2 Low Byte interrupts. If Timer 2 interrupts are
also enabled, an interrupt will be generated when the low byte of Timer 2 overflows.
Timer 2 Comparator Capture Enable.
When set to 1, this bit enables Timer 2 Comparator Capture Mode. If TF2CEN is set,
on a rising edge of the Comparator0 output the current 16-bit timer value in
TMR2H:TMR2L will be copied to TMR2RLH:TMR2RLL. If Timer 2 interrupts are also
enabled, an interrupt will be generated on this event.
3
2
T2SPLIT
TR2
Timer 2 Split Mode Enable.
When this bit is set, Timer 2 operates as two 8-bit timers with auto-reload.
0: Timer 2 operates in 16-bit auto-reload mode.
1: Timer 2 operates as two 8-bit auto-reload timers.
Timer 2 Run Control.
Timer 2 is enabled by setting this bit to 1. In 8-bit mode, this bit enables/disables
TMR2H only; TMR2L is always enabled in split mode.
1
0
Unused
T2XCLK
Read = 0b; Write = Don’t Care.
Timer 2 External Clock Select.
This bit selects the external clock source for Timer 2. If Timer 2 is in 8-bit mode, this
bit selects the external oscillator clock source for both timer bytes. However, the
Timer 2 Clock Select bits (T2MH and T2ML in register CKCON) may still be used to
select between the external clock and the system clock for either timer.
0: System clock divided by 12.
1: External clock divided by 8 (synchronized with SYSCLK when not in suspend).
222
Rev. 1.0
C8051F80x-83x
SFR Definition 28.9. TMR2RLL: Timer 2 Reload Register Low Byte
Bit
7
6
5
4
3
2
1
0
TMR2RLL[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xCA
Bit Name
Function
7:0 TMR2RLL[7:0] Timer 2 Reload Register Low Byte.
TMR2RLL holds the low byte of the reload value for Timer 2.
SFR Definition 28.10. TMR2RLH: Timer 2 Reload Register High Byte
Bit
7
6
5
4
3
2
1
0
TMR2RLH[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xCB
Bit Name
Function
7:0 TMR2RLH[7:0] Timer 2 Reload Register High Byte.
TMR2RLH holds the high byte of the reload value for Timer 2.
Rev. 1.0
223
C8051F80x-83x
SFR Definition 28.11. TMR2L: Timer 2 Low Byte
Bit
7
6
5
4
3
2
1
0
TMR2L[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xCC
Bit Name
7:0 TMR2L[7:0] Timer 2 Low Byte.
Function
In 16-bit mode, the TMR2L register contains the low byte of the 16-bit Timer 2. In 8-
bit mode, TMR2L contains the 8-bit low byte timer value.
SFR Definition 28.12. TMR2H Timer 2 High Byte
Bit
7
6
5
4
3
2
1
0
TMR2H[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xCD
Bit Name
7:0 TMR2H[7:0] Timer 2 Low Byte.
Function
In 16-bit mode, the TMR2H register contains the high byte of the 16-bit Timer 2. In 8-
bit mode, TMR2H contains the 8-bit high byte timer value.
224
Rev. 1.0
C8051F80x-83x
29. programmable Counter Array
The programmable counter array (PCA0) provides enhanced timer functionality while requiring less CPU
intervention than the standard 8051 counter/timers. The PCA consists of a dedicated 16-bit counter/timer
and three 16-bit capture/compare modules. Each capture/compare module has its own associated I/O line
(CEXn) which is routed through the Crossbar to Port I/O when enabled. The counter/timer is driven by a
programmable timebase that can select between six sources: system clock, system clock divided by four,
system clock divided by twelve, the external oscillator clock source divided by 8, Timer 0 overflows, or an
external clock signal on the ECI input pin. Each capture/compare module may be configured to operate
independently in one of six modes: Edge-Triggered Capture, Software Timer, High-Speed Output, Fre-
quency Output,
8 to 15-Bit PWM, or 16-Bit PWM (each mode is described in Section
“29.3. Capture/Compare Modules” on page 228). The external oscillator clock option is ideal for real-time
clock (RTC) functionality, allowing the PCA to be clocked by a precision external oscillator while the inter-
nal oscillator drives the system clock. The PCA is configured and controlled through the system controller's
Special Function Registers. The PCA block diagram is shown in Figure 29.1
Important Note: The PCA Module 2 may be used as a watchdog timer (WDT), and is enabled in this mode
following a system reset. Access to certain PCA registers is restricted while WDT mode is enabled.
See Section 29.4 for details.
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
PCA
16-Bit Counter/Timer
CLOCK
MUX
ECI
SYSCLK
External Clock/8
Capture/Compare
Module 0
Capture/Compare
Module 1
Capture/Compare
Module 2 / WDT
Crossbar
Port I/O
Figure 29.1. PCA Block Diagram
Rev. 1.0
225
C8051F80x-83x
29.1. PCA Counter/Timer
The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte
(MSB) of the 16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches
the value of PCA0H into a “snapshot” register; the following PCA0H read accesses this “snapshot” register.
Reading the PCA0L Register first guarantees an accurate reading of the entire 16-bit PCA0 counter.
Reading PCA0H or PCA0L does not disturb the counter operation. The CPS2–CPS0 bits in the PCA0MD
register select the timebase for the counter/timer as shown in Table 29.1.
When the counter/timer overflows from 0xFFFF to 0x0000, the Counter Overflow Flag (CF) in PCA0MD is
set to logic 1 and an interrupt request is generated if CF interrupts are enabled. Setting the ECF bit in
PCA0MD to logic 1 enables the CF flag to generate an interrupt request. The CF bit is not automatically
cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by soft-
ware. Clearing the CIDL bit in the PCA0MD register allows the PCA to continue normal operation while the
CPU is in Idle mode.
Table 29.1. PCA Timebase Input Options
CPS2
CPS1
CPS0 Timebase
0
0
0
0
0
1
0
1
0
System clock divided by 12
System clock divided by 4
Timer 0 overflow
High-to-low transitions on ECI (max rate = system clock divided
by 4)
0
1
1
1
1
1
0
0
1
0
1
x
System clock
External oscillator source divided by 8 (Note)
Reserved
Note: External oscillator source divided by 8 is synchronized with the system clock.
IDLE
PCA0MD
PCA0CN
C WW C C C E
I D D P P P C
D T L S S S F
L E C 2 1 0
K
C C
F R
C C C
C C C
F F F
2 1 0
To SFR Bus
PCA0L
read
Snapshot
Register
SYSCLK/12
SYSCLK/4
000
001
Timer 0 Overflow
ECI
010
011
100
101
0
Overflow
To PCA Interrupt System
PCA0H
PCA0L
1
SYSCLK
CF
External Clock/8
To PCA Modules
Figure 29.2. PCA Counter/Timer Block Diagram
226
Rev. 1.0
C8051F80x-83x
29.2. PCA0 Interrupt Sources
Figure 29.3 shows a diagram of the PCA interrupt tree. There are five independent event flags that can be
used to generate a PCA0 interrupt. They are: the main PCA counter overflow flag (CF), which is set upon
a 16-bit overflow of the PCA0 counter, an intermediate overflow flag (COVF), which can be set on an over-
flow from the 8th through 15th bit of the PCA0 counter, and the individual flags for each PCA channel
(CCF0, CCF1, and CCF2), which are set according to the operation mode of that module. These event
flags are always set when the trigger condition occurs. Each of these flags can be individually selected to
generate a PCA0 interrupt, using the corresponding interrupt enable flag (ECF for CF, ECOV for COVF,
and ECCFn for each CCFn). PCA0 interrupts must be globally enabled before any individual interrupt
sources are recognized by the processor. PCA0 interrupts are globally enabled by setting the EA bit in the
IE register and the EPCA0 bit in the EIE1 register to logic 1.
(for n = 0 to 2)
PCA0CPMn
PCA0CN
PCA0MD
PCA0PWM
P E C C M T P E
WC A A A O WC
MO P P T G M C
1 M P N n n n F
C C
F R
C C C
C C C
F F F
2 1 0
C WW C C C E
I D D P P P C
D T L S S S F
L E C 2 1 0
K
A E C E C C C
R C O A L L L
S O V R S S S
E V F 1 E E E
6 n n n
n
n
L
6 L L L
2 1 0
PCA Counter/Timer 8-bit
through 15-bit Overflow
Set 8 through 15 bit Operation
EPCA0
0
1
PCA Counter/Timer 16-
bit Overflow
0
1
EA
ECCF0
Interrupt
Priority
Decoder
0
1
0
1
0
1
PCA Module 0
(CCF0)
ECCF1
ECCF2
0
1
PCA Module 1
(CCF1)
0
1
PCA Module 2
(CCF2)
Figure 29.3. PCA Interrupt Block Diagram
Rev. 1.0
227
C8051F80x-83x
29.3. Capture/Compare Modules
Each module can be configured to operate independently in one of six operation modes: edge-triggered
capture, software timer, high-speed output, frequency output, 8-bit through 15-bit pulse width modulator, or
16-bit pulse width modulator. Each module has Special Function Registers (SFRs) associated with it in the
CIP-51 system controller. These registers are used to exchange data with a module and configure the
module's mode of operation. Table 29.2 summarizes the bit settings in the PCA0CPMn and PCA0PWM
registers used to select the PCA capture/compare module’s operating mode. Note that all modules set to
use 8-bit through 15-bit PWM mode must use the same cycle length (8–15 bits). Setting the ECCFn bit in a
PCA0CPMn register enables the module's CCFn interrupt.
Table 29.2. PCA0CPM and PCA0PWM Bit Settings for PCA Capture/Compare Modules1,2,3,4,5,6
Operational Mode
PCA0CPMn
PCA0PWM
Bit Number 7 6 5 4 3 2 1 0 7 6 5 4 3 2–0
Capture triggered by positive edge on CEXn
Capture triggered by negative edge on CEXn
Capture triggered by any transition on CEXn
Software Timer
X X 1 0 0 0 0 A 0 X B X X XXX
X X 0 1 0 0 0 A 0 X B X X XXX
X X 1 1 0 0 0 A 0 X B X X XXX
X C 0 0 1 0 0 A 0 X B X X XXX
X C 0 0 1 1 0 A 0 X B X X XXX
X C 0 0 0 1 1 A 0 X B X X XXX
0 C 0 0 E 0 1 A 0 X B X X 000
0 C 0 0 E 0 1 A D X B X X 001
0 C 0 0 E 0 1 A D X B X X 010
0 C 0 0 E 0 1 A D X B X X 011
0 C 0 0 E 0 1 A D X B X X 100
0 C 0 0 E 0 1 A D X B X X 101
0 C 0 0 E 0 1 A D X B X X 110
0 C 0 0 E 0 1 A D X B X X 111
1 C 0 0 E 0 1 A 0 X B X 0 XXX
1 C 0 0 E 0 1 A D X B X 1 XXX
High Speed Output
Frequency Output
7
8-Bit Pulse Width Modulator
7
9-Bit Pulse Width Modulator
7
10-Bit Pulse Width Modulator
7
11-Bit Pulse Width Modulator
7
12-Bit Pulse Width Modulator
7
13-Bit Pulse Width Modulator
7
14-Bit Pulse Width Modulator
7
15-Bit Pulse Width Modulator
16-Bit Pulse Width Modulator
16-Bit Pulse Width Modulator with Auto-Reload
Notes:
1. X = Don’t Care (no functional difference for individual module if 1 or 0).
2. A = Enable interrupts for this module (PCA interrupt triggered on CCFn set to 1).
3. B = Enable 8th through 15th bit overflow interrupt (Depends on setting of CLSEL[2:0]).
4. C = When set to 0, the digital comparator is off. For high speed and frequency output modes, the
associated pin will not toggle. In any of the PWM modes, this generates a 0% duty cycle (output = 0).
5. D = Selects whether the Capture/Compare register (0) or the Auto-Reload register (1) for the associated
channel is accessed via addresses PCA0CPHn and PCA0CPLn.
6. E = When set, a match event will cause the CCFn flag for the associated channel to be set.
7. All modules set to 8-bit through 15-bit PWM mode use the same cycle length setting.
228
Rev. 1.0
C8051F80x-83x
29.3.1. Edge-Triggered Capture Mode
In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA coun-
ter/timer and load it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and
PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn register are used to select the type of transi-
tion that triggers the capture: low-to-high transition (positive edge), high-to-low transition (negative edge),
or either transition (positive or negative edge). When a capture occurs, the Capture/Compare Flag (CCFn)
in PCA0CN is set to logic 1. An interrupt request is generated if the CCFn interrupt for that module is
enabled. The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt ser-
vice routine, and must be cleared by software. If both CAPPn and CAPNn bits are set to logic 1, then the
state of the Port pin associated with CEXn can be read directly to determine whether a rising-edge or fall-
ing-edge caused the capture.
PCA Interrupt
PCA0CPMn
P E C C M T P E
WC A A A O WC
M O P P T G M C
1 M P N n n n F
6 n n n
n
PCA0CN
C C
F R
C C C
C C C
F F F
2 1 0
n
x
x
0 0 0
x
PCA0CPLn
PCA0CPHn
0
1
CEXn
Capture
Port I/O
Crossbar
0
1
PCA
Timebase
PCA0L
PCA0H
Figure 29.4. PCA Capture Mode Diagram
Note: The CEXn input signal must remain high or low for at least 2 system clock cycles to be recognized by the
hardware.
Rev. 1.0
229
C8051F80x-83x
29.3.2. Software Timer (Compare) Mode
In Software Timer mode, the PCA counter/timer value is compared to the module's 16-bit capture/compare
register (PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in
PCA0CN is set to logic 1. An interrupt request is generated if the CCFn interrupt for that module is
enabled. The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt ser-
vice routine, and must be cleared by software. Setting the ECOMn and MATn bits in the PCA0CPMn regis-
ter enables Software Timer mode.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Cap-
ture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
Write to
0
PCA0CPLn
ENB
Reset
Write to
PCA0CPHn
ENB
PCA Interrupt
1
PCA0CPMn
P E C C M T P E
WC A A A O WC
M O P P T G M C
1 M P N n n n F
PCA0CN
C C C C C
F R
C C C
F F F
2 1 0
PCA0CPLn
PCA0CPHn
6 n n n
n
n
x
0 0
0 0
x
0
1
Enable
Match
16-bit Comparator
PCA
Timebase
PCA0L
PCA0H
Figure 29.5. PCA Software Timer Mode Diagram
230
Rev. 1.0
C8051F80x-83x
29.3.3. High-Speed Output Mode
In high-speed output mode, a module’s associated CEXn pin is toggled each time a match occurs between
the PCA Counter and the module's 16-bit capture/compare register (PCA0CPHn and PCA0CPLn). When a
match occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1. An interrupt request is gen-
erated if the CCFn interrupt for that module is enabled. The CCFn bit is not automatically cleared by hard-
ware when the CPU vectors to the interrupt service routine, and must be cleared by software. Setting the
TOGn, MATn, and ECOMn bits in the PCA0CPMn register enables the high-speed output mode. If ECOMn
is cleared, the associated pin will retain its state, and not toggle on the next match event.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Cap-
ture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
Write to
0
PCA0CPLn
ENB
Reset
PCA0CPMn
Write to
PCA0CPHn
P E C C M T P E
WC A A A O WC
MO P P T G M C
1 M P N n n n F
ENB
1
6 n n n
n
n
x
0 0
0
x
PCA Interrupt
PCA0CN
C C C C C
F R
C C C
F F F
2 1 0
PCA0CPLn
PCA0CPHn
0
1
Enable
Match
16-bit Comparator
TOGn
Toggle
0
CEXn
Crossbar
Port I/O
1
PCA
Timebase
PCA0L
PCA0H
Figure 29.6. PCA High-Speed Output Mode Diagram
Rev. 1.0
231
C8051F80x-83x
29.3.4. Frequency Output Mode
Frequency Output Mode produces a programmable-frequency square wave on the module’s associated
CEXn pin. The capture/compare module high byte holds the number of PCA clocks to count before the out-
put is toggled. The frequency of the square wave is then defined by Equation 29.1.
FPCA
FCEXn = ----------------------------------------
2 PCA0CPHn
Note: A value of 0x00 in the PCA0CPHn register is equal to 256 for this equation.
Equation 29.1. Square Wave Frequency Output
Where F
is the frequency of the clock selected by the CPS2–0 bits in the PCA mode register,
PCA
PCA0MD. The lower byte of the capture/compare module is compared to the PCA counter low byte; on a
match, CEXn is toggled and the offset held in the high byte is added to the matched value in PCA0CPLn.
Frequency Output Mode is enabled by setting the ECOMn, TOGn, and PWMn bits in the PCA0CPMn reg-
ister. The MATn bit should normally be set to 0 in this mode. If the MATn bit is set to 1, the CCFn flag for
the channel will be set when the 16-bit PCA0 counter and the 16-bit capture/compare register for the chan-
nel are equal.
Write to
0
PCA0CPLn
ENB
Reset
PCA0CPMn
P E C C M T P E
WC A A A O WC
MO P P T G M C
1 M P N n n n F
Write to
PCA0CPHn
ENB
PCA0CPLn
8-bit Adder
PCA0CPHn
1
Adder
Enable
6 n n n
n
n
TOGn
x
0 0 0
x
Toggle
0
CEXn
8-bit
Comparator
match
Enable
Crossbar
Port I/O
1
PCA Timebase
PCA0L
Figure 29.7. PCA Frequency Output Mode
29.3.5. 8-bit through 15-bit Pulse Width Modulator Modes
Each module can be used independently to generate a pulse width modulated (PWM) output on its associ-
ated CEXn pin. The frequency of the output is dependent on the timebase for the PCA counter/timer, and
the setting of the PWM cycle length (8, 9, 10, 11, 12, 13, 14, or 15-bits). For backwards-compatibility with
the 8-bit PWM mode available on other devices, the 8-bit PWM mode operates slightly different than 9, 10,
11, 12, 13, 14, and 15-bit PWM modes. It is important to note that all channels configured for 8-bit
through 15-bit PWM mode will use the same cycle length. For example, it is not possible to configure
one channel for 8-bit PWM mode and another for 11-bit mode. However, other PCA channels can be con-
figured to Pin Capture, High-Speed Output, Software Timer, Frequency Output, or 16-bit PWM mode inde-
pendently.
232
Rev. 1.0
C8051F80x-83x
29.3.5.1. 8-bit Pulse Width Modulator Mode
The duty cycle of the PWM output signal in 8-bit PWM mode is varied using the module's PCA0CPLn cap-
ture/compare register. When the value in the low byte of the PCA counter/timer (PCA0L) is equal to the
value in PCA0CPLn, the output on the CEXn pin will be set. When the count value in PCA0L overflows, the
CEXn output will be reset (see Figure 29.8). Also, when the counter/timer low byte (PCA0L) overflows from
0xFF to 0x00, PCA0CPLn is reloaded automatically with the value stored in the module’s capture/compare
high byte (PCA0CPHn) without software intervention. This synchronous update feature allows software to
asynchronously write a new PWM high time, which will then take effect on the following PWM period.
Setting the ECOMn and PWMn bits in the PCA0CPMn register, and setting the CLSEL bits in register
PCA0PWM to 000b enables 8-Bit Pulse Width Modulator mode. If the MATn bit is set to 1, the CCFn flag
for the module will be set each time an 8-bit comparator match (rising edge) occurs. The COVF flag in
PCA0PWM can be used to detect the overflow (falling edge), which will occur every 256 PCA clock cycles.
The duty cycle for 8-Bit PWM Mode is given in Equation 29.2.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Cap-
ture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
256 – PCA0CPHn
Duty Cycle = ---------------------------------------------------
256
Equation 29.2. 8-Bit PWM Duty Cycle
Using Equation 29.2, the largest duty cycle is 100% (PCA0CPHn = 0), and the smallest duty cycle is
0.39% (PCA0CPHn = 0xFF). A 0% duty cycle may be generated by clearing the ECOMn bit to 0.
Write to
0
PCA0CPLn
ENB
Reset
PCA0CPHn
PCA0CPLn
Write to
PCA0CPHn
ENB
COVF
1
PCA0PWM
PCA0CPMn
A E C E C C C
R C O A L L L
S O V R S S S
E V F 1 E E E
P E C C M T P E
WC A A A O WC
M O P P T G M C
1 M P N n n n F
L
6 L L L
2 1 0
6 n n n
n
n
0
x
x
0
0
0
0
0 0 x 0
x
8-bit
Comparator
SET
CLR
CEXn
Enable
Match
S
R
Q
Q
Crossbar
Port I/O
PCA Timebase
PCA0L
Overflow
Figure 29.8. PCA 8-Bit PWM Mode Diagram
Rev. 1.0
233
C8051F80x-83x
29.3.5.2. 9-bit through 15-bit Pulse Width Modulator Mode
The duty cycle of the PWM output signal in N-bit PWM mode (N=9 through 15) should be varied by writing
to an “Auto-Reload” Register, which is dual-mapped into the PCA0CPHn and PCA0CPLn register loca-
tions. The data written to define the duty cycle should be right-justified in the registers. The auto-reload
registers are accessed (read or written) when the bit ARSEL in PCA0PWM is set to 1. The capture/com-
pare registers are accessed when ARSEL is set to 0.
When the least-significant N bits of the PCA0 counter match the value in the associated module’s cap-
ture/compare register (PCA0CPn), the output on CEXn is asserted high. When the counter overflows from
the Nth bit, CEXn is asserted low (see Figure 29.9). Upon an overflow from the Nth bit, the COVF flag is
set, and the value stored in the module’s auto-reload register is loaded into the capture/compare register.
The value of N is determined by the CLSEL bits in register PCA0PWM. This synchronous update feature
allows software to asynchronously write a new PWM high time, which will then take effect on the following
PWM period.
The 9, 10, 11, 12, 13, 14, or 15-bit PWM mode is selected by setting the ECOMn and PWMn bits in the
PCA0CPMn register, and setting the CLSEL bits in register PCA0PWM to the desired cycle length (other
than 8-bits). If the MATn bit is set to 1, the CCFn flag for the module will be set each time a comparator
match (rising edge) occurs. The COVF flag in PCA0PWM can be used to detect the overflow (falling edge),
which will occur every 512 (9-bit), 1024 (10-bit), 2048 (11-bit), 4096 (12-bit), 8192 (13-bit), 16384 (14-bit),
or 32768 (15-bit) PCA clock cycles. The duty cycle for n-Bit PWM Mode (n=9 through 15) is given in
Equation 29.2, where N is the number of bits in the PWM cycle. A 0% duty cycle may be generated by
clearing the ECOMn bit to 0.
Important Note About PCA0CPHn and PCA0CPLn Registers: When writing a 16-bit value to the
PCA0CPn registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn
bit to 0; writing to PCA0CPHn sets ECOMn to 1.
2N – PCA0CPn
Duty Cycle = -------------------------------------------
2N
Equation 29.3. N-Bit PWM Duty Cycle (N=9 through 15)
Write to
0
PCA0CPLn
R/W when
ARSEL = 1
ENB
(Auto-Reload)
PCA0CPH:Ln
(right-justified)
PCA0PWM
Reset
A E C E C C C
R C O A L L L
S O V R S S S
E V F 1 E E E
Write to
PCA0CPHn
ENB
1
L
6 L L L
2 1 0
x
PCA0CPMn
x
P E C C M T P E
WC A A A O WC
MO P P T G M C
1 M P N n n n F
R/W when
ARSEL = 0
(Capture/Compare)
Set “N” bits:
001 = 9 bits
010 = 10 bits
011 = 11 bits
100 = 12 bits
101 = 13 bits
110 = 14 bits
111 = 15 bits
PCA0CPH:Ln
(right-justified)
6 n n n
n
n
0
0 0 x 0
x
SET
CLR
CEXn
Enable
Match
N-bit Comparator
S
R
Q
Q
Crossbar
Port I/O
PCA Timebase
PCA0H:L
Overflow of Nth Bit
Figure 29.9. PCA 9-bit through 15-Bit PWM Mode Diagram
234
Rev. 1.0
C8051F80x-83x
29.3.6. 16-Bit Pulse Width Modulator Mode
A PCA module may be operated in 16-Bit PWM mode. 16-bit PWM mode is independent of the other (8-bit
through 15-bit) PWM modes. In this mode, the 16-bit capture/compare module defines the number of PCA
clocks for the low time of the PWM signal. When the PCA counter matches the module contents, the out-
put on CEXn is asserted high; when the 16-bit counter overflows, CEXn is asserted low. 16-Bit PWM Mode
is enabled by setting the ECOMn, PWMn, and PWM16n bits in the PCA0CPMn register.
The duty cycle of the PWM output signal can be varied by writing to an “Auto-Reload” Register, which is
dual-mapped into the PCA0CPHn and PCA0CPLn register locations. The auto-reload registers are
accessed (read or written) when the bit ARSEL in PCA0PWM is set to 1. The capture/compare registers
are accessed when ARSEL is set to 0. This synchronous update feature allows software to asynchro-
nously write a new PWM high time, which will then take effect on the following PWM period.
For backwards-compatibility with the 16-bit PWM mode available on other devices, the PWM duty cycle
can also be changed without using the “Auto-Reload” register. To output a varying duty cycle without using
the “Auto-Reload” register, new value writes should be synchronized with PCA CCFn match interrupts.
Match interrupts should be enabled (ECCFn = 1 AND MATn = 1) to help synchronize the capture/compare
register writes. If the MATn bit is set to 1, the CCFn flag for the module will be set each time a 16-bit com-
parator match (rising edge) occurs. The CF flag in PCA0CN can be used to detect the overflow (falling
edge). The duty cycle for 16-Bit PWM Mode is given by Equation 29.4.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Cap-
ture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
65536 – PCA0CPn
Duty Cycle = ----------------------------------------------------
65536
Equation 29.4. 16-Bit PWM Duty Cycle
Using Equation 29.4, the largest duty cycle is 100% (PCA0CPn = 0), and the smallest duty cycle is
0.0015% (PCA0CPn = 0xFFFF). A 0% duty cycle may be generated by clearing the ECOMn bit to 0.
Write to
0
PCA0CPLn
R/W when
ARSEL = 1
ENB
PCA0PW M
A E C E C C C
(Auto-Reload)
Reset
PCA0CPH:Ln
R C O
S O V
A
R S
1
6
L
L
S
E
L
1
x
L
S
E
L
0
x
Write to
PCA0CPHn
ENB
1
E
L
V
F
E
L
2
x
PCA0CPMn
E C C M T
x
R/W when
ARSEL = 0
P
P E
(Capture/Compare)
PCA0CPH:Ln
W C A
M O P
A
P
A O W C
T G M C
1 M P N
n
n
n
F
n
6
n
1
n
n
n
0
0
x
0
x
CEXn
Enable
SET
Match
16-bit Comparator
S
R
Q
Q
Crossbar
Port I/O
CLR
PCA Timebase
PCA0H:L
Overflow
Figure 29.10. PCA 16-Bit PWM Mode
Rev. 1.0
235
C8051F80x-83x
29.4. Watchdog Timer Mode
A programmable watchdog timer (WDT) function is available through the PCA Module 2. The WDT is used
to generate a reset if the time between writes to the WDT update register (PCA0CPH2) exceed a specified
limit. The WDT can be configured and enabled/disabled as needed by software.
With the WDTE bit set in the PCA0MD register, Module 2 operates as a watchdog timer (WDT). The Mod-
ule 2 high byte is compared to the PCA counter high byte; the Module 2 low byte holds the offset to be
used when WDT updates are performed. The Watchdog Timer is enabled on reset. Writes to some
PCA registers are restricted while the Watchdog Timer is enabled. The WDT will generate a reset
shortly after code begins execution. To avoid this reset, the WDT should be explicitly disabled (and option-
ally re-configured and re-enabled if it is used in the system).
29.4.1. Watchdog Timer Operation
While the WDT is enabled:
PCA counter is forced on.
Writes to PCA0L and PCA0H are not allowed.
PCA clock source bits (CPS2–CPS0) are frozen.
PCA Idle control bit (CIDL) is frozen.
Module 2 is forced into software timer mode.
Writes to the Module 2 mode register (PCA0CPM2) are disabled.
While the WDT is enabled, writes to the CR bit will not change the PCA counter state; the counter will run
until the WDT is disabled. The PCA counter run control bit (CR) will read zero if the WDT is enabled but
user software has not enabled the PCA counter. If a match occurs between PCA0CPH2 and PCA0H while
the WDT is enabled, a reset will be generated. To prevent a WDT reset, the WDT may be updated with a
write of any value to PCA0CPH2. Upon a PCA0CPH2 write, PCA0H plus the offset held in PCA0CPL2 is
loaded into PCA0CPH2 (See Figure 29.11).
PCA0MD
C WW C C C E
I D D P P P C
PCA0CPH2
D T L S S S F
L E C 2 1 0
K
8-bit
Comparator
Match
Reset
Enable
PCA0L Overflow
PCA0CPL2
8-bit Adder
PCA0H
Adder
Enable
Write to
PCA0CPH2
Figure 29.11. PCA Module 2 with Watchdog Timer Enabled
The 8-bit offset held in PCA0CPH2 is compared to the upper byte of the 16-bit PCA counter. This offset
value is the number of PCA0L overflows before a reset. Up to 256 PCA clocks may pass before the first
PCA0L overflow occurs, depending on the value of the PCA0L when the update is performed. The total off-
236
Rev. 1.0
C8051F80x-83x
set is then given (in PCA clocks) by Equation 29.5, where PCA0L is the value of the PCA0L register at the
time of the update.
Offset = 256 PCA0CPL2 + 256 – PCA0L
Equation 29.5. Watchdog Timer Offset in PCA Clocks
The WDT reset is generated when PCA0L overflows while there is a match between PCA0CPH2 and
PCA0H. Software may force a WDT reset by writing a 1 to the CCF2 flag (PCA0CN.2) while the WDT is
enabled.
29.4.2. Watchdog Timer Usage
To configure the WDT, perform the following tasks:
1. Disable the WDT by writing a 0 to the WDTE bit.
2. Select the desired PCA clock source (with the CPS2–CPS0 bits).
3. Load PCA0CPL2 with the desired WDT update offset value.
4. Configure the PCA Idle mode (set CIDL if the WDT should be suspended while the CPU is in Idle
mode).
5. Enable the WDT by setting the WDTE bit to 1.
6. Reset the WDT timer by writing to PCA0CPH2.
The PCA clock source and Idle mode select cannot be changed while the WDT is enabled. The watchdog
timer is enabled by setting the WDTE or WDLCK bits in the PCA0MD register. When WDLCK is set, the
WDT cannot be disabled until the next system reset. If WDLCK is not set, the WDT is disabled by clearing
the WDTE bit.
The WDT is enabled following any reset. The PCA0 counter clock defaults to the system clock divided by
12, PCA0L defaults to 0x00, and PCA0CPL2 defaults to 0x00. Using Equation 29.5, this results in a WDT
timeout interval of 256 PCA clock cycles, or 3072 system clock cycles. Table 29.3 lists some example time-
out intervals for typical system clocks.
Table 29.3. Watchdog Timer Timeout Intervals1
System Clock (Hz)
PCA0CPL2
Timeout Interval (ms)
24,500,000
24,500,000
24,500,000
255
128
32
255
128
32
32.1
16.2
4.1
257
129.5
33.1
2
3,062,500
2
3,062,500
2
3,062,500
32,000
32,000
32,000
255
128
32
24576
12384
3168
Notes:
1. Assumes SYSCLK/12 as the PCA clock source, and a PCA0L value
of 0x00 at the update time.
2. Internal SYSCLK reset frequency = Internal Oscillator divided by 8.
29.5. Register Descriptions for PCA0
Following are detailed descriptions of the special function registers related to the operation of the PCA.
Rev. 1.0
237
C8051F80x-83x
SFR Definition 29.1. PCA0CN: PCA0 Control
Bit
7
6
5
4
3
2
1
0
CF
CR
CCF2
CCF1
CCF0
Name
Type
Reset
R/W
0
R/W
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
SFR Address = 0xD8; Bit-Addressable
Bit
Name
Function
7
CF
PCA Counter/Timer Overflow Flag.
Set by hardware when the PCA Counter/Timer overflows from 0xFFFF to 0x0000.
When the Counter/Timer Overflow (CF) interrupt is enabled, setting this bit causes the
CPU to vector to the PCA interrupt service routine. This bit is not automatically cleared
by hardware and must be cleared by software.
6
CR
PCA Counter/Timer Run Control.
This bit enables/disables the PCA Counter/Timer.
0: PCA Counter/Timer disabled.
1: PCA Counter/Timer enabled.
5:3
2
Unused Read = 000b, Write = Don't care.
CCF2
CCF1
CCF0
PCA Module 2 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF2 interrupt
is enabled, setting this bit causes the CPU to vector to the PCA interrupt service rou-
tine. This bit is not automatically cleared by hardware and must be cleared by software.
1
0
PCA Module 1 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF1 interrupt
is enabled, setting this bit causes the CPU to vector to the PCA interrupt service rou-
tine. This bit is not automatically cleared by hardware and must be cleared by software.
PCA Module 0 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF0 interrupt
is enabled, setting this bit causes the CPU to vector to the PCA interrupt service rou-
tine. This bit is not automatically cleared by hardware and must be cleared by software.
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SFR Definition 29.2. PCA0MD: PCA0 Mode
Bit
7
6
5
4
3
2
1
0
CIDL
WDTE
WDLCK
CPS2
CPS1
CPS0
ECF
Name
Type
Reset
R/W
0
R/W
1
R/W
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Address = 0xD9
Bit
Name
Function
7
CIDL
PCA Counter/Timer Idle Control.
Specifies PCA behavior when CPU is in idle mode.
0: PCA continues to function normally while the system controller is in Idle mode.
1: PCA operation is suspended while the system controller is in idle mode.
6
5
WDTE Watchdog Timer Enable.
If this bit is set, PCA Module 2 is used as the watchdog timer.
0: Watchdog Timer disabled.
1: PCA Module 2 enabled as Watchdog Timer.
WDLCK Watchdog Timer Lock.
This bit locks/unlocks the Watchdog Timer Enable. When WDLCK is set, the Watchdog
Timer may not be disabled until the next system reset.
0: Watchdog Timer Enable unlocked.
1: Watchdog Timer Enable locked.
4
Unused Read = 0b, Write = Don't care.
3:1 CPS[2:0] PCA Counter/Timer Pulse Select.
These bits select the timebase source for the PCA counter
000: System clock divided by 12
001: System clock divided by 4
010: Timer 0 overflow
011: High-to-low transitions on ECI (max rate = system clock divided by 4)
100: System clock
101: External clock divided by 8 (synchronized with the system clock)
11x: Reserved
0
ECF
PCA Counter/Timer Overflow Interrupt Enable.
This bit sets the masking of the PCA Counter/Timer Overflow (CF) interrupt.
0: Disable the CF interrupt.
1: Enable a PCA Counter/Timer Overflow interrupt request when CF (PCA0CN.7) is
set.
Note: When the WDTE bit is set to 1, the other bits in the PCA0MD register cannot be modified. To change the
contents of the PCA0MD register, the Watchdog Timer must first be disabled.
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SFR Definition 29.3. PCA0PWM: PCA0 PWM Configuration
Bit
7
ARSEL
R/W
0
6
ECOV
R/W
0
5
COVF
R/W
0
4
3
EAR16
R/W
0
2
1
CLSEL[1:0]
R/W
0
Name
Type
Reset
R
0
0
0
0
SFR Address = 0xF7
Bit
Name
Function
7
ARSEL
Auto-Reload Register Select.
This bit selects whether to read and write the normal PCA capture/compare registers
(PCA0CPn), or the Auto-Reload registers at the same SFR addresses. This function
is used to define the reload value for 9-bit through 15-bit PWM mode and 16-bit PWM
mode. In all other modes, the Auto-Reload registers have no function.
0: Read/Write Capture/Compare Registers at PCA0CPHn and PCA0CPLn.
1: Read/Write Auto-Reload Registers at PCA0CPHn and PCA0CPLn.
6
5
ECOV
COVF
Cycle Overflow Interrupt Enable.
This bit sets the masking of the Cycle Overflow Flag (COVF) interrupt.
0: COVF will not generate PCA interrupts.
1: A PCA interrupt will be generated when COVF is set.
Cycle Overflow Flag.
This bit indicates an overflow of the nth bit (n= 9 through 15) of the main PCA counter
(PCA0). The specific bit used for this flag depends on the setting of the CLSEL bits.
The bit can be set by hardware or software, but must be cleared by software.
0: No overflow has occurred since the last time this bit was cleared.
1: An overflow has occurred since the last time this bit was cleared.
4
3
Unused
EAR16
Read = 0b; Write = Don’t care.
16-Bit PWM Auto-Reload Enable.
This bit controls the Auto-Reload feature in 16-bit PWM mode, which loads the
PCA0CPn capture/compare registers with the values from the Auto-Reload registers
at the same SFR addresses on an overflow of the PCA counter (PCA0). This setting
affects all PCA channels that are configured to use 16-bit PWM mode.
0: 16-bit PWM mode Auto-Reload is disabled. This default setting is backwards-com-
patible with the 16-bit PWM mode available on other devices.
1: 16-bit PWM mode Auto-Reload is enabled.
2:0 CLSEL[2:0] Cycle Length Select.
When 16-bit PWM mode is not selected, these bits select the length of the PWM
cycle, from 8 to 15 bits. This affects all channels configured for PWM which are not
using 16-bit PWM mode. These bits are ignored for individual channels configured
to16-bit PWM mode.
000: 8 bits.
001: 9 bits.
010: 10 bits.
011: 11 bits.
100: 12 bits.
101: 13 bits.
110: 14 bits.
111: 15 bits.
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SFR Definition 29.4. PCA0CPMn: PCA0 Capture/Compare Mode
Bit
7
6
5
4
3
2
1
0
PWM16n
ECOMn
CAPPn
CAPNn
MATn
TOGn
PWMn
ECCFn
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Addresses: PCA0CPM0 = 0xDA, PCA0CPM1 = 0xDB, PCA0CPM2 = 0xDC
Bit
Name
Function
7
PWM16n 16-bit Pulse Width Modulation Enable.
This bit enables 16-bit mode when Pulse Width Modulation mode is enabled.
0: 8 to 15-bit PWM selected.
1: 16-bit PWM selected.
6
5
4
3
ECOMn Comparator Function Enable.
This bit enables the comparator function for PCA module n when set to 1.
CAPPn Capture Positive Function Enable.
This bit enables the positive edge capture for PCA module n when set to 1.
CAPNn Capture Negative Function Enable.
This bit enables the negative edge capture for PCA module n when set to 1.
MATn
Match Function Enable.
This bit enables the match function for PCA module n when set to 1. When enabled,
matches of the PCA counter with a module's capture/compare register cause the CCFn
bit in PCA0MD register to be set to logic 1.
2
1
0
TOGn
Toggle Function Enable.
This bit enables the toggle function for PCA module n when set to 1. When enabled,
matches of the PCA counter with a module's capture/compare register cause the logic
level on the CEXn pin to toggle. If the PWMn bit is also set to logic 1, the module oper-
ates in Frequency Output Mode.
PWMn Pulse Width Modulation Mode Enable.
This bit enables the PWM function for PCA module n when set to 1. When enabled, a
pulse width modulated signal is output on the CEXn pin. 8 to 15-bit PWM is used if
PWM16n is cleared; 16-bit mode is used if PWM16n is set to logic 1. If the TOGn bit is
also set, the module operates in Frequency Output Mode.
ECCFn Capture/Compare Flag Interrupt Enable.
This bit sets the masking of the Capture/Compare Flag (CCFn) interrupt.
0: Disable CCFn interrupts.
1: Enable a Capture/Compare Flag interrupt request when CCFn is set.
Note: When the WDTE bit is set to 1, the PCA0CPM2 register cannot be modified, and module 2 acts as the
watchdog timer. To change the contents of the PCA0CPM2 register or the function of module 2, the Watchdog
Timer must be disabled.
Rev. 1.0
241
C8051F80x-83x
SFR Definition 29.5. PCA0L: PCA0 Counter/Timer Low Byte
Bit
7
6
5
4
3
2
1
0
PCA0[7:0]
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Address = 0xF9
Bit Name
7:0 PCA0[7:0] PCA Counter/Timer Low Byte.
Function
The PCA0L register holds the low byte (LSB) of the 16-bit PCA Counter/Timer.
Note: When the WDTE bit is set to 1, the PCA0L register cannot be modified by software. To change the contents of
the PCA0L register, the Watchdog Timer must first be disabled.
SFR Definition 29.6. PCA0H: PCA0 Counter/Timer High Byte
Bit
7
6
5
4
3
2
1
0
PCA0[15:8]
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Address = 0xFA
Bit Name
7:0 PCA0[15:8] PCA Counter/Timer High Byte.
Function
The PCA0H register holds the high byte (MSB) of the 16-bit PCA Counter/Timer.
Reads of this register will read the contents of a “snapshot” register, whose contents
are updated only when the contents of PCA0L are read (see Section 29.1).
Note: When the WDTE bit is set to 1, the PCA0H register cannot be modified by software. To change the contents of
the PCA0H register, the Watchdog Timer must first be disabled.
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SFR Definition 29.7. PCA0CPLn: PCA0 Capture Module Low Byte
Bit
7
6
5
4
3
2
1
0
PCA0CPn[7:0]
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Addresses: PCA0CPL0 = 0xFB, PCA0CPL1 = 0xE9, PCA0CPL2 = 0xEB
Bit Name Function
7:0 PCA0CPn[7:0] PCA Capture Module Low Byte.
The PCA0CPLn register holds the low byte (LSB) of the 16-bit capture module n.
This register address also allows access to the low byte of the corresponding
PCA channel’s auto-reload value for 9-bit through 15-bit PWM mode and 16-bit
PWM mode. The ARSEL bit in register PCA0PWM controls which register is
accessed.
Note: A write to this register will clear the module’s ECOMn bit to a 0.
SFR Definition 29.8. PCA0CPHn: PCA0 Capture Module High Byte
Bit
7
6
5
4
3
2
1
0
PCA0CPn[15:8]
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Addresses: PCA0CPH0 = 0xFC, PCA0CPH1 = 0xEA, PCA0CPH2 = 0xEC
Bit Name Function
7:0 PCA0CPn[15:8] PCA Capture Module High Byte.
The PCA0CPHn register holds the high byte (MSB) of the 16-bit capture module n.
This register address also allows access to the high byte of the corresponding
PCA channel’s auto-reload value for 9-bit through 15-bit PWM mode and 16-bit
PWM mode. The ARSEL bit in register PCA0PWM controls which register is
accessed.
Note: A write to this register will set the module’s ECOMn bit to a 1.
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C8051F80x-83x
30. C2 Interface
C8051F80x-83x devices include an on-chip Silicon Labs 2-Wire (C2) debug interface to allow Flash pro-
gramming and in-system debugging with the production part installed in the end application. The C2 inter-
face operates using only two pins: a bi-directional data signal (C2D), and a clock input (C2CK). See the C2
Interface Specification for details on the C2 protocol.
30.1. C2 Interface Registers
The following describes the C2 registers necessary to perform Flash programming functions through the
C2 interface. All C2 registers are accessed through the C2 interface as described in the C2 Interface Spec-
ification.
C2 Register Definition 30.1. C2ADD: C2 Address
Bit
7
6
5
4
3
2
1
0
C2ADD[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
Bit
Name
Function
7:0 C2ADD[7:0] C2 Address.
The C2ADD register is accessed via the C2 interface to select the target Data register
for C2 Data Read and Data Write commands.
Address Name
Description
0x00
0x01
0x02
0xBF
0xD2
0xD3
0xCE
0xDE
0xCF
0xDD
DEVICEID
Selects the Device ID Register (read only)
Selects the Revision ID Register (read only)
Selects the C2 Flash Programming Control Register
Selects the C2 Flash Data Register
REVID
FPCTL
FPDAT
CRC0AUTO* Selects the CRC0AUTO Register
CRC0CNT*
CRC0CN*
Selects the CRC0CNT Register
Selects the CRC0CN Register
CRC0DATA* Selects the CRC0DATA Register
CRC0FLIP* Selects the CRC0FLIP Register
CRC0IN*
Selects the CRC0IN Register
*Note: CRC registers and functions are described in Section “24. Cyclic Redundancy Check Unit (CRC0)” on
page 159.
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C2 Register Definition 30.2. DEVICEID: C2 Device ID
Bit
7
6
5
4
3
2
1
0
DEVICEID[7:0]
R/W
Name
Type
Reset
1
1
1
0
0
0
0
1
C2 Address: 0x00
Bit Name
7:0 DEVICEID[7:0] Device ID.
This read-only register returns the 8-bit device ID: 0x23 (C8051F80x-83x).
Function
C2 Register Definition 30.3. REVID: C2 Revision ID
Bit
7
6
5
4
3
2
1
0
REVID[7:0]
R/W
Name
Type
Reset
Varies
Varies
Varies
Varies
Varies
Varies
Varies
Varies
C2 Address: 0x01
Bit Name
7:0 REVID[7:0] Revision ID.
This read-only register returns the 8-bit revision ID. For example: 0x00 = Revision A.
Function
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C8051F80x-83x
C2 Register Definition 30.4. FPCTL: C2 Flash Programming Control
Bit
7
6
5
4
3
2
1
0
FPCTL[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
C2 Address: 0x02
Bit Name
7:0 FPCTL[7:0] C2 Flash Programming Control Register.
Function
This register is used to enable Flash programming via the C2 interface. To enable C2
Flash programming, the following codes must be written in order: 0x02, 0x01. Once
C2 Flash programming is enabled, a system reset must be issued to resume normal
operation.
C2 Register Definition 30.5. FPDAT: C2 Flash Programming Data
Bit
7
6
5
4
3
2
1
0
FPDAT[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
C2 Address: 0xBF
Bit Name
7:0 FPDAT[7:0] C2 Flash Programming Data Register.
Function
This register is used to pass Flash commands, addresses, and data during C2 Flash
accesses. Valid commands are listed below.
Code
0x06
0x07
0x08
0x03
Command
Flash Block Read
Flash Block Write
Flash Page Erase
Device Erase
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30.2. C2CK Pin Sharing
The C2 protocol allows the C2 pins to be shared with user functions so that in-system debugging and
Flash programming may be performed. This is possible because C2 communication is typically performed
when the device is in the halt state, where all on-chip peripherals and user software are stalled. In this
halted state, the C2 interface can safely “borrow” the C2CK (RST) and C2D pins. In most applications,
external resistors are required to isolate C2 interface traffic from the user application. A typical isolation
configuration is shown in Figure 30.1.
C8051Fxxx
RST (a)
Input (b)
C2CK
C2D
Output (c)
C2 Interface Master
Figure 30.1. Typical C2 Pin Sharing
The configuration in Figure 30.1 assumes the following:
1. The user input (b) cannot change state while the target device is halted.
2. The RST pin on the target device is used as an input only.
Additional resistors may be necessary depending on the specific application.
Rev. 1.0
247
C8051F80x-83x
DOCUMENT CHANGE LIST
Revision 0.2 to Revision 1.0
Updated Electrical Specification Tables to reflect production characterization data.
Added Minimum SYSCLK specification for writing or erasing Flash.
Added caution for going into suspend with wake source active (Section 20.3)
Corrected VDM0CN reset values to "Varies".
Removed mention of IDAC in Pinout table.
248
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NOTES:
Rev. 1.0
249
C8051F80x-83x
CONTACT INFORMATION
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