C8051T321-GMR [SILICON]
Microcontroller,;
| 型号： | C8051T321-GMR |
| 厂家： | 
SILICON |
| 描述： | Microcontroller, 时钟 微控制器 外围集成电路 |
| 文件： | 总298页 (文件大小：3217K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
C8051T620/1/6/7 & C8051T320/1/2/3
Full Speed USB EPROM MCU Family
High-Speed 8051 µC Core
Analog Peripherals
-
10-Bit ADC (‘T620/6/7 and ‘T320/1 only)
-
Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
•
•
•
Up to 500 ksps
Up to 21 external inputs
-
-
Up to 48 MIPS throughput with 48 MHz clock
Expanded interrupt handler
VREF from on-chip VREF, external pin, Internal 1.8 V
Regulator or VDD
•
•
Internal or external start of conversion source
Built-in temperature sensor
Comparators
-
•
•
•
Programmable hysteresis and response time
Configurable as interrupt or reset source
Low current (<0.5 µA)
USB Function Controller
-
-
USB specification 2.0 compliant
Full speed (12 Mbps) or low speed (1.5 Mbps) oper-
ation
Integrated clock recovery; no external oscillator
required for full speed or low speed
Supports eight flexible endpoints
1 kB USB buffer memory
Integrated transceiver; no external resistors
required
-
-
-
-
On-Chip Debug
-
-
-
C8051F34A can be used as code development plat-
form; Complete development kit available
On-chip debug circuitry facilitates full speed, non-
intrusive in-system debug
Provides breakpoints, single stepping,
inspect/modify memory and registers
Supply Voltage 1.8 to 5.25 V
Package Options:
-
On-chip LDO for internal core supply
-
5 x 5 mm QFN28 or QFN32
-
Built-in supply voltage monitor
-
9 x 9 mm LQFP32
Temperature Range: –40 to +85 °C
ANALOG
PERIPHERALS
DIGITAL I/O
UART0
Port 0
UART1
A
M
U
X
10-bit
500 ksps
ADC
SMBus
VREF
SPI
Port 1
PCA
+
-
Timer 0
Timer 1
Timer 2
Timer 3
+
-
Port 2
P3.0
TEMP
SENSOR
VOLTAGE
COMPARATORS
LOW FREQUENCY INTERNAL
OSCILLATOR
USB Controller /
Transceiver
48 MHz PRECISION INTERNAL
OSCILLATOR
HIGH-SPEED CONTROLLER CORE
64 kB
EPROM
8051 CPU
(48 MIPS)
3328 B SRAM
FLEXIBLE
INTERRUPTS
DEBUG CIRCUITRY
POR WDT
Rev. 1.2 7/12
Copyright © 2012 by Silicon Laboratories
C8051T620/1/6/7 & C8051T320/1/2/3
C8051T620/1/6/7 & C8051T320/1/2/3
2
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
Table of Contents
1. System Overview ..................................................................................................... 15
2. Ordering Information............................................................................................... 21
3. Pin Definitions.......................................................................................................... 22
4. LQFP-32 Package Specifications ........................................................................... 28
5. QFN-32 Package Specifications ............................................................................. 30
6. QFN-28 Package Specifications ............................................................................. 32
7. Electrical Characteristics........................................................................................ 34
7.1. Absolute Maximum Specifications..................................................................... 34
7.2. Electrical Characteristics ................................................................................... 35
7.3. Typical Performance Curves ............................................................................. 44
8. 10-Bit ADC (ADC0, C8051T620/6/7 and C8051T320/1 Only)................................. 45
8.1. Output Code Formatting.................................................................................... 46
8.2. 8-Bit Mode ......................................................................................................... 46
8.3. Modes of Operation........................................................................................... 46
8.3.1. Starting a Conversion................................................................................ 46
8.3.2. Tracking Modes......................................................................................... 47
8.3.3. Settling Time Requirements...................................................................... 48
8.4. Programmable Window Detector....................................................................... 52
8.4.1. Window Detector Example........................................................................ 54
8.5. ADC0 Analog Multiplexer (C8051T620/6/7 and C8051T320/1 Only)................ 55
9. Temperature Sensor (C8051T620/6/7 and C8051T320/1 Only)............................. 57
9.1. Calibration ......................................................................................................... 58
10. Voltage Reference Options................................................................................... 59
11. Voltage Regulators (REG0 and REG1)................................................................. 61
11.1. Voltage Regulator (REG0)............................................................................... 61
11.1.1. Regulator Mode Selection....................................................................... 61
11.1.2. VBUS Detection ...................................................................................... 61
11.2. Voltage Regulator (REG1)............................................................................... 64
12. CIP-51 Microcontroller........................................................................................... 66
12.1. Instruction Set.................................................................................................. 67
12.1.1. Instruction and CPU Timing .................................................................... 67
12.2. CIP-51 Register Descriptions .......................................................................... 73
13. Prefetch Engine...................................................................................................... 76
14. Comparator0 and Comparator1............................................................................ 77
14.1. Comparator Multiplexers ................................................................................. 84
15. Memory Organization ............................................................................................ 87
15.1. Program Memory............................................................................................. 88
15.1.1. Derivative ID............................................................................................ 89
15.1.2. Temperature Offset Calibration............................................................... 89
15.1.3. Serialization............................................................................................. 89
15.2. Data Memory................................................................................................... 90
15.2.1. Internal RAM ........................................................................................... 90
15.2.1.1. General Purpose Registers ............................................................ 90
Rev. 1.2
3
C8051T620/1/6/7 & C8051T320/1/2/3
15.2.1.2. Bit Addressable Locations .............................................................. 90
15.2.1.3. Stack ............................................................................................ 90
15.2.2. External RAM.......................................................................................... 91
15.2.3. Accessing USB FIFO Space................................................................... 91
16. Special Function Registers................................................................................... 95
17. Interrupts .............................................................................................................. 101
17.1. MCU Interrupt Sources and Vectors.............................................................. 102
17.1.1. Interrupt Priorities.................................................................................. 102
17.1.2. Interrupt Latency ................................................................................... 102
17.2. Interrupt Register Descriptions...................................................................... 102
17.3. INT0 and INT1 External Interrupt Sources .................................................... 110
18. Program Memory (EPROM)................................................................................. 112
18.1. Programming the EPROM Memory............................................................... 112
18.1.1. EPROM Programming over the C2 Interface........................................ 112
18.1.2. EPROM In-Application Programming.................................................... 113
18.2. Security Options ............................................................................................ 114
18.3. EPROM Writing Guidelines ........................................................................... 114
18.3.1. VDD Maintenance and the VDD monitor .............................................. 114
18.3.2. PSWE Maintenance.............................................................................. 115
18.3.3. System Clock ........................................................................................ 115
18.4. Program Memory CRC.................................................................................. 115
18.4.1. Performing 32-bit CRCs on Full EPROM Content ................................ 115
18.4.2. Performing 16-bit CRCs on 256-Byte EPROM Blocks.......................... 115
19. Power Management Modes................................................................................. 118
19.1. Idle Mode....................................................................................................... 118
19.2. Stop Mode ..................................................................................................... 119
19.3. Suspend Mode .............................................................................................. 119
20. Reset Sources...................................................................................................... 121
20.1. Power-On Reset............................................................................................ 122
20.2. Power-Fail Reset / VDD Monitor ................................................................... 122
20.3. External Reset............................................................................................... 124
20.4. Missing Clock Detector Reset ....................................................................... 124
20.5. Comparator0 Reset ....................................................................................... 124
20.6. PCA Watchdog Timer Reset ......................................................................... 125
20.7. EPROM Error Reset...................................................................................... 125
20.8. Software Reset.............................................................................................. 125
20.9. USB Reset..................................................................................................... 125
21. Oscillators and Clock Selection ......................................................................... 127
21.1. System Clock Selection................................................................................. 128
21.2. USB Clock Selection ..................................................................................... 128
21.3. Programmable Internal High-Frequency (H-F) Oscillator.............................. 130
21.3.1. Internal Oscillator Suspend Mode......................................................... 130
21.4. Clock Multiplier .............................................................................................. 132
21.5. Programmable Internal Low-Frequency (L-F) Oscillator ............................... 133
21.5.1. Calibrating the Internal L-F Oscillator.................................................... 133
4
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
21.6. External Oscillator Drive Circuit..................................................................... 134
21.6.1. External Crystal Mode........................................................................... 134
21.6.2. External RC Example............................................................................ 136
21.6.3. External Capacitor Example.................................................................. 136
22. Port Input/Output ................................................................................................. 138
22.1. Port I/O Modes of Operation.......................................................................... 139
22.1.1. Port Pins Configured for Analog I/O...................................................... 139
22.1.2. Port Pins Configured For Digital I/O...................................................... 139
22.1.3. Interfacing Port I/O to 5 V Logic............................................................ 140
22.2. Assigning Port I/O Pins to Analog and Digital Functions............................... 140
22.2.1. Assigning Port I/O Pins to Analog Functions ........................................ 140
22.2.2. Assigning Port I/O Pins to Digital Functions.......................................... 140
22.2.3. Assigning Port I/O Pins to External Digital Event Capture Functions ... 141
22.3. Priority Crossbar Decoder ............................................................................. 142
22.4. Port I/O Initialization ...................................................................................... 146
22.5. Port Match ..................................................................................................... 149
22.6. Special Function Registers for Accessing and Configuring Port I/O ............. 152
23. Universal Serial Bus Controller (USB0)............................................................. 160
23.1. Endpoint Addressing ..................................................................................... 161
23.2. USB Transceiver ........................................................................................... 161
23.3. USB Register Access .................................................................................... 163
23.4. USB Clock Configuration............................................................................... 168
23.5. FIFO Management ........................................................................................ 169
23.5.1. FIFO Split Mode.................................................................................... 170
23.5.2. FIFO Double Buffering .......................................................................... 170
23.5.1. FIFO Access ......................................................................................... 171
23.6. Function Addressing...................................................................................... 172
23.7. Function Configuration and Control............................................................... 173
23.8. Interrupts ....................................................................................................... 176
23.9. The Serial Interface Engine........................................................................... 181
23.10. Endpoint0 .................................................................................................... 181
23.10.1. Endpoint0 SETUP Transactions ......................................................... 182
23.10.2. Endpoint0 IN Transactions.................................................................. 182
23.10.3. Endpoint0 OUT Transactions.............................................................. 183
23.11. Configuring Endpoints1-3............................................................................ 185
23.12. Controlling Endpoints1-3 IN......................................................................... 186
23.12.1. Endpoints1-3 IN Interrupt or Bulk Mode.............................................. 186
23.12.2. Endpoints1-3 IN Isochronous Mode.................................................... 187
23.13. Controlling Endpoints1-3 OUT..................................................................... 189
23.13.1. Endpoints1-3 OUT Interrupt or Bulk Mode.......................................... 190
23.13.2. Endpoints1-3 OUT Isochronous Mode................................................ 190
24. SMBus................................................................................................................... 194
24.1. Supporting Documents.................................................................................. 195
24.2. SMBus Configuration..................................................................................... 195
24.3. SMBus Operation .......................................................................................... 195
Rev. 1.2
5
C8051T620/1/6/7 & C8051T320/1/2/3
24.3.1. Transmitter Vs. Receiver....................................................................... 196
24.3.2. Arbitration.............................................................................................. 196
24.3.3. Clock Low Extension............................................................................. 196
24.3.4. SCL Low Timeout.................................................................................. 196
24.3.5. SCL High (SMBus Free) Timeout ......................................................... 197
24.4. Using the SMBus........................................................................................... 197
24.4.1. SMBus Configuration Register.............................................................. 197
24.4.2. SMB0CN Control Register .................................................................... 201
24.4.2.1. Software ACK Generation ............................................................ 201
24.4.2.2. Hardware ACK Generation........................................................... 201
24.4.3. Hardware Slave Address Recognition .................................................. 203
24.4.4. Data Register ........................................................................................ 206
24.5. SMBus Transfer Modes................................................................................. 207
24.5.1. Write Sequence (Master) ...................................................................... 207
24.5.2. Read Sequence (Master)...................................................................... 208
24.5.3. Write Sequence (Slave) ........................................................................ 209
24.5.4. Read Sequence (Slave)........................................................................ 210
24.6. SMBus Status Decoding................................................................................ 210
25. UART0................................................................................................................... 215
25.1. Enhanced Baud Rate Generation.................................................................. 216
25.2. Operational Modes ........................................................................................ 217
25.2.1. 8-Bit UART............................................................................................ 217
25.2.2. 9-Bit UART............................................................................................ 218
25.3. Multiprocessor Communications ................................................................... 219
26. UART1................................................................................................................... 223
26.1. Baud Rate Generator .................................................................................... 223
26.2. Data Format................................................................................................... 225
26.3. Configuration and Operation ......................................................................... 226
26.3.1. Data Transmission ................................................................................ 226
26.3.2. Data Reception ..................................................................................... 226
26.3.3. Multiprocessor Communications........................................................... 227
27. Enhanced Serial Peripheral Interface (SPI0) ..................................................... 233
27.1. Signal Descriptions........................................................................................ 234
27.1.1. Master Out, Slave In (MOSI)................................................................. 234
27.1.2. Master In, Slave Out (MISO)................................................................. 234
27.1.3. Serial Clock (SCK) ................................................................................ 234
27.1.4. Slave Select (NSS) ............................................................................... 234
27.2. SPI0 Master Mode Operation........................................................................ 235
27.3. SPI0 Slave Mode Operation.......................................................................... 236
27.4. SPI0 Interrupt Sources .................................................................................. 237
27.5. Serial Clock Phase and Polarity .................................................................... 237
27.6. SPI Special Function Registers..................................................................... 239
6
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
28. Timers ................................................................................................................... 246
28.1. Timer 0 and Timer 1 ...................................................................................... 248
28.1.1. Mode 0: 13-bit Counter/Timer ............................................................... 248
28.1.2. Mode 1: 16-bit Counter/Timer ............................................................... 249
28.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload..................................... 249
28.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................ 250
28.2. Timer 2 .......................................................................................................... 256
28.2.1. 16-bit Timer with Auto-Reload............................................................... 256
28.2.2. 8-bit Timers with Auto-Reload............................................................... 257
28.2.3. Low-Frequency Oscillator (LFO) Capture Mode ................................... 258
28.3. Timer 3 .......................................................................................................... 262
28.3.1. 16-bit Timer with Auto-Reload............................................................... 262
28.3.2. 8-bit Timers with Auto-Reload............................................................... 263
28.3.3. Low-Frequency Oscillator (LFO) Capture Mode ................................... 264
29. Programmable Counter Array............................................................................. 268
29.1. PCA Counter/Timer ....................................................................................... 269
29.2. PCA0 Interrupt Sources................................................................................. 270
29.3. Capture/Compare Modules ........................................................................... 271
29.3.1. Edge-triggered Capture Mode............................................................... 272
29.3.2. Software Timer (Compare) Mode.......................................................... 273
29.3.3. High-Speed Output Mode ..................................................................... 274
29.3.4. Frequency Output Mode ....................................................................... 275
29.3.5. 8-bit, 9-bit, 10-bit and 11-bit Pulse Width Modulator Modes ................. 276
29.3.5.1. 8-bit Pulse Width Modulator Mode................................................ 276
29.3.5.2. 9/10/11-bit Pulse Width Modulator Mode...................................... 277
29.3.6. 16-Bit Pulse Width Modulator Mode...................................................... 278
29.4. Watchdog Timer Mode .................................................................................. 279
29.4.1. Watchdog Timer Operation................................................................... 279
29.4.2. Watchdog Timer Usage ........................................................................ 280
29.5. Register Descriptions for PCA0..................................................................... 281
30. C2 Interface .......................................................................................................... 288
30.1. C2 Interface Registers................................................................................... 288
30.2. C2 Pin Sharing .............................................................................................. 295
Document Change List.............................................................................................. 296
Contact Information................................................................................................... 298
Rev. 1.2
7
C8051T620/1/6/7 & C8051T320/1/2/3
List of Figures
Figure 1.1. C8051T620/1 Block Diagram ................................................................ 16
Figure 1.2. C8051T626/7 Block Diagram ................................................................ 17
Figure 1.3. C8051T320/2 Block Diagram ................................................................ 18
Figure 1.4. C8051T321/3 Block Diagram ................................................................ 19
Figure 1.5. Typical Bus-Powered Connections ....................................................... 20
Figure 3.1. QFN-32 Pinout Diagram (Top View) ..................................................... 25
Figure 3.2. LQFP-32 Pinout Diagram (Top View) .................................................... 26
Figure 3.3. QFN-28 Pinout Diagram (Top View) ..................................................... 27
Figure 4.1. LQFP-32 Package Drawing ................................................................... 28
Figure 4.2. LQFP-32 Recommended PCB Land Pattern ........................................ 29
Figure 5.1. QFN-32 Package Drawing .................................................................... 30
Figure 5.2. QFN-32 Recommended PCB Land Pattern .......................................... 31
Figure 6.1. QFN-28 Package Drawing .................................................................... 32
Figure 6.2. QFN-28 Recommended PCB Land Pattern .......................................... 33
Figure 7.1. Normal Mode Digital Supply Current vs. Frequency (MPCE = 1) ......... 44
Figure 7.2. Idle Mode Digital Supply Current vs. Frequency (MPCE = 1) ............... 44
Figure 8.1. ADC0 Functional Block Diagram ........................................................... 45
Figure 8.2. 10-Bit ADC Track and Conversion Example Timing ............................. 47
Figure 8.3. ADC0 Equivalent Input Circuits ............................................................. 48
Figure 8.4. ADC Window Compare Example: Right-Justified Data ......................... 54
Figure 8.5. ADC Window Compare Example: Left-Justified Data ........................... 54
Figure 8.6. ADC0 Multiplexer Block Diagram .......................................................... 55
Figure 9.1. Temperature Sensor Transfer Function ................................................ 57
Figure 9.2. TOFFH and TOFFL Calibration Value Orientation ................................ 58
Figure 9.3. Temperature Sensor Error with 1-Point Calibration at 0 Celsius ........... 58
Figure 10.1. Voltage Reference Functional Block Diagram ..................................... 59
Figure 11.1. REG0 Configuration: USB Bus-Powered ............................................ 61
Figure 11.2. REG0 Configuration: USB Self-Powered ............................................ 62
Figure 11.3. REG0 Configuration: USB Self-Powered, Regulator Disabled ............ 62
Figure 11.4. REG0 Configuration: No USB Connection .......................................... 63
Figure 12.1. CIP-51 Block Diagram ......................................................................... 66
Figure 14.1. Comparator0 Functional Block Diagram ............................................. 77
Figure 14.2. Comparator1 Functional Block Diagram ............................................. 78
Figure 14.3. Comparator Hysteresis Plot ................................................................ 79
Figure 14.4. Comparator Input Multiplexer Block Diagram ...................................... 84
Figure 15.1. C8051T620/1 and C8051T320/1/2/3 Memory Map ............................. 87
Figure 15.2. C8051T626/7 Memory Map ................................................................. 88
Figure 15.3. Program Memory Map ......................................................................... 89
Figure 15.4. C8051T620/1 and C8051T320/1/2/3 USB FIFO Space and
XRAM Memory Map with USBFAE Set to 1 ....................................................... 92
Figure 15.5. C8051T626/7 USB FIFO Space and XRAM Memory Map
with USBFAE set to 1 ......................................................................................... 93
Figure 20.1. Reset Sources ................................................................................... 121
Rev. 1.2
8
C8051T620/1/6/7 & C8051T320/1/2/3
Figure 20.2. Power-On and VDD Monitor Reset Timing ....................................... 122
Figure 21.1. Oscillator Options .............................................................................. 127
Figure 21.2. External Crystal Example .................................................................. 135
Figure 22.1. Port I/O Functional Block Diagram .................................................... 138
Figure 22.2. Port I/O Cell Block Diagram .............................................................. 139
Figure 22.3. Priority Crossbar Decoder Potential Pin Assignments ...................... 143
Figure 22.4. Priority Crossbar Decoder Example 1—No Skipped Pins ................. 144
Figure 22.5. Priority Crossbar Decoder Example 2—Skipping Pins ...................... 145
Figure 23.1. USB0 Block Diagram ......................................................................... 160
Figure 23.2. USB0 Register Access Scheme ........................................................ 163
Figure 23.3. C8051T620/1 and C8051T320/1/2/3 USB FIFO Allocation ............... 169
Figure 23.4. C8051T626/7 USB FIFO Allocation .................................................. 170
Figure 24.1. SMBus Block Diagram ...................................................................... 194
Figure 24.2. Typical SMBus Configuration ............................................................ 195
Figure 24.3. SMBus Transaction ........................................................................... 196
Figure 24.4. Typical SMBus SCL Generation ........................................................ 198
Figure 24.5. Typical Master Write Sequence ........................................................ 207
Figure 24.6. Typical Master Read Sequence ........................................................ 208
Figure 24.7. Typical Slave Write Sequence .......................................................... 209
Figure 24.8. Typical Slave Read Sequence .......................................................... 210
Figure 25.1. UART0 Block Diagram ...................................................................... 215
Figure 25.2. UART0 Baud Rate Logic ................................................................... 216
Figure 25.3. UART Interconnect Diagram ............................................................. 217
Figure 25.4. 8-Bit UART Timing Diagram .............................................................. 217
Figure 25.5. 9-Bit UART Timing Diagram .............................................................. 218
Figure 25.6. UART Multi-Processor Mode Interconnect Diagram ......................... 219
Figure 26.1. UART1 Block Diagram ...................................................................... 223
Figure 26.2. UART1 Timing Without Parity or Extra Bit ......................................... 225
Figure 26.3. UART1 Timing With Parity ................................................................ 225
Figure 26.4. UART1 Timing With Extra Bit ............................................................ 225
Figure 26.5. Typical UART Interconnect Diagram ................................................. 226
Figure 26.6. UART Multi-Processor Mode Interconnect Diagram ......................... 227
Figure 27.1. SPI Block Diagram ............................................................................ 233
Figure 27.2. Multiple-Master Mode Connection Diagram ...................................... 235
Figure 27.3. 3-Wire Single Master and 3-Wire Single Slave Mode
Connection Diagram ........................................................................................ 235
Figure 27.4. 4-Wire Single Master Mode and 4-Wire Slave Mode
Connection Diagram ........................................................................................ 236
Figure 27.5. Master Mode Data/Clock Timing ....................................................... 238
Figure 27.6. Slave Mode Data/Clock Timing (CKPHA = 0) ................................... 238
Figure 27.7. Slave Mode Data/Clock Timing (CKPHA = 1) ................................... 239
Figure 27.8. SPI Master Timing (CKPHA = 0) ....................................................... 243
Figure 27.9. SPI Master Timing (CKPHA = 1) ....................................................... 243
Figure 27.10. SPI Slave Timing (CKPHA = 0) ....................................................... 244
9
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
Figure 27.11. SPI Slave Timing (CKPHA = 1) ....................................................... 244
Figure 28.1. T0 Mode 0 Block Diagram ................................................................. 249
Figure 28.2. T0 Mode 2 Block Diagram ................................................................. 250
Figure 28.3. T0 Mode 3 Block Diagram ................................................................. 251
Figure 28.4. Timer 2 16-Bit Mode Block Diagram ................................................. 256
Figure 28.5. Timer 2 8-Bit Mode Block Diagram ................................................... 257
Figure 28.6. Timer 2 Low-Frequency Oscillation Capture Mode Block Diagram ... 258
Figure 28.7. Timer 3 16-Bit Mode Block Diagram ................................................. 262
Figure 28.8. Timer 3 8-Bit Mode Block Diagram ................................................... 263
Figure 28.9. Timer 3 Low-Frequency Oscillation Capture Mode Block Diagram ... 264
Figure 29.1. PCA Block Diagram ........................................................................... 268
Figure 29.2. PCA Counter/Timer Block Diagram ................................................... 270
Figure 29.3. PCA Interrupt Block Diagram ............................................................ 271
Figure 29.4. PCA Capture Mode Diagram ............................................................. 273
Figure 29.5. PCA Software Timer Mode Diagram ................................................. 274
Figure 29.6. PCA High-Speed Output Mode Diagram ........................................... 275
Figure 29.7. PCA Frequency Output Mode ........................................................... 276
Figure 29.8. PCA 8-Bit PWM Mode Diagram ........................................................ 277
Figure 29.9. PCA 9, 10 and 11-Bit PWM Mode Diagram ...................................... 278
Figure 29.10. PCA 16-Bit PWM Mode ................................................................... 279
Figure 29.11. PCA Module 2 with Watchdog Timer Enabled ................................ 280
Figure 30.1. Typical C2 Pin Sharing ...................................................................... 295
Rev. 1.2
10
C8051T620/1/6/7 & C8051T320/1/2/3
List of Tables
Table 2.1. Product Selection Guide ......................................................................... 21
Table 3.1. Pin Definitions for the C8051T620/1/6/7 & C8051T320/1/2/3 ................ 22
Table 7.1. Absolute Maximum Ratings .................................................................... 34
Table 7.2. Global Electrical Characteristics ............................................................. 35
Table 7.3. Port I/O DC Electrical Characteristics ..................................................... 36
Table 7.4. Reset Electrical Characteristics .............................................................. 36
Table 7.5. Internal Voltage Regulator Electrical Characteristics ............................. 37
Table 7.6. EPROM Electrical Characteristics .......................................................... 38
Table 7.7. Internal High-Frequency Oscillator Electrical Characteristics ................. 38
Table 7.8. Internal Low-Frequency Oscillator Electrical Characteristics ................. 39
Table 7.9. External Oscillator Electrical Characteristics .......................................... 39
Table 7.10. ADC0 Electrical Characteristics ............................................................ 40
Table 7.11. Temperature Sensor Electrical Characteristics .................................... 41
Table 7.12. Voltage Reference Electrical Characteristics ....................................... 41
Table 7.13. Comparator Electrical Characteristics .................................................. 42
Table 7.14. USB Transceiver Electrical Characteristics .......................................... 43
Table 12.1. CIP-51 Instruction Set Summary .......................................................... 68
Table 16.1. Special Function Register (SFR) Memory Map .................................... 95
Table 16.2. Special Function Registers ................................................................... 96
Table 17.1. Interrupt Summary .............................................................................. 103
Table 18.1. Security Byte Decoding ...................................................................... 114
Table 23.1. Endpoint Addressing Scheme ............................................................ 161
Table 23.2. USB0 Controller Registers ................................................................. 166
Table 23.3. FIFO Configurations ........................................................................... 171
Table 26.1. Baud Rate Generator Settings for Standard Baud Rates ................... 224
Table 29.1. PCA Timebase Input Options ............................................................. 269
Table 29.2. PCA0CPM and PCA0PWM Bit Settings
for PCA Capture/Compare Modules ................................................... 272
Rev. 1.2
11
C8051T620/1/6/7 & C8051T320/1/2/3
List of Registers
SFR Definition 8.1. ADC0CF: ADC0 Configuration ...................................................... 49
SFR Definition 8.2. ADC0H: ADC0 Data Word MSB .................................................... 50
SFR Definition 8.3. ADC0L: ADC0 Data Word LSB ...................................................... 50
SFR Definition 8.4. ADC0CN: ADC0 Control ................................................................ 51
SFR Definition 8.5. ADC0GTH: ADC0 Greater-Than Data High Byte .......................... 52
SFR Definition 8.6. ADC0GTL: ADC0 Greater-Than Data Low Byte ............................ 52
SFR Definition 8.7. ADC0LTH: ADC0 Less-Than Data High Byte ................................ 53
SFR Definition 8.8. ADC0LTL: ADC0 Less-Than Data Low Byte ................................. 53
SFR Definition 8.9. AMX0P: AMUX0 Positive Channel Select ..................................... 56
SFR Definition 10.1. REF0CN: Reference Control ....................................................... 60
SFR Definition 11.1. REG01CN: Voltage Regulator Control ........................................ 65
SFR Definition 12.1. DPL: Data Pointer Low Byte ........................................................ 73
SFR Definition 12.2. DPH: Data Pointer High Byte ....................................................... 73
SFR Definition 12.3. SP: Stack Pointer ......................................................................... 74
SFR Definition 12.4. ACC: Accumulator ....................................................................... 74
SFR Definition 12.5. B: B Register ................................................................................ 74
SFR Definition 12.6. PSW: Program Status Word ........................................................ 75
SFR Definition 13.1. PFE0CN: Prefetch Engine Control .............................................. 76
SFR Definition 14.1. CPT0CN: Comparator0 Control ................................................... 80
SFR Definition 14.2. CPT0MD: Comparator0 Mode Selection ..................................... 81
SFR Definition 14.3. CPT1CN: Comparator1 Control ................................................... 82
SFR Definition 14.4. CPT1MD: Comparator1 Mode Selection ..................................... 83
SFR Definition 14.5. CPT0MX: Comparator0 MUX Selection ...................................... 85
SFR Definition 14.6. CPT1MX: Comparator1 MUX Selection ...................................... 86
SFR Definition 15.1. EMI0CN: External Memory Interface Control .............................. 91
SFR Definition 15.2. EMI0CF: External Memory Configuration .................................... 94
SFR Definition 17.1. IE: Interrupt Enable .................................................................... 104
SFR Definition 17.2. IP: Interrupt Priority .................................................................... 105
SFR Definition 17.3. EIE1: Extended Interrupt Enable 1 ............................................ 106
SFR Definition 17.4. EIP1: Extended Interrupt Priority 1 ............................................ 107
SFR Definition 17.5. EIE2: Extended Interrupt Enable 2 ............................................ 108
SFR Definition 17.6. EIP2: Extended Interrupt Priority 2 ............................................ 109
SFR Definition 17.7. IT01CF: INT0/INT1 ConfigurationO ........................................... 111
SFR Definition 18.1. PSCTL: Program Store R/W Control ......................................... 116
SFR Definition 18.2. MEMKEY: EPROM Memory Lock and Key ............................... 116
SFR Definition 18.3. IAPCN: In-Application Programming Control ............................. 117
SFR Definition 19.1. PCON: Power Control ................................................................ 120
SFR Definition 20.1. VDM0CN: VDD Monitor Control ................................................ 124
SFR Definition 20.2. RSTSRC: Reset Source ............................................................ 126
SFR Definition 21.1. CLKSEL: Clock Select ............................................................... 129
SFR Definition 21.2. OSCICL: Internal H-F Oscillator Calibration .............................. 130
SFR Definition 21.3. OSCICN: Internal H-F Oscillator Control ................................... 131
SFR Definition 21.4. CLKMUL: Clock Multiplier Control ............................................. 132
Rev. 1.2
12
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 21.5. OSCLCN: Internal L-F Oscillator Control ................................... 133
SFR Definition 21.6. OSCXCN: External Oscillator Control ........................................ 137
SFR Definition 22.1. XBR0: Port I/O Crossbar Register 0 .......................................... 147
SFR Definition 22.2. XBR1: Port I/O Crossbar Register 1 .......................................... 148
SFR Definition 22.3. XBR2: Port I/O Crossbar Register 2 .......................................... 149
SFR Definition 22.4. P0MASK: Port 0 Mask Register ................................................. 150
SFR Definition 22.5. P0MAT: Port 0 Match Register .................................................. 150
SFR Definition 22.6. P1MASK: Port 1 Mask Register ................................................. 151
SFR Definition 22.7. P1MAT: Port 1 Match Register .................................................. 151
SFR Definition 22.8. P0: Port 0 ................................................................................... 152
SFR Definition 22.9. P0MDIN: Port 0 Input Mode ....................................................... 153
SFR Definition 22.10. P0MDOUT: Port 0 Output Mode .............................................. 153
SFR Definition 22.11. P0SKIP: Port 0 Skip ................................................................. 154
SFR Definition 22.12. P1: Port 1 ................................................................................. 154
SFR Definition 22.13. P1MDIN: Port 1 Input Mode ..................................................... 155
SFR Definition 22.14. P1MDOUT: Port 1 Output Mode .............................................. 155
SFR Definition 22.15. P1SKIP: Port 1 Skip ................................................................. 156
SFR Definition 22.16. P2: Port 2 ................................................................................. 156
SFR Definition 22.17. P2MDIN: Port 2 Input Mode ..................................................... 157
SFR Definition 22.18. P2MDOUT: Port 2 Output Mode .............................................. 157
SFR Definition 22.19. P2SKIP: Port 2 Skip ................................................................. 158
SFR Definition 22.20. P3: Port 3 ................................................................................. 158
SFR Definition 22.21. P3MDOUT: Port 3 Output Mode .............................................. 159
SFR Definition 23.1. USB0XCN: USB0 Transceiver Control ...................................... 162
SFR Definition 23.2. USB0ADR: USB0 Indirect Address ........................................... 164
SFR Definition 23.3. USB0DAT: USB0 Data .............................................................. 165
SFR Definition 24.1. SMB0CF: SMBus Clock/Configuration ...................................... 200
SFR Definition 24.2. SMB0CN: SMBus Control .......................................................... 202
SFR Definition 24.3. SMB0ADR: SMBus Slave Address ............................................ 204
SFR Definition 24.4. SMB0ADM: SMBus Slave Address Mask .................................. 205
SFR Definition 24.5. SMB0DAT: SMBus Data ............................................................ 206
SFR Definition 25.1. SCON0: Serial Port 0 Control .................................................... 220
SFR Definition 25.2. SBUF0: Serial (UART0) Port Data Buffer .................................. 221
SFR Definition 26.1. SCON1: UART1 Control ............................................................ 228
SFR Definition 26.2. SMOD1: UART1 Mode .............................................................. 229
SFR Definition 26.3. SBUF1: UART1 Data Buffer ...................................................... 230
SFR Definition 26.4. SBCON1: UART1 Baud Rate Generator Control ...................... 231
SFR Definition 26.5. SBRLH1: UART1 Baud Rate Generator High Byte ................... 231
SFR Definition 26.6. SBRLL1: UART1 Baud Rate Generator Low Byte ..................... 232
SFR Definition 27.1. SPI0CFG: SPI0 Configuration ................................................... 240
SFR Definition 27.2. SPI0CN: SPI0 Control ............................................................... 241
SFR Definition 27.3. SPI0CKR: SPI0 Clock Rate ....................................................... 242
SFR Definition 27.4. SPI0DAT: SPI0 Data ................................................................. 242
SFR Definition 28.1. CKCON: Clock Control .............................................................. 247
13
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 28.2. TCON: Timer Control ................................................................. 252
SFR Definition 28.3. TMOD: Timer Mode ................................................................... 253
SFR Definition 28.4. TL0: Timer 0 Low Byte ............................................................... 254
SFR Definition 28.5. TL1: Timer 1 Low Byte ............................................................... 254
SFR Definition 28.6. TH0: Timer 0 High Byte ............................................................. 255
SFR Definition 28.7. TH1: Timer 1 High Byte ............................................................. 255
SFR Definition 28.8. TMR2CN: Timer 2 Control ......................................................... 259
SFR Definition 28.9. TMR2RLL: Timer 2 Reload Register Low Byte .......................... 260
SFR Definition 28.10. TMR2RLH: Timer 2 Reload Register High Byte ...................... 260
SFR Definition 28.11. TMR2L: Timer 2 Low Byte ....................................................... 260
SFR Definition 28.12. TMR2H Timer 2 High Byte ....................................................... 261
SFR Definition 28.13. TMR3CN: Timer 3 Control ....................................................... 265
SFR Definition 28.14. TMR3RLL: Timer 3 Reload Register Low Byte ........................ 266
SFR Definition 28.15. TMR3RLH: Timer 3 Reload Register High Byte ...................... 266
SFR Definition 28.16. TMR3L: Timer 3 Low Byte ....................................................... 266
SFR Definition 28.17. TMR3H Timer 3 High Byte ....................................................... 267
SFR Definition 29.1. PCA0CN: PCA Control .............................................................. 282
SFR Definition 29.2. PCA0MD: PCA Mode ................................................................ 283
SFR Definition 29.3. PCA0PWM: PCA PWM Configuration ....................................... 284
SFR Definition 29.4. PCA0CPMn: PCA Capture/Compare Mode .............................. 285
SFR Definition 29.5. PCA0L: PCA Counter/Timer Low Byte ...................................... 286
SFR Definition 29.6. PCA0H: PCA Counter/Timer High Byte ..................................... 286
SFR Definition 29.7. PCA0CPLn: PCA Capture Module Low Byte ............................. 287
SFR Definition 29.8. PCA0CPHn: PCA Capture Module High Byte ........................... 287
Rev. 1.2
14
C8051T620/1/6/7 & C8051T320/1/2/3
1. System Overview
C8051T620/1/6/7 & C8051T320/1/2/3 devices are fully integrated mixed-signal System-on-a-Chip MCUs.
Highlighted features are listed below. Refer to Table 2.1 for specific product feature selection and part
ordering numbers.
High-speed pipelined 8051-compatible microcontroller core (up to 48 MIPS)
In-system, full-speed, non-intrusive debug interface (on-chip)
C8051F34A ISP Flash device is available for quick in-system code development
Universal Serial Bus (USB) Function Controller with eight flexible endpoint pipes, integrated
transceiver, and 1 kB FIFO RAM
Supply Voltage Regulator
10-bit 500 ksps Single-ended ADC with analog multiplexer and integrated temperature sensor
Precision calibrated 48 MHz internal oscillator
Internal low-frequency oscillator for additional power savings
64, 32, or 16 kB of on-chip byte-programmable EPROM—(512 bytes are reserved)
1280 or 3328 bytes of on-chip RAM (256 + 1 kB or 3 kB)
SMBus/I2C, 2 UARTs, and Enhanced SPI serial interfaces implemented in hardware
Four general-purpose 16-bit timers
Programmable Counter/Timer Array (PCA) with five capture/compare modules and Watchdog Timer
function
On-chip Power-On Reset, V Monitor, and Temperature Sensor
DD
On-chip Voltage Comparators (2)
Up to 25 Port I/O
With on-chip Power-On Reset, V monitor, Watchdog Timer, and clock oscillator, the C8051T620/1/6/7 &
DD
C8051T320/1/2/3 devices are truly stand-alone System-on-a-Chip solutions. User software has complete
control of all peripherals, and may individually shut down any or all peripherals for power savings.
Code written for the C8051T620/1/6/7 & C8051T320/1/2/3 family of processors will run on the C8051F34A
Mixed-signal ISP Flash microcontroller, providing a quick, cost-effective way to develop code without
requiring special emulator circuitry. The C8051T620/1/6/7 & C8051T320/1/2/3 processors include Silicon
Laboratories’ 2-Wire C2 Debug and Programming interface, which allows non-intrusive (uses no on-chip
resources), full speed, in-circuit debugging using the production MCU installed in the final application. This
debug logic supports inspection of memory, viewing and modification of special function registers, setting
breakpoints, single stepping, run and halt commands. All analog and digital peripherals are fully functional
while debugging using C2. The two C2 interface pins can be shared with user functions, allowing in-system
debugging without occupying package pins.
Each device is specified for 1.8-to-5.25 V operation over the industrial temperature range (–40 to +85 °C).
For voltages above 3.6 V, the on-chip Voltage Regulator must be used. A minimum of 3.0 V is required for
USB communication. An additional internal LDO is used to supply the processor core voltage at 1.8 V. The
Port I/O and RST pins are tolerant of input signals up to 5 V. The C8051T620/1/6/7 are available in 32-pin
QFN packaging, the C8051T320/2 are available in 32-pin LQFP packaging, and the C8051T321/3 are
available in 28-pin QFN packaging. See Table 2.1 for ordering information. A block diagram is shown in
Figure 1.1.
Rev. 1.2
15
C8051T620/1/6/7 & C8051T320/1/2/3
VIO
Port I/O Configuration
Power On
Reset
CIP-51 8051
Controller Core
P0.0
P0.1
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7/VREF
Digital Peripherals
Reset
16k Byte OTP
Program Memory
UART0
Port 0
Drivers
Debug /
Programming
Hardware
C2CK/RST
UART1
256 Byte SRAM
1024 Byte XRAM
Timers 0,
Priority
Crossbar
Decoder
1, 2, 3
C2D
P1.0
P1.1
P1.2
In-system
Programming
Hardware
PCA/
WDT
SMBus
SPI
P1.3
P1.4
P1.5/VPP
P1.6
P1.7
Port 1
Drivers
VPP
Peripheral Power
Voltage
Regulator
REGIN
Crossbar Control
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
VDD
GND
Regulator
Core Power
SFR
Bus
Port 2
Drivers
System Clock Setup
Analog Peripherals
(C8051T620)
XTAL1
XTAL2
External Oscillator
P3.0/C2D
Port 3
Drivers
Voltage
Reference
Internal Oscillator
VREF
VDD
VREF
Clock
Recovery
Low Freq.
Oscillator
VDD
VREF
A
M
U
X
10-bit
500ksps
ADC
Temp
Sensor
USB Peripheral
GND
D+
D-
Controller
Full / Low
Speed
Transceiver
CP0, CP0A
CP1, CP1A
+
-
1k Byte
RAM
+
-
VBUS
2 Comparators
Figure 1.1. C8051T620/1 Block Diagram
16
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
VIO
Port I/O Configuration
Power On
Reset
CIP-51 8051
Controller Core
P0.0
P0.1
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7/VREF
Digital Peripherals
Reset
64/32k Byte OTP
Program Memory
UART0
Port 0
Drivers
Debug /
Programming
Hardware
C2CK/RST
UART1
256 Byte SRAM
3072 Byte XRAM
Timers 0,
Priority
Crossbar
Decoder
1, 2, 3
C2D
P1.0
P1.1
P1.2
In-system
Programming
Hardware
PCA/
WDT
SMBus
SPI
P1.3
P1.4
P1.5/VPP
P1.6
P1.7
Port 1
Drivers
VPP
Peripheral Power
Voltage
Regulator
REGIN
Crossbar Control
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
VDD
GND
Regulator
Core Power
SFR
Bus
Port 2
Drivers
System Clock Setup
Analog Peripherals
XTAL1
XTAL2
External Oscillator
P3.0/C2D
Port 3
Drivers
Voltage
Reference
Internal Oscillator
VREF
VDD
VREF
Clock
Recovery
Low Freq.
Oscillator
VDD
VREF
A
M
U
X
10-bit
500ksps
ADC
Temp
Sensor
USB Peripheral
GND
D+
D-
Controller
Full / Low
Speed
Transceiver
CP0, CP0A
CP1, CP1A
+
-
1k Byte
RAM
+
-
VBUS
2 Comparators
Figure 1.2. C8051T626/7 Block Diagram
Rev. 1.2
17
C8051T620/1/6/7 & C8051T320/1/2/3
Port I/O Configuration
Power On
Reset
CIP-51 8051
Controller Core
P0.0
P0.1
Digital Peripherals
Reset
16k Byte OTP
Program Memory
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
UART0
Port 0
Drivers
Debug /
Programming
Hardware
C2CK/RST
UART1
P0.5/RX
P0.6/CNVSTR
P0.7/VREF
256 Byte SRAM
1024 Byte XRAM
Timers 0,
Priority
Crossbar
Decoder
1, 2, 3
C2D
P1.0
P1.1
P1.2
In-system
Programming
Hardware
PCA/
WDT
SMBus
SPI
P1.3
P1.4
P1.5/VPP
P1.6
P1.7
Port 1
Drivers
VPP
Peripheral Power
Voltage
Regulator
REGIN
Crossbar Control
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
VDD
GND
Regulator
Core Power
SFR
Bus
Port 2
Drivers
System Clock Setup
Analog Peripherals
(C8051T320)
XTAL1
XTAL2
External Oscillator
P3.0/C2D
Port 3
Drivers
Voltage
Reference
Internal Oscillator
VREF
VDD
VREF
Clock
Recovery
Low Freq.
Oscillator
VDD
VREF
A
M
U
X
10-bit
500ksps
ADC
Temp
Sensor
USB Peripheral
GND
D+
D-
Controller
Full / Low
Speed
Transceiver
CP0, CP0A
CP1, CP1A
+
-
1k Byte
RAM
+
-
VBUS
2 Comparators
Figure 1.3. C8051T320/2 Block Diagram
18
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
Port I/O Configuration
Power On
Reset
CIP-51 8051
Controller Core
P0.0
P0.1
Digital Peripherals
Reset
16k Byte OTP
Program Memory
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
UART0
Port 0
Drivers
Debug /
Programming
Hardware
C2CK/RST
UART1
P0.5/RX
P0.6/CNVSTR
P0.7/VREF
256 Byte SRAM
1024 Byte XRAM
Timers 0,
Priority
Crossbar
Decoder
1, 2, 3
C2D
P1.0
P1.1
P1.2
In-system
Programming
Hardware
PCA/
WDT
SMBus
SPI
P1.3
P1.4
P1.5/VPP
P1.6
P1.7
Port 1
Drivers
VPP
Peripheral Power
Voltage
Regulator
REGIN
Crossbar Control
P2.0
P2.1
P2.2
P2.3
VDD
GND
Regulator
Core Power
Port 2
Drivers
SFR
Bus
P3.0/C2D
Port 3
Drivers
System Clock Setup
Analog Peripherals
(C8051T321)
XTAL1
XTAL2
External Oscillator
Voltage
Reference
Internal Oscillator
VREF
VDD
VREF
Clock
Recovery
Low Freq.
Oscillator
VDD
VREF
A
M
U
X
10-bit
500ksps
ADC
Temp
Sensor
USB Peripheral
GND
D+
D-
Controller
Full / Low
Speed
Transceiver
CP0, CP0A
CP1, CP1A
+
-
1k Byte
RAM
+
-
VBUS
2 Comparators
Figure 1.4. C8051T321/3 Block Diagram
Rev. 1.2
19
C8051T620/1/6/7 & C8051T320/1/2/3
1.8V to VDD
VIO*
VIO*
VIO can be connected directly
to VDD.
SUPPLY NET
VDD
Add decoupling/bypass
capacitors close to each
voltage supply pin.
4.7µF 0.1µF
RESET SIGNAL
1-5
kohm
A 1-5 kohm pull-up resistor can
RST/
C2CK
be connected to VIO* for added
noise immunity.
VREGIN
VBUS
C2CK
C2D
DEBUG SIGNALS
C2D
USB
Connections needed for
optional debug interface
GND
GND
1µF
Add ESD protection
diodes designed for
use with USB, such
as Littlefuse
SP0503BAHT or
equivalent.
GPIO
D-
D+
Unused port pins should be left
floating, configured to push-pull
output, and driven high.
Keep the USB shield ground
isolated from the device ground.
GND
*Note : VIO only appears on certain package options. If VIO is not present, the RST pullup can connect to VDD.
Figure 1.5. Typical Bus-Powered Connections
20
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
2. Ordering Information
Table 2.1. Product Selection Guide
1
C8051T620-GM
C8051T621-GM
48 16k 1280 Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
2
2
2
2
2
2
2
2
4
4
4
4
4
4
4
4
Y 24 Y
Y
Y
2
2
2
2
2
2
2
2
Y
Y
Y
Y
QFN32
QFN32
QFN32
QFN32
1
48 16k 1280 Y
Y 24 — — —
5
1
C8051T626-B-GM 48 64k 3328 Y
Y 24 Y
Y 24 Y
Y 25 Y
Y 21 Y
Y
Y
Y
Y
Y
Y
Y
Y
5
C8051T627-B-GM 48 32k 3328 Y
2
1
C8051T320-GQ
C8051T321-GM
48 16k 1280 Y
Y LQFP32
QFN28
Y LQFP32
QFN28
3
1
48 16k 1280 Y
Y
2
1
C8051T322-GQ
C8051T323-GM
Notes:
48 16k 1280 Y
Y 25 — — —
Y 21 — — —
3
1
48 16k 1280 Y
Y
1. 512 Bytes Reserved for Factory use.
2. Pin compatible with the C8051F320-GQ.
3. Pin compatible with the C8051F321-GM.
4. Lead plating material is 100% Matte Tin (Sn).
5. These ordering part numbers use a newer format that includes the silicon revision. For example, C8051T626-B-
GM indicates silicon revision “B”.
Rev. 1.2
21
C8051T620/1/6/7 & C8051T320/1/2/3
3. Pin Definitions
Table 3.1. Pin Definitions for the C8051T620/1/6/7 & C8051T320/1/2/3
Pin Number
Name
Type Description
‘T62x ‘T320/2 ‘T321/3
V
7
3
6
3
9
6
3
9
Power Supply Voltage.
DD
GND
RST/
Ground.
10
D I/O Device Reset. Open-drain output of internal POR or
V
monitor. An external source can initiate a system
DD
reset by driving this pin low for at least 10 µs.
Clock signal for the C2 Debug Interface.
C2CK
P3.0/
D I/O
11
8
10
7
10
7
D I/O Port 3.0.
C2D
D I/O Bi-directional data signal for the C2 Debug Interface.
REGIN
5 V Regulator Input. This pin is the input to the on-chip
voltage
regulator.
VBUS
9
8
8
D In
VBUS Sense Input. This pin should be connected to the
VBUS signal of a USB network. A 5 V signal on this pin
indicates
a USB network connection.
D+
D-
4
5
6
4
5
-
4
5
-
D I/O USB D+.
D I/O USB D–.
V
V I/O Supply Voltage Input. The voltage at this pin must
be less than or equal to the Core Supply Voltage (V ).
IO
DD
P0.0
P0.1
P0.2
2
1
2
1
2
1
D I/O or Port 0.0.
A In
D I/O or Port 0.1.
A In
32
32
28
D I/O or Port 0.2.
A In
XTAL1
A In
External Clock Input. This pin is the external oscillator
return for a crystal or resonator. See Oscillator Section.
Rev. 1.2
22
C8051T620/1/6/7 & C8051T320/1/2/3
Table 3.1. Pin Definitions for the C8051T620/1/6/7 & C8051T320/1/2/3(Continued)
Pin Number
Name
Type Description
‘T62x ‘T320/2 ‘T321/3
P0.3/
31
31
27
D I/O or Port 0.3.
A In
XTAL2
A Out External Clock Output. This pin is the excitation driver
for an external crystal or resonator.
External Clock Input. This pin is the external clock input
in external CMOS clock mode.
D In
External Clock Input. This pin is the external clock input
in capacitor or RC oscillator configurations.
See Oscillator Section for complete details.
A In
P0.4
P0.5
P0.6/
30
29
28
30
29
28
26
25
24
D I/O or Port 0.4.
A In
D I/O or Port 0.5.
A In
D I/O or Port 0.6.
A In
CNVSTR
P0.7/
D In
ADC0 External Convert Start or IDA0 Update Source
Input.
27
27
23
D I/O or Port 0.7
A In
VREF
P1.0
A I/O ADC Voltage Reference
26
25
24
23
22
26
25
24
23
22
22
21
20
19
18
D I/O or Port 1.0.
A In
P1.1
P1.2
P1.3
P1.4
D I/O or Port 1.1.
A In
D I/O or Port 1.2.
A In
D I/O or Port 1.3.
A In
D I/O or Port 1.4.
A In
23
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
Table 3.1. Pin Definitions for the C8051T620/1/6/7 & C8051T320/1/2/3(Continued)
Pin Number
Name
Type Description
‘T62x ‘T320/2 ‘T321/3
P1.5/
21
21
17
D I/O or Port 1.5.
A In
V
A In
V
Programming Supply Voltage
PP
PP
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
20
19
18
17
16
15
14
13
12
-
20
19
18
17
16
15
14
13
12
11
16
15
14
13
12
11
-
D I/O or Port 1.6.
A In
D I/O or Port 1.7.
A In
D I/O or Port 2.0.
A In
D I/O or Port 2.1.
A In
D I/O or Port 2.2.
A In
D I/O or Port 2.3.
A In
D I/O or Port 2.4.
A In
-
D I/O or Port 2.5.
A In
-
D I/O or Port 2.6.
A In
-
D I/O or Port 2.7.
A In
Rev. 1.2
24
C8051T620/1/6/7 & C8051T320/1/2/3
P0.1
P0.0
GND
D+
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
P1.2
P1.3
P1.4
P1.5 / VPP
P1.6
C8051T620/1/6/7-GM
Top View
D-
VIO
P1.7
VDD
REGIN
P2.0
GND (optional)
P2.1
Figure 3.1. QFN-32 Pinout Diagram (Top View)
25
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
P1.2
1
2
3
4
5
6
7
8
24
P0.1
P0.0
GND
D+
23 P1.3
P1.4
22
P1.5 / VPP
P1.6
21
20
C8051T320/2-GQ
Top View
D-
VDD
REGIN
VBUS
19 P1.7
P2.0
17 P2.1
18
Figure 3.2. LQFP-32 Pinout Diagram (Top View)
Rev. 1.2
26
C8051T620/1/6/7 & C8051T320/1/2/3
P0.1
P0.0
GND
D+
1
2
3
4
5
6
7
21
20
19
18
17
16
15
P1.1
P1.2
P1.3
C8051T321/3-GM
Top View
P1.4
D-
P1.5 / VPP
P1.6
VDD
REGIN
GND (optional)
P1.7
Figure 3.3. QFN-28 Pinout Diagram (Top View)
27
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
4. LQFP-32 Package Specifications
Figure 4.1. LQFP-32 Package Drawing
Table 4.1. LQFP-32 Package Dimensions
Dimension
Min
Typ
Max
Dimension
Min
Typ
Max
A
—
—
—
1.60
0.15
1.45
0.45
0.20
E
E1
L
9.00 BSC.
7.00 BSC.
0.60
A1
0.05
1.35
0.30
0.09
A2
1.40
0.45
0.75
b
0.37
aaa
bbb
ccc
ddd
θ
0.20
c
D
—
0.20
9.00 BSC.
7.00 BSC.
0.80 BSC.
0.10
D1
0.20
e
0°
3.5°
7°
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MS-026, variation BBA.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small
Body Components.
Rev. 1.2
28
C8051T620/1/6/7 & C8051T320/1/2/3
Figure 4.2. LQFP-32 Recommended PCB Land Pattern
Table 4.2. LQFP-32 PCB Land Pattern Dimensions
Dimension
Min
Max
Dimension
Min
Max
C1
C2
E
8.40
8.40
8.50
8.50
X1
Y1
0.40
1.25
0.50
1.35
0.80
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60 μm minimum, all the way around the pad.
Stencil Design
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used
to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all pads.
Card Assembly
7. A No-Clean, Type-3 solder paste is recommended.
8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small
Body Components.
29
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
5. QFN-32 Package Specifications
Figure 5.1. QFN-32 Package Drawing
Table 5.1. QFN-32 Package Dimensions
Dimension
Min
Typ
Max
Dimension
Min
Typ
Max
A
0.80
0.00
0.18
0.90
0.02
1.00
0.05
0.30
E2
L
3.20
0.30
0.00
3.30
0.40
—
3.40
0.50
0.15
A1
b
0.25
L1
D
5.00 BSC.
3.30
aaa
bbb
ddd
eee
0.15
0.10
0.05
0.08
D2
3.20
3.40
e
E
0.50 BSC.
5.00 BSC.
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220, variation VHHD except for
custom features D2, E2, and L which are toleranced per supplier designation.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
Rev. 1.2
30
C8051T620/1/6/7 & C8051T320/1/2/3
Figure 5.2. QFN-32 Recommended PCB Land Pattern
Table 5.2. QFN-32 PCB Land Pattern Dimensions
Dimension
Min
Max
Dimension
Min
Max
C1
C2
E
4.80
4.80
4.90
4.90
X2
Y1
Y2
3.20
0.75
3.20
3.40
0.85
3.40
0.50 BSC
0.30
X1
0.20
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60 μm minimum, all the way around the pad.
Stencil Design
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used
to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.
7. A 3x3 array of 1.0 mm openings on a 1.2 mm pitch should be used for the center pad to
assure the proper paste volume.
Card Assembly
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for
Small Body Components.
31
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
6. QFN-28 Package Specifications
Figure 6.1. QFN-28 Package Drawing
Table 6.1. QFN-28 Package Dimensions
Dimension
Min
Typ
Max
Dimension
Min
Typ
Max
A
0.80
0.00
0.90
0.02
1.00
0.05
L
0.35
0.00
0.55
—
0.65
0.15
A1
L1
A3
0.25 REF
0.23
aaa
bbb
ddd
eee
Z
0.15
0.10
0.05
0.08
0.44
0.18
b
0.18
2.90
0.30
3.35
D
D2
5.00 BSC.
3.15
e
0.50 BSC.
5.00 BSC.
3.15
E
Y
E2
2.90
3.35
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220, variation VHHD except for
custom features D2, E2, Z, Y, and L which are toleranced per supplier designation.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
Rev. 1.2
32
C8051T620/1/6/7 & C8051T320/1/2/3
Figure 6.2. QFN-28 Recommended PCB Land Pattern
Table 6.2. QFN-28 PCB Land Pattern Dimensions
Dimension
Min
Max
Dimension
Min
Max
C1
C2
E
4.80
4.80
0.50
X2
Y1
Y2
3.20
0.85
3.20
3.30
0.95
3.30
X1
0.20
0.30
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design
4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60 μm minimum, all the way around the pad.
Stencil Design
5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used
to assure good solder paste release.
6. The stencil thickness should be 0.125 mm (5 mils).
7. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.
8. A 3x3 array of 0.90mm openings on a 1.1 mm pitch should be used for the center pad to
assure the proper paste volume (67% Paste Coverage).
Card Assembly
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small
Body Components.
33
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
7. Electrical Characteristics
7.1. Absolute Maximum Specifications
Table 7.1. Absolute Maximum Ratings
Parameters
Test Condition
Min
Typ
Max
Unit
Ambient temperature under bias
Storage Temperature
–55
–65
—
—
125
150
5.8
°C
°C
Voltage on RST or any Port I/O
V
V
> 2.2 V
< 2.2 V
–0.3
–0.3
—
—
V
V
DD
DD
Pin (except V during program-
V
+ 3.6
PP
DD
ming) with respect to GND
Voltage on V with respect to
GND during a programming oper-
ation
V
> 2.4 V
–0.3
—
7.0
10
V
s
PP
DD
Duration of High-voltage on VPP
pin (cumulative)
V
> 3.6 V and In-Applica-
PP
tion Programming enabled
or a non-zero value written
to EPCTL
Voltage on V with respect to
GND
Regulator1 in Normal Mode
Regulator1 in Bypass Mode
–0.3
–0.3
—
—
4.2
1.98
V
V
DD
Maximum Total current through
—
—
500
mA
V
, V , REGIN, or GND
DD
IO
Maximum output current sunk by
RST or any Port pin
—
—
100
mA
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the devices at those or any other conditions above
those indicated in the operation listings of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
Rev. 1.2
34
C8051T620/1/6/7 & C8051T320/1/2/3
7.2. Electrical Characteristics
Table 7.2. Global Electrical Characteristics
–40 to +85 °C, 25 MHz system clock unless otherwise specified.
Parameters
Test Condition
Min
Typ
Max
Unit
Supply Voltage (Note 1)
Regulator1 in Normal Mode
Regulator1 in Bypass Mode
1.8
1.75
3.0
—
3.6
1.9
V
V
Digital Supply Current with CPU
Active
V
DD = 1.8 V, Clock = 48 MHz
—
—
9.4
1.6
11.4
—
mA
mA
VDD = 1.8 V, Clock = 1 MHz
VDD = 3.3 V, Clock = 48 MHz
VDD = 3.3 V, Clock = 1 MHz
—
—
11.0
1.7
13.7
—
mA
mA
VDD = 3.6 V, Clock = 48 MHz
VDD = 3.6 V, Clock = 1 MHz
—
—
11.1
1.8
13.8
—
mA
mA
Digital Supply Current with CPU
Inactive (not accessing EPROM)
VDD = 1.8 V, Clock = 48 MHz
VDD = 1.8 V, Clock = 1 MHz
—
—
4.6
0.4
5.5
—
mA
mA
VDD = 3.3 V, Clock = 48 MHz
VDD = 3.3 V, Clock = 1 MHz
—
—
5.1
0.45
5.9
—
mA
mA
VDD = 3.6 V, Clock = 48 MHz
VDD = 3.6 V, Clock = 1 MHz
—
—
5.1
0.5
6.0
—
mA
mA
Digital Supply Current
(shutdown)
Oscillator not running (stop mode), Inter-
nal Regulator Off
—
—
.1
—
µA
Oscillator not running (stop or suspend
mode), Internal Regulator On
375
—
µA
Digital Supply Current for USB
Module (USB Active Mode)
VDD = 3.6 V, USB Clock = 48 MHz
VDD = 3.3 V, USB Clock = 48 MHz
—
—
11.8
11.4
—
—
mA
mA
Digital Supply Current for USB
Module (USB Suspend Mode)
Oscillator not running; VDD monitor dis-
abled.
C8051T620/1/T320/1/2/3
C8051T626/7
—
—
60
90
—
—
µA
µA
Digital Supply RAM Data Reten-
tion Voltage
—
1.5
—
V
Specified Operating
Temperature Range
–40
—
+85
°C
SYSCLK (System Clock) (Note 2)
Tsysl (SYSCLK low time)
Tsysh (SYSCLK high time)
Notes:
0
—
—
—
48
—
—
MHz
ns
9.75
9.75
ns
1. Analog performance is not guaranteed when V
is below 1.8 V.
DD
2. SYSCLK must be at least 32 kHz to enable debugging.
35
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
Table 7.3. Port I/O DC Electrical Characteristics
VDD = 1.8 to 3.6 V, VIO < VDD, –40 to +85 °C unless otherwise specified.
Parameters
Test Condition
Min
Typ
Max
Unit
Output High Voltage
I
I
I
I
I
I
= –10 µA, Port I/O push-pull
= –3 mA, Port I/O push-pull
= –10 mA, Port I/O push-pull
= 10 µA
= 8.5 mA
= 25 mA
V
V
– 0.1
– 0.2
—
—
—
—
—
—
—
—
—
0.1
0.4
—
V
OH
OH
OH
OL
OL
OL
IO
IO
V
– 0.4
IO
Output Low Voltage
—
—
0.6
—
—
—
V
Input High Voltage
Input Low Voltage
Input Leakage
Current
0.7 x V
—
—
V
V
µA
µA
IO
0.6
+1
50
Weak Pullup Off
Weak Pullup On, V = 0 V
–1
—
25
IN
Table 7.4. Reset Electrical Characteristics
–40 to +85 °C unless otherwise specified.
Parameters
Test Condition
= 8.5 mA,
Min
Typ
Max
Unit
RST Output Low Voltage
I
—
—
0.6
V
OL
V
= 1.8 V to 3.6 V
DD
RST Input High Voltage
RST Input Low Voltage
RST Input Pullup Current
0.75 x V
—
—
—
—
0.6
50
V
V
IO
RST = 0.0 V
—
25
µA
V
V
POR Threshold (V
)
1.7
1.75
625
1.8
750
DD
RST
Missing Clock Detector Time- Time from last system clock
500
µs
out
rising edge to reset initiation
Reset Time Delay
Delay between release of any
reset source and code
execution at location 0x0000
—
—
—
60
—
µs
µs
Minimum RST Low Time to
Generate a System Reset
15
V
V
Monitor Turn-on Time
Monitor Supply Current
V
= V – 0.1 v
RST
—
—
50
20
—
µs
DD
DD
DD
30
µA
Rev. 1.2
36
C8051T620/1/6/7 & C8051T320/1/2/3
Table 7.5. Internal Voltage Regulator Electrical Characteristics
–40 to +85 °C unless otherwise specified.
Parameters
Test Condition
Min
Typ
Max
Unit
Voltage Regulator (REG0)
1, 3
Input Voltage Range
2.7
3.3
—
—
3.45
—
5.25
3.6
100
—
V
V
2
Output Voltage (V
)
Output Current = 1 to 100 mA
DD
2
Output Current
mA
V
VBUS Detection Input
Threshold
2.5
—
Bias Current
Normal Mode (REG0MD = 0)
Low Power Mode (REG0MD = 1)
—
—
83
38
98
52
µA
3
Dropout Voltage (V
)
I
I
= 1 mA
= 100 mA
—
—
1
100
—
—
mV/mA
mV/mA
DO
DD
DD
Voltage Regulator (REG1)
Input Voltage Range
Bias Current
1.8
—
—
3.6
V
Normal Mode (REG1MD = 0)
320
425
µA
Low Power Mode (REG1MD = 1)
C8051T626/7/T320/1/2/3
C8051T626/7
—
—
175
200
µA
µA
Notes:
1. Input range specified for regulation. When an external regulator is used, should be tied to V
.
DD
2. Output current is total regulator output, including any current required by the C8051T620/1/6/7 &
C8051T320/1/2/3.
3. The minimum input voltage is 2.7 V or V
+ V
(max load), whichever is greater.
DO
DD
37
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
Table 7.6. EPROM Electrical Characteristics
Parameters
Test Condition
Min
Typ
Max
Unit
EPROM Size (Note 1)
C8051T620/1 & C8051T320/1/2/3
C8051T626
16384
65535
32768
105
—
—
—
—
bytes
bytes
bytes
µs
C8051T627
—
—
Write Cycle Time (per
Byte)
155
205
(Note 2)
In-Application Program-
ming Write Cycle Time
(per Byte)
Capacitor on V = 4.7 µF and fully
discharged
—
—
37
26
—
—
ms
ms
V
PP
Capacitor on V = 4.7 µF and ini-
PP
(Note 3)
tially charged to 3.3 V
Programming Voltage
5.75
—
6.0
4.7
6.25
—
(V
)
PP
Capacitor on V for In-
µF
PP
application Programming
Notes:
1. 512 bytes at location 0x3E00 to 0x3FFF are not available for program storage on the 16k devices, and 512
bytes at location 0xFE00 to 0xFFFF are not available for program storage on the C8051T626.
2. For devices with a Date Code prior to 1040, the programming time over the C2 interface is twice as long. See
Section 18.1.1 for more information.
3. Duration of write time is largely dependent on VIO voltage, supply voltage, and residual charge on the VPP
capacitor. The majority of the write time consists of charging the voltage on VPP to 6.0 V. These
measurements include the VPP ramp time and VDD = VIO = 3.3 V
Table 7.7. Internal High-Frequency Oscillator Electrical Characteristics
VDD = 2.7 to 3.6 V; TA = –40 to +85 °C unless otherwise specified; Using factory-calibrated settings.
Parameters
Test Condition
IFCN = 11b
Min
Typ
Max
Unit
Oscillator Frequency
47.28
48
48.72
MHz
Oscillator Supply Current
25 °C, V = 3.0 V,
DD
(from V
)
OSCICN.7 = 1,
DD
OSCICN.5 = 0
C8051T626/7/T320/1/2/3
C8051T626/7
Constant Temperature
Constant Supply
—
—
—
—
900
925
±0.02
±20
1000
1100
—
µA
µA
%/V
Power Supply Sensitivity
Temperature Sensitivity
—
ppm/°C
Note: Represents mean ±1 standard deviation.
Rev. 1.2
38
C8051T620/1/6/7 & C8051T320/1/2/3
Table 7.8. Internal Low-Frequency Oscillator Electrical Characteristics
VDD = 2.7 to 3.6 V; TA = –40 to +85 °C unless otherwise specified; Using factory-calibrated settings.
Parameters
Test Condition
OSCLD = 11b
Min
Typ
Max
Unit
Oscillator Frequency
72
80
88
kHz
Oscillator Supply Current
25 °C, V = 3.0 V,
DD
(from V
)
OSCLCN.7 = 1
DD
C8051T626/7/T320/1/2/3
C8051T626/7
Constant Temperature
Constant Supply
—
—
—
—
3
4
6
7
—
—
µA
µA
%/V
Power Supply Sensitivity
Temperature Sensitivity
±0.09
±30
ppm/°C
Note: Represents mean ±1 standard deviation.
Table 7.9. External Oscillator Electrical Characteristics
VDD = 2.7 to 3.6 V; TA = –40 to +85 °C unless otherwise specified.
Parameters
Test Condition
Min
Typ
Max
Unit
External Crystal Frequency
External CMOS Oscillator Fre-
quency
.02
0
—
—
30
48
MHz
MHz
39
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
Table 7.10. ADC0 Electrical Characteristics
V
= 3.0 V, VREF = 2.40 V (REFSL=0), PGA Gain = 1, –40 to +85 °C unless otherwise specified.
DD
Parameters
Test Condition
Min
Typ
Max
Unit
DC Accuracy
Resolution
10
±0.5
±0.5
0
bits
LSB
Integral Nonlinearity
Differential Nonlinearity
Offset Error
—
—
–2
–2
—
±1
±1
+2
+2
—
Guaranteed Monotonic
LSB
LSB
Full Scale Error
0
LSB
Offset Temperature Coefficient
45
ppm/°C
Dynamic performance (10 kHz sine-wave single-ended input, 1 dB below Full Scale, 500 ksps)
Signal-to-Noise Plus Distortion
Total Harmonic Distortion
56
—
—
60
70
93
—
—
—
dB
dB
dB
Up to the 5th harmonic
Spurious-Free Dynamic Range
Conversion Rate
SAR Conversion Clock
—
13
11
—
—
—
—
—
—
8.00
—
—
MHz
clocks
clocks
ns
Conversion Time in SAR Clocks 10-bit Mode
8-bit Mode
Track/Hold Acquisition Time
VDD > 2.0 V
VDD < 2.0 V
300
2.0
—
—
—
µs
Throughput Rate
500
ksps
Analog Inputs
ADC Input Voltage Range
Single Ended (AIN+ – GND)
0
0
—
—
VREF
V
V
Absolute Pin Voltage with respect
to GND
V
IO
Sampling Capacitance
Gain = 1x (AMP0GN0 = 1)
Gain = 0.5x (AMP0GN0 = 0)
—
—
—
5
3
5
—
—
—
pF
pF
kΩ
Input Multiplexer Impedance
Power Specifications
Power Supply Current
Operating Mode, 500 ksps
C8051T626/7/T320/1/2/3
C8051T626/7
(V supplied to ADC0)
—
—
—
600
640
–70
900
900
—
µA
µA
dB
DD
Power Supply Rejection
Note: Represents one standard deviation from the mean.
Rev. 1.2
40
C8051T620/1/6/7 & C8051T320/1/2/3
Table 7.11. Temperature Sensor Electrical Characteristics
V
= 3.0 V, –40 to +85 °C unless otherwise specified.
DD
Parameters
Test Condition
Min
Typ
Max
Unit
Linearity
Slope
—
—
—
—
± 0.2
2.87
2.99
337
—
—
—
—
°C
C8051T626/7/T320/1/2/3
C8051T626/7
mV/°C
mV/°C
µV/°C
Slope Error*
Offset
Temp = 0 °C
C8051T626/7/T320/1/2/3
C8051T626/7
—
—
—
912
925
± 11
—
—
—
mV
mV
mV
Offset Error*
Temp = 0 °C
Note: Represents one standard deviation from the mean.
Table 7.12. Voltage Reference Electrical Characteristics
V
= 3.0 V; –40 to +85 °C unless otherwise specified.
DD
Parameters
Internal Reference (REFBE = 1)
Test Condition
Min
Typ
Max
Unit
Output Voltage
1.2 V Setting, 25 °C ambient
2.4 V Setting, 25 °C ambient
1.1
2.3
1.2
2.4
1.3
2.5
V
VREF Short-Circuit Current
—
—
4.5
6
mA
VREF Temperature
Coefficient
±15
—
ppm/°C
Load Regulation
Load = 0 to 200 µA to GND, 1.2 V Setting
Load = 0 to 200 µA to GND, 2.4 V Setting
—
—
3.3
5.7
—
—
µV/µA
µV/µA
VREF Turn-on Time
(1.2 V setting)
4.7 µF tantalum, 0.1 µF ceramic bypass
0.1 µF ceramic bypass
—
—
—
—
—
—
1.2
25
—
—
—
—
—
—
ms
µs
VREF Turn-on Time
(2.4 V setting)
4.7 µF tantalum, 0.1 µF ceramic bypass
0.1 µF ceramic bypass
3.8
90
ms
µs
Power Supply Rejection
1.2 V Setting
160
330
µV/V
µV/V
2.4 V Setting
External Reference (REFBE = 0)
Input Voltage Range
0
—
V
V
DD
Input Current
Sample Rate = 500 ksps; VREF = 3.0 V
—
12
—
µA
Power Specifications
Reference Bias Generator REFBE = 1 or TEMPE = 1
—
75
100
µA
41
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
Table 7.13. Comparator Electrical Characteristics
VDD = 3.0 V, –40 to +85 °C unless otherwise noted.
Parameters Test Condition
Min
Typ
Max
Unit
Response Time:
Mode 0, Vcm = 1.5 V
CP0+ – CP0– = 100 mV
CP0+ – CP0– = –100 mV
CP0+ – CP0– = 100 mV
CP0+ – CP0– = –100 mV
CP0+ – CP0– = 100 mV
CP0+ – CP0– = –100 mV
CP0+ – CP0– = 100 mV
CP0+ – CP0– = –100 mV
—
—
—
—
—
—
—
—
—
—
2
240
240
400
400
650
1100
2000
5500
1.0
0
—
—
—
—
—
—
—
—
4
ns
ns
*
Response Time:
ns
*
Mode 1, Vcm = 1.5 V
ns
Response Time:
ns
*
Mode 2, Vcm = 1.5 V
ns
Response Time:
ns
*
Mode 3, Vcm = 1.5 V
ns
Common-Mode Rejection Ratio
Positive Hysteresis 1
Positive Hysteresis 2
Positive Hysteresis 3
Positive Hysteresis 4
Negative Hysteresis 1
Negative Hysteresis 2
Negative Hysteresis 3
Negative Hysteresis 4
mV/V
mV
mV
mV
mV
mV
mV
mV
mV
V
CP0HYP1–0 = 00
CP0HYP1–0 = 01
CP0HYP1–0 = 10
CP0HYP1–0 = 11
CP0HYN1–0 = 00
CP0HYN1–0 = 01
CP0HYN1–0 = 10
CP0HYN1–0 = 11
1
5
8
6
10
14
28
1
12
20
0
2
6
5
8
10
14
28
12
20
Inverting or Non-Inverting Input
Voltage Range
–0.25
—
V
+ 0.25
DD
Input Capacitance
Input Offset Voltage
—
4
—
pF
–7.5
—
+7.5
mV
Power Supply
Power Supply Rejection
Power-up Time
—
—
—
—
—
—
0.5
10
26
10
3
—
—
50
20
6
mV/V
µs
Supply Current at DC
Mode 0
Mode 1
Mode 2
Mode 3
µA
µA
µA
0.5
2
µA
Note: Vcm is the common-mode voltage on CP0+ and CP0–.
Rev. 1.2
42
C8051T620/1/6/7 & C8051T320/1/2/3
Table 7.14. USB Transceiver Electrical Characteristics
VDD = 3.0 V to 3.6 V, –40 to +85 °C unless otherwise specified.
Parameters
Transmitter
Output High Voltage (V
Test Condition
Min
Typ
Max
Unit
)
2.8
—
—
—
—
—
V
V
V
OH
Output Low Voltage (V
)
0.8
2.0
OL
Output Crossover Point
(V
1.3
)
CRS
Output Impedance (Z
)
Driving High
Driving Low
—
—
36
36
—
—
Ω
kΩ
ns
ns
DRV
Pull-up Resistance (R
)
Full Speed (D+ Pull-up)
Low Speed (D- Pull-up)
1.425
1.5
1.575
PU
Output Rise Time (T )
Low Speed
Full Speed
75
4
—
—
300
20
R
Output Fall Time (T )
Low Speed
Full Speed
75
4
—
—
300
20
F
Receiver
Differential Input
| (D+) - (D-) |
0.2
0.8
—
—
—
—
2.5
—
V
V
Sensitivity (V )
DI
Differential Input Common
Mode Range (V
)
CM
Input Leakage Current (I ) Pullups Disabled
<1.0
µA
L
Note: Refer to the USB Specification for timing diagrams and symbol definitions.
43
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
7.3. Typical Performance Curves
12.0
10.0
8.0
VDD = 3.3 V
VDD = 1.8 V
6.0
4.0
2.0
0.0
0
5
10
15
20
25
30
35
40
45
50
SYSCLK (MHz)
Figure 7.1. Normal Mode Digital Supply Current vs. Frequency (MPCE = 1)
6.0
5.0
4.0
3.0
VDD = 3.3 V
VDD = 1.8 V
2.0
1.0
0.0
0
5
10
15
20
25
30
35
40
45
50
SYSCLK (MHz)
Figure 7.2. Idle Mode Digital Supply Current vs. Frequency (MPCE = 1)
Rev. 1.2
44
C8051T620/1/6/7 & C8051T320/1/2/3
8. 10-Bit ADC (ADC0, C8051T620/6/7 and C8051T320/1 Only)
ADC0 on the C8051T620/6/7 and C8051T320/1 is a 500 ksps, 10-bit successive-approximation-register
(SAR) ADC with integrated track-and-hold, a gain stage programmable to 1x or 0.5x, and a programmable
window detector. The ADC is fully configurable under software control via Special Function Registers. The
ADC may be configured to measure various different signals using the analog multiplexer described in
Section “8.5. ADC0 Analog Multiplexer (C8051T620/6/7 and C8051T320/1 Only)” on page 55. The voltage
reference for the ADC is selected as described in Section “10. Voltage Reference Options” on page 59.
The ADC0 subsystem is enabled only when the AD0EN bit in the ADC0 Control register (ADC0CN) is set
to logic 1. The ADC0 subsystem is in low power shutdown when this bit is logic 0.
ADC0CN
VDD
000
001
010
011
100
101
AD0BUSY (W)
Start
Conversion
Timer 0 Overflow
Timer 2 Overflow
Timer 1 Overflow
CNVSTR Input
Timer 3 Overflow
10-Bit
SAR
AIN
X1 or
X0.5
From
AMUX0
ADC
AMP0GN0
AD0WINT
Window
Compare
Logic
32
ADC0LTH ADC0LTL
ADC0GTH ADC0GTL
ADC0CF
Figure 8.1. ADC0 Functional Block Diagram
Rev. 1.2
45
C8051T620/1/6/7 & C8051T320/1/2/3
8.1. Output Code Formatting
The ADC measures the input voltage with reference to GND. The registers ADC0H and ADC0L contain the
high and low bytes of the output conversion code from the ADC at the completion of each conversion. Data
can be right-justified or left-justified, depending on the setting of the AD0LJST bit. Conversion codes are
represented as 10-bit unsigned integers. Inputs are measured from 0 to VREF x 1023/1024. Example
codes are shown below for both right-justified and left-justified data. Unused bits in the ADC0H and ADC0L
registers are set to 0.
Input Voltage
Right-Justified ADC0H:ADC0L
(AD0LJST = 0)
Left-Justified ADC0H:ADC0L
(AD0LJST = 1)
VREF x 1023/1024
VREF x 512/1024
VREF x 256/1024
0
0x03FF
0x0200
0x0100
0x0000
0xFFC0
0x8000
0x4000
0x0000
8.2. 8-Bit Mode
Setting the ADC08BE bit in register ADC0CF to 1 will put the ADC in 8-bit mode. In 8-bit mode, only the 8
MSBs of data are converted, and the ADC0H register holds the results. The AD0LJST bit is ignored for 8-
bit mode. 8-bit conversions take two fewer SAR clock cycles than 10-bit conversions, so the conversion is
completed faster, and a 500 ksps sampling rate can be achieved with a slower SAR clock.
8.3. Modes of Operation
ADC0 has a maximum conversion speed of 500 ksps. The ADC0 conversion clock is a divided version of
the system clock, determined by the AD0SC bits in the ADC0CF register.
8.3.1. Starting a Conversion
A conversion can be initiated in one of six ways, depending on the programmed states of the ADC0 Start of
Conversion Mode bits (AD0CM2–0) in register ADC0CN. Conversions may be initiated by one of the fol-
lowing:
1. Writing a 1 to the AD0BUSY bit of register ADC0CN
2. A Timer 0 overflow (i.e., timed continuous conversions)
3. A Timer 2 overflow
4. A Timer 1 overflow
5. A rising edge on the CNVSTR input signal
6. A Timer 3 overflow
Writing a 1 to AD0BUSY provides software control of ADC0 whereby conversions are performed "on-
demand". During conversion, the AD0BUSY bit is set to logic 1 and reset to logic 0 when the conversion is
complete. The falling edge of AD0BUSY triggers an interrupt (when enabled) and sets the ADC0 interrupt
flag (AD0INT). Note: When polling for ADC conversion completions, the ADC0 interrupt flag (AD0INT)
should be used. Converted data is available in the ADC0 data registers, ADC0H:ADC0L, when bit AD0INT
is logic 1. Note that when Timer 2 or Timer 3 overflows are used as the conversion source, Low Byte over-
flows are used if Timer 2/3 is in 8-bit mode; High byte overflows are used if Timer 2/3 is in 16-bit mode.
See Section “28. Timers” on page 246 for timer configuration.
Important Note About Using CNVSTR: The CNVSTR input pin also functions as a Port I/O pin. When the
CNVSTR input is used as the ADC0 conversion source, the associated pin should be skipped by the Digi-
tal Crossbar. See Section “22. Port Input/Output” on page 138 for details on Port I/O configuration.
46
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
8.3.2. Tracking Modes
The AD0TM bit in register ADC0CN enables "delayed conversions", and will delay the actual conversion
start by three SAR clock cycles, during which time the ADC will continue to track the input. If AD0TM is left
at logic 0, a conversion will begin immediately, without the extra tracking time. For internal start-of-conver-
sion sources, the ADC will track anytime it is not performing a conversion. When the CNVSTR signal is
used to initiate conversions, ADC0 will track either when AD0TM is logic 1, or when AD0TM is logic 0 and
CNVSTR is held low. See Figure 8.2 for track and convert timing details. Delayed conversion mode is use-
ful when AMUX settings are frequently changed, due to the settling time requirements described in Section
“8.3.3. Settling Time Requirements” on page 48.
A. ADC Timing for External Trigger Source
CNVSTR
(AD0CM[2:0]=1xx)
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15* 16 17
SAR
Clocks
AD0TM=1
Track
Convert
Track
*Conversion Ends at rising edge of 15th clock in 8-bit Mode
1
2 3 4 5 6 7 8 9 10 11 12* 13 14
SAR Clocks
AD0TM=0 N/C
Track
Convert
N/C
*Conversion Ends at rising edge of 12th clock in 8-bit Mode
B. ADC Timing for Internal Trigger Source
Write '1' to AD0BUSY,
Timer 0, Timer 2, Timer 1 Overflow
(AD0CM[2:0]=000, 001, 010, 011)
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15* 16 17
SAR
Clocks
Track
Convert
Track
AD0TM=1
*Conversion Ends at rising edge of 15th clock in 8-bit Mode
1
2 3 4 5 6 7 8 9 10 11 12* 13 14
SAR
Clocks
AD0TM=0
Track
Convert
Track
*Conversion Ends at rising edge of 12th clock in 8-bit Mode
Figure 8.2. 10-Bit ADC Track and Conversion Example Timing
Rev. 1.2
47
C8051T620/1/6/7 & C8051T320/1/2/3
8.3.3. Settling Time Requirements
A minimum tracking time is required before each conversion to ensure that an accurate conversion is per-
formed. This tracking time is determined by any series impedance, including the AMUX0 resistance, the
the ADC0 sampling capacitance, and the accuracy required for the conversion. Note that in delayed track-
ing mode, three SAR clocks are used for tracking at the start of every conversion. For many applications,
these three SAR clocks will meet the minimum tracking time requirements.
Figure 8.3 shows the equivalent ADC0 input circuit. The required ADC0 settling time for a given settling
accuracy (SA) may be approximated by Equation 8.1. See Table 7.10 for ADC0 minimum settling time
requirements as well as the mux impedance and sampling capacitor values.
2n
SA
------
t = ln
× RTOTALCSAMPLE
Equation 8.1. ADC0 Settling Time Requirements
Where:
SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB)
t is the required settling time in seconds
R
is the sum of the AMUX0 resistance and any external source resistance.
TOTAL
n is the ADC resolution in bits (10).
MUX Select
Input Pin
RMUX
CSAMPLE
RCInput= RMUX * CSAMPLE
Note: See electrical specification tables for RMUX and CSAMPLE parameters.
Figure 8.3. ADC0 Equivalent Input Circuits
48
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 8.1. ADC0CF: ADC0 Configuration
Bit
7
6
5
4
3
2
1
0
AD0SC[4:0]
AD0LJST AD08BE AMP0GN0
Name
Type
Reset
R/W
1
R/W
0
R/W
0
R/W
1
1
1
1
1
SFR Address = 0xBC
Bit Name
7:3 AD0SC[4:0]
Function
ADC0 SAR Conversion Clock Period Bits.
SAR Conversion clock is derived from system clock by the following equation, where
AD0SC refers to the 5-bit value held in bits AD0SC4–0. SAR Conversion clock
requirements are given in the ADC specification table.
SYSCLK
CLKSAR
----------------------
AD0SC =
– 1
Note: If the Memory Power Controller is enabled (MPCE = '1'), AD0SC must be set to at least
"00001" for proper ADC operation.
2
1
0
AD0LJST
AD08BE
ADC0 Left Justify Select.
0: Data in ADC0H:ADC0L registers are right-justified.
1: Data in ADC0H:ADC0L registers are left-justified.
Note: The AD0LJST bit is only valid for 10-bit mode (AD08BE = 0).
8-Bit Mode Enable.
0: ADC operates in 10-bit mode (normal).
1: ADC operates in 8-bit mode.
Note: When AD08BE is set to 1, the AD0LJST bit is ignored.
AMP0GN0
ADC Gain Control Bit.
0: Gain = 0.5
1: Gain = 1
Rev. 1.2
49
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 8.2. ADC0H: ADC0 Data Word MSB
Bit
7
6
5
4
3
2
1
0
ADC0H[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xBE
Bit Name
7:0 ADC0H[7:0]
Function
ADC0 Data Word High-Order Bits.
For AD0LJST = 0: Bits 7–2 will read 000000b. Bits 1–0 are the upper 2 bits of the 10-
bit ADC0 Data Word.
For AD0LJST = 1: Bits 7–0 are the most-significant bits of the 10-bit ADC0 Data
Word.
Note: In 8-bit mode AD0LJST is ignored, and ADC0H holds the 8-bit data word.
SFR Definition 8.3. ADC0L: ADC0 Data Word LSB
Bit
7
6
5
4
3
2
1
0
ADC0L[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xBD
Bit Name
7:0 ADC0L[7:0]
Function
ADC0 Data Word Low-Order Bits.
For AD0LJST = 0: Bits 7–0 are the lower 8 bits of the 10-bit Data Word.
For AD0LJST = 1: Bits 7–6 are the lower 2 bits of the 10-bit Data Word. Bits 5–0 will
read 000000b.
Note: In 8-bit mode AD0LJST is ignored, and ADC0L will read back 00000000b.
50
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 8.4. ADC0CN: ADC0 Control
Bit
7
6
5
4
3
2
1
0
AD0EN
AD0TM
AD0INT AD0BUSY AD0WINT
AD0CM[2:0]
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
0
SFR Address = 0xE8; Bit-Addressable
Bit
Name
Function
7
AD0EN
ADC0 Enable Bit.
0: ADC0 Disabled. ADC0 is in low-power shutdown.
1: ADC0 Enabled. ADC0 is active and ready for data conversions.
6
AD0TM
ADC0 Track Mode Bit.
0: Normal Track Mode: When ADC0 is enabled, tracking is continuous unless a con-
version is in progress. Conversion begins immediately on start-of-conversion event,
as defined by AD0CM[2:0].
1: Delayed Track Mode: When ADC0 is enabled, input is tracked when a conversion
is not in progress. A start-of-conversion signal initiates three SAR clocks of additional
tracking, and then begins the conversion.
5
4
AD0INT
ADC0 Conversion Complete Interrupt Flag.
0: ADC0 has not completed a data conversion since AD0INT was last cleared.
1: ADC0 has completed a data conversion.
AD0BUSY
ADC0 Busy Bit. Read:
0: ADC0 conversion is not in
progress.
Write:
0: No Effect.
1: Initiates ADC0 Conversion if
1: ADC0 conversion is in prog- AD0CM[2:0] = 000b
ress.
3
AD0WINT
ADC0 Window Compare Interrupt Flag.
0: ADC0 Window Comparison Data match has not occurred since this flag was last
cleared.
1: ADC0 Window Comparison Data match has occurred.
2:0 AD0CM[2:0]
ADC0 Start of Conversion Mode Select.
000: ADC0 start-of-conversion source is write of 1 to AD0BUSY.
001: ADC0 start-of-conversion source is overflow of Timer 0.
010: ADC0 start-of-conversion source is overflow of Timer 2.
011: ADC0 start-of-conversion source is overflow of Timer 1.
100: ADC0 start-of-conversion source is rising edge of external CNVSTR.
101: ADC0 start-of-conversion source is overflow of Timer 3.
11x: Reserved.
Rev. 1.2
51
C8051T620/1/6/7 & C8051T320/1/2/3
8.4. Programmable Window Detector
The ADC Programmable Window Detector continuously compares the ADC0 output registers to user-pro-
grammed limits, and notifies the system when a desired condition is detected. This is especially effective in
an interrupt-driven system, saving code space and CPU bandwidth while delivering faster system
response times. The window detector interrupt flag (AD0WINT in register ADC0CN) can also be used in
polled mode. The ADC0 Greater-Than (ADC0GTH, ADC0GTL) and Less-Than (ADC0LTH, ADC0LTL)
registers hold the comparison values. The window detector flag can be programmed to indicate when mea-
sured data is inside or outside of the user-programmed limits, depending on the contents of the ADC0
Less-Than and ADC0 Greater-Than registers.
SFR Definition 8.5. ADC0GTH: ADC0 Greater-Than Data High Byte
Bit
7
6
5
4
3
2
1
0
ADC0GTH[7:0]
R/W
Name
Type
Reset
1
1
1
1
1
1
1
1
SFR Address = 0xC4
Bit Name
7:0 ADC0GTH[7:0]
Function
ADC0 Greater-Than Data Word High-Order Bits.
SFR Definition 8.6. ADC0GTL: ADC0 Greater-Than Data Low Byte
Bit
7
6
5
4
3
2
1
0
ADC0GTL[7:0]
R/W
Name
Type
Reset
1
1
1
1
1
1
1
1
SFR Address = 0xC3
Bit Name
7:0 ADC0GTL[7:0]
Function
ADC0 Greater-Than Data Word Low-Order Bits.
52
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 8.7. ADC0LTH: ADC0 Less-Than Data High Byte
Bit
7
6
5
4
3
2
1
0
ADC0LTH[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xC6
Bit Name
7:0 ADC0LTH[7:0]
Function
ADC0 Less-Than Data Word High-Order Bits.
SFR Definition 8.8. ADC0LTL: ADC0 Less-Than Data Low Byte
Bit
7
6
5
4
3
2
1
0
ADC0LTL[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xC5
Bit Name
7:0 ADC0LTL[7:0]
Function
ADC0 Less-Than Data Word Low-Order Bits.
Rev. 1.2
53
C8051T620/1/6/7 & C8051T320/1/2/3
8.4.1. Window Detector Example
Figure 8.4
shows
two
example
window
comparisons
for
right-justified
data,
with
ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). The input voltage can
range from 0 to VREF x (1023/1024) with respect to GND, and is represented by a 10-bit unsigned integer
value. In the left example, an AD0WINT interrupt will be generated if the ADC0 conversion word
(ADC0H:ADC0L) is within the range defined by ADC0GTH:ADC0GTL and ADC0LTH:ADC0LTL
(if 0x0040 < ADC0H:ADC0L < 0x0080). In the right example, and AD0WINT interrupt will be generated if
the ADC0 conversion word is outside of the range defined by the ADC0GT and ADC0LT registers
(if ADC0H:ADC0L < 0x0040 or ADC0H:ADC0L > 0x0080). Figure 8.5 shows an example using left-justi-
fied data with the same comparison values.
ADC0H:ADC0L
0x03FF
ADC0H:ADC0L
0x03FF
Input Voltage
(AIN - GND)
Input Voltage
(AIN - GND)
VREF x (1023/
1024)
VREF x (1023/
1024)
AD0WINT
not affected
AD0WINT=1
0x0081
0x0081
VREF x (128/1024)
VREF x (64/1024)
0x0080
0x007F
ADC0LTH:ADC0LTL
VREF x (128/1024)
VREF x (64/1024)
0x0080
0x007F
ADC0GTH:ADC0GTL
AD0WINT
not affected
AD0WINT=1
0x0041
0x0040
0x0041
0x0040
ADC0GTH:ADC0GTL
ADC0LTH:ADC0LTL
0x003F
0x003F
AD0WINT=1
AD0WINT
not affected
0x0000
0x0000
0
0
Figure 8.4. ADC Window Compare Example: Right-Justified Data
ADC0H:ADC0L
0xFFC0
ADC0H:ADC0L
0xFFC0
Input Voltage
(AIN - GND)
Input Voltage
(AIN - GND)
VREF x (1023/
1024)
VREF x (1023/
1024)
AD0WINT
not affected
AD0WINT=1
0x2040
0x2040
VREF x (128/1024)
VREF x (64/1024)
0x2000
0x1FC0
ADC0LTH:ADC0LTL
VREF x (128/1024)
VREF x (64/1024)
0x2000
0x1FC0
ADC0GTH:ADC0GTL
AD0WINT
not affected
AD0WINT=1
0x1040
0x1000
0x1040
0x1000
ADC0GTH:ADC0GTL
ADC0LTH:ADC0LTL
0x0FC0
0x0FC0
AD0WINT=1
AD0WINT
not affected
0x0000
0x0000
0
0
Figure 8.5. ADC Window Compare Example: Left-Justified Data
54
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
8.5. ADC0 Analog Multiplexer (C8051T620/6/7 and C8051T320/1 Only)
ADC0 on the C8051T620/6/7 and C8051T320/1 uses an analog input multiplexer to select the positive
input to the ADC. Any of the following may be selected as the positive input: Port 1, 2, P3.0 and some Port
0 I/O pins, the on-chip temperature sensor, or the positive power supply (V ). The ADC0 input channel is
DD
selected in the AMX0P register described in SFR Definition 8.9.
AMX0P
P1.0
P3.0
P0.0
P0.1
P0.4
P0.5
AMUX
ADC0
Temp
Sensor
VDD
Figure 8.6. ADC0 Multiplexer Block Diagram
Important Note About ADC0 Input Configuration: Port pins selected as ADC0 inputs should be config-
ured as analog inputs, and should be skipped by the Digital Crossbar. To configure a Port pin for analog
input, set to 0 the corresponding bit in register PnMDIN. To force the Crossbar to skip a Port pin, set to 1
the corresponding bit in register PnSKIP. See Section “22. Port Input/Output” on page 138 for more Port
I/O configuration details.
Rev. 1.2
55
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 8.9. AMX0P: AMUX0 Positive Channel Select
Bit
7
6
5
4
3
2
1
0
AMX0P[4:0]
Name
Type
Reset
R
1
R
0
R
0
R/W
0
0
0
0
0
SFR Address = 0xBB
Bit
Name
Function
7:5
Unused
Read = 100b; Write = Don’t Care.
4:0 AMX0P[4:0]
AMUX0 Positive Input Selection.
00000:
00001:
00010:
00011:
00100:
00101:
00110:
00111:
01000:
01001:
01010:
01011:
01100:
01101:
01110:
01111:
10000:
10001:
10010:
10011:
10100:
10101-11101:
11110:
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4 (C8051T320/2 and C8051T620/6/7 Only)
P2.5 (C8051T320/2 and C8051T620/6/7 Only)
P2.6 (C8051T320/2 and C8051T620/6/7 Only)
P2.7 (C8051T320/2 Only)
P3.0
P0.0
P0.1
P0.4
P0.5
Reserved
Temp Sensor
11111:
V
DD
56
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
9. Temperature Sensor (C8051T620/6/7 and C8051T320/1 Only)
An on-chip temperature sensor is included on the C8051T620/6/7 and C8051T320/1 which can be directly
accessed via the ADC multiplexer in single-ended configuration. To use the ADC to measure the tempera-
ture sensor, the ADC mux channel should be configured to connect to the temperature sensor. The tem-
perature sensor transfer function is shown in Figure 9.1. The output voltage (V
) is the positive ADC
TEMP
input when the ADC multiplexer is set correctly. The TEMPE bit in register REF0CN enables/disables the
temperature sensor, as described in SFR Definition 10.1. While disabled, the temperature sensor defaults
to a high impedance state and any ADC measurements performed on the sensor will result in meaningless
data. Refer to Table 7.11 for the slope and offset parameters of the temperature sensor.
VTEMP = (Slope x TempC) + Offset
TempC = (VTEMP - Offset) / Slope
Slope (V / deg C)
Offset (V at 0 Celsius)
Temperature
Figure 9.1. Temperature Sensor Transfer Function
Rev. 1.2
57
C8051T620/1/6/7 & C8051T320/1/2/3
9.1. Calibration
The uncalibrated temperature sensor output is extremely linear and suitable for relative temperature mea-
surements (see Table 7.11 on page 41 for specifications). For absolute temperature measurements, offset
and/or gain calibration is recommended.
A single-point offset measurement of the temperature sensor is performed on each device during produc-
tion test. The TOFFH and TOFFL calibration values represent the output of the ADC when reading the
temperature sensor at 0 degrees Celsius, and using the internal regulator as a voltage reference. The
TOFFH and TOFFL values can be read from EPROM memory and are located at 0x3FFB (TOFFH) and
0x3FFA (TOFFL). The temperature sensor offset information is left-justified, so TOFFH contains the 8
most-significant bits of the calibration value and TOFFL.7-6 contain the 2 least-significant bits of the cali-
bration value, as shown in Figure 9.2. One LSB of this measurement is equivalent to one LSB of the ADC
output under the measurement conditions.
TOFFH
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TOFFL
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
10-bit Temperature Sensor Offset Calibration Value
Figure 9.2. TOFFH and TOFFL Calibration Value Orientation
Figure 9.3 shows the typical temperature sensor error assuming a 1-point calibration at 0 °C. Parameters
that affect ADC measurement, in particular the voltage reference value, will also affect temperature
measurement.
5.00
4.00
3.00
2.00
1.00
0.00
5.00
4.00
3.00
2.00
1.00
0.00
-1.00
-2.00
-3.00
-4.00
-5.00
-40.00
-20.00
0.00
20.00
40.00
60.00
80.00
-1.00
-2.00
-3.00
-4.00
-5.00
Temperature (degrees C)
Figure 9.3. Temperature Sensor Error with 1-Point Calibration at 0 Celsius
58
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
10. Voltage Reference Options
The Voltage reference multiplexer for the ADC is configurable to use an externally connected voltage refer-
ence, the on-chip reference voltage generator routed to the VREF pin, the unregulated power supply volt-
age (V ), or the regulated 1.8 V internal supply (see Figure 10.1). The REFSL bit in the Reference
DD
Control register (REF0CN, SFR Definition 10.1) selects the reference source for the ADC. For an external
source or the on-chip reference, REFSL should be set to 0 to select the VREF pin. To use V as the ref-
DD
erence source, REFSL should be set to 1. To override this selection and use the internal regulator as the
reference source, the REGOVR bit can be set to 1.
The BIASE bit enables the internal voltage bias generator, which is used by many of the analog peripherals
on the device. This bias is automatically enabled when any peripheral which requires it is enabled, and it
does not need to be enabled manually. The bias generator may be enabled manually by writing a 1 to the
BIASE bit in register REF0CN. The electrical specifications for the voltage reference circuit are given in
Table 7.12.
The C8051T620/6/7 and C8051T320/1 devices also include an on-chip voltage reference circuit which
consists of a 1.2 V, temperature stable bandgap voltage reference generator and a selectable-gain output
buffer amplifier. The buffer is configured for 1x or 2x gain using the REFBGS bit in register REF0CN. On
the 1x gain setting the output voltage is nominally 1.2 V, and on the 2x gain setting the output voltage is
nominally 2.4 V. The on-chip voltage reference can be driven on the VREF pin by setting the REFBE bit in
register REF0CN to a 1. The maximum load seen by the VREF pin must be less than 200 µA to GND.
Bypass capacitors of 0.1 µF and 4.7 µF are recommended from the VREF pin to GND, and a minimum of
0.1uF is required. If the on-chip reference is not used, the REFBE bit should be cleared to 0. Electrical
specifications for the on-chip voltage reference are given in Table 7.12.
Important Note about the VREF Pin: When using either an external voltage reference or the on-chip ref-
erence circuitry, the VREF pin should be configured as an analog pin and skipped by the Digital Crossbar.
Refer to Section “22. Port Input/Output” on page 138 for the location of the VREF pin, as well as details of
how to configure the pin in analog mode and to be skipped by the crossbar.
REF0CN
To ADC, IDAC,
Internal Oscillators,
Reference,
TempSensor
EN
EN
Bias Generator
Temp Sensor
IOSCEN
VDD
To Analog Mux
REFBE
External
Voltage
Reference
Circuit
R1
VREF
EN
1x/2x
1.2V Reference
REFBGS
GND
0
1
0
1
+
4.7μF
0.1μF
VREF
(to ADC)
VDD
Internal
Regulator
Recommended Bypass
Capacitors
REGOVR
Figure 10.1. Voltage Reference Functional Block Diagram
Rev. 1.2
59
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 10.1. REF0CN: Reference Control
Bit
7
6
5
4
3
2
1
0
REFBGS
REGOVR
REFSL
TEMPE
BIASE
REFBE
Name
Type
Reset
R/W
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Address = 0xD1
Bit
Name
Function
7
REFBGS
Reference Buffer Gain Select.
This bit selects between 1x and 2x gain for the on-chip voltage reference buffer.
0: 2x Gain
1: 1x Gain
6:5
4
Unused Read = 00b; Write = don’t care.
REGOVR
Regulator Reference Override.
This bit “overrides” the REFSL bit, and allows the internal regulator to be used as a ref-
erence source.
0: The voltage reference source is selected by the REFSL bit.
1: The internal regulator is used as the voltage reference.
3
REFSL
Voltage Reference Select.
This bit selects the ADCs voltage reference.
0: V
pin used as voltage reference.
REF
1: V used as voltage reference.
DD
2
1
0
TEMPE
BIASE
Temperature Sensor Enable Bit.
0: Internal Temperature Sensor off.
1: Internal Temperature Sensor on.
Internal Analog Bias Generator Enable Bit.
0: Internal Bias Generator off.
1: Internal Bias Generator on.
REFBE
On-chip Reference Buffer Enable Bit.
0: On-chip Reference Buffer off.
1: On-chip Reference Buffer on. Internal voltage reference driven on the V
pin.
REF
60
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
11. Voltage Regulators (REG0 and REG1)
C8051T620/1/6/7 & C8051T320/1/2/3 devices include two internal voltage regulators: one regulates a volt-
age source on REGIN to 3.45 V (REG0), and the other regulates the internal core supply to 1.8 V from a
V
supply of 1.8 to 3.6 V (REG1). When enabled, the REG0 output appears on the V pin and can be
DD
DD
used to power external devices. REG0 can be enabled/disabled by software using bit REG0DIS in register
REG01CN (SFR Definition 11.1). REG1 has two power-saving modes built into the regulator to help
reduce current consumption in low-power applications. These modes are accessed through the REG01CN
register. Electrical characteristics for the on-chip regulators are specified in Table 7.5 on page 37.
Note that the VBUS signal must be connected to the VBUS pin when using the device in a USB network.
The VBUS signal should only be connected to the REGIN pin when operating the device as a bus-powered
function. REG0 configuration options are shown in Figure 11.1–Figure 11.4.
11.1. Voltage Regulator (REG0)
11.1.1. Regulator Mode Selection
REG0 offers a low power mode intended for use when the device is in suspend mode. In this low power
mode, the REG0 output remains as specified; however the REG0 dynamic performance (response time) is
degraded. See Table 7.5 for normal and low power mode supply current specifications. The REG0 mode
selection is controlled via the REG0MD bit in register REG01CN.
11.1.2. VBUS Detection
When the USB Function Controller is used (see section Section “23. Universal Serial Bus Controller
(USB0)” on page 160), the VBUS signal should be connected to the VBUS pin. The VBSTAT bit (register
REG01CN) indicates the current logic level of the VBUS signal. If enabled, a VBUS interrupt will be gener-
ated when the VBUS signal has either a falling or rising edge. The VBUS interrupt is edge-sensitive, and
has no associated interrupt pending flag. See Table 7.5 for VBUS input parameters.
Important Note: When USB is selected as a reset source, a system reset will be generated when a falling
or rising edge occurs on the VBUS pin. See Section “20. Reset Sources” on page 121 for details on select-
ing USB as a reset source.
VBUS
VBUS Sense
From VBUS
REGIN
VDD
5V In
Voltage Regulator (REG0)
3V Out
To 3 V
Device
Power Net
Power Net
Figure 11.1. REG0 Configuration: USB Bus-Powered
Rev. 1.2
61
C8051T620/1/6/7 & C8051T320/1/2/3
VBUS
From VBUS
VBUS Sense
From 5 V
Power Net
REGIN
VDD
5 V In
Voltage Regulator (REG0)
3 V Out
To 3 V
Device
Power Net
Power Net
Figure 11.2. REG0 Configuration: USB Self-Powered
VBUS
From VBUS
VBUS Sense
REGIN
5 V In
Voltage Regulator (REG0)
3 V Out
From 3 V
Device
VDD
Power Net
Power Net
Figure 11.3. REG0 Configuration: USB Self-Powered, Regulator Disabled
62
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
VBUS
VBUS Sense
From 5 V
Power Net
REGIN
5 V In
Voltage Regulator (REG0)
3 V Out
To 3 V
Device
VDD
Power Net
Power Net
Figure 11.4. REG0 Configuration: No USB Connection
Rev. 1.2
63
C8051T620/1/6/7 & C8051T320/1/2/3
11.2. Voltage Regulator (REG1)
Under default conditions, the internal REG1 regulator will remain on when the device enters STOP mode.
This allows any enabled reset source to generate a reset for the device and bring the device out of STOP
mode. For additional power savings, the STOPCF bit can be used to shut down the regulator and the inter-
nal power network of the device when the part enters STOP mode. When STOPCF is set to 1, the RST pin
and a full power cycle of the device are the only methods of generating a reset.
REG1 offers an additional low power mode intended for use when the device is in suspend mode. This low
power mode should not be used during normal operation or if the REG0 Voltage Regulator is disabled. See
Table 7.5 for normal and low power mode supply current specifications. The REG1 mode selection is con-
trolled via the REG1MD bit in register REG01CN.
Important Note: At least 12 clock instructions must occur after placing REG1 in low power mode before
the Internal High Frequency Oscillator is Suspended (OSCICN.5 = 1b).
64
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 11.1. REG01CN: Voltage Regulator Control
Bit
7
6
5
4
3
2
1
0
REG0DIS
VBSTAT
Reserved
REG0MD
STOPCF
Reserved
REG1MD
MPCE
Name
Type
Reset
R/W
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Address = 0xC9
Bit
Name
Function
7
REG0DIS
Voltage Regulator (REG0) Disable.
This bit enables or disables the REG0 Voltage Regulator.
0: Voltage Regulator Enabled.
1: Voltage Regulator Disabled.
6
VBSTAT
VBUS Signal Status.
This bit indicates whether the device is connected to a USB network.
0: VBUS signal currently absent (device not attached to USB network).
1: VBUS signal currently present (device attached to USB network).
5
4
Reserved Must Write 0b.
REG0MD
Voltage Regulator (REG0) Mode Select.
This bit selects the Voltage Regulator mode for REG0. When REG0MD is set to 1, the REG0
voltage regulator operates in lower power (suspend) mode.
0: REG0 Voltage Regulator in normal mode.
1: REG0 Voltage Regulator in low power mode.
3
STOPCF
Stop Mode Configuration (REG1).
This bit configures the REG1 regulator’s behavior when the device enters STOP mode.
0: REG1 Regulator is still active in STOP mode. Any enabled reset source will reset the device.
1: REG1 Regulator is shut down in STOP mode. Only the RST pin or power cycle can reset the
device.
2
1
Reserved Must Write 0b.
REG1MD
Voltage Regulator (REG1) Mode.
This bit selects the Voltage Regulator mode for REG1. When REG1MD is set to 1, the REG1
voltage regulator operates in lower power mode.
0: REG1 Voltage Regulator in normal mode.
1: REG1 Voltage Regulator in low power mode.
Note: This bit should not be set to '1' if the REG0 Voltage Regulator is disabled.
0
MPCE
Memory Power Controller Enable.
This bit can help the system save power at slower system clock frequencies (about 2.0 MHz or
less) by automatically shutting down the EPROM memory between clocks when information is
not being fetched from the EPROM memory. This bit has no effect when the prefetch engine is
enabled.
0: Normal Mode - Memory power controller disabled (EPROM memory is always on).
1: Low Power Mode - Memory power controller enabled (EPROM turns on/off as needed).
Note: If an external clock source is used with the Memory Power Controller enabled, and the
clock frequency changes from slow (< 2.0 MHz) to fast (> 2.0 MHz), up to 20 clocks may
be "skipped" to ensure that the EPROM power is stable before reading memory.
Rev. 1.2
65
C8051T620/1/6/7 & C8051T320/1/2/3
12. CIP-51 Microcontroller
The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the
MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft-
ware. The MCU family has a superset of all the peripherals included with a standard 8051. The CIP-51
also includes on-chip debug hardware (see description in Section 30), and interfaces directly with the ana-
log and digital subsystems providing a complete data acquisition or control-system solution in a single inte-
grated circuit.
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as
additional custom peripherals and functions to extend its capability (see Figure 12.1 for a block diagram).
The CIP-51 includes the following features:
Fully Compatible with MCS-51 Instruction Set
48 MIPS Peak Throughput with 48 MHz Clock
0 to 48 MHz Clock Frequency
Reset Input
Power Management Modes
On-chip Debug Logic
Extended Interrupt Handler
Program and Data Memory Security
Performance
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan-
dard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51
core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more
than eight system clock cycles.
DATA BUS
ACCUMULATOR
B
REGISTER
STACK POINTER
TMP1
TMP2
SRAM
ADDRESS
REGISTER
PSW
SRAM
ALU
DATA BUS
SFR_ADDRESS
SFR_CONTROL
D8
BUFFER
SFR
BUS
INTERFACE
D8
SFR_WRITE_DATA
SFR_READ_DATA
DATA POINTER
D8
PC INCREMENTER
D8
MEM_ADDRESS
MEM_CONTROL
PROGRAM COUNTER (PC)
PRGM. ADDRESS REG.
PIPELINE
MEMORY
INTERFACE
A16
D8
MEM_WRITE_DATA
MEM_READ_DATA
CONTROL
LOGIC
RESET
CLOCK
SYSTEM_IRQs
INTERRUPT
INTERFACE
EMULATION_IRQ
D8
STOP
IDLE
POWER CONTROL
REGISTER
D8
Figure 12.1. CIP-51 Block Diagram
Rev. 1.2
66
C8051T620/1/6/7 & C8051T320/1/2/3
With the CIP-51's maximum system clock at 48 MHz, it has a peak throughput of 48 MIPS. The CIP-51 has
a total of 109 instructions. The table below shows the total number of instructions that require each execu-
tion time.
Clocks to Execute
1
2
2/4
5
3
3/5
7
4
5
5
2
4/6
1
6
2
8
1
Number of Instructions
26
50
10
Programming and Debugging Support
In-system programming of the EPROM program memory and communication with on-chip debug support
logic is accomplished via the Silicon Labs 2-Wire Development Interface (C2).
The on-chip debug support logic facilitates full speed in-circuit debugging, allowing the setting of hardware
breakpoints, starting, stopping and single stepping through program execution (including interrupt service
routines), examination of the program's call stack, and reading/writing the contents of registers and mem-
ory. This method of on-chip debugging is completely non-intrusive, requiring no RAM, Stack, timers, or
other on-chip resources. C2 details can be found in Section “30. C2 Interface” on page 288.
The CIP-51 is supported by development tools from Silicon Labs and third party vendors. Silicon Labs pro-
vides an integrated development environment (IDE) including editor, debugger and programmer. The IDE's
debugger and programmer interface to the CIP-51 via the C2 interface to provide fast and efficient in-sys-
tem device programming and debugging. Third party macro assemblers and C compilers are also avail-
able.
12.1. Instruction Set
The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ instruc-
tion set. Standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51
instructions are the binary and functional equivalent of their MCS-51™ counterparts, including opcodes,
addressing modes and effect on PSW flags. However, instruction timing is different than that of the stan-
dard 8051.
12.1.1. Instruction and CPU Timing
In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with
machine cycles varying from 2 to 12 clock cycles in length. However, the CIP-51 implementation is based
solely on clock cycle timing. All instruction timings are specified in terms of clock cycles.
Due to the pipelined architecture of the CIP-51, most instructions execute in the same number of clock
cycles as there are program bytes in the instruction. Conditional branch instructions take one less clock
cycle to complete when the branch is not taken as opposed to when the branch is taken. Table 12.1 is the
CIP-51 Instruction Set Summary, which includes the mnemonic, number of bytes, and number of clock
cycles for each instruction.
67
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
Table 12.1. CIP-51 Instruction Set Summary
Mnemonic
Description
Bytes
Clock
Cycles
Arithmetic Operations
ADD A, Rn
Add register to A
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
1
1
2
1
1
1
1
1
1
2
2
2
1
2
2
2
1
2
2
2
1
1
2
2
1
1
2
2
1
4
8
1
ADD A, direct
ADD A, @Ri
ADD A, #data
ADDC A, Rn
ADDC A, direct
ADDC A, @Ri
ADDC A, #data
SUBB A, Rn
SUBB A, direct
SUBB A, @Ri
SUBB A, #data
INC A
Add direct byte to A
Add indirect RAM to A
Add immediate to A
Add register to A with carry
Add direct byte to A with carry
Add indirect RAM to A with carry
Add immediate to A with carry
Subtract register from A with borrow
Subtract direct byte from A with borrow
Subtract indirect RAM from A with borrow
Subtract immediate from A with borrow
Increment A
INC Rn
Increment register
INC direct
Increment direct byte
INC @Ri
Increment indirect RAM
Decrement A
DEC A
DEC Rn
Decrement register
DEC direct
Decrement direct byte
DEC @Ri
Decrement indirect RAM
Increment Data Pointer
Multiply A and B
INC DPTR
MUL AB
DIV AB
Divide A by B
DA A
Decimal adjust A
Logical Operations
ANL A, Rn
AND Register to A
1
2
1
2
2
3
1
1
2
2
2
2
3
1
ANL A, direct
ANL A, @Ri
ANL A, #data
ANL direct, A
ANL direct, #data
ORL A, Rn
AND direct byte to A
AND indirect RAM to A
AND immediate to A
AND A to direct byte
AND immediate to direct byte
OR Register to A
Rev. 1.2
68
C8051T620/1/6/7 & C8051T320/1/2/3
Table 12.1. CIP-51 Instruction Set Summary(Continued)
Mnemonic
Description
Bytes
Clock
Cycles
ORL A, direct
OR direct byte to A
2
1
2
2
3
1
2
1
2
2
3
1
1
1
1
1
1
1
2
2
2
2
3
1
2
2
2
2
3
1
1
1
1
1
1
1
ORL A, @Ri
ORL A, #data
ORL direct, A
ORL direct, #data
XRL A, Rn
OR indirect RAM to A
OR immediate to A
OR A to direct byte
OR immediate to direct byte
Exclusive-OR Register to A
Exclusive-OR direct byte to A
Exclusive-OR indirect RAM to A
Exclusive-OR immediate to A
Exclusive-OR A to direct byte
Exclusive-OR immediate to direct byte
Clear A
XRL A, direct
XRL A, @Ri
XRL A, #data
XRL direct, A
XRL direct, #data
CLR A
CPL A
Complement A
RL A
Rotate A left
RLC A
Rotate A left through Carry
Rotate A right
RR A
RRC A
Rotate A right through Carry
Swap nibbles of A
SWAP A
Data Transfer
MOV A, Rn
Move Register to A
1
2
1
2
1
2
2
2
2
3
2
3
1
2
2
1
2
2
2
1
2
2
2
2
3
2
3
2
2
2
MOV A, direct
MOV A, @Ri
MOV A, #data
MOV Rn, A
Move direct byte to A
Move indirect RAM to A
Move immediate to A
Move A to Register
MOV Rn, direct
MOV Rn, #data
MOV direct, A
MOV direct, Rn
MOV direct, direct
MOV direct, @Ri
MOV direct, #data
MOV @Ri, A
MOV @Ri, direct
MOV @Ri, #data
Move direct byte to Register
Move immediate to Register
Move A to direct byte
Move Register to direct byte
Move direct byte to direct byte
Move indirect RAM to direct byte
Move immediate to direct byte
Move A to indirect RAM
Move direct byte to indirect RAM
Move immediate to indirect RAM
69
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
Table 12.1. CIP-51 Instruction Set Summary(Continued)
Mnemonic
Description
Bytes
Clock
Cycles
MOV DPTR, #data16
MOVC A, @A+DPTR
MOVC A, @A+PC
MOVX A, @Ri
MOVX @Ri, A
MOVX A, @DPTR
MOVX @DPTR, A
PUSH direct
POP direct
Load DPTR with 16-bit constant
Move code byte relative DPTR to A
Move code byte relative PC to A
Move external data (8-bit address) to A
Move A to external data (8-bit address)
Move external data (16-bit address) to A
Move A to external data (16-bit address)
Push direct byte onto stack
3
1
1
1
1
1
1
2
2
1
2
1
1
3
3
3
3
3
3
3
2
2
1
2
2
2
Pop direct byte from stack
XCH A, Rn
Exchange Register with A
XCH A, direct
XCH A, @Ri
XCHD A, @Ri
Boolean Manipulation
CLR C
Exchange direct byte with A
Exchange indirect RAM with A
Exchange low nibble of indirect RAM with A
Clear Carry
1
2
1
2
1
2
2
2
2
2
2
2
2
2
3
3
3
1
2
CLR bit
Clear direct bit
SETB C
Set Carry
1
SETB bit
Set direct bit
2
CPL C
Complement Carry
1
CPL bit
Complement direct bit
AND direct bit to Carry
AND complement of direct bit to Carry
OR direct bit to carry
OR complement of direct bit to Carry
Move direct bit to Carry
Move Carry to direct bit
Jump if Carry is set
2
ANL C, bit
2
ANL C, /bit
2
ORL C, bit
2
ORL C, /bit
2
MOV C, bit
2
MOV bit, C
2
JC rel
2/4
2/4
3/5
3/5
3/5
JNC rel
Jump if Carry is not set
Jump if direct bit is set
Jump if direct bit is not set
Jump if direct bit is set and clear bit
JB bit, rel
JNB bit, rel
JBC bit, rel
Program Branching
ACALL addr11
LCALL addr16
Absolute subroutine call
Long subroutine call
2
3
4
5
Rev. 1.2
70
C8051T620/1/6/7 & C8051T320/1/2/3
Table 12.1. CIP-51 Instruction Set Summary(Continued)
Mnemonic
Description
Bytes
Clock
Cycles
RET
Return from subroutine
1
1
2
3
2
1
2
2
3
3
3
6
6
RETI
Return from interrupt
AJMP addr11
LJMP addr16
SJMP rel
Absolute jump
4
Long jump
5
Short jump (relative address)
Jump indirect relative to DPTR
Jump if A equals zero
4
JMP @A+DPTR
JZ rel
4
2/4
2/4
3/5
3/5
3/5
JNZ rel
Jump if A does not equal zero
Compare direct byte to A and jump if not equal
Compare immediate to A and jump if not equal
CJNE A, direct, rel
CJNE A, #data, rel
CJNE Rn, #data, rel
Compare immediate to Register and jump if not
equal
CJNE @Ri, #data, rel
Compare immediate to indirect and jump if not
equal
3
4/6
DJNZ Rn, rel
DJNZ direct, rel
NOP
Decrement Register and jump if not zero
Decrement direct byte and jump if not zero
No operation
2
3
1
2/4
3/5
1
71
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
Notes on Registers, Operands and Addressing Modes:
Rn - Register R0–R7 of the currently selected register bank.
@Ri - Data RAM location addressed indirectly through R0 or R1.
rel - 8-bit, signed (two’s complement) offset relative to the first byte of the following instruction. Used by
SJMP and all conditional jumps.
direct - 8-bit internal data location’s address. This could be a direct-access Data RAM location (0x00–
0x7F) or an SFR (0x80–0xFF).
#data - 8-bit constant
#data16 - 16-bit constant
bit - Direct-accessed bit in Data RAM or SFR
addr11 - 11-bit destination address used by ACALL and AJMP. The destination must be within the same
2 kB page of program memory as the first byte of the following instruction.
addr16 - 16-bit destination address used by LCALL and LJMP. The destination may be anywhere within
the 8 kB program memory space.
There is one unused opcode (0xA5) that performs the same function as NOP.
All mnemonics copyrighted © Intel Corporation 1980.
Rev. 1.2
72
C8051T620/1/6/7 & C8051T320/1/2/3
12.2. CIP-51 Register Descriptions
Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits
should always be written to the value indicated in the SFR description. Future product versions may use
these bits to implement new features in which case the reset value of the bit will be the indicated value,
selecting the feature's default state. Detailed descriptions of the remaining SFRs are included in the sec-
tions of the datasheet associated with their corresponding system function.
SFR Definition 12.1. DPL: Data Pointer Low Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
DPL[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Address = 0x82
Bit
Name
DPL[7:0] Data Pointer Low.
The DPL register is the low byte of the 16-bit DPTR.
Function
7:0
SFR Definition 12.2. DPH: Data Pointer High Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
DPH[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Address = 0x83
Bit
Name
Function
7:0
DPH[7:0] Data Pointer High.
The DPH register is the high byte of the 16-bit DPTR.
73
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 12.3. SP: Stack Pointer
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
SP[7:0]
R/W
0
0
0
0
0
1
1
1
SFR Address = 0x81
Bit
Name
Function
7:0
SP[7:0]
Stack Pointer.
The Stack Pointer holds the location of the top of the stack. The stack pointer is incre-
mented before every PUSH operation. The SP register defaults to 0x07 after reset.
SFR Definition 12.4. ACC: Accumulator
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
ACC[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Address = 0xE0; Bit-Addressable
Bit
Name
Function
7:0
ACC[7:0] Accumulator.
This register is the accumulator for arithmetic operations.
SFR Definition 12.5. B: B Register
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
B[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Address = 0xF0; Bit-Addressable
Bit
Name
Function
7:0
B[7:0]
B Register.
This register serves as a second accumulator for certain arithmetic operations.
Rev. 1.2
74
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 12.6. PSW: Program Status Word
Bit
7
CY
R/W
0
6
AC
R/W
0
5
F0
R/W
0
4
3
2
OV
R/W
0
1
F1
R/W
0
0
Name
Type
Reset
RS[1:0]
R/W
PARITY
R
0
0
0
SFR Address = 0xD0; Bit-Addressable
Bit
Name
Function
7
CY
Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry (addition) or a bor-
row (subtraction). It is cleared to logic 0 by all other arithmetic operations.
6
AC
Auxiliary Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry into (addition) or a
borrow from (subtraction) the high order nibble. It is cleared to logic 0 by all other arith-
metic operations.
5
F0
User Flag 0.
This is a bit-addressable, general purpose flag for use under software control.
4:3
RS[1:0] Register Bank Select.
These bits select which register bank is used during register accesses.
00: Bank 0, Addresses 0x00-0x07
01: Bank 1, Addresses 0x08-0x0F
10: Bank 2, Addresses 0x10-0x17
11: Bank 3, Addresses 0x18-0x1F
2
OV
Overflow Flag.
This bit is set to 1 under the following circumstances:
An ADD, ADDC, or SUBB instruction causes a sign-change overflow.
A MUL instruction results in an overflow (result is greater than 255).
A DIV instruction causes a divide-by-zero condition.
The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all
other cases.
1
0
F1
User Flag 1.
This is a bit-addressable, general purpose flag for use under software control.
PARITY Parity Flag.
This bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared
if the sum is even.
75
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
13. Prefetch Engine
The C8051T620/1/6/7 & C8051T320/1/2/3 family of devices incorporate a 2-byte prefetch engine. Because
the access time of the EPROM memory is 40 ns, and the minimum instruction time is roughly 20 ns, the
prefetch engine is necessary for full-speed code execution. Instructions are read from EPROM memory
two bytes at a time by the prefetch engine and given to the CIP-51 processor core to execute. When run-
ning linear code (code without any jumps or branches), the prefetch engine allows instructions to be exe-
cuted at full speed. When a code branch occurs, the processor may be stalled for up to two clock cycles
while the next set of code bytes is retrieved from EPROM memory.
Note: The prefetch engine should be disabled when the device is in suspend mode to save power.
SFR Definition 13.1. PFE0CN: Prefetch Engine Control
Bit
7
6
5
4
3
2
1
0
PFEN
Name
Type
Reset
R
0
R
0
R/W
1
R
0
R
0
R
0
R
0
R
0
SFR Address = 0xAF
Bit
Name
Unused Read = 00b, Write = don’t care.
PFEN
Function
7:6
5
Prefetch Enable.
This bit enables the prefetch engine.
0: Prefetch engine is disabled.
1: Prefetch engine is enabled.
4:0
Unused Read = 00000b. Write = don’t care.
Rev. 1.2
76
C8051T620/1/6/7 & C8051T320/1/2/3
14. Comparator0 and Comparator1
C8051T620/1/6/7 & C8051T320/1/2/3 devices include two on-chip programmable voltage comparators:
Comparator0 is shown in Figure 14.1, Comparator1 is shown in Figure 14.2. The two comparators operate
identically with the following exceptions: (1) Their input selections differ as described in Section
“14.1. Comparator Multiplexers” on page 84; (2) Comparator0 can be used as a reset source.
The Comparators offer programmable response time and hysteresis, an analog input multiplexer, and two
outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0 or CP1), or an
asynchronous “raw” output (CP0A or CP1A). The asynchronous signals are available even when the sys-
tem clock is not active. This allows the Comparators to operate and generate an output with the device in
STOP mode. When assigned to a Port pin, the Comparator outputs may be configured as open drain or
push-pull (see Section “22.4. Port I/O Initialization” on page 146). Comparator0 may also be used as a
reset source (see Section “20.5. Comparator0 Reset” on page 124).
The Comparator inputs are selected by the comparator input multiplexers, as detailed in Section
“14.1. Comparator Multiplexers” on page 84.
CPT0CN
VDD
CP0 +
+
CP0
Comparator
Input Mux
SET
CLR
SET
CLR
D
Q
Q
D
Q
Q
CP0 -
-
Crossbar
(SYNCHRONIZER)
CP0A
GND
Reset
Decision
Tree
CPT0MD
0
1
CP0
Interrupt
CP0EN
EA
CP0RIF
CP0FIF
0
0
1
1
0
1
Figure 14.1. Comparator0 Functional Block Diagram
Rev. 1.2
77
C8051T620/1/6/7 & C8051T320/1/2/3
CPT1CN
VDD
CP1 +
+
CP1
Comparator
Input Mux
SET
CLR
SET
CLR
D
Q
Q
D
Q
Q
CP1 -
-
Crossbar
(SYNCHRONIZER)
CP1A
GND
CPT1MD
0
1
CP1
Interrupt
CP1EN
EA
CP1RIF
CP1FIF
0
0
1
1
0
1
Figure 14.2. Comparator1 Functional Block Diagram
The Comparator output can be polled in software, used as an interrupt source, and/or routed to a Port pin.
When routed to a Port pin, the Comparator output is available asynchronous or synchronous to the system
clock; the asynchronous output is available even in STOP mode (with no system clock active). When dis-
abled, the Comparator output (if assigned to a Port I/O pin via the Crossbar) defaults to the logic low state,
and the power supply to the comparator is turned off. See Section “22.3. Priority Crossbar Decoder” on
page 142 for details on configuring Comparator outputs via the digital Crossbar. Comparator inputs can be
externally driven from –0.25 V to (V ) + 0.25 V without damage or upset. The complete Comparator elec-
DD
trical specifications are given in Section “7. Electrical Characteristics” on page 34.
The Comparator response time may be configured in software via the CPTnMD registers (see SFR Defini-
tion 14.2 and SFR Definition 14.4). Selecting a longer response time reduces the Comparator supply cur-
rent.
78
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
CPn+
CPn-
VIN+
VIN-
+
CPn
_
OUT
CIRCUIT CONFIGURATION
Positive Hysteresis Voltage
(Programmed with CPnHYP Bits)
VIN-
Negative Hysteresis Voltage
INPUTS
(Programmed by CPnHYN Bits)
VIN+
VOH
OUTPUT
VOL
Negative Hysteresis
Disabled
Maximum
Negative Hysteresis
Positive Hysteresis
Disabled
Maximum
Positive Hysteresis
Figure 14.3. Comparator Hysteresis Plot
The Comparator hysteresis is software-programmable via its Comparator Control register CPTnCN
(for n = 0 or 1). The user can program both the amount of hysteresis voltage (referred to the input voltage)
and the positive and negative-going symmetry of this hysteresis around the threshold voltage.
The Comparator hysteresis is programmed using Bits3–0 in the Comparator Control Register CPTnCN
(shown in SFR Definition 14.1). The amount of negative hysteresis voltage is determined by the settings of
the CPnHYN bits. Settings of 20, 10 or 5 mV of nominal negative hysteresis can be programmed, or nega-
tive hysteresis can be disabled. In a similar way, the amount of positive hysteresis is determined by the
setting the CPnHYP bits.
Comparator interrupts can be generated on both rising-edge and falling-edge output transitions. (For Inter-
rupt enable and priority control, see Section “17.1. MCU Interrupt Sources and Vectors” on page 102). The
CPnFIF flag is set to logic 1 upon a Comparator falling-edge occurrence, and the CPnRIF flag is set to
logic 1 upon the Comparator rising-edge occurrence. Once set, these bits remain set until cleared by soft-
ware. The Comparator rising-edge interrupt mask is enabled by setting CPnRIE to a logic 1. The Compar-
ator falling-edge interrupt mask is enabled by setting CPnFIE to a logic 1.
The output state of the Comparator can be obtained at any time by reading the CPnOUT bit. The Compar-
ator is enabled by setting the CPnEN bit to logic 1, and is disabled by clearing this bit to logic 0.
Note that false rising edges and falling edges can be detected when the comparator is first powered on or
if changes are made to the hysteresis or response time control bits. Therefore, it is recommended that the
rising-edge and falling-edge flags be explicitly cleared to logic 0 a short time after the comparator is
enabled or its mode bits have been changed.
Rev. 1.2
79
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 14.1. CPT0CN: Comparator0 Control
Bit
7
6
5
4
3
2
1
0
CP0EN
CP0OUT
CP0RIF
CP0FIF
CP0HYP[1:0]
R/W
CP0HYN[1:0]
R/W
Name
Type
Reset
R/W
0
R
0
R/W
0
R/W
0
0
0
0
0
SFR Address = 0x9B
Bit
Name
Function
7
CP0EN
Comparator0 Enable Bit.
0: Comparator0 Disabled.
1: Comparator0 Enabled.
6
5
4
CP0OUT
CP0RIF
CP0FIF
Comparator0 Output State Flag.
0: Voltage on CP0+ < CP0–.
1: Voltage on CP0+ > CP0–.
Comparator0 Rising-Edge Flag. Must be cleared by software.
0: No Comparator0 Rising Edge has occurred since this flag was last cleared.
1: Comparator0 Rising Edge has occurred.
Comparator0 Falling-Edge Flag. Must be cleared by software.
0: No Comparator0 Falling-Edge has occurred since this flag was last cleared.
1: Comparator0 Falling-Edge has occurred.
3:2 CP0HYP[1:0]
1:0 CP0HYN[1:0]
Comparator0 Positive Hysteresis Control Bits.
00: Positive Hysteresis Disabled.
01: Positive Hysteresis = 5 mV.
10: Positive Hysteresis = 10 mV.
11: Positive Hysteresis = 20 mV.
Comparator0 Negative Hysteresis Control Bits.
00: Negative Hysteresis Disabled.
01: Negative Hysteresis = 5 mV.
10: Negative Hysteresis = 10 mV.
11: Negative Hysteresis = 20 mV.
80
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 14.2. CPT0MD: Comparator0 Mode Selection
Bit
7
6
5
4
3
2
1
0
CP0RIE
CP0FIE
CP0MD[1:0]
R/W
Name
Type
Reset
R
0
R
0
R/W
0
R/W
0
R
0
R
0
1
0
SFR Address = 0x9D
Bit
Name
Function
7:6
5
Unused
CP0RIE
Read = 00b, Write = Don’t Care.
Comparator0 Rising-Edge Interrupt Enable.
0: Comparator0 Rising-edge interrupt disabled.
1: Comparator0 Rising-edge interrupt enabled.
4
CP0FIE
Unused
Comparator0 Falling-Edge Interrupt Enable.
0: Comparator0 Falling-edge interrupt disabled.
1: Comparator0 Falling-edge interrupt enabled.
3:2
Read = 00b, Write = don’t care.
1:0 CP0MD[1:0]
Comparator0 Mode Select.
These bits affect the response time and power consumption for Comparator0.
00: Mode 0 (Fastest Response Time, Highest Power Consumption)
01: Mode 1
10: Mode 2
11: Mode 3 (Slowest Response Time, Lowest Power Consumption)
Rev. 1.2
81
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 14.3. CPT1CN: Comparator1 Control
Bit
7
6
5
4
3
2
1
0
CP1EN
CP1OUT
CP1RIF
CP1FIF
CP1HYP[1:0]
R/W
CP1HYN[1:0]
R/W
Name
Type
Reset
R/W
0
R
0
R/W
0
R/W
0
0
0
0
0
SFR Address = 0x9A
Bit
Name
Function
7
CP1EN
Comparator1 Enable Bit.
0: Comparator1 Disabled.
1: Comparator1 Enabled.
6
5
4
CP1OUT
CP1RIF
CP1FIF
Comparator1 Output State Flag.
0: Voltage on CP1+ < CP0–.
1: Voltage on CP1+ > CP0–.
Comparator1 Rising-Edge Flag. Must be cleared by software.
0: No Comparator1 Rising Edge has occurred since this flag was last cleared.
1: Comparator1 Rising Edge has occurred.
Comparator1 Falling-Edge Flag. Must be cleared by software.
0: No Comparator1 Falling-Edge has occurred since this flag was last cleared.
1: Comparator1 Falling-Edge has occurred.
3:2 CP1HYP[1:0]
1:0 CP1HYN[1:0]
Comparator1 Positive Hysteresis Control Bits.
00: Positive Hysteresis Disabled.
01: Positive Hysteresis = 5 mV.
10: Positive Hysteresis = 10 mV.
11: Positive Hysteresis = 20 mV.
Comparator1 Negative Hysteresis Control Bits.
00: Negative Hysteresis Disabled.
01: Negative Hysteresis = 5 mV.
10: Negative Hysteresis = 10 mV.
11: Negative Hysteresis = 20 mV.
82
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 14.4. CPT1MD: Comparator1 Mode Selection
Bit
7
6
5
4
3
2
1
0
CP1RIE
CP1FIE
CP1MD[1:0]
R/W
Name
Type
Reset
R
0
R
0
R/W
0
R/W
0
R
0
R
0
1
0
SFR Address = 0x9C
Bit
Name
Function
7:6
5
Unused
CP1RIE
Read = 00b, Write = Don’t Care.
Comparator1 Rising-Edge Interrupt Enable.
0: Comparator1 Rising-edge interrupt disabled.
1: Comparator1 Rising-edge interrupt enabled.
4
CP1FIE
Unused
Comparator1 Falling-Edge Interrupt Enable.
0: Comparator1 Falling-edge interrupt disabled.
1: Comparator1 Falling-edge interrupt enabled.
3:2
Read = 00b, Write = don’t care.
1:0 CP1MD[1:0]
Comparator1 Mode Select.
These bits affect the response time and power consumption for Comparator1.
00: Mode 0 (Fastest Response Time, Highest Power Consumption)
01: Mode 1
10: Mode 2
11: Mode 3 (Slowest Response Time, Lowest Power Consumption)
Rev. 1.2
83
C8051T620/1/6/7 & C8051T320/1/2/3
14.1. Comparator Multiplexers
C8051T620/1/6/7 & C8051T320/1/2/3 devices include an analog input multiplexer to connect Port I/O pins
to the comparator inputs. The Comparator inputs are selected in the CPTnMX registers (SFR Definition
14.5 and SFR Definition 14.6). The CMXnP2–CMXnP0 bits select the Comparator positive input; the CMX-
nN2–CMXnN0 bits select the Comparator negative input.
Important Note About Comparator Inputs: The Port pins selected as comparator inputs should be con-
figured as analog inputs in their associated Port configuration register, and configured to be skipped by the
Crossbar (for details on Port configuration, see Section “22.6. Special Function Registers for Accessing
and Configuring Port I/O” on page 152).
CPT0MX
CPT1MX
P1.0
P1.4
P2.0
P2.4
P0.0
P1.2
P1.6
P2.2
P0.4
VDD
VDD
CP0 +
CP0 -
CP1 +
CP1 -
+
-
+
-
P1.1
P1.5
P2.1
P2.5
P0.1
P1.3
P1.7
P2.3
P0.5
GND
GND
Figure 14.4. Comparator Input Multiplexer Block Diagram
Rev. 1.2
84
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 14.5. CPT0MX: Comparator0 MUX Selection
Bit
7
6
5
4
3
2
1
0
CMX0N[2:0]
CMX0P[2:0]
Name
Type
Reset
R
0
R/W
0
R
0
R/W
0
0
0
0
0
SFR Address = 0x9F
Bit
Name
Function
7
Unused
Read = 0b; Write = don’t care.
6:4 CMX0N[2:0]
Comparator0 Negative Input MUX Selection.
000:
P1.1
001:
P1.5
010:
P2.1
011:
P2.5
100:
P0.1
101-111:
RESERVED
3
Unused
Read = 0b; Write = don’t care.
2:0 CMX0P[2:0]
Comparator0 Positive Input MUX Selection.
0000:
0001:
0010:
0011:
P1.0
P1.4
P2.0
P2.4
0100:
101–111:
P0.0
RESERVED
85
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 14.6. CPT1MX: Comparator1 MUX Selection
Bit
7
6
5
4
3
2
1
0
CMX1N[2:0]
CMX1P[2:0]
Name
Type
Reset
R
0
R/W
0
R
0
R/W
0
0
0
0
0
SFR Address = 0x9E
Bit
Name
Function
7
Unused
Read = 0b; Write = don’t care.
6:4 CMX1N[2:0]
Comparator1 Negative Input MUX Selection.
000:
P1.3
001:
P1.7
010:
P2.3
011:
RESERVED
P0.5
100:
101-111:
RESERVED
3
Unused
Read = 0b; Write = don’t care.
2:0 CMX1P[2:0]
Comparator1 Positive Input MUX Selection.
000:
P1.2
001:
P1.6
010:
P2.2
011:
RESERVED
P0.4
100:
101-111:
RESERVED
Rev. 1.2
86
C8051T620/1/6/7 & C8051T320/1/2/3
15. Memory Organization
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are
two separate memory spaces: program memory and data memory. Program and data memory share the
same address space but are accessed via different instruction types. The memory organization of the
C8051T620/1/6/7 & C8051T320/1/2/3 device family is shown in Figure 15.1
DATA MEMORY (RAM)
INTERNAL DATA ADDRESS SPACE
PROGRAM/DATA MEMORY
(EPROM)
0xFF
0x3FFF
Upper 128 RAM
(Indirect Addressing
Only)
Special Function
Register's
(Direct Addressing Only)
RESERVED
0x3E00
0x3DFF
0x80
0x7F
(Direct and Indirect
Addressing)
Lower 128 RAM
(Direct and Indirect
Addressing)
0x30
0x2F
16k Bytes EPROM
Memory
Bit Addressable
0x20
0x1F
General Purpose
Registers
0x00
0x0000
EXTERNAL DATA ADDRESS SPACE
0xFFFF
Same 1024 bytes as from
0x0000 to 0x03FF, wrapped
on 1024-byte boundaries
0x07FF
0x0400
USB FIFOs
1024 Bytes
0x0400
0x03FF
XRAM - 1024 Bytes
(accessable using MOVX
instruction)
0x0000
Figure 15.1. C8051T620/1 and C8051T320/1/2/3 Memory Map
Rev. 1.2
87
C8051T620/1/6/7 & C8051T320/1/2/3
DATA MEMORY (RAM)
INTERNAL DATA ADDRESS SPACE
PROGRAM/DATA MEMORY
(EPROM)
0xFF
Upper 128 RAM
(Indirect Addressing
Only)
Special Function
Register's
(Direct Addressing Only)
C8051T627
0xFFFF
0x80
0x7F
RESERVED
0x8000
0x7FFF
(Direct and Indirect
Addressing)
Lower 128 RAM
(Direct and Indirect
Addressing)
32k Bytes EPROM
Memory
0x30
0x2F
Bit Addressable
0x0000
0xFFFF
0x20
0x1F
General Purpose
Registers
C8051T626
RESERVED
0x00
0xFE00
0xFDFF
EXTERNAL DATA ADDRESS SPACE
64k Bytes EPROM
Memory
0xFFFF
Same 4096 bytes as from
0x0000 to 0x0FFF, wrapped
on 4096-byte boundaries,
Except when USB FIFO is
mapped to XDATA – then
0x0000
0x1FFF
0x1000
wrap occurs at 8192-byte
USB FIFOs
1024 Bytes
boundaries.
0x1000
0x0FFF
Unused - Reads back 0x00
0x0C00
0x0BFF
XRAM - 3072 Bytes
(accessable using MOVX
instruction)
0x0000
Figure 15.2. C8051T626/7 Memory Map
15.1. Program Memory
The CIP-51 core has a 64 kB program memory space. The C8051T620/1/6/7 & C8051T320/1/2/3 imple-
ments up to 65535 bytes of this program memory space as in-system byte-programmable EPROM. Refer
to Table 2.1 on page 21 or Figure 15.1 for additional details on program memory size. Figure 15.3 shows
the program memory maps for C8051T620/1/6/7 & C8051T320/1/2/3 devices.
88
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
C8051T620/1 and
C*051F320/1/2/3
C8051T627
C8051T626
0xFFFF
0xFFFC
0xFFFB
0xFFFA
0x3FFF
0x3FFC
0x3FFB
0x3FFA
0xFFFF
0xFFFC
0xFFFB
0xFFFA
Serial Number
TOFFH and TOFFL
Derivative ID
Serial Number
TOFFH and TOFFL
Derivative ID
Serial Number
TOFFH and TOFFL
Derivative ID
0xFFF9
0xFFF8
0x3FF9
0x3FF8
0xFFF9
0xFFF8
Security Byte
Reserved
Security Byte
Reserved
Security Byte
Reserved
0xFFF7
0x8000
0x7FFF
0x3FF7
0x3E00
0x3DFF
0xFFF7
0xFE00
0xFDFF
32768 Bytes
15872 Bytes
65024 Bytes
EPROM Memory
EPROM Memory
EPROM Memory
0x0000
0x0000
0x0000
Figure 15.3. Program Memory Map
Program memory is read-only from within firmware. Individual program memory bytes can be read using
the MOVC instruction. This facilitates the use of byte-programmable EPROM space for constant storage.
15.1.1. Derivative ID
To distinguish between individual derivatives in the C8051T620/1/6/7 & C8051T320/1/2/3 device family,
the Derivative ID is located at the address indicated in Figure 15.3 in EPROM memory. The Derivative ID
for the devices in the C8051T620/1/6/7 & C8051T320/1/2/3 are as follows:
Device
Derivative ID
C8051T620
C8051T621
C8051T626
C8051T627
C8051T320
C8051T321
C8051T322
C8051T323
0xD0
0xD3
0xD6
0xD7
0xD1
0xD2
0xD4
0xD5
15.1.2. Temperature Offset Calibration
The C8051T620/1/6/7 & C8051T320/1/2/3 devices include a factory calibrated temperature sensor offset
coefficient located in the EPROM memory. The TOFFH and TOFFL values are located at the address indi-
cated in Figure 15.3. More information on using the temperature sensor calibration values can be found in
Section “9.1. Calibration” on page 58.
15.1.3. Serialization
All C8051T620/1/6/7 & C8051T320/1/2/3 devices have a factory serialization located in EPROM memory.
This value is unique to each device. The serial number is located at the address indicated in Figure 15.3
and can be accessed like any constant array in program memory.
Rev. 1.2
89
C8051T620/1/6/7 & C8051T320/1/2/3
15.2. Data Memory
The C8051T620/1 and C8051T320/1/2/3 device family includes 1280 bytes of RAM data memory, while
the C8051T626/6 devices include 3328 bytes. 256 bytes of this memory is mapped into the internal RAM
space of the 8051. The remaining 1024 or 3072 bytes of this memory is on-chip "external" memory. The
data memory map is shown in Figure 15.1 and Figure 15.2 for reference.
15.2.1. Internal RAM
There are 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The
lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either
direct or indirect addressing may be used to access the lower 128 bytes of data memory. Locations 0x00
through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight
byte-wide registers. The next 16 bytes, locations 0x20 through 0x2F, may either be addressed as bytes or
as 128 bit locations accessible with the direct addressing mode.
The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the
same address space as the Special Function Registers (SFR) but is physically separate from the SFR
space. The addressing mode used by an instruction when accessing locations above 0x7F determines
whether the CPU accesses the upper 128 bytes of data memory space or the SFRs. Instructions that use
direct addressing will access the SFR space. Instructions using indirect addressing above 0x7F access the
upper 128 bytes of data memory. Figure 15.1 illustrates the data memory organization of the
C8051T620/1/6/7 & C8051T320/1/2/3.
15.2.1.1. General Purpose Registers
The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of gen-
eral-purpose registers. Each bank consists of eight byte-wide registers designated R0 through R7. Only
one of these banks may be enabled at a time. Two bits in the program status word, RS0 (PSW.3) and RS1
(PSW.4), select the active register bank (see description of the PSW in SFR Definition 12.6). This allows
fast context switching when entering subroutines and interrupt service routines. Indirect addressing modes
use registers R0 and R1 as index registers.
15.2.1.2. Bit Addressable Locations
In addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20
through 0x2F are also accessible as 128 individually addressable bits. Each bit has a bit address from
0x00 to 0x7F. Bit 0 of the byte at 0x20 has bit address 0x00 while bit7 of the byte at 0x20 has bit address
0x07. Bit 7 of the byte at 0x2F has bit address 0x7F. A bit access is distinguished from a full byte access by
the type of instruction used (bit source or destination operands as opposed to a byte source or destina-
tion).
The MCS-51™ assembly language allows an alternate notation for bit addressing of the form XX.B where
XX is the byte address and B is the bit position within the byte. For example, the instruction:
MOV
C, 22.3h
moves the Boolean value at 0x13 (bit 3 of the byte at location 0x22) into the Carry flag.
15.2.1.3. Stack
A programmer's stack can be located anywhere in the 256-byte data memory. The stack area is desig-
nated using the Stack Pointer (SP) SFR. The SP will point to the last location used. The next value pushed
on the stack is placed at SP+1 and then SP is incremented. A reset initializes the stack pointer to location
0x07. Therefore, the first value pushed on the stack is placed at location 0x08, which is also the first regis-
ter (R0) of register bank 1. Thus, if more than one register bank is to be used, the SP should be initialized
to a location in the data memory not being used for data storage. The stack depth can extend up to
256 bytes.
90
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
15.2.2. External RAM
There are 1024 bytes (C8051T620/1/320/1/2/3 devices) or 3072 bytes (C8051T626/7 devices) of on-chip
RAM mapped into the external data memory space. All of these address locations may be accessed using
the external move instruction (MOVX) and the data pointer (DPTR), or using MOVX indirect addressing
mode. If the MOVX instruction is used with an 8-bit address operand (such as @R1), then the high byte of
the 16-bit address is provided by the External Memory Interface Control Register (EMI0CN as shown in
SFR Definition 15.1).
For a 16-bit MOVX operation (@DPTR), the upper three or five bits of the 16-bit external data memory
address word are "don't cares" (when USBFAE is cleared to 0). As a result, the XRAM is mapped modulo
style over the entire 64 k external data memory address range. For example, on the C8051T620/1 the
XRAM byte at address 0x0000 is shadowed at addresses 0x0400, 0x0800, 0x0C00, 0x1000, etc. This is a
useful feature when performing a linear memory fill, as the address pointer doesn't have to be reset when
reaching the RAM block boundary.
SFR Definition 15.1. EMI0CN: External Memory Interface Control
Bit
7
6
5
4
3
2
PGSEL[4:0]
R/W
1
0
Name
Type
Reset
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
0
SFR Address = 0xAA
Bit
Name
Function
7:5
Unused
Read = 00000b; Write = Don’t Care.
4:0 PGSEL[4:0]
XRAM Page Select.
The EMI0CN register provides the high byte of the 16-bit external data memory
address when using an 8-bit MOVX command, effectively selecting a 256-byte page
of RAM. Since the upper (unused) bits of the register are always zero, the PGSEL
determines which page of XRAM is accessed.
For Example: If EMI0CN = 0x01, addresses 0x0100 through 0x01FF will be
accessed.
Note: PGSEL[4:3] are only valid on the C8051T626/7 devices.
15.2.3. Accessing USB FIFO Space
The C8051T620/1/6/7 & C8051T320/1/2/3 include 1k of RAM which functions as USB FIFO space.
Figure 15.4 shows an expanded view of the FIFO space and user XRAM. FIFO space is normally
accessed via USB FIFO registers; see Section “23.5. FIFO Management” on page 169 for more informa-
tion on accessing these FIFOs. The MOVX instruction should not be used to load or modify USB data in
the FIFO space.
Unused areas of the USB FIFO space may be used as general purpose XRAM if necessary. The FIFO
block operates on the USB clock domain; thus the USB clock must be active when accessing FIFO space.
Note that the number of SYSCLK cycles required by the MOVX instruction is increased when accessing
USB FIFO space.
To access the FIFO RAM directly using MOVX instructions, the following conditions must be met: (1) the
USBFAE bit in register EMI0CF must be set to 1, and (2) the USB clock frequency must be greater than or
Rev. 1.2
91
C8051T620/1/6/7 & C8051T320/1/2/3
equal to twice the SYSCLK (USBCLK > 2 x SYSCLK). When this bit is set, the USB FIFO space is mapped
into XRAM space at addresses 0x0400 to 0x07FF. The normal on-chip XRAM at the same addresses can-
not be accessed when the USBFAE bit is set to 1.
Important Note: The USB clock must be active when accessing FIFO space.
0xFFFF
On-Chip XRAM
0x0800
0x07FF
Endpoint0
(64 bytes)
0x07C0
0x07BF
Endpoint1
(128 bytes)
0x0740
0x073F
Endpoint2
(256 bytes)
USB FIFO Space
0x0640
(USB Clock Domain)
0x063F
Endpoint3
(512 bytes)
0x0440
0x043F
Free
(64 bytes)
0x0400
0x03FF
On-Chip XRAM
0x0000
Figure 15.4. C8051T620/1 and C8051T320/1/2/3 USB FIFO Space and
XRAM Memory Map with USBFAE Set to 1
92
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
Same 8192 bytes as
0x0000 to 0x1FFF,
wrapped at 8192-byte
boundaries
0xFFFF
0x2000
0x1FFF
USB FIFO space
repeated 3 times
0x1400
0x13FF
Endpoint0
(64 bytes)
0x13C0
0x13BF
Endpoint1
(128 bytes)
0x1340
0x133F
Endpoint2
(256 bytes)
USB FIFO Space
0x1240
0x123F
(USB Clock Domain)
Endpoint3
(512 bytes)
0x1040
0x103F
Free
(64 bytes)
0x1000
0x0FFF
On-Chip XRAM (3kB)
and 1kB empty space
0x0000
Figure 15.5. C8051T626/7 USB FIFO Space and XRAM Memory Map with USBFAE set to 1
Rev. 1.2
93
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 15.2. EMI0CF: External Memory Configuration
Bit
7
6
5
4
3
2
1
0
USBFAE
Name
Type
Reset
R
0
R/W
0
R
0
R
0
R
0
R
0
R
1
R
1
SFR Address = 0x85
Bit
Name
Function
7
6
Unused
Read = 0b; Write = Don’t Care.
USBFAE
USB FIFO Access Enable.
0: USB FIFO RAM not available through MOVX instructions.
1: USB FIFO RAM available using MOVX instructions. The 1k of USB RAM will be
mapped in XRAM space at addresses 0x0400 to 0x07FF. The USB clock must be
active and greater than or equal to twice the SYSCLK (USBCLK > 2 x SYSCLK)
to access this area with MOVX instructions.
5:0
Unused
Read = 000011b; Write = Don’t Care.
94
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
16. Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFRs). The SFRs provide control and data exchange with the C8051T620/1/6/7 & C8051T320/1/2/3's
resources and peripherals. The CIP-51 controller core duplicates the SFRs found in a typical 8051 imple-
mentation as well as implementing additional SFRs used to configure and access the sub-systems unique
to the C8051T620/1/6/7 & C8051T320/1/2/3. This allows the addition of new functionality while retaining
compatibility with the MCS-51™ instruction set. Table 16.1 lists the SFRs implemented in the
C8051T620/1/6/7 & C8051T320/1/2/3 device family.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations
from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g., P0, TCON, SCON0, IE, etc.) are bit-
addressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied
addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate
effect and should be avoided. Refer to the corresponding pages of the data sheet, as indicated in
Table 16.2, for a detailed description of each register.
Table 16.1. Special Function Register (SFR) Memory Map
F8 SPI0CN
F0
PCA0L
PCA0H PCA0CPL0 PCA0CPH0 PCA0CPL4 PCA0CPH4 VDM0CN
P1MDIN P2MDIN PCA0PWM IAPCN EIP1 EIP2
B
P0MDIN
E8 ADC0CN PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2 PCA0CPL3 PCA0CPH3 RSTSRC
E0
ACC
XBR0
XBR1
XBR2
IT01CF
SMOD1
EIE1
EIE2
-
D8 PCA0CN PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2 PCA0CPM3 PCA0CPM4
D0
PSW
REF0CN
SCON1
SBUF1
P0SKIP
TMR2L
P1SKIP
TMR2H
P2SKIP
-
USB0XCN
SMB0ADM
C8 TMR2CN REG01CN TMR2RLL TMR2RLH
C0 SMB0CN SMB0CF SMB0DAT ADC0GTL ADC0GTH ADC0LTL ADC0LTH SMB0ADR
B8
B0
A8
A0
IP
P3
IE
CLKMUL P1MASK
OSCXCN OSCICN
AMX0P
OSCICL
-
ADC0CF
SBRLL1
SBCON1
ADC0L
SBRLH1
-
ADC0H
P1MAT
-
MEMKEY
PFE0CN
CLKSEL
EMI0CN
P0MASK
P2
SPI0CFG SPI0CKR SPI0DAT P0MDOUT P1MDOUT P2MDOUT P3MDOUT
98 SCON0
90 P1
88 TCON
SBUF0
CPT1CN
CPT0CN
CPT1MD
TMR3L
TH0
CPT0MD
TMR3H
TH1
CPT1MX
CPT0MX
TMR3CN TMR3RLL TMR3RLH
USB0ADR USB0DAT
TMOD
SP
TL0
DPL
2(A)
TL1
DPH
3(B)
CKCON
OSCLCN
6(E)
PSCTL
PCON
7(F)
80
P0
P0MAT
4(C)
EMI0CF
5(D)
0(8)
1(9)
Note: SFR Addresses ending in 0x0 or 0x8 are bit-addressable locations and can be used with bitwise instructions.
Rev. 1.2
95
C8051T620/1/6/7 & C8051T320/1/2/3
Table 16.2. Special Function Registers
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
ACC
Address
Description
Page
0xE0
Accumulator
74
0xBC
0xE8
0xC4
0xC3
0xBE
0xBD
0xC6
0xC5
0xBB
0xF0
0x8E
0xB9
0xA9
0x9B
0x9D
0x9F
0x9B
0x9D
0x9F
0x83
0x82
0xE6
0xE7
0xF6
0xF7
0x85
0xAA
ADC0 Configuration
ADC0 Control
49
51
ADC0CF
ADC0CN
ADC0GTH
ADC0GTL
ADC0H
ADC0L
ADC0LTH
ADC0LTL
AMX0P
B
ADC0 Greater-Than Compare High
ADC0 Greater-Than Compare Low
ADC0 High
52
52
50
ADC0 Low
50
ADC0 Less-Than Compare Word High
ADC0 Less-Than Compare Word Low
AMUX0 Positive Channel Select
B Register
53
53
56
74
Clock Control
247
132
129
80
CKCON
CLKMUL
CLKSEL
CPT0CN
CPT0MD
CPT0MX
CPT1CN
CPT1MD
CPT1MX
DPH
Clock Multiplier Control
Clock Select
Comparator0 Control
Comparator0 Mode Selection
Comparator0 MUX Selection
Comparator1 Control
81
85
82
Comparator1 Mode Selection
Comparator1 MUX Selection
Data Pointer High
83
86
73
Data Pointer Low
73
DPL
Extended Interrupt Enable 1
Extended Interrupt Enable 2
Extended Interrupt Priority 1
Extended Interrupt Priority 2
External Memory Configuration
External Memory Interface Control
106
108
107
109
94
EIE1
EIE2
EIP1
EIP2
EMI0CF
EMI0CN
91
96
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
Table 16.2. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
IAPCN
Address
Description
Page
0xF5
In-Application Programming Control
117
0xA8
0xB8
0xE4
0xB7
0xB3
0xB2
0x86
0xB1
0x80
0xAE
0x84
0xF1
0xA4
0xD4
0x90
0xBA
0xB6
0xF2
0xA5
0xD5
0xA0
0xF3
0xA6
0xD6
0xB0
0xA7
0xD8
Interrupt Enable
104
105
111
116
130
131
133
137
152
150
150
153
153
154
154
151
151
155
155
156
156
157
157
158
158
159
282
IE
Interrupt Priority
IP
INT0/INT1 Configuration
EPROM Memory Lock and Key
Internal Oscillator Calibration
Internal Oscillator Control
Low-Frequency Oscillator Control
External Oscillator Control
Port 0 Latch
IT01CF
MEMKEY
OSCICL
OSCICN
OSCLCN
OSCXCN
P0
Port 0 Mask Configuration
Port 0 Match Configuration
Port 0 Input Mode Configuration
Port 0 Output Mode Configuration
Port 0 Skip
P0MASK
P0MAT
P0MDIN
P0MDOUT
P0SKIP
P1
Port 1 Latch
Port 1Mask Configuration
Port 1 Match Configuration
Port 1 Input Mode Configuration
Port 1 Output Mode Configuration
Port 1 Skip
P1MASK
P1MAT
P1MDIN
P1MDOUT
P1SKIP
P2
Port 2 Latch
Port 2 Input Mode Configuration
Port 2 Output Mode Configuration
Port 2 Skip
P2MDIN
P2MDOUT
P2SKIP
P3
Port 3 Latch
Port 3 Output Mode Configuration
PCA Control
P3MDOUT
PCA0CN
Rev. 1.2
97
C8051T620/1/6/7 & C8051T320/1/2/3
Table 16.2. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
PCA0CPH0
PCA0CPH1
PCA0CPH2
PCA0CPH3
PCA0CPH4
PCA0CPL0
PCA0CPL1
PCA0CPL2
PCA0CPL3
PCA0CPL4
PCA0CPM0
PCA0CPM1
PCA0CPM2
PCA0CPM3
PCA0CPM4
PCA0H
Address
Description
Page
0xFC
PCA Capture 0 High
PCA Capture 1 High
PCA Capture 2 High
PCA Capture 3 High
PCA Capture 4 High
PCA Capture 0 Low
PCA Capture 1 Low
PCA Capture 2 Low
PCA Capture 3 Low
PCA Capture 4 Low
287
0xEA
0xEC
0xEE
0xFE
0xFB
0xE9
0xEB
0xED
0xFD
0xDA
0xDB
0xDC
0xDD
0xDE
0xFA
0xF9
0xD9
0xF4
0x87
0xAF
0x8F
0xD0
0xD1
0xC9
0xEF
0xAC
0xB5
287
287
287
287
287
287
287
287
287
285
285
285
285
285
286
286
283
284
120
76
PCA Module 0 Mode Register
PCA Module 1 Mode Register
PCA Module 2 Mode Register
PCA Module 3 Mode Register
PCA Module 4 Mode Register
PCA Counter High
PCA Counter Low
PCA0L
PCA Mode
PCA0MD
PCA0PWM
PCON
PCA PWM Configuration
Power Control
Prefetch Engine Control
Program Store R/W Control
Program Status Word
PFE0CN
116
75
PSCTL
PSW
Voltage Reference Control
Voltage Regulator Control
Reset Source Configuration/Status
UART1 Baud Rate Generator Control
UART1 Baud Rate Generator High Byte
60
REF0CN
65
REG01CN
RSTSRC
126
231
231
SBCON1
SBRLH1
98
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
Table 16.2. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
SBRLL1
SBUF0
SBUF1
SCON0
SCON1
SMB0ADM
SMB0ADR
SMB0CF
SMB0CN
SMB0DAT
SMOD1
SP
Address
Description
Page
0xB4
UART1 Baud Rate Generator Low Byte
232
0x99
0xD3
0x98
0xD2
0xCF
0xC7
0xC1
0xC0
0xC2
0xE5
0x81
0xA1
0xA2
0xF8
0xA3
0x88
0x8C
0x8D
0x8A
0x8B
0x89
0xC8
0xCD
0xCC
0xCB
0xCA
0x91
UART0 Data Buffer
UART1 Data Buffer
UART0 Control
221
230
220
228
205
204
200
202
206
229
74
UART1 Control
SMBus Slave Address Mask
SMBus Slave Address
SMBus Configuration
SMBus Control
SMBus Data
UART1 Mode
Stack Pointer
SPI Configuration
240
242
241
242
252
255
255
254
254
253
259
261
260
260
260
265
SPI0CFG
SPI0CKR
SPI0CN
SPI0DAT
TCON
SPI Clock Rate Control
SPI Control
SPI Data
Timer/Counter Control
Timer/Counter 0 High
Timer/Counter 1 High
Timer/Counter 0 Low
Timer/Counter 1 Low
Timer/Counter Mode
Timer/Counter 2 Control
Timer/Counter 2 High
Timer/Counter 2 Low
Timer/Counter 2 Reload High
Timer/Counter 2 Reload Low
Timer/Counter 3Control
TH0
TH1
TL0
TL1
TMOD
TMR2CN
TMR2H
TMR2L
TMR2RLH
TMR2RLL
TMR3CN
Rev. 1.2
99
C8051T620/1/6/7 & C8051T320/1/2/3
Table 16.2. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
TMR3H
Address
Description
Page
0x95
Timer/Counter 3 High
Timer/Counter 3Low
267
0x94
0x93
0x92
0x96
0x97
0xD7
0xFF
0xE1
0xE2
0xE3
266
266
266
164
165
162
124
147
148
149
TMR3L
Timer/Counter 3 Reload High
Timer/Counter 3 Reload Low
USB0 Indirect Address
USB0 Data
TMR3RLH
TMR3RLL
USB0ADR
USB0DAT
USB0XCN
VDM0CN
XBR0
USB0 Transceiver Control
V
Monitor Control
DD
Port I/O Crossbar Control 0
Port I/O Crossbar Control 1
Port I/O Crossbar Control 2
XBR1
XBR2
100
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
17. Interrupts
The C8051T620/1/6/7 & C8051T320/1/2/3 include an extended interrupt system supporting a total of
18 interrupt sources with two priority levels. The allocation of interrupt sources between on-chip peripher-
als and external inputs pins varies according to the specific version of the device. Each interrupt source
has one or more associated interrupt-pending flag(s) located in an SFR. When a peripheral or external
source meets a valid interrupt condition, the associated interrupt-pending flag is set to logic 1.
If interrupts are enabled for the source, an interrupt request is generated when the interrupt-pending flag is
set. As soon as execution of the current instruction is complete, the CPU generates an LCALL to a prede-
termined address to begin execution of an interrupt service routine (ISR). Each ISR must end with an RETI
instruction, which returns program execution to the next instruction that would have been executed if the
interrupt request had not occurred. If interrupts are not enabled, the interrupt-pending flag is ignored by the
hardware and program execution continues as normal. (The interrupt-pending flag is set to logic 1 regard-
less of the interrupt's enable/disable state).
Each interrupt source can be individually enabled or disabled through the use of an associated interrupt
enable bit in an SFR (IE, EIE1, or EIE2). However, interrupts must first be globally enabled by setting the
EA bit (IE.7) to logic 1 before the individual interrupt enables are recognized. Setting the EA bit to logic 0
disables all interrupt sources regardless of the individual interrupt-enable settings.
Note: Any instruction that clears a bit to disable an interrupt should be immediately followed by an instruc-
tion that has two or more opcode bytes. Using EA (global interrupt enable) as an example:
// in 'C':
EA = 0; // clear EA bit.
EA = 0; // this is a dummy instruction with two-byte opcode.
; in assembly:
CLR EA ; clear EA bit.
CLR EA ; this is a dummy instruction with two-byte opcode.
For example, if an interrupt is posted during the execution phase of a "CLR EA" opcode (or any instruction
which clears a bit to disable an interrupt source), and the instruction is followed by a single-cycle instruc-
tion, the interrupt may be taken. However, a read of the enable bit will return a '0' inside the interrupt ser-
vice routine. When the bit-clearing opcode is followed by a multi-cycle instruction, the interrupt will not be
taken.
Some interrupt-pending flags are automatically cleared by the hardware when the CPU vectors to the ISR.
However, most are not cleared by the hardware and must be cleared by software before returning from the
ISR. If an interrupt-pending flag remains set after the CPU completes the return-from-interrupt (RETI)
instruction, a new interrupt request will be generated immediately and the CPU will re-enter the ISR after
the completion of the next instruction.
Rev. 1.2
101
C8051T620/1/6/7 & C8051T320/1/2/3
17.1. MCU Interrupt Sources and Vectors
The C8051T620/1/6/7 & C8051T320/1/2/3 MCUs support 18 interrupt sources. Software can simulate an
interrupt by setting any interrupt-pending flag to logic 1. If interrupts are enabled for the flag, an interrupt
request will be generated and the CPU will vector to the ISR address associated with the interrupt-pending
flag. MCU interrupt sources, associated vector addresses, priority order and control bits are summarized in
Table 17.1. Refer to the datasheet section associated with a particular on-chip peripheral for information
regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s).
17.1.1. Interrupt Priorities
Each interrupt source can be individually programmed to one of two priority levels: low or high. A low prior-
ity interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be
preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP, EIP1, or EIP2) used to
configure its priority level. Low priority is the default. If two interrupts are recognized simultaneously, the
interrupt with the higher priority is serviced first. If both interrupts have the same priority level, a fixed prior-
ity order is used to arbitrate, given in Table 17.1.
17.1.2. Interrupt Latency
Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are
sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is 6
system clock cycles: 1 clock cycle to detect the interrupt and 5 clock cycles to complete the LCALL to the
ISR. If an interrupt is pending when a RETI is executed, a single instruction is executed before an LCALL
is made to service the pending interrupt. Therefore, the maximum response time for an interrupt (when no
other interrupt is currently being serviced or the new interrupt is of greater priority) occurs when the CPU is
performing an RETI instruction followed by a DIV as the next instruction. In this case, the response time is
20 system clock cycles: 1 clock cycle to detect the interrupt, 6 clock cycles to execute the RETI, 8 clock
cycles to complete the DIV instruction and 5 clock cycles to execute the LCALL to the ISR. If the CPU is
executing an ISR for an interrupt with equal or higher priority, the new interrupt will not be serviced until the
current ISR completes, including the RETI and following instruction.
Note that the CPU is stalled during EPROM write operations and USB FIFO MOVX accesses (see Section
“15.2.3. Accessing USB FIFO Space” on page 91). Interrupt service latency will be increased for interrupts
occurring while the CPU is stalled. The latency for these situations will be determined by the standard
interrupt service procedure (as described above) and the amount of time the CPU is stalled.
17.2. Interrupt Register Descriptions
The SFRs used to enable the interrupt sources and set their priority level are described in this section.
Refer to the data sheet section associated with a particular on-chip peripheral for information regarding
valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s).
102
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
Table 17.1. Interrupt Summary
Interrupt Source
Interrupt Priority
Pending Flag
Enable
Flag
Priority
Control
Vector
Order
Reset
0x0000
0x0003
Top
0
None
N/A N/A Always
Enabled
Always
Highest
External Interrupt 0
(INT0)
IE0 (TCON.1)
Y
Y
EX0 (IE.0) PX0 (IP.0)
Timer 0 Overflow
External Interrupt 1
(INT1)
0x000B
0x0013
1
2
TF0 (TCON.5)
IE1 (TCON.3)
Y
Y
Y
Y
ET0 (IE.1) PT0 (IP.1)
EX1 (IE.2) PX1 (IP.2)
Timer 1 Overflow
UART0
0x001B
0x0023
3
4
TF1 (TCON.7)
RI0 (SCON0.0)
Y
Y
Y
N
ET1 (IE.3) PT1 (IP.3)
ES0 (IE.4) PS0 (IP.4)
TI0 (SCON0.1)
Timer 2 Overflow
SPI0
0x002B
0x0033
5
6
TF2H (TMR2CN.7)
TF2L (TMR2CN.6)
SPIF (SPI0CN.7)
WCOL (SPI0CN.6)
MODF (SPI0CN.5)
RXOVRN (SPI0CN.4)
SI (SMB0CN.0)
Y
Y
N
N
ET2 (IE.5) PT2 (IP.5)
ESPI0
(IE.6)
PSPI0
(IP.6)
SMB0
USB0
0x003B
0x0043
0x004B
0x0053
0x005B
7
8
Y
N
Y
Y
Y
N
N
N
N
N
ESMB0
(EIE1.0)
EUSB0
(EIE1.0)
PSMB0
(EIP1.0)
PUSB0
(EIP1.1)
Special
ADC0 Window Com-
pare
ADC0 Conversion
Complete
Programmable Coun-
ter Array
9
AD0WINT
(ADC0CN.3)
AD0INT (ADC0CN.5)
EWADC0 PWADC0
(EIE1.2)
EADC0
(EIE1.3)
EPCA0
(EIE1.4)
(EIP1.2)
PADC0
(EIP1.3)
PPCA0
(EIP1.4)
10
11
CF (PCA0CN.7)
CCFn (PCA0CN.n)
COVF (PCA0PWM.6)
CP0FIF (CPT0CN.4)
CP0RIF (CPT0CN.5)
CP1FIF (CPT1CN.4)
CP1RIF (CPT1CN.5)
TF3H (TMR3CN.7)
TF3L (TMR3CN.6)
N/A
Comparator0
Comparator1
Timer 3 Overflow
VBUS Level
UART1
0x0063
0x006B
0x0073
0x007B
0x0083
12
13
14
15
16
N
N
N
N
N
N
ECP0
PCP0
(EIE1.5)
ECP1
(EIP1.5)
PCP1
(EIE1.6)
ET3
(EIP1.6)
PT3
(EIE1.7)
(EIP1.7)
PVBUS
(EIP2.0)
PS1
N/A N/A EVBUS
(EIE2.0)
N
RI1 (SCON1.0)
TI1 (SCON1.1)
N/A
N
ES1
(EIE2.1)
(EIP2.1)
Reserved
Port Match
0x008B
0x0093
17
18
N/A N/A N/A
N/A N/A EMAT
(EIE2.3)
N/A N/A N/A
N/A
None
PMAT
(EIP2.3)
N/A
Reserved
19
N/A
Rev. 1.2
103
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 17.1. IE: Interrupt Enable
Bit
7
6
5
4
3
2
1
0
EA
ESPI0
ET2
ES0
ET1
EX1
ET0
EX0
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Address = 0xA8; Bit-Addressable
Bit
Name
Function
7
EA
Enable All Interrupts.
Globally enables/disables all interrupts. It overrides individual interrupt mask settings.
0: Disable all interrupt sources.
1: Enable each interrupt according to its individual mask setting.
6
5
4
3
2
1
0
ESPI0
ET2
ES0
ET1
EX1
ET0
EX0
Enable Serial Peripheral Interface (SPI0) Interrupt.
This bit sets the masking of the SPI0 interrupts.
0: Disable all SPI0 interrupts.
1: Enable interrupt requests generated by SPI0.
Enable Timer 2 Interrupt.
This bit sets the masking of the Timer 2 interrupt.
0: Disable Timer 2 interrupt.
1: Enable interrupt requests generated by the TF2L or TF2H flags.
Enable UART0 Interrupt.
This bit sets the masking of the UART0 interrupt.
0: Disable UART0 interrupt.
1: Enable UART0 interrupt.
Enable Timer 1 Interrupt.
This bit sets the masking of the Timer 1 interrupt.
0: Disable all Timer 1 interrupt.
1: Enable interrupt requests generated by the TF1 flag.
Enable External Interrupt 1.
This bit sets the masking of External Interrupt 1.
0: Disable external interrupt 1.
1: Enable interrupt requests generated by the INT1 input.
Enable Timer 0 Interrupt.
This bit sets the masking of the Timer 0 interrupt.
0: Disable all Timer 0 interrupt.
1: Enable interrupt requests generated by the TF0 flag.
Enable External Interrupt 0.
This bit sets the masking of External Interrupt 0.
0: Disable external interrupt 0.
1: Enable interrupt requests generated by the INT0 input.
104
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 17.2. IP: Interrupt Priority
Bit
7
6
5
4
3
2
1
0
PSPI0
PT2
PS0
PT1
PX1
PT0
PX0
Name
Type
Reset
R
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Address = 0xB8; Bit-Addressable
Bit
Name
Unused Read = 1b, Write = Don't Care.
Function
7
6
PSPI0
PT2
PS0
PT1
PX1
PT0
PX0
Serial Peripheral Interface (SPI0) Interrupt Priority Control.
This bit sets the priority of the SPI0 interrupt.
0: SPI0 interrupt set to low priority level.
1: SPI0 interrupt set to high priority level.
5
4
3
2
1
0
Timer 2 Interrupt Priority Control.
This bit sets the priority of the Timer 2 interrupt.
0: Timer 2 interrupt set to low priority level.
1: Timer 2 interrupt set to high priority level.
UART0 Interrupt Priority Control.
This bit sets the priority of the UART0 interrupt.
0: UART0 interrupt set to low priority level.
1: UART0 interrupt set to high priority level.
Timer 1 Interrupt Priority Control.
This bit sets the priority of the Timer 1 interrupt.
0: Timer 1 interrupt set to low priority level.
1: Timer 1 interrupt set to high priority level.
External Interrupt 1 Priority Control.
This bit sets the priority of the External Interrupt 1 interrupt.
0: External Interrupt 1 set to low priority level.
1: External Interrupt 1 set to high priority level.
Timer 0 Interrupt Priority Control.
This bit sets the priority of the Timer 0 interrupt.
0: Timer 0 interrupt set to low priority level.
1: Timer 0 interrupt set to high priority level.
External Interrupt 0 Priority Control.
This bit sets the priority of the External Interrupt 0 interrupt.
0: External Interrupt 0 set to low priority level.
1: External Interrupt 0 set to high priority level.
Rev. 1.2
105
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 17.3. EIE1: Extended Interrupt Enable 1
Bit
7
6
5
4
3
2
1
0
ET3
ECP1
ECP0
EPCA0
EADC0
EWADC0
EUSB0
ESMB0
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Address = 0xE6
Bit
Name
Function
7
ET3
Enable Timer 3 Interrupt.
This bit sets the masking of the Timer 3 interrupt.
0: Disable Timer 3 interrupts.
1: Enable interrupt requests generated by the TF3L or TF3H flags.
6
5
4
3
2
1
0
ECP1
ECP0
Enable Comparator1 (CP1) Interrupt.
This bit sets the masking of the CP1 interrupt.
0: Disable CP1 interrupts.
1: Enable interrupt requests generated by the CP1RIF or CP1FIF flags.
Enable Comparator0 (CP0) Interrupt.
This bit sets the masking of the CP0 interrupt.
0: Disable CP0 interrupts.
1: Enable interrupt requests generated by the CP0RIF or CP0FIF flags.
EPCA0
EADC0
EWADC0
EUSB0
ESMB0
Enable Programmable Counter Array (PCA0) Interrupt.
This bit sets the masking of the PCA0 interrupts.
0: Disable all PCA0 interrupts.
1: Enable interrupt requests generated by PCA0.
Enable ADC0 Conversion Complete Interrupt.
This bit sets the masking of the ADC0 Conversion Complete interrupt.
0: Disable ADC0 Conversion Complete interrupt.
1: Enable interrupt requests generated by the AD0INT flag.
Enable Window Comparison ADC0 Interrupt.
This bit sets the masking of ADC0 Window Comparison interrupt.
0: Disable ADC0 Window Comparison interrupt.
1: Enable interrupt requests generated by ADC0 Window Compare flag (AD0WINT).
Enable USB (USB0) Interrupt.
This bit sets the masking of the USB0 interrupt.
0: Disable all USB0 interrupts.
1: Enable interrupt requests generated by USB0.
Enable SMBus (SMB0) Interrupt.
This bit sets the masking of the SMB0 interrupt.
0: Disable all SMB0 interrupts.
1: Enable interrupt requests generated by SMB0.
106
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 17.4. EIP1: Extended Interrupt Priority 1
Bit
7
6
5
4
3
2
1
0
PT3
PCP1
PCP0
PPCA0
PADC0
PWADC0
PUSB0
PSMB0
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Address = 0xF6
Bit
Name
Function
7
PT3
Timer 3 Interrupt Priority Control.
This bit sets the priority of the Timer 3 interrupt.
0: Timer 3 interrupts set to low priority level.
1: Timer 3 interrupts set to high priority level.
6
5
4
3
2
1
0
PCP1
PCP0
Comparator1 (CP1) Interrupt Priority Control.
This bit sets the priority of the CP1 interrupt.
0: CP1 interrupt set to low priority level.
1: CP1 interrupt set to high priority level.
Comparator0 (CP0) Interrupt Priority Control.
This bit sets the priority of the CP0 interrupt.
0: CP0 interrupt set to low priority level.
1: CP0 interrupt set to high priority level.
PPCA0
PADC0
PWADC0
PUSB0
PSMB0
Programmable Counter Array (PCA0) Interrupt Priority Control.
This bit sets the priority of the PCA0 interrupt.
0: PCA0 interrupt set to low priority level.
1: PCA0 interrupt set to high priority level.
ADC0 Conversion Complete Interrupt Priority Control.
This bit sets the priority of the ADC0 Conversion Complete interrupt.
0: ADC0 Conversion Complete interrupt set to low priority level.
1: ADC0 Conversion Complete interrupt set to high priority level.
ADC0 Window Comparator Interrupt Priority Control.
This bit sets the priority of the ADC0 Window interrupt.
0: ADC0 Window interrupt set to low priority level.
1: ADC0 Window interrupt set to high priority level.
USB (USB0) Interrupt Priority Control.
This bit sets the priority of the USB0 interrupt.
0: USB0 interrupt set to low priority level.
1: USB0 interrupt set to high priority level.
SMBus (SMB0) Interrupt Priority Control.
This bit sets the priority of the SMB0 interrupt.
0: SMB0 interrupt set to low priority level.
1: SMB0 interrupt set to high priority level.
Rev. 1.2
107
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 17.5. EIE2: Extended Interrupt Enable 2
Bit
7
6
5
4
Reserved
R/W
3
EMAT
R/W
0
2
Reserved
R/W
1
0
EVBUS
R/W
0
Name
Type
Reset
ES1
R/W
0
R/W
0
R/W
0
R/W
0
0
0
SFR Address = 0xE7
Bit
Name
Function
7:3
4
Unused Read = 0000b, Write = Don't Care.
Reserved Must write 0b.
3
EMAT
Enable Port Match Interrupts.
This bit sets the masking of the Port Match Event interrupt.
0: Disable all Port Match interrupts.
1: Enable interrupt requests generated by a Port Match.
2
1
Reserved Must write 0b.
ES1
Enable UART1 Interrupt.
This bit sets the masking of the UART1 interrupt.
0: Disable UART1 interrupt.
1: Enable UART1 interrupt.
0
EVBUS
Enable VBUS Level Interrupt.
This bit sets the masking of the VBUS interrupt.
0: Disable all VBUS interrupts.
1: Enable interrupt requests generated by VBUS level sense.
108
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 17.6. EIP2: Extended Interrupt Priority 2
Bit
7
6
5
4
Reserved
R/W
3
PMAT
R/W
0
2
Reserved
R/W
1
0
PVBUS
R/W
0
Name
Type
Reset
PS1
R/W
0
R
0
R
0
R
0
0
0
SFR Address = 0xF7
Bit
Name
Function
7:5
4
Unused Read = 0000b, Write = Don't Care.
Reserved Must Write 0b.
3
PMAT
Port Match Interrupt Priority Control.
This bit sets the priority of the Port Match Event interrupt.
0: Port Match interrupt set to low priority level.
1: Port Match interrupt set to high priority level.
2
1
Reserved Must Write 0b.
PS1
UART1 Interrupt Priority Control.
This bit sets the priority of the UART1 interrupt.
0: UART1 interrupt set to low priority level.
1: UART1 interrupt set to high priority level.
0
PVBUS
VBUS Level Interrupt Priority Control.
This bit sets the priority of the VBUS interrupt.
0: VBUS interrupt set to low priority level.
1: VBUS interrupt set to high priority level.
Rev. 1.2
109
C8051T620/1/6/7 & C8051T320/1/2/3
17.3. INT0 and INT1 External Interrupt Sources
The INT0 and INT1 external interrupt sources are configurable as active high or low, edge or level sensi-
tive. The IN0PL (INT0 Polarity) and IN1PL (INT1 Polarity) bits in the IT01CF register select active high or
active low; the IT0 and IT1 bits in TCON (Section “28.1. Timer 0 and Timer 1” on page 248) select level or
edge sensitive. The table below lists the possible configurations.
IT0
IN0PL INT0 Interrupt
IT1
IN1PL INT1 Interrupt
1
1
0
0
0
1
0
1
Active low, edge sensitive
1
1
0
0
0
1
0
1
Active low, edge sensitive
Active high, edge sensitive
Active low, level sensitive
Active high, level sensitive
Active high, edge sensitive
Active low, level sensitive
Active high, level sensitive
INT0 and INT1 are assigned to Port pins as defined in the IT01CF register (see SFR Definition 17.7). Note
that INT0 and INT0 Port pin assignments are independent of any Crossbar assignments. INT0 and INT1
will monitor their assigned Port pins without disturbing the peripheral that was assigned the Port pin via the
Crossbar. To assign a Port pin only to INT0 and/or INT1, configure the Crossbar to skip the selected pin(s).
This is accomplished by setting the associated bit in register PnSKIP (see Section “22.3. Priority Crossbar
Decoder” on page 142 for complete details on configuring the Crossbar).
IE0 (TCON.1) and IE1 (TCON.3) serve as the interrupt-pending flags for the INT0 and INT1 external inter-
rupts, respectively. If an INT0 or INT1 external interrupt is configured as edge-sensitive, the corresponding
interrupt-pending flag is automatically cleared by the hardware when the CPU vectors to the ISR. When
configured as level sensitive, the interrupt-pending flag remains logic 1 while the input is active as defined
by the corresponding polarity bit (IN0PL or IN1PL); the flag remains logic 0 while the input is inactive. The
external interrupt source must hold the input active until the interrupt request is recognized. It must then
deactivate the interrupt request before execution of the ISR completes or another interrupt request will be
generated.
110
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 17.7. IT01CF: INT0/INT1 ConfigurationO
Bit
7
6
5
4
3
2
1
0
IN1PL
IN1SL[2:0]
IN0PL
IN0SL[2:0]
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
0
0
0
1
SFR Address = 0xE4
Bit
Name
Function
7
IN1PL
INT1 Polarity.
0: INT1 input is active low.
1: INT1 input is active high.
6:4 IN1SL[2:0]
INT1 Port Pin Selection Bits.
These bits select which Port pin is assigned to INT1. Note that this pin assignment is
independent of the Crossbar; INT1 will monitor the assigned Port pin without disturb-
ing the peripheral that has been assigned the Port pin via the Crossbar. The Crossbar
will not assign the Port pin to a peripheral if it is configured to skip the selected pin.
000: Select P0.0
001: Select P0.1
010: Select P0.2
011: Select P0.3
100: Select P0.4
101: Select P0.5
110: Select P0.6
111: Select P0.7
3
IN0PL
INT0 Polarity.
0: INT0 input is active low.
1: INT0 input is active high.
2:0 IN0SL[2:0]
INT0 Port Pin Selection Bits.
These bits select which Port pin is assigned to INT0. Note that this pin assignment is
independent of the Crossbar; INT0 will monitor the assigned Port pin without disturb-
ing the peripheral that has been assigned the Port pin via the Crossbar. The Crossbar
will not assign the Port pin to a peripheral if it is configured to skip the selected pin.
000: Select P0.0
001: Select P0.1
010: Select P0.2
011: Select P0.3
100: Select P0.4
101: Select P0.5
110: Select P0.6
111: Select P0.7
Rev. 1.2
111
C8051T620/1/6/7 & C8051T320/1/2/3
18. Program Memory (EPROM)
C8051T620/1/6/7 & C8051T320/1/2/3 devices include 64, 32, or 16 kB of on-chip byte-programmable
EPROM for program code storage. The EPROM memory can be programmed via the C2 debug and pro-
gramming interface when a special programming voltage is applied to the V pin. Additionally, EPROM
PP
bytes can be programmed in system using an external capacitor on the V pin. Each location in EPROM
PP
memory is programmable only once (i.e. non-erasable). Table 7.6 on page 38 shows the EPROM specifi-
cations.
18.1. Programming the EPROM Memory
18.1.1. EPROM Programming over the C2 Interface
Programming of the EPROM memory is accomplished through the C2 programming and debug interface.
When creating hardware to program the EPROM, it is necessary to follow the programming steps listed
below. Please refer to the “C2 Interface Specification” available at http://www.silabs.com for details on
communicating via the C2 interface. Section “30. C2 Interface” on page 288 has information about C2 reg-
ister addresses for the C8051T620/1/6/7 & C8051T320/1/2/3.
1. Reset the device using the RST pin.
2. Wait at least 20 ms before sending the first C2 command.
3. Place the device in core reset: Write 0x04 to the DEVCTL register.
4. Set the device to program mode (1st step): Write 0x40 to the EPCTL register.
5. Set the device to program mode (2nd step): Write 0x4A to the EPCTL register.
Note: Devices with a Date Code prior to 1040 should write 0x58 to the EPCTL register.
6. Apply the V programming Voltage.
PP
7. Write the first EPROM address for programming to EPADDRH and EPADDRL.
8. Write a data byte to EPDAT. EPADDRH:L will increment by 1 after this write.
9. Poll the EPBusy bit using a C2 Address Read command. Note: If EPError is set at this time, the write
operation failed.
10.If programming is not finished, return to Step 8 to write the next address in sequence, or return to
Step 7 to program a new address.
11. Remove the V programming Voltage.
PP
12.Remove program mode (1st step): Write 0x40 to the EPCTL register.
13.Remove program mode (2nd step): Write 0x00 to the EPCTL register.
14.Reset the device: Write 0x02 and then 0x00 to the DEVCTL register.
Important Note 1: There is a finite amount of time which V can be applied without damaging the device,
PP
which is cumulative over the life of the device. Refer to Table 7.1 on page 34 for the V timing specifica-
PP
tion.
Rev. 1.2
112
C8051T620/1/6/7 & C8051T320/1/2/3
18.1.2. EPROM In-Application Programming
The EPROM of the C8051T620/1/6/7 & C8051T320/1/2/3 devices has an In-Application Programming
option. In-Application Programming will be much slower than normal programming where the V pro-
PP
gramming voltage is applied to the V pin, but it allows a small number of bytes to be programmed any-
PP
where in the non-reserved areas of the EPROM. In order to use this option, V must be within a specific
IO
range and a capacitor must be connected externally to the V pin. Refer to Section “7. Electrical Charac-
PP
teristics” on page 34 for the acceptable range of values for V and the capacitor on the V pin.
IO
PP
Bytes in the EPROM memory must be written one byte at a time. An EPROM write will be performed after
each MOVX write instruction. The recommended procedure for writing to the EPROM is as follows:
1. Disable interrupts.
2. Change the core clock to 25 MHz or less.
3. Enable the VDD Monitor. Write 0x80 to VDM0CN.
4. Enable the VDD Monitor as a reset source. Write 0x02 to RSTSRC.
5. Disable the Prefetch engine. Write 0x00 to the PFE0CN register.
6. Set the VPP Pin to an open-drain configuration, with a ‘1’ in the port latch.
7. Set the PSWE bit (register PSCTL).
8. Write the first key code to MEMKEY: 0xA5.
9. Write the second key code to MEMKEY: 0xF1.
10.Enable in-application programming. Write 0x80 to the IAPCN register.
11.Using a MOVX write instruction, write a single data byte to the desired location.
12.Disable in-application EPROM programming. Write 0x00 to the IAPCN register.
13.Clear the PSWE bit.
14.Re-enable the Prefetch engine. Write 0x20 to the PFE0CN register.
15.Delay for at least 1 us.
16.Disable the programming hardware. Write 0x40 to the IAPCN register.
17.Restore the core clock (if changed in Step 2)
18.Re-enable interrupts.
Steps 8–11 must be repeated for each byte to be written.
When an application uses the In-Application Programming feature, the V pin must be set to open-drain
PP
mode, with a ‘1’ in the port latch. The pin can still be used a as a general-purpose I/O pin if the program-
ming circuitry of the pin is disabled after all writes are completed by using the IAPHWD bit in the IAPCN
register (IAPCN.6). It is not necessary to disable the programming hardware if the In-Application Program-
ming feature has not been used.
Important Note: Software should delay for at least 1 µs after the last EPROM write before setting the
IAPHWD bit.
113
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
18.2. Security Options
The C8051T620/1/6/7 & C8051T320/1/2/3 devices provide security options to prevent unauthorized view-
ing of proprietary program code and constants. A security byte stored in the EPROM address space can
be used to lock the program memory from being read or written across the C2 interface. On the
C8051T626/7 devices, the security byte is located at address 0xFFF8. On the C8051T620/1 and
C8051T320/1/2/3, the security byte is located at address 0x3FF8. The lock byte can always be read
regardless of the security settings. Table 18.1 shows the security byte decoding. Refer to
“Figure 15.3. Program Memory Map” on page 89 for the location of the security byte in EPROM memory.
Important Note: Once the security byte has been written, there are no means of unlocking the device.
Locking memory from write access should be performed only after all other code has been successfully
programmed to memory.
Table 18.1. Security Byte Decoding
Bits
Description
7–4
Write Lock: Clearing any of these bits to logic 0 prevents all code
memory from being written across the C2 interface.
3–0
Read Lock: Clearing any of these bits to logic 0 prevents all code
memory from being read across the C2 interface.
18.3. EPROM Writing Guidelines
Any system which contains routines which write EPROM memory from software involves some risk that
the write routines will execute unintentionally if the CPU is operating outside its specified operating range
of V , system clock frequency, or temperature. This accidental execution of EPROM modifying code can
DD
result in alteration of EPROM memory contents causing a system failure.
The following guidelines are recommended for any system which contains routines which write EPROM
memory from code.
18.3.1. VDD Maintenance and the VDD monitor
1. If the system power supply is subject to voltage or current "spikes," add sufficient transient protection
devices to the power supply to ensure that the supply voltages listed in the Absolute Maximum Ratings
table are not exceeded.
2. Make certain that the minimum V rise time specification of 1 ms is met. If the system cannot meet
DD
this rise time specification, then add an external V brownout circuit to the RST pin of the device that
DD
holds the device in reset until V reaches V
and re-asserts RST if V drops below V
.
DD
RST
DD
RST
3. Enable the on-chip V monitor and enable the V monitor as a reset source as early in code as
DD
DD
possible. This should be the first set of instructions executed after the Reset Vector. For 'C'-based
systems, this will involve modifying the startup code added by the 'C' compiler. See your compiler
documentation for more details. Make certain that there are no delays in software between enabling the
V
monitor and enabling the V monitor as a reset source. Note: Both the VDD Monitor and the VDD
DD
DD
Monitor reset source must be enabled to write the EPROM without generating an EPROM Error Device
Reset.
4. As an added precaution, explicitly enable the V monitor and enable the V monitor as a reset
DD
DD
source inside the functions that write EPROM memory. The V monitor enable instructions should be
DD
placed just after the instruction to set PSWE to a 1, but before the EPROM write operation instruction.
5. Make certain that all writes to the RSTSRC (Reset Sources) register use direct assignment operators
and explicitly DO NOT use the bit-wise operators (such as AND or OR). For example,"RSTSRC =
0x02" is correct. "RSTSRC |= 0x02" is incorrect.
Rev. 1.2
114
C8051T620/1/6/7 & C8051T320/1/2/3
6. Make certain that all writes to the RSTSRC register explicitly set the PORSF bit to a 1. Areas to check
are initialization code which enables other reset sources, such as the Missing Clock Detector, for
example, and instructions which force a Software Reset. A global search on "RSTSRC" can quickly
verify this.
18.3.2. PSWE Maintenance
7. Reduce the number of places in code where the PSWE bit (PSCTL.0) is set to a 1. There should be
exactly one routine in code that sets PSWE to a 1 to write EPROM bytes.
8. Minimize the number of variable accesses while PSWE is set to a 1. Handle pointer address updates
and loop variable maintenance outside the "PSWE = 1;... PSWE = 0;" area.
9. Disable interrupts prior to setting PSWE to a '1' and leave them disabled until after PSWE has been
reset to '0'. Any interrupts posted during the EPROM write operation will be serviced in priority order
after the EPROM operation has been completed and interrupts have been re-enabled by software.
10.Make certain that the EPROM write pointer variables are not located in XRAM. See your compiler
documentation for instructions regarding how to explicitly locate variables in different memory areas.
11.Add address bounds checking to the routines that write EPROM memory to ensure that a routine called
with an illegal address does not result in modification of the EPROM.
18.3.3. System Clock
12.If operating from an external crystal, be advised that crystal performance is susceptible to electrical
interference and is sensitive to layout and to changes in temperature. If the system is operating in an
electrically noisy environment, use the internal oscillator or an external CMOS clock.
13.If operating from the external oscillator, switch to the internal oscillator during EPROM write operations.
The external oscillator can continue to run, and the CPU can switch back to the external oscillator after
the EPROM operation has completed.
18.4. Program Memory CRC
A CRC engine is included on-chip which provides a means of verifying EPROM contents once the device
has been programmed. The CRC engine is available for EPROM verification even if the device is fully read
and write locked, allowing for verification of code contents at any time.
The CRC engine is operated through the C2 debug and programming interface, and performs 16-bit CRCs
on individual 256-Byte blocks of program memory, or a 32-bit CRC on the entire memory space. To prevent
hacking and extrapolation of security-locked source code, the CRC engine will only allow CRCs to be per-
formed on contiguous 256-Byte blocks beginning on 256-Byte boundaries (lowest 8-bits of address are
0x00). For example, the CRC engine can perform a CRC for locations 0x0400 through 0x04FF, but it can-
not perform a CRC for locations 0x0401 through 0x0500, or on block sizes smaller or larger than 256
Bytes.
18.4.1. Performing 32-bit CRCs on Full EPROM Content
A 32-bit CRC on the entire EPROM space is initiated by writing to the CRC1 byte over the C2 interface.
The CRC calculation begins at address 0x0000, and ends at the end of user EPROM space. The EPBusy
bit in register C2ADD will be set during the CRC operation, and cleared once the operation is complete.
The 32-bit results will be available in the CRC3-0 registers. CRC3 is the MSB, and CRC0 is the LSB. The
polynomial used for the 32-bit CRC calculation is 0x04C11DB7. Note: If a 16-bit CRC has been performed
since the last device reset, a device reset should be initiated before performing a 32-bit CRC operation.
18.4.2. Performing 16-bit CRCs on 256-Byte EPROM Blocks
A 16-bit CRC of individual 256-byte blocks of EPROM can be initiated by writing to the CRC0 byte over the
C2 interface. The value written to CRC0 is the high byte of the beginning address for the CRC. For exam-
ple, if CRC0 is written to 0x02, the CRC will be performed on the 256-bytes beginning at address 0x0200,
and ending at address 0x2FF. The EPBusy bit in register C2ADD will be set during the CRC operation, and
cleared once the operation is complete. The 16-bit results will be available in the CRC1-0 registers. CRC1
is the MSB, and CRC0 is the LSB. The polynomial for the 16-bit CRC calculation is 0x1021.
115
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 18.1. PSCTL: Program Store R/W Control
Bit
7
6
5
4
3
2
1
0
PSWE
Name
Type
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
SFR Address = 0x8F
Bit Name
7:1 Unused Read = 0000000b. Write = don’t care.
PSWE
Function
0
Program Store Write Enable.
Setting this bit allows writing a byte of data to the EPROM program memory using the
MOVX write instruction.
0: Writes to EPROM program memory disabled.
1: Writes to EPROM program memory enabled; the MOVX write instruction targets
EPROM memory.
SFR Definition 18.2. MEMKEY: EPROM Memory Lock and Key
Bit
7
6
5
4
3
2
1
0
MEMKEY[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xB7
Bit Name
7:0 MEMKEY[7:0]
Function
EPROM Lock and Key Register.
Write:
This register provides a lock and key function for EPROM writes. EPROM writes are
enabled by writing 0xA5 followed by 0xF1 to the MEMKEY register. EPROM writes
are automatically disabled after the next write is complete. If any writes to MEMKEY
are performed incorrectly, or if a EPROM write operation is attempted while these
operations are disabled, the EPROM will be permanently locked from writes until the
next device reset. If an application never writes to EPROM, it can intentionally lock
the EPROM by writing a non-0xA5 value to MEMKEY from software.
Read:
When read, bits 1–0 indicate the current EPROM lock state.
00: EPROM is write locked.
01: The first key code has been written (0xA5).
10: EPROM is unlocked (writes allowed).
11: EPROM writes disabled until the next reset.
Rev. 1.2
116
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 18.3. IAPCN: In-Application Programming Control
Bit
7
6
5
4
3
2
1
0
IAPEN
IAPDISD
Name
Type
Reset
R/W
0
R/W
0
R
0
R
0
R
0
R
0
R
0
R
0
SFR Address = 0xF5
Bit
Name
Function
7
IAPEN
In-Application Programming Enable.
0: In-Application Programming is disabled.
1: In-Application Programming is enabled.
6
IAPHWD
Unused
In-Application Programming Hardware Disable.
This bit disables the In-Application Programming hardware so the V programming
pin can be used as a normal GPIO pin.
Note: This bit should not be set less than 1 µs after the last EPROM write.
0: In-Application Programming discharge hardware enabled.
1: In-Application Programming discharge hardware disabled.
PP
5:0
Read = 000000b. Write = don’t care.
117
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
19. Power Management Modes
The C8051T620/1/6/7 & C8051T320/1/2/3 devices have three software programmable power manage-
ment modes: Idle, Stop, and Suspend. Idle mode and stop mode are part of the standard 8051 architec-
ture, while suspend mode is an enhanced power-saving mode implemented by the high-speed oscillator
peripheral.
Idle mode halts the CPU while leaving the peripherals and clocks active. In stop mode, the CPU is halted,
all interrupts and timers (except the Missing Clock Detector) are inactive, and the internal oscillator is
stopped (analog peripherals remain in their selected states; the external oscillator is not affected). Sus-
pend mode is similar to stop mode in that the internal oscillator is halted, but the device can wake on
events such as a Port Mismatch, Timer 3 overflow, or activity with the USB transceiver. Additionally, the
CPU is not halted in suspend mode, so it can run on another oscillator, if desired. Since clocks are running
in Idle mode, power consumption is dependent upon the system clock frequency and the number of
peripherals left in active mode before entering Idle. Stop mode and suspend mode consume the least
power because the majority of the device is shut down with no clocks active. SFR Definition 19.1 describes
the Power Control Register (PCON) used to control the C8051T620/1/6/7 & C8051T320/1/2/3's Stop and
Idle power management modes. Suspend mode is controlled by the SUSPEND bit in the OSCICN register
(SFR Definition 21.3).
Although the C8051T620/1/6/7 & C8051T320/1/2/3 has Idle, Stop, and suspend modes available, more
control over the device power can be achieved by enabling/disabling individual peripherals as needed.
Each analog peripheral can be disabled when not in use and placed in low power mode. Digital peripher-
als, such as timers or serial buses, draw little power when they are not in use. Turning off oscillators lowers
power consumption considerably, at the expense of reduced functionality.
19.1. Idle Mode
Setting the Idle Mode Select bit (PCON.0) causes the hardware to halt the CPU and enter Idle mode as
soon as the instruction that sets the bit completes execution. All internal registers and memory maintain
their original data. All analog and digital peripherals can remain active during idle mode.
Idle mode is terminated when an enabled interrupt is asserted or a reset occurs. The assertion of an
enabled interrupt will cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU to resume
operation. The pending interrupt will be serviced and the next instruction to be executed after the return
from interrupt (RETI) will be the instruction immediately following the one that set the Idle Mode Select bit.
If Idle mode is terminated by an internal or external reset, the CIP-51 performs a normal reset sequence
and begins program execution at address 0x0000.
Note: If the instruction following the write of the IDLE bit is a single-byte instruction and an interrupt occurs
during the execution phase of the instruction that sets the IDLE bit, the CPU may not wake from Idle mode
when a future interrupt occurs. Therefore, instructions that set the IDLE bit should be followed by an
instruction that has two or more opcode bytes, for example:
// in ‘C’:
PCON |= 0x01;
PCON = PCON;
// set IDLE bit
// ... followed by a 3-cycle dummy instruction
; in assembly:
ORL PCON, #01h
MOV PCON, PCON
; set IDLE bit
; ... followed by a 3-cycle dummy instruction
If enabled, the Watchdog Timer (WDT) will eventually cause an internal watchdog reset and thereby termi-
nate the Idle mode. This feature protects the system from an unintended permanent shutdown in the event
of an inadvertent write to the PCON register. If this behavior is not desired, the WDT may be disabled by
software prior to entering the Idle mode if the WDT was initially configured to allow this operation. This pro-
Rev. 1.2
118
C8051T620/1/6/7 & C8051T320/1/2/3
vides the opportunity for additional power savings, allowing the system to remain in the Idle mode indefi-
nitely, waiting for an external stimulus to wake up the system. Refer to Section “20.6. PCA Watchdog Timer
Reset” on page 125 for more information on the use and configuration of the WDT.
19.2. Stop Mode
Setting the stop mode Select bit (PCON.1) causes the controller core to enter stop mode as soon as the
instruction that sets the bit completes execution. In stop mode the internal oscillator, CPU, and all digital
peripherals are stopped; the state of the external oscillator circuit is not affected. Each analog peripheral
(including the external oscillator circuit) may be shut down individually prior to entering stop mode. Stop
mode can only be terminated by an internal or external reset. On reset, the device performs the normal
reset sequence and begins program execution at address 0x0000.
If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the stop mode.
The Missing Clock Detector should be disabled if the CPU is to be put to in STOP mode for longer than the
MCD timeout.
By default, when in stop mode the internal regulator is still active. However, the regulator can be config-
ured to shut down while in stop mode to save power. To shut down the regulator in stop mode, the
STOPCF bit in register REG01CN should be set to 1 prior to setting the STOP bit (see SFR Definition
11.1). If the regulator is shut down using the STOPCF bit, only the RST pin or a full power cycle are capa-
ble of resetting the device.
19.3. Suspend Mode
Setting the SUSPEND bit (OSCICN.5) causes the hardware to halt the high-frequency internal oscillator
and go into suspend mode as soon as the instruction that sets the bit completes execution. All internal reg-
isters and memory maintain their original data. The CPU is not halted in Suspend, so code can still be exe-
cuted using an oscillator other than the internal High Frequency Oscillator. Most digital peripherals are not
active in suspend mode. The exception to this are the USB0 Transceiver, Port Match feature, and Timer 3,
when it is run from an external oscillator source or the internal low-frequency oscillator.
Suspend mode can be terminated by four types of events: a port match (described in Section “22.5. Port
Match” on page 149), a Timer 3 overflow (described in Section “28.3. Timer 3” on page 262), resume sig-
nalling on the USB data pins, or a device reset event. Note that in order to run Timer 3 in suspend mode,
the timer must be configured to clock from either the external clock source or the internal low-frequency
oscillator source. When suspend mode is terminated, the device will continue execution on the instruction
following the one that set the SUSPEND bit. If the wake event (USB0 resume signalling, port match, or
Timer 3 overflow) was configured to generate an interrupt, the interrupt will be serviced upon waking the
device. If suspend mode is terminated by an internal or external reset, the CIP-51 performs a normal reset
sequence and begins program execution at address 0x0000.
119
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 19.1. PCON: Power Control
Bit
7
6
5
4
3
2
1
0
GF[5:0]
R/W
STOP
IDLE
Name
Type
Reset
R/W
0
R/W
0
0
0
0
0
0
0
SFR Address = 0x87
Bit
Name
Function
7:2
GF[5:0]
General Purpose Flags 5–0.
These are general purpose flags for use under software control.
1
0
STOP
IDLE
Stop Mode Select.
Setting this bit will place the CIP-51 in stop mode. This bit will always be read as 0.
1: CPU goes into stop mode (internal oscillator stopped).
IDLE: Idle Mode Select.
Setting this bit will place the CIP-51 in Idle mode. This bit will always be read as 0.
1: CPU goes into Idle mode. (Shuts off clock to CPU, but clock to Timers, Interrupts,
Serial Ports, and Analog Peripherals are still active.)
Rev. 1.2
120
C8051T620/1/6/7 & C8051T320/1/2/3
20. Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this
reset state, the following occur:
CIP-51 halts program execution
Special Function Registers (SFRs) are initialized to their defined reset values
External Port pins are forced to a known state
Interrupts and timers are disabled.
All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal
data memory are unaffected during a reset; any previously stored data is preserved. However, since the
stack pointer SFR is reset, the stack is effectively lost, even though the data on the stack is not altered.
The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pullups are enabled
during and after the reset. For V Monitor and power-on resets, the RST pin is driven low until the device
DD
exits the reset state.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the inter-
nal oscillator. The Watchdog Timer is enabled with the system clock divided by 12 as its clock source. Pro-
gram execution begins at location 0x0000.
VDD
Power On
Reset
Supply
Monitor
+
-
'0'
RST
Enable
Comparator 0
(wired-OR)
Px.x
Px.x
+
-
C0RSEF
Missing
Clock
Detector
(one-
shot)
Reset
Funnel
PCA
WDT
(Software Reset)
SWRSF
EN
EN
Errant OTP
Operation
Low
Frequency
Oscillator
Internal
Oscillator
System
Clock
CIP-51
Microcontroller
Core
System Reset
External
Oscillator
Drive
EXTCLK
Clock Select
Extended Interrupt
Handler
Figure 20.1. Reset Sources
Rev. 1.2
121
C8051T620/1/6/7 & C8051T320/1/2/3
20.1. Power-On Reset
During power-up, the device is held in a reset state and the RST pin is driven low until V settles above
DD
V
. A delay occurs before the device is released from reset; the delay decreases as the V ramp time
DD
RST
increases (V
ramp time is defined as how fast V
ramps from 0 V to V ). Figure 20.2. plots the
RST
DD
DD
power-on and V
monitor event timing. The maximum V
ramp time is 1 ms; slower ramp times may
DD
DD
cause the device to be released from reset before V reaches the V
level. For ramp times less than
DD
RST
1 ms, the power-on reset delay (T
) is typically less than 0.3 ms.
PORDelay
On exit from a power-on or V monitor reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1.
DD
When PORSF is set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is
cleared by all other resets). Since all resets cause program execution to begin at the same location
(0x0000) software can read the PORSF flag to determine if a power-up was the cause of reset. The con-
tent of internal data memory should be assumed to be undefined after a power-on reset. The V monitor
DD
is enabled following a power-on reset.
VDD
VRST
t
RST
Logic HIGH
TPORDelay
Logic LOW
VDD
Power-On
Reset
Monitor
Reset
Figure 20.2. Power-On and VDD Monitor Reset Timing
20.2. Power-Fail Reset / V Monitor
DD
When a power-down transition or power irregularity causes V
to drop below V , the power supply
RST
DD
monitor will drive the RST pin low and hold the CIP-51 in a reset state (see Figure 20.2). When V returns
DD
to a level above V
, the CIP-51 will be released from the reset state. Note that even though internal data
RST
memory contents are not altered by the power-fail reset, it is impossible to determine if V dropped below
DD
122
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
the level required for data retention. If the PORSF flag reads 1, the data may no longer be valid. The V
DD
monitor is enabled after power-on resets. Its defined state (enabled/disabled) is not altered by any other
reset source. For example, if the V monitor is disabled by code and a software reset is performed, the
DD
V
monitor will still be disabled after the reset.
DD
Important Note: If the V monitor is being turned on from a disabled state, it should be enabled before it
DD
is selected as a reset source. Selecting the V monitor as a reset source before it is enabled and stabi-
DD
lized may cause a system reset. In some applications, this reset may be undesirable. If this is not desirable
in the application, a delay should be introduced between enabling the monitor and selecting it as a reset
source. The procedure for enabling the V monitor and configuring it as a reset source from a disabled
DD
state is shown below:
1. Enable the V monitor (VDMEN bit in VDM0CN = 1).
DD
2. If necessary, wait for the V monitor to stabilize (see Table 7.4 for the V Monitor turn-on time).
DD
DD
3. Select the V monitor as a reset source (PORSF bit in RSTSRC = 1).
DD
See Figure 20.2 for V
monitor timing; note that the power-on-reset delay is not incurred after a V
DD
DD
monitor reset. See Table 7.4 for complete electrical characteristics of the V monitor.
DD
Rev. 1.2
123
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 20.1. VDM0CN: V Monitor Control
DD
Bit
7
6
5
4
3
2
1
0
VDMEN VDDSTAT
Name
Type
Reset
R/W
R
R
R
R
R
R
R
Varies
Varies
Varies
Varies
Varies
Varies
Varies
Varies
SFR Address = 0xFF
Bit
Name
Function
7
VDMEN
V
Monitor Enable.
DD
This bit turns the V monitor circuit on/off. The V Monitor cannot generate sys-
DD
DD
tem resets until it is also selected as a reset source in register RSTSRC (SFR Defi-
nition 20.2). Selecting the V monitor as a reset source before it has stabilized
DD
may generate a system reset. In systems where this reset would be undesirable, a
delay should be introduced between enabling the V Monitor and selecting it as a
DD
reset source. See Table 7.4 for the minimum V Monitor turn-on time.
DD
0: V Monitor Disabled.
DD
1: V Monitor Enabled.
DD
6
VDDSTAT
Unused
V
Status.
DD
This bit indicates the current power supply status (V Monitor output).
0: V is at or below the V monitor threshold.
1: V is above the V monitor threshold.
DD
DD
DD
DD
DD
5:0
Read = Varies; Write = Don’t care.
20.3. External Reset
The external RST pin provides a means for external circuitry to force the device into a reset state. Assert-
ing an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST
pin may be necessary to avoid erroneous noise-induced resets. See Table 7.4 for complete RST pin spec-
ifications. The PINRSF flag (RSTSRC.0) is set on exit from an external reset.
20.4. Missing Clock Detector Reset
The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system
clock remains high or low for more than the MCD time-out, a reset will be generated. After a MCD reset,
the MCDRSF flag (RSTSRC.2) will read 1, signifying the MCD as the reset source; otherwise, this bit reads
0. Writing a 1 to the MCDRSF bit enables the Missing Clock Detector; writing a 0 disables it. The state of
the RST pin is unaffected by this reset.
20.5. Comparator0 Reset
Comparator0 can be configured as a reset source by writing a 1 to the C0RSEF flag (RSTSRC.5). Com-
parator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on chatter
on the output from generating an unwanted reset. The Comparator0 reset is active-low: if the non-inverting
input voltage (on CP0+) is less than the inverting input voltage (on CP0-), the device is put into the reset
state. After a Comparator0 reset, the C0RSEF flag (RSTSRC.5) will read 1 signifying Comparator0 as the
reset source; otherwise, this bit reads 0. The state of the RST pin is unaffected by this reset.
124
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
20.6. PCA Watchdog Timer Reset
The programmable Watchdog Timer (WDT) function of the Programmable Counter Array (PCA) can be
used to prevent software from running out of control during a system malfunction. The PCA WDT function
can be enabled or disabled by software as described in Section “29.4. Watchdog Timer Mode” on
page 279; the WDT is enabled and clocked by SYSCLK / 12 following any reset. If a system malfunction
prevents user software from updating the WDT, a reset is generated and the WDTRSF bit (RSTSRC.5) is
set to 1. The state of the RST pin is unaffected by this reset.
20.7. EPROM Error Reset
If an EPROM program read or write targets an illegal address, a system reset is generated. This may occur
due to any of the following:
Programming hardware attempts to write or read an EPROM location which is above the user code
space address limit.
An EPROM read from firmware is attempted above user code space. This occurs when a MOVC
operation is attempted above the user code space address limit.
A Program read is attempted above user code space. This occurs when user code attempts to branch
to an address above the user code space address limit.
The MEMERR bit (RSTSRC.6) is set following an EPROM error reset. The state of the RST pin is unaf-
fected by this reset.
20.8. Software Reset
Software may force a reset by writing a 1 to the SWRSF bit (RSTSRC.4). The SWRSF bit will read 1 fol-
lowing a software forced reset. The state of the RST pin is unaffected by this reset.
20.9. USB Reset
Writing 1 to the USBRSF bit in register RSTSRC selects USB0 as a reset source. With USB0 selected as
a reset source, a system reset will be generated when either of the following occur:
1. RESET signaling is detected on the USB network. The USB Function Controller (USB0) must be
enabled for RESET signaling to be detected. See Section “23. Universal Serial Bus Controller (USB0)”
on page 160 for information on the USB Function Controller.
2. A falling or rising voltage on the VBUS pin matches the edge polarity selected by the VBPOL bit in
register REG01CN. See Section “11. Voltage Regulators (REG0 and REG1)” on page 61 for details on
the VBUS detection circuit.
The USBRSF bit will read 1 following a USB reset. The state of the /RST pin is unaffected by this reset.
Rev. 1.2
125
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 20.2. RSTSRC: Reset Source
Bit
7
6
5
4
3
2
1
0
USBRSF MEMERR C0RSEF
SWRSF WDTRSF MCDRSF
PORSF
PINRSF
Name
Type
Reset
R/W
R
R/W
R/W
R
R/W
R/W
R
Varies
Varies
Varies
Varies
Varies
Varies
Varies
Varies
SFR Address = 0xEF
Bit
Name
Description
Write
Read
7
USBRSF
Writing a 1 enables USB
as a reset source.
Set to 1 if USB caused the
last reset.
USB Reset Flag
6
5
4
3
2
MEMERR
C0RSEF
SWRSF
N/A
Set to 1 if EPROM
read/write error caused
the last reset.
EPROM Error Reset Flag.
Writing a 1 enables
Comparator0 as a reset
source (active-low).
Set to 1 if Comparator0
caused the last reset.
Comparator0 Reset Enable
and Flag.
Writing a 1 forces a sys-
tem reset.
Set to 1 if last reset was
caused by a write to
SWRSF.
Software Reset Force and
Flag.
WDTRSF
MCDRSF
N/A
Set to 1 if Watchdog Timer
overflow caused the last
reset.
Watchdog Timer Reset Flag.
Writing a 1 enables the
Missing Clock Detector.
Set to 1 if Missing Clock
Detector timeout caused
Missing Clock Detector
Enable and Flag.
The MCD triggers a reset the last reset.
if a missing clock condition
is detected.
1
PORSF
Writing a 1 enables the
monitor as a reset
source.
Set to 1 anytime a power-
Power-On / V Monitor
DD
V
on or V monitor reset
DD
DD
Reset Flag, and V monitor
DD
occurs.
When set to 1 all other
Reset Enable.
Writing 1 to this bit
before the V monitor RSTSRC flags are inde-
DD
is enabled and stabilized terminate.
may cause a system
reset.
0
PINRSF
N/A
Set to 1 if RST pin caused
the last reset.
HW Pin Reset Flag.
Note: Do not use read-modify-write operations on this register
126
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
21. Oscillators and Clock Selection
C8051T620/1/6/7 & C8051T320/1/2/3 devices include a programmable internal high-frequency oscillator, a
programmable internal low-frequency oscillator, and an external oscillator drive circuit. The internal high-
frequency oscillator can be enabled/disabled and calibrated using the OSCICN and OSCICL registers, as
shown in Figure 21.1. The internal low-frequency oscillator can be enabled/disabled and calibrated using
the OSCLCN register. The system clock can be sourced by the external oscillator circuit or either internal
oscillator. Both internal oscillators offer a selectable post-scaling feature. The USB clock (USBCLK) can be
derived from the internal oscillators or external oscillator.
OSCICL
OSCICN
OSCLCN
CLKSEL
C Mode
XTAL2
RC Mode
VDD
OSCLF OSCLD
4
2
n
ProgrammableEN
Internal Clock
Generator
XTAL2
OSCLF
SYSCLK
EN
Low Frequency
Oscillator
n
Option 1
OSCLD
XTAL1
Input
Circuit
OSC
10MΩ
XTAL2
Internal HFO
Internal HFO / 8
EXOSC
CMOS Mode
XTAL2
USBCLK
EXOSC / 2
EXOSC / 3
OSCXCN
EXOSC / 4
CLKMUL
Internal LFO
Figure 21.1. Oscillator Options
Rev. 1.2
127
C8051T620/1/6/7 & C8051T320/1/2/3
21.1. System Clock Selection
The CLKSL[2:0] bits in register CLKSEL select which oscillator source is used as the system clock.
CLKSL[2:0] must be set to 001b for the system clock to run from the external oscillator; however the exter-
nal oscillator may still clock certain peripherals (timers, PCA) when the internal oscillator is selected as the
system clock. The system clock may be switched on-the-fly between the internal oscillators and external
oscillator so long as the selected clock source is enabled and running.
The internal high-frequency and low-frequency oscillators require little start-up time and may be selected
as the system clock immediately following the register write which enables the oscillator. The external RC
and C modes also typically require no startup time.
21.2. USB Clock Selection
The USBCLK[2:0] bits in register CLKSEL select which oscillator source is used as the USB clock. The
USB clock may be derived from the internal oscillators, a divided version of the internal High-Frequency
oscillator, or a divided version of the external oscillator. Note that the USB clock must be 48 MHz when
operating USB0 as a Full Speed Function; the USB clock must be 6 MHz when operating USB0 as a Low
Speed Function. See SFR Definition 21.1 for USB clock selection options.
Some example USB clock configurations for Full and Low Speed mode are given below:
USB Full Speed (48 MHz)
Internal Oscillator
Clock Signal
Input Source Selection Register Bit Settings
USB Clock
Internal Oscillator
Internal Oscillator*
Divide by 1
USBCLK = 000b
IFCN = 11b
External Oscillator
Clock Signal
Input Source Selection Register Bit Settings
USB Clock
External Oscillator
External Oscillator
CMOS Oscillator Mode
48 MHz Oscillator
USBCLK = 010b
XOSCMD = 010b
Note: Clock Recovery must be enabled for this configuration.
USB Low Speed (6 MHz)
Internal Oscillator
Clock Signal
Input Source Selection Register Bit Settings
USB Clock
Internal Oscillator
Internal Oscillator / 8
Divide by 1
USBCLK = 001b
IFCN = 11b
External Oscillator
Clock Signal
Input Source Selection Register Bit Settings
USB Clock
External Oscillator
External Oscillator / 4
CMOS Oscillator Mode
24 MHz Oscillator
USBCLK = 101b
XOSCMD = 010b
Crystal Oscillator Mode
24 MHz Oscillator
XOSCMD = 110b
XFCN = 111b
128
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 21.1. CLKSEL: Clock Select
Bit
7
6
5
4
3
2
1
0
USBCLK[2:0]
OUTCLK
CLKSL[2:0]
Name
Type
Reset
R
0
R/W
0
R/W
0
R/W
0
0
0
0
0
SFR Address = 0xA9
Bit
Name
Function
7
Unused
Read = 0b; Write = Don’t Care
6:4 USBCLK[2:0]
USB Clock Source Select Bits.
000: USBCLK derived from the Internal High-Frequency Oscillator.
001: USBCLK derived from the Internal High-Frequency Oscillator / 8.
010: USBCLK derived from the External Oscillator.
011: USBCLK derived from the External Oscillator / 2.
100: USBCLK derived from the External Oscillator / 3.
101: USBCLK derived from the External Oscillator / 4.
110: USBCLK derived from the Internal Low-Frequency Oscillator.
111: RESERVED.
3
OUTCLK
Crossbar Clock Out Select.
If the SYSCLK signal is enabled on the Crossbar, this bit selects between outputting
SYSCLK and SYSCLK synchronized with the Port I/O pins.
0: Enabling the Crossbar SYSCLK signal outputs SYSCLK.
1: Enabling the Crossbar SYSCLK signal outputs SYSCLK synchronized with the
Port I/O.
2:0 CLKSL[2:0]
System Clock Source Select Bits.
000: SYSCLK derived from the Internal High-Frequency Oscillator and scaled per
the IFCN bits in register OSCICN.
001: SYSCLK derived from the External Oscillator circuit.
010: SYSCLK derived from the Internal High-Frequency Oscillator / 2.
011: SYSCLK derived from the Internal High-Frequency Oscillator.
100: SYSCLK derived from the Internal Low-Frequency Oscillator and scaled per
the OSCLD bits in register OSCLCN.
101-111: RESERVED.
Rev. 1.2
129
C8051T620/1/6/7 & C8051T320/1/2/3
21.3. Programmable Internal High-Frequency (H-F) Oscillator
All C8051T620/1/6/7 & C8051T320/1/2/3 devices include a programmable internal high-frequency oscilla-
tor that defaults as the system clock after a system reset. The internal oscillator period can be adjusted via
the OSCICL register as defined by SFR Definition 21.2.
On C8051T620/1/6/7 & C8051T320/1/2/3 devices, OSCICL is factory calibrated to obtain a 48 MHz base
frequency. Note that the system clock may be derived from the programmed internal oscillator divided by
1, 2, 4, or 8 after a divide by 4 stage, as defined by the IFCN bits in register OSCICN. The divide value
defaults to 8 following a reset, which results in a 1.5 MHz system clock.
21.3.1. Internal Oscillator Suspend Mode
When software writes a logic 1 to SUSPEND (OSCICN.5), the internal oscillator is suspended. If the sys-
tem clock is derived from the internal oscillator, the input clock to the peripheral or CIP-51 will be stopped
until one of the following events occur:
Port 0 Match Event.
Port 1 Match Event.
Timer3 Overflow Event.
USB0 Transceiver Resume Signalling
When one of the oscillator awakening events occur, the internal oscillator, CIP-51, and affected peripherals
resume normal operation, regardless of whether the event also causes an interrupt. The CPU resumes
execution at the instruction following the write to the SUSPEND bit.
Note: The prefetch engine can be turned off in suspend mode to save power. Additionally, both Voltage
Regulators (REG0 and REG1) have low-power modes for additional power savings in suspend mode. See
Section “13. Prefetch Engine” on page 76 and Section “11. Voltage Regulators (REG0 and REG1)” on
page 61 for more information.
SFR Definition 21.2. OSCICL: Internal H-F Oscillator Calibration
Bit
7
6
5
4
3
2
1
0
OSCICL[6:0]
Name
Type
Reset
R
0
R/W
Varies
Varies
Varies
Varies
Varies
Varies
Varies
SFR Address = 0xB3
Bit
Name
Function
7
Unused
Read = 0; Write = Don’t Care
6:0 OSCICL[6:0]
Internal Oscillator Calibration Bits.
These bits determine the internal oscillator period. When set to 0000000b, the H-F
oscillator operates at its fastest setting. When set to 1111111b, the H-F oscillator
operates at its slowest setting. The reset value is factory calibrated to generate an
internal oscillator frequency of 48 MHz.
Rev. 1.2
130
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 21.3. OSCICN: Internal H-F Oscillator Control
Bit
7
6
5
4
3
2
1
0
IOSCEN
IFRDY
SUSPEND
IFCN[1:0]
R/W
Name
Type
Reset
R/W
1
R
1
R/W
0
R
0
R
0
R
0
0
0
SFR Address = 0xB2
Bit
Name
Function
7
IOSCEN
Internal H-F Oscillator Enable Bit.
0: Internal H-F Oscillator Disabled.
1: Internal H-F Oscillator Enabled.
6
5
IFRDY
Internal H-F Oscillator Frequency Ready Flag.
0: Internal H-F Oscillator is not running at programmed frequency.
1: Internal H-F Oscillator is running at programmed frequency.
SUSPEND
Internal Oscillator Suspend Enable Bit.
Setting this bit to logic 1 places the internal oscillator in SUSPEND mode. The inter-
nal oscillator resumes operation when one of the SUSPEND mode awakening
events occurs.
4:2
1:0
Unused
Read = 000b; Write = Don’t Care
IFCN[1:0]
Internal H-F Oscillator Frequency Divider Control Bits.
The Internal H-F Oscillator is divided by the IFCN bit setting after a divide-by-4 stage.
00: SYSCLK can be derived from Internal H-F Oscillator divided by 8 (1.5 MHz).
01: SYSCLK can be derived from Internal H-F Oscillator divided by 4 (3 MHz).
10: SYSCLK can be derived from Internal H-F Oscillator divided by 2 (6 MHz).
11: SYSCLK can be derived from Internal H-F Oscillator divided by 1 (12 MHz).
131
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
21.4. Clock Multiplier
The C8051T620/1/6/7 & C8051T320/1/2/3 device includes a 48 MHz high-frequency oscillator instead of a
12 MHz oscillator and a 4x Clock Multiplier, so the USB0 module can be run directly from the internal high-
frequency oscillator. For compatibility with the Flash development platform, however, the CLKMUL register
(SFR Definition 21.4) behaves as if the Clock Multiplier is present.
SFR Definition 21.4. CLKMUL: Clock Multiplier Control
Bit
7
6
5
4
3
2
1
0
MULEN
MULINIT MULRDY
MULSEL[1:0]
R
Name
Type
Reset
R
1
R
1
R
1
R
0
R
0
R
0
0
0
SFR Address = 0xB9
Bit
Name
Description
Write
Read
7
MULEN
Clock Multiplier Enable Bit.
0: Clock Multiplier disabled.
1: Clock Multiplier enabled.
This bit always reads 1.
6
MULINIT
Clock Multiplier Initialize
Bit.
This bit should be a 0
when the Clock Multiplier when the Clock Multiplier
The MULRDY bit reads 1
is enabled. Once
is stabilized.
enabled, writing a 1 to
this bit will initialize the
Clock Multiplier.
This bit always reads 1.
5
MULRDY
Unused
Clock Multiplier Ready Bit.
0: Clock Multiplier not ready.
1: Clock Multiplier ready (locked).
This bit always reads 1.
4:2
Read = 000b; Write = Don’t Care
1:0 MULSEL[1:0]
Clock Multiplier Input Select Bits.
These bits select the clock supplied to the Clock Multiplier.
00: Internal High-Frequency Oscillator
01: External Oscillator
10: External Oscillator/2
11: Reserved.
These bits always read 00.
Rev. 1.2
132
C8051T620/1/6/7 & C8051T320/1/2/3
21.5. Programmable Internal Low-Frequency (L-F) Oscillator
All C8051T620/1/6/7 & C8051T320/1/2/3 devices include a programmable low-frequency internal oscilla-
tor, which is calibrated to a nominal frequency of 80 kHz. The low-frequency oscillator circuit includes a
divider that can be changed to divide the clock by 1, 2, 4, or 8, using the OSCLD bits in the OSCLCN reg-
ister (see SFR Definition 21.5). Additionally, the OSCLF[3:0] bits can be used to adjust the oscillator’s out-
put frequency.
21.5.1. Calibrating the Internal L-F Oscillator
Timers 2 and 3 include capture functions that can be used to capture the oscillator frequency, when run-
ning from a known time base. When either Timer 2 or Timer 3 is configured for L-F Oscillator Capture
Mode, a falling edge (Timer 2) or rising edge (Timer 3) of the low-frequency oscillator’s output will cause a
capture event on the corresponding timer. As a capture event occurs, the current timer value
(TMRnH:TMRnL) is copied into the timer reload registers (TMRnRLH:TMRnRLL). By recording the differ-
ence between two successive timer capture values, the low-frequency oscillator’s period can be calcu-
lated. The OSCLF bits can then be adjusted to produce the desired oscillator frequency.
SFR Definition 21.5. OSCLCN: Internal L-F Oscillator Control
Bit
7
6
5
4
3
2
1
0
OSCLEN OSCLRDY
OSCLF[3:0]
R.W
OSCLD[1:0]
R/W
Name
Type
Reset
R/W
0
R
0
Varies
Varies
Varies
Varies
0
0
SFR Address = 0x86
Bit
Name
Function
7
OSCLEN
Internal L-F Oscillator Enable.
0: Internal L-F Oscillator Disabled.
1: Internal L-F Oscillator Enabled.
6
OSCLRDY
Internal L-F Oscillator Ready.
0: Internal L-F Oscillator frequency not stabilized.
1: Internal L-F Oscillator frequency stabilized.
Note: OSCLRDY is only set back to 0 in the event of a device reset or a change to the
OSCLD[1:0] bits.
5:2 OSCLF[3:0]
1:0 OSCLD[1:0]
Internal L-F Oscillator Frequency Control Bits.
Fine-tune control bits for the Internal L-F oscillator frequency. When set to 0000b, the
L-F oscillator operates at its fastest setting. When set to 1111b, the L-F oscillator
operates at its slowest setting.
Internal L-F Oscillator Divider Select.
00: Divide by 8 selected.
01: Divide by 4 selected.
10: Divide by 2 selected.
11: Divide by 1 selected.
Rev. 1.2
133
C8051T620/1/6/7 & C8051T320/1/2/3
21.6. External Oscillator Drive Circuit
The external oscillator circuit may drive an external crystal, ceramic resonator, capacitor, or RC network. A
CMOS clock may also provide a clock input. Figure 21.1 shows a block diagram of the four external oscil-
lator options. The external oscillator is enabled and configured using the OSCXCN register (see SFR Defi-
nition 21.6).
Important Note on External Oscillator Usage: Port pins must be configured when using the external
oscillator circuit. When the external oscillator drive circuit is enabled in crystal/resonator mode, Port pins
P0.2 and P0.3 are used as XTAL1 and XTAL2, respectively. When the external oscillator drive circuit is
enabled in capacitor, RC, or CMOS clock mode, Port pin P0.3 is used as XTAL2. The Port I/O Crossbar
should be configured to skip the Port pin used by the oscillator circuit; see Section “22.3. Priority Crossbar
Decoder” on page 142 for Crossbar configuration. Additionally, when using the external oscillator circuit in
crystal/resonator, capacitor, or RC mode, the associated Port pins should be configured as analog inputs.
In CMOS clock mode, the associated pin should be configured as a digital input. See Section “22.4. Port
I/O Initialization” on page 146 for details on Port input mode selection.
The external oscillator output may be selected as the system clock or used to clock some of the digital
peripherals (e.g. Timers, PCA, etc.). See the data sheet chapters for each digital peripheral for details. See
Section “7. Electrical Characteristics” on page 34 for complete oscillator specifications.
21.6.1. External Crystal Mode
If a crystal or ceramic resonator is used as the external oscillator, the crystal/resonator and a 10 MΩ resis-
tor must be wired across the XTAL1 and XTAL2 pins as shown in Figure 21.1, “Crystal Mode”. Appropriate
loading capacitors should be added to XTAL1 and XTAL2, and both pins should be configured for analog
I/O with the digital output drivers disabled.
The capacitors shown in the external crystal configuration provide the load capacitance required by the
crystal for correct oscillation. These capacitors are “in series” as seen by the crystal and “in parallel” with
the stray capacitance of the XTAL1 and XTAL2 pins.
Note: The recommended load capacitance depends upon the crystal and the manufacturer. Please refer to
the crystal data sheet when completing these calculations.
The equation for determining the load capacitance for two capacitors is
CA × CB
CA + CB
-------------------
+ CS
CL
=
Where:
C and C are the capacitors connected to the crystal leads.
A
B
C is the total stray capacitance of the PCB.
S
The stray capacitance for a typical layout where the crystal is as close as possible to the pins is 2-5 pF per
pin.
If C and C are the same (C), then the equation becomes
A
B
C
2
---
CL
=
+ CS
For example, a tuning-fork crystal of 32 kHz with a recommended load capacitance of 12.5 pF should use
the configuration shown in Figure 21.1, Option 1. With a stray capacitance of 3 pF per pin (6 pF total), the
13 pF capacitors yield an equivalent capacitance of 12.5 pF across the crystal, as shown in Figure 21.2.
Rev. 1.2
134
C8051T620/1/6/7 & C8051T320/1/2/3
13 pF
XTAL1
10 MΩ
32 kHz
13 pF
XTAL2
Figure 21.2. External Crystal Example
Important Note on External Crystals: Crystal oscillator circuits are quite sensitive to PCB layout. The
crystal should be placed as close as possible to the XTAL pins on the device. The traces should be as
short as possible and shielded with ground plane from any other traces which could introduce noise or
interference.
When using an external crystal, the external oscillator drive circuit must be configured by software for Crys-
tal Oscillator Mode or Crystal Oscillator Mode with divide by 2 stage. The divide by 2 stage ensures that the
clock derived from the external oscillator has a duty cycle of 50%. The External Oscillator Frequency Con-
trol value (XFCN) must also be specified based on the crystal frequency (see SFR Definition 21.6).
When the crystal oscillator is first enabled, the external oscillator valid detector allows software to deter-
mine when the external system clock is valid and running. Switching to the external oscillator before the
crystal oscillator has stabilized can result in unpredictable behavior. The recommended procedure for start-
ing the crystal is:
1. Configure XTAL1 and XTAL2 for analog I/O.
2. Disable the XTAL1 and XTAL2 digital output drivers by writing 1s to the appropriate bits in the Port
Latch register.
3. Configure and enable the external oscillator.
4. Wait at least 1 ms.
5. Poll for XTLVLD => '1'.
6. Switch the system clock to the external oscillator.
135
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
21.6.2. External RC Example
If an RC network is used as an external oscillator source for the MCU, the circuit should be configured as
shown in Figure 21.1, “RC Mode”. The capacitor should be no greater than 100 pF; however, for very small
capacitors, the total capacitance may be dominated by parasitic capacitance in the PCB layout. To deter-
mine the required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register, first
select the RC network value to produce the desired frequency of oscillation, according to Equation , where
f = the frequency of oscillation in MHz, C = the capacitor value in pF, and R = the pull-up resistor value in
kΩ.
f = 1.23 × 103 ⁄ (R × C)
Equation 21.1. RC Mode Oscillator Frequency
For example: If the frequency desired is 100 kHz, let R = 246 kΩ and C = 50 pF:
3
3
f = 1.23( 10 ) / RC = 1.23 ( 10 ) / [ 246 x 50 ] = 0.1 MHz = 100 kHz
Referring to the table in SFR Definition 21.6, the required XFCN setting is 010b.
21.6.3. External Capacitor Example
If a capacitor is used as an external oscillator for the MCU, the circuit should be configured as shown in
Figure 21.1, “C Mode”. The capacitor should be no greater than 100 pF; however, for very small capaci-
tors, the total capacitance may be dominated by parasitic capacitance in the PCB layout. To determine the
required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register, select the capaci-
tor to be used and find the frequency of oscillation according to Equation , where f = the frequency of oscil-
lation in MHz, C = the capacitor value in pF, and V = the MCU power supply in Volts.
DD
f = (KF) ⁄ (C × VDD
)
Equation 21.2. C Mode Oscillator Frequency
For example: Assume V = 3.0 V and f = 150 kHz:
DD
f = KF / (C x VDD)
0.150 MHz = KF / (C x 3.0)
Since the frequency of roughly 150 kHz is desired, select the K Factor from the table in SFR Definition 21.6
(OSCXCN) as KF = 22:
0.150 MHz = 22 / (C x 3.0)
C x 3.0 = 22 / 0.150 MHz
C = 146.6 / 3.0 pF = 48.8 pF
Therefore, the XFCN value to use in this example is 011b and C = 50 pF.
Rev. 1.2
136
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 21.6. OSCXCN: External Oscillator Control
Bit
7
6
5
4
3
2
1
0
XCLKVLD
XOSCMD[2:0]
-
XFCN[2:0]
Name
Type
Reset
R
0
R/W
0
R
0
R/W
0
0
0
0
0
SFR Address = 0xB1
Bit
Name
Function
7
XCLKVLD
External Oscillator Valid Flag.
Provides External Oscillator status and is valid at all times for all modes of opera-
tion except External CMOS Clock Mode and External CMOS Clock Mode with
divide by 2. In these modes, XCLKVLD always returns 0.
0: External Oscillator is unused or not yet stable.
1: External Oscillator is running and stable.
6:4 XOSCMD[2:0] External Oscillator Mode Select.
00x: External Oscillator circuit off.
010: External CMOS Clock Mode.
011: External CMOS Clock Mode with divide by 2 stage.
100: RC Oscillator Mode.
101: Capacitor Oscillator Mode.
110: Crystal Oscillator Mode.
111: Crystal Oscillator Mode with divide by 2 stage.
3
Unused
Read = 0; Write = Don’t Care
2:0
XFCN[2:0]
External Oscillator Frequency Control Bits.
Set according to the desired frequency for RC mode.
Set according to the desired K Factor for C mode.
XFCN
000
001
010
011
Crystal Mode
f ≤ 20 kHz
RC Mode
f ≤ 25 kHz
C Mode
K Factor = 0.87
K Factor = 2.6
K Factor = 7.7
K Factor = 22
K Factor = 65
K Factor = 180
K Factor = 664
K Factor = 1590
20 kHz < f ≤ 58 kHz
58 kHz < f ≤ 155 kHz
25 kHz < f ≤ 50 kHz
50 kHz < f ≤ 100 kHz
155 kHz < f ≤ 415 kHz 100 kHz < f ≤ 200 kHz
415 kHz < f ≤ 1.1 MHz 200 kHz < f ≤ 400 kHz
1.1 MHz < f ≤ 3.1 MHz 400 kHz < f ≤ 800 kHz
3.1 MHz < f ≤ 8.2 MHz 800 kHz < f ≤ 1.6 MHz
8.2 MHz < f ≤ 25 MHz 1.6 MHz < f ≤ 3.2 MHz
100
101
110
111
137
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
22. Port Input/Output
Digital and analog resources are available through 21, 24, or 25 I/O pins, depending on the specific device.
Port pins P0.0-P2.7 can be defined as general-purpose I/O (GPIO), assigned to one of the internal digital
resources, or assigned to an analog function as shown in Figure 22.3. Port pin P3.0 on can be used as
GPIO and is shared with the C2 Interface Data signal (C2D). The designer has complete control over
which functions are assigned, limited only by the number of physical I/O pins. This resource assignment
flexibility is achieved through the use of a Priority Crossbar Decoder. Note that the state of a Port I/O pin
can always be read in the corresponding Port latch, regardless of the Crossbar settings.
The Crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder
(Figure 22.4). The registers XBR0, XBR1, and XBR2, defined in SFR Definition 22.1, SFR Definition 22.2,
and SFR Definition 22.2, are used to select internal digital functions.
All Port I/Os are 5 V tolerant (refer to Figure 22.2 for the Port cell circuit). The Port I/O cells are configured
as either push-pull or open-drain in the Port Output Mode registers (PnMDOUT, where n = 0,1). Complete
Electrical Specifications for Port I/O are given in Table 7.3 on page 36.
XBR0, XBR1,
XBR2, PnSKIP
Registers
Port Match
P0MASK, P0MAT
P1MASK, P1MAT
External Interrupts
EX0 and EX1
Priority
Decoder
PnMDOUT,
PnMDIN Registers
2
4
2
2
2
Highest
Priority
UART0
SPI
P0.0
SMBus
P0
I/O
Cells
Digital
Crossbar
8
8
7
CP0
Outputs
P0.7
P1.0
CP1
Outputs
SYSCLK
P1
I/O
Cells
6
2
PCA
P1.7
P2.0
T0, T1
2
P2
I/O
Lowest
Priority
UART1
Cells
8
P2.7
P3.0
P0
P1
P2
P3
(P0.0-P0.7)
8
P3
I/O
Cell
(P1.0-P1.7)
7
(P2.0-P2.6)
To Analog Peripherals
(ADC0, CP0, CP1, VREF,
EXTCLK)
1
(P3.0)
Figure 22.1. Port I/O Functional Block Diagram
Rev. 1.2
138
C8051T620/1/6/7 & C8051T320/1/2/3
22.1. Port I/O Modes of Operation
Port pins use the Port I/O cell shown in Figure 22.2. Each Port I/O cell can be configured by software for
analog I/O or digital I/O using the PnMDIN registers. On reset, all Port I/O cells default to a high impedance
state with weak pull-ups enabled until the Crossbar is enabled (XBARE = 1).
22.1.1. Port Pins Configured for Analog I/O
Any pins to be used as Comparator or ADC input, external oscillator input/output, or VREF should be con-
figured for analog I/O (PnMDIN.n = 1). When a pin is configured for analog I/O, its weak pullup, digital
driver, and digital receiver are disabled. Port pins configured for analog I/O will always read back a value of
0.
Configuring pins as analog I/O saves power and isolates the Port pin from digital interference. Port pins
configured as digital inputs may still be used by analog peripherals; however, this practice is not recom-
mended and may result in measurement errors.
22.1.2. Port Pins Configured For Digital I/O
Any pins to be used by digital peripherals (UART, SPI, SMBus, etc.), external digital event capture func-
tions, or as GPIO should be configured as digital I/O (PnMDIN.n = 1). For digital I/O pins, one of two output
modes (push-pull or open-drain) must be selected using the PnMDOUT registers.
Push-pull outputs (PnMDOUT.n = 1) drive the Port pad to the V or GND supply rails based on the output
IO
logic value of the Port pin. Open-drain outputs have the high side driver disabled; therefore, they only drive
the Port pad to GND when the output logic value is 0 and become high impedance inputs (both high and
low drivers turned off) when the output logic value is 1.
When a digital I/O cell is placed in the high impedance state, a weak pull-up transistor pulls the Port pad to
the V
supply voltage to ensure the digital input is at a defined logic state. Weak pull-ups are disabled
DD
when the I/O cell is driven to GND to minimize power consumption and may be globally disabled by setting
WEAKPUD to 1. The user should ensure that digital I/O are always internally or externally pulled or driven
to a valid logic state to minimize power consumption. Port pins configured for digital I/O always read back
the logic state of the Port pad, regardless of the output logic value of the Port pin.
WEAKPUD
(Weak Pull-Up Disable)
PxMDOUT.x
(1 for push-pull)
(0 for open-drain)
VIO
VIO
XBARE
(Crossbar
Enable)
(WEAK)
PORT
PAD
Px.x – Output
Logic Value
(Port Latch or
Crossbar)
PxMDIN.x
(1 for digital)
(0 for analog)
GND
To/From Analog
Peripheral
Px.x – Input Logic Value
(Reads 0 when pin is configured as an analog I/O)
Figure 22.2. Port I/O Cell Block Diagram
139
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
22.1.3. Interfacing Port I/O to 5 V Logic
All Port I/O configured for digital, open-drain operation are capable of interfacing to digital logic operating at
a supply voltage higher than V and less than 5.25V. An external pull-up resistor to the higher supply volt-
IO
age is typically required for most systems.
Important Note: In a multi-voltage interface, the external pull-up resistor should be sized to allow a current
of at least 150uA to flow into the Port pin when the supply voltage is between (V + 0.6V) and (V
+
IO
IO
1.0V). Once the Port pin voltage increases beyond this range, the current flowing into the Port pin is mini-
mal.
22.2. Assigning Port I/O Pins to Analog and Digital Functions
Port I/O pins can be assigned to various analog, digital, and external interrupt functions. The Port pins
assigned to analog functions should be configured for analog I/O, and Port pins assigned to digital or exter-
nal interrupt functions should be configured for digital I/O.
22.2.1. Assigning Port I/O Pins to Analog Functions
Table 22.1 shows all available analog functions that require Port I/O assignments. Port pins selected for
these analog functions should have their corresponding bit in PnSKIP set to 1. This reserves the pin
for use by the analog function and does not allow it to be claimed by the Crossbar. Table 22.1 shows the
potential mapping of Port I/O to each analog function.
Table 22.1. Port I/O Assignment for Analog Functions
Analog Function
ADC Input
PotentiallyAssignable
Port Pins
Suffers) used for
Assignment
P0.0, P0.1, P0.4, P0.5,
P1.0- P3.0
AMX0P, PnSKIP
Comparator Input
P0.0, P0.1, P0.4, P0.5,
P1.0-P1.7, P2.0-P2.5
CPT0MX, CPT1MX,
PnSKIP
Voltage Reference (VREF0)
P0.7
P0.2, P0.3
P0.3
REF0CN, PnSKIP
OSCXCN, PnSKIP
OSCXCN, PnSKIP
External Oscillator in Crystal Mode (XTAL1, XTAL2)
External Oscillator in RC or C Mode (XTAL2)
22.2.2. Assigning Port I/O Pins to Digital Functions
Any Port pins not assigned to analog functions may be assigned to digital functions or used as GPIO. Most
digital functions rely on the Crossbar for pin assignment; however, some digital functions bypass the
Crossbar in a manner similar to the analog functions listed above. Port pins used by these digital func-
tions and any Port pins selected for use as GPIO should have their corresponding bit in PnSKIP set
to 1. Table 22.2 shows all available digital functions and the potential mapping of Port I/O to each digital
function.
Rev. 1.2
140
C8051T620/1/6/7 & C8051T320/1/2/3
Table 22.2. Port I/O Assignment for Digital Functions
Digital Function
Potentially Assignable Port Pins
Suffers) used for
Assignment
UART0, SPI0, SMBus, CP0, Any Port pin available for assignment by the
XBR0, XBR1, XBR2
CP0A, CP1, CP1A,
SYSCLK, PCA0 (CEX0-4
and ECI), T0, T1, or UART1.
Crossbar. This includes P0.0 - P2.6 pins which
have their PnSKIP bit set to 0.
Note: The Crossbar will always assign UART0
pins to P0.4 and P0.5.
Any pin used for GPIO
P0.0 - P3.0
PnSKIP
22.2.3. Assigning Port I/O Pins to External Digital Event Capture Functions
External digital event capture functions can be used to trigger an interrupt or wake the device from a low
power mode when a transition occurs on a digital I/O pin. The digital event capture functions do not require
dedicated pins and will function on both GPIO pins (PnSKIP = 1) and pins in use by the Crossbar (PnSKIP
= 0). External digital event capture functions cannot be used on pins configured for analog I/O. Table 22.3
shows all available external digital event capture functions.
141
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
Table 22.3. Port I/O Assignment for External Digital Event Capture Functions
Digital Function
Potentially Assignable Port Pins
SFR(s) used for
Assignment
External Interrupt 0
External Interrupt 1
Port Match
P0.0 - P0.7
P0.0 - P0.7
P0.0 - P1.7
IT01CF
IT01CF
P0MASK, P0MAT
P1MASK, P1MAT
22.3. Priority Crossbar Decoder
The Priority Crossbar Decoder assigns a priority to each I/O function, starting at the top with UART0. When
a digital resource is selected, the least-significant unassigned Port pin is assigned to that resource (exclud-
ing UART0, which is always at pins 4 and 5). If a Port pin is assigned, the Crossbar skips that pin when
assigning the next selected resource. Additionally, the Crossbar will skip Port pins whose associated bits in
the PnSKIP registers are set. The PnSKIP registers allow software to skip Port pins that are to be used for
analog input, dedicated functions, or GPIO.
Because of the nature of the Priority Crossbar Decoder, not all peripherals can be located on all port pins.
Figure 22.3 shows the possible pins on which peripheral I/O can appear.
Important Note on Crossbar Configuration: If a Port pin is claimed by a peripheral without use of the
Crossbar, its corresponding PnSKIP bit should be set. The Crossbar skips selected pins as if they were
already assigned, and moves to the next unassigned pin.
Registers XBR0, XBR1, and XBR2 are used to assign the digital I/O resources to the physical I/O Port
pins. Note that when the SMBus is selected, the Crossbar assigns both pins associated with the SMBus
(SDA and SCL); when a UART is selected, the Crossbar assigns both pins associated with the UART (TX
and RX). UART0 pin assignments are fixed for bootloading purposes: UART TX0 is always assigned to
P0.4; UART RX0 is always assigned to P0.5. Standard Port I/Os appear contiguously after the prioritized
functions have been assigned. Figure 22.4 and Figure 22.5 show examples of how the crossbar assigns
peripherals according to the XBRn and PnSKIP register settings.
Important Note: The SPI can be operated in either 3-wire or 4-wire modes, pending the state of the NSS-
MD1–NSSMD0 bits in register SPI0CN. According to the SPI mode, the NSS signal may or may not be
routed to a Port pin.
Rev. 1.2
142
C8051T620/1/6/7 & C8051T320/1/2/3
Port
P0
4
P1
4
P21
4
Pin Number 0
1
2
3
5
6
7
0
1
2
3
5
6
7
0
1
2
3
5 6 7
Special
Function
Signals
TX0
RX0
SCK
MISO
MOSI
NSS
SDA
SCL
CP0
CP0A
CP1
CP1A
SYSCLK
CEX0
CEX1
CEX2
CEX3
CEX4
ECI
T0
T1
TX1
RX1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 0 0
Pin Skip
Settings
P0SKIP
P1SKIP
P2SKIP
Pins P0.0-P2.71 are capable of being assigned to crossbar peripherals.
The crossbar peripherals are assigned in priority order from top to bottom, according to this
diagram.
These boxes represent Port pins which can potentially be assigned to a peripheral.
Special Function Signals are not assigned by the crossbar. When these signals are enabled,
the Crossbar should be manually configured to skip the corresponding port pins.
Pins can be “skipped” by setting the corresponding bit in PnSKIP to ‘1’.
Notes:
1. P2.4-P2.7 are only available in certain packages.
2. NSS is only pinned out when the SPI is in 4-wire mode.
Figure 22.3. Priority Crossbar Decoder Potential Pin Assignments
143
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
Port
P0
4
P1
4
P21
4
Pin Number 0
1
2
3
5
6
7
0
1
2
3
5
6
7
0
1
2
3
5 6 7
Special
Function
Signals
TX0
RX0
SCK
MISO
MOSI
NSS
SDA
SCL
CP0
CP0A
CP1
CP1A
SYSCLK
CEX0
CEX1
CEX2
CEX3
CEX4
ECI
T0
T1
TX1
RX1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 0 0
Pin Skip
Settings
P0SKIP
P1SKIP
P2SKIP
In this example, the crossbar is configured to assign the UART TX0 and RX0 signals, the SPI
signals, and three PCA signals. Note that the SPI signals are assigned as multiple signals, and
there are no pins skipped using the P0SKIP or P1SKIP registers.
These boxes represent the port pins which are used by the peripherals in this configuration.
1st TX0 is assigned to P0.4
2nd RX0 is assigned to P0.5
3rd SCK, MISO, MOSI, and NSS are assigned to P0.0, P0.1, P0.2, and P0.3, respectively.
4th CEX0, CEX1, and CEX2 are assigned to P0.6, P0.7, and P1.0, respectively.
All unassigned pins can be used as GPIO or for other non-crossbar functions.
Notes:
1. P2.4-P2.7 are only available in certain packages.
Figure 22.4. Priority Crossbar Decoder Example 1—No Skipped Pins
Rev. 1.2
144
C8051T620/1/6/7 & C8051T320/1/2/3
Port
P0
4
P1
4
P21
4
Pin Number 0
1
2
3
5
6
7
0
1
2
3
5
6
7
0
1
2
3
5 6 7
Special
Function
Signals
TX0
RX0
SCK
MISO
MOSI
NSS
SDA
SCL
CP0
CP0A
CP1
CP1A
SYSCLK
CEX0
CEX1
CEX2
CEX3
CEX4
ECI
T0
T1
TX1
RX1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 0 0
Pin Skip
Settings
P0SKIP
P1SKIP
P2SKIP
In this example, the crossbar is configured to assign the UART TX0 and RX0 signals, the SPI
signals, and three PCA signals. Note that the SPI signals are assigned as multiple signals.
Additionally, pins P0.0, P0.2, and P0.3 are configured to be skipped using the P0SKIP register.
These boxes represent the port pins which are used by the peripherals in this configuration.
1st TX0 is assigned to P0.4
2nd RX0 is assigned to P0.5
3rd SCK, MISO, MOSI, and NSS are assigned to P0.1, P0.6, P0.7, and P1.0, respectively.
4th CEX0, CEX1, and CEX2 are assigned to P1.1, P1.2, and P1.3, respectively.
All unassigned pins, including those skipped by XBR0 can be used as GPIO or for other non-
crossbar functions.
Notes:
1. P2.4-P2.7 are only available in certain packages.
Figure 22.5. Priority Crossbar Decoder Example 2—Skipping Pins
145
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
22.4. Port I/O Initialization
Port I/O initialization consists of the following steps:
1. Select the input mode (analog or digital) for all Port pins, using the Port Input Mode register (PnMDIN).
2. Select the output mode (open-drain or push-pull) for all Port pins, using the Port Output Mode register
(PnMDOUT).
3. Select any pins to be skipped by the I/O Crossbar using the Port Skip registers (PnSKIP).
4. Assign Port pins to desired peripherals (XBR0, XBR1, XBR2).
5. Enable the Crossbar (XBARE = 1).
All Port pins must be configured as either analog or digital inputs. Any pins to be used as Comparator or
ADC inputs should be configured as an analog inputs. When a pin is configured as an analog input, its
weak pullup, digital driver, and digital receiver are disabled. This process saves power and reduces noise
on the analog input. Pins configured as digital inputs may still be used by analog peripherals; however this
practice is not recommended.
Additionally, all analog input pins should be configured to be skipped by the Crossbar (accomplished by
setting the associated bits in PnSKIP). Port input mode is set in the PnMDIN register, where a 1 indicates a
digital input, and a 0 indicates an analog input. All pins default to digital inputs on reset. See SFR Definition
22.9, SFR Definition 22.13, and SFR Definition 22.17 for the PnMDIN register details.
The output driver characteristics of the I/O pins are defined using the Port Output Mode registers (PnMD-
OUT). Each Port Output driver can be configured as either open drain or push-pull. This selection is
required even for the digital resources selected in the XBRn registers, and is not automatic. The only
exception to this is the SMBus (SDA, SCL) pins, which are configured as open-drain regardless of the
PnMDOUT settings. When the WEAKPUD bit in XBR1 is 0, a weak pullup is enabled for all Port I/O config-
ured as open-drain. WEAKPUD does not affect the push-pull Port I/O. Furthermore, the weak pullup is
turned off on an output that is driving a 0 to avoid unnecessary power dissipation.
Registers XBR0, XBR1, and XBR2 must be loaded with the appropriate values to select the digital I/O
functions required by the design. Setting the XBARE bit in XBR1 to 1 enables the Crossbar. Until the
Crossbar is enabled, the external pins remain as standard Port I/O (in input mode), regardless of the XBRn
Register settings. For given XBRn Register settings, one can determine the I/O pin-out using the Priority
Decode Table; as an alternative, the Configuration Wizard utility of the Silicon Labs IDE software will deter-
mine the Port I/O pin-assignments based on the XBRn Register settings.
The Crossbar must be enabled to use Port pins as standard Port I/O in output mode. Port output drivers
are disabled while the Crossbar is disabled.
Rev. 1.2
146
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 22.1. XBR0: Port I/O Crossbar Register 0
Bit
7
CP1AE
R/W
0
6
CP1E
R/W
0
5
CP0AE
R/W
0
4
CP0E
R/W
0
3
SYSCKE
R/W
2
SMB0E
R/W
0
1
SPI0E
R/W
0
0
URT0E
R/W
0
Name
Type
Reset
0
SFR Address = 0xE1
Bit
Name
Function
7
CP1AE Comparator1 Asynchronous Output Enable.
0: Asynchronous CP1 unavailable at Port pin.
1: Asynchronous CP1 routed to Port pin.
6
5
4
3
CP1E
Comparator1 Output Enable.
0: CP1 unavailable at Port pin.
1: CP1 routed to Port pin.
CP0AE Comparator0 Asynchronous Output Enable.
0: Asynchronous CP0 unavailable at Port pin.
1: Asynchronous CP0 routed to Port pin.
CP0E
Comparator0 Output Enable.
0: CP0 unavailable at Port pin.
1: CP0 routed to Port pin.
SYSCKE /SYSCLK Output Enable.
The source of this signal is determined by the OUTCLK bit (see SFR Definition 21.1).
0: /SYSCLK unavailable at Port pin.
1: /SYSCLK output routed to Port pin.
2
1
SMB0E SMBus I/O Enable.
0: SMBus I/O unavailable at Port pins.
1: SMBus I/O routed to Port pins.
SPI0E
SPI I/O Enable.
0: SPI I/O unavailable at Port pins.
1: SPI I/O routed to Port pins. Note that the SPI can be assigned either 3 or 4 GPIO
pins.
0
URT0E UART I/O Output Enable.
0: UART I/O unavailable at Port pin.
1: UART TX0, RX0 routed to Port pins P0.4 and P0.5.
147
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 22.2. XBR1: Port I/O Crossbar Register 1
Bit
7
6
5
4
3
ECIE
R/W
0
2
1
0
Name WEAKPUD XBARE
T1E
R/W
0
T0E
R/W
0
PCA0ME[2:0]
Type
R/W
0
R/W
0
R/W
0
Reset
0
0
SFR Address = 0xE2
Bit
Name
Function
7
WEAKPUD Port I/O Weak Pullup Disable.
0: Weak Pullups enabled (except for Ports whose I/O are configured for analog
mode).
1: Weak Pullups disabled.
6
5
4
3
XBARE
T1E
Crossbar Enable.
0: Crossbar disabled.
1: Crossbar enabled.
T1 Enable.
0: T1 unavailable at Port pin.
1: T1 routed to Port pin.
T0E
T0 Enable.
0: T0 unavailable at Port pin.
1: T0 routed to Port pin.
ECIE
PCA0 External Counter Input Enable.
0: ECI unavailable at Port pin.
1: ECI routed to Port pin.
2:0 PCA0ME[2:0] PCA Module I/O Enable Bits.
000: All PCA I/O unavailable at Port pins.
001: CEX0 routed to Port pin.
010: CEX0, CEX1 routed to Port pins.
011: CEX0, CEX1, CEX2 routed to Port pins.
100: CEX0, CEX1, CEX2, CEX3 routed to Port pins.
101: CEX0, CEX1, CEX2, CEX3, CEX4 routed to Port pins.
110-111: Reserved.
Rev. 1.2
148
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 22.3. XBR2: Port I/O Crossbar Register 2
Bit
7
6
5
4
3
2
1
Reserved
R/W
0
URT1E
R/W
0
Name
Type
Reset
R
0
R
0
R
0
R
0
R
0
R
0
0
SFR Address = 0xE3
Bit
7:2
1
Name
Unused
Reserved
URT1E
Function
Read = 0000000b; Write = Don’t Care.
Must write 0.
0
UART1 I/O Output Enable Bit.
0: UART1 I/O unavailable at Port pins.
1: UART1 TX1, RX1 routed to Port pins.
22.5. Port Match
Port match functionality allows system events to be triggered by a logic value change on P0 or P1. A soft-
ware controlled value stored in the PnMATCH registers specifies the expected or normal logic values of P0
and P1. A Port mismatch event occurs if the logic levels of the Port’s input pins no longer match the soft-
ware controlled value. This allows Software to be notified if a certain change or pattern occurs on P0 or P1
input pins regardless of the XBRn settings.
The PnMASK registers can be used to individually select which P0 and P1 pins should be compared
against the PnMATCH registers. A Port mismatch event is generated if (P0 & P0MASK) does not equal
(P0MATCH & P0MASK) or if (P1 & P1MASK) does not equal (P1MATCH & P1MASK).
A Port mismatch event may be used to generate an interrupt or wake the device from a low power mode,
such as IDLE or SUSPEND. See the Interrupts and Power Options chapters for more details on interrupt
and wake-up sources.
149
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 22.4. P0MASK: Port 0 Mask Register
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P0MASK[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Address = 0xAE
Bit Name
7:0 P0MASK[7:0] Port 0 Mask Value.
Function
Selects P0 pins to be compared to the corresponding bits in P0MAT.
0: P0.n pin logic value is ignored and cannot cause a Port Mismatch event.
1: P0.n pin logic value is compared to P0MAT.n.
SFR Definition 22.5. P0MAT: Port 0 Match Register
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P0MAT[7:0]
R/W
1
1
1
1
1
1
1
1
SFR Address = 0x84
Bit
Name
Function
7:0
P0MAT[7:0]
Port 0 Match Value.
Match comparison value used on Port 0 for bits in P0MASK which are set to 1.
0: P0.n pin logic value is compared with logic LOW.
1: P0.n pin logic value is compared with logic HIGH.
Rev. 1.2
150
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 22.6. P1MASK: Port 1 Mask Register
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P1MASK[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Address = 0xBA
Bit Name
7:0 P1MASK[7:0] Port 1 Mask Value.
Function
Selects P1 pins to be compared to the corresponding bits in P1MAT.
0: P1.n pin logic value is ignored and cannot cause a Port Mismatch event.
1: P1.n pin logic value is compared to P1MAT.n.
SFR Definition 22.7. P1MAT: Port 1 Match Register
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P1MAT[7:0]
R/W
1
1
1
1
1
1
1
1
SFR Address = 0xB6
Bit
Name
Function
7:0
P1MAT[7:0]
Port 1 Match Value.
Match comparison value used on Port 1 for bits in P1MASK which are set to 1.
0: P1.n pin logic value is compared with logic LOW.
1: P1.n pin logic value is compared with logic HIGH.
151
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
22.6. Special Function Registers for Accessing and Configuring Port I/O
All Port I/O are accessed through corresponding special function registers (SFRs) that are both byte
addressable and bit addressable. When writing to a Port, the value written to the SFR is latched to main-
tain the output data value at each pin. When reading, the logic levels of the Port's input pins are returned
regardless of the XBRn settings (i.e., even when the pin is assigned to another signal by the Crossbar, the
Port register can always read its corresponding Port I/O pin). The exception to this is the execution of the
read-modify-write instructions that target a Port Latch register as the destination. The read-modify-write
instructions when operating on a Port SFR are the following: ANL, ORL, XRL, JBC, CPL, INC, DEC, DJNZ
and MOV, CLR or SETB, when the destination is an individual bit in a Port SFR. For these instructions, the
value of the latch register (not the pin) is read, modified, and written back to the SFR.
Each Port has a corresponding PnSKIP register which allows its individual Port pins to be assigned to dig-
ital functions or skipped by the Crossbar. All Port pins used for analog functions or GPIO should have their
PnSKIP bit set to 1.
The Port input mode of the I/O pins is defined using the Port Input Mode registers (PnMDIN). Each Port
cell can be configured for analog or digital I/O. This selection is required even for the digital resources
selected in the XBRn registers, and is not automatic. The only exception to this is P3.0, which can only be
used for digital I/O.
The output driver characteristics of the I/O pins are defined using the Port Output Mode registers (PnMD-
OUT). Each Port Output driver can be configured as either open drain or push-pull. This selection is
required even for the digital resources selected in the XBRn registers, and is not automatic. The only
exception to this is the SMBus (SDA, SCL) pins, which are configured as open-drain regardless of the
PnMDOUT settings.
SFR Definition 22.8. P0: Port 0
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P0[7:0]
R/W
1
1
1
1
1
1
1
1
SFR Address = 0x80; Bit-Addressable
Bit
Name
P0[7:0] Port 0 Data.
Sets the Port latch logic
Description
Write
0: Set output latch to logic 0: P0.n Port pin is logic
LOW. LOW.
1: Set output latch to logic 1: P0.n Port pin is logic
Read
7:0
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
HIGH.
HIGH.
Rev. 1.2
152
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 22.9. P0MDIN: Port 0 Input Mode
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P0MDIN[7:0]
R/W
1
1
1
1
1
1
1
1
SFR Address = 0xF1
Bit
Name
Function
7:0
P0MDIN[7:0] Analog Configuration Bits for P0.7–P0.0 (respectively).
Port pins configured for analog mode have their weak pullup, digital driver, and
digital receiver disabled.
0: Corresponding P0.n pin is configured for analog mode.
1: Corresponding P0.n pin is not configured for analog mode.
SFR Definition 22.10. P0MDOUT: Port 0 Output Mode
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P0MDOUT[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Address = 0xA4
Bit Name
Function
7:0 P0MDOUT[7:0] Output Configuration Bits for P0.7–P0.0 (respectively).
These bits are ignored if the corresponding bit in register P0MDIN is logic 0.
0: Corresponding P0.n Output is open-drain.
1: Corresponding P0.n Output is push-pull.
153
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 22.11. P0SKIP: Port 0 Skip
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P0SKIP[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Address = 0xD4
Bit
Name
Function
7:0
P0SKIP[7:0] Port 0 Crossbar Skip Enable Bits.
These bits select Port 0 pins to be skipped by the Crossbar Decoder. Port pins
used for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P0.n pin is not skipped by the Crossbar.
1: Corresponding P0.n pin is skipped by the Crossbar.
SFR Definition 22.12. P1: Port 1
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P1[7:0]
R/W
1
1
1
1
1
1
1
1
SFR Address = 0x90; Bit-Addressable
Bit
Name
P1[7:0] Port 1 Data.
Sets the Port latch logic
Description
Write
0: Set output latch to logic 0: P1.n Port pin is logic
LOW. LOW.
1: Set output latch to logic 1: P1.n Port pin is logic
Read
7:0
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
HIGH.
HIGH.
Rev. 1.2
154
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 22.13. P1MDIN: Port 1 Input Mode
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P1MDIN[7:0]
R/W
1
1
1
1
1
1
1
1
SFR Address = 0xF2
Bit
Name
Function
7:0
P1MDIN[7:0] Analog Configuration Bits for P1.7–P1.0 (respectively).
Port pins configured for analog mode have their weak pullup, digital driver, and
digital receiver disabled.
0: Corresponding P1.n pin is configured for analog mode.
1: Corresponding P1.n pin is not configured for analog mode.
SFR Definition 22.14. P1MDOUT: Port 1 Output Mode
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P1MDOUT[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Address = 0xA5
Bit Name
Function
7:0 P1MDOUT[7:0] Output Configuration Bits for P1.7–P1.0 (respectively).
These bits are ignored if the corresponding bit in register P1MDIN is logic 0.
0: Corresponding P1.n Output is open-drain.
1: Corresponding P1.n Output is push-pull.
155
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 22.15. P1SKIP: Port 1 Skip
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P1SKIP[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Address = 0xD5
Bit
Name
Function
7:0
P1SKIP[7:0] Port 1 Crossbar Skip Enable Bits.
These bits select Port 1 pins to be skipped by the Crossbar Decoder. Port pins
used for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P1.n pin is not skipped by the Crossbar.
1: Corresponding P1.n pin is skipped by the Crossbar.
SFR Definition 22.16. P2: Port 2
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P2[7:0]
R/W
1
1
1
1
1
1
1
1
SFR Address = 0xA0; Bit-Addressable
Bit
Name
P2[7:0] Port 2 Data.
Sets the Port latch logic
Description
Write
0: Set output latch to logic 0: P2.n Port pin is logic
LOW. LOW.
1: Set output latch to logic 1: P2.n Port pin is logic
Read
7:0
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
HIGH.
HIGH.
Rev. 1.2
156
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 22.17. P2MDIN: Port 2 Input Mode
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P2MDIN[7:0]
R/W
1
1
1
1
1
1
1
1
SFR Address = 0xF3
Bit
Name
Function
7:0
P2MDIN[7:0] Analog Configuration Bits for P2.7–P2.0 (respectively).
Port pins configured for analog mode have their weak pullup, digital driver, and
digital receiver disabled.
0: Corresponding P2.n pin is configured for analog mode.
1: Corresponding P2.n pin is not configured for analog mode.
SFR Definition 22.18. P2MDOUT: Port 2 Output Mode
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P2MDOUT[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Address = 0xA6
Bit Name
Function
7:0 P2MDOUT[7:0] Output Configuration Bits for P2.7–P2.0 (respectively).
These bits are ignored if the corresponding bit in register P2MDIN is logic 0.
0: Corresponding P2.n Output is open-drain.
1: Corresponding P2.n Output is push-pull.
157
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 22.19. P2SKIP: Port 2 Skip
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P2SKIP[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Address = 0xD6
Bit
Name
Function
7:0
P2SKIP[7:0] Port 2 Crossbar Skip Enable Bits.
These bits select Port 2 pins to be skipped by the Crossbar Decoder. Port pins
used for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P2.n pin is not skipped by the Crossbar.
1: Corresponding P2.n pin is skipped by the Crossbar.
SFR Definition 22.20. P3: Port 3
Bit
7
6
5
4
3
2
1
0
P3[0]
R/W
1
Name
Type
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
SFR Address = 0xB0; Bit-Addressable
Bit
7:1
0
Name
Description
Write
Read
Unused Unused.
Don’t Care
0000000b
P3[0]
Port 3 Data.
0: Set output latch to logic 0: P3.0 Port pin is logic
LOW. LOW.
1: Set output latch to logic 1: P3.0 Port pin is logic
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
HIGH.
HIGH.
Rev. 1.2
158
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 22.21. P3MDOUT: Port 3 Output Mode
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P3MDOUT[0]
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
SFR Address = 0xA7
Bit
7:1
0
Name
Function
Unused
Read = 0000000b; Write = Don’t Care
P3MDOUT[0] Output Configuration Bits for P3.0.
0: P3.0 Output is open-drain.
1: P3.0 Output is push-pull.
159
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
23. Universal Serial Bus Controller (USB0)
C8051T620/1/6/7 & C8051T320/1/2/3 devices include a complete Full/Low Speed USB function for USB
peripheral implementations. The USB Function Controller (USB0) consists of a Serial Interface Engine
(SIE), USB Transceiver (including matching resistors and configurable pull-up resistors), 1 kB FIFO block,
and clock recovery mechanism for crystal-less operation. No external components are required. The USB
Function Controller and Transceiver is Universal Serial Bus Specification 2.0 compliant.
Transceiver
Serial Interface Engine (SIE)
Endpoint0
VDD
IN/OUT
D+
D-
USB
Data
Transfer
Control
Control,
CIP-51 Core
Endpoint1
Endpoint2
Endpoint3
Status, and
Interrupt
Registers
OUT
IN
USB FIFOs
(1k RAM)
Figure 23.1. USB0 Block Diagram
Important Note: This document assumes a comprehensive understanding of the USB Protocol. Terms and
abbreviations used in this document are defined in the USB Specification. We encourage you to review the
latest version of the USB Specification before proceeding.
Note: The C8051T620/1/6/7 & C8051T320/1/2/3 cannot be used as a USB Host device.
Rev. 1.2
160
C8051T620/1/6/7 & C8051T320/1/2/3
23.1. Endpoint Addressing
A total of eight endpoint pipes are available. The control endpoint (Endpoint0) always functions as a bi-
directional IN/OUT endpoint. The other endpoints are implemented as three pairs of IN/OUT endpoint
pipes:
Table 23.1. Endpoint Addressing Scheme
Endpoint
Associated Pipes
USB Protocol Address
Endpoint0
Endpoint0 IN
Endpoint0 OUT
Endpoint1 IN
Endpoint1 OUT
Endpoint2 IN
0x00
0x00
0x81
0x01
0x82
0x02
Endpoint1
Endpoint2
Endpoint2 OUT
Endpoint3
Endpoint3 IN
Endpoint3 OUT
0x83
0x03
23.2. USB Transceiver
The USB Transceiver is configured via the USB0XCN register shown in SFR Definition 23.1. This configu-
ration includes Transceiver enable/disable, pull-up resistor enable/disable, and device speed selection
(Full or Low Speed). When bit SPEED = 1, USB0 operates as a Full Speed USB function, and the on-chip
pull-up resistor (if enabled) appears on the D+ pin. When bit SPEED = 0, USB0 operates as a Low Speed
USB function, and the on-chip pull-up resistor (if enabled) appears on the D- pin. Bits4-0 of register
USB0XCN can be used for Transceiver testing as described in SFR Definition 23.1. The pull-up resistor is
enabled only when VBUS is present (see Section “11.1.2. VBUS Detection” on page 61 for details on
VBUS detection).
Important Note: The USB clock should be active before the Transceiver is enabled.
161
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 23.1. USB0XCN: USB0 Transceiver Control
Bit
7
6
5
4
3
2
1
0
PREN
PHYEN
SPEED
PHYTST[1:0]
R/W
DFREC
Dp
Dn
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R
0
R
0
R
0
0
0
SFR Address = 0xD7
Bit
Name
Function
7
PREN
Internal Pull-up Resistor Enable.
The location of the pull-up resistor (D+ or D-) is determined by the SPEED bit.
0: Internal pull-up resistor disabled (device effectively detached from USB network).
1: Internal pull-up resistor enabled when VBUS is present (device attached to the
USB network).
6
5
PHYEN
SPEED
Physical Layer Enable.
0: USB0 physical layer Transceiver disabled (suspend).
1: USB0 physical layer Transceiver enabled (normal).
USB0 Speed Select.
This bit selects the USB0 speed.
0: USB0 operates as a Low Speed device. If enabled, the internal pull-up resistor
appears on the D– line.
1: USB0 operates as a Full Speed device. If enabled, the internal pull-up resistor
appears on the D+ line.
4:3 PHYTST[1:0]
Physical Layer Test Bits.
00: Mode 0: Normal (non-test mode) (D+ = X, D- = X)
01: Mode 1: Differential 1 Forced (D+ = 1, D- = 0)
10: Mode 2: Differential 0 Forced (D+ = 0, D- = 1)
11: Mode 3: Single-Ended 0 Forced (D+ = 0, D– = 0)
2
DFREC
Differential Receiver Bit
The state of this bit indicates the current differential value present on the D+ and D-
lines when PHYEN = 1.
0: Differential 0 signalling on the bus.
1: Differential 1 signalling on the bus.
1
0
Dp
Dn
D+ Signal Status.
This bit indicates the current logic level of the D+ pin.
0: D+ signal currently at logic 0.
1: D+ signal currently at logic 1.
D– Signal Status.
This bit indicates the current logic level of the D- pin.
0: D– signal currently at logic 0.
1: D– signal currently at logic 1.
Rev. 1.2
162
C8051T620/1/6/7 & C8051T320/1/2/3
23.3. USB Register Access
The USB0 controller registers listed in Table 23.2 are accessed through two SFRs: USB0 Address
(USB0ADR) and USB0 Data (USB0DAT). The USB0ADR register selects which USB register is targeted
by reads/writes of the USB0DAT register. See Figure 23.2.
Endpoint control/status registers are accessed by first writing the USB register INDEX with the target end-
point number. Once the target endpoint number is written to the INDEX register, the control/status registers
associated with the target endpoint may be accessed. See the “Indexed Registers” section of Table 23.2
for a list of endpoint control/status registers.
Important Note: The USB clock must be active when accessing USB registers.
8051
SFRs
USB Controller
Interrupt
Registers
FIFO
Access
Common
Registers
Index
USB0DAT
Register
Endpoint0 Control/
Status Registers
Endpoint1 Control/
Status Registers
Endpoint2 Control/
Status Registers
USB0ADR
Endpoint3 Control/
Status Registers
Figure 23.2. USB0 Register Access Scheme
163
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 23.2. USB0ADR: USB0 Indirect Address
Bit
7
6
5
4
3
2
1
0
BUSY
AUTORD
USBADDR[5:0]
R/W
Name
Type
Reset
R/W
0
R/W
0
0
0
0
0
0
0
SFR Address = 0x96
Bit
Name
Description
Write
Read
0: USB0DAT register data
7
BUSY
0: No effect.
1: A USB0 indirect regis- is valid.
USB0 Register Read
Busy Flag.
ter read is initiated at the 1: USB0 is busy access-
address specified by the ing an indirect register;
This bit is used during
indirect USB0 register
accesses.
USBADDR bits.
USB0DAT register data is
invalid.
6
AUTORD
USB0 Register Auto-read Flag.
This bit is used for block FIFO reads.
0: BUSY must be written manually for each USB0 indirect register read.
1: The next indirect register read will automatically be initiated when software
reads USB0DAT (USBADDR bits will not be changed).
5:0 USBADDR[5:0] USB0 Indirect Register Address Bits.
These bits hold a 6-bit address used to indirectly access the USB0 core registers.
Table 23.2 lists the USB0 core registers and their indirect addresses. Reads and
writes to USB0DAT will target the register indicated by the USBADDR bits.
Rev. 1.2
164
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 23.3. USB0DAT: USB0 Data
Bit
7
6
5
4
3
2
1
0
USB0DAT[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Address = 0x97
Bit Name
7:0 USB0DAT[7:0]
Description
Write
Read
Write Procedure:
1. Poll for BUSY
(USB0ADR.7) => 0.
2. Load the target USB0
register address into the
USBADDR bits in register
USB0ADR.
Read Procedure:
1. Poll for BUSY
(USB0ADR.7) => 0.
2. Load the target USB0
register address into the
USBADDR bits in register
USB0ADR.
USB0 Data Bits.
This SFR is used to indi-
rectly read and write
USB0 registers.
3. Write 1 to the BUSY bit
in register USB0ADR
(steps 2 and 3 can be per-
formed in the same write).
4. Poll for BUSY
3. Write data to USB0DAT.
4. Repeat (Step 2 may be
skipped when writing to
the same USB0 register).
(USB0ADR.7) => 0.
5. Read data from
USB0DAT.
6. Repeat from Step 2
(Step 2 may be skipped
when reading the same
USB0 register; Step 3 may
be skipped when the
AUTORD bit
(USB0ADR.6) is logic 1).
165
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
Table 23.2. USB0 Controller Registers
USB Register
Name
USB Register
Address
Description
Page Number
Interrupt Registers
IN1INT
OUT1INT
CMINT
IN1IE
OUT1IE
CMIE
0x02
0x04
0x06
0x07
0x09
0x0B
Endpoint0 and Endpoints1-3 IN Interrupt Flags
Endpoints1-3 OUT Interrupt Flags
Common USB Interrupt Flags
Endpoint0 and Endpoints1-3 IN Interrupt Enables
Endpoints1-3 OUT Interrupt Enables
Common USB Interrupt Enables
176
177
178
179
180
181
Common Registers
FADDR
POWER
FRAMEL
FRAMEH
INDEX
CLKREC
EENABLE
FIFOn
0x00
0x01
0x0C
0x0D
0x0E
Function Address
172
174
175
175
167
168
186
171
Power Management
Frame Number Low Byte
Frame Number High Byte
Endpoint Index Selection
Clock Recovery Control
Endpoint Enable
0x0F
0x1E
0x20-0x23
Endpoints0-3 FIFOs
Indexed Registers
E0CSR
EINCSRL
EINCSRH
EOUTCSRL
EOUTCSRH
E0CNT
Endpoint0 Control / Status
184
188
189
191
192
185
192
193
0x11
Endpoint IN Control / Status Low Byte
Endpoint IN Control / Status High Byte
Endpoint OUT Control / Status Low Byte
Endpoint OUT Control / Status High Byte
Number of Received Bytes in Endpoint0 FIFO
Endpoint OUT Packet Count Low Byte
Endpoint OUT Packet Count High Byte
0x12
0x14
0x15
0x16
0x17
EOUTCNTL
EOUTCNTH
Rev. 1.2
166
C8051T620/1/6/7 & C8051T320/1/2/3
USB Register Definition 23.4. INDEX: USB0 Endpoint Index
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
EPSEL[3:0]
R/W
R
0
R
0
R
0
R
0
0
0
0
0
USB Register Address = 0x0E
Bit
7:4
3:0
Name
Function
Unused
Read = 0000b. Write = don’t care.
EPSEL[3:0]
Endpoint Select Bits.
These bits select which endpoint is targeted when indexed USB0 registers are
accessed.
0000: Endpoint 0
0001: Endpoint 1
0010: Endpoint 2
0011: Endpoint 3
0100-1111: Reserved.
167
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
23.4. USB Clock Configuration
USB0 is capable of communication as a Full or Low Speed USB function. Communication speed is
selected via the SPEED bit in SFR USB0XCN. When operating as a Low Speed function, the USB0 clock
must be 6 MHz. When operating as a Full Speed function, the USB0 clock must be 48 MHz. Clock options
are described in Section “21. Oscillators and Clock Selection” on page 127. The USB0 clock is selected via
SFR CLKSEL (see SFR Definition 21.1).
Clock Recovery circuitry uses the incoming USB data stream to adjust the internal oscillator; this allows
the internal oscillator to meet the requirements for USB clock tolerance. Clock Recovery should be used in
the following configurations:
Communication Speed
USB Clock
Full Speed
Low Speed
Internal Oscillator
Internal Oscillator / 8
When operating USB0 as a Low Speed function with Clock Recovery, software must write 1 to the CRLOW
bit to enable Low Speed Clock Recovery. Clock Recovery is typically not necessary in Low Speed mode.
Single Step Mode can be used to help the Clock Recovery circuitry to lock when high noise levels are pres-
ent on the USB network. This mode is not required (or recommended) in typical USB environments.
USB Register Definition 23.5. CLKREC: Clock Recovery Control
Bit
7
6
5
4
3
2
1
0
CRE
CRSSEN CRLOW Reserved Reserved Reserved Reserved Reserved
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
R/W
1
R/W
1
R/W
1
USB Register Address = 0x0F
Bit
Name
Function
7
CRE
Clock Recovery Enable Bit.
This bit enables/disables the USB clock recovery feature.
0: Clock recovery disabled.
1: Clock recovery enabled.
6
5
CRSSEN Clock Recovery Single Step.
This bit forces the oscillator calibration into ‘single-step’ mode during clock
recovery.
0: Normal calibration mode.
1: Single step mode.
CRLOW Low Speed Clock Recovery Mode.
This bit must be set to 1 if clock recovery is used when operating as a Low Speed USB
device.
0: Full Speed Mode.
1: Low Speed Mode.
4:0 Reserved Read = Variable. Must Write = 01111b.
Rev. 1.2
168
C8051T620/1/6/7 & C8051T320/1/2/3
23.5. FIFO Management
1024 bytes of on-chip XRAM are used as FIFO space for USB0. This FIFO space is split between End-
points0-3 as shown in Figure 23.3. FIFO space allocated for Endpoints1-3 is configurable as IN, OUT, or
both (Split Mode: half IN, half OUT).
0x07FF
Endpoint0
(64 bytes)
0x07C0
0x07BF
Endpoint1
(128 bytes)
0x0740
0x073F
Configurable as
IN, OUT, or both (Split
Endpoint2
(256 bytes)
Mode)
0x0640
0x063F
Endpoint3
(512 bytes)
0x0440
0x043F
Free
(64 bytes)
0x0400
USB Clock Domain
System Clock Domain
0x03FF
User XRAM
(1024 bytes)
0x0000
Figure 23.3. C8051T620/1 and C8051T320/1/2/3 USB FIFO Allocation
169
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
0x13FF
Endpoint0
(64 bytes)
0x13C0
0x13BF
Endpoint1
(128 bytes)
0x1340
0x133F
Configurable as
IN, OUT, or both (Split
Endpoint2
(256 bytes)
Mode)
0x1240
0x123F
Endpoint3
(512 bytes)
0x1040
0x103F
Free
(64 bytes)
0x1000
USB Clock Domain
System Clock Domain
0x0FFF
0x0000
User XRAM
(3072 bytes, followed by
1024 bytes unused
space)
Figure 23.4. C8051T626/7 USB FIFO Allocation
23.5.1. FIFO Split Mode
The FIFO space for Endpoints1-3 can be split such that the upper half of the FIFO space is used by the IN
endpoint, and the lower half is used by the OUT endpoint. For example: if the Endpoint3 FIFO is configured
for Split Mode, the upper 256 bytes (0x0540 to 0x063F) are used by Endpoint3 IN and the lower 256 bytes
(0x0440 to 0x053F) are used by Endpoint3 OUT.
If an endpoint FIFO is not configured for split mode, that endpoint IN/OUT pair’s FIFOs are combined to
form a single IN or OUT FIFO. In this case only one direction of the endpoint IN/OUT pair may be used at
a time. The endpoint direction (IN/OUT) is determined by the DIRSEL bit in the corresponding endpoint’s
EINCSRH register (see SFR Definition 23.13).
23.5.2. FIFO Double Buffering
FIFO slots for Endpoints1-3 can be configured for double-buffered mode. In this mode, the maximum
packet size is halved and the FIFO may contain two packets at a time. This mode is available for End-
points1-3. When an endpoint is configured for split mode, double buffering may be enabled for the IN End-
point and/or the OUT endpoint. When split mode is not enabled, double-buffering may be enabled for the
entire endpoint FIFO. See Table 23.3 for a list of maximum packet sizes for each FIFO configuration.
Rev. 1.2
170
C8051T620/1/6/7 & C8051T320/1/2/3
Table 23.3. FIFO Configurations
Endpoint
Number
Split Mode
Enabled?
Maximum IN Packet Size
(Double Buffer Disabled /
Enabled)
Maximum OUT Packet Size
(Double Buffer Disabled /
Enabled)
0
1
N/A
N
Y
N
Y
64
128 / 64
64 / 32
64 / 32
128 / 64
256 / 128
256 / 128
512 / 256
2
3
128 / 64
N
Y
256 / 128
23.5.1. FIFO Access
Each endpoint FIFO is accessed through a corresponding FIFOn register. A read of an endpoint FIFOn
register unloads one byte from the FIFO; a write of an endpoint FIFOn register loads one byte into the end-
point FIFO. When an endpoint FIFO is configured for Split Mode, a read of the endpoint FIFOn register
unloads one byte from the OUT endpoint FIFO; a write of the endpoint FIFOn register loads one byte into
the IN endpoint FIFO.
USB Register Definition 23.6. FIFOn: USB0 Endpoint FIFO Access
Bit
7
6
5
4
3
2
1
0
FIFODATA[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
USB Register Address = 0x20-0x23
Bit Name
7:0 FIFODATA[7:0] Endpoint FIFO Access Bits.
Function
USB Addresses 0x20-0x23 provide access to the 4 pairs of endpoint FIFOs:
0x20: Endpoint 0
0x21: Endpoint 1
0x22: Endpoint 2
0x23: Endpoint 3
Writing to the FIFO address loads data into the IN FIFO for the corresponding
endpoint. Reading from the FIFO address unloads data from the OUT FIFO for
the corresponding endpoint.
171
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
23.6. Function Addressing
The FADDR register holds the current USB0 function address. Software should write the host-assigned 7-
bit function address to the FADDR register when received as part of a SET_ADDRESS command. A new
address written to FADDR will not take effect (USB0 will not respond to the new address) until the end of
the current transfer (typically following the status phase of the SET_ADDRESS command transfer). The
UPDATE bit (FADDR.7) is set to 1 by hardware when software writes a new address to the FADDR regis-
ter. Hardware clears the UPDATE bit when the new address takes effect as described above.
USB Register Definition 23.7. FADDR: USB0 Function Address
Bit
7
6
5
4
3
2
1
0
UPDATE
FADDR[6:0]
Name
Type
Reset
R
0
R/W
0
0
0
0
0
0
0
USB Register Address = 0x00
Bit
Name
Function
7
UPDATE Function Address Update Bit.
Set to 1 when software writes the FADDR register. USB0 clears this bit to 0 when the
new address takes effect.
0: The last address written to FADDR is in effect.
1: The last address written to FADDR is not yet in effect.
6:0 FADDR[6:0] Function Address Bits.
Holds the 7-bit function address for USB0. This address should be written by software
when the SET_ADDRESS standard device request is received on Endpoint0. The
new address takes effect when the device request completes.
Rev. 1.2
172
C8051T620/1/6/7 & C8051T320/1/2/3
23.7. Function Configuration and Control
The USB register POWER (USB Register Definition 23.8) is used to configure and control USB0 at the
device level (enable/disable, Reset/Suspend/Resume handling, etc.).
USB Reset: The USBRST bit (POWER.3) is set to 1 by hardware when Reset signaling is detected on the
bus. Upon this detection, the following occur:
1. The USB0 Address is reset (FADDR = 0x00).
2. Endpoint FIFOs are flushed.
3. Control/status registers are reset to 0x00 (E0CSR, EINCSRL, EINCSRH, EOUTCSRL, EOUTCSRH).
4. USB register INDEX is reset to 0x00.
5. All USB interrupts (excluding the Suspend interrupt) are enabled and their corresponding flags cleared.
6. A USB Reset interrupt is generated if enabled.
Writing a 1 to the USBRST bit will generate an asynchronous USB0 reset. All USB registers are reset to
their default values following this asynchronous reset.
Suspend Mode: With Suspend Detection enabled (SUSEN = 1), USB0 will enter Suspend Mode when
Suspend signaling is detected on the bus. An interrupt will be generated if enabled (SUSINTE = 1). The
Suspend Interrupt Service Routine (ISR) should perform application-specific configuration tasks such as
disabling appropriate peripherals and/or configuring clock sources for low power modes. See Section
“21.3. Programmable Internal High-Frequency (H-F) Oscillator” on page 130 for more details on internal
oscillator configuration, including the Suspend mode feature of the internal oscillator.
USB0 exits Suspend mode when any of the following occur: (1) Resume signaling is detected or gener-
ated, (2) Reset signaling is detected, or (3) a device or USB reset occurs. If suspended, the internal oscil-
lator will exit Suspend mode upon any of the above listed events.
Resume Signaling: USB0 will exit Suspend mode if Resume signaling is detected on the bus. A Resume
interrupt will be generated upon detection if enabled (RESINTE = 1). Software may force a Remote
Wakeup by writing 1 to the RESUME bit (POWER.2). When forcing a Remote Wakeup, software should
write RESUME = 0 to end Resume signaling 10-15 ms after the Remote Wakeup is initiated (RESUME =
1).
ISO Update: When software writes 1 to the ISOUP bit (POWER.7), the ISO Update function is enabled.
With ISO Update enabled, new packets written to an ISO IN endpoint will not be transmitted until a new
Start-Of-Frame (SOF) is received. If the ISO IN endpoint receives an IN token before a SOF, USB0 will
transmit a zero-length packet. When ISOUP = 1, ISO Update is enabled for all ISO endpoints.
USB Enable: USB0 is disabled following a Power-On-Reset (POR). USB0 is enabled by clearing the
USBINH bit (POWER.4). Once written to 0, the USBINH can only be set to 1 by one of the following: (1) a
Power-On-Reset (POR), or (2) an asynchronous USB0 reset generated by writing 1 to the USBRST bit
(POWER.3).
Software should perform all USB0 configuration before enabling USB0. The configuration sequence
should be performed as follows:
1. Select and enable the USB clock source.
2. Reset USB0 by writing USBRST= 1.
3. Configure and enable the USB Transceiver.
4. Perform any USB0 function configuration (interrupts, Suspend detect).
5. Enable USB0 by writing USBINH = 0.
173
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
USB Register Definition 23.8. POWER: USB0 Power
Bit
7
6
5
4
3
2
1
0
ISOUD
USBINH USBRST RESUME SUSMD
SUSEN
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
1
R/W
0
R/W
0
R
0
R/W
0
USB Register Address = 0x01
Bit
Name
Function
7
ISOUD ISO Update Bit.
This bit affects all IN Isochronous endpoints.
0: When software writes INPRDY = 1, USB0 will send the packet when the next IN token
is received.
1: When software writes INPRDY = 1, USB0 will wait for a SOF token before sending the
packet. If an IN token is received before a SOF token, USB0 will send a zero-length data
packet.
6:5 Unused Read = 00b. Write = don’t care.
4
USBINH USB0 Inhibit Bit.
This bit is set to 1 following a power-on reset (POR) or an asynchronous USB0 reset.
Software should clear this bit after all USB0 transceiver initialization is complete. Soft-
ware cannot set this bit to 1.
0: USB0 enabled.
1: USB0 inhibited. All USB traffic is ignored.
3
2
USBRST Reset Detect.
Read:
Write:
0: Reset signaling is not present. Writing 1 to this bit forces an
1: Reset signaling detected on
the bus.
asynchronous USB0 reset.
RESUME Force Resume.
Writing a 1 to this bit while in Suspend mode (SUSMD = 1) forces USB0 to generate
Resume signaling on the bus (a remote wakeup event). Software should write RESUME
= 0 after 10 to 15 ms to end the Resume signaling. An interrupt is generated, and hard-
ware clears SUSMD, when software writes RESUME = 0.
1
0
SUSMD Suspend Mode.
Set to 1 by hardware when USB0 enters suspend mode. Cleared by hardware when soft-
ware writes RESUME = 0 (following a remote wakeup) or reads the CMINT register after
detection of Resume signaling on the bus.
0: USB0 not in suspend mode.
1: USB0 in suspend mode.
SUSEN Suspend Detection Enable.
0: Suspend detection disabled. USB0 will ignore suspend signaling on the bus.
1: Suspend detection enabled. USB0 will enter suspend mode if it detects suspend sig-
naling on the bus.
Rev. 1.2
174
C8051T620/1/6/7 & C8051T320/1/2/3
USB Register Definition 23.9. FRAMEL: USB0 Frame Number Low
Bit
7
6
5
4
3
2
1
0
FRMEL[7:0]
Name
Type
Reset
R
0
0
0
0
0
0
0
0
USB Register Address = 0x0C
Bit Name
7:0 FRMEL[7:0] Frame Number Low Bits.
Function
This register contains bits 7-0 of the last received frame number.
USB Register Definition 23.10. FRAMEH: USB0 Frame Number High
Bit
7
6
5
4
3
2
1
0
FRMEH[2:0]
Name
Type
Reset
R
0
R
0
R
0
R
0
R
0
R
0
0
0
USB Register Address = 0x0D
Bit
Name
Function
7:3
Unused
Read = 00000b. Write = don’t care.
2:0 FRMEH[2:0]
Frame Number High Bits.
This register contains bits 10-8 of the last received frame number.
175
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
23.8. Interrupts
The read-only USB0 interrupt flags are located in the USB registers shown in USB Register
Definition 23.11 through USB Register Definition 23.13. The associated interrupt enable bits are located in
the USB registers shown in USB Register Definition 23.14 through USB Register Definition 23.16. A USB0
interrupt is generated when any of the USB interrupt flags is set to 1. The USB0 interrupt is enabled via the
EIE1 SFR (see Section “17. Interrupts” on page 101).
Important Note: Reading a USB interrupt flag register resets all flags in that register to 0.
USB Register Definition 23.11. IN1INT: USB0 IN Endpoint Interrupt
Bit
7
6
5
4
3
2
1
0
IN3
IN2
IN1
EP0
Name
Type
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
USB Register Address = 0x02
Bit
Name
Function
7:4
3
Unused
IN3
Read = 0000b. Write = don’t care.
IN Endpoint 3 Interrupt-Pending Flag.
This bit is cleared when software reads the IN1INT register.
0: IN Endpoint 3 interrupt inactive.
1: IN Endpoint 3 interrupt active.
2
1
0
IN2
IN1
IN Endpoint 2 Interrupt-Pending Flag.
This bit is cleared when software reads the IN1INT register.
0: IN Endpoint 2 interrupt inactive.
1: IN Endpoint 2 interrupt active.
IN Endpoint 1 Interrupt-Pending Flag.
This bit is cleared when software reads the IN1INT register.
0: IN Endpoint 1 interrupt inactive.
1: IN Endpoint 1 interrupt active.
EP0
Endpoint 0 Interrupt-Pending Flag.
This bit is cleared when software reads the IN1INT register.
0: Endpoint 0 interrupt inactive.
1: Endpoint 0 interrupt active.
Rev. 1.2
176
C8051T620/1/6/7 & C8051T320/1/2/3
USB Register Definition 23.12. OUT1INT: USB0 OUT Endpoint Interrupt
Bit
7
6
5
4
3
2
1
0
OUT3
OUT2
OUT1
Name
Type
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
USB Register Address = 0x04
Bit
Name
Function
7:4
3
Unused
OUT3
Read = 0000b. Write = don’t care.
OUT Endpoint 3 Interrupt-pending Flag.
This bit is cleared when software reads the OUT1INT register.
0: OUT Endpoint 3 interrupt inactive.
1: OUT Endpoint 3 interrupt active.
2
1
0
OUT2
OUT1
OUT Endpoint 2 Interrupt-pending Flag.
This bit is cleared when software reads the OUT1INT register.
0: OUT Endpoint 2 interrupt inactive.
1: OUT Endpoint 2 interrupt active.
OUT Endpoint 1 Interrupt-pending Flag.
This bit is cleared when software reads the OUT1INT register.
0: OUT Endpoint 1 interrupt inactive.
1: OUT Endpoint 1 interrupt active.
Unused
Read = 0b. Write = don’t care.
177
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
USB Register Definition 23.13. CMINT: USB0 Common Interrupt
Bit
7
6
5
4
3
2
1
0
SOF
RSTINT
RSUINT
SUSINT
Name
Type
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
USB Register Address = 0x06
Bit
Name
Function
7:4
3
Unused
SOF
Read = 0000b. Write = don’t care.
Start of Frame Interrupt Flag.
Set by hardware when a SOF token is received. This interrupt event is synthesized by
hardware: an interrupt will be generated when hardware expects to receive a SOF
event, even if the actual SOF signal is missed or corrupted.
This bit is cleared when software reads the CMINT register.
0: SOF interrupt inactive.
1: SOF interrupt active.
2
1
RSTINT
RSUINT
Reset Interrupt-pending Flag.
Set by hardware when Reset signaling is detected on the bus.
This bit is cleared when software reads the CMINT register.
0: Reset interrupt inactive.
1: Reset interrupt active.
Resume Interrupt-pending Flag.
Set by hardware when Resume signaling is detected on the bus while USB0 is in sus-
pend mode.
This bit is cleared when software reads the CMINT register.
0: Resume interrupt inactive.
1: Resume interrupt active.
0
SUSINT
Suspend Interrupt-pending Flag.
When Suspend detection is enabled (bit SUSEN in register POWER), this bit is set by
hardware when Suspend signaling is detected on the bus. This bit is cleared when
software reads the CMINT register.
0: Suspend interrupt inactive.
1: Suspend interrupt active.
Rev. 1.2
178
C8051T620/1/6/7 & C8051T320/1/2/3
USB Register Definition 23.14. IN1IE: USB0 IN Endpoint Interrupt Enable
Bit
7
6
5
4
3
2
1
0
IN3E
IN2E
IN1E
EP0E
Name
Type
Reset
R
0
R
0
R
0
R
0
R/W
1
R/W
1
R/W
1
R/W
1
USB Register Address = 0x07
Bit
Name
Function
7:4
3
Unused
IN3E
Read = 0000b. Write = don’t care.
IN Endpoint 3 Interrupt Enable.
0: IN Endpoint 3 interrupt disabled.
1: IN Endpoint 3 interrupt enabled.
2
1
0
IN2E
IN1E
EP0E
IN Endpoint 2 Interrupt Enable.
0: IN Endpoint 2 interrupt disabled.
1: IN Endpoint 2 interrupt enabled.
IN Endpoint 1 Interrupt Enable.
0: IN Endpoint 1 interrupt disabled.
1: IN Endpoint 1 interrupt enabled.
Endpoint 0 Interrupt Enable.
0: Endpoint 0 interrupt disabled.
1: Endpoint 0 interrupt enabled.
179
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
USB Register Definition 23.15. OUT1IE: USB0 OUT Endpoint Interrupt Enable
Bit
7
6
5
4
3
2
1
0
OUT3E
OUT2E
OUT1E
Name
Type
Reset
R
0
R
0
R
0
R
0
R/W
1
R/W
1
R/W
1
R
0
USB Register Address = 0x09
Bit
Name
Function
7:4
3
Unused
OUT3E
Read = 0000b. Write = don’t care.
OUT Endpoint 3 Interrupt Enable.
0: OUT Endpoint 3 interrupt disabled.
1: OUT Endpoint 3 interrupt enabled.
2
1
0
OUT2E
OUT1E
Unused
OUT Endpoint 2 Interrupt Enable.
0: OUT Endpoint 2 interrupt disabled.
1: OUT Endpoint 2 interrupt enabled.
OUT Endpoint 1 Interrupt Enable.
0: OUT Endpoint 1 interrupt disabled.
1: OUT Endpoint 1 interrupt enabled.
Read = 0b. Write = don’t care.
Rev. 1.2
180
C8051T620/1/6/7 & C8051T320/1/2/3
USB Register Definition 23.16. CMIE: USB0 Common Interrupt Enable
Bit
7
6
5
4
3
2
1
0
SOFE
RSTINTE RSUINTE SUSINTE
Name
Type
Reset
R
0
R
0
R
0
R
0
R/W
0
R/W
1
R/W
1
R/W
0
USB Register Address = 0x0B
Bit
Name
Function
7:4
3
Unused
SOFE
Read = 0000b. Write = don’t care.
Start of Frame Interrupt Enable.
0: SOF interrupt disabled.
1: SOF interrupt enabled.
2
1
0
RSTINTE
RSUINTE
SUSINTE
Reset Interrupt Enable.
0: Reset interrupt disabled.
1: Reset interrupt enabled.
Resume Interrupt Enable.
0: Resume interrupt disabled.
1: Resume interrupt enabled.
Suspend Interrupt Enable.
0: Suspend interrupt disabled.
1: Suspend interrupt enabled.
23.9. The Serial Interface Engine
The Serial Interface Engine (SIE) performs all low level USB protocol tasks, interrupting the processor
when data has successfully been transmitted or received. When receiving data, the SIE will interrupt the
processor when a complete data packet has been received; appropriate handshaking signals are automat-
ically generated by the SIE. When transmitting data, the SIE will interrupt the processor when a complete
data packet has been transmitted and the appropriate handshake signal has been received.
The SIE will not interrupt the processor when corrupted/erroneous packets are received.
23.10. Endpoint0
Endpoint0 is managed through the USB register E0CSR (USB Register Definition 23.18). The INDEX reg-
ister must be loaded with 0x00 to access the E0CSR register.
An Endpoint0 interrupt is generated when:
1. A data packet (OUT or SETUP) has been received and loaded into the Endpoint0 FIFO. The OPRDY
bit (E0CSR.0) is set to 1 by hardware.
2. An IN data packet has successfully been unloaded from the Endpoint0 FIFO and transmitted to the
host; INPRDY is reset to 0 by hardware.
3. An IN transaction is completed (this interrupt generated during the status stage of the transaction).
4. Hardware sets the STSTL bit (E0CSR.2) after a control transaction ended due to a protocol violation.
181
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
5. Hardware sets the SUEND bit (E0CSR.4) because a control transfer ended before firmware sets the
DATAEND bit (E0CSR.3).
The E0CNT register (USB Register Definition 23.11) holds the number of received data bytes in the End-
point0 FIFO.
Hardware will automatically detect protocol errors and send a STALL condition in response. Firmware may
force a STALL condition to abort the current transfer. When a STALL condition is generated, the STSTL bit
will be set to 1 and an interrupt generated. The following conditions will cause hardware to generate a
STALL condition:
1. The host sends an OUT token during a OUT data phase after the DATAEND bit has been set to 1.
2. The host sends an IN token during an IN data phase after the DATAEND bit has been set to 1.
3. The host sends a packet that exceeds the maximum packet size for Endpoint0.
4. The host sends a non-zero length DATA1 packet during the status phase of an IN transaction.
Firmware sets the SDSTL bit (E0CSR.5) to 1.
23.10.1. Endpoint0 SETUP Transactions
All control transfers must begin with a SETUP packet. SETUP packets are similar to OUT packets, contain-
ing an 8-byte data field sent by the host. Any SETUP packet containing a command field of anything other
than 8 bytes will be automatically rejected by USB0. An Endpoint0 interrupt is generated when the data
from a SETUP packet is loaded into the Endpoint0 FIFO. Software should unload the command from the
Endpoint0 FIFO, decode the command, perform any necessary tasks, and set the SOPRDY bit to indicate
that it has serviced the OUT packet.
23.10.2. Endpoint0 IN Transactions
When a SETUP request is received that requires USB0 to transmit data to the host, one or more IN
requests will be sent by the host. For the first IN transaction, firmware should load an IN packet into the
Endpoint0 FIFO, and set the INPRDY bit (E0CSR.1). An interrupt will be generated when an IN packet is
transmitted successfully. Note that no interrupt will be generated if an IN request is received before firm-
ware has loaded a packet into the Endpoint0 FIFO. If the requested data exceeds the maximum packet
size for Endpoint0 (as reported to the host), the data should be split into multiple packets; each packet
should be of the maximum packet size excluding the last (residual) packet. If the requested data is an inte-
ger multiple of the maximum packet size for Endpoint0, the last data packet should be a zero-length packet
signaling the end of the transfer. Firmware should set the DATAEND bit to 1 after loading into the End-
point0 FIFO the last data packet for a transfer.
Upon reception of the first IN token for a particular control transfer, Endpoint0 is said to be in Transmit
Mode. In this mode, only IN tokens should be sent by the host to Endpoint0. The SUEND bit (E0CSR.4) is
set to 1 if a SETUP or OUT token is received while Endpoint0 is in Transmit Mode.
Endpoint0 will remain in Transmit Mode until any of the following occur:
1. USB0 receives an Endpoint0 SETUP or OUT token.
2. Firmware sends a packet less than the maximum Endpoint0 packet size.
3. Firmware sends a zero-length packet.
Firmware should set the DATAEND bit (E0CSR.3) to 1 when performing (2) and (3) above.
The SIE will transmit a NAK in response to an IN token if there is no packet ready in the IN FIFO (INPRDY
= 0).
Rev. 1.2
182
C8051T620/1/6/7 & C8051T320/1/2/3
23.10.3. Endpoint0 OUT Transactions
When a SETUP request is received that requires the host to transmit data to USB0, one or more OUT
requests will be sent by the host. When an OUT packet is successfully received by USB0, hardware will set
the OPRDY bit (E0CSR.0) to 1 and generate an Endpoint0 interrupt. Following this interrupt, firmware
should unload the OUT packet from the Endpoint0 FIFO and set the SOPRDY bit (E0CSR.6) to 1.
If the amount of data required for the transfer exceeds the maximum packet size for Endpoint0, the data
will be split into multiple packets. If the requested data is an integer multiple of the maximum packet size
for Endpoint0 (as reported to the host), the host will send a zero-length data packet signaling the end of the
transfer.
Upon reception of the first OUT token for a particular control transfer, Endpoint0 is said to be in Receive
Mode. In this mode, only OUT tokens should be sent by the host to Endpoint0. The SUEND bit (E0CSR.4)
is set to 1 if a SETUP or IN token is received while Endpoint0 is in Receive Mode.
Endpoint0 will remain in Receive mode until:
1. The SIE receives a SETUP or IN token.
2. The host sends a packet less than the maximum Endpoint0 packet size.
3. The host sends a zero-length packet.
Firmware should set the DATAEND bit (E0CSR.3) to 1 when the expected amount of data has been
received. The SIE will transmit a STALL condition if the host sends an OUT packet after the DATAEND bit
has been set by firmware. An interrupt will be generated with the STSTL bit (E0CSR.2) set to 1 after the
STALL is transmitted.
183
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
USB Register Definition 23.17. E0CSR: USB0 Endpoint0 Control
Bit
7
6
5
4
3
2
1
0
SSUEND SOPRDY
SDSTL
SUEND DATAEND
STSTL
INPRDY
OPRDY
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R
0
R/W
0
R/W
0
R/W
0
R
0
USB Register Address = 0x11
Bit
Name
Description
Write
Read
This bit always reads 0.
7
SSUEND
Software should set this bit to 1
after servicing a Setup End (bit
SUEND) event. Hardware clears
the SUEND bit when software
writes 1 to SSUEND.
Serviced Setup End
Bit.
6
SOPRDY
Software should write 1 to this bit This bit always reads 0.
after servicing a received
Serviced OPRDY Bit.
Endpoint0 packet. The OPRDY bit
will be cleared by a write of 1 to
SOPRDY.
5
4
3
SDSTL
SUEND
Send Stall Bit.
Software can write 1 to this bit to terminate the current transfer (due to an error condi-
tion, unexpected transfer request, etc.). Hardware will clear this bit to 0 when the STALL
handshake is transmitted.
Setup End Bit.
Hardware sets this read-only bit to 1 when a control transaction ends before software
has written 1 to the DATAEND bit. Hardware clears this bit when software writes 1 to
SSUEND.
DATAEND
Data End Bit.
Software should write 1 to this bit: 1) When writing 1 to INPRDY for the last outgoing
data packet. 2) When writing 1 to INPRDY for a zero-length data packet. 3) When writ-
ing 1 to SOPRDY after servicing the last incoming data packet.
This bit is automatically cleared by hardware.
2
1
STSTL
Sent Stall Bit.
Hardware sets this bit to 1 after transmitting a STALL handshake signal. This flag must
be cleared by software.
INPRDY
IN Packet Ready Bit.
Software should write 1 to this bit after loading a data packet into the Endpoint0 FIFO
for transmit. Hardware clears this bit and generates an interrupt under either of the fol-
lowing conditions: 1) The packet is transmitted. 2) The packet is overwritten by an
incoming SETUP packet. 3) The packet is overwritten by an incoming OUT packet.
0
OPRDY
OUT Packet Ready Bit.
Hardware sets this read-only bit and generates an interrupt when a data packet has
been received. This bit is cleared only when software writes 1 to the SOPRDY bit.
Rev. 1.2
184
C8051T620/1/6/7 & C8051T320/1/2/3
USB Register Definition 23.18. E0CNT: USB0 Endpoint0 Data Count
Bit
7
6
5
4
3
2
1
0
E0CNT[6:0]
Name
Type
Reset
R
0
R
0
0
0
0
0
0
0
USB Register Address = 0x16
Bit
Name
Function
7
Unused
Read = 0b. Write = don’t care.
6:0 E0CNT[6:0]
Endpoint 0 Data Count.
This 7-bit number indicates the number of received data bytes in the Endpoint 0
FIFO. This number is only valid while bit OPRDY is a 1.
23.11. Configuring Endpoints1-3
Endpoints1-3 are configured and controlled through their own sets of the following control/status registers:
IN registers EINCSRL and EINCSRH, and OUT registers EOUTCSRL and EOUTCSRH. Only one set of
endpoint control/status registers is mapped into the USB register address space at a time, defined by the
contents of the INDEX register (USB Register Definition 23.4).
Endpoints1-3 can be configured as IN, OUT, or both IN/OUT (Split Mode) as described in Section 23.5.1.
The endpoint mode (Split/Normal) is selected via the SPLIT bit in register EINCSRH.
When SPLIT = 1, the corresponding endpoint FIFO is split, and both IN and OUT pipes are available.
When SPLIT = 0, the corresponding endpoint functions as either IN or OUT; the endpoint direction is
selected by the DIRSEL bit in register EINCSRH.
Endpoints1-3 can be disabled individually by the corresponding bits in the ENABLE register. When an End-
point is disabled, it will not respond to bus traffic or stall the bus. All Endpoints are enabled by default.
185
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
USB Register Definition 23.19. EENABLE: USB0 Endpoint Enable
Bit
7
6
5
4
3
2
1
0
EEN3
EEN2
EEN1
Reserved
Name
Type
Reset
R
1
R
1
R
1
R
1
R/W
1
R/W
1
R/W
1
R/W
1
USB Register Address = 0x1E
Bit
Name
Function
7:4
3
Unused
EEN3
Read = 1111b. Write = don’t care.
Endpoint 3 Enable.
This bit enables/disables Endpoint 3.
0: Endpoint 3 is disabled (no NACK, ACK, or STALL on the USB network).
1: Endpoint 3 is enabled (normal).
2
1
0
EEN2
EEN1
Endpoint 2 Enable.
This bit enables/disables Endpoint 2.
0: Endpoint 2 is disabled (no NACK, ACK, or STALL on the USB network).
1: Endpoint 2 is enabled (normal).
Endpoint 1 Enable.
This bit enables/disables Endpoint 1.
0: Endpoint 1 is disabled (no NACK, ACK, or STALL on the USB network).
1: Endpoint 1 is enabled (normal).
Reserved Read = 1b. Must Write 1b.
23.12. Controlling Endpoints1-3 IN
Endpoints1-3 IN are managed via USB registers EINCSRL and EINCSRH. All IN endpoints can be used
for Interrupt, Bulk, or Isochronous transfers. Isochronous (ISO) mode is enabled by writing 1 to the ISO bit
in register EINCSRH. Bulk and Interrupt transfers are handled identically by hardware.
An Endpoint1-3 IN interrupt is generated by any of the following conditions:
1. An IN packet is successfully transferred to the host.
2. Software writes 1 to the FLUSH bit (EINCSRL.3) when the target FIFO is not empty.
3. Hardware generates a STALL condition.
23.12.1. Endpoints1-3 IN Interrupt or Bulk Mode
When the ISO bit (EINCSRH.6) = 0 the target endpoint operates in Bulk or Interrupt Mode. Once an end-
point has been configured to operate in Bulk/Interrupt IN mode (typically following an Endpoint0 SET_IN-
TERFACE command), firmware should load an IN packet into the endpoint IN FIFO and set the INPRDY
bit (EINCSRL.0). Upon reception of an IN token, hardware will transmit the data, clear the INPRDY bit, and
generate an interrupt.
Writing 1 to INPRDY without writing any data to the endpoint FIFO will cause a zero-length packet to be
transmitted upon reception of the next IN token.
A Bulk or Interrupt pipe can be shut down (or Halted) by writing 1 to the SDSTL bit (EINCSRL.4). While
SDSTL = 1, hardware will respond to all IN requests with a STALL condition. Each time hardware gener-
Rev. 1.2
186
C8051T620/1/6/7 & C8051T320/1/2/3
ates a STALL condition, an interrupt will be generated and the STSTL bit (EINCSRL.5) set to 1. The
STSTL bit must be reset to 0 by firmware.
Hardware will automatically reset INPRDY to 0 when a packet slot is open in the endpoint FIFO. Note that
if double buffering is enabled for the target endpoint, it is possible for firmware to load two packets into the
IN FIFO at a time. In this case, hardware will reset INPRDY to 0 immediately after firmware loads the first
packet into the FIFO and sets INPRDY to 1. An interrupt will not be generated in this case; an interrupt will
only be generated when a data packet is transmitted.
When firmware writes 1 to the FCDT bit (EINCSRH.3), the data toggle for each IN packet will be toggled
continuously, regardless of the handshake received from the host. This feature is typically used by Inter-
rupt endpoints functioning as rate feedback communication for Isochronous endpoints. When FCDT = 0,
the data toggle bit will only be toggled when an ACK is sent from the host in response to an IN packet.
23.12.2. Endpoints1-3 IN Isochronous Mode
When the ISO bit (EINCSRH.6) is set to 1, the target endpoint operates in Isochronous (ISO) mode. Once
an endpoint has been configured for ISO IN mode, the host will send one IN token (data request) per
frame; the location of data within each frame may vary. Because of this, it is recommended that double
buffering be enabled for ISO IN endpoints.
Hardware will automatically reset INPRDY (EINCSRL.0) to 0 when a packet slot is open in the endpoint
FIFO. Note that if double buffering is enabled for the target endpoint, it is possible for firmware to load two
packets into the IN FIFO at a time. In this case, hardware will reset INPRDY to 0 immediately after firm-
ware loads the first packet into the FIFO and sets INPRDY to 1. An interrupt will not be generated in this
case; an interrupt will only be generated when a data packet is transmitted.
If there is not a data packet ready in the endpoint FIFO when USB0 receives an IN token from the host,
USB0 will transmit a zero-length data packet and set the UNDRUN bit (EINCSRL.2) to 1.
The ISO Update feature (see Section 23.7) can be useful in starting a double buffered ISO IN endpoint. If
the host has already set up the ISO IN pipe (has begun transmitting IN tokens) when firmware writes the
first data packet to the endpoint FIFO, the next IN token may arrive and the first data packet sent before
firmware has written the second (double buffered) data packet to the FIFO. The ISO Update feature
ensures that any data packet written to the endpoint FIFO will not be transmitted during the current frame;
the packet will only be sent after a SOF signal has been received.
187
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
USB Register Definition 23.20. EINCSRL: USB0 IN Endpoint Control Low
Bit
7
6
5
4
3
2
1
0
CLRDT
STSTL
SDSTL
FLUSH
UNDRUN FIFONE
INPRDY
Name
Type
Reset
R
0
W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
USB Register Address = 0x11
Bit
Name
Description
Write
Read
This bit always reads 0.
7
6
Unused Read = 0b. Write = don’t care.
CLRDT
STSTL
Software should write 1 to
this bit to reset the IN End-
point data toggle to 0.
Clear Data Toggle Bit.
5
4
Sent Stall Bit.
Hardware sets this bit to 1 when a STALL handshake signal is transmitted. The FIFO is
flushed, and the INPRDY bit cleared. This flag must be cleared by software.
SDSTL
FLUSH
Send Stall.
Software should write 1 to this bit to generate a STALL handshake in response to an IN
token. Software should write 0 to this bit to terminate the STALL signal. This bit has no
effect in ISO mode.
3
2
FIFO Flush Bit.
Writing a 1 to this bit flushes the next packet to be transmitted from the IN Endpoint
FIFO. The FIFO pointer is reset and the INPRDY bit is cleared. If the FIFO contains mul-
tiple packets, software must write 1 to FLUSH for each packet. Hardware resets the
FLUSH bit to 0 when the FIFO flush is complete.
UNDRUN
Data Underrun Bit.
The function of this bit depends on the IN Endpoint mode:
ISO: Set when a zero-length packet is sent after an IN token is received while bit
INPRDY = 0.
Interrupt/Bulk: Set when a NAK is returned in response to an IN token.
This bit must be cleared by software.
1
0
FIFONE
INPRDY
FIFO Not Empty.
0: The IN Endpoint FIFO is empty.
1. The IN Endpoint FIFO contains one or more packets.
In Packet Ready.
Software should write 1 to this bit after loading a data packet into the IN Endpoint FIFO.
Hardware clears INPRDY due to any of the following: 1) A data packet is transmitted. 2)
Double buffering is enabled (DBIEN = 1) and there is an open FIFO packet slot. 3) If the
endpoint is in Isochronous Mode (ISO = 1) and ISOUD = 1, INPRDY will read 0 until the
next SOF is received.
Note: An interrupt (if enabled) will be generated when hardware clears INPRDY as a result of a
packet being transmitted.
Rev. 1.2
188
C8051T620/1/6/7 & C8051T320/1/2/3
USB Register Definition 23.21. EINCSRH: USB0 IN Endpoint Control High
Bit
7
6
5
4
3
2
1
0
DBIEN
ISO
DIRSEL
FCDT
SPLIT
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R
0
R/W
0
R/W
0
R
0
R
0
USB Register Address = 0x12
Bit
Name
Function
7
DBIEN
IN Endpoint Double-buffer Enable.
0: Double-buffering disabled for the selected IN endpoint.
1: Double-buffering enabled for the selected IN endpoint.
6
5
ISO
Isochronous Transfer Enable.
This bit enables/disables isochronous transfers on the current endpoint.
0: Endpoint configured for bulk/interrupt transfers.
1: Endpoint configured for isochronous transfers.
DIRSEL
Endpoint Direction Select.
This bit is valid only when the selected FIFO is not split (SPLIT = 0).
0: Endpoint direction selected as OUT.
1: Endpoint direction selected as IN.
4
3
Unused Read = 0b. Write = don’t care.
FCDT
Force Data Toggle Bit.
0: Endpoint data toggle switches only when an ACK is received following a data packet
transmission.
1: Endpoint data toggle forced to switch after every data packet is transmitted, regard-
less of ACK reception.
2
SPLIT
FIFO Split Enable.
When SPLIT = 1, the selected endpoint FIFO is split. The upper half of the selected
FIFO is used by the IN endpoint; the lower half of the selected FIFO is used by the OUT
endpoint.
1:0 Unused Read = 00b. Write = don’t care.
23.13. Controlling Endpoints1-3 OUT
Endpoints1-3 OUT are managed via USB registers EOUTCSRL and EOUTCSRH. All OUT endpoints can
be used for Interrupt, Bulk, or Isochronous transfers. Isochronous (ISO) mode is enabled by writing 1 to the
ISO bit in register EOUTCSRH. Bulk and Interrupt transfers are handled identically by hardware.
An Endpoint1-3 OUT interrupt may be generated by the following:
1. Hardware sets the OPRDY bit (EINCSRL.0) to 1.
2. Hardware generates a STALL condition.
189
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
23.13.1. Endpoints1-3 OUT Interrupt or Bulk Mode
When the ISO bit (EOUTCSRH.6) = 0 the target endpoint operates in Bulk or Interrupt mode. Once an end-
point has been configured to operate in Bulk/Interrupt OUT mode (typically following an Endpoint0
SET_INTERFACE command), hardware will set the OPRDY bit (EOUTCSRL.0) to 1 and generate an
interrupt upon reception of an OUT token and data packet. The number of bytes in the current OUT data
packet (the packet ready to be unloaded from the FIFO) is given in the EOUTCNTH and EOUTCNTL reg-
isters. In response to this interrupt, firmware should unload the data packet from the OUT FIFO and reset
the OPRDY bit to 0.
A Bulk or Interrupt pipe can be shut down (or Halted) by writing 1 to the SDSTL bit (EOUTCSRL.5). While
SDSTL = 1, hardware will respond to all OUT requests with a STALL condition. Each time hardware gener-
ates a STALL condition, an interrupt will be generated and the STSTL bit (EOUTCSRL.6) set to 1. The
STSTL bit must be reset to 0 by firmware.
Hardware will automatically set OPRDY when a packet is ready in the OUT FIFO. Note that if double buff-
ering is enabled for the target endpoint, it is possible for two packets to be ready in the OUT FIFO at a time.
In this case, hardware will set OPRDY to 1 immediately after firmware unloads the first packet and resets
OPRDY to 0. A second interrupt will be generated in this case.
23.13.2. Endpoints1-3 OUT Isochronous Mode
When the ISO bit (EOUTCSRH.6) is set to 1, the target endpoint operates in Isochronous (ISO) mode.
Once an endpoint has been configured for ISO OUT mode, the host will send exactly one data per USB
frame; the location of the data packet within each frame may vary, however. Because of this, it is recom-
mended that double buffering be enabled for ISO OUT endpoints.
Each time a data packet is received, hardware will load the received data packet into the endpoint FIFO,
set the OPRDY bit (EOUTCSRL.0) to 1, and generate an interrupt (if enabled). Firmware would typically
use this interrupt to unload the data packet from the endpoint FIFO and reset the OPRDY bit to 0.
If a data packet is received when there is no room in the endpoint FIFO, an interrupt will be generated and
the OVRUN bit (EOUTCSRL.2) set to 1. If USB0 receives an ISO data packet with a CRC error, the data
packet will be loaded into the endpoint FIFO, OPRDY will be set to 1, an interrupt (if enabled) will be gen-
erated, and the DATAERR bit (EOUTCSRL.3) will be set to 1. Software should check the DATAERR bit
each time a data packet is unloaded from an ISO OUT endpoint FIFO.
Rev. 1.2
190
C8051T620/1/6/7 & C8051T320/1/2/3
USB Register Definition 23.22. EOUTCSRL: USB0 OUT Endpoint Control Low Byte
Bit
7
6
5
4
3
2
1
0
CLRDT
STSTL
SDSTL
FLUSH
DATERR
OVRUN
FIFOFUL
OPRDY
Name
Type
Reset
W
0
R/W
0
R/W
0
R/W
0
R
0
R/W
0
R
0
R/W
0
USB Register Address = 0x14
Bit
Name
Description
Write
Read
7
CLRDT
Software should write 1 to
this bit to reset the OUT end-
point data toggle to 0.
This bit always reads 0.
Clear Data Toggle Bit.
6
5
4
STSTL
SDSTL
FLUSH
Sent Stall Bit.
Hardware sets this bit to 1 when a STALL handshake signal is transmitted. This flag
must be cleared by software.
Send Stall Bit.
Software should write 1 to this bit to generate a STALL handshake. Software should
write 0 to this bit to terminate the STALL signal. This bit has no effect in ISO mode.
FIFO Flush Bit.
Writing a 1 to this bit flushes the next packet to be read from the OUT endpoint FIFO.
The FIFO pointer is reset and the OPRDY bit is cleared. Multiple packets must be
flushed individually. Hardware resets the FLUSH bit to 0 when the flush is complete.
Note: If data for the current packet has already been read from the FIFO, the FLUSH bit should
not be used to flush the packet. Instead, the FIFO should be read manually.
3
2
DATERR
OVRUN
Data Error Bit.
In ISO mode, this bit is set by hardware if a received packet has a CRC or bit-stuffing
error. It is cleared when software clears OPRDY. This bit is only valid in ISO mode.
Data Overrun Bit.
This bit is set by hardware when an incoming data packet cannot be loaded into the
OUT endpoint FIFO. This bit is only valid in ISO mode, and must be cleared by software.
0: No data overrun.
1: A data packet was lost because of a full FIFO since this flag was last cleared.
1
0
FIFOFUL
OPRDY
OUT FIFO Full.
This bit indicates the contents of the OUT FIFO. If double buffering is enabled (DBIEN =
1), the FIFO is full when the FIFO contains two packets. If DBIEN = 0, the FIFO is full
when the FIFO contains one packet.
0: OUT endpoint FIFO is not full.
1: OUT endpoint FIFO is full.
OUT Packet Ready.
Hardware sets this bit to 1 and generates an interrupt when a data packet is available.
Software should clear this bit after each data packet is unloaded from the OUT endpoint
FIFO.
191
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
USB Register Definition 23.23. EOUTCSRH: USB0 OUT Endpoint Control High
Byte
Bit
7
6
5
4
3
2
1
0
DBOEN
ISO
Name
Type
Reset
R/W
0
R/W
0
R
0
R
0
R
0
R
0
R
0
R
0
USB Register Address = 0x15
Bit
Name
Function
7
DBOEN
Double-buffer Enable.
0: Double-buffering disabled for the selected OUT endpoint.
1: Double-buffering enabled for the selected OUT endpoint.
6
ISO
Isochronous Transfer Enable.
This bit enables/disables isochronous transfers on the current endpoint.
0: Endpoint configured for bulk/interrupt transfers.
1: Endpoint configured for isochronous transfers.
5:0 Unused Read = 000000b. Write = don’t care.
USB Register Definition 23.24. EOUTCNTL: USB0 OUT Endpoint Count Low
Bit
7
6
5
4
3
2
1
0
EOCL[7:0]
R
Name
Type
Reset
0
0
0
0
0
0
0
0
USB Register Address = 0x16
Bit Name
7:0 EOCL[7:0]
Function
OUT Endpoint Count Low Byte.
EOCL holds the lower 8-bits of the 10-bit number of data bytes in the last received
packet in the current OUT endpoint FIFO. This number is only valid while OPRDY = 1.
Rev. 1.2
192
C8051T620/1/6/7 & C8051T320/1/2/3
USB Register Definition 23.25. EOUTCNTH: USB0 OUT Endpoint Count High
Bit
7
6
5
4
3
2
1
0
EOCH[1:0]
Name
Type
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
USB Register Address = 0x17
Bit
Name
Unused Read = 000000b. Write = don’t care.
Function
7:2
1:0 EOCH[1:0]
OUT Endpoint Count High Byte.
EOCH holds the upper 2-bits of the 10-bit number of data bytes in the last received
packet in the current OUT endpoint FIFO. This number is only valid while OPRDY = 1.
193
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
24. SMBus
The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System
2
Management Bus Specification, version 1.1, and compatible with the I C serial bus. Reads and writes to
the interface by the system controller are byte oriented with the SMBus interface autonomously controlling
the serial transfer of the data. Data can be transferred at up to 1/20th of the system clock as a master or
slave (this can be faster than allowed by the SMBus specification, depending on the system clock used). A
method of extending the clock-low duration is available to accommodate devices with different speed
capabilities on the same bus.
The SMBus interface may operate as a master and/or slave, and may function on a bus with multiple mas-
ters. The SMBus provides control of SDA (serial data), SCL (serial clock) generation and synchronization,
arbitration logic, and START/STOP control and generation. The SMBus peripheral can be fully driven by
software (i.e., software accepts/rejects slave addresses, and generates ACKs), or hardware slave address
recognition and automatic ACK generation can be enabled to minimize software overhead. A block dia-
gram of the SMBus peripheral and the associated SFRs is shown in Figure 24.1.
SMB0CN
SMB0CF
M T S S A A A S
A X T T C R C I
S M A O K B K
E
I
B E S S S S
N N U X M M M M
S H S T B B B B
T O
E D
R E
R L
Q O
S
M
B
Y H T F C C
O O T S S
L E E 1 0
D
T
00
01
10
11
T0 Overflow
T1 Overflow
TMR2H Overflow
TMR2L Overflow
SCL
SMBUS CONTROL LOGIC
Arbitration
FILTER
Interrupt
Request
SCL Synchronization
SCL Generation (Master Mode)
SDA Control
SCL
Control
C
R
O
S
S
B
A
R
N
Hardware Slave Address Recognition
Hardware ACK Generation
Port I/O
Data Path
SDA
Control
IRQ Generation
Control
SMB0DAT
7 6 5 4 3 2 1 0
SDA
FILTER
S S S S S S S G S S S S S S S E
L L L L L L L C L L L L L L L H
V V V V V V V
6 5 4 3 2 1 0
V V V V V V V A
M M M M M M M C
6 5 4 3 2 1 0 K
SMB0ADR
SMB0ADM
N
Figure 24.1. SMBus Block Diagram
Rev. 1.2
194
C8051T620/1/6/7 & C8051T320/1/2/3
24.1. Supporting Documents
It is assumed the reader is familiar with or has access to the following supporting documents:
2
1. The I C-Bus and How to Use It (including specifications), Philips Semiconductor.
2
2. The I C-Bus Specification—Version 2.0, Philips Semiconductor.
3. System Management Bus Specification—Version 1.1, SBS Implementers Forum.
24.2. SMBus Configuration
Figure 24.2 shows a typical SMBus configuration. The SMBus specification allows any recessive voltage
between 3.0 V and 5.0 V; different devices on the bus may operate at different voltage levels. The bi-direc-
tional SCL (serial clock) and SDA (serial data) lines must be connected to a positive power supply voltage
through a pullup resistor or similar circuit. Every device connected to the bus must have an open-drain or
open-collector output for both the SCL and SDA lines, so that both are pulled high (recessive state) when
the bus is free. The maximum number of devices on the bus is limited only by the requirement that the rise
and fall times on the bus not exceed 300 ns and 1000 ns, respectively.
VDD = 5V
VDD = 3V
VDD = 5V
VDD = 3V
Master
Device
Slave
Device 1
Slave
Device 2
SDA
SCL
Figure 24.2. Typical SMBus Configuration
24.3. SMBus Operation
Two types of data transfers are possible: data transfers from a master transmitter to an addressed slave
receiver (WRITE), and data transfers from an addressed slave transmitter to a master receiver (READ).
The master device initiates both types of data transfers and provides the serial clock pulses on SCL. The
SMBus interface may operate as a master or a slave, and multiple master devices on the same bus are
supported. If two or more masters attempt to initiate a data transfer simultaneously, an arbitration scheme
is employed with a single master always winning the arbitration. Note that it is not necessary to specify one
device as the Master in a system; any device who transmits a START and a slave address becomes the
master for the duration of that transfer.
A typical SMBus transaction consists of a START condition followed by an address byte (Bits7–1: 7-bit
slave address; Bit0: R/W direction bit), one or more bytes of data, and a STOP condition. Bytes that are
received (by a master or slave) are acknowledged (ACK) with a low SDA during a high SCL (see
Figure 24.3). If the receiving device does not ACK, the transmitting device will read a NACK (not acknowl-
edge), which is a high SDA during a high SCL.
The direction bit (R/W) occupies the least-significant bit position of the address byte. The direction bit is set
to logic 1 to indicate a "READ" operation and cleared to logic 0 to indicate a "WRITE" operation.
195
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
All transactions are initiated by a master, with one or more addressed slave devices as the target. The
master generates the START condition and then transmits the slave address and direction bit. If the trans-
action is a WRITE operation from the master to the slave, the master transmits the data a byte at a time
waiting for an ACK from the slave at the end of each byte. For READ operations, the slave transmits the
data waiting for an ACK from the master at the end of each byte. At the end of the data transfer, the master
generates a STOP condition to terminate the transaction and free the bus. Figure 24.3 illustrates a typical
SMBus transaction.
SCL
SDA
SLA6
SLA5-0
R/W
D7
D6-0
START
Slave Address + R/W
ACK
Data Byte
NACK
STOP
Figure 24.3. SMBus Transaction
24.3.1. Transmitter Vs. Receiver
On the SMBus communications interface, a device is the “transmitter” when it is sending an address or
data byte to another device on the bus. A device is a “receiver” when an address or data byte is being sent
to it from another device on the bus. The transmitter controls the SDA line during the address or data byte.
After each byte of address or data information is sent by the transmitter, the receiver sends an ACK or
NACK bit during the ACK phase of the transfer, during which time the receiver controls the SDA line.
24.3.2. Arbitration
A master may start a transfer only if the bus is free. The bus is free after a STOP condition or after the SCL
and SDA lines remain high for a specified time (see Section “24.3.5. SCL High (SMBus Free) Timeout” on
page 197). In the event that two or more devices attempt to begin a transfer at the same time, an arbitra-
tion scheme is employed to force one master to give up the bus. The master devices continue transmitting
until one attempts a HIGH while the other transmits a LOW. Since the bus is open-drain, the bus will be
pulled LOW. The master attempting the HIGH will detect a LOW SDA and lose the arbitration. The winning
master continues its transmission without interruption; the losing master becomes a slave and receives the
rest of the transfer if addressed. This arbitration scheme is non-destructive: one device always wins, and
no data is lost.
24.3.3. Clock Low Extension
SMBus provides a clock synchronization mechanism, similar to I2C, which allows devices with different
speed capabilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow
slower slave devices to communicate with faster masters. The slave may temporarily hold the SCL line
LOW to extend the clock low period, effectively decreasing the serial clock frequency.
24.3.4. SCL Low Timeout
If the SCL line is held low by a slave device on the bus, no further communication is possible. Furthermore,
the master cannot force the SCL line high to correct the error condition. To solve this problem, the SMBus
protocol specifies that devices participating in a transfer must detect any clock cycle held low longer than
25 ms as a “timeout” condition. Devices that have detected the timeout condition must reset the communi-
cation no later than 10 ms after detecting the timeout condition.
When the SMBTOE bit in SMB0CF is set, Timer 3 is used to detect SCL low timeouts. Timer 3 is forced to
reload when SCL is high, and allowed to count when SCL is low. With Timer 3 enabled and configured to
Rev. 1.2
196
C8051T620/1/6/7 & C8051T320/1/2/3
overflow after 25 ms (and SMBTOE set), the Timer 3 interrupt service routine can be used to reset (disable
and re-enable) the SMBus in the event of an SCL low timeout.
24.3.5. SCL High (SMBus Free) Timeout
The SMBus specification stipulates that if the SCL and SDA lines remain high for more that 50 µs, the bus
is designated as free. When the SMBFTE bit in SMB0CF is set, the bus will be considered free if SCL and
SDA remain high for more than 10 SMBus clock source periods (as defined by the timer configured for the
SMBus clock source). If the SMBus is waiting to generate a Master START, the START will be generated
following this timeout. A clock source is required for free timeout detection, even in a slave-only implemen-
tation.
24.4. Using the SMBus
The SMBus can operate in both Master and Slave modes. The interface provides timing and shifting con-
trol for serial transfers; higher level protocol is determined by user software. The SMBus interface provides
the following application-independent features:
Byte-wise serial data transfers
Clock signal generation on SCL (Master Mode only) and SDA data synchronization
Timeout/bus error recognition, as defined by the SMB0CF configuration register
START/STOP timing, detection, and generation
Bus arbitration
Interrupt generation
Status information
Optional hardware recognition of slave address and automatic acknowledgement of address/data
SMBus interrupts are generated for each data byte or slave address that is transferred. When hardware
acknowledgement is disabled, the point at which the interrupt is generated depends on whether the hard-
ware is acting as a data transmitter or receiver. When a transmitter (i.e., sending address/data, receiving
an ACK), this interrupt is generated after the ACK cycle so that software may read the received ACK value;
when receiving data (i.e., receiving address/data, sending an ACK), this interrupt is generated before the
ACK cycle so that software may define the outgoing ACK value. If hardware acknowledgement is enabled,
these interrupts are always generated after the ACK cycle. See Section 24.5 for more details on transmis-
sion sequences.
Interrupts are also generated to indicate the beginning of a transfer when a master (START generated), or
the end of a transfer when a slave (STOP detected). Software should read the SMB0CN (SMBus Control
register) to find the cause of the SMBus interrupt. The SMB0CN register is described in Section 24.4.2;
Table 24.5 provides a quick SMB0CN decoding reference.
24.4.1. SMBus Configuration Register
The SMBus Configuration register (SMB0CF) is used to enable the SMBus Master and/or Slave modes,
select the SMBus clock source, and select the SMBus timing and timeout options. When the ENSMB bit is
set, the SMBus is enabled for all master and slave events. Slave events may be disabled by setting the
INH bit. With slave events inhibited, the SMBus interface will still monitor the SCL and SDA pins; however,
the interface will NACK all received addresses and will not generate any slave interrupts. When the INH bit
is set, all slave events will be inhibited following the next START (interrupts will continue for the duration of
the current transfer).
197
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
Table 24.1. SMBus Clock Source Selection
SMBCS1 SMBCS0
SMBus Clock Source
0
0
1
1
0
1
0
1
Timer 0 Overflow
Timer 1 Overflow
Timer 2 High Byte Overflow
Timer 2 Low Byte Overflow
The SMBCS1–0 bits select the SMBus clock source, which is used only when operating as a master or
when the Free Timeout detection is enabled. When operating as a master, overflows from the selected
source determine the absolute minimum SCL low and high times as defined in Equation 24.1. Note that the
selected clock source may be shared by other peripherals so long as the timer is left running at all times.
For example, Timer 1 overflows may generate the SMBus and UART baud rates simultaneously. Timer
configuration is covered in Section “28. Timers” on page 246.
1
---------------------------------------------
THighMin = TLowMin
=
fClockSourceOverflow
Equation 24.1. Minimum SCL High and Low Times
The selected clock source should be configured to establish the minimum SCL High and Low times as per
Equation 24.1. When the interface is operating as a master (and SCL is not driven or extended by any
other devices on the bus), the typical SMBus bit rate is approximated by Equation 24.2.
fClockSourceOverflow
---------------------------------------------
BitRate =
3
Equation 24.2. Typical SMBus Bit Rate
Figure 24.4 shows the typical SCL generation described by Equation 24.2. Notice that T
is typically
HIGH
twice as large as T
. The actual SCL output may vary due to other devices on the bus (SCL may be
LOW
extended low by slower slave devices, or driven low by contending master devices). The bit rate when
operating as a master will never exceed the limits defined by equation Equation 24.1.
Timer Source
Overflows
SCL
TLow
THigh
SCL High Timeout
Figure 24.4. Typical SMBus SCL Generation
Rev. 1.2
198
C8051T620/1/6/7 & C8051T320/1/2/3
Setting the EXTHOLD bit extends the minimum setup and hold times for the SDA line. The minimum SDA
setup time defines the absolute minimum time that SDA is stable before SCL transitions from low-to-high.
The minimum SDA hold time defines the absolute minimum time that the current SDA value remains stable
after SCL transitions from high-to-low. EXTHOLD should be set so that the minimum setup and hold times
meet the SMBus Specification requirements of 250 ns and 300 ns, respectively. Table 24.2 shows the min-
imum setup and hold times for the two EXTHOLD settings. Setup and hold time extensions are typically
necessary when SYSCLK is above 10 MHz.
Table 24.2. Minimum SDA Setup and Hold Times
EXTHOLD
Minimum SDA Setup Time
Minimum SDA Hold Time
T
– 4 system clocks
or
low
0
1
3 system clocks
12 system clocks
*
1 system clock + s/w delay
11 system clocks
Note: Setup Time for ACK bit transmissions and the MSB of all data transfers. When using
software acknowledgement, the s/w delay occurs between the time SMB0DAT or
ACK is written and when SI is cleared. Note that if SI is cleared in the same write
that defines the outgoing ACK value, s/w delay is zero.
With the SMBTOE bit set, Timer 3 should be configured to overflow after 25 ms in order to detect SCL low
timeouts (see Section “24.3.4. SCL Low Timeout” on page 196). The SMBus interface will force Timer 3 to
reload while SCL is high, and allow Timer 3 to count when SCL is low. The Timer 3 interrupt service routine
should be used to reset SMBus communication by disabling and re-enabling the SMBus.
SMBus Free Timeout detection can be enabled by setting the SMBFTE bit. When this bit is set, the bus will
be considered free if SDA and SCL remain high for more than 10 SMBus clock source periods (see
Figure 24.4).
199
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 24.1. SMB0CF: SMBus Clock/Configuration
Bit
7
6
5
4
3
2
1
0
ENSMB
INH
BUSY
EXTHOLD SMBTOE SMBFTE
SMBCS[1:0]
R/W
Name
Type
Reset
R/W
0
R/W
0
R
0
R/W
0
R/W
0
R/W
0
0
0
SFR Address = 0xC1
Bit
Name
Function
7
ENSMB
SMBus Enable.
This bit enables the SMBus interface when set to 1. When enabled, the interface
constantly monitors the SDA and SCL pins.
6
INH
SMBus Slave Inhibit.
When this bit is set to logic 1, the SMBus does not generate an interrupt when slave
events occur. This effectively removes the SMBus slave from the bus. Master Mode
interrupts are not affected.
5
4
BUSY
SMBus Busy Indicator.
This bit is set to logic 1 by hardware when a transfer is in progress. It is cleared to
logic 0 when a STOP or free-timeout is sensed.
EXTHOLD
SMBus Setup and Hold Time Extension Enable.
This bit controls the SDA setup and hold times according to Table 24.2.
0: SDA Extended Setup and Hold Times disabled.
1: SDA Extended Setup and Hold Times enabled.
3
SMBTOE
SMBus SCL Timeout Detection Enable.
This bit enables SCL low timeout detection. If set to logic 1, the SMBus forces
Timer 3 to reload while SCL is high and allows Timer 3 to count when SCL goes low.
If Timer 3 is configured to Split Mode, only the High Byte of the timer is held in reload
while SCL is high. Timer 3 should be programmed to generate interrupts at 25 ms,
and the Timer 3 interrupt service routine should reset SMBus communication.
2
SMBFTE
SMBus Free Timeout Detection Enable.
When this bit is set to logic 1, the bus will be considered free if SCL and SDA remain
high for more than 10 SMBus clock source periods.
1:0 SMBCS[1:0]
SMBus Clock Source Selection.
These two bits select the SMBus clock source, which is used to generate the SMBus
bit rate. The selected device should be configured according to Equation 24.1.
00: Timer 0 Overflow
01: Timer 1 Overflow
10: Timer 2 High Byte Overflow
11: Timer 2 Low Byte Overflow
Rev. 1.2
200
C8051T620/1/6/7 & C8051T320/1/2/3
24.4.2. SMB0CN Control Register
SMB0CN is used to control the interface and to provide status information (see SFR Definition 24.2). The
higher four bits of SMB0CN (MASTER, TXMODE, STA, and STO) form a status vector that can be used to
jump to service routines. MASTER indicates whether a device is the master or slave during the current
transfer. TXMODE indicates whether the device is transmitting or receiving data for the current byte.
STA and STO indicate that a START and/or STOP has been detected or generated since the last SMBus
interrupt. STA and STO are also used to generate START and STOP conditions when operating as a mas-
ter. Writing a 1 to STA will cause the SMBus interface to enter Master Mode and generate a START when
the bus becomes free (STA is not cleared by hardware after the START is generated). Writing a 1 to STO
while in Master Mode will cause the interface to generate a STOP and end the current transfer after the
next ACK cycle. If STO and STA are both set (while in Master Mode), a STOP followed by a START will be
generated.
The ARBLOST bit indicates that the interface has lost an arbitration. This may occur anytime the interface
is transmitting (master or slave). A lost arbitration while operating as a slave indicates a bus error condi-
tion. ARBLOST is cleared by hardware each time SI is cleared.
The SI bit (SMBus Interrupt Flag) is set at the beginning and end of each transfer, after each byte frame, or
when an arbitration is lost; see Table 24.3 for more details.
Important Note About the SI Bit: The SMBus interface is stalled while SI is set; thus SCL is held low, and
the bus is stalled until software clears SI.
24.4.2.1. Software ACK Generation
When the EHACK bit in register SMB0ADM is cleared to 0, the firmware on the device must detect incom-
ing slave addresses and ACK or NACK the slave address and incoming data bytes. As a receiver, writing
the ACK bit defines the outgoing ACK value; as a transmitter, reading the ACK bit indicates the value
received during the last ACK cycle. ACKRQ is set each time a byte is received, indicating that an outgoing
ACK value is needed. When ACKRQ is set, software should write the desired outgoing value to the ACK
bit before clearing SI. A NACK will be generated if software does not write the ACK bit before clearing SI.
SDA will reflect the defined ACK value immediately following a write to the ACK bit; however SCL will
remain low until SI is cleared. If a received slave address is not acknowledged, further slave events will be
ignored until the next START is detected.
24.4.2.2. Hardware ACK Generation
When the EHACK bit in register SMB0ADM is set to 1, automatic slave address recognition and ACK gen-
eration is enabled. More detail about automatic slave address recognition can be found in Section 24.4.3.
As a receiver, the value currently specified by the ACK bit will be automatically sent on the bus during the
ACK cycle of an incoming data byte. As a transmitter, reading the ACK bit indicates the value received on
the last ACK cycle. The ACKRQ bit is not used when hardware ACK generation is enabled. If a received
slave address is NACKed by hardware, further slave events will be ignored until the next START is
detected, and no interrupt will be generated.
Table 24.3 lists all sources for hardware changes to the SMB0CN bits. Refer to Table 24.5 for SMBus sta-
tus decoding using the SMB0CN register.
201
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 24.2. SMB0CN: SMBus Control
Bit
7
6
5
4
3
2
1
0
MASTER TXMODE
STA
STO
ACKRQ ARBLOST
ACK
SI
Name
Type
Reset
R
0
R
0
R/W
0
R/W
0
R
0
R
0
R/W
0
R/W
0
SFR Address = 0xC0; Bit-Addressable
Bit
Name
Description
Read
Write
7
MASTER
0: SMBus operating in
slave mode.
1: SMBus operating in
master mode.
N/A
N/A
SMBus Master/Slave
Indicator. This read-only bit
indicates when the SMBus is
operating as a master.
6
TXMODE
0: SMBus in Receiver
Mode.
1: SMBus in Transmitter
Mode.
SMBus Transmit Mode
Indicator. This read-only bit
indicates when the SMBus is
operating as a transmitter.
5
4
STA
STO
0: No Start or repeated
Start detected.
1: Start or repeated Start
detected.
0: No Start generated.
1: When Configured as a
Master, initiates a START
or repeated START.
SMBus Start Flag.
0: No Stop condition
detected.
0: No STOP condition is
transmitted.
SMBus Stop Flag.
1: Stop condition detected 1: When configured as a
(if in Slave Mode) or pend- Master, causes a STOP
ing (if in Master Mode).
condition to be transmit-
ted after the next ACK
cycle.
Cleared by Hardware.
3
2
1
0
ACKRQ
ARBLOST
ACK
0: No Ack requested
1: ACK requested
N/A
SMBus Acknowledge
Request.
0: No arbitration error.
1: Arbitration Lost
N/A
SMBus Arbitration Lost
Indicator.
0: NACK received.
1: ACK received.
0: Send NACK
1: Send ACK
SMBus Acknowledge.
SI
0: Clear interrupt, and initi-
ate next state machine
event.
SMBus Interrupt Flag.
This bit is set by hardware
under the conditions listed in
Table 15.3. SI must be cleared
by software. While SI is set,
SCL is held low and the
SMBus is stalled.
0: No interrupt pending
1: Interrupt Pending
1: Force interrupt.
Rev. 1.2
202
C8051T620/1/6/7 & C8051T320/1/2/3
Table 24.3. Sources for Hardware Changes to SMB0CN
Bit
Set by Hardware When:
A START is generated.
Cleared by Hardware When:
A STOP is generated.
Arbitration is lost.
A START is detected.
Arbitration is lost.
MASTER
START is generated.
SMB0DAT is written before the start of an
SMBus frame.
TXMODE
SMB0DAT is not written before the
start of an SMBus frame.
A START followed by an address byte is
received.
A STOP is detected while addressed as a
slave.
Must be cleared by software.
STA
STO
A pending STOP is generated.
Arbitration is lost due to a detected STOP.
A byte has been received and an ACK
response value is needed (only when
hardware ACK is not enabled).
A repeated START is detected as a
MASTER when STA is low (unwanted
repeated START).
After each ACK cycle.
Each time SI is cleared.
ACKRQ
SCL is sensed low while attempting to
generate a STOP or repeated START
condition.
ARBLOST
ACK
SDA is sensed low while transmitting a 1
(excluding ACK bits).
The incoming ACK value is low
(ACKNOWLEDGE).
The incoming ACK value is high
(NOT ACKNOWLEDGE).
Must be cleared by software.
A START has been generated.
Lost arbitration.
A byte has been transmitted and an
ACK/NACK received.
SI
A byte has been received.
A START or repeated START followed by a
slave address + R/W has been received.
A STOP has been received.
24.4.3. Hardware Slave Address Recognition
The SMBus hardware has the capability to automatically recognize incoming slave addresses and send an
ACK without software intervention. Automatic slave address recognition is enabled by setting the EHACK
bit in register SMB0ADM to 1. This will enable both automatic slave address recognition and automatic
hardware ACK generation for received bytes (as a master or slave). More detail on automatic hardware
ACK generation can be found in Section 24.4.2.2.
The registers used to define which address(es) are recognized by the hardware are the SMBus Slave
Address register (SFR Definition 24.3) and the SMBus Slave Address Mask register (SFR Definition 24.4).
A single address or range of addresses (including the General Call Address 0x00) can be specified using
these two registers. The most-significant seven bits of the two registers are used to define which
addresses will be ACKed. A 1 in bit positions of the slave address mask SLVM[6:0] enable a comparison
between the received slave address and the hardware’s slave address SLV[6:0] for those bits. A 0 in a bit
of the slave address mask means that bit will be treated as a “don’t care” for comparison purposes.
203
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
In this case, either a 1 or a 0 value are acceptable on the incoming slave address. Additionally, if the GC bit
in register SMB0ADR is set to 1, hardware will recognize the General Call Address (0x00). Table 24.4
shows some example parameter settings and the slave addresses that will be recognized by hardware
under those conditions.
Table 24.4. Hardware Address Recognition Examples (EHACK = 1)
Hardware Slave Address Slave Address Mask
GC bit Slave Addresses Recognized by
Hardware
SLV[6:0]
SLVM[6:0]
0x34
0x34
0x34
0x34
0x70
0x7F
0x7F
0x7E
0x7E
0x73
0
1
0
1
0
0x34
0x34, 0x00 (General Call)
0x34, 0x35
0x34, 0x35, 0x00 (General Call)
0x70, 0x74, 0x78, 0x7C
SFR Definition 24.3. SMB0ADR: SMBus Slave Address
Bit
7
6
5
4
3
2
1
0
SLV[6:0]
GC
Name
Type
Reset
R/W
0
R/W
0
0
0
0
0
0
0
SFR Address = 0xC7
Bit
Name
Function
7:1
SLV[6:0]
SMBus Hardware Slave Address.
Defines the SMBus Slave Address(es) for automatic hardware acknowledgement.
Only address bits which have a 1 in the corresponding bit position in SLVM[6:0]
are checked against the incoming address. This allows multiple addresses to be
recognized.
0
GC
General Call Address Enable.
When hardware address recognition is enabled (EHACK = 1), this bit will deter-
mine whether the General Call Address (0x00) is also recognized by hardware.
0: General Call Address is ignored.
1: General Call Address is recognized.
Rev. 1.2
204
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 24.4. SMB0ADM: SMBus Slave Address Mask
Bit
7
6
5
4
3
2
1
0
SLVM[6:0]
EHACK
Name
Type
Reset
R/W
1
R/W
0
1
1
1
1
1
1
SFR Address = 0xCF
Bit
Name
Function
7:1
SLVM[6:0]
SMBus Slave Address Mask.
Defines which bits of register SMB0ADR are compared with an incoming address
byte, and which bits are ignored. Any bit set to 1 in SLVM[6:0] enables compari-
sons with the corresponding bit in SLV[6:0]. Bits set to 0 are ignored (can be either
0 or 1 in the incoming address).
0
EHACK
Hardware Acknowledge Enable.
Enables hardware acknowledgement of slave address and received data bytes.
0: Firmware must manually acknowledge all incoming address and data bytes.
1: Automatic Slave Address Recognition and Hardware Acknowledge is Enabled.
205
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
24.4.4. Data Register
The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been
received. Software may safely read or write to the data register when the SI flag is set. Software should not
attempt to access the SMB0DAT register when the SMBus is enabled and the SI flag is cleared to logic 0,
as the interface may be in the process of shifting a byte of data into or out of the register.
Data in SMB0DAT is always shifted out MSB first. After a byte has been received, the first bit of received
data is located at the MSB of SMB0DAT. While data is being shifted out, data on the bus is simultaneously
being shifted in. SMB0DAT always contains the last data byte present on the bus. In the event of lost arbi-
tration, the transition from master transmitter to slave receiver is made with the correct data or address in
SMB0DAT.
SFR Definition 24.5. SMB0DAT: SMBus Data
Bit
7
6
5
4
3
2
1
0
SMB0DAT[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xC2
Bit Name
7:0 SMB0DAT[7:0]
Function
SMBus Data.
The SMB0DAT register contains a byte of data to be transmitted on the SMBus
serial interface or a byte that has just been received on the SMBus serial interface.
The CPU can read from or write to this register whenever the SI serial interrupt flag
(SMB0CN.0) is set to logic 1. The serial data in the register remains stable as long
as the SI flag is set. When the SI flag is not set, the system may be in the process
of shifting data in/out and the CPU should not attempt to access this register.
Rev. 1.2
206
C8051T620/1/6/7 & C8051T320/1/2/3
24.5. SMBus Transfer Modes
The SMBus interface may be configured to operate as master and/or slave. At any particular time, it will be
operating in one of the following four modes: Master Transmitter, Master Receiver, Slave Transmitter, or
Slave Receiver. The SMBus interface enters Master Mode any time a START is generated, and remains in
Master Mode until it loses an arbitration or generates a STOP. An SMBus interrupt is generated at the end
of all SMBus byte frames. Note that the position of the ACK interrupt when operating as a receiver
depends on whether hardware ACK generation is enabled. As a receiver, the interrupt for an ACK occurs
before the ACK with hardware ACK generation disabled, and after the ACK when hardware ACK genera-
tion is enabled. As a transmitter, interrupts occur after the ACK, regardless of whether hardware ACK gen-
eration is enabled or not.
24.5.1. Write Sequence (Master)
During a write sequence, an SMBus master writes data to a slave device. The master in this transfer will be
a transmitter during the address byte, and a transmitter during all data bytes. The SMBus interface gener-
ates the START condition and transmits the first byte containing the address of the target slave and the
data direction bit. In this case the data direction bit (R/W) will be logic 0 (WRITE). The master then trans-
mits one or more bytes of serial data. After each byte is transmitted, an acknowledge bit is generated by
the slave. The transfer is ended when the STO bit is set and a STOP is generated. Note that the interface
will switch to Master Receiver Mode if SMB0DAT is not written following a Master Transmitter interrupt.
Figure 24.5 shows a typical master write sequence. Two transmit data bytes are shown, though any num-
ber of bytes may be transmitted. Notice that all of the “data byte transferred” interrupts occur after the ACK
cycle in this mode, regardless of whether hardware ACK generation is enabled.
Interrupts with Hardware ACK Enabled (EHACK = 1)
S
SLA
W
A
Data Byte
A
Data Byte
A
P
Interrupts with Hardware ACK Disabled (EHACK = 0)
S = START
P = STOP
A = ACK
Received by SMBus
Interface
W = WRITE
Transmitted by
SLA = Slave Address
SMBus Interface
Figure 24.5. Typical Master Write Sequence
207
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
24.5.2. Read Sequence (Master)
During a read sequence, an SMBus master reads data from a slave device. The master in this transfer will
be a transmitter during the address byte, and a receiver during all data bytes. The SMBus interface gener-
ates the START condition and transmits the first byte containing the address of the target slave and the
data direction bit. In this case the data direction bit (R/W) will be logic 1 (READ). Serial data is then
received from the slave on SDA while the SMBus outputs the serial clock. The slave transmits one or more
bytes of serial data.
If hardware ACK generation is disabled, the ACKRQ is set to 1 and an interrupt is generated after each
received byte. Software must write the ACK bit at that time to ACK or NACK the received byte.
With hardware ACK generation enabled, the SMBus hardware will automatically generate the ACK/NACK,
and then post the interrupt. It is important to note that the appropriate ACK or NACK value should be
set up by the software prior to receiving the byte when hardware ACK generation is enabled.
Writing a 1 to the ACK bit generates an ACK; writing a 0 generates a NACK. Software should write a 0 to
the ACK bit for the last data transfer, to transmit a NACK. The interface exits Master Receiver Mode after
the STO bit is set and a STOP is generated. The interface will switch to Master Transmitter Mode if SMB0-
DAT is written while an active Master Receiver. Figure 24.6 shows a typical master read sequence. Two
received data bytes are shown, though any number of bytes may be received. Notice that the ‘data byte
transferred’ interrupts occur at different places in the sequence, depending on whether hardware ACK gen-
eration is enabled. The interrupt occurs before the ACK with hardware ACK generation disabled, and after
the ACK when hardware ACK generation is enabled.
Interrupts with Hardware ACK Enabled (EHACK = 1)
S
SLA
R
A
Data Byte
A
Data Byte
N
P
Interrupts with Hardware ACK Disabled (EHACK = 0)
S = START
P = STOP
A = ACK
Received by SMBus
Interface
N = NACK
R = READ
SLA = Slave Address
Transmitted by
SMBus Interface
Figure 24.6. Typical Master Read Sequence
Rev. 1.2
208
C8051T620/1/6/7 & C8051T320/1/2/3
24.5.3. Write Sequence (Slave)
During a write sequence, an SMBus master writes data to a slave device. The slave in this transfer will be
a receiver during the address byte, and a receiver during all data bytes. When slave events are enabled
(INH = 0), the interface enters Slave Receiver Mode when a START followed by a slave address and direc-
tion bit (WRITE in this case) is received. If hardware ACK generation is disabled, upon entering Slave
Receiver Mode, an interrupt is generated and the ACKRQ bit is set. The software must respond to the
received slave address with an ACK, or ignore the received slave address with a NACK. If hardware ACK
generation is enabled, the hardware will apply the ACK for a slave address which matches the criteria set
up by SMB0ADR and SMB0ADM. The interrupt will occur after the ACK cycle.
If the received slave address is ignored (by software or hardware), slave interrupts will be inhibited until the
next START is detected. If the received slave address is acknowledged, zero or more data bytes are
received.
If hardware ACK generation is disabled, the ACKRQ is set to 1 and an interrupt is generated after each
received byte. Software must write the ACK bit at that time to ACK or NACK the received byte.
With hardware ACK generation enabled, the SMBus hardware will automatically generate the ACK/NACK,
and then post the interrupt. It is important to note that the appropriate ACK or NACK value should be
set up by the software prior to receiving the byte when hardware ACK generation is enabled.
The interface exits Slave Receiver Mode after receiving a STOP. Note that the interface will switch to Slave
Transmitter Mode if SMB0DAT is written while an active Slave Receiver. Figure 24.7 shows a typical slave
write sequence. Two received data bytes are shown, though any number of bytes may be received. Notice
that the ‘data byte transferred’ interrupts occur at different places in the sequence, depending on whether
hardware ACK generation is enabled. The interrupt occurs before the ACK with hardware ACK generation
disabled, and after the ACK when hardware ACK generation is enabled.
Interrupts with Hardware ACK Enabled (EHACK = 1)
S
SLA
W
A
Data Byte
A
Data Byte
A
P
Interrupts with Hardware ACK Disabled (EHACK = 0)
S = START
P = STOP
A = ACK
Received by SMBus
Interface
W = WRITE
SLA = Slave Address
Transmitted by
SMBus Interface
Figure 24.7. Typical Slave Write Sequence
209
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
24.5.4. Read Sequence (Slave)
During a read sequence, an SMBus master reads data from a slave device. The slave in this transfer will
be a receiver during the address byte, and a transmitter during all data bytes. When slave events are
enabled (INH = 0), the interface enters Slave Receiver Mode (to receive the slave address) when a START
followed by a slave address and direction bit (READ in this case) is received. If hardware ACK generation
is disabled, upon entering Slave Receiver Mode, an interrupt is generated and the ACKRQ bit is set. The
software must respond to the received slave address with an ACK, or ignore the received slave address
with a NACK. If hardware ACK generation is enabled, the hardware will apply the ACK for a slave address
which matches the criteria set up by SMB0ADR and SMB0ADM. The interrupt will occur after the ACK
cycle.
If the received slave address is ignored (by software or hardware), slave interrupts will be inhibited until the
next START is detected. If the received slave address is acknowledged, zero or more data bytes are trans-
mitted. If the received slave address is acknowledged, data should be written to SMB0DAT to be transmit-
ted. The interface enters slave transmitter mode, and transmits one or more bytes of data. After each byte
is transmitted, the master sends an acknowledge bit; if the acknowledge bit is an ACK, SMB0DAT should
be written with the next data byte. If the acknowledge bit is a NACK, SMB0DAT should not be written to
before SI is cleared (an error condition may be generated if SMB0DAT is written following a received
NACK while in slave transmitter mode). The interface exits slave transmitter mode after receiving a STOP.
Note that the interface will switch to slave receiver mode if SMB0DAT is not written following a Slave
Transmitter interrupt. Figure 24.8 shows a typical slave read sequence. Two transmitted data bytes are
shown, though any number of bytes may be transmitted. Notice that all of the “data byte transferred” inter-
rupts occur after the ACK cycle in this mode, regardless of whether hardware ACK generation is enabled.
Interrupts with Hardware ACK Enabled (EHACK = 1)
S
SLA
R
A
Data Byte
A
Data Byte
N
P
Interrupts with Hardware ACK Disabled (EHACK = 0)
S = START
P = STOP
N = NACK
Received by SMBus
Interface
R = READ
SLA = Slave Address
Transmitted by
SMBus Interface
Figure 24.8. Typical Slave Read Sequence
24.6. SMBus Status Decoding
The current SMBus status can be easily decoded using the SMB0CN register. The appropriate actions to
take in response to an SMBus event depend on whether hardware slave address recognition and ACK
generation is enabled or disabled. Table 24.5 describes the typical actions when hardware slave address
recognition and ACK generation is disabled. Table 24.6 describes the typical actions when hardware slave
address recognition and ACK generation is enabled. In the tables, STATUS VECTOR refers to the four
upper bits of SMB0CN: MASTER, TXMODE, STA, and STO. The shown response options are only the typ-
ical responses; application-specific procedures are allowed as long as they conform to the SMBus specifi-
cation. Highlighted responses are allowed by hardware but do not conform to the SMBus specification.
Rev. 1.2
210
C8051T620/1/6/7 & C8051T320/1/2/3
Table 24.5. SMBus Status Decoding With Hardware ACK Generation Disabled (EHACK = 0)
Values to
Write
Values Read
Current SMbus State
Typical Response Options
A master START was gener- Load slave address + R/W into
0
0
X
1100
1110
1100
0
0
0
0
X
ated.
SMB0DAT.
A master data or address byte Set STA to restart transfer.
1
0
0
1
X
X
1110
—
0 was transmitted; NACK
received.
Abort transfer.
Load next data byte into
SMB0DAT.
0
0
X
1100
End transfer with STOP.
0
1
1
1
X
X
—
—
A master data or address byte End transfer with STOP and start
0
0
1 was transmitted; ACK
received.
another transfer.
Send repeated START.
1
0
0
0
X
X
1110
1000
Switch to Master Receiver Mode
(clear SI without writing new data
to SMB0DAT).
Acknowledge received byte;
Read SMB0DAT.
0
0
1
0
1
1
1
0
0
1000
—
Send NACK to indicate last byte,
and send STOP.
Send NACK to indicate last byte,
and send STOP followed by
START.
1110
Send ACK followed by repeated
START.
1
1
0
0
0
0
1
0
1
1110
1110
1100
A master data byte was
0 X
1000
1
received; ACK requested.
Send NACK to indicate last byte,
and send repeated START.
Send ACK and switch to Master
Transmitter Mode (write to
SMB0DAT before clearing SI).
Send NACK and switch to Mas-
ter Transmitter Mode (write to
SMB0DAT before clearing SI).
0
0
0
1100
211
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
Table 24.5. SMBus Status Decoding With Hardware ACK Generation Disabled (EHACK = 0)
(Continued)
Values to
Write
Values Read
Current SMbus State
Typical Response Options
A slave byte was transmitted; No action required (expecting
0
0
0
0
0
0
0
0
X
X
X
X
0001
0100
0001
—
0
0
0
0
0
1
0
1
NACK received.
A slave byte was transmitted; Load SMB0DAT with next data
ACK received. byte to transmit.
A Slave byte was transmitted; No action required (expecting
STOP condition).
0100
0101
X
error detected.
Master to end transfer).
An illegal STOP or bus error
0
1
X
0
X was detected while a Slave
Transmission was in progress.
Clear STO.
If Write, Acknowledge received
address
0
0
0
0
1
1
0000
0100
A slave address + R/W was
X
If Read, Load SMB0DAT with
data byte; ACK received address
received; ACK requested.
NACK received address.
0
0
0
0
0
1
—
If Write, Acknowledge received
address
0000
0010
If Read, Load SMB0DAT with
data byte; ACK received address
0
0
1
0100
Lost arbitration as master;
X slave address + R/W received;
ACK requested.
1
1
NACK received address.
0
1
0
0
0
0
—
Reschedule failed transfer;
NACK received address.
1110
A STOP was detected while
0
0
X
—
0
1
0
1
X addressed as a Slave Trans- Clear STO.
mitter or Slave Receiver.
0001
0000
Lost arbitration while attempt- No action required (transfer
X
0
0
0
0
0
1
—
ing a STOP.
complete/aborted).
Acknowledge received byte;
Read SMB0DAT.
0000
A slave byte was received;
ACK requested.
1
0
X
NACK received byte.
Abort failed transfer.
0
0
1
0
1
0
1
0
0
0
0
0
0
0
0
X
X
X
X
0
—
—
Lost arbitration while attempt-
ing a repeated START.
0010
0001
0
0
1
1
X
X
Reschedule failed transfer.
Abort failed transfer.
1110
—
Lost arbitration due to a
detected STOP.
Reschedule failed transfer.
Abort failed transfer.
1110
—
Lost arbitration while transmit-
ting a data byte as master.
0000
1
1
X
0
1110
Reschedule failed transfer.
Rev. 1.2
212
C8051T620/1/6/7 & C8051T320/1/2/3
Table 24.6. SMBus Status Decoding With Hardware ACK Generation Enabled (EHACK = 1)
Values to
Write
Values Read
Current SMbus State
Typical Response Options
A master START was gener- Load slave address + R/W into
0
0
X
1100
1110
0
0
0
0
X
ated.
SMB0DAT.
A master data or address byte Set STA to restart transfer.
1
0
0
1
X
X
1110
—
0 was transmitted; NACK
received.
Abort transfer.
Load next data byte into
SMB0DAT.
0
0
X
1100
End transfer with STOP.
0
1
1
1
X
X
—
—
1100
End transfer with STOP and start
another transfer.
A master data or address byte
1 was transmitted; ACK
received.
0
0
Send repeated START.
1
0
0
0
X
1
1110
1000
Switch to Master Receiver Mode
(clear SI without writing new data
to SMB0DAT). Set ACK for initial
data byte.
Set ACK for next data byte;
Read SMB0DAT.
0
0
0
0
1
0
1000
1000
Set NACK to indicate next data
byte as the last data byte;
Read SMB0DAT.
A master data byte was
received; ACK sent.
0
0
1
Initiate repeated START.
1
0
0
0
0
1110
1100
Switch to Master Transmitter
Mode (write to SMB0DAT before
clearing SI).
X
1000
Read SMB0DAT; send STOP.
0
1
1
1
0
0
—
Read SMB0DAT; Send STOP
followed by START.
1110
A master data byte was
0 received; NACK sent (last
byte).
0
0
Initiate repeated START.
1
0
0
0
0
1110
1100
Switch to Master Transmitter
Mode (write to SMB0DAT before
clearing SI).
X
213
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
Table 24.6. SMBus Status Decoding With Hardware ACK Generation Enabled (EHACK = 1)
(Continued)
Values to
Write
Values Read
Current SMbus State
Typical Response Options
A slave byte was transmitted; No action required (expecting
0
0
0
0
0
0
0
0
X
X
X
X
0001
0100
0001
—
0
0
0
0
0
1
0
1
NACK received.
A slave byte was transmitted; Load SMB0DAT with next data
ACK received. byte to transmit.
A Slave byte was transmitted; No action required (expecting
STOP condition).
0100
0101
X
error detected.
Master to end transfer).
An illegal STOP or bus error
0
0
X
0
X was detected while a Slave
Transmission was in progress.
Clear STO.
If Write, Set ACK for first data
byte.
0
0
0
0
0
0
0
0
1
X
1
0000
0100
0000
0100
A slave address + R/W was
X
received; ACK sent.
If Read, Load SMB0DAT with
data byte
0010
If Write, Set ACK for first data
byte.
Lost arbitration as master;
0
1
X slave address + R/W received; If Read, Load SMB0DAT with
X
ACK sent.
data byte
Reschedule failed transfer
1
0
0
0
X
X
1110
—
A STOP was detected while
0
0
0
1
X addressed as a Slave Trans- Clear STO.
mitter or Slave Receiver.
0001
0000
Lost arbitration while attempt- No action required (transfer
X
0
0
0
0
0
0
0
1
0
—
ing a STOP.
complete/aborted).
Set ACK for next data byte;
Read SMB0DAT.
0000
0000
0
0
X A slave byte was received.
Set NACK for next data byte;
Read SMB0DAT.
Abort failed transfer.
0
1
0
1
0
1
0
0
0
0
0
0
X
X
X
X
X
X
—
1110
—
Lost arbitration while attempt-
ing a repeated START.
0010
0001
0
0
1
1
X
Reschedule failed transfer.
Abort failed transfer.
Lost arbitration due to a
detected STOP.
X
Reschedule failed transfer.
Abort failed transfer.
1110
—
Lost arbitration while transmit-
ting a data byte as master.
0000
0
1
X
1110
Reschedule failed transfer.
Rev. 1.2
214
C8051T620/1/6/7 & C8051T320/1/2/3
25. UART0
UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART.
Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details
in Section “25.1. Enhanced Baud Rate Generation” on page 216). Received data buffering allows UART0
to start reception of a second incoming data byte before software has finished reading the previous data
byte.
UART0 has two associated SFRs: Serial Control Register 0 (SCON0) and Serial Data Buffer 0 (SBUF0).
The single SBUF0 location provides access to both transmit and receive registers. Writes to SBUF0
always access the Transmit register. Reads of SBUF0 always access the buffered Receive register;
it is not possible to read data from the Transmit register.
With UART0 interrupts enabled, an interrupt is generated each time a transmit is completed (TI0 is set in
SCON0), or a data byte has been received (RI0 is set in SCON0). The UART0 interrupt flags are not
cleared by hardware when the CPU vectors to the interrupt service routine. They must be cleared manually
by software, allowing software to determine the cause of the UART0 interrupt (transmit complete or receive
complete).
SFR Bus
Write to
SBUF
TB8
SBUF
SET
(TX Shift)
D
Q
TX
CLR
Crossbar
Zero Detector
Stop Bit
Shift
Data
Start
Tx Control
Tx Clock
Send
Tx IRQ
SCON
TI
UART Baud
Rate Generator
Serial
Port
Interrupt
Port I/O
RI
Rx IRQ
Rx Clock
Rx Control
Load
SBUF
Start
Shift
0x1FF
RB8
Input Shift Register
(9 bits)
Load SBUF
SBUF
(RX Latch)
Read
SBUF
SFR Bus
RX
Crossbar
Figure 25.1. UART0 Block Diagram
Rev. 1.2
215
C8051T620/1/6/7 & C8051T320/1/2/3
25.1. Enhanced Baud Rate Generation
The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by
TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer in Figure 25.2), which is not user-
accessible. Both TX and RX Timer overflows are divided by two to generate the TX and RX baud rates.
The RX Timer runs when Timer 1 is enabled, and uses the same reload value (TH1). However, an
RX Timer reload is forced when a START condition is detected on the RX pin. This allows a receive to
begin any time a START is detected, independent of the TX Timer state.
Timer 1
TL1
UART
Overflow
TX Clock
2
2
TH1
Start
Detected
Overflow
RX Clock
RX Timer
Figure 25.2. UART0 Baud Rate Logic
Timer 1 should be configured for Mode 2, 8-bit auto-reload (see Section “28.1.3. Mode 2: 8-bit
Counter/Timer with Auto-Reload” on page 249). The Timer 1 reload value should be set so that overflows
will occur at two times the desired UART baud rate frequency. Note that Timer 1 may be clocked by one of
six sources: SYSCLK, SYSCLK/4, SYSCLK/12, SYSCLK/48, the external oscillator clock/8, or an external
input T1. For any given Timer 1 clock source, the UART0 baud rate is determined by Equation 25.1-A and
Equation 25.1-B.
1
2
A)
B)
--
UARTBaudRate = × T1_Overflow_Rate
T1CLK
-------------------------
T1_Overflow_Rate =
256 – TH1
Equation 25.1. UART0 Baud Rate
Where T1
is the frequency of the clock supplied to Timer 1, and T1H is the high byte of Timer 1 (reload
CLK
value). Timer 1 clock frequency is selected as described in Section “28. Timers” on page 246. A quick ref-
erence for typical baud rates and system clock frequencies is given in Table 25.1 through Table 25.2. The
internal oscillator may still generate the system clock when the external oscillator is driving Timer 1.
216
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
25.2. Operational Modes
UART0 provides standard asynchronous, full duplex communication. The UART mode (8-bit or 9-bit) is
selected by the S0MODE bit (SCON0.7). Typical UART connection options are shown in Figure 25.3.
TX
RS-232
RS-232
LEVEL
C8051xxxx
RX
XLTR
OR
TX
RX
TX
RX
MCU
C8051xxxx
Figure 25.3. UART Interconnect Diagram
25.2.1. 8-Bit UART
8-Bit UART mode uses a total of 10 bits per data byte: one start bit, eight data bits (LSB first), and one stop
bit. Data are transmitted LSB first from the TX0 pin and received at the RX0 pin. On receive, the eight data
bits are stored in SBUF0 and the stop bit goes into RB80 (SCON0.2).
Data transmission begins when software writes a data byte to the SBUF0 register. The TI0 Transmit Inter-
rupt Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data recep-
tion can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to logic 1. After the stop bit is
received, the data byte will be loaded into the SBUF0 receive register if the following conditions are met:
RI0 must be logic 0, and if MCE0 is logic 1, the stop bit must be logic 1. In the event of a receive data over-
run, the first received 8 bits are latched into the SBUF0 receive register and the following overrun data bits
are lost.
If these conditions are met, the eight bits of data is stored in SBUF0, the stop bit is stored in RB80 and the
RI0 flag is set. If these conditions are not met, SBUF0 and RB80 will not be loaded and the RI0 flag will not
be set. An interrupt will occur if enabled when either TI0 or RI0 is set.
MARK
START
BIT
STOP
BIT
D0
D1
D2
D3
D4
D5
D6
D7
SPACE
BIT TIMES
BIT SAMPLING
Figure 25.4. 8-Bit UART Timing Diagram
Rev. 1.2
217
C8051T620/1/6/7 & C8051T320/1/2/3
25.2.2. 9-Bit UART
9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programma-
ble ninth data bit, and a stop bit. The state of the ninth transmit data bit is determined by the value in TB80
(SCON0.3), which is assigned by user software. It can be assigned the value of the parity flag (bit P in reg-
ister PSW) for error detection, or used in multiprocessor communications. On receive, the ninth data bit
goes into RB80 (SCON0.2) and the stop bit is ignored.
Data transmission begins when an instruction writes a data byte to the SBUF0 register. The TI0 Transmit
Interrupt Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data
reception can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to 1. After the stop bit is
received, the data byte will be loaded into the SBUF0 receive register if the following conditions are met:
(1) RI0 must be logic 0, and (2) if MCE0 is logic 1, the 9th bit must be logic 1 (when MCE0 is logic 0, the
state of the ninth data bit is unimportant). If these conditions are met, the eight bits of data are stored in
SBUF0, the ninth bit is stored in RB80, and the RI0 flag is set to 1. If the above conditions are not met,
SBUF0 and RB80 will not be loaded and the RI0 flag will not be set to 1. A UART0 interrupt will occur if
enabled when either TI0 or RI0 is set to 1.
MARK
START
BIT
STOP
BIT
D0
D1
D2
D3
D4
D5
D6
D7
D8
SPACE
BIT TIMES
BIT SAMPLING
Figure 25.5. 9-Bit UART Timing Diagram
218
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
25.3. Multiprocessor Communications
9-Bit UART mode supports multiprocessor communication between a master processor and one or more
slave processors by special use of the ninth data bit. When a master processor wants to transmit to one or
more slaves, it first sends an address byte to select the target(s). An address byte differs from a data byte
in that its ninth bit is logic 1; in a data byte, the ninth bit is always set to logic 0.
Setting the MCE0 bit (SCON0.5) of a slave processor configures its UART such that when a stop bit is
received, the UART will generate an interrupt only if the ninth bit is logic 1 (RB80 = 1) signifying an address
byte has been received. In the UART interrupt handler, software will compare the received address with
the slave's own assigned 8-bit address. If the addresses match, the slave will clear its MCE0 bit to enable
interrupts on the reception of the following data byte(s). Slaves that weren't addressed leave their MCE0
bits set and do not generate interrupts on the reception of the following data bytes, thereby ignoring the
data. Once the entire message is received, the addressed slave resets its MCE0 bit to ignore all transmis-
sions until it receives the next address byte.
Multiple addresses can be assigned to a single slave and/or a single address can be assigned to multiple
slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. The master
processor can be configured to receive all transmissions or a protocol can be implemented such that the
master/slave role is temporarily reversed to enable half-duplex transmission between the original master
and slave(s).
Master
Device
Slave
Device
Slave
Device
Slave
Device
V+
RX
TX
RX
TX
RX
TX
RX
TX
Figure 25.6. UART Multi-Processor Mode Interconnect Diagram
Rev. 1.2
219
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 25.1. SCON0: Serial Port 0 Control
Bit
7
6
5
4
3
2
1
0
S0MODE
MCE0
REN0
TB80
RB80
TI0
RI0
Name
Type
Reset
R/W
0
R
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Address = 0x98; Bit-Addressable
Bit
Name
Function
7
S0MODE Serial Port 0 Operation Mode.
Selects the UART0 Operation Mode.
0: 8-bit UART with Variable Baud Rate.
1: 9-bit UART with Variable Baud Rate.
6
5
Unused Read = 1b, Write = Don’t Care.
MCE0
Multiprocessor Communication Enable.
The function of this bit is dependent on the Serial Port 0 Operation Mode:
Mode 0: Checks for valid stop bit.
0: Logic level of stop bit is ignored.
1: RI0 will only be activated if stop bit is logic level 1.
Mode 1: Multiprocessor Communications Enable.
0: Logic level of ninth bit is ignored.
1: RI0 is set and an interrupt is generated only when the ninth bit is logic 1.
4
3
2
1
REN0
TB80
RB80
TI0
Receive Enable.
0: UART0 reception disabled.
1: UART0 reception enabled.
Ninth Transmission Bit.
The logic level of this bit will be sent as the ninth transmission bit in 9-bit UART Mode
(Mode 1). Unused in 8-bit mode (Mode 0).
Ninth Receive Bit.
RB80 is assigned the value of the STOP bit in Mode 0; it is assigned the value of the
9th data bit in Mode 1.
Transmit Interrupt Flag.
Set by hardware when a byte of data has been transmitted by UART0 (after the 8th bit
in 8-bit UART Mode, or at the beginning of the STOP bit in 9-bit UART Mode). When
the UART0 interrupt is enabled, setting this bit causes the CPU to vector to the UART0
interrupt service routine. This bit must be cleared manually by software.
0
RI0
Receive Interrupt Flag.
Set to 1 by hardware when a byte of data has been received by UART0 (set at the
STOP bit sampling time). When the UART0 interrupt is enabled, setting this bit to 1
causes the CPU to vector to the UART0 interrupt service routine. This bit must be
cleared manually by software.
220
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 25.2. SBUF0: Serial (UART0) Port Data Buffer
Bit
7
6
5
4
3
2
1
0
SBUF0[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Address = 0x99
Bit Name
7:0 SBUF0[7:0] Serial Data Buffer Bits 7–0 (MSB–LSB).
Function
This SFR accesses two registers; a transmit shift register and a receive latch register.
When data is written to SBUF0, it goes to the transmit shift register and is held for
serial transmission. Writing a byte to SBUF0 initiates the transmission. A read of
SBUF0 returns the contents of the receive latch.
Rev. 1.2
221
C8051T620/1/6/7 & C8051T320/1/2/3
Table 25.1. Timer Settings for Standard Baud Rates
Using The Internal 24.5 MHz Oscillator
Frequency: 24.5 MHz
1
Target
Baud Rate Oscillator Timer Clock
SCA1–SCA0
(pre-scale
Timer 1
Reload
Value (hex)
T1M
% Error
Divide
Factor
Source
Baud Rate
(bps)
1
select)
2
230400
115200
57600
28800
14400
9600
–0.32%
–0.32%
0.15%
–0.32%
0.15%
–0.32%
–0.32%
0.15%
106
212
426
SYSCLK
SYSCLK
SYSCLK
SYSCLK/4
SYSCLK/12
SYSCLK/12
SYSCLK/48
SYSCLK/48
XX
1
1
1
0
0
0
0
0
0xCB
0x96
0x2B
0x96
0xB9
0x96
0x96
0x2B
XX
XX
01
00
00
10
10
848
1704
2544
10176
20448
2400
1200
Notes:
1. SCA1–SCA0 and T1M bit definitions can be found in Section 28.1.
2. X = Don’t care.
Table 25.2. Timer Settings for Standard Baud Rates
Using an External 22.1184 MHz Oscillator
Frequency: 22.1184 MHz
1
Target
Baud Rate Oscillator Timer Clock
SCA1–SCA0
(pre-scale
Timer 1
Reload
Value (hex)
T1M
% Error
Divide
Factor
Source
Baud Rate
(bps)
1
select)
2
230400
115200
57600
28800
14400
9600
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
96
192
384
SYSCLK
SYSCLK
SYSCLK
XX
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0xD0
0xA0
0x40
0xE0
0xC0
0xA0
0xA0
0x40
0xFA
0xF4
0xE8
0xD0
0xA0
0x70
XX
XX
00
00
00
10
10
11
11
11
11
11
11
768
SYSCLK / 12
SYSCLK / 12
SYSCLK / 12
SYSCLK / 48
SYSCLK / 48
EXTCLK / 8
EXTCLK / 8
EXTCLK / 8
EXTCLK / 8
EXTCLK / 8
EXTCLK / 8
1536
2304
9216
18432
96
192
384
768
1536
2304
2400
1200
230400
115200
57600
28800
14400
9600
Notes:
1. SCA1–SCA0 and T1M bit definitions can be found in Section 28.1.
2. X = Don’t care.
222
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
26. UART1
UART1 is an asynchronous, full duplex serial port offering a variety of data formatting options. A dedicated
baud rate generator with a 16-bit timer and selectable prescaler is included, which can generate a wide
range of baud rates (details in Section “26.1. Baud Rate Generator” on page 223). A received data FIFO
allows UART1 to receive up to three data bytes before data is lost and an overflow occurs.
UART1 has six associated SFRs. Three are used for the Baud Rate Generator (SBCON1, SBRLH1, and
SBRLL1), two are used for data formatting, control, and status functions (SCON1, SMOD1), and one is
used to send and receive data (SBUF1). The single SBUF1 location provides access to both the transmit
holding register and the receive FIFO. Writes to SBUF1 always access the Transmit Holding Register.
Reads of SBUF1 always access the first byte of the Receive FIFO; it is not possible to read data
from the Transmit Holding Register.
With UART1 interrupts enabled, an interrupt is generated each time a transmit is completed (TI1 is set in
SCON1), or a data byte has been received (RI1 is set in SCON1). The UART1 interrupt flags are not
cleared by hardware when the CPU vectors to the interrupt service routine. They must be cleared manually
by software, allowing software to determine the cause of the UART1 interrupt (transmit complete or receive
complete). Note that if additional bytes are available in the Receive FIFO, the RI1 bit cannot be cleared by
software.
TX
Logic
Data Formatting
TX1
Baud Rate Generator
SMOD1
SBRLH1 SBRLL1
Overflow
TX Holding
Register
Pre-Scaler
(1, 4, 12, 48)
SYSCLK
Timer (16-bit)
EN
Write to SBUF1
Read of SBUF1
SBUF1
Control / Status
SCON1
RX FIFO
(3 Deep)
SBCON1
RX
RX1
Logic
UART1
Interrupt
Figure 26.1. UART1 Block Diagram
26.1. Baud Rate Generator
The UART1 baud rate is generated by a dedicated 16-bit timer which runs from the controller’s core clock
(SYSCLK), and has prescaler options of 1, 4, 12, or 48. The timer and prescaler options combined allow
for a wide selection of baud rates over many SYSCLK frequencies.
The baud rate generator is configured using three registers: SBCON1, SBRLH1, and SBRLL1. The
UART1 Baud Rate Generator Control Register (SBCON1, SFR Definition ) enables or disables the baud
rate generator, and selects the prescaler value for the timer. The baud rate generator must be enabled for
UART1 to function. Registers SBRLH1 and SBRLL1 contain a 16-bit reload value for the dedicated 16-bit
timer. The internal timer counts up from the reload value on every clock tick. On timer overflows (0xFFFF
to 0x0000), the timer is reloaded. For reliable UART operation, it is recommended that the UART baud rate
is not configured for baud rates faster than SYSCLK/16. The baud rate for UART1 is defined in
Equation 26.1.
Rev. 1.2
223
C8051T620/1/6/7 & C8051T320/1/2/3
SYSCLK
1
1
--------------------------------------------------------------------------- -- ---------------------
Baud Rate =
× ×
(65536 – (SBRLH1:SBRLL1)) 2 Prescaler
Equation 26.1. UART1 Baud Rate
A quick reference for typical baud rates and system clock frequencies is given in Table 26.1.
Table 26.1. Baud Rate Generator Settings for Standard Baud Rates
Target Baud Actual Baud Baud Rate
Oscillator
Divide
SB1PS[1:0]
Reload Value in
SBRLH1:SBRLL1
Rate (bps)
Rate (bps)
Error
(Prescaler Bits)
Factor
230400
115200
57600
28800
14400
9600
230769
115385
57692
28846
14388
9600
0.16%
0.16%
0.16%
0.16%
0.08%
0.0%
52
104
208
416
834
1250
5000
10000
104
208
416
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
0xFFE6
0xFFCC
0xFF98
0xFF30
0xFE5F
0xFD8F
0xF63C
0xEC78
0xFFCC
0xFF98
0xFF30
0xFE5F
0xFCBF
0xFB1E
0xEC78
0xD8F0
0xFF98
0xFF30
0xFE5F
0xFCBF
0xF97D
0xF63C
0xD8F0
0xB1E0
2400
1200
2400
1200
0.0%
0.0%
230400
115200
57600
28800
14400
9600
230769
115385
57692
28777
14406
9600
0.16%
0.16%
0.16%
0.08%
0.04%
0.0%
834
1666
2500
10000
20000
208
2400
1200
2400
1200
0.0%
0.0%
230400
115200
57600
28800
14400
9600
230769
115385
57554
28812
14397
9600
0.16%
0.16%
0.08%
0.04%
0.02%
0.0%
416
834
1666
3334
5000
20000
40000
2400
1200
2400
1200
0.0%
0.0%
224
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
26.2. Data Format
UART1 has a number of available options for data formatting. Data transfers begin with a start bit (logic
low), followed by the data bits (sent LSB-first), a parity or extra bit (if selected), and end with one or two
stop bits (logic high). The data length is variable between 5 and 8 bits. A parity bit can be appended to the
data, and automatically generated and detected by hardware for even, odd, mark, or space parity. The stop
bit length is selectable between short (1 bit time) and long (1.5 or 2 bit times), and a multi-processor com-
munication mode is available for implementing networked UART buses. All of the data formatting options
can be configured using the SMOD1 register, shown in SFR Definition . Figure 26.2 shows the timing for a
UART1 transaction without parity or an extra bit enabled. Figure 26.3 shows the timing for a UART1 trans-
action with parity enabled (PE1 = 1). Figure 26.4 is an example of a UART1 transaction when the extra bit
is enabled (XBE1 = 1). Note that the extra bit feature is not available when parity is enabled, and the sec-
ond stop bit is only an option for data lengths of 6, 7, or 8 bits.
MARK
START
BIT
STOP
BIT 1
STOP
BIT 2
D0
D1
DN-2
DN-1
SPACE
BIT TIMES
Optional
N bits; N = 5, 6, 7, or 8
Figure 26.2. UART1 Timing Without Parity or Extra Bit
MARK
START
BIT
STOP
BIT 1
STOP
BIT 2
D0
D1
DN-2
DN-1
PARITY
SPACE
BIT TIMES
Optional
N bits; N = 5, 6, 7, or 8
Figure 26.3. UART1 Timing With Parity
MARK
START
BIT
STOP
BIT 1
STOP
BIT 2
D0
D1
DN-2
DN-1
EXTRA
SPACE
BIT TIMES
Optional
N bits; N = 5, 6, 7, or 8
Figure 26.4. UART1 Timing With Extra Bit
Rev. 1.2
225
C8051T620/1/6/7 & C8051T320/1/2/3
26.3. Configuration and Operation
UART1 provides standard asynchronous, full duplex communication. It can operate in a point-to-point
serial communications application, or as a node on a multi-processor serial interface. To operate in a point-
to-point application, where there are only two devices on the serial bus, the MCE1 bit in SMOD1 should be
cleared to 0. For operation as part of a multi-processor communications bus, the MCE1 and XBE1 bits
should both be set to 1. In both types of applications, data is transmitted from the microcontroller on the
TX1 pin, and received on the RX1 pin. The TX1 and RX1 pins are configured using the crossbar and the
Port I/O registers, as detailed in Section “22. Port Input/Output” on page 138.
In typical UART communications, The transmit (TX) output of one device is connected to the receive (RX)
input of the other device, either directly or through a bus transceiver, as shown in Figure 26.5.
TX
RS-232
LEVEL
TRANSLATOR
PC
COM Port
RS-232
C8051Fxxx
RX
OR
TX
RX
TX
RX
MCU
C8051Fxxx
Figure 26.5. Typical UART Interconnect Diagram
26.3.1. Data Transmission
Data transmission is double-buffered, and begins when software writes a data byte to the SBUF1 register.
Writing to SBUF1 places data in the Transmit Holding Register, and the Transmit Holding Register Empty
flag (THRE1) will be cleared to 0. If the UARTs shift register is empty (i.e. no transmission is in progress)
the data will be placed in the shift register, and the THRE1 bit will be set to 1. If a transmission is in prog-
ress, the data will remain in the Transmit Holding Register until the current transmission is complete. The
TI1 Transmit Interrupt Flag (SCON1.1) will be set at the end of any transmission (the beginning of the stop-
bit time). If enabled, an interrupt will occur when TI1 is set.
If the extra bit function is enabled (XBE1 = 1) and the parity function is disabled (PE1 = 0), the value of the
TBX1 (SCON1.3) bit will be sent in the extra bit position. When the parity function is enabled (PE1 = 1),
hardware will generate the parity bit according to the selected parity type (selected with S1PT[1:0]), and
append it to the data field. Note: when parity is enabled, the extra bit function is not available.
26.3.2. Data Reception
Data reception can begin any time after the REN1 Receive Enable bit (SCON1.4) is set to logic 1. After the
stop bit is received, the data byte will be stored in the receive FIFO if the following conditions are met: the
receive FIFO (3 bytes deep) must not be full, and the stop bit(s) must be logic 1. In the event that the
receive FIFO is full, the incoming byte will be lost, and a Receive FIFO Overrun Error will be generated
(OVR1 in register SCON1 will be set to logic 1). If the stop bit(s) were logic 0, the incoming data will not be
stored in the receive FIFO. If the reception conditions are met, the data is stored in the receive FIFO, and
the RI1 flag will be set. Note: when MCE1 = 1, RI1 will only be set if the extra bit was equal to 1. Data can
be read from the receive FIFO by reading the SBUF1 register.
226
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
The SBUF1 register represents the oldest byte in the FIFO. After SBUF1 is read, the next byte in the FIFO
is immediately loaded into SBUF1, and space is made available in the FIFO for another incoming byte. If
enabled, an interrupt will occur when RI1 is set. RI1 can only be cleared to '0' by software when there is no
more information in the FIFO. The recommended procedure to empty the FIFO contents is:
1. Clear RI1 to '0'
2. Read SBUF1
3. Check RI1, and repeat at Step 1 if RI1 is set to '1'.
If the extra bit function is enabled (XBE1 = 1) and the parity function is disabled (PE1 = 0), the extra bit for
the oldest byte in the FIFO can be read from the RBX1 bit (SCON1.2). If the extra bit function is not
enabled, the value of the stop bit for the oldest FIFO byte will be presented in RBX1. When the parity func-
tion is enabled (PE1 = 1), hardware will check the received parity bit against the selected parity type
(selected with S1PT[1:0]) when receiving data. If a byte with parity error is received, the PERR1 flag will be
set to 1. This flag must be cleared by software. Note: when parity is enabled, the extra bit function is not
available.
26.3.3. Multiprocessor Communications
UART1 supports multiprocessor communication between a master processor and one or more slave pro-
cessors by special use of the extra data bit. When a master processor wants to transmit to one or more
slaves, it first sends an address byte to select the target(s). An address byte differs from a data byte in that
its extra bit is logic 1; in a data byte, the extra bit is always set to logic 0.
Setting the MCE1 bit (SMOD1.7) of a slave processor configures its UART such that when a stop bit is
received, the UART will generate an interrupt only if the extra bit is logic 1 (RBX1 = 1) signifying an
address byte has been received. In the UART interrupt handler, software will compare the received
address with the slave's own assigned address. If the addresses match, the slave will clear its MCE1 bit to
enable interrupts on the reception of the following data byte(s). Slaves that weren't addressed leave their
MCE1 bits set and do not generate interrupts on the reception of the following data bytes, thereby ignoring
the data. Once the entire message is received, the addressed slave resets its MCE1 bit to ignore all trans-
missions until it receives the next address byte.
Multiple addresses can be assigned to a single slave and/or a single address can be assigned to multiple
slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. The master
processor can be configured to receive all transmissions or a protocol can be implemented such that the
master/slave role is temporarily reversed to enable half-duplex transmission between the original master
and slave(s).
Master
Device
Slave
Device
Slave
Device
Slave
Device
V+
RX
TX
RX
TX
RX
TX
RX
TX
Figure 26.6. UART Multi-Processor Mode Interconnect Diagram
Rev. 1.2
227
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 26.1. SCON1: UART1 Control
Bit
7
6
5
4
3
2
1
0
OVR1
PERR1
THRE1
REN1
TBX1
RBX1
TI1
RI1
Name
Type
Reset
R/W
0
R/W
0
R
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Address = 0xD2
Bit
Name
Function
7
OVR1
Receive FIFO Overrun Flag.
This bit indicates a receive FIFO overrun condition, where an incoming character is discarded
due to a full FIFO. This bit must be cleared to 0 by software.
0: Receive FIFO Overrun has not occurred.
1: Receive FIFO Overrun has occurred.
6
PERR1
Parity Error Flag.
When parity is enabled, this bit indicates that a parity error has occurred. It is set to 1 when the
parity of the oldest byte in the FIFO does not match the selected Parity Type. This bit must be
cleared to 0 by software.
0: Parity Error has not occurred.
1: Parity Error has occurred.
5
4
THRE1
REN1
Transmit Holding Register Empty Flag.
0: Transmit Holding Register not Empty - do not write to SBUF1.
1: Transmit Holding Register Empty - it is safe to write to SBUF1.
Receive Enable.
This bit enables/disables the UART receiver. When disabled, bytes can still be read from the
receive FIFO.
0: UART1 reception disabled.
1: UART1 reception enabled.
3
2
1
TBX1
RBX1
TI1
Extra Transmission Bit.
The logic level of this bit will be assigned to the extra transmission bit when XBE1 = 1. This bit is
not used when Parity is enabled.
Extra Receive Bit.
RBX1 is assigned the value of the extra bit when XBE1 = 1. If XBE1 is cleared to 0, RBX1 is
assigned the logic level of the first stop bit. This bit is not valid when Parity is enabled.
Transmit Interrupt Flag.
Set to a 1 by hardware after data has been transmitted at the beginning of the STOP bit. When
the UART1 interrupt is enabled, setting this bit causes the CPU to vector to the UART1 interrupt
service routine. This bit must be cleared manually by software.
0
RI1
Receive Interrupt Flag.
Set to 1 by hardware when a byte of data has been received by UART1 (set at the STOP bit sam-
pling time). When the UART1 interrupt is enabled, setting this bit to 1 causes the CPU to vector
to the UART1 interrupt service routine. This bit must be cleared manually by software. Note that
RI1 will remain set to '1' as long as there is still data in the UART FIFO. After the last byte has
been shifted from the FIFO to SBUF1, RI1 can be cleared.
228
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 26.2. SMOD1: UART1 Mode
Bit
7
6
5
4
3
2
1
0
MCE1
S1PT[1:0]
R/W
PE1
S1DL[1:0]
R/W
XBE1
SBL1
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
0
0
1
1
SFR Address = 0xE5
Bit
Name
Function
7
MCE1
Multiprocessor Communication Enable.
0: RI will be activated if stop bit(s) are 1.
1: RI will be activated if stop bit(s) and extra bit are 1 (extra bit must be enabled using
XBE1).
Note: This function is not available when hardware parity is enabled.
6:5 S1PT[1:0]
Parity Type Bits.
00: Odd
01: Even
10: Mark
11: Space
4
PE1
Parity Enable.
This bit activates hardware parity generation and checking. The parity type is selected
by bits S1PT1-0 when parity is enabled.
0: Hardware parity is disabled.
1: Hardware parity is enabled.
3:2 S1DL[1:0]
Data Length.
00: 5-bit data
01: 6-bit data
10: 7-bit data
11: 8-bit data
1
0
XBE1
SBL1
Extra Bit Enable.
When enabled, the value of TBX1 will be appended to the data field.
0: Extra Bit Disabled.
1: Extra Bit Enabled.
Stop Bit Length.
0: Short - Stop bit is active for one bit time.
1: Long - Stop bit is active for two bit times (data length = 6, 7, or 8 bits), or 1.5 bit times
(data length = 5 bits).
Rev. 1.2
229
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 26.3. SBUF1: UART1 Data Buffer
Bit
7
6
5
4
3
2
1
0
SBUF1[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xD3
Bit Name
Description
Write
Read
Reading SBUF1 retrieves
initiates the transmission. data from the receive
7:0 SBUF1[7:0
]
Writing a byte to SBUF1
Serial Data Buffer Bits.
This SFR is used to both send
data from the UART and to
read received data from the
UART1 receive FIFO.
When data is written to
SBUF1, it first goes to the est byte in the receive
Transmit Holding Register, FIFO is returned, and
where it is held for serial
transmission. When the
transmit shift register is
available, data is trans-
FIFO. When read, the old-
removed from the FIFO.
Up to three bytes may be
held in the FIFO. If there
are additional bytes avail-
ferred into the shift regis- able in the FIFO, the RI1
ter, and SBUF1 may be
written again.
bit will remain at logic 1,
even after being cleared
by software.
230
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 26.4. SBCON1: UART1 Baud Rate Generator Control
Bit
7
6
5
4
3
2
1
0
Reserved SB1RUN Reserved Reserved Reserved Reserved
SB1PS[1:0]
R/W
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
0
SFR Address = 0xAC
Bit
Name
Reserved Read = 0b. Must Write 0b.
SB1RUN
Function
7
6
Baud Rate Generator Enable.
0: Baud Rate Generator is disabled. UART1 will not function.
1: Baud Rate Generator is enabled.
5:2 Reserved Read = 0000b. Must Write 0000b.
1:0 SB1PS[1:0]
Baud Rate Prescaler Select.
00: Prescaler = 12
01: Prescaler = 4
10: Prescaler = 48
11: Prescaler = 1
SFR Definition 26.5. SBRLH1: UART1 Baud Rate Generator High Byte
Bit
7
6
5
4
3
2
1
0
SBRLH1[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xB5
Bit Name
7:0 SBRLH1[7:0]
Function
UART1 Baud Rate Reload High Bits.
High Byte of reload value for UART1 Baud Rate Generator.
Rev. 1.2
231
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 26.6. SBRLL1: UART1 Baud Rate Generator Low Byte
Bit
7
6
5
4
3
2
1
0
SBRLL1[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xB4
Bit Name
7:0 SBRLL1[7:0]
Function
UART1 Baud Rate Reload Low Bits.
Low Byte of reload value for UART1 Baud Rate Generator.
232
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
27. Enhanced Serial Peripheral Interface (SPI0)
The Enhanced Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous
serial bus. SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports mul-
tiple masters and slaves on a single SPI bus. The slave-select (NSS) signal can be configured as an input
to select SPI0 in slave mode, or to disable Master Mode operation in a multi-master environment, avoiding
contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS can
also be configured as a chip-select output in master mode, or disabled for 3-wire operation. Additional gen-
eral purpose port I/O pins can be used to select multiple slave devices in master mode.
SFR Bus
SPI0CKR
SPI0CFG
SPI0CN
Clock Divide
Logic
SYSCLK
SPI CONTROL LOGIC
SPI IRQ
Data Path
Control
Pin Interface
Control
MOSI
Tx Data
C
R
O
S
S
B
A
R
SPI0DAT
SCK
MISO
NSS
Transmit Data Buffer
Pin
Control
Logic
Port I/O
Shift Register
Rx Data
7 6 5 4 3 2 1 0
Receive Data Buffer
Read
SPI0DAT
Write
SPI0DAT
SFR Bus
Figure 27.1. SPI Block Diagram
Rev. 1.2
233
C8051T620/1/6/7 & C8051T320/1/2/3
27.1. Signal Descriptions
The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below.
27.1.1. Master Out, Slave In (MOSI)
The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices. It
is used to serially transfer data from the master to the slave. This signal is an output when SPI0 is operat-
ing as a master and an input when SPI0 is operating as a slave. Data is transferred most-significant bit
first. When configured as a master, MOSI is driven by the MSB of the shift register in both 3- and 4-wire
mode.
27.1.2. Master In, Slave Out (MISO)
The master-in, slave-out (MISO) signal is an output from a slave device and an input to the master device.
It is used to serially transfer data from the slave to the master. This signal is an input when SPI0 is operat-
ing as a master and an output when SPI0 is operating as a slave. Data is transferred most-significant bit
first. The MISO pin is placed in a high-impedance state when the SPI module is disabled and when the SPI
operates in 4-wire mode as a slave that is not selected. When acting as a slave in 3-wire mode, MISO is
always driven by the MSB of the shift register.
27.1.3. Serial Clock (SCK)
The serial clock (SCK) signal is an output from the master device and an input to slave devices. It is used
to synchronize the transfer of data between the master and slave on the MOSI and MISO lines. SPI0 gen-
erates this signal when operating as a master. The SCK signal is ignored by a SPI slave when the slave is
not selected (NSS = 1) in 4-wire slave mode.
27.1.4. Slave Select (NSS)
The function of the slave-select (NSS) signal is dependent on the setting of the NSSMD1 and NSSMD0
bits in the SPI0CN register. There are three possible modes that can be selected with these bits:
1. NSSMD[1:0] = 00: 3-Wire Master or 3-Wire Slave Mode: SPI0 operates in 3-wire mode, and NSS is
disabled. When operating as a slave device, SPI0 is always selected in 3-wire mode. Since no select
signal is present, SPI0 must be the only slave on the bus in 3-wire mode. This is intended for point-to-
point communication between a master and one slave.
2. NSSMD[1:0] = 01: 4-Wire Slave or Multi-Master Mode: SPI0 operates in 4-wire mode, and NSS is
enabled as an input. When operating as a slave, NSS selects the SPI0 device. When operating as a
master, a 1-to-0 transition of the NSS signal disables the master function of SPI0 so that multiple
master devices can be used on the same SPI bus.
3. NSSMD[1:0] = 1x: 4-Wire Master Mode: SPI0 operates in 4-wire mode, and NSS is enabled as an
output. The setting of NSSMD0 determines what logic level the NSS pin will output. This configuration
should only be used when operating SPI0 as a master device.
See Figure 27.2, Figure 27.3, and Figure 27.4 for typical connection diagrams of the various operational
modes. Note that the setting of NSSMD bits affects the pinout of the device. When in 3-wire master or
3-wire slave mode, the NSS pin will not be mapped by the crossbar. In all other modes, the NSS signal will
be mapped to a pin on the device. See Section “22. Port Input/Output” on page 138 for general purpose
port I/O and crossbar information.
234
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
27.2. SPI0 Master Mode Operation
A SPI master device initiates all data transfers on a SPI bus. SPI0 is placed in master mode by setting the
Master Enable flag (MSTEN, SPI0CN.6). Writing a byte of data to the SPI0 data register (SPI0DAT) when
in master mode writes to the transmit buffer. If the SPI shift register is empty, the byte in the transmit buffer
is moved to the shift register, and a data transfer begins. The SPI0 master immediately shifts out the data
serially on the MOSI line while providing the serial clock on SCK.
The SPIF (SPI0CN.7) flag is set to logic 1 at the end of the transfer. If interrupts are enabled, an interrupt
request is generated when the SPIF flag is set. While the SPI0 master transfers data to a slave on the
MOSI line, the addressed SPI slave device simultaneously transfers the contents of its shift register to the
SPI master on the MISO line in a full-duplex operation. Therefore, the SPIF flag serves as both a transmit-
complete and receive-data-ready flag. The data byte received from the slave is transferred MSB-first into
the master's shift register. When a byte is fully shifted into the register, it is moved to the receive buffer
where it can be read by the processor by reading SPI0DAT.
When configured as a master, SPI0 can operate in one of three different modes: multi-master mode, 3-wire
single-master mode, and 4-wire single-master mode. The default, multi-master mode is active when NSS-
MD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In this mode, NSS is an input to the device, and is
used to disable the master SPI0 when another master is accessing the bus. When NSS is pulled low in this
mode, MSTEN (SPI0CN.6) and SPIEN (SPI0CN.0) are set to 0 to disable the SPI master device, and a
Mode Fault is generated (MODF, SPI0CN.5 = 1). Mode Fault will generate an interrupt if enabled. SPI0
must be manually re-enabled in software under these circumstances. In multi-master systems, devices will
typically default to being slave devices while they are not acting as the system master device. In multi-mas-
ter mode, slave devices can be addressed individually (if needed) using general-purpose I/O pins.
Figure 27.2 shows a connection diagram between two master devices in multiple-master mode.
3-wire single-master mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 0. In this
mode, NSS is not used, and is not mapped to an external port pin through the crossbar. Any slave devices
that must be addressed in this mode should be selected using general-purpose I/O pins. Figure 27.3
shows a connection diagram between a master device in 3-wire master mode and a slave device.
4-wire single-master mode is active when NSSMD1 (SPI0CN.3) = 1. In this mode, NSS is configured as an
output pin, and can be used as a slave-select signal for a single SPI device. In this mode, the output value
of NSS is controlled (in software) with the bit NSSMD0 (SPI0CN.2). Additional slave devices can be
addressed using general-purpose I/O pins. Figure 27.4 shows a connection diagram for a master device in
4-wire master mode and two slave devices.
NSS
MISO
MOSI
SCK
GPIO
MISO
MOSI
SCK
Master
Device 1
Master
Device 2
GPIO
NSS
Figure 27.2. Multiple-Master Mode Connection Diagram
Master
Device
Slave
Device
MISO
MOSI
SCK
MISO
MOSI
SCK
Figure 27.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram
Rev. 1.2
235
C8051T620/1/6/7 & C8051T320/1/2/3
MISO
MOSI
SCK
MISO
MOSI
SCK
Master
Device
Slave
Device
NSS
NSS
GPIO
MISO
MOSI
SCK
Slave
Device
NSS
Figure 27.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram
27.3. SPI0 Slave Mode Operation
When SPI0 is enabled and not configured as a master, it will operate as a SPI slave. As a slave, bytes are
shifted in through the MOSI pin and out through the MISO pin by a master device controlling the SCK sig-
nal. A bit counter in the SPI0 logic counts SCK edges. When 8 bits have been shifted through the shift reg-
ister, the SPIF flag is set to logic 1, and the byte is copied into the receive buffer. Data is read from the
receive buffer by reading SPI0DAT. A slave device cannot initiate transfers. Data to be transferred to the
master device is pre-loaded into the shift register by writing to SPI0DAT. Writes to SPI0DAT are double-
buffered, and are placed in the transmit buffer first. If the shift register is empty, the contents of the transmit
buffer will immediately be transferred into the shift register. When the shift register already contains data,
the SPI will load the shift register with the transmit buffer’s contents after the last SCK edge of the next (or
current) SPI transfer.
When configured as a slave, SPI0 can be configured for 4-wire or 3-wire operation. The default, 4-wire
slave mode, is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In 4-wire mode, the
NSS signal is routed to a port pin and configured as a digital input. SPI0 is enabled when NSS is logic 0,
and disabled when NSS is logic 1. The bit counter is reset on a falling edge of NSS. Note that the NSS sig-
nal must be driven low at least 2 system clocks before the first active edge of SCK for each byte transfer.
Figure 27.4 shows a connection diagram between two slave devices in 4-wire slave mode and a master
device.
3-wire slave mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 0. NSS is not
used in this mode, and is not mapped to an external port pin through the crossbar. Since there is no way of
uniquely addressing the device in 3-wire slave mode, SPI0 must be the only slave device present on the
bus. It is important to note that in 3-wire slave mode there is no external means of resetting the bit counter
that determines when a full byte has been received. The bit counter can only be reset by disabling and re-
enabling SPI0 with the SPIEN bit. Figure 27.3 shows a connection diagram between a slave device in 3-
wire slave mode and a master device.
236
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
27.4. SPI0 Interrupt Sources
When SPI0 interrupts are enabled, the following four flags will generate an interrupt when they are set to
logic 1:
All of the following bits must be cleared by software.
The SPI Interrupt Flag, SPIF (SPI0CN.7) is set to logic 1 at the end of each byte transfer. This flag can
occur in all SPI0 modes.
The Write Collision Flag, WCOL (SPI0CN.6) is set to logic 1 if a write to SPI0DAT is attempted when
the transmit buffer has not been emptied to the SPI shift register. When this occurs, the write to
SPI0DAT will be ignored, and the transmit buffer will not be written.This flag can occur in all SPI0
modes.
The Mode Fault Flag MODF (SPI0CN.5) is set to logic 1 when SPI0 is configured as a master, and for
multi-master mode and the NSS pin is pulled low. When a Mode Fault occurs, the MSTEN and SPIEN
bits in SPI0CN are set to logic 0 to disable SPI0 and allow another master device to access the bus.
The Receive Overrun Flag RXOVRN (SPI0CN.4) is set to logic 1 when configured as a slave, and a
transfer is completed and the receive buffer still holds an unread byte from a previous transfer. The new
byte is not transferred to the receive buffer, allowing the previously received data byte to be read. The
data byte which caused the overrun is lost.
27.5. Serial Clock Phase and Polarity
Four combinations of serial clock phase and polarity can be selected using the clock control bits in the
SPI0 Configuration Register (SPI0CFG). The CKPHA bit (SPI0CFG.5) selects one of two clock phases
(edge used to latch the data). The CKPOL bit (SPI0CFG.4) selects between an active-high or active-low
clock. Both master and slave devices must be configured to use the same clock phase and polarity. SPI0
should be disabled (by clearing the SPIEN bit, SPI0CN.0) when changing the clock phase or polarity. The
clock and data line relationships for master mode are shown in Figure 27.5. For slave mode, the clock and
data relationships are shown in Figure 27.6 and Figure 27.7. Note that CKPHA should be set to 0 on both
the master and slave SPI when communicating between two Silicon Labs C8051 devices.
The SPI0 Clock Rate Register (SPI0CKR) as shown in SFR Definition 27.3 controls the master mode
serial clock frequency. This register is ignored when operating in slave mode. When the SPI is configured
as a master, the maximum data transfer rate (bits/sec) is one-half the system clock frequency or 12.5 MHz,
whichever is slower. When the SPI is configured as a slave, the maximum data transfer rate (bits/sec) for
full-duplex operation is 1/10 the system clock frequency, provided that the master issues SCK, NSS (in 4-
wire slave mode), and the serial input data synchronously with the slave’s system clock. If the master
issues SCK, NSS, and the serial input data asynchronously, the maximum data transfer rate (bits/sec)
must be less than 1/10 the system clock frequency. In the special case where the master only wants to
transmit data to the slave and does not need to receive data from the slave (i.e. half-duplex operation), the
SPI slave can receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency.
This is provided that the master issues SCK, NSS, and the serial input data synchronously with the slave’s
system clock.
Rev. 1.2
237
C8051T620/1/6/7 & C8051T320/1/2/3
SCK
(CKPOL=0, CKPHA=0)
SCK
(CKPOL=0, CKPHA=1)
SCK
(CKPOL=1, CKPHA=0)
SCK
(CKPOL=1, CKPHA=1)
MISO/MOSI
MSB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
NSS (Must Remain High
in Multi-Master Mode)
Figure 27.5. Master Mode Data/Clock Timing
SCK
(CKPOL=0, CKPHA=0)
SCK
(CKPOL=1, CKPHA=0)
MOSI
MSB
MSB
Bit 6
Bit 6
Bit 5
Bit 5
Bit 4
Bit 4
Bit 3
Bit 3
Bit 2
Bit 2
Bit 1
Bit 0
MISO
Bit 1
Bit 0
NSS (4-Wire Mode)
Figure 27.6. Slave Mode Data/Clock Timing (CKPHA = 0)
238
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
SCK
(CKPOL=0, CKPHA=1)
SCK
(CKPOL=1, CKPHA=1)
MOSI
MSB
MSB
Bit 6
Bit 6
Bit 5
Bit 5
Bit 4
Bit 4
Bit 3
Bit 3
Bit 2
Bit 2
Bit 1
Bit 1
Bit 0
MISO
Bit 0
NSS (4-Wire Mode)
Figure 27.7. Slave Mode Data/Clock Timing (CKPHA = 1)
27.6. SPI Special Function Registers
SPI0 is accessed and controlled through four special function registers in the system controller: SPI0CN
Control Register, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate
Register. The four special function registers related to the operation of the SPI0 Bus are described in the
following figures.
Rev. 1.2
239
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 27.1. SPI0CFG: SPI0 Configuration
Bit
7
6
5
4
3
2
1
0
SPIBSY
MSTEN
CKPHA
CKPOL
SLVSEL
NSSIN
SRMT
RXBMT
Name
Type
Reset
R
0
R/W
0
R/W
0
R/W
0
R
0
R
1
R
1
R
1
SFR Address = 0xA1
Bit
Name
Function
7
SPIBSY
SPI Busy.
This bit is set to logic 1 when a SPI transfer is in progress (master or slave mode).
6
5
4
3
MSTEN
CKPHA
CKPOL
SLVSEL
Master Mode Enable.
0: Disable master mode. Operate in slave mode.
1: Enable master mode. Operate as a master.
SPI0 Clock Phase.
*
0: Data centered on first edge of SCK period.
1: Data centered on second edge of SCK period.
*
SPI0 Clock Polarity.
0: SCK line low in idle state.
1: SCK line high in idle state.
Slave Selected Flag.
This bit is set to logic 1 whenever the NSS pin is low indicating SPI0 is the selected
slave. It is cleared to logic 0 when NSS is high (slave not selected). This bit does
not indicate the instantaneous value at the NSS pin, but rather a de-glitched ver-
sion of the pin input.
2
1
NSSIN
SRMT
NSS Instantaneous Pin Input.
This bit mimics the instantaneous value that is present on the NSS port pin at the
time that the register is read. This input is not de-glitched.
Shift Register Empty (valid in slave mode only).
This bit will be set to logic 1 when all data has been transferred in/out of the shift
register, and there is no new information available to read from the transmit buffer
or write to the receive buffer. It returns to logic 0 when a data byte is transferred to
the shift register from the transmit buffer or by a transition on SCK. SRMT = 1 when
in Master Mode.
0
RXBMT
Receive Buffer Empty (valid in slave mode only).
This bit will be set to logic 1 when the receive buffer has been read and contains no
new information. If there is new information available in the receive buffer that has
not been read, this bit will return to logic 0. RXBMT = 1 when in Master Mode.
Note: In slave mode, data on MOSI is sampled in the center of each data bit. In master mode, data on MISO is
sampled one SYSCLK before the end of each data bit, to provide maximum settling time for the slave device.
See Table 27.1 for timing parameters.
240
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 27.2. SPI0CN: SPI0 Control
Bit
7
6
5
4
3
2
1
0
SPIF
WCOL
MODF
RXOVRN
NSSMD[1:0]
R/W
TXBMT
SPIEN
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R
1
R/W
0
0
1
SFR Address = 0xF8; Bit-Addressable
Bit
Name
Function
7
SPIF
SPI0 Interrupt Flag.
This bit is set to logic 1 by hardware at the end of a data transfer. If SPI interrupts
are enabled, an interrupt will be generated. This bit is not automatically cleared by
hardware, and must be cleared by software.
6
5
4
WCOL
MODF
Write Collision Flag.
This bit is set to logic 1 if a write to SPI0DAT is attempted when TXBMT is 0. When
this occurs, the write to SPI0DAT will be ignored, and the transmit buffer will not be
written. If SPI interrupts are enabled, an interrupt will be generated. This bit is not
automatically cleared by hardware, and must be cleared by software.
Mode Fault Flag.
This bit is set to logic 1 by hardware when a master mode collision is detected
(NSS is low, MSTEN = 1, and NSSMD[1:0] = 01). If SPI interrupts are enabled, an
interrupt will be generated. This bit is not automatically cleared by hardware, and
must be cleared by software.
RXOVRN
Receive Overrun Flag (valid in slave mode only).
This bit is set to logic 1 by hardware when the receive buffer still holds unread data
from a previous transfer and the last bit of the current transfer is shifted into the
SPI0 shift register. If SPI interrupts are enabled, an interrupt will be generated. This
bit is not automatically cleared by hardware, and must be cleared by software.
3:2 NSSMD[1:0]
Slave Select Mode.
Selects between the following NSS operation modes:
(See Section 27.2 and Section 27.3).
00: 3-Wire Slave or 3-Wire Master Mode. NSS signal is not routed to a port pin.
01: 4-Wire Slave or Multi-Master Mode (Default). NSS is an input to the device.
1x: 4-Wire Single-Master Mode. NSS signal is mapped as an output from the
device and will assume the value of NSSMD0.
1
0
TXBMT
SPIEN
Transmit Buffer Empty.
This bit will be set to logic 0 when new data has been written to the transmit buffer.
When data in the transmit buffer is transferred to the SPI shift register, this bit will
be set to logic 1, indicating that it is safe to write a new byte to the transmit buffer.
SPI0 Enable.
0: SPI disabled.
1: SPI enabled.
Rev. 1.2
241
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 27.3. SPI0CKR: SPI0 Clock Rate
Bit
7
6
5
4
3
2
1
0
SCR[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xA2
Bit
Name
Function
7:0
SCR[7:0]
SPI0 Clock Rate.
These bits determine the frequency of the SCK output when the SPI0 module is
configured for master mode operation. The SCK clock frequency is a divided ver-
sion of the system clock, and is given in the following equation, where SYSCLK is
the system clock frequency and SPI0CKR is the 8-bit value held in the SPI0CKR
register.
SYSCLK
2 × (SPI0CKR[7:0] + 1)
----------------------------------------------------------
=
fSCK
for 0 <= SPI0CKR <= 255
Example: If SYSCLK = 2 MHz and SPI0CKR = 0x04,
2000000
2 × (4 + 1)
-------------------------
=
fSCK
fSCK = 200kHz
SFR Definition 27.4. SPI0DAT: SPI0 Data
Bit
7
6
5
4
3
2
1
0
SPI0DAT[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xA3
Bit Name
7:0 SPI0DAT[7:0]
Function
SPI0 Transmit and Receive Data.
The SPI0DAT register is used to transmit and receive SPI0 data. Writing data to
SPI0DAT places the data into the transmit buffer and initiates a transfer when in
Master Mode. A read of SPI0DAT returns the contents of the receive buffer.
242
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
SCK*
T
T
MCKH
MCKL
T
T
MIS
MIH
MISO
MOSI
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
Figure 27.8. SPI Master Timing (CKPHA = 0)
SCK*
T
T
MCKH
MCKL
T
T
MIH
MIS
MISO
MOSI
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
Figure 27.9. SPI Master Timing (CKPHA = 1)
Rev. 1.2
243
C8051T620/1/6/7 & C8051T320/1/2/3
NSS
T
T
T
SD
SE
CKL
SCK*
T
CKH
T
T
SIH
SIS
MOSI
MISO
T
T
T
SDZ
SEZ
SOH
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
Figure 27.10. SPI Slave Timing (CKPHA = 0)
NSS
T
T
T
SD
SE
CKL
SCK*
T
CKH
T
T
SIH
SIS
MOSI
T
T
T
SDZ
T
SOH
SLH
SEZ
MISO
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
Figure 27.11. SPI Slave Timing (CKPHA = 1)
244
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
Table 27.1. SPI Slave Timing Parameters
Parameter
Description
Min
Max
Units
Master Mode Timing (See Figure 27.8 and Figure 27.9)
T
T
T
T
SCK High Time
1 x T
—
—
—
—
ns
ns
ns
ns
MCKH
MCKL
MIS
SYSCLK
SYSCLK
SCK Low Time
1 x T
1 x T
MISO Valid to SCK Shift Edge
SCK Shift Edge to MISO Change
+ 20
SYSCLK
0
MIH
Slave Mode Timing (See Figure 27.10 and Figure 27.11)
T
T
T
T
T
T
T
T
T
T
NSS Falling to First SCK Edge
Last SCK Edge to NSS Rising
NSS Falling to MISO Valid
NSS Rising to MISO High-Z
SCK High Time
2 x T
2 x T
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SE
SYSCLK
SD
SYSCLK
—
4 x T
SYSCLK
SEZ
SDZ
CKH
CKL
SIS
—
4 x T
SYSCLK
5 x T
5 x T
2 x T
2 x T
—
SYSCLK
SYSCLK
SYSCLK
SCK Low Time
—
—
—
MOSI Valid to SCK Sample Edge
SCK Sample Edge to MOSI Change
SCK Shift Edge to MISO Change
SIH
SOH
SLH
SYSCLK
—
4 x T
8 x T
SYSCLK
SYSCLK
Last SCK Edge to MISO Change
(CKPHA = 1 ONLY)
6 x T
SYSCLK
Note: T
is equal to one period of the device system clock (SYSCLK).
SYSCLK
Rev. 1.2
245
C8051T620/1/6/7 & C8051T320/1/2/3
28. Timers
Each MCU includes four counter/timers: two are 16-bit counter/timers compatible with those found in the
standard 8051, and two are 16-bit auto-reload timer for use with the SMBus or for general purpose use.
These timers can be used to measure time intervals, count external events and generate periodic interrupt
requests. Timer 0 and Timer 1 are nearly identical and have four primary modes of operation. Timer 2 and
Timer 3 offer 16-bit and split 8-bit timer functionality with auto-reload. Additionally, Timer 3 offers the ability
to be clocked from the external oscillator while the device is in Suspend mode, and can be used as a
wake-up source. This allows for implementation of a very low-power system, including RTC capability.
Timer 0 and Timer 1 Modes:
Timer 2 Modes:
Timer 3 Modes:
13-bit counter/timer
16-bit counter/timer
8-bit counter/timer with auto-
reload
Two 8-bit counter/timers (Timer 0
only)
16-bit timer with auto-reload
16-bit timer with auto-reload
Two 8-bit timers with auto-reload Two 8-bit timers with auto-reload
Timers 0 and 1 may be clocked by one of five sources, determined by the Timer Mode Select bits (T1M–
T0M) and the Clock Scale bits (SCA1–SCA0). The Clock Scale bits define a pre-scaled clock from which
Timer 0 and/or Timer 1 may be clocked (See SFR Definition 28.1 for pre-scaled clock selection).
Timer 0/1 may then be configured to use this pre-scaled clock signal or the system clock. Timer 2 and
Timer 3 may be clocked by the system clock, the system clock divided by 12, or the external oscillator
clock source divided by 8.
Timer 0 and Timer 1 may also be operated as counters. When functioning as a counter, a counter/timer
register is incremented on each high-to-low transition at the selected input pin (T0 or T1). Events with a fre-
quency of up to one-fourth the system clock frequency can be counted. The input signal need not be peri-
odic, but it should be held at a given level for at least two full system clock cycles to ensure the level is
properly sampled.
Rev. 1.2
246
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 28.1. CKCON: Clock Control
Bit
7
6
5
4
3
2
1
0
T3MH
T3ML
T2MH
T2ML
T1M
T0M
SCA[1:0]
R/W
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
0
SFR Address = 0x8E
Bit
Name
Function
7
T3MH
Timer 3 High Byte Clock Select.
Selects the clock supplied to the Timer 3 high byte (split 8-bit timer mode only).
0: Timer 3 high byte uses the clock defined by the T3XCLK bit in TMR3CN.
1: Timer 3 high byte uses the system clock.
6
T3ML
Timer 3 Low Byte Clock Select.
Selects the clock supplied to Timer 3. Selects the clock supplied to the lower 8-bit timer
in split 8-bit timer mode.
0: Timer 3 low byte uses the clock defined by the T3XCLK bit in TMR3CN.
1: Timer 3 low byte uses the system clock.
5
4
T2MH
T2ML
Timer 2 High Byte Clock Select.
Selects the clock supplied to the Timer 2 high byte (split 8-bit timer mode only).
0: Timer 2 high byte uses the clock defined by the T2XCLK bit in TMR2CN.
1: Timer 2 high byte uses the system clock.
Timer 2 Low Byte Clock Select.
Selects the clock supplied to Timer 2. If Timer 2 is configured in split 8-bit timer mode,
this bit selects the clock supplied to the lower 8-bit timer.
0: Timer 2 low byte uses the clock defined by the T2XCLK bit in TMR2CN.
1: Timer 2 low byte uses the system clock.
3
2
T1
T0
Timer 1 Clock Select.
Selects the clock source supplied to Timer 1. Ignored when C/T1 is set to 1.
0: Timer 1 uses the clock defined by the prescale bits SCA[1:0].
1: Timer 1 uses the system clock.
Timer 0 Clock Select.
Selects the clock source supplied to Timer 0. Ignored when C/T0 is set to 1.
0: Counter/Timer 0 uses the clock defined by the prescale bits SCA[1:0].
1: Counter/Timer 0 uses the system clock.
1:0 SCA[1:0]
Timer 0/1 Prescale Bits.
These bits control the Timer 0/1 Clock Prescaler:
00: System clock divided by 12
01: System clock divided by 4
10: System clock divided by 48
11: External clock divided by 8 (synchronized with the system clock)
247
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
28.1. Timer 0 and Timer 1
Each timer is implemented as a 16-bit register accessed as two separate bytes: a low byte (TL0 or TL1)
and a high byte (TH0 or TH1). The Counter/Timer Control register (TCON) is used to enable Timer 0 and
Timer 1 as well as indicate status. Timer 0 interrupts can be enabled by setting the ET0 bit in the IE regis-
ter (Section “ Note that the CPU is stalled during EPROM write operations and USB FIFO MOVX accesses
(see Section “15.2.3. Accessing USB FIFO Space” on page 91). Interrupt service latency will be increased
for interrupts occurring while the CPU is stalled. The latency for these situations will be determined by the
standard interrupt service procedure (as described above) and the amount of time the CPU is stalled.” on
page 102); Timer 1 interrupts can be enabled by setting the ET1 bit in the IE register (Section “ Note that
the CPU is stalled during EPROM write operations and USB FIFO MOVX accesses (see Section
“15.2.3. Accessing USB FIFO Space” on page 91). Interrupt service latency will be increased for interrupts
occurring while the CPU is stalled. The latency for these situations will be determined by the standard
interrupt service procedure (as described above) and the amount of time the CPU is stalled.” on
page 102). Both counter/timers operate in one of four primary modes selected by setting the Mode Select
bits T1M1–T0M0 in the Counter/Timer Mode register (TMOD). Each timer can be configured inde-
pendently. Each operating mode is described below.
28.1.1. Mode 0: 13-bit Counter/Timer
Timer 0 and Timer 1 operate as 13-bit counter/timers in Mode 0. The following describes the configuration
and operation of Timer 0. However, both timers operate identically, and Timer 1 is configured in the same
manner as described for Timer 0.
The TH0 register holds the eight MSBs of the 13-bit counter/timer. TL0 holds the five LSBs in bit positions
TL0.4–TL0.0. The three upper bits of TL0 (TL0.7–TL0.5) are indeterminate and should be masked out or
ignored when reading. As the 13-bit timer register increments and overflows from 0x1FFF (all ones) to
0x0000, the timer overflow flag TF0 in TCON is set and an interrupt will occur if Timer 0 interrupts are
enabled.
The C/T0 bit in the TMOD register selects the counter/timer's clock source. When C/T0 is set to logic 1,
high-to-low transitions at the selected Timer 0 input pin (T0) increment the timer register (Refer to Section
“22.3. Priority Crossbar Decoder” on page 142 for information on selecting and configuring external I/O
pins). Clearing C/T selects the clock defined by the T0M bit in register CKCON. When T0M is set, Timer 0
is clocked by the system clock. When T0M is cleared, Timer 0 is clocked by the source selected by the
Clock Scale bits in CKCON (see SFR Definition 28.1).
Setting the TR0 bit (TCON.4) enables the timer when either GATE0 in the TMOD register is logic 0 or the
input signal INT0 is active as defined by bit IN0PL in register IT01CF (see SFR Definition 17.7). Setting
GATE0 to 1 allows the timer to be controlled by the external input signal INT0 (see Section “ Note that the
CPU is stalled during EPROM write operations and USB FIFO MOVX accesses (see Section
“15.2.3. Accessing USB FIFO Space” on page 91). Interrupt service latency will be increased for interrupts
occurring while the CPU is stalled. The latency for these situations will be determined by the standard
interrupt service procedure (as described above) and the amount of time the CPU is stalled.” on
page 102), facilitating pulse width measurements
TR0
GATE0
INT0
Counter/Timer
0
1
1
1
X
0
1
1
X
X
0
1
Disabled
Enabled
Disabled
Enabled
Note: X = Don't Care
Rev. 1.2
248
C8051T620/1/6/7 & C8051T320/1/2/3
Setting TR0 does not force the timer to reset. The timer registers should be loaded with the desired initial
value before the timer is enabled.
TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as described above for TL0 and TH0.
Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0. The
input signal INT1 is used with Timer 1; the INT1 polarity is defined by bit IN1PL in register IT01CF (see
SFR Definition 17.7).
TMOD
IT01CF
G C T T G C T T
I I I I I I I I
A
/
1
1 A
/
0
0
N N N N N N N N
T0M
T T M M T T M M
1
1 1 1 0 0 0 0
E 1
1
1
0 E 0
0
1
0
P S S S P S S S
L
L
2
L
1
L
0
L
L
2
L
1
L
0
Pre-scaled Clock
SYSCLK
0
1
0
1
TF1
TR1
TF0
TR0
IE1
T0
Interrupt
TCLK
TL0
(5 bits)
TH0
(8 bits)
TR0
IT1
GATE0
IE0
IT0
Crossbar
IN0PL
XOR
INT0
Figure 28.1. T0 Mode 0 Block Diagram
28.1.2. Mode 1: 16-bit Counter/Timer
Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The
counter/timers are enabled and configured in Mode 1 in the same manner as for Mode 0.
28.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload
Mode 2 configures Timer 0 and Timer 1 to operate as 8-bit counter/timers with automatic reload of the start
value. TL0 holds the count and TH0 holds the reload value. When the counter in TL0 overflows from all
ones to 0x00, the timer overflow flag TF0 in the TCON register is set and the counter in TL0 is reloaded
from TH0. If Timer 0 interrupts are enabled, an interrupt will occur when the TF0 flag is set. The reload
value in TH0 is not changed. TL0 must be initialized to the desired value before enabling the timer for the
first count to be correct. When in Mode 2, Timer 1 operates identically to Timer 0.
Both counter/timers are enabled and configured in Mode 2 in the same manner as Mode 0. Setting the
TR0 bit (TCON.4) enables the timer when either GATE0 in the TMOD register is logic 0 or when the input
signal INT0 is active as defined by bit IN0PL in register IT01CF (see Section “17.3. INT0 and INT1 External
Interrupt Sources” on page 110 for details on the external input signals INT0 and INT1).
249
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
TMOD
IT01CF
G C T T G C T T
I I I I I I I I
A
/
1 1 A
/
0 0
N N N N N N N N
1 1 1 1 0 0 0 0
P S S S P S S S
L L L L L L L L
T T M M T T M M
E 1 1 0 E 0 1 0
1
T0M
0
2 1
0
2 1 0
Pre-scaled Clock
SYSCLK
0
1
0
1
T0
TF1
TR1
TF0
TR0
IE1
TCLK
TL0
(8 bits)
Interrupt
TR0
IT1
IE0
IT0
Crossbar
GATE0
TH0
Reload
(8 bits)
IN0PL
XOR
INT0
Figure 28.2. T0 Mode 2 Block Diagram
28.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)
In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The
counter/timer in TL0 is controlled using the Timer 0 control/status bits in TCON and TMOD: TR0, C/T0,
GATE0 and TF0. TL0 can use either the system clock or an external input signal as its timebase. The TH0
register is restricted to a timer function sourced by the system clock or prescaled clock. TH0 is enabled
using the Timer 1 run control bit TR1. TH0 sets the Timer 1 overflow flag TF1 on overflow and thus controls
the Timer 1 interrupt.
Timer 1 is inactive in Mode 3. When Timer 0 is operating in Mode 3, Timer 1 can be operated in Modes 0,
1 or 2, but cannot be clocked by external signals nor set the TF1 flag and generate an interrupt. However,
the Timer 1 overflow can be used to generate baud rates or overflow conditions for other peripherals.
While Timer 0 is operating in Mode 3, Timer 1 run control is handled through its mode settings. To run
Timer 1 while Timer 0 is in Mode 3, set the Timer 1 Mode as 0, 1, or 2. To disable Timer 1, configure it for
Mode 3.
Rev. 1.2
250
C8051T620/1/6/7 & C8051T320/1/2/3
TMOD
G C T T G C T T
A
/
1
1 A
/ 0 0
T0M
T T M M T T M M
E 1
1
1
0 E 0
0
1 0
Pre-scaled Clock
SYSCLK
0
1
TH0
(8 bits)
TR1
Interrupt
Interrupt
TF1
TR1
TF0
TR0
IE1
0
1
IT1
IE0
IT0
T0
TL0
(8 bits)
TR0
Crossbar
GATE0
IN0PL
XOR
INT0
Figure 28.3. T0 Mode 3 Block Diagram
251
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 28.2. TCON: Timer Control
Bit
7
6
5
4
3
2
1
0
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Address = 0x88; Bit-Addressable
Bit
Name
Function
7
TF1
Timer 1 Overflow Flag.
Set to 1 by hardware when Timer 1 overflows. This flag can be cleared by software
but is automatically cleared when the CPU vectors to the Timer 1 interrupt service
routine.
6
5
TR1
TF0
Timer 1 Run Control.
Timer 1 is enabled by setting this bit to 1.
Timer 0 Overflow Flag.
Set to 1 by hardware when Timer 0 overflows. This flag can be cleared by software
but is automatically cleared when the CPU vectors to the Timer 0 interrupt service
routine.
4
3
TR0
IE1
Timer 0 Run Control.
Timer 0 is enabled by setting this bit to 1.
External Interrupt 1.
This flag is set by hardware when an edge/level of type defined by IT1 is detected. It
can be cleared by software but is automatically cleared when the CPU vectors to the
External Interrupt 1 service routine in edge-triggered mode.
2
IT1
Interrupt 1 Type Select.
This bit selects whether the configured INT1 interrupt will be edge or level sensitive.
INT1 is configured active low or high by the IN1PL bit in the IT01CF register (see
SFR Definition 17.7).
0: INT1 is level triggered.
1: INT1 is edge triggered.
1
0
IE0
IT0
External Interrupt 0.
This flag is set by hardware when an edge/level of type defined by IT1 is detected. It
can be cleared by software but is automatically cleared when the CPU vectors to the
External Interrupt 0 service routine in edge-triggered mode.
Interrupt 0 Type Select.
This bit selects whether the configured INT0 interrupt will be edge or level sensitive.
INT0 is configured active low or high by the IN0PL bit in register IT01CF (see SFR
Definition 17.7).
0: INT0 is level triggered.
1: INT0 is edge triggered.
Rev. 1.2
252
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 28.3. TMOD: Timer Mode
Bit
7
6
5
4
3
2
1
0
GATE1
C/T1
T1M[1:0]
R/W
GATE0
C/T0
T0M[1:0]
R/W
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
0
0
0
0
SFR Address = 0x89
Bit
Name
Function
7
GATE1
Timer 1 Gate Control.
0: Timer 1 enabled when TR1 = 1 irrespective of INT1 logic level.
1: Timer 1 enabled only when TR1 = 1 AND INT1 is active as defined by bit IN1PL in
register IT01CF (see SFR Definition 17.7).
6
C/T1
Counter/Timer 1 Select.
0: Timer: Timer 1 incremented by clock defined by T1M bit in register CKCON.
1: Counter: Timer 1 incremented by high-to-low transitions on external pin (T1).
5:4
T1M[1:0] Timer 1 Mode Select.
These bits select the Timer 1 operation mode.
00: Mode 0, 13-bit Counter/Timer
01: Mode 1, 16-bit Counter/Timer
10: Mode 2, 8-bit Counter/Timer with Auto-Reload
11: Mode 3, Timer 1 Inactive
3
GATE0
C/T0
Timer 0 Gate Control.
0: Timer 0 enabled when TR0 = 1 irrespective of INT0 logic level.
1: Timer 0 enabled only when TR0 = 1 AND INT0 is active as defined by bit IN0PL in
register IT01CF (see SFR Definition 17.7).
2
Counter/Timer 0 Select.
0: Timer: Timer 0 incremented by clock defined by T0M bit in register CKCON.
1: Counter: Timer 0 incremented by high-to-low transitions on external pin (T0).
1:0
T0M[1:0] Timer 0 Mode Select.
These bits select the Timer 0 operation mode.
00: Mode 0, 13-bit Counter/Timer
01: Mode 1, 16-bit Counter/Timer
10: Mode 2, 8-bit Counter/Timer with Auto-Reload
11: Mode 3, Two 8-bit Counter/Timers
253
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 28.4. TL0: Timer 0 Low Byte
Bit
7
6
5
4
3
2
1
0
TL0[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Address = 0x8A
Bit
Name
Function
7:0
TL0[7:0]
Timer 0 Low Byte.
The TL0 register is the low byte of the 16-bit Timer 0.
SFR Definition 28.5. TL1: Timer 1 Low Byte
Bit
7
6
5
4
3
2
1
0
TL1[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Address = 0x8B
Bit
Name
Function
7:0
TL1[7:0]
Timer 1 Low Byte.
The TL1 register is the low byte of the 16-bit Timer 1.
Rev. 1.2
254
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 28.6. TH0: Timer 0 High Byte
Bit
7
6
5
4
3
2
1
0
TH0[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Address = 0x8C
Bit
Name
Function
7:0
TH0[7:0]
Timer 0 High Byte.
The TH0 register is the high byte of the 16-bit Timer 0.
SFR Definition 28.7. TH1: Timer 1 High Byte
Bit
7
6
5
4
3
2
1
0
TH1[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Address = 0x8D
Bit
Name
Function
7:0
TH1[7:0]
Timer 1 High Byte.
The TH1 register is the high byte of the 16-bit Timer 1.
255
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
28.2. Timer 2
Timer 2 is a 16-bit timer formed by two 8-bit SFRs: TMR2L (low byte) and TMR2H (high byte). Timer 2 may
operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T2SPLIT bit (TMR2CN.3) defines
the Timer 2 operation mode.
Timer 2 may be clocked by the system clock, the system clock divided by 12, or the external oscillator
source divided by 8. The external clock mode is ideal for real-time clock (RTC) functionality, where the
internal oscillator drives the system clock while Timer 2 (and/or the PCA) is clocked by an external preci-
sion oscillator. Note that the external oscillator source divided by 8 is synchronized with the system clock.
28.2.1. 16-bit Timer with Auto-Reload
When T2SPLIT (TMR2CN.3) is zero, Timer 2 operates as a 16-bit timer with auto-reload. Timer 2 can be
clocked by SYSCLK, SYSCLK divided by 12, or the external oscillator clock source divided by 8. As the
16-bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in the Timer 2
reload registers (TMR2RLH and TMR2RLL) is loaded into the Timer 2 register as shown in Figure 28.4,
and the Timer 2 High Byte Overflow Flag (TMR2CN.7) is set. If Timer 2 interrupts are enabled (if IE.5 is
set), an interrupt will be generated on each Timer 2 overflow. Additionally, if Timer 2 interrupts are enabled
and the TF2LEN bit is set (TMR2CN.5), an interrupt will be generated each time the lower 8 bits (TMR2L)
overflow from 0xFF to 0x00.
CKCON
T T T T T T S S
3 3 2 2 1 0 C C
T2XCLK
M M M M M M A A
H L H L
1 0
To ADC,
SMBus
To SMBus
TMR2H
SYSCLK / 12
0
1
TL2
Overflow
0
1
TCLK
TR2
TF2H
TMR2L
Interrupt
External Clock / 8
SYSCLK
TF2L
TF2LEN
TF2CEN
T2SPLIT
TR2
T2XCLK
TMR2RLL TMR2RLH
Reload
Figure 28.4. Timer 2 16-Bit Mode Block Diagram
Rev. 1.2
256
C8051T620/1/6/7 & C8051T320/1/2/3
28.2.2. 8-bit Timers with Auto-Reload
When T2SPLIT is set, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers oper-
ate in auto-reload mode as shown in Figure 28.5. TMR2RLL holds the reload value for TMR2L; TMR2RLH
holds the reload value for TMR2H. The TR2 bit in TMR2CN handles the run control for TMR2H. TMR2L is
always running when configured for 8-bit Mode.
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, or the external oscillator clock
source divided by 8. The Timer 2 Clock Select bits (T2MH and T2ML in CKCON) select either SYSCLK or
the clock defined by the Timer 2 External Clock Select bit (T2XCLK in TMR2CN), as follows:
T2MH
T2XCLK TMR2H Clock Source
T2ML
T2XCLK TMR2L Clock Source
0
0
1
0
1
SYSCLK / 12
External Clock / 8
SYSCLK
0
0
1
0
1
SYSCLK / 12
External Clock / 8
SYSCLK
X
X
The TF2H bit is set when TMR2H overflows from 0xFF to 0x00; the TF2L bit is set when TMR2L overflows
from 0xFF to 0x00. When Timer 2 interrupts are enabled (IE.5), an interrupt is generated each time
TMR2H overflows. If Timer 2 interrupts are enabled and TF2LEN (TMR2CN.5) is set, an interrupt is gener-
ated each time either TMR2L or TMR2H overflows. When TF2LEN is enabled, software must check the
TF2H and TF2L flags to determine the source of the Timer 2 interrupt. The TF2H and TF2L interrupt flags
are not cleared by hardware and must be manually cleared by software.
CKCON
T T T T T T S S
3 3 2 2 1 0 C C
T2XCLK
M M M M M M A A
Reload
TMR2RLH
To SMBus
H L H L
1 0
SYSCLK / 12
0
1
0
External Clock / 8
TCLK
TF2H
TF2L
TMR2H
Interrupt
TR2
1
TF2LEN
TF2CEN
T2SPLIT
TR2
Reload
TMR2RLL
T2XCLK
SYSCLK
1
0
To ADC,
SMBus
TCLK
TMR2L
Figure 28.5. Timer 2 8-Bit Mode Block Diagram
257
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
28.2.3. Low-Frequency Oscillator (LFO) Capture Mode
The Low-Frequency Oscillator Capture Mode allows the LFO clock to be measured against the system
clock or an external oscillator source. Timer 2 can be clocked from the system clock, the system clock
divided by 12, or the external oscillator divided by 8, depending on the T2ML (CKCON.4), and T2XCLK
settings.
Setting TF2CEN to 1 enables the LFO Capture Mode for Timer 2. In this mode, T2SPLIT should be set to
0, as the full 16-bit timer is used. Upon a falling edge of the low-frequency oscillator, the contents of Timer
2 (TMR2H:TMR2L) are loaded into the Timer 2 reload registers (TMR2RLH:TMR2RLL) and the TF2H flag
is set. By recording the difference between two successive timer capture values, the LFO clock frequency
can be determined with respect to the Timer 2 clock. The Timer 2 clock should be much faster than the
LFO to achieve an accurate reading.
CKCON
T T T T T T S S
3 3 2 2 1 0 C C
T2XCLK
MM M MM M A A
H L H L
1 0
SYSCLK / 12
0
1
0
1
TCLK
TR2
TMR2L
TMR2H
External Clock / 8
SYSCLK
Capture
TF2CEN
Low-Frequency
Oscillator
TF2H
TF2L
TF2LEN
TF2CEN
T2SPLIT
TR2
Interrupt
TMR2RLL TMR2RLH
T2XCLK
Figure 28.6. Timer 2 Low-Frequency Oscillation Capture Mode Block Diagram
Rev. 1.2
258
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 28.8. TMR2CN: Timer 2 Control
Bit
7
TF2H
R/W
0
6
TF2L
R/W
0
5
TF2LEN
R/W
0
4
3
2
1
0
T2XCLK
R/W
0
Name
Type
Reset
TF2CEN T2SPLIT
TR2
R/W
0
R/W
0
R/W
0
R
0
SFR Address = 0xC8; Bit-Addressable
Bit
Name
Function
7
TF2H
Timer 2 High Byte Overflow Flag.
Set by hardware when the Timer 2 high byte overflows from 0xFF to 0x00. In 16 bit
mode, this will occur when Timer 2 overflows from 0xFFFF to 0x0000. When the
Timer 2 interrupt is enabled, setting this bit causes the CPU to vector to the Timer 2
interrupt service routine. This bit is not automatically cleared by hardware.
6
TF2L
Timer 2 Low Byte Overflow Flag.
Set by hardware when the Timer 2 low byte overflows from 0xFF to 0x00. TF2L will
be set when the low byte overflows regardless of the Timer 2 mode. This bit is not
automatically cleared by hardware.
5
4
TF2LEN
TF2CEN
Timer 2 Low Byte Interrupt Enable.
When set to 1, this bit enables Timer 2 Low Byte interrupts. If Timer 2 interrupts are
also enabled, an interrupt will be generated when the low byte of Timer 2 overflows.
Timer 2 Low-Frequency Oscillator Capture Enable.
When set to 1, this bit enables Timer 2 Low-Frequency Oscillator Capture Mode. If
TF2CEN is set and Timer 2 interrupts are enabled, an interrupt will be generated on
a falling edge of the low-frequency oscillator output, and the current 16-bit timer
value in TMR2H:TMR2L will be copied to TMR2RLH:TMR2RLL.
3
2
T2SPLIT
TR2
Timer 2 Split Mode Enable.
When this bit is set, Timer 2 operates as two 8-bit timers with auto-reload.
0: Timer 2 operates in 16-bit auto-reload mode.
1: Timer 2 operates as two 8-bit auto-reload timers.
Timer 2 Run Control.
Timer 2 is enabled by setting this bit to 1. In 8-bit mode, this bit enables/disables
TMR2H only; TMR2L is always enabled in split mode.
1
0
Unused
T2XCLK
Read = 0b; Write = Don’t Care
Timer 2 External Clock Select.
This bit selects the external clock source for Timer 2. If Timer 2 is in 8-bit mode, this
bit selects the external oscillator clock source for both timer bytes. However, the
Timer 2 Clock Select bits (T2MH and T2ML in register CKCON) may still be used to
select between the external clock and the system clock for either timer.
0: Timer 2 clock is the system clock divided by 12.
1: Timer 2 clock is the external clock divided by 8 (synchronized with SYSCLK).
259
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 28.9. TMR2RLL: Timer 2 Reload Register Low Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
TMR2RLL[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Address = 0xCA
Bit Name
Function
7:0 TMR2RLL[7:0] Timer 2 Reload Register Low Byte.
TMR2RLL holds the low byte of the reload value for Timer 2.
SFR Definition 28.10. TMR2RLH: Timer 2 Reload Register High Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
TMR2RLH[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Address = 0xCB
Bit Name
Function
7:0 TMR2RLH[7:0] Timer 2 Reload Register High Byte.
TMR2RLH holds the high byte of the reload value for Timer 2.
SFR Definition 28.11. TMR2L: Timer 2 Low Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
TMR2L[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Address = 0xCC
Bit Name
7:0 TMR2L[7:0] Timer 2 Low Byte.
Function
In 16-bit mode, the TMR2L register contains the low byte of the 16-bit Timer 2. In 8-
bit mode, TMR2L contains the 8-bit low byte timer value.
Rev. 1.2
260
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 28.12. TMR2H Timer 2 High Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
TMR2H[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Address = 0xCD
Bit Name
7:0 TMR2H[7:0] Timer 2 Low Byte.
Function
In 16-bit mode, the TMR2H register contains the high byte of the 16-bit Timer 2. In 8-
bit mode, TMR2H contains the 8-bit high byte timer value.
261
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
28.3. Timer 3
Timer 3 is a 16-bit timer formed by two 8-bit SFRs: TMR3L (low byte) and TMR3H (high byte). Timer 3 may
operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T3SPLIT bit (TMR3CN.3) defines
the Timer 3 operation mode.
Timer 3 may be clocked by the system clock, the system clock divided by 12, the external oscillator source
divided by 8, or the internal low-frequency oscillator divided by 8. The external clock mode is ideal for real-
time clock (RTC) functionality, where the internal high-frequency oscillator drives the system clock while
Timer 3 is clocked by an external oscillator source. Note that the external oscillator source divided by 8 and
the LFO source divided by 8 are synchronized with the system clock when in all operating modes except
suspend. When the internal oscillator is placed in suspend mode, The external clock/8 signal or the LFO/8
output can directly drive the timer. This allows the use of an external clock or the LFO to wake up the
device from suspend mode. The timer will continue to run in suspend mode and count up. When the timer
overflow occurs, the device will wake from suspend mode, and begin executing code again. The timer
value may be set prior to entering suspend, to overflow in the desired amount of time (number of clocks) to
wake the device. If a wake-up source other than the timer wakes the device from suspend mode, it may
take up to three timer clocks before the timer registers can be read or written. During this time, the
STSYNC bit in register OSCICN will be set to 1, to indicate that it is not safe to read or write the timer reg-
isters.
Important Note: In internal LFO/8 mode, the divider for the internal LFO must be set to 1 for proper func-
tionality. The timer will not operate if the LFO divider is not set to 1.
28.3.1. 16-bit Timer with Auto-Reload
When T3SPLIT (TMR3CN.3) is zero, Timer 3 operates as a 16-bit timer with auto-reload. Timer 3 can be
clocked by SYSCLK, SYSCLK divided by 12, or the external oscillator clock source divided by 8. As the
16-bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in the Timer 3
reload registers (TMR3RLH and TMR3RLL) is loaded into the Timer 3 register as shown in Figure 28.7,
and the Timer 3 High Byte Overflow Flag (TMR3CN.7) is set. If Timer 3 interrupts are enabled (if EIE1.7 is
set), an interrupt will be generated on each Timer 3 overflow. Additionally, if Timer 3 interrupts are enabled
and the TF3LEN bit is set (TMR3CN.5), an interrupt will be generated each time the lower 8 bits (TMR3L)
overflow from 0xFF to 0x00.
CKCON
T T T T T T S S
3 3 2 2 1 0 C C
T3XCLK[1:0]
M M M M M M A A
H L H L
1 0
SYSCLK / 12
External Clock / 8
Internal LFO / 8
00
To ADC
0
01
11
TCLK
TR3
TF3H
TF3L
TMR3L
TMR3H
Interrupt
TF3LEN
TF3CEN
T3SPLIT
TR3
1
T3XCLK1
T3XCLK0
SYSCLK
TMR3RLL TMR3RLH
Reload
Figure 28.7. Timer 3 16-Bit Mode Block Diagram
Rev. 1.2
262
C8051T620/1/6/7 & C8051T320/1/2/3
28.3.2. 8-bit Timers with Auto-Reload
When T3SPLIT is set, Timer 3 operates as two 8-bit timers (TMR3H and TMR3L). Both 8-bit timers oper-
ate in auto-reload mode as shown in Figure 28.8. TMR3RLL holds the reload value for TMR3L; TMR3RLH
holds the reload value for TMR3H. The TR3 bit in TMR3CN handles the run control for TMR3H. TMR3L is
always running when configured for 8-bit Mode.
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, the external oscillator clock
source divided by 8, or the internal Low-frequency Oscillator. The Timer 3 Clock Select bits (T3MH and
T3ML in CKCON) select either SYSCLK or the clock defined by the Timer 3 External Clock Select bits
(T3XCLK[1:0] in TMR3CN), as follows:
T3MH
T3XCLK[1:0] TMR3H Clock
Source
T3ML
T3XCLK[1:0] TMR3L Clock
Source
0
0
0
0
1
00
01
10
11
X
SYSCLK / 12
External Clock / 8
Reserved
0
0
0
0
1
00
01
10
11
X
SYSCLK / 12
External Clock / 8
Reserved
Internal LFO
SYSCLK
Internal LFO
SYSCLK
The TF3H bit is set when TMR3H overflows from 0xFF to 0x00; the TF3L bit is set when TMR3L overflows
from 0xFF to 0x00. When Timer 3 interrupts are enabled, an interrupt is generated each time TMR3H over-
flows. If Timer 3 interrupts are enabled and TF3LEN (TMR3CN.5) is set, an interrupt is generated each
time either TMR3L or TMR3H overflows. When TF3LEN is enabled, software must check the TF3H and
TF3L flags to determine the source of the Timer 3 interrupt. The TF3H and TF3L interrupt flags are not
cleared by hardware and must be manually cleared by software.
CKCON
T T T T T T S S
3 3 2 2 1 0 C C
T3XCLK[1:0]
M MM M MM A A
Reload
TMR3RLH
H L H L
1 0
SYSCLK / 12
External Clock / 8
Internal LFO / 8
00
0
1
01
11
TCLK
TF3H
TF3L
TF3LEN
TF3CEN
T3SPLIT
TR3
TMR3H
Interrupt
TR3
Reload
T3XCLK1
T3XCLK0
TMR3RLL
SYSCLK
1
0
TCLK
TMR3L
To ADC
Figure 28.8. Timer 3 8-Bit Mode Block Diagram
263
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
28.3.3. Low-Frequency Oscillator (LFO) Capture Mode
The Low-Frequency Oscillator Capture Mode allows the LFO clock to be measured against the system
clock or an external oscillator source. Timer 3 can be clocked from the system clock, the system clock
divided by 12, or the external oscillator divided by 8, depending on the T3ML (CKCON.6), and
T3XCLK[1:0] settings.
Setting TF3CEN to 1 enables the LFO Capture Mode for Timer 3. In this mode, T3SPLIT should be set to
0, as the full 16-bit timer is used. Upon a falling edge of the low-frequency oscillator, the contents of
Timer 3 (TMR3H:TMR3L) are loaded into the Timer 3 reload registers (TMR3RLH:TMR3RLL) and the
TF3H flag is set. By recording the difference between two successive timer capture values, the LFO clock
frequency can be determined with respect to the Timer 3 clock. The Timer 3 clock should be much faster
than the LFO to achieve an accurate reading. This means that the LFO/8 should not be selected as the
timer clock source in this mode.
CKCON
T T T T T T S S
3 3 2 2 1 0 C C
M MM M MM A A
T3XCLK[1:0]
H L H L
1 0
SYSCLK / 12
00
01
0
1
TCLK
TR3
TMR3L
TMR3H
External Clock / 8
SYSCLK
Capture
TF3CEN
Low-Frequency
Oscillator
TF3H
TF3L
TF3LEN
TF3CEN
T3SPLIT
TR3
Interrupt
TMR3RLL TMR3RLH
T3XCLK1
T3XCLK0
Figure 28.9. Timer 3 Low-Frequency Oscillation Capture Mode Block Diagram
Rev. 1.2
264
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 28.13. TMR3CN: Timer 3 Control
Bit
7
TF3H
R/W
0
6
TF3L
R/W
0
5
TF3LEN
R/W
0
4
3
2
1
0
Name
Type
Reset
TF3CEN T3SPLIT
TR3
R/W
0
T3XCLK[1:0]
R/W
R/W
0
R/W
0
0
0
SFR Address = 0x91
Bit
Name
Function
7
TF3H
Timer 3 High Byte Overflow Flag.
Set by hardware when the Timer 3 high byte overflows from 0xFF to 0x00. In 16 bit
mode, this will occur when Timer 3 overflows from 0xFFFF to 0x0000. When the
Timer 3 interrupt is enabled, setting this bit causes the CPU to vector to the Timer 3
interrupt service routine. This bit is not automatically cleared by hardware.
6
TF3L
Timer 3 Low Byte Overflow Flag.
Set by hardware when the Timer 3 low byte overflows from 0xFF to 0x00. TF3L will
be set when the low byte overflows regardless of the Timer 3 mode. This bit is not
automatically cleared by hardware.
5
4
TF3LEN
TF3CEN
Timer 3 Low Byte Interrupt Enable.
When set to 1, this bit enables Timer 3 Low Byte interrupts. If Timer 3 interrupts are
also enabled, an interrupt will be generated when the low byte of Timer 3 overflows.
Timer 3 Low-Frequency Oscillator Capture Enable.
When set to 1, this bit enables Timer 3 Low-Frequency Oscillator Capture Mode. If
TF3CEN is set and Timer 3 interrupts are enabled, an interrupt will be generated on
a falling edge of the low-frequency oscillator output, and the current 16-bit timer
value in TMR3H:TMR3L will be copied to TMR3RLH:TMR3RLL.
3
2
T3SPLIT
TR3
Timer 3 Split Mode Enable.
When this bit is set, Timer 3 operates as two 8-bit timers with auto-reload.
0: Timer 3 operates in 16-bit auto-reload mode.
1: Timer 3 operates as two 8-bit auto-reload timers.
Timer 3 Run Control.
Timer 3 is enabled by setting this bit to 1. In 8-bit mode, this bit enables/disables
TMR3H only; TMR3L is always enabled in split mode.
1:0 T3XCLK[1:0] Timer 3 External Clock Select.
This bit selects the “external” clock source for Timer 3. If Timer 3 is in 8-bit mode,
this bit selects the external oscillator clock source for both timer bytes. However, the
Timer 3 Clock Select bits (T3MH and T3ML in register CKCON) may still be used to
select between the external clock and the system clock for either timer.
00: System clock divided by 12.
01: External clock divided by 8 (synchronized with SYSCLK when not in suspend).
10: Reserved.
11: Internal LFO/8 (synchronized with SYSCLK when not in suspend).
265
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 28.14. TMR3RLL: Timer 3 Reload Register Low Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
TMR3RLL[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Address = 0x92
Bit Name
Function
7:0 TMR3RLL[7:0] Timer 3 Reload Register Low Byte.
TMR3RLL holds the low byte of the reload value for Timer 3.
SFR Definition 28.15. TMR3RLH: Timer 3 Reload Register High Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
TMR3RLH[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Address = 0x93
Bit Name
Function
7:0 TMR3RLH[7:0] Timer 3 Reload Register High Byte.
TMR3RLH holds the high byte of the reload value for Timer 3.
SFR Definition 28.16. TMR3L: Timer 3 Low Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
TMR3L[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Address = 0x94
Bit
Name
Function
7:0
TMR3L[7:0] Timer 3 Low Byte.
In 16-bit mode, the TMR3L register contains the low byte of the 16-bit Timer 3. In
8-bit mode, TMR3L contains the 8-bit low byte timer value.
Rev. 1.2
266
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 28.17. TMR3H Timer 3 High Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
TMR3H[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Address = 0x95
Bit
Name
Function
7:0
TMR3H[7:0] Timer 3 High Byte.
In 16-bit mode, the TMR3H register contains the high byte of the 16-bit Timer 3. In
8-bit mode, TMR3H contains the 8-bit high byte timer value.
267
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
29. Programmable Counter Array
The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU
intervention than the standard 8051 counter/timers. The PCA consists of a dedicated 16-bit counter/timer
and five 16-bit capture/compare modules. Each capture/compare module has its own associated I/O line
(CEXn) which is routed through the Crossbar to Port I/O when enabled. The counter/timer is driven by a
programmable timebase that can select between six sources: system clock, system clock divided by four,
system clock divided by twelve, the external oscillator clock source divided by 8, Timer 0 overflows, or an
external clock signal on the ECI input pin. Each capture/compare module may be configured to operate
independently in one of six modes: Edge-Triggered Capture, Software Timer, High-Speed Output, Fre-
quency Output,
8 to 11-Bit PWM, or 16-Bit PWM (each mode is described in Section
“29.3. Capture/Compare Modules” on page 271). The external oscillator clock option is ideal for real-time
clock (RTC) functionality, allowing the PCA to be clocked by a precision external oscillator while the inter-
nal oscillator drives the system clock. The PCA is configured and controlled through the system controller's
Special Function Registers. The PCA block diagram is shown in Figure 29.1.
Important Note: The PCA Module 4 may be used as a watchdog timer (WDT), and is enabled in this mode
following a system reset. Access to certain PCA registers is restricted while WDT mode is enabled.
See Section 29.4 for details.
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
PCA
16-Bit Counter/Timer
CLOCK
MUX
ECI
SYSCLK
External Clock/8
Capture/Compare
Module 0
Capture/Compare
Module 1
Capture/Compare
Module 2
Capture/Compare
Module 3
Capture/Compare
Module 4 / WDT
Digital Crossbar
Port I/O
Figure 29.1. PCA Block Diagram
Rev. 1.2
268
C8051T620/1/6/7 & C8051T320/1/2/3
29.1. PCA Counter/Timer
The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte
(MSB) of the 16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches
the value of PCA0H into a “snapshot” register; the following PCA0H read accesses this “snapshot” register.
Reading the PCA0L Register first guarantees an accurate reading of the entire 16-bit PCA0 counter.
Reading PCA0H or PCA0L does not disturb the counter operation. The CPS2–CPS0 bits in the PCA0MD
register select the timebase for the counter/timer as shown in Table 29.1.
When the counter/timer overflows from 0xFFFF to 0x0000, the Counter Overflow Flag (CF) in PCA0MD is
set to logic 1 and an interrupt request is generated if CF interrupts are enabled. Setting the ECF bit in
PCA0MD to logic 1 enables the CF flag to generate an interrupt request. The CF bit is not automatically
cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by soft-
ware. Clearing the CIDL bit in the PCA0MD register allows the PCA to continue normal operation while the
CPU is in Idle mode.
Table 29.1. PCA Timebase Input Options
CPS2
CPS1
CPS0
Timebase
0
0
0
0
0
0
1
1
0
1
0
1
System clock divided by 12
System clock divided by 4
Timer 0 overflow
High-to-low transitions on ECI (max rate = system clock divided
by 4)
1
1
1
0
0
1
0
1
x
System clock
*
External oscillator source divided by 8
Reserved.
Note: External oscillator source divided by 8 is synchronized with the system clock.
269
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
IDLE
PCA0MD
PCA0CN
C W W C C C E
I D D P P P C
D T L S S S F
L E C 2 1 0
K
C C C C C C C
F R C C C C C
F F F F F
4 3 2 1 0
To SFR Bus
PCA0L
read
Snapshot
Register
SYSCLK/12
SYSCLK/4
000
001
Timer 0 Overflow
ECI
010
011
100
101
0
Overflow
To PCA Interrupt System
PCA0H
PCA0L
1
SYSCLK
CF
External Clock/8
To PCA Modules
Figure 29.2. PCA Counter/Timer Block Diagram
29.2. PCA0 Interrupt Sources
Figure 29.3 shows a diagram of the PCA interrupt tree. There are five independent event flags that can be
used to generate a PCA0 interrupt. They are: the main PCA counter overflow flag (CF), which is set upon
a 16-bit overflow of the PCA0 counter, an intermediate overflow flag (COVF), which can be set on an over-
flow from the 8th, 9th, 10th, or 11th bit of the PCA0 counter, and the individual flags for each PCA channel
(CCF0, CCF1, CCF2, CCF3, and CCF4), which are set according to the operation mode of that module.
These event flags are always set when the trigger condition occurs. Each of these flags can be individually
selected to generate a PCA0 interrupt, using the corresponding interrupt enable flag (ECF for CF, ECOV
for COVF, and ECCFn for each CCFn). PCA0 interrupts must be globally enabled before any individual
interrupt sources are recognized by the processor. PCA0 interrupts are globally enabled by setting the EA
bit and the EPCA0 bit to logic 1.
Rev. 1.2
270
C8051T620/1/6/7 & C8051T320/1/2/3
(for n = 0 to 4)
PCA0CPMn
PCA0CN
PCA0MD
PCA0PWM
P E C C M T P E
W C A A A O W C
M O P P T G M C
1 M P N n n n F
C C C C C C C
F R C C C C C
F F F F F
C WW C C C E
I D D P P P C
D T L S S S F
L E C 2 1 0
K
A E C
C C
L L
S S
E E
L L
1 0
R C O
S O V
E V F
L
4 3 2 1 0
6 n n n
n
n
PCA Counter/Timer 8, 9,
10 or 11-bit Overflow
Set 8, 9, 10, or 11 bit Operation
0
1
PCA Counter/Timer 16-
bit Overflow
0
1
ECCF0
EPCA0
EA
0
1
PCA Module 0
(CCF0)
Interrupt
Priority
Decoder
0
1
0
1
ECCF1
ECCF2
ECCF3
ECCF4
0
1
PCA Module 1
(CCF1)
0
1
PCA Module 2
(CCF2)
0
1
PCA Module 3
(CCF3)
0
1
PCA Module 4
(CCF4)
Figure 29.3. PCA Interrupt Block Diagram
29.3. Capture/Compare Modules
Each module can be configured to operate independently in one of six operation modes: Edge-triggered
Capture, Software Timer, High Speed Output, Frequency Output, 8 to 11-Bit Pulse Width Modulator, or 16-
Bit Pulse Width Modulator. Each module has Special Function Registers (SFRs) associated with it in the
CIP-51 system controller. These registers are used to exchange data with a module and configure the
module's mode of operation. Table 29.2 summarizes the bit settings in the PCA0CPMn and PCA0PWM
registers used to select the PCA capture/compare module’s operating mode. Note that all modules set to
use 8, 9, 10, or 11-bit PWM mode must use the same cycle length (8-11 bits). Setting the ECCFn bit in a
PCA0CPMn register enables the module's CCFn interrupt.
271
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
Table 29.2. PCA0CPM and PCA0PWM Bit Settings for PCA Capture/Compare Modules
Operational Mode
PCA0CPMn
PCA0PWM
Bit Number
7 6 5 4 3 2 1 0 7 6 5 4-2
1-0
Capture triggered by positive edge on CEXn
Capture triggered by negative edge on CEXn
Capture triggered by any transition on CEXn
Software Timer
X X 1 0 0 0 0 A 0 X B XXX XX
X X 0 1 0 0 0 A 0 X B XXX XX
X X 1 1 0 0 0 A 0 X B XXX XX
X C 0 0 1 0 0 A 0 X B XXX XX
X C 0 0 1 1 0 A 0 X B XXX XX
X C 0 0 0 1 1 A 0 X B XXX XX
0 C 0 0 E 0 1 A 0 X B XXX 00
0 C 0 0 E 0 1 A D X B XXX 01
0 C 0 0 E 0 1 A D X B XXX 10
0 C 0 0 E 0 1 A D X B XXX 11
1 C 0 0 E 0 1 A 0 X B XXX XX
High Speed Output
Frequency Output
8-Bit Pulse Width Modulator (Note 7)
9-Bit Pulse Width Modulator (Note 7)
10-Bit Pulse Width Modulator (Note 7)
11-Bit Pulse Width Modulator (Note 7)
16-Bit Pulse Width Modulator
1. X = Don’t Care (no functional difference for individual module if 1 or 0).
2. A = Enable interrupts for this module (PCA interrupt triggered on CCFn set to 1).
3. B = Enable 8th, 9th, 10th or 11th bit overflow interrupt (Depends on setting of CLSEL[1:0]).
4. C = When set to 0, the digital comparator is off. For high speed and frequency output modes, the
associated pin will not toggle. In any of the PWM modes, this generates a 0% duty cycle (output = 0).
5. D = Selects whether the Capture/Compare register (0) or the Auto-Reload register (1) for the associated
channel is accessed via addresses PCA0CPHn and PCA0CPLn.
6. E = When set, a match event will cause the CCFn flag for the associated channel to be set.
7. All modules set to 8, 9, 10 or 11-bit PWM mode use the same cycle length setting.
29.3.1. Edge-triggered Capture Mode
In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA
counter/timer and load it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and
PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn register are used to select the type of transi-
tion that triggers the capture: low-to-high transition (positive edge), high-to-low transition (negative edge),
or either transition (positive or negative edge). When a capture occurs, the Capture/Compare Flag (CCFn)
in PCA0CN is set to logic 1. An interrupt request is generated if the CCFn interrupt for that module is
enabled. The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt ser-
vice routine, and must be cleared by software. If both CAPPn and CAPNn bits are set to logic 1, then the
state of the Port pin associated with CEXn can be read directly to determine whether a rising-edge or fall-
ing-edge caused the capture.
Rev. 1.2
272
C8051T620/1/6/7 & C8051T320/1/2/3
PCA Interrupt
PCA0CPMn
PCA0CN
P E C C M T P E
W C A A A O W C
M O P P T G M C
1 M P N n n n F
C C C C C C C
F R C C C C C
F F F F F
4 3 2 1 0
6 n n n
n
n
x
x
0 0 0 x
PCA0CPLn
PCA0CPHn
0
1
CEXn
Capture
Port I/O
Crossbar
0
1
PCA
Timebase
PCA0L
PCA0H
Figure 29.4. PCA Capture Mode Diagram
Note: The CEXn input signal must remain high or low for at least 2 system clock cycles to be recognized by the
hardware.
29.3.2. Software Timer (Compare) Mode
In Software Timer mode, the PCA counter/timer value is compared to the module's 16-bit capture/compare
register (PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in
PCA0CN is set to logic 1. An interrupt request is generated if the CCFn interrupt for that module is
enabled. The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt ser-
vice routine, and must be cleared by software. Setting the ECOMn and MATn bits in the PCA0CPMn regis-
ter enables Software Timer mode.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Cap-
ture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
273
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
Write to
0
PCA0CPLn
ENB
Reset
Write to
PCA0CPHn
ENB
PCA Interrupt
1
PCA0CPMn
P E C C M T P E
W C A A A O W C
M O P P T G M C
1 M P N n n n F
PCA0CN
C C C C C C C
F R C C C C C
F F F F F
PCA0CPLn
PCA0CPHn
6 n n n
n
4 3 2 1 0
n
x
0 0
0 0
x
0
1
Enable
Match
16-bit Comparator
PCA
Timebase
PCA0L
PCA0H
Figure 29.5. PCA Software Timer Mode Diagram
29.3.3. High-Speed Output Mode
In High-Speed Output mode, a module’s associated CEXn pin is toggled each time a match occurs
between the PCA Counter and the module's 16-bit capture/compare register (PCA0CPHn and
PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1. An
interrupt request is generated if the CCFn interrupt for that module is enabled. The CCFn bit is not auto-
matically cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared
by software. Setting the TOGn, MATn, and ECOMn bits in the PCA0CPMn register enables the High-
Speed Output mode. If ECOMn is cleared, the associated pin will retain its state, and not toggle on the next
match event.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Cap-
ture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
Rev. 1.2
274
C8051T620/1/6/7 & C8051T320/1/2/3
Write to
0
PCA0CPLn
ENB
Reset
PCA0CPMn
Write to
PCA0CPHn
P E C C M T P E
W C A A A O W C
M O P P T G M C
1 M P N n n n F
ENB
1
6 n n n
n
n
x
0 0
0 x
PCA Interrupt
PCA0CN
C C C C C C C
F R C C C C C
F F F F F
PCA0CPLn
PCA0CPHn
4 3 2 1 0
0
1
Enable
Match
16-bit Comparator
TOGn
Toggle
0
CEXn
Crossbar
Port I/O
1
PCA
Timebase
PCA0L
PCA0H
Figure 29.6. PCA High-Speed Output Mode Diagram
29.3.4. Frequency Output Mode
Frequency Output Mode produces a programmable-frequency square wave on the module’s associated
CEXn pin. The capture/compare module high byte holds the number of PCA clocks to count before the out-
put is toggled. The frequency of the square wave is then defined by Equation 29.1.
FPCA
----------------------------------------
=
FCEXn
2 × PCA0CPHn
Note: A value of 0x00 in the PCA0CPHn register is equal to 256 for this equation.
Equation 29.1. Square Wave Frequency Output
Where F
is the frequency of the clock selected by the CPS2–0 bits in the PCA mode register,
PCA
PCA0MD. The lower byte of the capture/compare module is compared to the PCA counter low byte; on a
match, CEXn is toggled and the offset held in the high byte is added to the matched value in PCA0CPLn.
Frequency Output Mode is enabled by setting the ECOMn, TOGn, and PWMn bits in the PCA0CPMn reg-
ister. Note that the MATn bit should normally be set to 0 in this mode. If the MATn bit is set to 1, the CCFn
flag for the channel will be set when the 16-bit PCA0 counter and the 16-bit capture/compare register for
the channel are equal.
275
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
Write to
0
PCA0CPLn
ENB
Reset
PCA0CPMn
P E C C M T P E
W C A A A O W C
M O P P T G M C
1 M P N n n n F
Write to
PCA0CPHn
ENB
PCA0CPLn
8-bit Adder
PCA0CPHn
1
Adder
Enable
6 n n n
n
n
TOGn
x
0 0 0
x
Toggle
0
CEXn
8-bit
Comparator
match
Enable
Crossbar
Port I/O
1
PCA Timebase
PCA0L
Figure 29.7. PCA Frequency Output Mode
29.3.5. 8-bit, 9-bit, 10-bit and 11-bit Pulse Width Modulator Modes
Each module can be used independently to generate a pulse width modulated (PWM) output on its associ-
ated CEXn pin. The frequency of the output is dependent on the timebase for the PCA counter/timer, and
the setting of the PWM cycle length (8, 9, 10 or 11-bits). For backwards-compatibility with the 8-bit PWM
mode available on other devices, the 8-bit PWM mode operates slightly different than 9, 10 and 11-bit
PWM modes. It is important to note that all channels configured for 8/9/10/11-bit PWM mode will use
the same cycle length. It is not possible to configure one channel for 8-bit PWM mode and another for 11-
bit mode (for example). However, other PCA channels can be configured to Pin Capture, High-Speed Out-
put, Software Timer, Frequency Output, or 16-bit PWM mode independently.
29.3.5.1. 8-bit Pulse Width Modulator Mode
The duty cycle of the PWM output signal in 8-bit PWM mode is varied using the module's PCA0CPLn cap-
ture/compare register. When the value in the low byte of the PCA counter/timer (PCA0L) is equal to the
value in PCA0CPLn, the output on the CEXn pin will be set. When the count value in PCA0L overflows, the
CEXn output will be reset (see Figure 29.8). Also, when the counter/timer low byte (PCA0L) overflows from
0xFF to 0x00, PCA0CPLn is reloaded automatically with the value stored in the module’s capture/compare
high byte (PCA0CPHn) without software intervention. Setting the ECOMn and PWMn bits in the
PCA0CPMn register, and setting the CLSEL bits in register PCA0PWM to 00b enables 8-Bit Pulse Width
Modulator mode. If the MATn bit is set to 1, the CCFn flag for the module will be set each time an 8-bit
comparator match (rising edge) occurs. The COVF flag in PCA0PWM can be used to detect the overflow
(falling edge), which will occur every 256 PCA clock cycles. The duty cycle for 8-Bit PWM Mode is given in
Equation 29.2.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Cap-
ture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
(256 – PCA0CPHn)
---------------------------------------------------
Duty Cycle =
256
Equation 29.2. 8-Bit PWM Duty Cycle
Using Equation 29.2, the largest duty cycle is 100% (PCA0CPHn = 0), and the smallest duty cycle is
0.39% (PCA0CPHn = 0xFF). A 0% duty cycle may be generated by clearing the ECOMn bit to 0.
Rev. 1.2
276
C8051T620/1/6/7 & C8051T320/1/2/3
Write to
0
PCA0CPLn
ENB
Reset
PCA0CPHn
Write to
PCA0CPHn
ENB
COVF
1
PCA0PWM
PCA0CPMn
A E C
C C
L L
S S
E E
L L
1 0
P E C C M T P E
W C A A A O W C
M O P P T G M C
1 M P N n n n F
R C O
S O V
E V F
L
PCA0CPLn
6 n n n
n
n
0
x
0
0
0
0 0 x 0
x
8-bit
Comparator
match
SET
CLR
CEXn
Enable
S
R
Q
Q
Crossbar
Port I/O
PCA Timebase
PCA0L
Overflow
Figure 29.8. PCA 8-Bit PWM Mode Diagram
29.3.5.2. 9/10/11-bit Pulse Width Modulator Mode
The duty cycle of the PWM output signal in 9/10/11-bit PWM mode should be varied by writing to an “Auto-
Reload” Register, which is dual-mapped into the PCA0CPHn and PCA0CPLn register locations. The data
written to define the duty cycle should be right-justified in the registers. The auto-reload registers are
accessed (read or written) when the bit ARSEL in PCA0PWM is set to 1. The capture/compare registers
are accessed when ARSEL is set to 0.
When the least-significant N bits of the PCA0 counter match the value in the associated module’s cap-
ture/compare register (PCA0CPn), the output on CEXn is asserted high. When the counter overflows from
the Nth bit, CEXn is asserted low (see Figure 29.9). Upon an overflow from the Nth bit, the COVF flag is
set, and the value stored in the module’s auto-reload register is loaded into the capture/compare register.
The value of N is determined by the CLSEL bits in register PCA0PWM.
The 9, 10 or 11-bit PWM mode is selected by setting the ECOMn and PWMn bits in the PCA0CPMn regis-
ter, and setting the CLSEL bits in register PCA0PWM to the desired cycle length (other than 8-bits). If the
MATn bit is set to 1, the CCFn flag for the module will be set each time a comparator match (rising edge)
occurs. The COVF flag in PCA0PWM can be used to detect the overflow (falling edge), which will occur
every 512 (9-bit), 1024 (10-bit) or 2048 (11-bit) PCA clock cycles. The duty cycle for 9/10/11-Bit PWM
Mode is given in Equation 29.2, where N is the number of bits in the PWM cycle.
Important Note About PCA0CPHn and PCA0CPLn Registers: When writing a 16-bit value to the
PCA0CPn registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn
bit to 0; writing to PCA0CPHn sets ECOMn to 1.
(2N – PCA0CPn)
-------------------------------------------
Duty Cycle =
2N
Equation 29.3. 9, 10, and 11-Bit PWM Duty Cycle
277
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
A 0% duty cycle may be generated by clearing the ECOMn bit to 0.
Write to
0
PCA0CPLn
R/W when
ARSEL = 1
ENB
(Auto-Reload)
PCA0CPH:Ln
(right-justified)
PCA0PWM
Reset
A E C
C C
L L
S S
E E
L L
1 0
R C O
S O V
E V F
L
Write to
PCA0CPHn
ENB
1
PCA0CPMn
x
R/W when
ARSEL = 0
P E C C M T P E
W C A A A O W C
M O P P T G M C
1 M P N n n n F
(Capture/Compare)
Set “N” bits:
01 = 9 bits
10 = 10 bits
11 = 11 bits
PCA0CPH:Ln
(right-justified)
6 n n n
n
n
0
0 0 x 0
x
match
SET
CEXn
Enable
N-bit Comparator
S
R
Q
Q
Crossbar
Port I/O
CLR
PCA Timebase
PCA0H:L
Overflow of Nth Bit
Figure 29.9. PCA 9, 10 and 11-Bit PWM Mode Diagram
29.3.6. 16-Bit Pulse Width Modulator Mode
A PCA module may also be operated in 16-Bit PWM mode. 16-bit PWM mode is independent of the other
(8/9/10/11-bit) PWM modes. In this mode, the 16-bit capture/compare module defines the number of PCA
clocks for the low time of the PWM signal. When the PCA counter matches the module contents, the out-
put on CEXn is asserted high; when the 16-bit counter overflows, CEXn is asserted low. To output a vary-
ing duty cycle, new value writes should be synchronized with PCA CCFn match interrupts. 16-Bit PWM
Mode is enabled by setting the ECOMn, PWMn, and PWM16n bits in the PCA0CPMn register. For a vary-
ing duty cycle, match interrupts should be enabled (ECCFn = 1 AND MATn = 1) to help synchronize the
capture/compare register writes. If the MATn bit is set to 1, the CCFn flag for the module will be set each
time a 16-bit comparator match (rising edge) occurs. The CF flag in PCA0CN can be used to detect the
overflow (falling edge). The duty cycle for 16-Bit PWM Mode is given by Equation 29.4.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Cap-
ture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
(65536 – PCA0CPn)
----------------------------------------------------
Duty Cycle =
65536
Equation 29.4. 16-Bit PWM Duty Cycle
Using Equation 29.4, the largest duty cycle is 100% (PCA0CPn = 0), and the smallest duty cycle is
0.0015% (PCA0CPn = 0xFFFF). A 0% duty cycle may be generated by clearing the ECOMn bit to 0.
Rev. 1.2
278
C8051T620/1/6/7 & C8051T320/1/2/3
Write to
0
PCA0CPLn
ENB
Reset
Write to
PCA0CPHn
ENB
1
PCA0CPMn
P E C C M T P E
W C A A A O W C
M O P P T G M C
1 M P N n n n F
PCA0CPHn
PCA0CPLn
6 n n n
n
n
1
0 0 x 0
x
match
SET
CLR
CEXn
Enable
16-bit Comparator
S
R
Q
Q
Crossbar
Port I/O
PCA Timebase
PCA0H
PCA0L
Overflow
Figure 29.10. PCA 16-Bit PWM Mode
29.4. Watchdog Timer Mode
A programmable watchdog timer (WDT) function is available through the PCA Module 4. The WDT is used
to generate a reset if the time between writes to the WDT update register (PCA0CPH4) exceed a specified
limit. The WDT can be configured and enabled/disabled as needed by software.
With the WDTE bit set in the PCA0MD register, Module 4 operates as a watchdog timer (WDT). The Mod-
ule 4 high byte is compared to the PCA counter high byte; the Module 4 low byte holds the offset to be
used when WDT updates are performed. The Watchdog Timer is enabled on reset. Writes to some
PCA registers are restricted while the Watchdog Timer is enabled. The WDT will generate a reset
shortly after code begins execution. To avoid this reset, the WDT should be explicitly disabled (and option-
ally re-configured and re-enabled if it is used in the system).
29.4.1. Watchdog Timer Operation
While the WDT is enabled:
PCA counter is forced on.
Writes to PCA0L and PCA0H are not allowed.
PCA clock source bits (CPS2–CPS0) are frozen.
PCA Idle control bit (CIDL) is frozen.
Module 4 is forced into software timer mode.
Writes to the Module 4 mode register (PCA0CPM4) are disabled.
While the WDT is enabled, writes to the CR bit will not change the PCA counter state; the counter will run
until the WDT is disabled. The PCA counter run control bit (CR) will read zero if the WDT is enabled but
user software has not enabled the PCA counter. If a match occurs between PCA0CPH4 and PCA0H while
the WDT is enabled, a reset will be generated. To prevent a WDT reset, the WDT may be updated with a
write of any value to PCA0CPH4. Upon a PCA0CPH4 write, PCA0H plus the offset held in PCA0CPL4 is
loaded into PCA0CPH4 (See Figure 29.11).
279
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
PCA0MD
C W W C C C E
I D D P P P C
D T L S S S F
L E C 2 1 0
K
PCA0CPH4
8-bit
Comparator
Match
Reset
Enable
PCA0L Overflow
PCA0CPL4
8-bit Adder
PCA0H
Adder
Enable
Write to
PCA0CPH4
Figure 29.11. PCA Module 2 with Watchdog Timer Enabled
Note that the 8-bit offset held in PCA0CPH4 is compared to the upper byte of the 16-bit PCA counter. This
offset value is the number of PCA0L overflows before a reset. Up to 256 PCA clocks may pass before the
first PCA0L overflow occurs, depending on the value of the PCA0L when the update is performed. The
total offset is then given (in PCA clocks) by Equation 29.5, where PCA0L is the value of the PCA0L register
at the time of the update.
Offset = (256 × PCA0CPL4) + (256 – PCA0L)
Equation 29.5. Watchdog Timer Offset in PCA Clocks
The WDT reset is generated when PCA0L overflows while there is a match between PCA0CPH4 and
PCA0H. Software may force a WDT reset by writing a 1 to the CCF4 flag (PCA0CN.4) while the WDT is
enabled.
29.4.2. Watchdog Timer Usage
To configure the WDT, perform the following tasks:
Disable the WDT by writing a 0 to the WDTE bit.
Select the desired PCA clock source (with the CPS2–CPS0 bits).
Load PCA0CPL4 with the desired WDT update offset value.
Configure the PCA Idle mode (set CIDL if the WDT should be suspended while the CPU is in Idle
mode).
Enable the WDT by setting the WDTE bit to 1.
Reset the WDT timer by writing to PCA0CPH4.
The PCA clock source and Idle mode select cannot be changed while the WDT is enabled. The watchdog
timer is enabled by setting the WDTE or WDLCK bits in the PCA0MD register. When WDLCK is set, the
WDT cannot be disabled until the next system reset. If WDLCK is not set, the WDT is disabled by clearing
the WDTE bit.
The WDT is enabled following any reset. The PCA0 counter clock defaults to the system clock divided by
12, PCA0L defaults to 0x00, and PCA0CPL4 defaults to 0x00. Using Equation 29.5, this results in a WDT
timeout interval of 256 PCA clock cycles, or 3072 system clock cycles. Table 29.3 lists some example tim-
Rev. 1.2
280
C8051T620/1/6/7 & C8051T320/1/2/3
eout intervals for typical system clocks.
Table 29.3. Watchdog Timer Timeout Intervals1
System Clock (Hz)
12,000,000
PCA0CPL4
255
128
32
Timeout Interval (ms)
65.5
33.0
12,000,000
12,000,000
8.4
24,000,000
255
128
32
32.8
24,000,000
16.5
24,000,000
4.2
2
1,500,000
255
128
32
524.3
264.2
67.6
2
1,500,000
2
1,500,000
32,768
32,768
32,768
255
128
32
24,000
12,093.75
3,093.75
Notes:
1. Assumes SYSCLK/12 as the PCA clock source, and a PCA0L value
of 0x00 at the update time.
2. Internal SYSCLK reset frequency = Internal Oscillator divided by 8.
29.5. Register Descriptions for PCA0
Following are detailed descriptions of the special function registers related to the operation of the PCA.
281
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 29.1. PCA0CN: PCA Control
Bit
7
CF
R/W
0
6
CR
R/W
0
5
4
CCF4
R/W
0
3
CCF3
R/W
0
2
CCF2
R/W
0
1
CCF1
R/W
0
0
CCF0
R/W
0
Name
Type
Reset
R
0
SFR Address = 0xD8; Bit-Addressable
Bit
Name
Function
7
CF
PCA Counter/Timer Overflow Flag.
Set by hardware when the PCA Counter/Timer overflows from 0xFFFF to 0x0000.
When the Counter/Timer Overflow (CF) interrupt is enabled, setting this bit causes the
CPU to vector to the PCA interrupt service routine. This bit is not automatically cleared
by hardware and must be cleared by software.
6
CR
PCA Counter/Timer Run Control.
This bit enables/disables the PCA Counter/Timer.
0: PCA Counter/Timer disabled.
1: PCA Counter/Timer enabled.
5
4
Unused Read = 0b, Write = Don't care.
PCA Module 4 Capture/Compare Flag.
CCF4
CCF3
CCF2
CCF1
CCF0
This bit is set by hardware when a match or capture occurs. When the CCF4 interrupt
is enabled, setting this bit causes the CPU to vector to the PCA interrupt service rou-
tine. This bit is not automatically cleared by hardware and must be cleared by software.
3
2
1
0
PCA Module 3Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF3 interrupt
is enabled, setting this bit causes the CPU to vector to the PCA interrupt service rou-
tine. This bit is not automatically cleared by hardware and must be cleared by software.
PCA Module 2 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF2 interrupt
is enabled, setting this bit causes the CPU to vector to the PCA interrupt service rou-
tine. This bit is not automatically cleared by hardware and must be cleared by software.
PCA Module 1 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF1 interrupt
is enabled, setting this bit causes the CPU to vector to the PCA interrupt service rou-
tine. This bit is not automatically cleared by hardware and must be cleared by software.
PCA Module 0 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF0 interrupt
is enabled, setting this bit causes the CPU to vector to the PCA interrupt service rou-
tine. This bit is not automatically cleared by hardware and must be cleared by software.
Rev. 1.2
282
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 29.2. PCA0MD: PCA Mode
Bit
7
CIDL
R/W
0
6
WDTE
R/W
1
5
WDLCK
R/W
0
4
3
CPS2
R/W
0
2
CPS1
R/W
0
1
CPS0
R/W
0
0
Name
Type
Reset
ECF
R/W
0
R
0
SFR Address = 0xD9
Bit
Name
Function
7
CIDL
PCA Counter/Timer Idle Control.
Specifies PCA behavior when CPU is in Idle Mode.
0: PCA continues to function normally while the system controller is in Idle Mode.
1: PCA operation is suspended while the system controller is in Idle Mode.
6
5
WDTE Watchdog Timer Enable.
If this bit is set, PCA Module 4 is used as the watchdog timer.
0: Watchdog Timer disabled.
1: PCA Module 4 enabled as Watchdog Timer.
WDLCK Watchdog Timer Lock.
This bit locks/unlocks the Watchdog Timer Enable. When WDLCK is set, the Watchdog
Timer may not be disabled until the next system reset.
0: Watchdog Timer Enable unlocked.
1: Watchdog Timer Enable locked.
4
Unused Read = 0b, Write = Don't care.
3:1 CPS[2:0] PCA Counter/Timer Pulse Select.
These bits select the timebase source for the PCA counter
000: System clock divided by 12
001: System clock divided by 4
010: Timer 0 overflow
011: High-to-low transitions on ECI (max rate = system clock divided by 4)
100: System clock
101: External clock divided by 8 (synchronized with the system clock)
11x: Reserved
0
ECF
PCA Counter/Timer Overflow Interrupt Enable.
This bit sets the masking of the PCA Counter/Timer Overflow (CF) interrupt.
0: Disable the CF interrupt.
1: Enable a PCA Counter/Timer Overflow interrupt request when CF (PCA0CN.7) is
set.
Note: When the WDTE bit is set to 1, the other bits in the PCA0MD register cannot be modified. To change the
contents of the PCA0MD register, the Watchdog Timer must first be disabled.
283
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 29.3. PCA0PWM: PCA PWM Configuration
Bit
7
ARSEL
R/W
0
6
ECOV
R/W
0
5
COVF
R/W
0
4
3
2
1
0
Name
Type
Reset
CLSEL[1:0]
R/W
R
0
R
0
R
0
0
0
SFR Address = 0xF4
Bit
Name
Function
7
ARSEL
Auto-Reload Register Select.
This bit selects whether to read and write the normal PCA capture/compare registers
(PCA0CPn), or the Auto-Reload registers at the same SFR addresses. This function
is used to define the reload value for 9, 10, and 11-bit PWM modes. In all other
modes, the Auto-Reload registers have no function.
0: Read/Write Capture/Compare Registers at PCA0CPHn and PCA0CPLn.
1: Read/Write Auto-Reload Registers at PCA0CPHn and PCA0CPLn.
6
5
ECOV
COVF
Cycle Overflow Interrupt Enable.
This bit sets the masking of the Cycle Overflow Flag (COVF) interrupt.
0: COVF will not generate PCA interrupts.
1: A PCA interrupt will be generated when COVF is set.
Cycle Overflow Flag.
This bit indicates an overflow of the 8th, 9th, 10th, or 11th bit of the main PCA counter
(PCA0). The specific bit used for this flag depends on the setting of the Cycle Length
Select bits. The bit can be set by hardware or software, but must be cleared by soft-
ware.
0: No overflow has occurred since the last time this bit was cleared.
1: An overflow has occurred since the last time this bit was cleared.
4:2
Unused
Read = 000b; Write = Don’t care.
1:0 CLSEL[1:0] Cycle Length Select.
When 16-bit PWM mode is not selected, these bits select the length of the PWM
cycle, between 8, 9, 10, or 11 bits. This affects all channels configured for PWM which
are not using 16-bit PWM mode. These bits are ignored for individual channels config-
ured to16-bit PWM mode.
00: 8 bits.
01: 9 bits.
10: 10 bits.
11: 11 bits.
Rev. 1.2
284
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 29.4. PCA0CPMn: PCA Capture/Compare Mode
Bit
7
6
ECOMn
R/W
0
5
CAPPn
R/W
0
4
CAPNn
R/W
0
3
MATn
R/W
0
2
TOGn
R/W
0
1
PWMn
R/W
0
0
ECCFn
R/W
0
Name PWM16n
Type
R/W
0
Reset
SFR Addresses: 0xDA (n = 0), 0xDB (n = 1), 0xDC (n = 2), 0xDD (n = 3), 0xDE (n = 4)
Bit
Name
Function
7
PWM16n 16-bit Pulse Width Modulation Enable.
This bit enables 16-bit mode when Pulse Width Modulation mode is enabled.
0: 8 to 11-bit PWM selected.
1: 16-bit PWM selected.
6
5
4
3
ECOMn Comparator Function Enable.
This bit enables the comparator function for PCA module n when set to 1.
CAPPn Capture Positive Function Enable.
This bit enables the positive edge capture for PCA module n when set to 1.
CAPNn Capture Negative Function Enable.
This bit enables the negative edge capture for PCA module n when set to 1.
MATn
Match Function Enable.
This bit enables the match function for PCA module n when set to 1. When enabled,
matches of the PCA counter with a module's capture/compare register cause the CCFn
bit in PCA0MD register to be set to logic 1.
2
1
0
TOGn
Toggle Function Enable.
This bit enables the toggle function for PCA module n when set to 1. When enabled,
matches of the PCA counter with a module's capture/compare register cause the logic
level on the CEXn pin to toggle. If the PWMn bit is also set to logic 1, the module oper-
ates in Frequency Output Mode.
PWMn Pulse Width Modulation Mode Enable.
This bit enables the PWM function for PCA module n when set to 1. When enabled, a
pulse width modulated signal is output on the CEXn pin. 8 to 11-bit PWM is used if
PWM16n is cleared; 16-bit mode is used if PWM16n is set to logic 1. If the TOGn bit is
also set, the module operates in Frequency Output Mode.
ECCFn Capture/Compare Flag Interrupt Enable.
This bit sets the masking of the Capture/Compare Flag (CCFn) interrupt.
0: Disable CCFn interrupts.
1: Enable a Capture/Compare Flag interrupt request when CCFn is set.
Note: When the WDTE bit is set to 1, the PCA0CPM4 register cannot be modified, and module 4 acts as the
watchdog timer. To change the contents of the PCA0CPM4 register or the function of module 4, the Watchdog
Timer must be disabled.
285
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 29.5. PCA0L: PCA Counter/Timer Low Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
PCA0[7:0]
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Address = 0xF9
Bit Name
7:0 PCA0[7:0] PCA Counter/Timer Low Byte.
Function
The PCA0L register holds the low byte (LSB) of the 16-bit PCA Counter/Timer.
Note: When the WDTE bit is set to 1, the PCA0L register cannot be modified by software. To change the contents of
the PCA0L register, the Watchdog Timer must first be disabled.
SFR Definition 29.6. PCA0H: PCA Counter/Timer High Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
PCA0[15:8]
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Address = 0xFA
Bit Name
7:0 PCA0[15:8] PCA Counter/Timer High Byte.
Function
The PCA0H register holds the high byte (MSB) of the 16-bit PCA Counter/Timer.
Reads of this register will read the contents of a “snapshot” register, whose contents
are updated only when the contents of PCA0L are read (see Section 29.1).
Note: When the WDTE bit is set to 1, the PCA0H register cannot be modified by software. To change the contents of
the PCA0H register, the Watchdog Timer must first be disabled.
Rev. 1.2
286
C8051T620/1/6/7 & C8051T320/1/2/3
SFR Definition 29.7. PCA0CPLn: PCA Capture Module Low Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
PCA0CPn[7:0]
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Addresses: 0xFB (n = 0), 0xE9 (n = 1), 0xEB (n = 2), 0xED (n = 3), 0xFD (n = 4)
Bit Name Function
7:0 PCA0CPn[7:0] PCA Capture Module Low Byte.
The PCA0CPLn register holds the low byte (LSB) of the 16-bit capture module n.
This register address also allows access to the low byte of the corresponding
PCA channel’s auto-reload value for 9, 10, or 11-bit PWM mode. The ARSEL bit
in register PCA0PWM controls which register is accessed.
Note: A write to this register will clear the module’s ECOMn bit to a 0.
SFR Definition 29.8. PCA0CPHn: PCA Capture Module High Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
PCA0CPn[15:8]
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Addresses: 0xFC (n = 0), 0xEA (n = 1), 0xEC (n = 2), 0xEE (n = 3), 0xFE (n = 4)
Bit Name Function
7:0 PCA0CPn[15:8] PCA Capture Module High Byte.
The PCA0CPHn register holds the high byte (MSB) of the 16-bit capture module n.
This register address also allows access to the high byte of the corresponding
PCA channel’s auto-reload value for 9, 10, or 11-bit PWM mode. The ARSEL bit in
register PCA0PWM controls which register is accessed.
Note: A write to this register will set the module’s ECOMn bit to a 1.
287
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
30. C2 Interface
C8051T620/1/6/7 & C8051T320/1/2/3 devices include an on-chip Silicon Labs 2-Wire (C2) debug interface
to allow EPROM programming and in-system debugging with the production part installed in the end appli-
cation. The C2 interface operates using only two pins: a bi-directional data signal (C2D), and a clock input
(C2CK). See the C2 Interface Specification for details on the C2 protocol.
30.1. C2 Interface Registers
The following describes the C2 registers necessary to perform EPROM programming functions through the
C2 interface. All C2 registers are accessed through the C2 interface as described in the C2 Interface Spec-
ification.
C2 Register Definition 30.1. C2ADD: C2 Address
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
C2ADD[7:0]
R/W
0
0
0
0
0
0
0
0
Bit
Name
Function
7:0 C2ADD[7:0] Write: C2 Address.
Selects the target Data register for C2 Data Read and Data Write commands accord-
ing to the following list.
Address Name
Description
DEVICEID Selects the Device ID Register (read only)
REVID Selects the Revision ID Register (read only)
DEVCTL Selects the C2 Device Control Register
0x00
0x01
0x02
0xDF
0xBF
0xB7
0xAF
0xAE
0xA9
0xAA
0xAB
0xAC
EPCTL
EPDAT
EPSTAT
Selects the C2 EPROM Programming Control Register
Selects the C2 EPROM Data Register
Selects the C2 EPROM Status Register
EPADDRH Selects the C2 EPROM Address High Byte Register
EPADDRL Selects the C2 EPROM Address Low Byte Register
CRC0
CRC1
CRC2
CRC3
Selects the CRC0 Register
Selects the CRC1 Register
Selects the CRC2 Register
Selects the CRC3 Register
Read: C2 Status
Returns status information on the current programming operation.
When the MSB (bit 7) is set to 1, a read or write operation is in progress. All other bits
can be ignored by the programming tools.
Rev. 1.2
288
C8051T620/1/6/7 & C8051T320/1/2/3
C2 Register Definition 30.2. DEVICEID: C2 Device ID
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
DEVICEID[7:0]
R/W
Varies
Varies
Varies
Varies
Varies
Varies
Varies
Varies
C2 Address: 0x00
Bit Name
7:0 DEVICEID[7:0] Device ID.
Function
This read-only register returns the 8-bit device ID: 0x18
(C8051T620/621/320/321/322/323). 0x2C (C8051T626/627).
C2 Register Definition 30.3. REVID: C2 Revision ID
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
REVID[7:0]
R/W
Varies
Varies
Varies
Varies
Varies
Varies
Varies
Varies
C2 Address: 0x01
Bit Name
7:0 REVID[7:0] Revision ID.
Function
This read-only register returns the 8-bit revision ID. For example: 0x00 = Revision A.
289
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
C2 Register Definition 30.4. DEVCTL: C2 Device Control
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
DEVCTL[7:0]
R/W
0
0
0
0
0
0
0
0
C2 Address: 0x02
Bit Name
7:0 DEVCTL[7:0] Device Control Register.
Function
This register is used to halt the device for EPROM operations via the C2 interface.
Refer to the EPROM chapter for more information.
C2 Register Definition 30.5. EPCTL: EPROM Programming Control Register
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
EPCTL[7:0]
R/W
0
0
0
0
0
0
0
0
C2 Address: 0xDF
Bit Name
7:0 EPCTL[7:0] EPROM Programming Control Register.
Function
This register is used to enable EPROM programming via the C2 interface. Refer to
the EPROM chapter for more information.
Rev. 1.2
290
C8051T620/1/6/7 & C8051T320/1/2/3
C2 Register Definition 30.6. EPDAT: C2 EPROM Data
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
EPDAT[7:0]
R/W
0
0
0
0
0
0
0
0
C2 Address: 0xBF
Bit Name
7:0 EPDAT[7:0] C2 EPROM Data Register.
This register is used to pass EPROM data during C2 EPROM operations.
Function
C2 Register Definition 30.7. EPSTAT: C2 EPROM Status
Bit
7
6
5
4
3
2
1
0
Name WRLOCK RDLOCK
ERROR
Type
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Reset
C2 Address: 0xB7
Bit
Name
WRLOCK Write Lock Indicator.
Set to '1' if EPADDR currently points to a write-locked address.
RDLOCK Read Lock Indicator.
Function
7
6
Set to '1' if EPADDR currently points to a read-locked address.
Read = 00000b; Write = don’t care.
Error Indicator.
5:1
0
Unused
ERROR
Set to '1' if last EPROM read or write operation failed due to a security restriction.
291
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
C2 Register Definition 30.8. EPADDRH: C2 EPROM Address High Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
EPADDR[15:8]
R/W
0
0
0
0
0
0
0
0
C2 Address: 0xAF
Bit Name
7:0 EPADDR[15:8] C2 EPROM Address High Byte.
Function
This register is used to set the EPROM address location during C2 EPROM oper-
ations.
C2 Register Definition 30.9. EPADDRL: C2 EPROM Address Low Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
EPADDR[7:0]
R/W
0
0
0
0
0
0
0
0
C2 Address: 0xAE
Bit Name
7:0 EPADDR[15:8] C2 EPROM Address Low Byte.
Function
This register is used to set the EPROM address location during C2 EPROM oper-
ations.
Rev. 1.2
292
C8051T620/1/6/7 & C8051T320/1/2/3
C2 Register Definition 30.10. CRC0: CRC Byte 0
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
CRC[7:0]
R/W
0
0
0
0
0
0
0
0
C2 Address: 0xA9
Bit
Name
Function
7:0
CRC[7:0] CRC Byte 0.
A write to this register initiates a 16-bit CRC of one 256-byte block of EPROM mem-
ory. The byte written to CRC0 is the upper byte of the 16-bit address where the CRC
will begin. The lower byte of the beginning address is always 0x00. When complete,
the 16-bit result will be available in CRC1 (MSB) and CRC0 (LSB). See Section
“18.4. Program Memory CRC” on page 115.
C2 Register Definition 30.11. CRC1: CRC Byte 1
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
CRC[15:8]
R/W
0
0
0
0
0
0
0
0
C2 Address: 0xAA
Bit Name
7:0 CRC[15:8] CRC Byte 1.
Function
A write to this register initiates a 32-bit CRC on the entire program memory space.
The CRC begins at address 0x0000. When complete, the 32-bit result is stored in
CRC3 (MSB), CRC2, CRC1, and CRC0 (LSB). See Section “18.4. Program Memory
CRC” on page 115.
293
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
C2 Register Definition 30.12. CRC2: CRC Byte 2
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
CRC[23:16]
R/W
0
0
0
0
0
0
0
0
C2 Address: 0xAB
Bit Name
7:0 CRC[23:16] CRC Byte 2.
See Section “18.4. Program Memory CRC” on page 115.
Function
C2 Register Definition 30.13. CRC3: CRC Byte 3
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
CRC[31:24]
R/W
0
0
0
0
0
0
0
0
C2 Address: 0xAC
Bit Name
7:0 CRC[31:24] CRC Byte 3.
Function
See Section “18.4. Program Memory CRC” on page 115.
Rev. 1.2
294
C8051T620/1/6/7 & C8051T320/1/2/3
30.2. C2 Pin Sharing
The C2 protocol allows the C2 pins to be shared with user functions so that in-system debugging and
EPROM programming functions may be performed. This is possible because C2 communication is typi-
cally performed when the device is in the halt state, where all on-chip peripherals and user software are
stalled. In this halted state, the C2 interface can safely ‘borrow’ the C2CK (normally RST) and C2D pins. In
most applications, external resistors are required to isolate C2 interface traffic from the user application
when performing debug functions. These external resistors are not necessary for production boards. A typ-
ical isolation configuration is shown in Figure 30.1.
RST (a)
Input (b)
C2CK
C2D
Output (c)
C2 Interface Master
Figure 30.1. Typical C2 Pin Sharing
The configuration in Figure 30.1 assumes the following:
1. The user input (b) cannot change state while the target device is halted.
2. The RST pin on the target device is used as an input only.
Additional resistors may be necessary depending on the specific application.
295
Rev. 1.2
C8051T620/1/6/7 & C8051T320/1/2/3
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 1.0
Updated “Electrical Characteristics” on page 34.
Revision 1.0 to Revision 1.1
Updated reset values for POWER, EMI0CF, VDM0CN, AMX0P, CPT0MX, and CPT1MX SFRs.
Updated Figure 21.1 on page 127.
Revision 1.1 to Revision 1.2
Added C8051T626/7 part numbers and added details about these devices throughout the document.
Updated maximum memory options on Page 1 and in Section “1. System Overview” on page 15.
Added C8051T626/7 ordering part numbers to Table 2.1 on page 21 along with a note about the new
part numbering scheme.
Added electrical specifications for the new part numbers C8051T626/7 wherever they differed from the
specifications for the rest of the part numbers.
Table 7.2, “Global Electrical Characteristics,” on page 35 - Digital Supply Current (USB Suspend Mode).
Table 7.5, “Internal Voltage Regulator Electrical Characteristics,” on page 37 - Bias Current (REG1).
Table 7.7, “Internal High-Frequency Oscillator Electrical Characteristics,” on page 38 - Internal Oscillator Supply
Current.
Table 7.8, “Internal Low-Frequency Oscillator Electrical Characteristics,” on page 39 - Internal Oscillator Supply
Current.
Table 7.10, “ADC0 Electrical Characteristics,” on page 40 - Power Supply Current.
Table 7.11, “Temperature Sensor Electrical Characteristics,” on page 41 - Slope and Offset.
Updated Section “15. Memory Organization” on page 87 and Section “23. Universal Serial Bus
Controller (USB0)” on page 160 to describe the additional memory on the new part numbers
(C8051T626/7).
Expanded PGSEL field from 3 bits to 5 bits in SFR Definition 15.1 “EMI0CN: External Memory Interface
Control” on page 91 to support additional XRAM available on C8051T626/7 devices.
Updated Table 17.1, “Interrupt Summary,” on page 103 to indicate that interrupt position #19 is
reserved.
Updated SFR Definition 17.5 “EIE2: Extended Interrupt Enable 2” on page 108 and SFR Definition 17.6
“EIP2: Extended Interrupt Priority 2” on page 109 to indicate that bit 4 is reserved and requires 0b
writes to this bit position.
Updated SFR Definition 22.3 “XBR2: Port I/O Crossbar Register 2” on page 149 to indicate that bit 1 is
reserved and requires 0b writes to this bit position.
Rev. 1.2
296
C8051T620/1/6/7 & C8051T320/1/2/3
NOTES:
297
Rev. 1.2
Simplicity Studio
One-click access to MCU and
wireless tools, documentation,
software, source code libraries &
more. Available for Windows,
Mac and Linux!
IoT Portfolio
www.silabs.com/IoT
SW/HW
www.silabs.com/simplicity
Quality
www.silabs.com/quality
Support and Community
community.silabs.com
Disclaimer
Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using
or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and
"Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories reserves the right to
make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the
included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses
granted hereunder to design or fabricate any integrated circuits. The products are not designed or authorized to be used within any Life Support System without the specific written consent
of Silicon Laboratories. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant
personal injury or death. Silicon Laboratories products are not designed or authorized for military applications. Silicon Laboratories products shall under no circumstances be used in
weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.
Trademark Information
Silicon Laboratories Inc.® , Silicon Laboratories®, Silicon Labs®, SiLabs® and the Silicon Labs logo®, Bluegiga®, Bluegiga Logo®, Clockbuilder®, CMEMS®, DSPLL®, EFM®, EFM32®,
EFR, Ember®, Energy Micro, Energy Micro logo and combinations thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZRadio®, EZRadioPRO®, Gecko®,
ISOmodem®, Precision32®, ProSLIC®, Simplicity Studio®, SiPHY®, Telegesis, the Telegesis Logo®, USBXpress® and others are trademarks or registered trademarks of Silicon Laborato-
ries Inc. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or registered trademarks of ARM Holdings. Keil is a registered trademark of ARM Limited. All other products or brand
names mentioned herein are trademarks of their respective holders.
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
USA
http://www.silabs.com
相关型号：
C8051T326-GM
Microcontroller, 8-Bit, OTPROM, 30MHz, CMOS, 5 X 5 MM, ROHS COMPLIANT, MO-220VHHD, QFN-28
SILICON
©2020 ICPDF网 联系我们和版权申明