CP2400-GDI [SILICON]
Liquid Crystal Driver;
| 型号： | CP2400-GDI |
| 厂家： | 
SILICON |
| 描述： | Liquid Crystal Driver 驱动 接口集成电路 |
| 文件： | 总16页 (文件大小：1488K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CP2400-C-GDI
Tested 128 Segment LCD Driver Die in Wafer Form
Digital Bus Interface
LCD Driver
-
-
-
-
Controls up to 128 segments
-
4-wire SPI Interface (SPI device only) operates up
to 2.5 Mbps with synchronous external clock or up
to 1 Mbps with internal clock
Supports static, 2-mux, 3-mux, and 4-mux displays
On-chip bias generation with internal charge pump
Low power blink capability
-
-
Dedicated RST and INT pins
Optional CLK pin can be used as a CMOS clock
input.
GPIO Expander
-
Expands GPIO count by up to 36 pins
-
-
2-wire SMBus/I2C interface (SMBus/I2C device
-
GPIO pins may be configured to push-pull or open-
drain outputs with two drive levels. GPIO may also
be used as digital inputs
Port Match Capability can wake up host controller
using interrupt pin
only) operates up to 400 kHz with internal clock
Optional PWR pin (SMBus/I2C device only) places
the device in a low-power mode. SPI devices use
the NSS pin to place device in a low-power mode
-
-
Low Power
5 V Tolerant I/O
-
-
-
1.8–3.6 V operation with integrated LDO
Ultra Low Power Mode w/ LCD (<3 µA typical)
Shutdown current (0.05 µA typical)
Real Time Clock, SmaRTClock
-
Precision time keeping with 32.768 kHz watch crys-
tal; self-oscillate mode requires no external crystal;
accepts external 32 kHz CMOS clock
Example Applications
-
-
-
36-hour programmable counter with wake up alarm
Can wake up the host controller using interrupt pin
Low power (<1.5 µA)
-
-
-
-
Handheld Equipment
Utility Meters
Thermostat Display
Home Security Systems
256 Bytes RAM
-
General purpose RAM expands the memory avail-
able to host controller.
Temperature Range: –40 to +85 °C
Full Technical Data Sheet
-
16-bit Timers
CP2400/1/2/3
l Two general purpose 16-bit timers
Clock Sources
-
20 MHz Internal oscillator
-
Can be clocked from an external CMOS clock
CP2400/1
Optional
20 MHz
Internal
Oscillator
32.768 kHz
smaRTClock
GPIO Expander
LCD Controller
Host
Interface
SPI
Host
(CP2400)
2 x 16-bit
Timers
Digital I/O
LCD
Controller
OR
SMBus/I2C
(CP2401)
256 Byte
SRAM
Rev. 1.1 4/12
Copyright © 2012 by Silicon Laboratories
CP2400-C-GDI
CP2400-C-GDI
1. Ordering Information
Table 1.1. Product Selection Guide
1,2
CP2400-GDI
20
256
2
36
Tested Die in
Wafer Form
Notes:
1. See “SPI Bonding Information” on page 7.
2. See “SMBus/I2C Bonding Information” on page 10.
2
Rev. 1.1
CP2400-C-GDI
2. Pin Definitions
Table 2.1 lists the pin definitions for the CP2400-C-GDI.
Table 2.1. Pin Definitions for the CP2400-C-GDI
Name
Physical Pad
Number
Type
Description
SPI
SMBus/
2
I C
XTAL1
XTAL2
2
3
2
3
4
A In
Crystal Input. This pin is the return for the external oscillator
driver. This pin can be overdriven by an external CMOS clock.
A Out
Crystal Output. This pin is the excitation driver for a quartz
crystal.
V
4
Power In 1.8–3.6 V Power Supply Voltage Input.
Ground Ground
DD
GND
5, 6, 43
5, 6,
43, 53
CAP
1
1
Power
Out
LCD Power Supply Voltage Output. This pin requires a 10 µF
decoupling capacitor.
CLK
RST
57
56
57
56
D In
D In
CMOS clock input. This pin should not be left floating.
Device Reset. An external source can initiate a system reset
by driving this pin low for at least 15 µs. This pin has an
internal weak pullup.
INT
NSS
MOSI
55
52
51
55
—
—
D Out
D In
Interrupt Service Request. This pin provides notification to the
host. This pin is a push-pull output.
Slave select signal for SPI interface. This pin should not be
left floating.
D In
Master Out/Slave In data signal for SPI interface. This pin
should not be left floating.
MISO
SCK
50
49
—
—
D Out
D In
Master In/Slave Out data signal for SPI interface
Clock signal for SPI interface. This pin should not be left
floating.
PWR
SCL
SDA
—
—
—
54
52
51
D In
D I/O
D I/O
Allows SMBus device to enter the Ultra Low Power mode.
This pin should not be left floating.
Clock signal for SMBus interface. This pin should not be left
floating.
Data signal for SMBus interface. This pin should not be left
floating.
Rev. 1.1
3
CP2400-C-GDI
Table 2.1. Pin Definitions for the CP2400-C-GDI (Continued)
Name
Physical Pad
Number
Type
Description
SPI
SMBus/
2
I C
SMBA0
—
48
47
46
45
42
41
40
39
38
37
36
35
34
33
32
50
48
47
46
45
42
41
40
39
38
37
36
35
34
33
32
D In
Bit 0, SMBus Slave Address. This pin should not be left
floating.
P0.0
LCD0
D I/O
A Out
Bit 0, Port 0
Bit 1, Port 0
Bit 2, Port 0
Bit 3, Port 0
Bit 4, Port 0
Bit 5, Port 0
Bit 6, Port 0
Bit 7, Port 0
Bit 0, Port 1
Bit 1, Port 1
Bit 2, Port 1
Bit 3, Port 1
Bit 4, Port 1
Bit 5, Port 1
Bit 6, Port 1
P0.1
LCD1
D I/O
A Out
P0.2
LCD2
D I/O
A Out
P0.3
LCD3
D I/O
A Out
P0.4
LCD4
D I/O
A Out
P0.5
LCD5
D I/O
A Out
P0.6
LCD6
D I/O
A Out
P0.7
LCD7
D I/O
A Out
P1.0
LCD8
D I/O
A Out
P1.1
LCD9
D I/O
A Out
P1.2
LCD10
D I/O
A Out
P1.3
LCD11
D I/O
A Out
P1.4
LCD12
D I/O
A Out
P1.5
LCD13
D I/O
A Out
P1.6
LCD14
D I/O
A Out
4
Rev. 1.1
CP2400-C-GDI
Table 2.1. Pin Definitions for the CP2400-C-GDI (Continued)
Name
Physical Pad
Number
Type
Description
SPI
SMBus/
2
I C
P1.7
LCD15
31
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
31
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
D I/O
A Out
Bit 7, Port 1
Bit 0, Port 2
Bit 1, Port 2
Bit 2, Port 2
Bit 3, Port 2
Bit 4, Port 2
Bit 5, Port 2
Bit 6, Port 2
Bit 7, Port 2
Bit 0, Port 3
Bit 1, Port 3
Bit 2, Port 3
Bit 3, Port 3
Bit 4, Port 3
Bit 5, Port 3
Bit 6, Port 3
P2.0
LCD16
D I/O
A Out
P2.1
LCD17
D I/O
A Out
P2.2
LCD18
D I/O
A Out
P2.3
LCD19
D I/O
A Out
P2.4
LCD20
D I/O
A Out
P2.5
LCD21
D I/O
A Out
P2.6
LCD22
D I/O
A Out
P2.7
LCD23
D I/O
A Out
P3.0
LCD24
D I/O
A Out
P3.1
LCD25
D I/O
A Out
P3.2
LCD26
D I/O
A Out
P3.3
LCD27
D I/O
A Out
P3.4
LCD28
D I/O
A Out
P3.5
LCD29
D I/O
A Out
P3.6
LCD30
D I/O
A Out
Rev. 1.1
5
CP2400-C-GDI
Table 2.1. Pin Definitions for the CP2400-C-GDI (Continued)
Name
Physical Pad
Number
Type
Description
SPI
SMBus/
2
I C
P3.7
LCD31
11
10
9
11
10
9
D I/O
A Out
Bit 7, Port 3
Bit 0, Port 4
Bit 1, Port 4
Bit 2, Port 4
Bit 3, Port 4
P4.0
COM0
D I/O
A Out
P4.1
COM1
D I/O
A Out
P4.2
COM2
8
8
D I/O
A Out
P4.3
COM3
7
7
D I/O
A Out
6
Rev. 1.1
CP2400-C-GDI
3. Bonding Information
3.1. SPI Bonding Information
Table 3.1. SPI Bonding Pad Coordinates (Relative to Center of Die)
Physical Pad
Number
Example Package Package Pin Name
Physical Pad X
(µm)
Physical Pad Y
(µm)
Pin Number
(QFN-48)
1
48
CAP
–858.75
–858.75
–858.75
–858.75
–858.75
–858.75
–858.75
–858.75
–858.75
–858.75
–858.75
–858.75
–858.75
–858.75
–858.75
–508.49
–433.49
–358.49
–283.49
–208.49
–133.49
–58.49
545.41
470.41
395.41
320.41
245.41
170.41
50.41
2
1
XTAL1
3
2
XTAL2
4
3
VDD
5
4
GND
6
4
GND
7
5
P4.3/COM3
P4.2/COM2
P4.1/COM1
P4.0/COM0
P3.7/LCD31
P3.6/LCD30
P3.5/LCD29
P3.4/LCD28
P3.3/LCD27
P3.2/LCD26
P3.1/LCD25
P3.0/LCD24
P2.7/LCD23
P2.6/LCD22
P2.5/LCD21
P2.4/LCD20
P2.3/LCD19
P2.2/LCD18
P2.1/LCD17
P2.0/LCD16
—
8
6
–24.59
–99.59
–174.59
–249.59
–324.59
–399.59
–474.59
–549.59
–739.5
–739.5
–739.5
–739.5
–739.5
–739.5
–739.5
–739.5
–739.5
–739.5
–739.5
–739.5
–739.5
–739.5
9
7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
8
9
10
11
12
13
14
15
16
17
18
19
20
21
61.51
22
136.51
23
211.51
24
286.51
Reserved*
Reserved*
Reserved*
361.51
—
436.51
—
511.51
*Note: Pins marked “Reserved” should not be connected.
Rev. 1.1
7
CP2400-C-GDI
Table 3.1. SPI Bonding Pad Coordinates (Relative to Center of Die) (Continued)
Physical Pad
Number
Example Package Package Pin Name
Physical Pad X
(µm)
Physical Pad Y
(µm)
Pin Number
(QFN-48)
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
Reserved*
—
858.75
858.75
858.75
858.75
858.75
858.75
858.75
858.75
858.75
858.75
858.75
858.75
858.75
858.75
509.87
434.87
359.87
284.87
209.87
134.87
14.87
–515.09
–440.09
–365.09
–290.09
–215.09
–140.09
–65.09
54.91
25
P1.7/LCD15
P1.6/LCD14
P1.5/LCD13
P1.4/LCD12
P1.3/LCD11
P1.2/LCD10
P1.1/LCD9
P1.0/LCD8
P0.7/LCD7
P0.6/LCD6
P0.5/LCD5
P0.4/LCD4
GND
26
27
28
29
30
31
32
129.91
204.91
279.91
354.91
429.91
504.91
739.5
33
34
35
36
GND
Reserved*
—
37
P0.3/LCD3
P0.2/LCD2
P0.1/LCD1
P0.0/LCD0
SCK
739.5
38
739.5
39
739.5
40
739.5
41
739.5
42
MISO
739.5
43
MOSI
–60.13
–135.13
–210.13
–285.13
–360.13
–435.13
–510.12
739.5
44
Reserved*
Reserved*
45
NSS
739.5
—
739.5
—
739.5
INT
739.5
46
RST
739.5
47
CLK
739.5
*Note: Pins marked “Reserved” should not be connected.
8
Rev. 1.1
CP2400-C-GDI
48
1
25
13
Figure 3.1. Example Die Bonding (QFN-48) for SPI
Rev. 1.1
9
CP2400-C-GDI
2
3.2. SMBus/I C Bonding Information
Table 3.2. SMBus/I2C Bonding Pad Coordinates (Relative to Center of Die)
Physical Pad
Number
Example
Package Pin
Number
Package Pin Name Physical Pad X (µm) Physical Pad Y (µm)
(QFP-48)
1
48
CAP
–858.75
–858.75
–858.75
–858.75
–858.75
–858.75
–858.75
–858.75
–858.75
–858.75
–858.75
–858.75
–858.75
–858.75
–858.75
–508.49
–433.49
–358.49
–283.49
–208.49
–133.49
–58.49
545.41
470.41
395.41
320.41
245.41
170.41
50.41
2
1
XTAL1
3
2
XTAL2
4
3
VDD
5
4
GND
6
4
GND
7
5
P4.3/COM3
P4.2/COM2
P4.1/COM1
P4.0/COM0
P3.7/LCD31
P3.6/LCD30
P3.5/LCD29
P3.4/LCD28
P3.3/LCD27
P3.2/LCD26
P3.1/LCD25
P3.0/LCD24
P2.7/LCD23
P2.6/LCD22
P2.5/LCD21
P2.4/LCD20
P2.3/LCD19
P2.2/LCD18
P2.1/LCD17
P2.0/LCD16
—
8
6
–24.59
–99.59
–174.59
–249.59
–324.59
–399.59
–474.59
–549.59
–739.5
–739.5
–739.5
–739.5
–739.5
–739.5
–739.5
–739.5
–739.5
–739.5
–739.5
–739.5
–739.5
–739.5
9
7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
8
9
10
11
12
13
14
15
16
17
18
19
20
21
61.51
22
136.51
23
211.51
24
286.51
Reserved*
Reserved*
Reserved*
361.51
—
436.51
—
511.51
*Note: Pins marked “Reserved” should not be connected.
10
Rev. 1.1
CP2400-C-GDI
Table 3.2. SMBus/I2C Bonding Pad Coordinates (Relative to Center of Die)
Physical Pad
Number
Example
Package Pin
Number
Package Pin Name Physical Pad X (µm) Physical Pad Y (µm)
(QFP-48)
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
Reserved*
—
858.75
858.75
858.75
858.75
858.75
858.75
858.75
858.75
858.75
858.75
858.75
858.75
858.75
858.75
509.87
434.87
359.87
284.87
209.87
134.87
14.87
–515.09
–440.09
–365.09
–290.09
–215.09
–140.09
–65.09
54.91
25
P1.7/LCD15
P1.6/LCD14
P1.5/LCD13
P1.4/LCD12
P1.3/LCD11
P1.2/LCD10
P1.1/LCD9
P1.0/LCD8
P0.7/LCD7
P0.6/LCD6
P0.5/LCD5
P0.4/LCD4
GND
26
27
28
29
30
31
32
129.91
204.91
279.91
354.91
429.91
504.91
739.5
33
34
35
36
GND
Reserved*
—
37
38
P0.3/LCD3
P0.2/LCD2
P0.1/LCD1
P0.0/LCD0
—
739.5
739.5
39
739.5
40
739.5
Reserved*
41
739.5
SMBA0
739.5
42
SDA
–60.13
–135.13
–210.13
–285.13
–360.13
–435.13
–510.12
739.5
43
SCL
739.5
GND
44
GND
739.5
/PWR
739.5
45
/INT
739.5
46
/RST
739.5
47
/CLK
739.5
*Note: Pins marked “Reserved” should not be connected.
Rev. 1.1
11
CP2400-C-GDI
Figure 3.2. Example Die Bonding (QFP-48) for SMBus/I2C
12
Rev. 1.1
CP2400-C-GDI
Table 3.3. Wafer and Die Information
CP2401C
8 in
Wafer ID
Wafer Dimensions
Die Dimensions
1.88 mm x 1.64 mm
12 mil ±1 mil
Notch
Wafer Thickness
Wafer Identification
Scribe Line Width
80 µm
Contact Sales for info
Standard
Die Per Wafer*
Passivation
Wafer Jar
60 µm x 60 µm
250 °C
Wafer Packaging Detail
Bond Pad Dimensions
Maximum Processing Temperature
Electronic Die Map Format
Bond Pad Pitch Minimum
.txt
65 µm
*Note: This is the Expected Known Good Die yielded per wafer and
represents the batch order quantity (one wafer).
Rev. 1.1
13
CP2400-C-GDI
4. Wafer Storage Guidelines
It is necessary to conform to appropriate wafer storage practices to avoid product degradation or contami-
nation.
Wafers may be stored for up to 18 months in the original packaging supplied by Silicon Labs.
Wafers must be stored at a temperature of 18–24 °C.
Wafers must be stored in a humidity-controlled environment with a relative humidity of <30%.
Wafers should be stored in a clean, dry, inert atmosphere (e.g. nitrogen or clean, dry air).
14
Rev. 1.1
CP2400-C-GDI
DOCUMENT CHANGE LIST
Revision 1.0 to Revision 1.1
Changed Wafer Packaging Detail to “Wafer Jar”
in Table 3.3 on page 13.
Rev. 1.1
15
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