CY28346OXCT [SILICON]
Processor Specific Clock Generator, 200MHz, CMOS, PDSO56, LEAD FREE, SSOP-56;
| 型号： | CY28346OXCT |
| 厂家： | 
SILICON |
| 描述： | Processor Specific Clock Generator, 200MHz, CMOS, PDSO56, LEAD FREE, SSOP-56 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总19页 (文件大小：186K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY28346
Clock Synthesizer with Differential CPU Outputs
• 5/6 copies of 3V66 clocks
Features
• SMBus support with read-back capabilities
• Compliant with Intel® CK 408 Mobile Clock Synthesizer
specifications
• Spread Spectrum electromagnetic interference (EMI)
reduction
• 3.3V power supply
• Dial-a-Frequency™ features
• Dial-a-dB™ features
• Three differential CPU clocks
• Ten copies of PCI clocks
• 56-pin TSSOP and SSOP packages
Table 1. Frequency Table[1]
66BUFF(0:2)/
USB/
S2
S1
S0 CPU (0:2)
3V66
3V66(0:4)
66IN/3V66–5
66-MHz clock input
66-MHz clock input
66-MHz clock input
66-MHZ clock input
66M
PCI_FPCI
66IN/2
66IN/2
66IN/2
66IN/2
33 M
REF
DOT
1
0
0
1
0
1
0
1
0
1
0
1
66M
100M
200M
133M
66M
66M
66IN
14.318M
14.318M
14.318M
14.318M
14.318M
14.318M
14.318M
14.318M
Hi-Z
48M
1
0
66M
66IN
48M
1
1
66M
66IN
48M
1
1
66M
66IN
48M
0
0
66M
66M
48M
0
0
100M
200M
133M
Hi-Z
66M
66M
66M
33 M
48M
0
1
66M
66M
66M
33 M
48M
0
1
66M
66M
66M
33 M
48M
M
M
0
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
0
TCLK/2
TCLK/4
TCLK/4
TCLK/4
TCLK/8
TCLK
TCLK/2
Block Diagram
Pin Configuration
1
2
3
4
5
6
7
8
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
REF
S1
S0
CPU_STP#
CPUT0
CPUC0
VDD
CPUT1
CPUC1
VSS
VDD
XIN
XOUT
XIN
XOUT
REF
VSS
CPUT(0:2)
CPUC(0:2)
PLL1
PCIF0
PCIF1
PCIF2
VDD
VSS
PCI0
PCI1
PCI2
PCI3
VDD
VSS
PCI4
PCI5
PCI6
VDD
VSS
CPU_STP#
IREF
VSSIREF
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
3V66_0
S(0:2)
VDD
CPUT2
CPUC2
MULT0
IREF
VSSIREF
S2
48MUSB
48MDOT
VDD
3V66_1/VCH
MULT0
VTT_PG#
PCI_STP#
/2
PCI(0:6)
PCI_F(0:2)
48M USB
48M DOT
PLL2
VSS
66B0/3V66_2
66B1/3V66_3
66B2/3V66_4
66IN/3V66_5
PD#
WD
Logic
PD#
3V66_1/VCH
PCI_STP#
3V66_0
VDD
VSS
SCLK
I2C
Logic
SDATA
SCLK
VDDA
VSSA
VTT_PG#
66B[0:2]/3V66[2:4]
66IN/3V66-5
Power
Up Logic
VDDA
SDATA
Note:
1. TCLK is a test clock driven on the XTAL_IN input during test mode. M = driven to a level between 1.0V and 1.8V. If the S2 pin is at a M level during power-up, a
0 state will be latched into the device’s internal state register.
........................Document #: 38-07331 Rev. *C Page 1 of 19
400 West Cesar Chavez, Austin, TX 78701
1+(512) 416-8500 1+(512) 416-9669
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CY28346
Pin Description
Pin
Name
PWR
I/O
I
Description
2
XIN
Oscillator Buffer Input. Connect to a crystal or to an external clock.
3
XOUT
VDD
VDD
O
Oscillator Buffer Output. Connect to a crystal. Donot connect when an external
clock is applied at XIN.
52, 51, 49, 48, CPUT(0:2),
O
O
O
Differential Host Output Clock Pairs. See Table 1 for frequency/functionality.
PCI Clock Outputs. Are synchronous to 66IN or 3V66 clock. See Table 1.
45, 44
CPUC(0:2)
PCI(0:6)
10, 11, 12, 13,
16, 17, 18
VDDP
VDD
5, 6, 7
PCIF (0:2)
33MHz PCI Clocks. 2 copies of 66IN or 3V66 clocks that may be free running
(not stopped when PCI_STP# is asserted LOW) or may be stoppable depending
on the programming of SMBus register Byte3,Bits (3:5).
56
42
REF
VDD
VDD
O
I
Buffered Output Copy of the Device’s XIN Clock.
IREF
Current Reference Programming Input for CPU Buffers. A resistor is
connected between this pin and VSSIREF.
28
VTT_PG#
VDD
I
Qualifying Input that Latches S(0:2) and MULT0. When this input is at a logic
LOW, the S(0:2) and MULT0 are latched.
39
38
33
35
48MUSB
48MDOT
VDD48
VDD48
VDD
O
O
O
O
Fixed 48 MHz USB Clock Outputs.
Fixed 48 MHZ DOT Clock Outputs.
3.3V 66 MHz Fixed-frequency Clock.
3V66_0
3V66_1/VCH
VDD
3.3V Clock Selectable with SMBus Byte0,Bit5, When Byte5,Bit5. When Byte
0,Bit 5 is at a logic 1, then this pin is a 48M output clock. When Byte0,Bit5 is a
logic 0, this is a 66M output clock (default).
25
43
PD#
VDD
I
Power-down Mode Pin. A logic LOW level causes the device to enter a
PU power-down state. All internal logic is turned off except for the SMBus logic. All
output buffers are stopped.
MULT0
I
Programming Input Selection for CPU Clock Current Multiplier.
PU
55, 54
29
S(0,1)
I
I
I
I
Frequency Select Inputs. See Table 1.
SDATA
Serial Data Input. Conforms to the SMBus specification of a Slave
Receive/Transmit device. It is an input when receiving data. It is an open drain
output when acknowledging or transmitting data.
30
40
SCLK
S2
I
I
Serial Clock Input. Conforms to the SMBus specification.
VDD
I
T
Frequency Select Input. See Table 1. This is a Tri-level input which is driven
HIGH, LOW or driven to a intermediate level.
34
PCI_STP#
VDD
I
PCI Clock Disable Input. When asserted LOW, PCI (0:6) clocks are synchro-
PU nously disabled in a LOW state. This pin does not effect PCIF (0:2) clocks’
outputs if they are programmed to be PCIF clocks via the device’s SMBus
interface.
53
CPU_STP#
VDD
I
CPU Clock Disable Input. When asserted LOW, CPUT (0:2) clocks are
PU synchronously disabled in a HIGH state and CPUC(0:2) clocks are synchro-
nously disabled in a LOW state.
24
66IN/3V66_5
VDD
VDD
I/O Input Connection for 66CLK(0:2) Output Clock Buffers if S2 = 1, or output
clock for fixed 66-MHz clock if S2 = 0. See Table 1.
21, 22, 23
66B(0:2)/
3V66(2:4)
O
3.3V Clock Outputs. These clocks are buffered copies of the 66IN clock or fixed
at 66 MHz. See Table 1.
1,8,14, 19, 32,
37, 46, 50
VDD
PWR 3.3V Power Supply.
4,9,15, 20, 27,
31, 36, 47
VSS
PWR Common Ground.
41
VSSIREF
PWR Current Reference Programming Input for CPU Buffers. A resistor is
connected between this pin and IREF. This pin should also be returned to device
VSS
.
26
VDDA
–
PWR Analog Power Input. Used for phase-locked loops (PLLs) and internal analog
circuits. It is also specifically used to detect and determine when power is at an
acceptable level to enable the device to operate.
........................Document #: 38-07331 Rev. *C Page 2 of 19
CY28346
Two-Wire SMBus Control Interface
Serial Control Registers
The two-wire control interface implements a Read/Write slave
only interface according to SMBus specification.
Following the acknowledge of the Address Byte, two additional
bytes must be sent:
The device will accept data written to the D2 address and data
may read back from address D3. It will not respond to any
other addresses, and previously set control registers are
retained as long as power in maintained on the device.
1. “Command code” byte
2. “Byte count” byte.
Although the data (bits) in the command is considered “don’t
care,” it must be sent and will be acknowledged. After the
Command Code and the Byte Count have been acknowl-
edged, the sequence (Byte 0, Byte 1, and Byte 2) described
below will be valid and acknowledged.
Byte 0: CPU Clock Register[2,3]
Bit
@Pup
Pin#
Description
7
0
Spread Spectrum Enable. 0 = Spread Off, 1 = Spread On
This is a Read and Write control bit.
6
0
0
CPU Clock Power-down Mode Select. 0 = Drive CPUT(0:2) to 4 or 6 IREF and drive
CPUC(0:2) LOW when PD# is asserted LOW. 1 = Tri-state all CPU outputs. This is only
applicable when PD# is LOW. It is not applicable to CPU_STP#.
5
4
3
35
3V66_1/VCH Frequency Select, 0 = 66M selected, 1 = 48M selected
This is a Read and Write control bit.
Pin 53 44,45,48,49,5 CPU_STP#. Reflects the current value of the external CPU_STP# (pin 53) This bit is
1,52 Read-only.
Pin 34 10,11,12,13,16 Reflects the current value of the internal PCI_STP# function when read. Internally PCI_STP#
,17,18
is a logical AND function of the internal SMBus register bit and the external PCI_STP# pin.
Frequency Select Bit 2. Reflects the value of SEL2 (pin 40). This bit is Read-only.
Frequency Select Bit 1. Reflects the value of SEL1 (pin 55). This bit is Read-only.
Frequency Select Bit 0. Reflects the value of SEL0 (pin 54). This bit is Read-only.
2
1
0
Pin 40
Pin 55
Pin 54
Byte 1: CPU Clock Register
Bit
7
@Pup
Pin 43
0
Pin#
43
Description
MULT0 (Pin 43) Value. This bit is Read-only.
6
53
CPUT/C(0:2) Output Functionality Control When CPU_STP# is Asserted. 0 = Drive
CPUT(0:2) to 4 or 6 IREF and drive CPUC(0:2) LOW when CPU_STP# asserted LOW.
1 = three-state all CPU outputs. This bit will override Byte0,Bit6 such that even if it is 0,
when PD# goes LOW the CPU outputs will be three-stated.
5
4
3
2
1
0
0
0
1
1
1
44,45
48,49
51,52
44,45
48,49
51,52
CPU2 Functionality Control When CPU_STP# is Asserted LOW. 1 = Free Running, 0 =
Stopped LOW with CPU_STP# asserted LOW. This is a Read and Write control bit.
CPU1 Functionality Control When CPU_STP# is Asserted LOW. 1 = Free Running, 0 =
Stopped LOW with CPU_STP# asserted LOW. This is a Read and Write control bit.
CPUT0 Functionality Control When CPU_STP# is Asserted LOW. 1 = Free Running, 0 =
Stopped LOW with CPU_STP# asserted LOW. This is a Read and Write control bit.
CPUT/C2 Output Control. 1 = enabled, 0 = disable HIGH and CPUC2 disables LOW. This
is a Read and Write control bit.
CPUT/C1 Output Control. 1 = enabled, 0 = disable HIGH and CPUC1 disables LOW. This
is a Read and Write control bit.
0
CPUT/C0 Output Control. 1 = enabled, 0 = disable HIGH and CPUC0 disables LOW. This
is a Read and Write control bit.
Notes:
2. PU = internal pull-up. PD = internal pull-down. T = tri-level logic input with valid logic voltages of LOW = < 0.8V, T = 1.0 – 1.8V and HIGH = > 2.0V.
3. The “Pin#” column lists the relevant pin number where applicable. The “@Pup” column gives the default state at power-up.
........................Document #: 38-07331 Rev. *C Page 3 of 19
CY28346
Byte 2: PCI Clock Control Register (all bits are Read and Write functional)
Bit
7
@Pup
Pin#
53
18
17
16
13
12
11
Description
REF Output Control. 0 = high strength, 1 = low strength.
PCI6 Output Control. 1 = enabled, 0 = forced LOW.
PCI5 Output Control. 1 = enabled, 0 = forced LOW.
PCI4 Output Control. 1 = enabled, 0 = forced LOW.
PCI3 Output Control. 1 = enabled, 0 = forced LOW.
PCI2 Output Control. 1 = enabled, 0 = forced LOW.
PCI1 Output Control. 1 = enabled, 0 = forced LOW.
PCI0 Output Control. 1 = enabled, 0 = forced LOW.
0
1
1
1
1
1
1
1
6
5
4
3
2
1
0
10
Byte 3: PCI_F Clock and 48M Control Register (all bits are Read and Write functional)
Bit
7
@Pup
Pin#
38
39
7
Description
48MDOT Output Control. 1 = enabled, 0 = forced LOW.
48MUSB Output Control. 1 = enabled, 0 = forced LOW.
1
1
0
0
0
1
1
1
6
5
PCI_STP#, Control of PCI_F2. 0 = Free Running, 1 = Stopped when PCI_STP# is LOW.
PCI_STP#, Control of PCI_F1. 0 = Free Running, 1 = Stopped when PCI_STP# is LOW.
PCI_STP#, Control of PCI_F0. 0 = Free Running, 1 = Stopped when PCI_STP# is LOW.
PCI_F2 Output Control. 1 = running, 0 = forced LOW.
4
6
3
5
2
7
1
6
PCI_F1 Output Control. 1 = running, 0 = forced LOW.
0
5
PCI_F0 Output Control. 1 = running, 0 = forced LOW.
Byte 4: DRCG Control Register (all bits are Read and Write functional)
Bit @Pup Pin# Description
7
6
5
4
3
2
1
0
0
0
1
1
1
1
1
1
SS2 Spread Spectrum Control Bit (0 = down spread, 1 = center spread).
Reserved. Set = 0.
33 3V66_0 Output Enabled. 1 = enabled, 0 = disable.
35 3V66_1/VCH Output Enable. 1 = enabled, 0 = disabled.
24 3V66_5 Output Enable. 1 = enabled, 0 = disabled.
23 66B2/3V66_4 Output Enabled. 1 = enabled, 0 = disabled.
22 66B1/3V66_3 Output Enabled. 1 = enabled, 0 = disabled.
21 66B0/3V66_2 Output Enabled. 1 = enabled, 0 = disabled.
Byte 5: Clock Control Register (all bits are Read and Write functional)
Bit @Pup Pin# Description
7
6
5
4
3
2
1
0
0
1
0
0
0
0
0
0
SS1 Spread Spectrum Control Bit.
SS0 Spread Spectrum Control Bit.
66IN to 66M delay Control MSB.
66IN to 66M delay Control LSB.
Reserved. Set = 0.
48MDOT Edge Rate Control. When set to 1, the edge is slowed by 15%.
Reserved. Set = 0.
USB edge rate control. When set to 1, the edge is slowed by 15%.
........................Document #: 38-07331 Rev. *C Page 4 of 19
CY28346
Byte 6: Silicon Signature Register[4] (all bits are Read-only)
Bit
7
@Pup
Pin#
Description
Description
Description
0
0
0
1
0
0
1
1
Revision = 0001
6
5
4
3
Vendor Code = 0011
2
1
0
Byte 7: Reserved Register
Bit
7
@Pup
Pin#
0
0
0
0
0
0
0
0
Reserved. Set = 0.
Reserved. Set = 0.
Reserved. Set = 0.
Reserved. Set = 0.
Reserved. Set = 0.
Reserved. Set = 0.
Reserved. Set = 0.
Reserved. Set = 0.
6
5
4
3
2
1
0
Byte 8: Dial-a-Frequency Control Register N
Bit
7
@Pup
Name
0
0
0
0
0
0
0
0
Reserved. Set = 0.
6
N6, MSB These bits are for programming the PLL’s internal N register. This access allows the user to
modify the CPU frequency at very high resolution (accuracy). All other synchronous clocks
(clocks that are generated from the same PLL, such as PCI) remain at their existing ratios
5
N5
4
N4
relative to the CPU clock.
3
N3
2
N2
1
N3
0
N0, LSB
Byte 9: Dial-a-Frequency Control Register R
Bit
7
@Pup
Name
Description
0
0
0
0
0
0
0
Reserved. Set = 0.
6
R5, MSB
R4
These bits are for programming the PLL’s internal R register. This access allows the user to
modify the CPU frequency at very high resolution (accuracy). All other synchronous clocks
(clocks that are generated from the same PLL, such as PCI) remain at their existing ratios
relative to the CPU clock.
5
4
R3
3
R2
2
R1
1
R0
DAF_ENB R and N register mux selection. 0 = R and N values come from the ROM. 1 = data is loaded
from DAF (SMBus) registers.
0
0
Note:
4. When writing to this register, the device will acknowledge the Write operation, but the data itself will be ignored.
........................Document #: 38-07331 Rev. *C Page 5 of 19
CY28346
therefore causing the average energy at any one point in this
band to decrease in value. This technique is achieved by
modulating the clock away from its resting frequency by a
certain percentage (which also determines the amount of EMI
reduction). In this device, Spread Spectrum is enabled by
setting specific register bits in the SMBus control bytes.
Table 3 is a listing of the modes and percentages of Spread
Spectrum modulation that this device incorporates.
Dial-a-Frequency Features
SMBus Dial-a-Frequency feature is available in this device via
Byte8 and Byte9.
P is a large-value PLL constant that depends on the frequency
selection achieved through the hardware selectors (S1, S0). P
value may be determined from Table 2.
Table 2. P Value
Table 3. Spread Spectrum
S(1:0)
0 0
P
SS2 SS1
SS0
0
Spread Mode
Down
Spread%
32005333
48008000
96016000
64010667
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
+0.00, –0.25
+0.00, –0.50
+0.00, –0.75
+0.00, –1.00
+0.13, –0.13
+0.25, –0.25
+0.37, –0.37
+0.50, –1.50
0 1
1
Down
1 0
0
Down
1 1
1
Down
0
Center
Center
Center
Center
Dial-a-dB Features
1
SMBus Dial-a-dB feature is available in this device via Byte8
and Byte9.
0
1
Spread Spectrum Clock Generation (SSCG)
Test and Measurement Set-up
Spread Spectrum is a modulation technique used to
minimizing EMI radiation generated by repetitive digital
signals. A clock presents the greatest EMI energy at the center
frequency it is generating. Spread Spectrum distributes this
energy over a specific and controlled frequency bandwidth
For Differential CPU Output Signals
The following diagram shows lumped test load configurations
for the differential Host Clock Outputs.
TPCB
Measurement Point
Measurem ent Point
CPUT
2pF
MULTSEL
TPCB
CPUC
2pF
Figure 1. 1.0V Test Load Termination
TPCB
Measurement Point
CPUT
VDD
2pF
2pF
MULTSEL
TPCB
Measurement Point
CPUC
Figure 2. 0.7V Test Load Termination
........................Document #: 38-07331 Rev. *C Page 6 of 19
CY28346
Output under Test
Probe
Load Cap
3.3V signals
tDC
-
-
3.3V
2.4V
1.5V
0.4V
0V
Tr
Tf
Figure 3. For Single-ended Output Signals
3. Series resistance in the buffer circuit—Ros (see Figure 4).
Buffer Characteristics
4. Current accuracy at given configuration into nominal test
load for given configuration.
Current Mode CPU Clock Buffer Characteristics
The current mode output buffer detail and current reference
circuit details are contained in the previous table of this data
sheet. The following parameters are used to specify output
buffer characteristics:
Iout is selectable depending on implementation. The param-
eters above apply to all configurations. Vout is the voltage at
the pin of the device.
The various output current configurations are shown in the
host swing select functions table. For all configurations, the
deviation from the expected output current is ±7% as shown in
the current accuracy table.
1. Output impedance of the current mode buffer circuit—Ro
(see Figure 4).
2. Minimum and maximum required voltage operation range
of the circuit—Vop (see Figure 4).
VDD3 (3.3V +/- 5%)
Slope ~ 1/R0
Ro
Iout
Ros
0V
1.2V
Iout
Vout = 1.2V max
Vout
Figure 4. Buffer Characteristics
........................Document #: 38-07331 Rev. *C Page 7 of 19
CY28346
Table 4. Host Clock (HCSL) Buffer Characteristics
Characteristic
Min.
Max.
Ro
3000 (recommended)
N/A
Ros
Vout
N/A
1.2V
Table 5. CPU Clock Current Select Function
Mult0
Board Target Trace/Term Z
Reference R, Iref – Vdd (3*Rr)
Rr = 221 1%, Iref = 5.00mA
Rr = 475 1%, Iref = 2.32mA
Output Current
Ioh = 4*Iref
Voh @ Z
1.0V @ 50
0.7V @ 50
0
1
50
50
Ioh = 6*Iref
Table 6. Group Timing Relationship and Tolerances
Description
Offset
2.5 ns
0.0 ns
2.5 ns
Tolerance
1.0 ns
Conditions
3V66 Leads PCI (unbuffered mode)
0 degrees phase shift
3V66 to PCI
48MUSB to 48MDOT Skew
66B(0:2) to PCI offset
1.0 ns
1.0 ns
66B Leads PCI (buffered mode)
USB and DOT 48M Phase Relationship
66B(0:2) to PCI Buffered Clock Skew
The 48MUSB and 48MDOT clocks are in phase. It is under-
stood that the difference in edge rate will introduce some
inherent offset. When 3V66_1/VCH clock is configured for
VCH (48-MHz) operation it is also in phase with the USB and
DOT outputs. See Figure 5.
Figure 7 shows the difference (skew) between the 3V33(0:5)
outputs when the 66M clocks are connected to 66IN. This
offset is described in the Group Timing Relationship and Toler-
ances section of this data sheet. The measurements were
taken at 1.5V.
3V66 to PCI Un-Buffered Clock Skew
66IN to 66B(0:2) Buffered Prop Delay
Figure 8 shows the timing relationship between 3V66(0:5) and
PCI(0:6) and PCI_F(0:2) when configured to run in the unbuf-
fered mode.
The 66IN to 66B(0:2) output delay is shown in Figure 6.
The Tpd is the prop delay from the input pin (66IN) to the
output pins (66B[0:2]). The outputs’ variation of Tpd is
described in the AC parameters section of this data sheet. The
measurement taken at 1.5V.
48MUSB
48MDOT
Figure 5. 48MUSB and 48MDOT Phase Relationship
66IN
Tpd
66B(0:2)
Figure 6. 66IN to 66B(0:2) Output Delay Figure
66B(0:2)
1.5-
3.5ns
PCI(0:6)
PCIF(0:2)
Figure 7. Buffer Mode – 33V66(0:1); 66BUF(0:2) Phase Relationship
........................Document #: 38-07331 Rev. *C Page 8 of 19
CY28346
CPU_STP# Clarification
Special Functions
The CPU_STP# signal is an active LOW input used to
synchronously stop and start the CPU output clocks while the
rest of the clock generator continues to function.
PCI_F and IOAPIC Clock Outputs
The PCIF clock outputs are intended to be used, if required,
for systems IOAPIC clock functionality. Any two of the PCI_F
clock outputs can be used as IOAPIC 33 Mhz clock outputs.
They are 3.3V outputs will be divided down via a simple
resistive voltage divider to meet specific system IOAPIC clock
voltage requirements. In the event that these clocks are not
required, they can be used as general PCI clocks or disabled
via the assertion of the PCI_STP# pin.
CPU_STP# – Assertion
When CPU_STP# pin is asserted, all CPUT/C outputs that are
set with the SMBus configuration to be stoppable via assertion
of CPU_STP# will be stopped after being sampled by two
falling CPUT/C clock edges. The final state of the stopped
CPU signals is CPUT = HIGH and CPU0C = LOW. There is no
change to the output drive current values during the stopped
state. The CPUT is driven HIGH with a current value equal to
(Mult 0 “select”) × (Iref), and the CPUC signal will not be
driven. Due to external pull-down circuitry CPUC will be LOW
during this stopped state.
3V66_1/VCH Clock Output
The 3V66_1/VCH pin has a dual functionality that is selectable
via SMBus.
Configured as DRCG (66M), SMBus Byte0, Bit 5 = “0”
CPU_STP# Deassertion
The default condition for this pin is to power-up in a 66M
operation. In 66M operation this output is SSCG-capable and
when spreading is turned on, this clock will be modulated.
The deassertion of the CPU_STP# signal will cause all
CPUT/C outputs that were stopped to resume normal
operation in a synchronous manner (meaning that no short or
stretched clock pulses will be produces when the clock
resumes). The maximum latency from the deassertion to
active outputs is no more than two CPUC clock cycles.
Configured as VCH (48M), SMBus Byte0, Bit 5 = “1”
In this mode, output is configured as a 48-Mhz non-spread
spectrum output that is phase-aligned with other 48M outputs
(USB and DOT) to within 1 ns pin-to-pin skew. The switching
of 3V66_1/VCH into VCH mode occurs at system power-on.
When the SMBus Bit 5 of Byte 0 is programmed from a “0” to
a “1,” the 3V66_1/VCH output may glitch while transitioning to
48M output mode.
Three-state Control of CPU Clocks Clarification
During CPU_STP# and PD# modes, CPU clock outputs may
be set to driven or undriven (tri-state) by setting the corre-
sponding SMBus entry in Bit6 of Byte0 and Bit6 of Byte1.
3V66(0:5)
Tpci
PCI(0:6)
PCI_F(0:2)
Figure 8. Unbuffered Mode – 3V66(0:5) to PCI (0:6) and PCI_F(0:2) Phase Relationship
CPU_STP#
CPUT
CPUC
CPUT
CPUC
Figure 9. CPU_STP# Assertion Waveform
........................Document #: 38-07331 Rev. *C Page 9 of 19
CY28346
PCI_STP# Assertion
time for capturing PCI_STP# going LOW is 10 ns (tsetup) (see
Figure 14.) The PCI_F (0:2) clocks will not be affected by this
pin if their control bits in the SMBus register are set to allow
them to be free running.
The PCI_STP# signal is an active LOW input used for
synchronous stopping and starting the PCI outputs while the
rest of the clock generator continues to function. The set-up
CPU_STP#
CPUT
CPUC
CPUT
CPUC
Figure 10. CPU_STP# Deassertion Waveform
Table 7. Cypress Clock Power Management Truth Table
B0b6
B1b6
PD#
CPU_STP# Stoppable CPUT
Stoppable
CPUC
Non-Stop CPUT Non-Stop CPUC
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Running
Iref x6
Iref x2
Iref x2
Running
Hi-Z
Running
Iref x6
LOW
Running
Running
Iref x2
Iref x2
Running
Running
Hi-Z
Running
Running
LOW
LOW
LOW
Running
Hi-Z
Running
Running
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Running
Iref x6
Hi-Z
Running
Iref x6
Hi-Z
Running
Running
Hi-Z
Running
Running
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Running
Hi-Z
Running
Hi-Z
Running
Running
Hi-Z
Running
Running
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
......................Document #: 38-07331 Rev. *C Page 10 of 19
CY28346
PCI_STP# – Deassertion (transition from logic “0”
to logic “1”)
asynchronous function for powering up the system. When PD#
is LOW, all clocks are driven to a LOW value and held there
and the VCO and PLLs are also powered down. All clocks are
shut down in a synchronous manner so has not to cause
glitches while transitioning to the LOW “stopped” state.
The deassertion of the PCI_STP# signal will cause all PCI(0:6)
and stoppable PCI_F(0:2) clocks to resume running in a
synchronous manner within two PCI clock periods after
PCI_STP# transitions to a HIGH level.
PD# – Assertion
Note. The PCI STOP function is controlled by two inputs. One
is the device PCI_STP# pin number 34 and the other is SMBus
Byte 0,Bit 3. These two inputs to the function are logically
AND’ed. If either the external pin or the internal SMBus
register bit is set LOW, the stoppable PCI clocks will be
stopped in a logic LOW state. Reading SMBus Byte 0,Bit 3 will
return a 0 value if either of these control bits are set LOW
(which indicates that the devices stoppable PCI clocks are not
running).
When PD# is sampled LOW by two consecutive rising edges
of the CPUC clock, then on the next HIGH-to-LOW transition
of PCIF, the PCIF clock is stopped LOW. On the next
HIGH-to-LOW transition of 66Buff, the 66Buff clock is stopped
LOW. From this time, each clock will stop LOW on its next
HIGH-to-LOW transition, except the CPUT clock. The CPU
clocks are held with the CPUT clock pin driven HIGH with a
value of 2 × Iref, and CPUC undriven. After the last clock has
stopped, the rest of the generator will be shut down.
PD# (Power-down) Clarification
PD# – Deassertion
The PD# (power-down) pin is used to shut off all clocks prior
to shutting off power to the device. PD# is an asynchronous
active LOW input. This signal is synchronized internally to the
device powering down the clock synthesizer. PD# is an
The power-up latency between PD# rising to a valid logic ‘1’
level and the starting of all clocks is less than 3.0 ms.
t setup
PCI_STP#
PCI_F(0:2) 33M
PCI(0:6) 33M
Figure 11. PCI_STP# Assertion Waveform
t setup
PCI_STP#
PCI_F(0:2)
PCI(0:6)
Figure 12. PCI_STP# Deassertion Waveform
......................Document #: 38-07331 Rev. *C Page 11 of 19
CY28346
66Buff[0..2]
PCIF
PW RDW N#
CPU 133MHz
CPU# 133MHz
3V66
66In
USB 48MHz
REF 14.318MHz
Figure 13. Power-down Assertion Timing Waveforms Figure—Buffered Mode
PWRDWN#
CPUT(0:2) 133MHz
CPUC(0:2) 133MHz
PCI 33MHz
3V66
USB 48MHz
REF 14.318MHz
Figure 14. Power-down Assertion Timing Waveforms—Unbuffered Mode
......................Document #: 38-07331 Rev. *C Page 12 of 19
CY28346
30uS min
<1.8mS
400uS max
66Buff1 / GMCH
66Buff[0,2]
PCIF / APIC
33MHz
PCI 33MHz
PWRDWN#
CPU 133MHz
CPU# 133MHz
3V66
66In
USB 48MHz
REF 14.318MHz
Figure 15. Power-down Deassertion Timing Waveforms—Buffered Mode
Table 8. PD# Functionality
PD#
1
DRCG
66M
66CLK (0:2)
66Input
PCI_F/PCI
66Input/2
LOW
PCI
66Input/2
LOW
USB/DOT
48M
0
LOW
LOW
LOW
......................Document #: 38-07331 Rev. *C Page 13 of 19
CY28346
Absolute Maximum Ratings[5]
Storage Temperature:................................ –65C to + 150C
Operating Temperature:.................................... 0C to +85C
Maximum Power Supply:................................................ 3.5V
Input Voltage Relative to VSS:.............................. VSS – 0.3V
Input Voltage Relative to VDDQ or AVDD: .............VDD + 0.3V
Current Accuracy[6]
Parameter
Iout
Conditions
Configuration
Load
Min.
Max.
VDD = nominal (3.30V)
M0 = 0 or 1 and Rr (see Table 1)
Nominal test load for given
configuration
–7%
Inom Inom
+ 7%
Iout
V
DD = 3.30 ± 5%
All combinations of M0 or 1 and Rr Nominal test load for given
(see Table 1) configuration
–12% + 12%
Inom Inom
DC Parameters (VDD = VDDA = 3.3V ±5%, TA = 0°C to +70°C)
Parameter
Description
Dynamic Supply Current
Power-down Supply Current
Input Pin Capacitance
Output Pin Capacitance
Pin Inductance
Conditions
All frequencies at maximum values[7]
Min.
Typ.
Max.
Unit
mA
mA
pF
IDD3.3V
280
IPD3.3V
PD# asserted
Note 8
CIN
5
6
COUT
LPIN
pF
7
nH
pF
CXTAL
Crystal Pin Capacitance
Measured from the XIN or XOUT pin to ground
30
36
42
AC Parameters (VDD = VDDA = 3.3V ±5%, TA = 0°C to +70°C)
66 MHz 100 MHz
133 MHz
200 MHz
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Unit Notes
Crystal
TDC
XIN Duty Cycle
47.5
52.5
71.0
47.5
52.5
47.5
52.5
71.0
47.5
52.5
71.0
%
9, 10, 11
TPERIOD
XIN period
69.84
69.84
71.0 69.84
69.84
ns
9, 12,
13, 10
VHIGH
VLOW
TR / TF
TCCJ
XIN HIGH Voltage
0.7VDD VDD
0.7VDD VDD 0.7VDD VDD 0.7VDD VDD
V
V
XIN LOW Voltage
0
0.3VDD
10.0
0
0.3VDD
10.0
0
0.3VDD
10.0
0
0.3VDD
10.0
XIN Rise and Fall Times
XIN Cycle to Cycle Jitter
ns
ps
14
500
500
500
500
12, 15,
10
CPU at 0.7V Timing
TDC
CPUT and CPUC Duty
Cycle
45
55
45
55
45
55
45
55
5.1
100
%
ns
ps
15, 16,
19
TPERIOD
CPUT and CPUC
Period
14.85
15.3
100
9.85
10.2
100
7.35
7.65
100
4.85
15, 16,
19
TSKEW
Any CPU to CPU Clock
Skew
12, 15,
16
Notes:
5. Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
6. Inom refers to the expected current based on the configuration of the device.
7. All outputs loaded as per maximum capacitive load table.
8. Absolute value = ((Programmed CPU Iref) × (2)) + 10 mA.
9. This parameter is measured as an average over 1 s duration, with a crystal center frequency of 14.31818 MHz.
10. When Xin is driven from an external clock source.
11. This is required for the duty cycle on the REF clock out to be as specified. The device will operate reliably with input duty cycles up to 30/70 but the REF clock
duty cycle will not be within data sheet specifications.
12. All outputs loaded as perTable 9 below.
13. Probes are placed on the pins and measurements are acquired at 1.5V for 3.3V signals (see test and measurement set-up section of this data sheet).
14. Measured between 0.2V and 0.7V
.
DD
DD
15. This measurement is applicable with Spread ON or Spread OFF.
16. Measured at crossing point (Vx) or where subtraction of CLK–CLK# crosses 0V Measured from V = 0.175V to V = 0.525V.
OL
OH
17. Measured from V = 0.175V to V = 0.525V.
OL
OH
18. Determined as a fraction of 2*(Trise–Tfall)/ (Trise+Tfall).
19. Test load is Rta = 33.2, Rd = 49.9.
......................Document #: 38-07331 Rev. *C Page 14 of 19
CY28346
AC Parameters (VDD = VDDA = 3.3V ±5%, TA = 0°C to +70°C) (continued)
66 MHz 100 MHz
133 MHz
200 MHz
Parameter
TCCJ
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Unit Notes
CPU Cycle to Cycle
Jitter
150
700
20%
150
150
150
ps
15, 16,
19
TR/TF
CPUT and CPUC Rise
and Fall Times
175
175
700
175
700
175
700
ps
15, 17,
20
Rise/Fall Matching
20%
20%
20%
17, 18,
19
DeltaTR
DeltaTF
VCROSS
Rise Time Variation
Fall Time Variation
125
125
430
125
125
430
125
125
430
125
125
430
ps
ps
17, 19
17, 19
Crossing Point Voltage
at 0.7V Swing
280
280
280
280
mV 15, 19
CPU at 1.0V Timing
TDC
CPUT and CPUC Duty
Cycle
45
55
45
55
45
55
45
55
%
15, 16
15, 16
TPERIOD
TSKEW
TCCJ
CPUT and CPUC
Period
14.85
15.3
100
150
467
325
9.85
10.2
100
150
467
325
7.35
7.65
100
150
467
325
4.85
5.1
nS
Any CPU to Any CPU
Clock Skew
100
150
467
325
pS 12, 15,
16
CPU Cycle to Cycle
Jitter
pS
ps
ps
12, 16
15, 20
21, 22
Differential
TR/TF
CPUT and CPUC Rise
and Fall Times
175
510
175
510
175
510
175
510
SE–
DeltaSlew
Absolute Single- ended
Rise/Fall Waveform
Symmetry
VCROSS
Cross Point at 1.0V
swing
760
760
760
760
mV
22
3V66
TDC
3V66 Duty Cycle
3V66 Period
45
55
45
55
45
55
45
55
%
12, 13
TPERIOD
THIGH
TLOW
15.0
4.95
4.55
0.5
15.3
15.0
4.95
4.55
0.5
15.3
15.0
4.95
4.55
0.5
15.3
15.0
4.95
4.55
0.5
15.3
ns 9, 12, 13
3V66 HIGH Time
3V66 LOW Time
ns
ns
ns
23
24
25
TR/TF
3V66 Rise and Fall
Times
2.0
500
250
250
2.0
500
250
250
2.0
500
250
250
2.0
500
250
250
TSKEW
Unbuffered
3V66 to 3V66 Clock
Skew
ps
ps
ps
12, 13
12, 13
12, 13
TSKEW
Buffered
3V66 to 3V66 Clock
Skew
TCCJ
DRCG Cycle to Cycle
Jitter
Notes:
20. Measurement taken from differential waveform, from –0.35V to +0.35V.
21. Measurements taken from common mode waveforms, measure rise/fall time from 0.41 to 0.86V. Rise/fall time matching is defined as “the instantaneous difference
between maximum CLK rise (fall) and minimum CLK# fall (rise) time or minimum CLK rise (fall) and maximum CLK# fall (rise) time.” This parameter is designed
form waveform symmetry.
22. Measured in absolute voltage, i.e., single-ended measurement.
23. THIGH is measured at 2.4V for non-host outputs.
24. TLOW is measured at 0.4V for all outputs.
25. Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V signals (see test and measurement set-up section of this data
sheet).
......................Document #: 38-07331 Rev. *C Page 15 of 19
CY28346
AC Parameters (VDD = VDDA = 3.3V ±5%, TA = 0°C to +70°C) (continued)
66 MHz 100 MHz
133 MHz
200 MHz
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Unit Notes
66B
TDC
66B(0:2) Duty Cycle
45
55
45
55
45
55
45
55
%
12, 13
12, 25
TR/TF
66B(0:2) Rise and Fall
Times
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
ns
TSKEW
TPD
Any 66B to Any 66B
Skew
175
4.5
175
4.5
175
4.5
175
4.5
ps
ns
ps
12, 13
12, 13
66IN to 66B(0:2) Propa- 2.5
gation Delay
2.5
2.5
2.5
TCCJ
66B(0:2) Cycle to Cycle
Jitter
100
100
100
100
12, 13,
26
PCI
TDC
PCI_F(0:2) PCI (0:6)
Duty Cycle
45
55
45
55
45
55
45
30
55
%
12, 13
TPERIOD
THIGH
TLOW
PCI_F(0:2) PCI (0:6)
Period
30.0
12.0
12.0
0.5
30.0
12.0
12.0
0.5
30.0
12.0
12.0
0.5
nS 9, 12, 13
PCI_F(0:2) PCI (0:6)
HIGH Time
12.0
12.0
0.5
nS
nS
nS
pS
ps
23
24
PCI_F(0:2) PCI (0:6)
LOW Time
TR/TF
TSKEW
TCCJ
PCI_F(0:2) PCI (0:6)
Rise and Fall Times
2.0
500
250
2.0
500
250
2.0
500
250
2.0
500
250
25
Any PCI Clock to Any
PCI Clock Skew
12, 13
12, 13
PCI_F(0:2) PCI (0:6)
Cycle to Cycle Jitter
48MUSB
TDC
48MUSB Duty Cycle
48MUSB Period
45
55
45
55
45
55
45
55
%
12, 13
12, 13
12, 25
TPERIOD
TR/TF
20.8299 20.8333 20.8299 20.8333 20.8299 20.8333 20.8299 20.8333 ns
48MUSB Rise and Fall
Times
1.0
2.0
1.0
2.0
1.0
2.0
1.0
2.10
ns
TCCJ
48MUSBCycletoCycle
Jitter
350
350
350
350
ps 9, 12, 13
48MDOT
TDC
48MDOT Duty Cycle
48MDOT Period
45
20.837
0.5
55
45
20.837
0.5
55
45
20.837
0.5
55
45
20.837
0.5
55
%
ns
ns
12, 13
12, 13
12, 13
TPERIOD
TR/TF
48MDOT Rise and Fall
Times
1.0
1.0
1.0
1.0
TCCJ
48MDOT Cycle to Cy-
cle Jitter
350
350
350
350
ps
12, 13
REF
TDC
REF Duty Cycle
REF Period
45
69.84
1.0
55
71.0
4.0
45
69.84
1.0
55
45
55
71.0
4.0
45
69.84
1.0
55
71.0
4.0
%
ns
ns
12, 13
12, 13
12, 25
TPERIOD
TR/TF
71.0 69.84
REF Rise and Fall
Times
4.0
1.0
TCCJ
REF Cycle to Cycle
Jitter
1000
1000
1000
1000
ps
12, 13
Note:
26. This figure is in addition to any jitter already present when the 66IN pin is being used as an input. Otherwise a 500-ps jitter figure is specified.
......................Document #: 38-07331 Rev. *C Page 16 of 19
CY28346
AC Parameters (VDD = VDDA = 3.3V ±5%, TA = 0°C to +70°C) (continued)
66 MHz 100 MHz
133 MHz
200 MHz
Parameter
Description
Min.
1.0
Max.
Min.
Max.
Min.
Max.
Min.
Max. Unit Notes
TPZL/TPZH
Output Enable Delay
(All Outputs)
10.0
1.0
10.0
1.0
10.0
1.0
10.0
10.0
3
ns
10
10
10
T
PZL/TPZH
Outputdisabledelay(all 1.0
outputs)
10.0
3
1.0
10.0
3
1.0
10.0
3
1.0
ns
TSTABLE
All Clock Stabilization
from Power-up
ms
TSS
TSH
TSU
Stopclock Set-up Time
Stopclock Hold Time
Oscillator Start-up Time
10.0
0
10.0
0
10.0
0
10.0
0
ns
ns
27
27
28
X
X
X
X
ms
VID (0:3),
SEL (0,1)
VTT_PWRGD#
PWRGD
0.2-0.3mS
Delay
Wait for
VTT_GD#
Sample Sels
State 2
VDD Clock Gen
Clock State
State 0
Off
State 1
State 3
(Note A)
On
Clock Outputs
Clock VCO
On
Figure 16. VTT_PWRGD# Timing Diagram29[29]
Off
Table 9. Maximum Lumped Capacitive Output Loads
Clock
PCI Clocks
3V66 (0,1)
66B(0:2)
Max. Load
Units
pF
30
30
30
20
10
50
pF
pF
48MUSB Clock
48MDOT
pF
pF
REF Clock
pF
Notes:
27. CPU_STP# and PCI _STP# set-up time with respect to any PCI_F clock to guarantee that the effected clock will stop or start at the next PCI_F clock’s rising edge
28. When crystal meets minimum 40 device series resistance specification.
29. Device is not affected, VTT_PWRGD# is ignored.
......................Document #: 38-07331 Rev. *C Page 17 of 19
CY28346
S1
S2
Sample
Inputs (pins
54,55)
Delay 0.25mS
Enable Outputs
VDDA = 2.0V
S0
S3
Normal
Operation
Power Off
VDD3.3 = Off
Figure 17. Clock Generator Power-up/Run State Diagram
Package Type
Ordering Information
Part Number
CY28346OC
Product Flow
56-pin SSOP – Tube
Commercial, 0 to 70C
Commercial, 0 to 70C
Commercial, 0 to 70C
Commercial, 0 to 70C
CY28346OCT
CY28346ZC
56-pin SSOP – Tape and Reel
56-pin TSSOP – Tube
CY28346ZCT
Lead-free
56-pin TSSOP – Tape and Reel
CY28346OXC
CY28346OXCT
CY28346ZXC
CY28346ZXCT
56-pin SSOP – Tube
Commercial, 0 to 70C
Commercial, 0 to 70C
Commercial, 0 to 70C
Commercial, 0 to 70C
56-pin SSOP – Tape and Reel
56-pin TSSOP – Tube
56-pin TSSOP – Tape and Reel
......................Document #: 38-07331 Rev. *C Page 18 of 19
CY28346
Package Drawing and Dimensions
56-lead Shrunk Small Outline Package O56
56-Lead Thin Shrunk Small Outline Package, Type II (6 mm x 12 mm) Z56
0.249[0.009]
28
1
DIMENSIONS IN MM[INCHES] MIN.
MAX.
7.950[0.313]
8.255[0.325]
REFERENCE JEDEC MO-153
PACKAGE WEIGHT 0.42gms
5.994[0.236]
6.198[0.244]
PART #
Z5624 STANDARD PKG.
ZZ5624 LEAD FREE PKG.
29
56
13.894[0.547]
14.097[0.555]
1.100[0.043]
MAX.
GAUGE PLANE
0.25[0.010]
0.20[0.008]
0.508[0.020]
0.762[0.030]
0.051[0.002]
0.152[0.006]
0.851[0.033]
0.950[0.037]
0.500[0.020]
BSC
0°-8°
0.100[0.003]
0.200[0.008]
0.170[0.006]
0.279[0.011]
SEATING
PLANE
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Sil-
icon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the
use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or
parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, repre-
sentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-
sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized appli-
cation, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
......................Document #: 38-07331 Rev. *C Page 19 of 19
相关型号：
CY28346ZC
Processor Specific Clock Generator, 200MHz, CMOS, PDSO56, 6 X 12 MM, MO-153, TSSOP2-56
SILICON
CY28346ZCT
Processor Specific Clock Generator, 200MHz, CMOS, PDSO56, 6 X 12 MM, MO-153, TSSOP2-56
SILICON
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