CY28549LFXC [SILICON]
Clock Generator,;
| 型号： | CY28549LFXC |
| 厂家： | 
SILICON |
| 描述： | Clock Generator, |
| 文件： | 总23页 (文件大小：860K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY28549
PRELIMINARY
Clock Generator for Intel® CK410M
• 96/100-MHz low power spreadable differential video
clock
Features
• Compliant to Intel® CK410M
• 33-MHz PCI clocks
• Selectable CPU frequencies
• Buffered Reference Clock 14.318 MHz
• Low-voltage frequency select inputs
• I2C support with readback capabilities
• Low power differential CPU clock pairs
• 100-MHz low power differential SRC clocks
• 96-MHz low power differential dot clock
• 27-MHz Spread and Non-spread video clock
• 48-MHz USB clock
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 3.3V power supply
• 72-pin QFN package
• SRC clocks independently stoppable through
CLKREQ#[1:9]
Table 1. Output Confguration Table
CPU
SRC
PCI
x5
REF
x 2
DOT96
x 1
USB_48M
x 1
LCD
x1
27M
x2
x2/x3
x9/11
Block Diagram
Pin Configuration
VDD_REF
REF[1:0]
Xin
Xout
14.318MHz
Crystal
PLL Reference
VDD_CPU
CPUT[1:0]
CPUC[1:0]
CPU_STP#
PCI_STP#
CLKREQ#
PLL1
CPU
Divider
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
VDD_SRC
1
2
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
CLKREQ9#
VDD_SRC
SRCC_9
VDD_SRC
CPUT2_ITP/SRCT10
CPUC2_ITP/SRCC10
SRCC_2
FS[C:A]
ITP_EN
3
SRCT_2
SRCT_9
4
SRCC_1/SATAC
SRCT_1/SATAT
VDD_SRC
VDD_SRC
5
VSS_SRC
Divider
Divider
CPUC2_ITP
CPUT2_ITP
/
SRCC_10
SRCT_10
VDDA
6
SRCT [9:1]
SRCC [9:1]
/
7
SRCC_0
SRCT_0
/
LCD100MC
8
/ LCD100MT
VDD_PCI
VSSA
9
CY28549
CLKREQ1#
PCI[4:1]
GND
10
11
12
13
14
15
16
17
18
FSB/TEST_MODE
VDD_PCI
CPUC1_MCH
CPUT1_MCH
VDD_CPU
CPUC0
DOT96C
DOT96T
VSS_48
/
27M_SS
/
27M_NSS
PCIF0
VDD_SRC
48M
/ FSA
PLL3
Graphi
c
LCD_100MT/SRCT0
LCD_100MC/SRCC0
Divider
Divider
CPUT0
VDD_48
VSS_CPU
SCLK
VTT_PW RGD#
CLKREQ7#
/ PD
VDD_48
27_SS
FCTSEL
SDATA
PCIF0/ITP_SEL
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
VDD_48
PLL2
Fixed
DOT96T
DOT96C
VDD_48
USB_48 [1:0]
PLL4
27M
VDD_48
27_NSS
VTTPWR_GD#/PD
I2C
Logic
SDATA
SCLK
Cypress Semiconductor Corporation
Document #:xxx-xxxxx Rev **
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 14, 2006
PRELIMINARY
CY28549
Pin Description
Pin No.
Name
CLKREQ9#
VDD_SRC
Type
Description
3.3V LVTTL input for enabling assigned SRC clock (active LOW).
1
2
3
4
5
6
I
PWR 3.3V power supply for outputs.
SRCC_9
SRCT_9
VSS_SRC
O, DIF Complementary 100-MHz Differential serial reference clocks.
O, DIF True 100-MHz Differential serial reference clocks.
GND Ground for outputs.
CPUC2_ITP/SRCC10 O, DIF Selectable Complementary differential CPU or SRC clock output.
ITP_SEL = 0 @ VTTPWRGD#/PD assertion = SRC10
ITP_SEL = 1 @ VTTPWRGD#/PD assertion = CPU2
7
CPUT2_ITP/SRCT10, O, DIF Selectable True differential CPU or SRC clock output.
ITP_SEL = 0 @ VTTPWRGD#/PD assertion = SRC10
ITP_SEL = 1 @ VTTPWRGD#/PD assertion = CPU2
8
VDDA
PWR 3.3V power supply for PLL.
9
VSSA
GND Ground for PLL.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
GND
GND Ground for outputs.
CPUC1_MCH,
CPUT1_MCH,
VDD_CPU
CPUC0
O, DIF Complementary Differential CPU clock output to MCH
O, DIF True Differential CPU clock output to MCH
PWR 3.3V power supply for outputs.
O, DIF Complementary Differential CPU clock output
O, DIF True Differential CPU clock output
GND Ground for outputs.
CPUT0
VSS_CPU
SCLK
I
SMBus-compatible SCLOCK.
SDATA
I/O, OD SMBus-compatible SDATA.
PWR 3.3V power supply for outputs.
O, SE 14.318-MHz crystal output.
VDD_REF
XOUT
XIN
I
14.318-MHz crystal input.
VSS_REF
REF0/FSC_TESTSEL
GND Ground for outputs.
I/O
Fixed 14.318 clock output/3.3V-tolerant input for CPU frequency
selection/Selects test mode if pulled to VIMFS_C when VTTPWRGD#/PD is
asserted LOW.
Refer to DC Electrical Specifications table for VILFS_C,VIMFS_C,VIHFS_C specifi-
cations.
24
25
26
27
28
29
30
31
32
33
CPU_STP#
PCI_SRC_STP#
CLKREQ2#
PCI1
I
I
I
3.3V LVTTL input for CPU_STP# active LOW
3.3V LVTTL input for PCI_STP# active LOW
3.3V LVTTL input for enabling assigned SRC clock (active LOW).
O, SE 33MHz clock output
CLKREQ3#
CLKREQ5#
VDD_PCI
VSS_PCI
PCI2
I
I
3.3V LVTTL input for enabling assigned SRC clock (active LOW).
3.3V LVTTL input for enabling assigned SRC clock (active LOW).
PWR 3.3V power supply for outputs.
GND Ground for outputs.
O, SE 33-MHz clock output
O, SE 33-MHz clock output
PCI3
Document #:xxx-xxxxx Rev **
Page 2 of 23
PRELIMINARY
CY28549
Pin Description (continued)
Pin No.
Name
Type
Description
34
PCI4/FCTSEL1
I/O,SE, 33-MHz clock output/3.3V LVTTL input for selecting pins 47,48 (SRC[T/C]0,
100M[T/C]) and pins 43,44 (DOT96[T/C] and 27M Spread and Non-spread)
(sampled on VTTPWRGD#/PD assertion).
FCTSEL1 Pin 43
0 DOT96T
Pin 44
DOT96C
27M_SS
Pin 47
Pin 48
96/100M_T 96/100M_C
1 27M_NSS
SRCT0 SRCC0
35
36
37
VSS_PCI
GND Ground for outputs.
PWR 3.3V power supply for outputs.
VDD_PCI
ITP_SEL/PCIF0
I/O, SE 3.3V LVTTL input to enable SRC10 or CPU2_ITP/33-MHz clock output. (sampled
on VTTPWRGD#/PD assertion).
1 = CPU2_ITP, 0 = SRC10
38
39
CLKREQ7#
I
I
3.3V LVTTL input for enabling assigned SRC clock (active LOW).
VTT_PWRGD#/PD
3.3V LVTTL input. This pin is a level sensitive strobe. it latches data on the FSA,
FSB, FSC, FCTSEL1 and ITP_SEL pins. After assertion, it becomes a real time
input for controlling power down.
40
41
VDD_48
PWR 3.3V power supply for outputs.
48M/FSA
I/O
Fixed 48-MHz clock output/3.3V-tolerant input for CPU frequency selection
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
42
43
VSS_48
GND Ground for outputs.
DOT96T/ 27M_NSS
O, DIF True Fixed 96-MHz clock output or 27 Mhz Spread and Non-spread output
Selected via FCTSEL1 at VTTPWRGD#/PD assertion.
44
45
DOT96C/ 27M_SS
FSB/TEST_MODE
O, DIF Complementary Fixed 96-MHz clock output or 27 Mhz Spread and Non-spread
output Selected via FCTSEL1 at VTTPWRGD#/PD assertion.
I
3.3V-tolerant input for CPU frequency selection. Selects Ref/N or Tri-state when
in test mode
0 = Tri-state, 1 = Ref/N
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
46
47
CLKREQ6#
I
3.3V LVTTL input for enabling assigned SRC clock (active LOW).
SRCT_0/
LCD100MT
O,DIF True 100-MHz differential serial reference clock output/Differential 96/100-MHz
SS clock for flat-panel display
Selected via FCTSEL1 at VTTPWRGD#/PD assertion.
48
SRCC0/
LCD100MC
O,DIF Complementary 100-MHz differential serial reference clock output/Differential
96/100-MHz SS clock for flat-panel display
Selected via FCTSEL1 at VTTPWRGD#/PD assertion.
49
50
51
52
53
54
55
56
57
58
59
60
61
VDD_SRC
SRCT_1/SATAT,
SRCC_1/SATAC
SRCT_2
PWR 3.3V power supply for outputs.
O, DIF True 100-MHz Differential serial reference clocks.
O, DIF Complementary 100-MHz Differential serial reference clocks.
O, DIF True 100-MHz Differential serial reference clocks.
O, DIF Complementary 100-MHz Differential serial reference clocks.
PWR 3.3V power supply for outputs.
SRCC_2
VDD_SRC
SRCT_3
O, DIF True 100-MHz Differential serial reference clocks.
O, DIF Complementary 100-MHz Differential serial reference clocks.
SRCC_3
CLKREQ4#
SRCT_4
I
3.3V LVTTL input for enabling assigned SRC clock (active LOW).
O, DIF True 100-MHz Differential serial reference clocks.
O, DIF Complementary 100-MHz Differential serial reference clocks.
GND Ground for outputs.
SRCC_4
VSS_SRC
SRCT_5
O, DIF True 100-MHz Differential serial reference clocks.
Document #:xxx-xxxxx Rev **
Page 3 of 23
PRELIMINARY
CY28549
Pin Description (continued)
Pin No.
Name
SRCC_5
Type
O, DIF Complementary 100-MHz Differential serial reference clocks.
3.3V LVTTL input for enabling assigned SRC clock (active LOW).
Description
62
63
64
65
66
67
68
69
70
71
72
CLKREQ6#
SRCT_6
I
O, DIF True 100-MHz Differential serial reference clocks.
O, DIF Complementary 100-MHz Differential serial reference clocks.
PWR 3.3V power supply for outputs.
SRCC_6
VDD_SRC
SRCT_7
O, DIF True 100-MHz Differential serial reference clocks.
O, DIF Complementary 100-MHz Differential serial reference clocks.
GND Ground for outputs.
SRCC_7
VSS_SRC
SRCC_8
SRCT_8
O, DIF Complementary 100-MHz Differential serial reference clocks.
O, DIF True 100-MHz Differential serial reference clocks.
CLKREQ8#
I
3.3V LVTTL input for enabling assigned SRC clock (active LOW).
initialize to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
Frequency Select Pins (FSA, FSB, and FSC)
Host clock frequency selection is achieved by applying the
appropriate logic levels to FSA, FSB, FSC inputs prior to
VTT_PWRGD# assertion (as seen by the clock synthesizer).
Upon VTT_PWRGD# being sampled LOW by the clock chip
(indicating processor VTT voltage is stable), the clock chip
samples the FSA, FSB, and FSC input values. For all logic
levels of FSA, FSB, and FSC, VTT_PWRGD# employs a
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in Table 3.
one-shot functionality in that once
a valid LOW on
VTT_PWRGD# has been sampled, all further VTT_PWRGD#,
FSA, FSB, and FSC transitions will be ignored, except in test
mode.
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
Table 2. Frequency Select Table FSA, FSB, and FSC
The block write and block read protocol is outlined in Table 4
while Table 5 outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h)
FSC FSB FSA
CPU
SRC
PCIF/PCI
33 MHz
33 MHz
33 MHz
33 MHz
27MHz
27 MHz
27 MHz
27 MHz
27 MHz
REF
DOT96
96 MHz
96 MHz
96 MHz
96 MHz
USB
1
0
0
0
0
0
1
1
1
1
1
0
100 MHz
133 MHz
166 MHz
200 MHz
100 MHz
100 MHz
100 MHz
100 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
48 MHz
48 MHz
48 MHz
48 MHz
Table 3. Command Code Definition
Bit
Description
7
0 = Block read or block write operation, 1 = Byte read or byte write operation
(6:0)
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be
'0000000'
Table 4. Block Read and Block Write Protocol
Block Write Protocol
Block Read Protocol
Description
Bit
1
Description
Bit
1
Start
Start
8:2
9
Slave address–7 bits
Write
8:2
9
Slave address–7 bits
Write
Document #:xxx-xxxxx Rev **
Page 4 of 23
PRELIMINARY
CY28549
Table 4. Block Read and Block Write Protocol (continued)
Block Write Protocol
Description
Block Read Protocol
Description
Bit
10
Bit
10
Acknowledge from slave
Acknowledge from slave
18:11
19
Command Code–8 bits
Acknowledge from slave
18:11
19
Command Code–8 bits
Acknowledge from slave
Repeat start
27:20
Byte Count–8 bits
20
(Skip this step if I2C_EN bit set)
28
36:29
37
Acknowledge from slave
Data byte 1–8 bits
27:21
28
Slave address–7 bits
Read = 1
Acknowledge from slave
Data byte 2–8 bits
29
Acknowledge from slave
Byte Count from slave–8 bits
Acknowledge
45:38
46
37:30
38
Acknowledge from slave
Data Byte/Slave Acknowledges
Data Byte N–8 bits
....
46:39
47
Data byte 1 from slave–8 bits
Acknowledge
....
....
Acknowledge from slave
Stop
55:48
56
Data byte 2 from slave–8 bits
Acknowledge
....
....
Data bytes from slave/Acknowledge
Data Byte N from slave–8 bits
NOT Acknowledge
....
....
....
Stop
Table 5. Byte Read and Byte Write Protocol
Byte Write Protocol
Byte Read Protocol
Description
Bit
1
Description
Bit
1
Start
Start
8:2
9
Slave address–7 bits
Write
8:2
9
Slave address–7 bits
Write
10
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Data byte–8 bits
10
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Repeated start
18:11
19
18:11
19
27:20
28
20
Acknowledge from slave
Stop
27:21
28
Slave address–7 bits
Read
29
29
Acknowledge from slave
Data from slave–8 bits
NOT Acknowledge
Stop
37:30
38
39
Control Registers
Byte 0 Control Register 0
Bit
7
@Pup
Name
Description
0
0
0
0
RESEREVD
RESEREVD
RESEREVD
RESEREVD
RESERVED
RESERVED
RESERVED
RESERVED
6
5
4
Document #:xxx-xxxxx Rev **
Page 5 of 23
PRELIMINARY
CY28549
Control Registers
Byte 0 Control Register 0
Bit
3
@Pup
Name
Description
0
0
0
1
RESEREVD
RESEREVD
RESEREVD
RESEREVD
RESERVED
RESERVED
RESERVED
RESERVED
2
1
0
Byte 1 Control Register 1
Bit
@Pup
Name
Description
7
1
SRC[T/C]7
SRC[T/C]7 Output Enable
0 = Disabled, 1 = Enabled
6
5
4
3
2
1
0
1
1
1
1
1
1
1
SRC[T/C]6
SRC[T/C]5
SRC[T/C]4
SRC[T/C]3
SRC[T/C]2
SRC[T/C]1
SRC[T/C]6 Output Enable
0 = Disabled, 1 = Enabled
SRC[T/C]5 Output Enable
0 = Disabled, 1 = Enabled
SRC[T/C]4 Output Enable
0 = Disabled, 1 = Enabled
SRC[T/C]3 Output Enable
0 = Disabled, 1 = Enabled
SRC[T/C]2 Output Enable
0 = Disabled, 1 = Enabled
SRC[T/C]1 Output Enable
0 = Disabled, 1 = Enabled
SRC[T/C]0
/LCD_96_100M[T/C]
SRC[T/C]0/LCD_96_100M[T/C] Output Enable
0 = Disabled, 1 = Enabled
Byte 2 Control Register 2
Bit
@Pup
Name
Description
7
1
PCIF0
PCIF0 Output Enable
0 = Disabled, 1 = Enabled
6
5
4
1
1
1
27M NSS/DOT_96[T/C] 27M Non-spread and DOT_96 MHz Output Enable
0 = Disable, 1 = Enabled
48M
48-MHz Output Enable
0 = Disabled, 1 = Enabled
REF0
REF0 Output Enable
0 = Disabled, 1 = Enabled
3
2
1
1
RESERVED
CPU[T/C]1
RESERVED
CPU[T/C]1 Output Enable
0 = Disabled, 1 = Enabled
1
0
1
1
CPU[T/C]0
CPU[T/C]0 Output Enable
0 = Disabled, 1 = Enabled
CPU, SRC, PCI, PCIF PLL1 (CPU PLL) Spread Spectrum Enable
Spread Enable
0 = Spread off, 1 = Spread on
Byte 3 Control Register 3
Bit
@Pup
Name
Description
7
1
PCI4
PCI4 Output Enable
0 = Disabled, 1 = Enabled
6
5
1
1
PCI3
PCI2
PCI3 Output Enable
0 = Disabled, 1 = Enabled
PCI2 Output Enable
0 = Disabled, 1 = Enabled
Document #:xxx-xxxxx Rev **
Page 6 of 23
PRELIMINARY
CY28549
Byte 3 Control Register 3
Bit
@Pup
Name
Description
4
1
PCI1
PCI1 Output Enable
0 = Disabled, 1 = Enabled
3
2
1
1
1
1
RESERVED
RESERVED
RESERVED
RESERVED
CPU[T/C]2/SRC[T/C]10 CPU[T/C]2/SRC[T/C]10 Output Enable
0 = Disabled, 1 = Enabled
0
1
RESERVED
RESERVED
Byte 4 Control Register 4
Bit
@Pup
Name
Description
7
0
SRC7
Allow control of SRC[T/C]7 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
6
5
4
3
2
1
0
0
0
0
0
0
0
0
SRC6
SRC5
SRC4
SRC3
SRC2
SRC1
SRC0
Allow control of SRC[T/C]6 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]5 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]4 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]3 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]2 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]1 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]0 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Byte 5 Control Register 5
Bit
@Pup
Name
Description
7
0
LCD_96_100M[T/C]
LCD_96_100M[T/C] PWRDWN Drive Mode
0 = Driven in PWRDWN, 1 = Tri-state
6
0
DOT96[T/C]
DOT PWRDWN Drive Mode
0 = Driven in PWRDWN, 1 = Tri-state
5
4
3
0
0
0
RESERVED
RESERVED
PCIF0
RESERVED, Set = 0
RESERVED, Set = 0
Allow control of PCIF0 with assertion of SW and HW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
2
1
0
1
1
1
CPU[T/C]2
CPU[T/C]1
CPU[T/C]0
Allow control of CPU[T/C]2 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
Allow control of CPU[T/C]1 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
Allow control of CPU[T/C]0 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
Byte 6 Control Register 6
Bit
@Pup
Name
Description
7
0
SRC[T/C]
SRC[T/C] Stop Drive Mode
0 = Driven when PCI_STP# asserted
1 = Tri-state when PCI_STP# asserted
6
0
CPU[T/C]2
CPU[T/C]2 Stop Drive Mode
0 = Driven when CPU_STP# asserted
1 = Tri-state when CPU_STP# asserted
Document #:xxx-xxxxx Rev **
Page 7 of 23
PRELIMINARY
CY28549
Byte 6 Control Register 6
5
4
3
2
1
0
0
0
0
0
0
0
CPU[T/C]1
CPU[T/C]0
SRC[T/C][9:1]
CPU[T/C]2
CPU[T/C]1
CPU[T/C]0
CPU[T/C]1 Stop Drive Mode
0 = Driven when CPU_STP# asserted
1 = Tri-state when CPU_STP# asserted
CPU[T/C]0 Stop Drive Mode
0 = Driven when CPU_STP# asserted
1 = Tri-state when CPU_STP# asserted
SRC[T/C][9:1] PWRDWN Drive Mode
0 = Driven when PD asserted
1 = Tri-state when PD asserted
CPU[T/C]2 PWRDWN Drive Mode
0 = Driven when PD asserted
1 = Tri-state when PD asserted
CPU[T/C]1 PWRDWN Drive Mode
0 = Driven when PD asserted
1 = Tri-state when PD asserted
CPU[T/C]0 PWRDWN Drive Mode
0 = Driven when PD asserted
1 = Tri-state when PD asserted
Byte 7 Control Register 7
Bit
@Pup
Name
Description
7
0
TEST_SEL
REF/N or Tri-state Select
0 = Tri-state, 1 = REF/N Clock
6
0
TEST_MODE
Test Clock Mode Entry Control
0 = Normal operation, 1 = REF/N or Tri-state mode,
5
4
1
1
RESEREVD
REF0
RESERVED
REF0 Output Drive Strength
0 = Low, 1 = High
3
1
PCI, PCIF and SRC clock SW PCI_STP Function
outputs except those set to 0 = SW PCI_STP assert, 1= SW PCI_STP deassert
free running
When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will
be stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will
resume in a synchronous manner with no short pulses.
2
1
0
HW
HW
HW
FSC
FSB
FSA
FSC Reflects the value of the FSC pin sampled on power up
0 = FSC was low during VTT_PWRGD# assertion
FSB Reflects the value of the FSB pin sampled on power up
0 = FSB was low during VTT_PWRGD# assertion
FSA Reflects the value of the FSA pin sampled on power up
0 = FSA was low during VTT_PWRGD# assertion
Byte 8 Vendor ID
Bit
7
@Pup
Name
Description
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
0
1
0
1
1
0
0
0
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
6
5
4
3
2
Vendor ID Bit 2
Vendor ID Bit 2
1
Vendor ID Bit 1
Vendor ID Bit 1
0
Vendor ID Bit 0
Vendor ID Bit 0
Byte 9 Control Register 9
Bit @Pup
Name
Description
Document #:xxx-xxxxx Rev **
Page 8 of 23
PRELIMINARY
CY28549
Byte 9 Control Register 9
7
6
5
4
3
2
0
0
0
0
0
1
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
48M
RESERVED, Set = 0
RESERVED, Set = 0
RESERVED
RESERVED
RESERVED
48-MHz Output Drive Strength
0 = Low, 1 = High
1
0
1
1
RESERVED
PCIF0
RESERVED
PCIF0 Output Drive Strength
0 = Low, 1 = High
Byte 10 Control Register 10
Bit
7
@Pup
Name
RESERVED
RESERVED
S1
Description
0
0
0
0
RESERVED
RESERVED
6
5
27M_SS/LCD 96_100M SS Spread Spectrum Selection table:
S[1:0] SS%
‘00’ = –0.5%(Default value)
‘01’ = –1.0%
4
S0
‘10’ = –1.5%
‘11’ = –2.0%
3
2
1
1
RESERVED
27M_SS
RESERVED
27M Spread Output Enable
0 = Disabled, 1 = Enabled
1
1
27M_SS/LCD_100M
Spread Enable
27M_SS/LCD_100M Spread spectrum enable.
0 = Disabled, 1 = Enabled
0
0
RESERVED
RESERVED
Byte 11 Control Register 11
Bit
7
@Pup
Name
Description
RESERVED
0
0
1
RESERVED
RESERVED
SRC[T/C]9
6
RESERVED
5
SRC[T/C]9 Output Enable
0 = Disable (Hi-Z), 1 = Enable
4
1
SRC[T/C]8
SRC[T/C]8 Output Enable
0 = Disable (Hi-Z), 1 = Enable
3
2
1
0
RESERVED
SRC[T/C]10
RESERVED
Allow control of SRC[T/C]10 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
1
0
0
0
SRC[T/C]9
SRC[T/C]8
Allow control of SRC[T/C]9 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]8 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Byte 12 Control Register 12
Bit
7
@Pup
0
Name
Description
RESERVED, Set = 0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
6
HW
HW
HW
5
RESERVED
4
RESERVED
Document #:xxx-xxxxx Rev **
Page 9 of 23
PRELIMINARY
CY28549
Byte 12 Control Register 12
Bit
@Pup
Name
Description
3
1
27M_SS/27M_NSS
27-MHz (spread and non-spread) Output Drive Strength
0 = Low, 1 = High
2
1
0
0
1
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED, Set = 1
RESERVED
HW
Byte 13 Control Register 13
Bit
@Pup
Name
Description
7
0
CLKREQ#9
CLKREQ#9 Input Enable
0 = Disabled, 1 = Enabled
6
5
4
3
2
1
0
0
0
0
0
0
0
0
CLKREQ#8
CLKREQ#7
CLKREQ#6
CLKREQ#5
CLKREQ#4
CLKREQ#3
CLKREQ#2
CLKREQ#8 Input Enable
0 = Disabled, 1 = Enabled
CLKREQ#7 Input Enable
0 = Disabled, 1 = Enabled
CLKREQ#6 Input Enable
0 = Disabled, 1 = Enabled
CLKREQ#5 Input Enable
0 = Disabled, 1 = Enabled
CLKREQ#4 Input Enable
0 = Disabled, 1 = Enabled
CLKREQ#3 Input Enable
0 = Disabled, 1 = Enabled
CLKREQ#2 Input Enable
0 = Disabled, 1 = Enabled
Byte 14 Control Register 14
Bit
@Pup
Name
Description
7
0
CLKREQ#1
CLKREQ#1 Input Enable
0 = Disabled, 1 = Enabled
6
1
LCD 96_100M Clock
Speed
LCD 96_100M Clock Speed
0 = 96 MHz 1 = 100 MHz
5
4
3
1
1
1
RESERVED
RESERVED
PCI4
RESERVED, Set = 1
RESERVED, Set = 1
PCI4 (Spread and Non-spread) Output Drive Strength
0 = Low, 1 = High
2
1
0
1
1
1
PCI3
PCI2
PCI1
PCI3 (Spread and Non-spread) Output Drive Strength
0 = Low, 1 = High
PCI2 (Spread and Non-spread) Output Drive Strength
0 = Low, 1 = High
PCI1 (Spread and Non-spread) Output Drive Strength
0 = Low, 1 = High
Byte 15 Control Register 15
Bit
7
@Pup
Name
Description
RESERVED
HW
1
RESEREVD
RESERVED
RESERVED
RESERVED
RESERVED
6
RESERVED
5
1
RESERVED
4
1
RESERVED
3
1
RESERVED
Document #:xxx-xxxxx Rev **
Page 10 of 23
PRELIMINARY
CY28549
Byte 15 Control Register 15
Bit
2
@Pup
Name
Description
1
0
1
IO_VOUT2
IO_VOUT1
IO_VOUT0
IO_VOUT[2,1,0]
000 = 0.63V
001 = 0.71V
1
0
010 = 0.77V
011 = 0.82V (Default)
100 = 0.86V
101 = 0.90V
110 = 0.93V
111 = Reserved
Table 6. Crystal Recommendations
Frequency
Drive
(max.)
Shunt Cap Motional
Tolerance
(max.)
Stability
(max.)
Aging
(max.)
(Fund)
Cut
Loading Load Cap
(max.)
(max.)
14.31818 MHz
AT
Parallel 20 pF
0.1 mW
5 pF
0.016 pF
35 ppm
30 ppm
5 ppm
The CY28549 requires a Parallel Resonance Crystal. Substi-
tuting a series resonance crystal will cause the CY28549 to
operate at the wrong frequency and violate the ppm specifi-
cation. For most applications there is a 300-ppm frequency
shift between series and parallel crystals due to incorrect
loading.
Clock Chip
Ci2
Ci1
Pin
3 to 6p
Crystal Loading
Crystal loading plays a critical role in achieving low ppm perfor-
mance. To realize low ppm performance, the total capacitance
the crystal will see must be considered to calculate the appro-
priate capacitive loading (CL).
X2
X1
Cs2
Cs1
Trace
2.8 pF
Figure 1 shows a typical crystal configuration using the two
trim capacitors. An important clarification for the following
discussion is that the trim capacitors are in series with the
crystal not parallel. It’s a common misconception that load
capacitors are in parallel with the crystal and should be
approximately equal to the load capacitance of the crystal.
This is not true.
XTAL
Ce1
Ce2
Trim
33 pF
Figure 2. Crystal Loading Example
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2.
Load Capacitance (each side)
Ce = 2 * CL – (Cs + Ci)
Total Capacitance (as seen by the crystal)
1
CLe
=
1
1
Figure 1. Crystal Capacitive Clarification
(
)
+
Ce2 + Cs2 + Ci2
Ce1 + Cs1 + Ci1
CL....................................................Crystal load capacitance
Calculating Load Capacitors
CLe.........................................Actual loading seen by crystal
using standard value trim capacitors
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading. As mentioned previously,
the capacitance on each side of the crystal is in series with the
crystal. This means the total capacitance on each side of the
crystal must be twice the specified crystal load capacitance
(CL). While the capacitance on each side of the crystal is in
series with the crystal, trim capacitors (Ce1,Ce2) should be
calculated to provide equal capacitive loading on both sides.
Ce.....................................................External trim capacitors
Cs..............................................Stray capacitance (terraced)
Ci .......................................................... Internal capacitance
(lead frame, bond wires etc.)
CLK_REQ# Description
The CLKREQ# signals are active LOW inputs used for clean
enabling and disabling selected SRC outputs. The outputs
Document #:xxx-xxxxx Rev **
Page 11 of 23
PRELIMINARY
CY28549
CLKREQ#X
SRCT(free running)
SRCC(free running)
SRCT(stoppable)
SRCT(stoppable)
Figure 3. CLK_REQ#[1:9] Deassertion/Assertion Waveform
controlled by CLKREQ# are determined by the settings in
register byte 8. The CLKREQ# signal is a de-bounced signal
in that it’s state must remain unchanged during two consec-
utive rising edges of SRCC to be recognized as a valid
assertion or deassertion. (The assertion and deassertion of
this signal is absolutely asynchronous.)
shutting off power to the device. This signal is synchronized
internal to the device prior to powering down the clock synthe-
sizer. PD is also an asynchronous input for powering up the
system. When PD is asserted HIGH, all clocks need to be
driven to a LOW value and held prior to turning off the VCOs
and the crystal oscillator.
CLK_REQ[1:9]# Assertion (CLKREQ# -> LOW)
PD (Power-down) Assertion
All differential outputs that were stopped are to resume normal
operation in a glitch-free manner. The maximum latency from
the assertion to active outputs is between 2 and 6 SRC clock
periods (2 clocks are shown) with all SRC outputs resuming
simultaneously. All stopped SRC outputs must be driven HIGH
within 10 ns of CLKREQ# deassertion to a voltage greater than
200 mV.
When PD is sampled HIGH by two consecutive rising edges
of CPUC, all single-ended outputs will be held LOW on their
next HIGH-to-LOW transition and differential clocks must be
held HIGH or tri-stated (depending on the state of the control
register drive mode bit) on the next diff clock# HIGH-to-LOW
transition within 4 clock periods. When the SMBus PD drive
mode bit corresponding to the differential (CPU, SRC, and
DOT) clock output of interest is programmed to ‘0’, the clock
outputs are held with “Diff clock” pin driven HIGH, and “Diff
clock#” tri-state. If the control register PD drive mode bit corre-
sponding to the output of interest is programmed to “1”, then
both the “Diff clock” and the “Diff clock#” are tri-state. Note that
Figure 4 shows CPUT = 133 MHz and PD drive mode = ‘1’ for
all differential outputs. This diagram and description is appli-
cable to valid CPU frequencies 100, 133, 166, and 200 MHz.
In the event that PD mode is desired as the initial power-on
state, PD must be asserted HIGH in less than 10 μs after
asserting Vtt_PwrGd#. It should be noted that 96_100_SSC
will follow the DOT waveform when selected for 96 MHz and
the SRC waveform when in 100-MHz mode.
CLK_REQ[1:9]# Deassertion (CLKREQ# -> HIGH)
The impact of deasserting the CLKREQ# pins is that all SRC
outputs that are set in the control registers to stoppable via
deassertion of CLKREQ# are to be stopped after their next
transition. The final state of all stopped SRC clocks is
Low/Low.
PD (Power-down) Clarification
The VTT_PWRGD#/PD pin is a dual-function pin. During initial
power-up, the pin functions as VTT_PWRGD#. Once
VTT_PWRGD# has been sampled LOW by the clock chip, the
pin assumes PD functionality. The PD pin is an asynchronous
active HIGH input used to shut off all clocks cleanly prior to
PD
CPUT, 133MHz
CPUC, 133MHz
SRCT 100MHz
SRCC 100MHz
USB, 48MHz
DOT96T
DOT96C
PCI, 33 MHz
REF
Figure 4. Power-down Assertion Timing Waveform
Document #:xxx-xxxxx Rev **
Page 12 of 23
PRELIMINARY
CY28549
PD Deassertion
than 300 μs of PD deassertion to a voltage greater than
200 mV. After the clock chip’s internal PLL is powered up and
locked, all outputs will be enabled within a few clock cycles of
each other. Figure 5 is an example showing the relationship of
clocks coming up. It should be noted that 96_100_SSC will
follow the DOT waveform when selected for 96 MHz and the
SRC waveform when in 100-MHz mode.
The power-up latency is less than 1.8 ms. This is the time from
the deassertion of the PD pin or the ramping of the power
supply until the time that stable clocks are output from the
clock chip. All differential outputs stopped in a three-state
condition resulting from power down will be driven high in less
Tstable
<1.8 ms
PD
CPUT, 133MHz
CPUC, 133MHz
SRCT 100MHz
SRCC 100MHz
USB, 48MHz
DOT96T
DOT96C
PCI, 33MHz
Tdrive_PWRDN#
<300 μs, >200 mV
REF
Figure 5. Power-down Deassertion Timing Waveform
set with the SMBus configuration to be stoppable via assertion
CPU_STP# Assertion
of CPU_STP# will be stopped within two–six CPU clock
periods after being sampled by two rising edges of the internal
CPUC clock. The final state of all stopped CPU clocks is
High/Low when driven, Low/Low when tri-stated.
The CPU_STP# signal is an active LOW input used for
synchronous stopping and starting the CPU output clocks
while the rest of the clock generator continues to function.
When the CPU_STP# pin is asserted, all CPU outputs that are
CPU_STP#
CPUT
CPUC
Figure 6. CPU_STP# Assertion Waveform
CPU_STP#
CPUT
CPUC
CPUT Internal
CPUC Internal
Tdrive_CPU_STP#,10 ns>200 mV
Figure 7. CPU_STP# Deassertion Waveform
Document #:xxx-xxxxx Rev **
Page 13 of 23
PRELIMINARY
CY28549
PCI_STP# Assertion
driven Low, SRC outputs are High/Low if set to driven and
Low/Low if set to tri-state.
The PCI_STP# signal is an active LOW input used for
synchronous stopping and starting the PCI outputs and SRC
outputs if they are set to be stoppable in SMbus while the rest
of the clock generator continues to function. The set-up time
for capturing PCI_STP# going LOW is 10 ns (tSU). (See
Figure 9.) The PCIF clocks will not be affected by this pin if
their corresponding control bit in the SMBus register is set to
allow them to be free running. All stopped PCI outputs are
PCI_STP# Deassertion
The deassertion of the PCI_STP# signal will cause all PCI and
stoppable PCIF clocks to resume running in a synchronous
manner within two PCI clock periods after PCI_STP# transi-
tions to a HIGH level
1.8mS
CPU_STOP#
PD
CPUT(Free Running)
CPUC(Free Running)
CPUT(Stoppable)
CPUC(Stoppable)
DOT96T
DOT96C
Figure 8. CPU_STP# = Tri-state, CPU_PD = Tri-state, DOT_PD = Tri-state
Tsu
PCI_STP#
PCI_F
PCI
SRC 100MHz
Figure 9. PCI_STP# Assertion Waveform
1.8 ms
CPU_STOP#
PD
CPUT(Free Running
CPUC(Free Running
CPUT(Stoppable)
CPUC(Stoppable)
Figure 10. CPU_STP# = Driven, CPU_PD = Driven, DOT_PD = Driven
Document #:xxx-xxxxx Rev **
Page 14 of 23
PRELIMINARY
CY28549
Tdrive_SRC
Tsu
PCI_STP#
PCI_F
PCI
SRC 100MHz
Figure 11. PCI_STP# Deassertion Waveform
FS_A, FS_B,FS_C
VTT_PWRGD#
PWRGD_VRM
0.2-0.3mS
Delay
Wait for
VTT_PWRGD#
Device is not affected,
VTT_PWRGD# is ignored
Sample Sels
State 2
VDD Clock Gen
Clock State
State 0
Off
State 1
State 3
On
Clock Outputs
Clock VCO
On
Off
Figure 12. VTTPWRGD# Timing DIagram
Document #:xxx-xxxxx Rev **
Page 15 of 23
PRELIMINARY
CY28549
Absolute Maximum Conditions
Parameter
VDD
Description
Core Supply Voltage
Condition
Min.
–0.5
–0.5
–0.5
–65
0
Max.
4.6
Unit
V
4.6
VDD_A
VIN
Analog Supply Voltage
Input Voltage
V
V
+ 0.5
Relative to VSS
Non-functional
VDC
°C
DD
TS
Temperature, Storage
150
85
150
20
60
–
TA
Temperature, Operating Ambient
Temperature, Junction
Functional
°C
TJ
Functional
–
°C
ØJC
Dissipation, Junction to Case
Dissipation, Junction to Ambient
Mil-STD-883E Method 1012.1
JEDEC (JESD 51)
–
°C/W
°C/W
V
ØJA
–
ESDHBM
UL-94
MSL
ESD Protection (Human Body Model) MIL-STD-883, Method 3015
2000
Flammability Rating
At 1/8 in.
V–0
1
Moisture Sensitivity Level
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
DC Electrical Specifications
Parameter
All VDDs
VILI2C
VIHI2C
VIL_FS
VIH_FS
VILFS_C
VIMFS_C
VIHFS_C
VIL
Description
3.3V Operating Voltage
Input Low Voltage
Condition
Min.
3.135
–
Max. Unit
3.3 ± 5%
3.465
1.0
V
V
SDATA, SCLK
SDATA, SCLK
Input High Voltage
2.2
–
V
V
V
– 0.3
FS_[A,B] Input Low Voltage
FS_[A,B] Input High Voltage
FS_C Input Low Voltage
FS_C Input Middle Voltage
FS_C Input High Voltage
3.3V Input Low Voltage
3.3V Input High Voltage
Input Low Leakage Current
Input High Leakage Current
3.3V Output Low Voltage
3.3V Output High Voltage
High-impedance Output Current
Input Pin Capacitance
Output Pin Capacitance
Pin Inductance
0.35
V
SS
V
+ 0.5
0.7
– 0.3
V
DD
0.35
1.7
+ 0.5
V
SS
0.7
2.0
– 0.3
V
V
V
V
DD
V
0.8
+ 0.3
V
SS
VIH
2.0
–5
–
V
DD
IIL
Except internal pull-up resistors, 0 < VIN < VDD
Except internal pull-down resistors, 0 < VIN < VDD
IOL = 1 mA
5
5
μA
μA
V
IIH
VOL
–
0.4
–
VOH
IOH = –1 mA
2.4
–10
3
V
IOZ
10
5
μA
pF
pF
nH
V
CIN
COUT
LIN
3
6
–
7
VXIH
Xin High Voltage
0.7V
VDD
DD
VXIL
Xin Low Voltage
0
–
0.3V
V
DD
IDD3.3V
Dynamic Supply Current
In low drive mode per Figure 13 and Figure 15
250
mA
@133 MHz
IPD3.3V
IPD3.3V
Power-down Supply Current
Power-down Supply Current
PD asserted, Outputs Driven
PD asserted, Outputs Tri-state
–
–
30
5
mA
mA
Document #:xxx-xxxxx Rev **
Page 16 of 23
PRELIMINARY
CY28549
AC Electrical Specifications
Parameter
Crystal
TDC
Description
Condition
Min.
Max. Unit
XIN Duty Cycle
The device will operate reliably with input duty
cycles up to 30/70 but the REF clock duty cycle
will not be within specification
47.5
52.5
%
TPERIOD
TR/TF
XIN Period
When XIN is driven from an external clock source 69.841
71.0
10.0
500
300
ns
ns
XIN Rise and Fall Times
XIN Cycle to Cycle Jitter
Long-term Accuracy
Measured between 0.3VDD and 0.7VDD
As an average over 1-μs duration
Measured at crossing point VOX
–
–
–
TCCJ
ps
LACC
ppm
CPU at 0.8V
TDC
CPUT and CPUC Duty Cycle
Measured at crossing point VOX
45
55
%
ns
ns
ns
ns
ns
9.997001 10.00300
7.497751 7.502251
5.998201 6.001801
4.998500 5.001500
9.997001 10.05327
TPERIOD
TPERIOD
TPERIOD
TPERIOD
100-MHz CPUT and CPUC Period Measured at crossing point VOX
133-MHz CPUT and CPUC Period Measured at crossing point VOX
166-MHz CPUT and CPUC Period Measured at crossing point VOX
200-MHz CPUT and CPUC Period Measured at crossing point VOX
TPERIODSS 100-MHz CPUT and CPUC Period, Measured at crossing point VOX
SSC
7.497751 7.539950
5.998201 6.031960
4.998500 5.026634
9.912001 10.08800
7.412751 7.587251
5.913201 6.086801
4.913500 5.086500
9.912001 10.13827
7.412751 7.624950
5.913201 6.116960
TPERIODSS 133-MHz CPUT and CPUC Period, Measured at crossing point VOX
SSC
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TPERIODSS 166-MHz CPUT and CPUC Period, Measured at crossing point VOX
SSC
TPERIODSS 200-MHz CPUT and CPUC Period, Measured at crossing point VOX
SSC
TPERIODAbs 100-MHz CPUT and CPUC Absolute Measured at crossing point VOX
period
TPERIODAbs 133-MHz CPUT and CPUC Absolute Measured at crossing point VOX
period
TPERIODAbs 166-MHz CPUT and CPUC Absolute Measured at crossing point VOX
period
TPERIODAbs 200-MHz CPUT and CPUC Absolute Measured at crossing point VOX
period
TPERI-
ODSSAbs
100-MHz CPUT and CPUC Absolute Measured at crossing point VOX
period, SSC
TPERI-
ODSSAbs
TPERI-
133-MHz CPUT and CPUC Absolute Measured at crossing point VOX
period, SSC
166-MHz CPUT and CPUC Absolute Measured at crossing point VOX
period, SSC
ODSSAbs
4.913500 5.111634
TPERI-
ODSSAbs
200-MHz CPUT and CPUC Absolute Measured at crossing point VOX
period, SSC
ns
[1]
–
–
85
TCCJ
CPUT/C Cycle to Cycle Jitter
CPU2_ITP Cycle to Cycle Jitter
Long-term Accuracy
Measured at crossing point VOX
Measured at crossing point VOX
Measured at crossing point VOX
Measured at crossing point VOX
Measured at crossing point VOX
ps
ps
[1]
125
TCCJ2
LACC
–
300
100
150
700
ppm
ps
TSKEW
TSKEW2
TR/TF
CPU1 to CPU0 Clock Skew
CPU2_ITP to CPU0 Clock Skew
–
–
ps
CPUT and CPUC Rise and Fall Time Measured from VOL = 0.175 to
OH = 0.525V
175
ps
V
TRFM
Rise/Fall Matching
Determined as a fraction of
2*(TR – TF)/(TR + TF)
–
20
%
Document #:xxx-xxxxx Rev **
Page 17 of 23
PRELIMINARY
CY28549
AC Electrical Specifications (continued)
Parameter
Description
Rise Time Variation
Fall Time Variation
Condition
Min.
Max. Unit
ΔTR
–
–
125
125
ps
ps
ΔTF
Note:
1. Measured with one REF on.
VHIGH
VLOW
VOX
Voltage High
Math averages Figure 15
Math averages Figure 15
660
–150
250
–
850
–
mV
mV
mV
V
Voltage Low
Crossing Point Voltage at 0.7V Swing
Maximum Overshoot Voltage
550
VOVS
VHIGH
0.3
+
VUDS
Minimum Undershoot Voltage
Ring Back Voltage
–0.3
–
–
V
V
VRB
See Figure 15. Measure SE
0.2
SRC at 0.8V
TDC
SRCT and SRCC Duty Cycle
Measured at crossing point VOX
45
55
%
ns
ns
9.997001 10.00300
9.997001 10.05327
TPERIOD
100-MHz SRCT and SRCC Period Measured at crossing point VOX
TPERIODSS 100-MHz SRCT and SRCC Period, Measured at crossing point VOX
SSC
9.872001 10.12800
9.872001 10.17827
TPERIODAbs 100-MHz SRCT and SRCC Absolute Measured at crossing point VOX
Period
ns
ns
TPERI-
100-MHz SRCT and SRCC Absolute Measured at crossing point VOX
Period, SSC
ODSSAbs
TSKEW
Any SRCT/C to SRCT/C Clock Skew Measured at crossing point VOX
–
–
250
125[1]
300
ps
ps
TCCJ
LACC
TR/TF
SRCT/C Cycle to Cycle Jitter
SRCT/C Long Term Accuracy
Measured at crossing point VOX
Measured at crossing point VOX
–
ppm
ps
SRCT and SRCC Rise and Fall Time Measured from VOL = 0.175 to
OH = 0.525V
175
800
V
TRFM
Rise/Fall Matching
Determined as a fraction of
2*(TR – TF)/(TR + TF)
–
20
%
ΔTR
Rise TimeVariation
Fall Time Variation
–
–
125
125
15
ps
ps
ns
ΔTF
Tdrive
SRC output enable after PCI_STP#
de-assertion
VHIGH
VLOW
VOX
Voltage High
Math averages Figure 15
Math averages Figure 15
660
–150
180
–
850
–
mV
mV
mV
V
Voltage Low
Crossing Point Voltage at 0.7V Swing
Maximum Overshoot Voltage
550
VOVS
VHIGH
0.3
+
VUDS
VRB
Minimum Undershoot Voltage
Ring Back Voltage
–0.3
–
–
V
V
See Figure 15. Measure SE
0.2
LCD 96_100M_SSC at 0.8V
TDC
SSCT and SSCC Duty Cycle
100-MHz SSCT and SSCC Period
Measured at crossing point VOX
Measured at crossing point VOX
45
55
%
ns
ns
9.997001 10.00300
9.997001 10.05327
TPERIOD
TPERIODSS 100-MHz SSCT and SSCC Period, Measured at crossing point VOX
SSC
9.872001 10.12800
9.872001 10.17827
10.41354 10.41979
TPERIODAbs 100-MHz SSCT and SSCC Absolute Measured at crossing point VOX
Period
ns
ns
ns
TPERI-
ODSSAbs
TPERIOD
100-MHz SRCT and SRCC Absolute Measured at crossing point VOX
Period, SSC
96-MHz SSCT and SSCC Period
Measured at crossing point VOX
Document #:xxx-xxxxx Rev **
Page 18 of 23
PRELIMINARY
CY28549
AC Electrical Specifications (continued)
Parameter
Description
Condition
Measured at crossing point VOX
Min.
Max. Unit
10.41354 10.47215
10.16354 10.66979
10.16354 10.72266
TPERIODSS 96-MHz SSCT and SSCC Period,
SSC
ns
ns
ns
TPERIODAbs 96-MHz SSCT and SSCC Absolute Measured at crossing point VOX
Period
TPERI-
ODSSAbs
TCCJ
96-MHz SRCT and SRCC Absolute Measured at crossing point VOX
Period, SSC
SSCT/C Cycle to Cycle Jitter
SSCT/C Long Term Accuracy
Measured at crossing point VOX
Measured at crossing point VOX
–
–
125
300
700
ps
ppm
ps
LACC
175
TR/TF
SSCT and SSCC Rise and Fall Time Measured from VOL = 0.175 to
OH = 0.525V
V
–
20
TRFM
Rise/Fall Matching
Determined as a fraction of
2*(TR – TF)/(TR + TF)
%
–
–
125
125
850
–
ΔTR
Rise TimeVariation
ps
ps
ΔTF
Fall Time Variation
660
–150
250
–
VHIGH
VLOW
VOX
Voltage High
Math averages Figure 15
Math averages Figure 15
mV
mV
mV
V
Voltage Low
550
Crossing Point Voltage at 0.7V Swing
Maximum Overshoot Voltage
V
+
VOVS
HIGH
0.3
–0.3
–
–
VUDS
VRB
Minimum Undershoot Voltage
Ring Back Voltage
V
V
0.2
See Figure 15. Measure SE
PCI/PCIF at 3.3V
45
55
TDC
PCI Duty Cycle
Spread Disabled PCIF/PCI Period
Measurement at 1.5V
Measurement at 1.5V
Measurement at 1.5V
%
ns
ns
29.99100 30.00900
29.9910 30.15980
TPERIOD
TPERIODSS Spread Enabled PCIF/PCI Period,
SSC
29.49100 30.50900
29.49100 30.65980
TPERIODAbs Spread Disabled PCIF/PCI Period
Measurement at 1.5V
Measurement at 1.5V
ns
ns
TPERI-
ODSSAbs
THIGH
Spread Enabled PCIF/PCI Period,
SSC
12.0
12.0
1.0
–
–
–
PCIF and PCI high time
PCIF and PCI low time
Measurement at 2.4V
Measurement at 0.4V
ns
ns
TLOW
TR/TF
TSKEW
Tdelay
Tdrive
PCIF/PCI rising and falling Edge Rate Measured between 0.8V and 2.0V
Any PCI clock to Any PCI clock Skew Measurement at 1.5V
4.0
1000
200
15
V/ns
ps
Intentional PCI-PCI delay
Measurement at 1.5V
pS
ns
PCI output enable after PCI_STP#
de-assertion
–
–
500
300
TCCJ
LACC
PCIF and PCI Cycle to Cycle Jitter Measurement at 1.5V
PCIF/PCI Long Term Accuracy Measured at crossing point VOX
ps
ppm
DOT96 at 0.8V
45
55
TDC
DOT96T and DOT96C Duty Cycle
DOT96T and DOT96C Period
Measured at crossing point VOX
Measured at crossing point VOX
Measured at crossing point VOX
%
ns
ns
10.41354 10.41979
10.16354 10.66979
TPERIOD
TPERIODAbs DOT96T and DOT96C Absolute
Period
–
–
250
300
900
TCCJ
LACC
TR/TF
DOT96T/C Cycle to Cycle Jitter
DOT96T/C Long Term Accuracy
Measured at crossing point VOX
Measured at crossing point VOX
ps
ppm
ps
175
DOT96T and DOT96C Rise and Fall Measured from VOL = 0.175 to
Time OH = 0.525V
V
Document #:xxx-xxxxx Rev **
Page 19 of 23
PRELIMINARY
CY28549
AC Electrical Specifications (continued)
Parameter
Description
Rise/Fall Matching
Condition
Min.
Max. Unit
TRFM
Determined as a fraction of
2*(TR – TF)/(TR + TF)
–
20
%
ΔTR
Rise Time Variation
–
–
125
125
850
–
ps
ps
ΔTF
Fall Time Variation
660
–150
250
–
VHIGH
VLOW
VOX
Voltage High
Math averages Figure 15
Math averages Figure 15
mV
mV
mV
V
Voltage Low
550
Crossing Point Voltage at 0.7V Swing
Maximum Overshoot Voltage
V
+
VOVS
HIGH
0.3
–0.3
–
–
VUDS
Minimum Undershoot Voltage
Ring Back Voltage
V
V
0.2
VRB
See Figure 15. Measure SE
48_M at 3.3V
TDC
45
55
Duty Cycle
Period
Measurement at 1.5V
%
ns
20.83125 20.83542
20.48125 21.18542
TPERIOD
Measurement at 1.5V
TPERIODAbs Absolute Period
Measurement at 1.5V
ns
8.094
7.694
1.0
–
11.100
11.100
2.0
THIGH
48_M High time
Measurement at 2.4V
ns
TLOW
48_M Low time
Measurement at 0.4V
ns
TR/TF
Rising and Falling Edge Rate
Cycle to Cycle Jitter
48M Long Term Accuracy
Measured between 0.8V and 2.0V
Measurement at 1.5V
V/ns
ps
350
TCCJ
–
100
LACC
Measured at crossing point VOX
ppm
27_M at 3.3V
TDC
Duty Cycle
Measurement at 1.5V
45
27.000
27.000
10.5
10.5
1.0
55
27.0547
27.0547
–
%
TPERIOD
Spread Disabled 27M Period
Spread Enabled 27M Period
27_M High time
Measurement at 1.5V
ns
Measurement at 1.5V
THIGH
Measurement at 2.0V
ns
ns
–
TLOW
27_M Low time
Measurement at 0.8V
4.0
TR/TF
Rising and Falling Edge Rate
Cycle to Cycle Jitter
27_M Long Term Accuracy
Measured between 0.8V and 2.0V
Measurement at 1.5V
V/ns
ps
–
500
TCCJ
–
50
LACC
Measured at crossing point VOX
ppm
REF at 3.3V
TDC
45
55
REF Duty Cycle
REF Period
Measurement at 1.5V
Measurement at 1.5V
Measurement at 1.5V
Measured between 0.8V and 2.0V
Measurement at 1.5V
Measurement at 1.5V
Measurement at 1.5V
%
ns
69.8203 69.8622
68.82033 70.86224
TPERIOD
TPERIODAbs REF Absolute Period
ns
1.0
–
4.0
500
TR/TF
TSKEW
TCCJ
REF Rising and Falling Edge Rate
V/ns
ps
REF Clock to REF Clock
REF Cycle to Cycle Jitter
Long Term Accuracy
–
1000
300
ps
–
LACC
ppm
ENABLE/DISABLE and SET-UP
TSTABLE Clock Stabilization from Power-up
TSS
–
10.0
0
1.8
–
ms
ns
ns
Stopclock Set-up Time
Stopclock Hold Time
TSH
–
Document #:xxx-xxxxx Rev **
Page 20 of 23
PRELIMINARY
CY28549
Test and Measurement Set-up
For Single-ended Signals and Reference
The following diagram shows test load configurations for the
single-ended PCI, USB, and REF output signals.
Measurement
Point
5 pF
33Ω
PCI/
USB
60Ω
Measurement
Point
5 pF
12Ω
12Ω
60Ω
60Ω
REF
Measurement
Point
5 pF
Figure 13.Single-ended Load Configuration Low Drive Option
Measurement
12Ω
Point
60Ω
60Ω
5 pF
Measurement
Point
12Ω
PCI/
USB
5 pF
Measurement
Point
5 pF
12Ω
60Ω
Measurement
Point
5 pF
Measurement
Point
5 pF
12Ω
12Ω
REF
60Ω
60Ω
Figure 14. Single-ended Load Configuration High Drive Option
The following diagram shows the test load configuration for the
differential CPU and SRC outputs.
Figure 15. 0.8V Differential Load Configuration
Document #:xxx-xxxxx Rev **
Page 21 of 23
PRELIMINARY
CY28549
3 .3 V s ig n a ls
T D C
-
-
3.3V
2.0V
1.5V
0.8V
0V
T R
T F
Figure 16. Single-ended Output Signals (for AC Parameters Measurement)
Ordering Information
Part Number
Lead-free
Package Type
Product Flow
CY28549LFXC
CY28549LFXCT
72-pin QFN
Commercial, 0° to 85°C
Commercial, 0° to 85°C
72-pin QFN–Tape and Reel
Package Diagram
72-Lead QFN 10 x 10 mm (Punch Version) LF72A
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2
Purchase of I C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips
2
2
2
I C Patent Rights to use these components in an I C system, provided that the system conforms to the I C Standard Specification
as defined by Philips. Intel and Pentium are registered trademarks of Intel Corporation. All product and company names mentioned
in this document are the trademarks of their respective holders.
Document #:xxx-xxxxx Rev **
Page 22 of 23
PRELIMINARY
CY28549
Document History Page
Document Title: CY28549 Clock Generator for Intel® CK410M
Document Number: xxx-xxxxx
Orig. of
REV.
ECN NO. Issue Date Change
Description of Change
**
New data sheet
Document #:xxx-xxxxx Rev **
Page 23 of 23
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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