CYW150OXC [SILICON]
440BX AGPset Spread Spectrum Frequency Synthesizer;
| 型号： | CYW150OXC |
| 厂家： | 
SILICON |
| 描述： | 440BX AGPset Spread Spectrum Frequency Synthesizer |
| 文件： | 总15页 (文件大小：1140K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CYW150
440BX AGPset Spread Spectrum Frequency Synthesizer
Table 1. Mode Input Table
Features
Mode
Pin 3
PCI_STOP#
REF0
• Maximized electromagnetic interference (EMI)
suppression using Cypress’s Spread Spectrum
technology
• Single-chip system frequency synthesizer for Intel®
440BX AGPset
0
1
Table 2. Pin Selectable Frequency
Input Address
CPU_F, 1:2
PCI_F, 0:5
• Three copies of CPU output
FS3 FS2 FS1 FS0
(MHz)
133.3
124
150
140
105
110
(MHz)
• Seven copies of PCI output
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
33.3 (CPU/4)
31 (CPU/4)
• One 48 MHz output for USB/one 24 MHz for SIO
• Two buffered reference outputs
• Two IOAPIC outputs
37.5 (CPU/4)
35 (CPU/4)
• 17 SDRAM outputs provide support for four DIMMs
• Supports frequencies up to 150 MHz
• SMBus interface for programming
• Power management control inputs
35 (CPU/3)
36.7 (CPU/3)
38.3 (CPU/3)
40 (CPU/3)
115
120
100
133.3
112
33.3 (CPU/3)
44.43 (CPU/3)
37.3 (CPU/3)
34.3 (CPU/3)
33.4 (CPU/2)
41.7 (CPU/2)
37.5 (CPU/2)
41.3 (CPU/3)
Key Specifications
CPU Cycle-to-Cycle Jitter: ..........................................250 ps
CPU to CPU Output Skew: .........................................175 ps
PCI to PCI Output Skew:.............................................500 ps
SDRAMIN to SDRAM0:15 Delay:.......................... 3.7 ns typ.
103
66.8
83.3
75
V
DDQ3:..................................................................... 3.3V±5%
DDQ2:..................................................................... 2.5V±5%
V
124
SDRAM0:15 (leads) to SDRAM_F Skew: ............. 0.4 ns typ.
[1]
Logic Block Diagram
Pin Configuration
VDDQ3
REF0/(PCI_STOP#)
VDDQ3
REF1/FS2
REF0/(PCI_STOP#)
GND
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDDQ2
IOAPIC0
IOAPIC_F
GND
2
REF1/FS2
X1
X2
XTAL
OSC
3
4
PLL Ref Freq
X1
5
CPU_F
CPU1
VDDQ2
CPU2
GND
VDDQ2
X2
6
Stop
Clock
Control
IOAPIC_F
VDDQ3
PCI_F/MODE
PCI0/FS3
GND
7
I/O Pin
Control
8
IOAPIC0
9
CLK_STOP#
SDRAM_F
VDDQ3
SDRAM0
SDRAM1
GND
SDRAM2
SDRAM3
SDRAM4
SDRAM5
VDDQ3
SDRAM6
SDRAM7
GND
CLK_STOP#
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VDDQ2
CPU_F
PCI1
PCI2
Stop
Clock
PCI3
CPU1
CPU2
PCI4
Control
PLL 1
VDDQ3
PCI5
÷2,3,4
SDRAMIN
SDRAM11
SDRAM10
VDDQ3
SDRAM9
SDRAM8
GND
VDDQ3
PCI_F/MODE
PCI0/FS3
PCI1
Stop
Clock
Control
PCI2
PCI3
SDRAM15
SDRAM12
SDRAM13
VDDQ3
24MHz/FS0
48MHz/FS1
25
26
27
28
SDRAM14
SDATA
SCLK
SMBus
Logic
GND
PCI4
SDATA
SCLK
PCI5
VDDQ3
Note:
48MHz/FS1
1. 1.Internal pull-up resistors should not be relied upon for setting I/O pins HIGH. Pin function
with parentheses determined by MODE pin resistor strapping. Unlike other I/O pins, input
FS3 has an internal pull-down resistor.
PLL2
24MHz/FS0
VDDQ3
SDRAM0:15
Stop
Clock
Control
SDRAMIN
16
SDRAM_F
........................ Document #: 38-07177 Rev. *B Page 1 of 14
400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1+(512) 416-9669
www.silabs.com
CYW150
Pin Definitions
Pin
Pin No. Type
Pin Name
Pin Description
CPU1:2
51, 49
O
O
O
CPU Outputs 1 and 2: Frequency is set by the FS0:3 inputs or through serial input interface,
see Table 2 and Table 6. These outputs are affected by the CLK_STOP# input.
CPU_F
PCI1:5
52
Free-Running CPU Output: Frequency is set by the FS0:3 inputs or through serial input
interface, see Table 2 and Table 6. This output is not affected by the CLK_STOP# input.
11,12,13,
14, 16
PCI Outputs 1 through 5: Frequency is set by the FS0:3 inputs or through serial input
interface, see Table 2 and Table 6. These outputs are affected by the PCI_STOP# input.
PCI0/FS3
9
I/O PCI Output/Frequency Select Input: As an output, frequency is set by the FS0:3 inputs or
through serial input interface, see Table 2 and Table 6. This output is affected by the
PCI_STOP# input. When an input, latches data selecting the frequency of the CPU and PCI outputs.
PCI_F/MODE
CLK_STOP#
8
I/O Free Running PCI Output: Frequency is set by the FS0:3 inputs or through serial input
interface, see Table 2 and Table 6. This output is not affected by the PCI_STOP# input. When
an input, selects function of pin 3 as described in Table 1.
47
I
CLK_STOP# Input: When brought LOW, affected outputs are stopped LOW after completing
a full clock cycle (2–3 CPU clock latency). When brought HIGH, affected outputs start
beginning with a full clock cycle (2–3 CPU clock latency).
IOAPIC_F
IOAPIC0
54
55
29
O
O
Free-running IOAPIC Output: This output is a buffered version of the reference input which
is not affected by the CPU_STOP# logic input. Its swing is set by voltage applied to VDDQ2.
IOAPIC Output: Provides 14.318 MHz fixed frequency. The output voltage swing is set by
voltage applied to VDDQ2. This output is disabled when CLK_STOP# is set LOW.
48MHz/FS1
I/O 48 MHz Output: 48 MHz is provided in normal operation. In standard systems, this output can
be used as the reference for the Universal Serial Bus. Upon power up, FS1 input will be
latched, setting output frequencies as described in Table 2.
24MHz/FS0
REF1/FS2
30
I/O 24 MHz Output: 24 MHz is provided in normal operation. In standard systems, this output can
be used as the clock input for a Super I/O chip. Upon power up, FS0 input will be latched,
setting output frequencies as described in Table 2.
2
3
I/O Reference Output: 14.318 MHz is provided in normal operation. Upon power-up, FS2 input
will be latched, setting output frequencies as described in Table 2.
REF0
(PCI_STOP#)
I/O Fixed 14.318 MHz Output 0 or PCI_STOP# Pin: Function determined by MODE pin. The
PCI_STOP# input enables the PCI 0:5 outputs when HIGH and causes them to remain at logic
0 when LOW. The PCI_STOP signal is latched on the rising edge of PCI_F. Its effects take
place on the next PCI_F clock cycle. As an output, this pin provides a fixed clock signal equal
in frequency to the reference signal provided at the X1/X2 pins (14.318 MHz).
SDRAMIN
17
I
Buffered Input Pin: The signal provided to this input pin is buffered to 17 outputs
(SDRAM0:15, SDRAM_F).
SDRAM0:15
44, 43,
41, 40,
39, 38,
36, 35,
22, 21,
19, 18,
33, 32,
25, 24
O
Buffered Outputs: These sixteen dedicated outputs provide copies of the signal provided at
the SDRAMIN input. The swing is set by VDDQ3, and they are deactivated when CLK_STOP#
input is set LOW.
SDRAM_F
46
O
I
Free-Running Buffered Output: This output provides a single copy of the SDRAMIN input.
The swing is set by VDDQ3; this signal is unaffected by the CLK_STOP# input.
SCLK
SDATA
X1
28
27
5
Clock pin for SMBus circuitry.
I/O Data pin for SMBus circuitry.
I
Crystal Connection or External Reference Frequency Input: This pin has dual functions.
It can be used as an external 14.318 MHz crystal connection or as an external reference
frequency input.
X2
6
I
Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an
external reference, this pin must be left unconnected.
VDDQ3
1, 7, 15,
20, 31,
37, 45
P
Power Connection: Power supply for core logic, PLL circuitry, SDRAM output buffers, PCI
output buffers, reference output buffers, and 48 MHz/24 MHz output buffers. Connect to 3.3V.
........................Document #: 38-07177 Rev. *B Page 2 of 14
CYW150
Pin Definitions (continued)
Pin
Pin Name
VDDQ2
Pin No. Type
Pin Description
50, 56
P
Power Connection: Power supply for IOAPIC and CPU output buffers. Connect to 2.5V or
3.3V.
GND
4, 10, 23,
26, 34,
G
Ground Connections: Connect all ground pins to the common system ground plane.
42, 48, 53
resistor on the l/O pins to pull the pins and their associated
capacitive clock load to either a logic HIGH or LOW state. At
Overview
The CYW150 was designed as a single-chip alternative to the
standard two-chip Intel 440BX AGPset clock solution. It
provides sufficient outputs to support most single-processor,
four SDRAM DIMM designs.
the end of the 2-ms period, the established logic “0” or “1”
condition of the l/O pin is latched. Next the output buffer is
enabled, converting the l/O pins into operating clock outputs.
The 2-ms timer starts when VDD reaches 2.0V. The input bits
can only be reset by turning VDD off and then back on again.
Functional Description
It should be noted that the strapping resistors have no signif-
icant effect on clock output signal integrity. The drive
impedance of clock output (< 40, nominal) is minimally
affected by the 10-k strap to ground or VDD. As with the
series termination resistor, the output strapping resistor should
be placed as close to the l/O pin as possible in order to keep
the interconnecting trace short. The trace from the resistor to
ground or VDD should be kept less than two inches in length
to minimize system noise coupling during input logic sampling.
I/O Pin Operation
Pins 2, 8, 9, 29, and 30 are dual-purpose l/O pins. Upon
power-up these pins act as logic inputs, allowing the determi-
nation of assigned device functions. A short time after
power-up, the logic state of each pin is latched and the pins
become clock outputs. This feature reduces device pin count
by combining clock outputs with input select pins.
An external 10-k “strapping” resistor is connected between
the l/O pin and ground or VDD. Connection to ground sets a
latch to “0,” connection to VDD sets a latch to “1.” Figure 1 and
Figure 2 show two suggested methods for strapping resistor
connections.
When the clock outputs are enabled following the 2-ms input
period, the corresponding specified output frequency is
delivered on the pins, assuming that VDD has stabilized. If VDD
has not yet reached full value, output frequency initially may
be below target but will increase to target once VDD voltage
has stabilized. In either case, a short output clock cycle may
be produced from the CPU clock outputs when the outputs are
enabled.
Upon CYW150 power-up, the first 2 ms of operation are used
for input logic selection. During this period, the five I/O pins (2,
8, 9, 29, 30) are three-stated, allowing the output strapping
V
DD
Output Strapping Resistor
Series Termination Resistor
10 k
(Load Option 1)
Clock Load
CYW150
Output
Buffer
Power-on
Reset
Timer
Hold
Output
Low
Output Three-state
10 k
(Load Option 0)
Q
D
Data
Latch
Figure 1. Input Logic Selection Through Resistor Load Option
........................Document #: 38-07177 Rev. *B Page 3 of 14
CYW150
Jumper Options
Output Strapping Resistor
Series Termination Resistor
VDD
10 k
Clock Load
CYW150
R
Output
Buffer
Power-on
Reset
Timer
Resistor Value R
Hold
Output
Low
Output Three-state
Q
D
Data
Latch
Figure 2. Input Logic Selection Through Jumper Option
Where P is the percentage of deviation and F is the frequency
in MHz where the reduction is measured.
Spread Spectrum Generator
The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occupies. By increasing
the bandwidth of the fundamental and its harmonics, the ampli-
tudes of the radiated electromagnetic emissions are reduced.
This effect is depicted in Figure 3.
The output clock is modulated with a waveform depicted in
Figure 4. This waveform, as discussed in “Spread Spectrum
Clock Generation for the Reduction of Radiated Emissions” by
Bush, Fessler, and Hardin produces the maximum reduction
in the amplitude of radiated electromagnetic emissions. The
deviation selected for this chip is specified in Table 6. Figure 4
details the Cypress spreading pattern. Cypress does offer
options with more spread and greater EMI reduction. Contact
your local Sales representative for details on these devices.
As shown in Figure 3, a harmonic of a modulated clock has a
much lower amplitude than that of an unmodulated signal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction is
Spread Spectrum clocking is activated or deactivated by
selecting the appropriate values for bits 1–0 in data byte 0 of
the SMBus data stream. Refer to Table 7 for more details.
dB = 6.5 + 9*log10(P) + 9*log10(F)
5 dB/div
SSFTG
Typical Clock
–1.0
0
+1.0
+0.5%
+SS%
–0.5%
–SS%
Frequency Span (MHz)
Figure 3. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
........................Document #: 38-07177 Rev. *B Page 4 of 14
CYW150
MAX
MIN
Figure 4. Typical Modulation Profile
outputs of the chipset. If needed, clock device register
changes are normally made upon system initialization. The
interface can also be used during system operation for power
management functions. Table 3 summarizes the control
functions of the serial data interface.
Serial Data Interface
The CYW150 features a two-pin, serial data interface that can
be used to configure internal register settings that control
particular device functions. Upon power-up, the CYW150
initializes with default register settings, therefore the use of this
serial data interface is optional. The serial interface is
write-only (to the clock chip) and is the dedicated function of
device pins SDATA and SCLOCK. In motherboard applica-
tions, SDATA and SCLOCK are typically driven by two logic
Operation
Data is written to the CYW150 in eleven bytes of eight bits
each. Bytes are written in the order shown in Table 4.
Table 3. Serial Data Interface Control Functions Summary
Control Function
Description
Common Application
Clock Output Disable Any individual clock output(s) can be disabled.
Disabled outputs are actively held LOW.
Unused outputs are disabled to reduce EMI and
system power. Examples are clock outputs to
unused PCI slots.
CPU Clock
Provides CPU/PCI frequency selections through
For alternate microprocessors and power
management options. Smooth frequency transition
allowsCPUfrequencychangeundernormalsystem
operation.
Frequency Selection software. Frequency is changed in a smooth and
controlled fashion.
Spread Spectrum
Enabling
Enables or disables spread spectrum clocking.
Puts clock output into a high-impedance state.
For EMI reduction.
Output Three-state
Test Mode
Production PCB testing.
Production PCB testing.
All clock outputs toggle in relation to X1 input,
internal PLL is bypassed. Refer to Table 5.
(Reserved)
Reserved function for future device revision or
production device testing.
No user application. Register bit must be written as
0.
Table 4. Byte Writing Sequence
Byte
Sequence Byte Name Bit Sequence
Byte Description
1
2
3
Slave Address 11010010
Commands the CYW150 to accept the bits in Data Bytes 0–7 for internal register
configuration. Since other devices may exist on the same common serial data bus,
it is necessary to have a specific slave address for each potential receiver. The
slave receiver address for the CYW150 is 11010010. Register setting will not be
made if the Slave Address is not correct (or is for an alternate slave receiver).
Command
Code
Don’t Care
Don’t Care
Unused by the CYW150, therefore bit values are ignored (“Don’t Care”). This byte
must be included in the data write sequence to maintain proper byte allocation. The
Command Code Byte is part of the standard serial communication protocol and
may be used when writing to another addressed slave receiver on the serial data
bus.
Byte Count
Unused by the CYW150, therefore bit values are ignored (“Don’t Care”). This byte
must be included in the data write sequence to maintain proper byte allocation. The
Byte Count Byte is part of the standard serial communication protocol and may be
used when writing to another addressed slave receiver on the serial data bus.
........................Document #: 38-07177 Rev. *B Page 5 of 14
CYW150
Table 4. Byte Writing Sequence (continued)
Byte
Sequence Byte Name Bit Sequence
Byte Description
4
5
Data Byte 0
Data Byte 1
Data Byte 2
Data Byte 3
Data Byte 4
Data Byte 5
Data Byte 6
Data Byte 7
Refer to Table 5 The data bits in Data Bytes 0–5 set internal CYW150 registers that control device
operation. The data bits are only accepted when the Address Byte bit sequence is
11010010, as noted above. For description of bit control functions, refer to Table 5,
Data Byte Serial Configuration Map.
6
7
8
9
10
11
Don’t Care
Unused by the CYW150, therefore bit values are ignored (Don’t Care).
Writing Data Bytes
Table 5 gives the bit formats for registers located in Data Bytes
0–7.
Each bit in Data Bytes 0–7 control a particular device function
except for the “reserved” bits which must be written as a logic
0. Bits are written MSB (most significant bit) first, which is bit 7.
Table 6 details additional frequency selections that are
available through the serial data interface.
Table 7 details the select functions for Byte 0, bits 1 and 0.
Table 5. Data Bytes 0–5 Serial Configuration Map
Affected Pin
Bit Control
Bit(s)
Pin No.
Pin Name
Control Function
0
1
Default
Data Byte 0
7
6
5
4
3
–
–
–
–
–
–
–
–
–
–
(Reserved)
–
–
0
0
0
0
0
SEL_2
See Table 6
See Table 6
See Table 6
SEL_1
SEL_0
Frequency Table Selection
Frequency
Controlled by FS
(3:0) Table 2
Frequency
Controlled by SEL
(3:0) Table 6
2
–
–
–
–
SEL3
Refer to Table 6
0
1–0
Bit 1
Bit 0
Function (See Table 7 for function details)
Normal Operation
00
0
0
1
1
0
1
0
1
(Reserved)
Spread Spectrum On
All Outputs Three-stated
Data Byte 1
7
6
5
4
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
0
0
0
1
1
1
1
–
–
–
–
3
2
1
0
46
49
51
52
SDRAM_F
CPU2
CPU1
CPU_F
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Low
Low
Low
Low
Active
Active
Active
Active
Data Byte 2
7
6
–
8
–
(Reserved)
–
–
0
1
1
PCI_F
PCI5
Clock Output Disable
Clock Output Disable
Low
Low
Active
Active
5
16
........................Document #: 38-07177 Rev. *B Page 6 of 14
CYW150
Table 5. Data Bytes 0–5 Serial Configuration Map (continued)
Affected Pin
Bit Control
Bit(s)
Pin No.
Pin Name
PCI4
Control Function
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
0
1
Default
4
3
2
1
0
14
13
12
11
9
Low
Low
Low
Low
Low
Active
Active
Active
Active
Active
1
1
1
1
1
PCI3
PCI2
PCI1
PCI0
Data Byte 3
7
6
–
–
–
(Reserved)
–
–
0
0
1
1
1
–
(Reserved)
–
–
5
4
3
29
30
48MHz
24MHz
Clock Output Disable
Clock Output Disable
Low
Low
Low
Active
Active
Active
33, 32, SDRAM12:15 Clock Output Disable
25, 24
2
1
0
22, 21,
19, 18
SDRAM8:11 Clock Output Disable
SDRAM4:7 Clock Output Disable
SDRAM0:3 Clock Output Disable
Low
Low
Low
Active
Active
Active
1
1
1
39, 38,
36, 35
44, 43,
41, 40
Data Byte 4
7
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
Data Byte 5
7
6
–
–
–
(Reserved)
–
–
–
–
0
0
1
1
0
0
1
1
–
IOAPIC_F
IOAPICO
–
(Reserved)
5
4
3
2
1
0
54
55
–
Disabled
Low
Low
–
Active
Active
–
Disabled
(Reserved)
–
–
(Reserved)
–
–
2
REF1
REF0
Clock Output Disable
Clock Output Disable
Low
Low
Active
Active
3
........................Document #: 38-07177 Rev. *B Page 7 of 14
CYW150
Table 6. Frequency Selections through Serial Data Interface Data Bytes
Input Conditions
Output Frequency
Spread On
Data Byte 0, Bit 3 = 1
Bit 2
Bit 6
Bit 5
Bit 4
CPU, SDRAM
Clocks (MHz)
PCI Clocks
(MHz)
SEL_3
SEL_2
SEL_1
SEL_0
Spread Percentage
± 0.5% Center
± 0.5% Center
± 0.5% Center
± 0.5% Center
± 0.5% Center
± 0.9% Center
± 0.5% Center
± 0.5% Center
± 0.5% Center
± 0.5% Center
± 0.5% Center
± 0.5% Center
± 0.5% Center
± 0.9% Center
± 0.5% Center
± 0.5% Center
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
133.3
124
150
140
105
110
33.3 (CPU/4)
31 (CPU/4)
37.5 (CPU/4)
35 (CPU/4)
35 (CPU/3)
36.7 (CPU/3)
38.3 (CPU/3)
40 (CPU/3)
115
120
100
133.3
112
33.3 (CPU/3)
44.43 (CPU/3)
37.3 (CPU/3)
34.3 (CPU/3)
33.4 (CPU/2)
41.7 (CPU/2)
37.5 (CPU/2)
41.3 (CPU/3)
103
66.8
83.3
75
124
Table 7. Select Function for Data Byte 0, Bits 0:1
Input Conditions
Data Byte 0
Output Conditions
REF0:1, IO-
Function
Normal Operation
Test Mode
Bit 1
Bit 0
CPU_F, 1:2 PCI_F, PCI0:5
APIC0,_F
14.318 MHz
X1
48 MHZ
24 MHZ
24 MHz
X1/4
0
0
1
1
0
1
0
1
Note 2
X1/2
Note 2
CPU/(2 or 3)
Note 2
48 MHz
X1/2
Spread Spectrum
Tristate
Note 2
Hi-Z
14.318 MHz
Hi-Z
48 MHz
Hi-Z
24 MHz
Hi-Z
Hi-Z
Note:
2. CPU and PCI frequency selections are listed in Table 2 and Table 6.
........................Document #: 38-07177 Rev. *B Page 8 of 14
CYW150
Absolute Maximum Ratings[3]
Stresses greater than those listed in this table may cause
permanent damage to the device. These represent a stress
rating only. Operation of the device at these or any other condi-
tions above those specified in the operating sections of this
specification is not implied. Maximum conditions for extended
periods may affect reliability.
Parameter
DD, VIN
Description
Voltage on any pin with respect to GND
Storage Temperature
Rating
–0.5 to +7.0
–65 to +150
–55 to +125
0 to +70
Unit
V
V
TSTG
TB
°C
°C
°C
kV
Ambient Temperature under Bias
Operating Temperature
TA
ESDPROT
Input ESD Protection
2 (min)
DC Electrical Characteristics (TA = 0°C to +70°C; VDDQ3 = 3.3V ±5%; VDDQ2 = 2.5V ±5%)
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
Supply Current
IDD
IDD
Logic Inputs
3.3V Supply Current
CPU_F, 1:2= 100 MHz
Outputs Loaded[4]
320
40
mA
mA
2.5V Supply Current
CPU_F, 1:2= 100 MHz
Outputs Loaded[4]
VIL
VIH
IIL
Input Low Voltage
GND – 0.3
2.0
0.8
VDD + 0.3
–25
V
Input High Voltage
Input Low Current[5]
Input High Current[5]
V
A
A
µA
µA
IIH
IIL
10
Input Low Current (SEL100/66#)
Input High Current (SEL100/66#)
–5
IIH
+5
Clock Outputs
VOL
VOH
VOH
IOL
Output Low Voltage
Output High Voltage
IOL = 1 mA
IOH = 1 mA
50
mV
V
3.1
2.2
60
96
72
61
60
60
95
43
76
60
50
50
50
75
Output High Voltage CPU_F, 1:2, IOAPIC IOH = –1 mA
V
Output Low Current CPU_F, 1:2
PCI_F, PCI1:5
VOL = 1.25V
OL = 1.5V
73
110
92
71
70
70
110
60
96
90
60
60
60
95
85
130
110
80
mA
mA
mA
mA
mA
mA
V
IOAPIC0, IOAPIC_F VOL = 1.25V
REF0:1
VOL = 1.5V
48-MHz
VOL = 1.5V
80
24-MHz
V
OL = 1.5V
OL = 1.5V
80
SDRAM0:15, _F
V
130
80
IOH
Output High Current CPU_F, 1:2
VOH = 1.25V
mA
mA
mA
mA
mA
mA
PCI_F, PCI1:5
IOAPIC
VOH = 1.5V
VOH = 1.25V
VOH = 1.5V
VOH = 1.5V
VOH = 1.5V
VOH = 1.5V
120
130
72
REF0:1
48-MHz
72
24-MHz
72
SDRAM0:15, _F
120
Notes:
3. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
4. All clock outputs loaded with 6" 60 traces with 22-pF capacitors.
5. CYW150 logic inputs have internal pull-up devices (not to full CMOS level). Logic input FS3 has an internal pull-down device.
........................Document #: 38-07177 Rev. *B Page 9 of 14
CYW150
DC Electrical Characteristics (TA = 0°C to +70°C; VDDQ3 = 3.3V ±5%; VDDQ2 = 2.5V ±5%) (continued)
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
Crystal Oscillator
VTH
X1 Input threshold Voltage[6]
VDDQ3 = 3.3V
1.65
14
V
CLOAD
Load Capacitance, Imposed on
External Crystal[7]
pF
CIN,X1
X1 Input Capacitance[8]
Pin X2 unconnected
Except X1 and X2
28
pF
Pin Capacitance/Inductance
CIN
Input Pin Capacitance
Output Pin Capacitance
Input Pin Inductance
5
6
7
pF
pF
nH
COUT
LIN
AC Electrical Characteristics
TA = 0°C to +70°C; VDDQ3 = 3.3V±5%; VDDQ2 = 2.5V±5%; fXTL
= 14.31818 MHz. AC clock parameters are tested and
guaranteed over stated operating conditions using the stated
lump capacitive load at the clock output; Spread Spectrum
clocking is disabled.
CPU Clock Outputs, CPU_F, 1:2 (Lump Capacitance Test Load = 20 pF)
CPU = 66.8 MHz
CPU = 100 MHz
Parameter
tP
Description
Period
Test Condition/Comments
Measured on rising edge at 1.25
Duration of clock cycle above 2.0V
Duration of clock cycle below 0.4V
Min. Typ. Max. Min. Typ. Max. Unit
15
5.2
5.0
1
15.5
10
3.0
2.8
1
10.5
ns
ns
tH
tL
High Time
Low Time
ns
tR
tF
tD
Output Rise Edge Rate Measured from 0.4V to 2.0V
Output Fall Edge Rate Measured from 2.0V to 0.4V
4
4
4
4
V/ns
V/ns
%
1
1
Duty Cycle
Measured on rising and falling edge at
45
55
45
55
1.25V
tJC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.25V.
Maximum difference of cycle time
between two adjacent cycles.
250
250
ps
tSK
fST
Output Skew
Measured on rising edge at 1.25V
175
3
175
3
ps
Frequency Stabilization Assumes full supply voltage reached
from Power-up (cold
start)
ms
within 1 ms from power-up. Short cycles
exist prior to frequency stabilization.
Zo
AC Output Impedance Average value during switching
transition. Used for determining series
termination value.
20
20
PCI Clock Outputs, PCI_F and PCI0:5 (Lump Capacitance Test Load = 30 pF)
CPU = 66.6/100 MHz
Min. Typ. Max.
30
Parameter
tP
Description
Test Condition/Comments
Measured on rising edge at 1.5V
Duration of clock cycle above 2.4V
Duration of clock cycle below 0.4V
Measured from 0.4V to 2.4V
Unit
Period
ns
ns
tH
tL
High Time
12.0
12.0
1
Low Time
ns
tR
Output Rise Edge Rate
4
V/ns
Notes:
6. X1 input threshold voltage (typical) is V
/2.
DDQ3
7. The CYW150 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is
14 pF; this includes typical stray capacitance of short PCB traces to crystal.
8. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
1
4
V/ns
......................Document #: 38-07177 Rev. *B Page 10 of 14
CYW150
PCI Clock Outputs, PCI_F and PCI0:5 (Lump Capacitance Test Load = 30 pF) (continued)
CPU = 66.6/100 MHz
Parameter
tD
Description
Duty Cycle
Test Condition/Comments
Min.
Typ.
Max.
55
Unit
%
Measured on rising and falling edge at 1.5V
45
tJC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maximum
difference of cycle time between two
adjacent cycles.
250
ps
tSK
tO
Output Skew
Measured on rising edge at 1.5V
500
4
ps
ns
CPU to PCI Clock Skew
Covers all CPU/PCI outputs. Measured on
rising edge at 1.5V. CPU leads PCI output.
1.5
fST
Frequency Stabilization
from Power-up (cold start) 1 ms from power-up. Short cycles exist prior
to frequency stabilization.
Assumes full supply voltage reached within
3
ms
Zo
AC Output Impedance
Average value during switching transition.
Used for determining series termination
value.
15
IOAPIC0 and IOAPIC_F Clock Outputs (Lump Capacitance Test Load = 20 pF)
CPU = 66.6/100 MHz
Parameter
Description
Frequency, Actual
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Test Condition/Comments
Frequency generated by crystal oscillator
Measured from 0.4V to 2.0V
Min.
Typ.
Max.
Unit
MHz
V/ns
V/ns
%
f
14.31818
tR
1
1
4
4
tF
Measured from 2.0V to 0.4V
tD
Measured on rising and falling edge at 1.25V
45
55
1.5
fST
Frequency Stabilization
Assumes full supply voltage reached within
ms
from Power-up (cold start) 1 ms from power-up. Short cycles exist prior to
frequency stabilization.
Zo
AC Output Impedance
Average value during switching transition.
Used for determining series termination value.
15
REF0:1 Clock Outputs (Lump Capacitance Test Load = 20 pF)
CPU = 66.6/100 MHz
Parameter
Description
Test Condition/Comments
Min.
Typ. Max.
Unit
MHz
V/ns
V/ns
%
f
Frequency, Actual
Frequency generated by crystal oscillator
14.318
tR
Output Rise Edge Rate Measured from 0.4V to 2.4V
Output Fall Edge Rate Measured from 2.4V to 0.4V
0.5
0.5
45
2
2
tF
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
55
3
fST
Frequency Stabilization Assumes full supply voltage reached within 1 ms from
ms
from Power-up (cold
start)
power-up. Short cycles exist prior to frequency stabili-
zation.
Zo
AC Output Impedance Average value during switching transition. Used for
determining series termination value.
25
SDRAM 0:15, _F Clock Outputs (Lump Capacitance Test Load = 30 pF)
CPU = 66.8 MHz
CPU = 100 MHz
Parameter
Description
Period
Test Condition/Comments
Measured on rising edge at 1.5V
Duration of clock cycle above 2.4V
Duration of clock cycle below 0.4V
Min. Typ. Max. Min. Typ. Max. Unit
t
15
5.2
5.0
1
15.5
10
3.0
2.0
1
10.5
ns
ns
P
tH
High Time
Low Time
tL
tR
tF
ns
Output Rise Edge Rate Measured from 0.4V to 2.4V
Output Fall Edge Rate Measured from 2.4V to 0.4V
4
4
4
4
V/ns
V/ns
1
1
...................... Document #: 38-07177 Rev. *B Page 11 of 14
CYW150
SDRAM 0:15, _F Clock Outputs (Lump Capacitance Test Load = 30 pF) (continued)
CPU = 66.8 MHz
Min. Typ. Max. Min. Typ. Max. Unit
CPU = 100 MHz
Parameter
tD
Description
Duty Cycle
Test Condition/Comments
Measured on rising and falling edge at
1.5V
45
55
45
55
%
tSK
Output Skew
Measured on rising and falling edge at
1.5V
250
250
ps
tPD
Zo
Propagation Delay
Measured from SDRAMIN
3.7
15
3.7
15
ns
AC Output Impedance Average value during switching
transition. Used for determining series
termination value.
48-MHz Clock Output (Lump Capacitance Test Load = 20 pF)
CPU = 66.8/100 MHz
Min. Typ. Max. Unit
Parameter
Description
Test Condition/Comments
Determined by PLL divider ratio (see m/n below)
f
Frequency, Actual
48.008
+167
MHz
ppm
fD
Deviation from 48 MHz (48.008 – 48)/48
m/n
tR
PLL Ratio
(14.31818 MHz x 57/17 = 48.008 MHz)
57/17
Output Rise Edge Rate Measured from 0.4V to 2.4V
0.5
0.5
45
2
2
V/ns
V/ns
%
tF
Output Fall Edge Rate
Duty Cycle
Measured from 2.4V to 0.4V
tD
Measured on rising and falling edge at 1.5V
55
3
fST
Frequency Stabilization Assumes full supply voltage reached within 1 ms from
ms
from Power-up (cold
start)
power-up. Short cycles exist prior to frequency stabili-
zation.
Zo
AC Output Impedance
Average value during switching transition. Used for deter-
mining series termination value.
25
24-MHz Clock Output (Lump Capacitance Test Load = 20 pF
CPU = 66.8/100 MHz
Parameter
Description
Test Condition/Comments
Min.
Typ.
24.004
+167
Max.
Unit
MHz
ppm
f
Frequency, Actual
Determined by PLL divider ratio (see m/n below)
fD
Deviation from 24 MHz (24.004 – 24)/24
m/n
tR
PLL Ratio
(14.31818 MHz x 57/34 = 24.004 MHz)
57/34
Output Rise Edge Rate Measured from 0.4V to 2.4V
Output Fall Edge Rate Measured from 2.4V to 0.4V
0.5
0.5
45
2
2
V/ns
V/ns
%
tF
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
55
3
fST
Frequency Stabilization Assumes full supply voltage reached within 1 ms from
ms
from Power-up (cold
start)
power-up. Short cycles exist prior to frequency stabili-
zation.
Zo
AC Output Impedance Average value during switching transition. Used for
determining series termination value.
25
Layout Example
......................Document #: 38-07177 Rev. *B Page 12 of 14
CYW150
+2.5V Supply
FB
+3.3V Supply
FB
VDDQ2
VDDQ3
10 mF
0.005 mf
10 mF
0.005 mF
C1
C2
C3
C4
G
G
G
G
V
G
G
V
1
56
55
54
53
G
G
2
3
4
G
G
G
5
52
G
6
51
50
49
48
47
46
45
G
V
V
G
7
G
G
8
G
G
9
G
10
11
12
V
G
G
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
G
G
V
G
G
G
G
G
V
V
G
G
G
G
G
G
V
G
G
G
G
FB = Dale ILB1206 - 300 (300@ 100 MHz)
C2 & C4 = 0.005
µF
µF
Cermaic CapsC1 & C3 = 10 – 22
= VIA to GND plane layer
V =VIA to respective supply plane layer
G
Note: Each supply plane or strip should have a ferrite bead and capacitors
All bypass caps = 0.1F ceramic
......................Document #: 38-07177 Rev. *B Page 13 of 14
CYW150
Ordering Information
Ordering Code
Package Type
56-pin SSOP
56-pin SSOP – Tape and Reel
Industrial Product Flow
Commercial, 0 to 70°C
Commercial, 0 to 70°C
CYW150OXC
CYW150OXCT
Package Drawing and Dimensions
56-Lead Shrunk Small Outline Package O56
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Sil-
icon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the
use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or
parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, repre-
sentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
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sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized appli-
cation, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
......................Document #: 38-07177 Rev. *B Page 14 of 14
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