EFM32WG230F256-QFN64 [SILICON]
Updated specifications based on the results of additional silicon characterization;
| 型号： | EFM32WG230F256-QFN64 |
| 厂家： | 
SILICON |
| 描述： | Updated specifications based on the results of additional silicon characterization 时钟 外围集成电路 |
| 文件： | 总75页 (文件大小：2043K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EFM32WG232 DATASHEET
F256/F128/F64
• ARM Cortex-M4 CPU platform
• Communication interfaces
• High Performance 32-bit processor @ up to 48 MHz
• DSP instruction support and floating-point unit
• Memory Protection Unit
• Flexible Energy Management System
• 20 nA @ 3 V Shutoff Mode
• 0.4 µA @ 3 V Shutoff Mode with RTC
• 0.65 µA @ 3 V Stop Mode, including Power-on Reset, Brown-out
Detector, RAM and CPU retention
• 0.95 µA @ 3 V Deep Sleep Mode, including RTC with 32.768 kHz
oscillator, Power-on Reset, Brown-out Detector, RAM and CPU
retention
• 3× Universal Synchronous/Asynchronous Receiv-
er/Transmitter
• UART/SPI/SmartCard (ISO 7816)/IrDA/I2S
• 2× Low Energy UART
• Autonomous operation with DMA in Deep Sleep
Mode
• 2× I2C Interface with SMBus support
• Address recognition in Stop Mode
• Ultra low power precision analog peripherals
• 12-bit 1 Msamples/s Analog to Digital Converter
• 8 single ended channels/4 differential channels
• On-chip temperature sensor
• 63 µA/MHz @ 3 V Sleep Mode
• 225 µA/MHz @ 3 V Run Mode, with code executed from flash
• 256/128/64 KB Flash
• 12-bit 500 ksamples/s Digital to Analog Converter
• 2× Analog Comparator
• 32 KB RAM
• 53 General Purpose I/O pins
• Capacitive sensing with up to 16 inputs
• 3× Operational Amplifier
• Configurable push-pull, open-drain, pull-up/down, input filter, drive
strength
• 6.1 MHz GBW, Rail-to-rail, Programmable Gain
• Supply Voltage Comparator
• Configurable peripheral I/O locations
• 16 asynchronous external interrupts
• Output state retention and wake-up from Shutoff Mode
• 12 Channel DMA Controller
• Low Energy Sensor Interface (LESENSE)
• Autonomous sensor monitoring in Deep Sleep Mode
• Wide range of sensors supported, including LC sen-
sors and capacitive buttons
• 12 Channel Peripheral Reflex System (PRS) for autonomous in-
ter-peripheral signaling
• Ultra efficient Power-on Reset and Brown-Out Detec-
tor
• Hardware AES with 128/256-bit keys in 54/75 cycles
• Timers/Counters
• 4× 16-bit Timer/Counter
• Debug Interface
• 2-pin Serial Wire Debug interface
• 1-pin Serial Wire Viewer
• 4×3 Compare/Capture/PWM channels
• Dead-Time Insertion on TIMER0
• 16-bit Low Energy Timer
• 1× 24-bit Real-Time Counter and 1× 32-bit Real-Time Counter
• 3× 16/8-bit Pulse Counter
• Embedded Trace Module v3.5 (ETM)
• Pre-Programmed UART Bootloader
• Temperature range -40 to 85 ºC
• Single power supply 1.98 to 3.8 V
• TQFP64 package
• Watchdog Timer with dedicated RC oscillator @ 50 nA
• Backup Power Domain
• RTC and retention registers in a separate power domain, avail-
able in all energy modes
• Operation from backup battery when main power drains out
32-bit ARM Cortex-M0+, Cortex-M3 and Cortex-M4 microcontrollers for:
• Energy, gas, water and smart metering
• Health and fitness applications
• Smart accessories
• Alarm and security systems
• Industrial and home automation
...the world's most energy friendly microcontrollers
1 Ordering Information
Table 1.1 (p. 2) shows the available EFM32WG232 devices.
Table 1.1. Ordering Information
Ordering Code
Flash (kB) RAM (kB)
Max
Speed
(MHz)
Supply
Voltage
(V)
Temperature
(ºC)
Package
EFM32WG232F64-QFP64
EFM32WG232F128-QFP64
EFM32WG232F256-QFP64
64
32
32
32
48
48
48
1.98 - 3.8
1.98 - 3.8
1.98 - 3.8
-40 - 85
-40 - 85
-40 - 85
TQFP64
TQFP64
TQFP64
128
256
Visit www.silabs.com for information on global distributors and representatives.
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2 System Summary
2.1 System Introduction
The EFM32 MCUs are the world’s most energy friendly microcontrollers. With a unique combination of
the powerful 32-bit ARM Cortex-M4, with DSP instruction support and floating-point unit, innovative low
energy techniques, short wake-up time from energy saving modes, and a wide selection of peripherals,
the EFM32WG microcontroller is well suited for any battery operated application as well as other systems
requiring high performance and low-energy consumption. This section gives a short introduction to each
of the modules in general terms and also shows a summary of the configuration for the EFM32WG232
devices. For a complete feature set and in-depth information on the modules, the reader is referred to
the EFM32WG Reference Manual.
A block diagram of the EFM32WG232 is shown in Figure 2.1 (p. 3) .
Figure 2.1. Block Diagram
WG232F64/ 128/ 256
Core and Memory
Clock Management
Energy Management
Aux High Freq.
RC
Oscillator
High Freq.
RC
Oscillator
Voltage
Comparator
Voltage
Regulator
Memory
Protection
Unit
ARM Cortex™M4 processor
with DSP extensions and FPU
Low Freq.
RC
Oscillator
High Freq.
Crystal
Oscillator
Brown- out
Detector
Power- on
Reset
Flash
Debug
Interface
w/ ETM
DMA
Controller
RAM
Back- up
Power
Domain
Program
Memory
Memory
Low Freq.
Crystal
Oscillator
Ultra Low Freq.
RC
Oscillator
32- bit bus
Peripheral Reflex System
Serial Interfaces
I/ O Ports
Timers and Triggers
Analog Interfaces
Security
Timer/
Counter
LESENSE
Hardware
AES
ADC
USART
Low Energy
Timer
Real Time
Counter
Low
Energy
Uart™
General
Purpose
I/ O
External
Interrupts
Operational
Amplifier
I2C
DAC
Pulse
Counter
Watchdog
Timer
Pin
Reset
Pin
Wakeup
Analog
Comparator
Back- up
RTC
2.1.1 ARM Cortex-M4 Core
The ARM Cortex-M4 includes a 32-bit RISC processor, with DSP instruction support and floating-point
unit, which can achieve as much as 1.25 Dhrystone MIPS/MHz. A Memory Protection Unit with support
for up to 8 memory segments is included, as well as a Wake-up Interrupt Controller handling interrupts
triggered while the CPU is asleep. The EFM32 implementation of the Cortex-M4 is described in detail
in ARM Cortex-M4 Devices Generic User Guide.
2.1.2 Debug Interface (DBG)
This device includes hardware debug support through a 2-pin serial-wire debug interface and an Embed-
ded Trace Module (ETM) for data/instruction tracing. In addition there is also a 1-wire Serial Wire Viewer
pin which can be used to output profiling information, data trace and software-generated messages.
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2.1.3 Memory System Controller (MSC)
The Memory System Controller (MSC) is the program memory unit of the EFM32WG microcontroller.
The flash memory is readable and writable from both the Cortex-M4 and DMA. The flash memory is
divided into two blocks; the main block and the information block. Program code is normally written to
the main block. Additionally, the information block is available for special user data and flash lock bits.
There is also a read-only page in the information block containing system and device calibration data.
Read and write operations are supported in the energy modes EM0 and EM1.
2.1.4 Direct Memory Access Controller (DMA)
The Direct Memory Access (DMA) controller performs memory operations independently of the CPU.
This has the benefit of reducing the energy consumption and the workload of the CPU, and enables
the system to stay in low energy modes when moving for instance data from the USART to RAM or
from the External Bus Interface to a PWM-generating timer. The DMA controller uses the PL230 µDMA
controller licensed from ARM.
2.1.5 Reset Management Unit (RMU)
The RMU is responsible for handling the reset functionality of the EFM32WG.
2.1.6 Energy Management Unit (EMU)
The Energy Management Unit (EMU) manage all the low energy modes (EM) in EFM32WG microcon-
trollers. Each energy mode manages if the CPU and the various peripherals are available. The EMU
can also be used to turn off the power to unused SRAM blocks.
2.1.7 Clock Management Unit (CMU)
The Clock Management Unit (CMU) is responsible for controlling the oscillators and clocks on-board the
EFM32WG. The CMU provides the capability to turn on and off the clock on an individual basis to all
peripheral modules in addition to enable/disable and configure the available oscillators. The high degree
of flexibility enables software to minimize energy consumption in any specific application by not wasting
power on peripherals and oscillators that are inactive.
2.1.8 Watchdog (WDOG)
The purpose of the watchdog timer is to generate a reset in case of a system failure, to increase appli-
cation reliability. The failure may e.g. be caused by an external event, such as an ESD pulse, or by a
software failure.
2.1.9 Peripheral Reflex System (PRS)
The Peripheral Reflex System (PRS) system is a network which lets the different peripheral module
communicate directly with each other without involving the CPU. Peripheral modules which send out
Reflex signals are called producers. The PRS routes these reflex signals to consumer peripherals which
apply actions depending on the data received. The format for the Reflex signals is not given, but edge
triggers and other functionality can be applied by the PRS.
2.1.10 Inter-Integrated Circuit Interface (I2C)
The I2C module provides an interface between the MCU and a serial I2C-bus. It is capable of acting as
both a master and a slave, and supports multi-master buses. Both standard-mode, fast-mode and fast-
mode plus speeds are supported, allowing transmission rates all the way from 10 kbit/s up to 1 Mbit/s.
Slave arbitration and timeouts are also provided to allow implementation of an SMBus compliant system.
The interface provided to software by the I2C module, allows both fine-grained control of the transmission
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process and close to automatic transfers. Automatic recognition of slave addresses is provided in all
energy modes.
2.1.11 Universal Synchronous/Asynchronous Receiver/Transmitter (US-
ART)
The Universal Synchronous Asynchronous serial Receiver and Transmitter (USART) is a very flexible
serial I/O module. It supports full duplex asynchronous UART communication as well as RS-485, SPI,
MicroWire and 3-wire. It can also interface with ISO7816 SmartCards, IrDA and I2S devices.
2.1.12 Pre-Programmed UART Bootloader
The bootloader presented in application note AN0003 is pre-programmed in the device at factory. Auto-
baud and destructive write are supported. The autobaud feature, interface and commands are described
further in the application note.
2.1.13 Low Energy Universal Asynchronous Receiver/Transmitter
(LEUART)
The unique LEUARTTM, the Low Energy UART, is a UART that allows two-way UART communication on
a strict power budget. Only a 32.768 kHz clock is needed to allow UART communication up to 9600 baud/
s. The LEUART includes all necessary hardware support to make asynchronous serial communication
possible with minimum of software intervention and energy consumption.
2.1.14 Timer/Counter (TIMER)
The 16-bit general purpose Timer has 3 compare/capture channels for input capture and compare/Pulse-
Width Modulation (PWM) output. TIMER0 also includes a Dead-Time Insertion module suitable for motor
control applications.
2.1.15 Real Time Counter (RTC)
The Real Time Counter (RTC) contains a 24-bit counter and is clocked either by a 32.768 kHz crystal
oscillator, or a 32.768 kHz RC oscillator. In addition to energy modes EM0 and EM1, the RTC is also
available in EM2. This makes it ideal for keeping track of time since the RTC is enabled in EM2 where
most of the device is powered down.
2.1.16 Backup Real Time Counter (BURTC)
The Backup Real Time Counter (BURTC) contains a 32-bit counter and is clocked either by a 32.768 kHz
crystal oscillator, a 32.768 kHz RC oscillator or a 1 kHz ULFRCO. The BURTC is available in all Energy
Modes and it can also run in backup mode, making it operational even if the main power should drain out.
2.1.17 Low Energy Timer (LETIMER)
The unique LETIMERTM, the Low Energy Timer, is a 16-bit timer that is available in energy mode EM2
in addition to EM1 and EM0. Because of this, it can be used for timing and output generation when most
of the device is powered down, allowing simple tasks to be performed while the power consumption of
the system is kept at an absolute minimum. The LETIMER can be used to output a variety of waveforms
with minimal software intervention. It is also connected to the Real Time Counter (RTC), and can be
configured to start counting on compare matches from the RTC.
2.1.18 Pulse Counter (PCNT)
The Pulse Counter (PCNT) can be used for counting pulses on a single input or to decode quadrature
encoded inputs. It runs off either the internal LFACLK or the PCNTn_S0IN pin as external clock source.
The module may operate in energy mode EM0 – EM3.
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2.1.19 Analog Comparator (ACMP)
The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indi-
cating which input voltage is higher. Inputs can either be one of the selectable internal references or from
external pins. Response time and thereby also the current consumption can be configured by altering
the current supply to the comparator.
2.1.20 Voltage Comparator (VCMP)
The Voltage Supply Comparator is used to monitor the supply voltage from software. An interrupt can
be generated when the supply falls below or rises above a programmable threshold. Response time and
thereby also the current consumption can be configured by altering the current supply to the comparator.
2.1.21 Analog to Digital Converter (ADC)
The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits
at up to one million samples per second. The integrated input mux can select inputs from 8 external
pins and 6 internal signals.
2.1.22 Digital to Analog Converter (DAC)
The Digital to Analog Converter (DAC) can convert a digital value to an analog output voltage. The DAC
is fully differential rail-to-rail, with 12-bit resolution. It has two single ended output buffers which can be
combined into one differential output. The DAC may be used for a number of different applications such
as sensor interfaces or sound output.
2.1.23 Operational Amplifier (OPAMP)
The EFM32WG232 features 3 Operational Amplifiers. The Operational Amplifier is a versatile general
purpose amplifier with rail-to-rail differential input and rail-to-rail single ended output. The input can be set
to pin, DAC or OPAMP, whereas the output can be pin, OPAMP or ADC. The current is programmable
and the OPAMP has various internal configurations such as unity gain, programmable gain using internal
resistors etc.
2.1.24 Low Energy Sensor Interface (LESENSE)
The Low Energy Sensor Interface (LESENSETM), is a highly configurable sensor interface with support
for up to 16 individually configurable sensors. By controlling the analog comparators and DAC, LESENSE
is capable of supporting a wide range of sensors and measurement schemes, and can for instance mea-
sure LC sensors, resistive sensors and capacitive sensors. LESENSE also includes a programmable
FSM which enables simple processing of measurement results without CPU intervention. LESENSE is
available in energy mode EM2, in addition to EM0 and EM1, making it ideal for sensor monitoring in
applications with a strict energy budget.
2.1.25 Backup Power Domain
The backup power domain is a separate power domain containing a Backup Real Time Counter, BURTC,
and a set of retention registers, available in all energy modes. This power domain can be configured to
automatically change power source to a backup battery when the main power drains out. The backup
power domain enables the EFM32WG232 to keep track of time and retain data, even if the main power
source should drain out.
2.1.26 Advanced Encryption Standard Accelerator (AES)
The AES accelerator performs AES encryption and decryption with 128-bit or 256-bit keys. Encrypting or
decrypting one 128-bit data block takes 52 HFCORECLK cycles with 128-bit keys and 75 HFCORECLK
cycles with 256-bit keys. The AES module is an AHB slave which enables efficient access to the data
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and key registers. All write accesses to the AES module must be 32-bit operations, i.e. 8- or 16-bit
operations are not supported.
2.1.27 General Purpose Input/Output (GPIO)
In the EFM32WG232, there are 53 General Purpose Input/Output (GPIO) pins, which are divided into
ports with up to 16 pins each. These pins can individually be configured as either an output or input. More
advanced configurations like open-drain, filtering and drive strength can also be configured individually
for the pins. The GPIO pins can also be overridden by peripheral pin connections, like Timer PWM
outputs or USART communication, which can be routed to several locations on the device. The GPIO
supports up to 16 asynchronous external pin interrupts, which enables interrupts from any pin on the
device. Also, the input value of a pin can be routed through the Peripheral Reflex System to other
peripherals.
2.2 Configuration Summary
The features of the EFM32WG232 is a subset of the feature set described in the EFM32WG Reference
Manual. Table 2.1 (p. 7) describes device specific implementation of the features.
Table 2.1. Configuration Summary
Module
Cortex-M4
DBG
Configuration
Pin Connections
Full configuration
Full configuration
NA
DBG_SWCLK, DBG_SWDIO,
DBG_SWO
MSC
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration with IrDA
Full configuration with I2S
Full configuration with I2S
Full configuration
Full configuration
Full configuration with DTI
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
NA
DMA
NA
RMU
NA
EMU
NA
CMU
CMU_OUT0, CMU_OUT1
NA
WDOG
PRS
NA
I2C0
I2C0_SDA, I2C0_SCL
I2C1_SDA, I2C1_SCL
US0_TX, US0_RX. US0_CLK, US0_CS
US1_TX, US1_RX, US1_CLK, US1_CS
US2_TX, US2_RX, US2_CLK, US2_CS
LEU0_TX, LEU0_RX
LEU1_TX, LEU1_RX
TIM0_CC[2:0], TIM0_CDTI[2:0]
TIM1_CC[2:0]
I2C1
USART0
USART1
USART2
LEUART0
LEUART1
TIMER0
TIMER1
TIMER2
TIMER3
RTC
TIM2_CC[2:0]
TIM3_CC[2:0]
NA
BURTC
LETIMER0
NA
LET0_O[1:0]
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Module
PCNT0
PCNT1
PCNT2
ACMP0
ACMP1
VCMP
ADC0
Configuration
Pin Connections
Full configuration, 16-bit count register PCNT0_S[1:0]
Full configuration, 8-bit count register
Full configuration, 8-bit count register
Full configuration
PCNT1_S[1:0]
PCNT2_S[1:0]
ACMP0_CH[7:0], ACMP0_O
ACMP1_CH[7:0], ACMP1_O
NA
Full configuration
Full configuration
Full configuration
ADC0_CH[7:0]
DAC0
Full configuration
DAC0_OUT[1:0], DAC0_OUTxALT
OPAMP
AES
Full configuration
53 pins
NA
GPIO
Available pins are shown in
Table 4.3 (p. 60)
2.3 Memory Map
The EFM32WG232 memory map is shown in Figure 2.2 (p. 8), with RAM and Flash sizes for the
largest memory configuration.
Figure 2.2. EFM32WG232 Memory Map with largest RAM and Flash sizes
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3 Electrical Characteristics
3.1 Test Conditions
3.1.1 Typical Values
The typical data are based on TAMB=25°C and VDD=3.0 V, as defined in Table 3.2 (p. 9), by simu-
lation and/or technology characterisation unless otherwise specified.
3.1.2 Minimum and Maximum Values
The minimum and maximum values represent the worst conditions of ambient temperature, supply volt-
age and frequencies, as defined in Table 3.2 (p. 9), by simulation and/or technology characterisa-
tion unless otherwise specified.
3.2 Absolute Maximum Ratings
The absolute maximum ratings are stress ratings, and functional operation under such conditions are
not guaranteed. Stress beyond the limits specified in Table 3.1 (p. 9) may affect the device reliability
or cause permanent damage to the device. Functional operating conditions are given in Table 3.2 (p.
9) .
Table 3.1. Absolute Maximum Ratings
Symbol
Parameter
Condition
Min
Typ
Max
Unit
1501 °C
TSTG
Storage tempera-
ture range
-40
TS
Maximum soldering Latest IPC/JEDEC J-STD-020
260 °C
temperature
Standard
VDDMAX
External main sup-
ply voltage
0
3.8
V
V
VIOPIN
Voltage on any I/O
pin
-0.3
VDD+0.3
1Based on programmed devices tested for 10000 hours at 150ºC. Storage temperature affects retention of preprogrammed cal-
ibration values stored in flash. Please refer to the Flash section in the Electrical Characteristics for information on flash data re-
tention for different temperatures.
3.3 General Operating Conditions
3.3.1 General Operating Conditions
Table 3.2. General Operating Conditions
Symbol
TAMB
VDDOP
fAPB
Parameter
Min
Typ
Max
Unit
85 °C
3.8
Ambient temperature range
Operating supply voltage
Internal APB clock frequency
Internal AHB clock frequency
-40
1.98
V
48 MHz
48 MHz
fAHB
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3.3.2 Environmental
Table 3.3. Environmental
Symbol
Parameter
Condition
Min
Typ
Max
Unit
VESDHBM
ESD (Human Body
Model HBM)
TAMB=25°C
2000
750
V
VESDCDM
ESD (Charged De-
vice Model, CDM)
TAMB=25°C
V
Latch-up sensitivity passed: ±100 mA/1.5 × VSUPPLY(max) according to JEDEC JESD 78 method Class
II, 85°C.
3.4 Current Consumption
Table 3.4. Current Consumption
Symbol
Parameter
Condition
Min
Typ
Max
Unit
48 MHz HFXO, all peripheral
clocks disabled, VDD= 3.0 V,
TAMB=25°C
225
225
226
227
228
229
230
231
232
233
238
238
236 µA/
MHz
48 MHz HFXO, all peripheral
clocks disabled, VDD= 3.0 V,
TAMB=85°C
µA/
MHz
28 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=25°C
238 µA/
MHz
28 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=85°C
µA/
MHz
21 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=25°C
240 µA/
MHz
21 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=85°C
µA/
MHz
EM0 current. No
prescaling. Running
prime number cal-
culation code from
Flash. (Production
test condition = 14
MHz)
IEM0
14 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=25°C
243 µA/
MHz
14 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=85°C
µA/
MHz
11 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=25°C
245 µA/
MHz
11 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=85°C
µA/
MHz
6.6 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=25°C
250 µA/
MHz
6.6 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=85°C
µA/
MHz
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Symbol
Parameter
Condition
Min
Typ
Max
Unit
1.2 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=25°C
271
275
63
286 µA/
MHz
1.2 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=85°C
µA/
MHz
48 MHz HFXO, all peripheral
clocks disabled, VDD= 3.0 V,
TAMB=25°C
75 µA/
MHz
48 MHz HFXO, all peripheral
clocks disabled, VDD= 3.0 V,
TAMB=85°C
65
76 µA/
MHz
28 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=25°C
64
75 µA/
MHz
28 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=85°C
65
77 µA/
MHz
21 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=25°C
65
76 µA/
MHz
21 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=85°C
66
78 µA/
MHz
14 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=25°C
67
79 µA/
MHz
EM1 current (Pro-
duction test condi-
tion = 14 MHz)
IEM1
14 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=85°C
68
82 µA/
MHz
11 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=25°C
68
81 µA/
MHz
11 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=85°C
70
83 µA/
MHz
6.6 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=25°C
74
87 µA/
MHz
6.6 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=85°C
76
89 µA/
MHz
1.2 MHz HFRCO. all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=25°C
106
112
0.951
120 µA/
MHz
1.2 MHz HFRCO. all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=85°C
129 µA/
MHz
EM2 current with RTC
prescaled to 1 Hz, 32.768
kHz LFRCO, VDD= 3.0 V,
TAMB=25°C
1.71 µA
IEM2
EM2 current
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Symbol
Parameter
Condition
Min
Typ
Max
Unit
4.01 µA
EM2 current with RTC
prescaled to 1 Hz, 32.768
kHz LFRCO, VDD= 3.0 V,
TAMB=85°C
3.01
VDD= 3.0 V, TAMB=25°C
VDD= 3.0 V, TAMB=85°C
VDD= 3.0 V, TAMB=25°C
VDD= 3.0 V, TAMB=85°C
0.65
2.65
0.02
0.44
1.3 µA
4.0 µA
IEM3
EM3 current
EM4 current
0.055 µA
0.9 µA
IEM4
1Using backup RTC.
3.4.1 EM1 Current Consumption
Figure 3.1. EM1 Current consumption with all peripheral clocks disabled and HFXO running at
48MHz
3.15
3.10
3.05
3.00
2.95
2.90
3.15
3.10
3.05
3.00
2.95
2.90
2.0V
2.2V
2.4V
2.6V
2.8V
3.0V
3.2V
3.4V
3.6V
3.8V
- 40°C
- 15°C
5°C
25°C
45°C
65°C
85°C
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
Figure 3.2. EM1 Current consumption with all peripheral clocks disabled and HFRCO running
at 28MHz
1.85
1.80
1.75
1.70
1.65
1.60
1.85
1.80
1.75
1.70
1.65
1.60
2.0V
2.2V
2.4V
2.6V
2.8V
3.0V
3.2V
3.4V
3.6V
3.8V
- 40°C
- 15°C
5°C
25°C
45°C
65°C
85°C
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
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Figure 3.3. EM1 Current consumption with all peripheral clocks disabled and HFRCO running
at 21MHz
1.42
1.40
1.38
1.36
1.34
1.32
1.30
1.28
1.26
1.24
1.42
1.40
1.38
1.36
1.34
1.32
1.30
1.28
1.26
1.24
2.0V
2.2V
2.4V
2.6V
2.8V
3.0V
3.2V
3.4V
3.6V
3.8V
- 40°C
- 15°C
5°C
25°C
45°C
65°C
85°C
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
Figure 3.4. EM1 Current consumption with all peripheral clocks disabled and HFRCO running
at 14MHz
0.98
0.96
0.94
0.92
0.90
0.88
0.86
0.98
0.96
0.94
0.92
0.90
0.88
0.86
2.0V
2.2V
2.4V
2.6V
2.8V
3.0V
3.2V
3.4V
3.6V
3.8V
- 40°C
- 15°C
5°C
25°C
45°C
65°C
85°C
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
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Figure 3.5. EM1 Current consumption with all peripheral clocks disabled and HFRCO running
at 11MHz
0.78
0.76
0.74
0.72
0.70
0.78
0.76
0.74
0.72
0.70
2.0V
2.2V
2.4V
2.6V
2.8V
3.0V
3.2V
3.4V
3.6V
3.8V
- 40°C
- 15°C
5°C
25°C
45°C
65°C
85°C
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
Figure 3.6. EM1 Current consumption with all peripheral clocks disabled and HFRCO running
at 6.6MHz
0.52
0.51
0.50
0.49
0.48
0.47
0.46
0.45
0.52
0.51
0.50
0.49
0.48
0.47
0.46
0.45
2.0V
2.2V
2.4V
2.6V
2.8V
3.0V
3.2V
3.4V
3.6V
3.8V
- 40°C
- 15°C
5°C
25°C
45°C
65°C
85°C
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
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Figure 3.7. EM1 Current consumption with all peripheral clocks disabled and HFRCO running
at 1.2MHz
0.138
0.136
0.134
0.132
0.130
0.128
0.126
0.124
0.122
0.160
0.155
0.150
0.145
0.140
0.135
0.130
0.125
0.120
0.115
- 40°C
- 15°C
5°C
2.0V
2.2V
2.4V
2.6V
2.8V
3.0V
3.2V
3.4V
3.6V
3.8V
25°C
45°C
65°C
85°C
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
3.4.2 EM2 Current Consumption
Figure 3.8. EM2 current consumption. RTC1 prescaled to 1kHz, 32.768 kHz LFRCO.
3.5
3.0
2.5
2.0
1.5
1.0
0.5
3.5
3.0
2.5
2.0
1.5
1.0
0.5
- 40.0°C
- 15.0°C
5.0°C
Vdd= 2.0V
Vdd= 2.2V
Vdd= 2.4V
Vdd= 2.6V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.2V
Vdd= 3.4V
Vdd= 3.6V
Vdd= 3.8V
25.0°C
45.0°C
65.0°C
85.0°C
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–20
0
20
40
60
80
Vdd [V]
Temperature [°C]
1Using backup RTC.
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3.4.3 EM3 Current Consumption
Figure 3.9. EM3 current consumption.
3.0
3.0
- 40.0°C
Vdd= 2.0V
- 15.0°C
5.0°C
Vdd= 2.2V
Vdd= 2.4V
2.5
2.0
1.5
1.0
0.5
0.0
2.5
25.0°C
45.0°C
65.0°C
85.0°C
Vdd= 2.6V
Vdd= 2.8V
Vdd= 3.0V
2.0
Vdd= 3.2V
Vdd= 3.4V
Vdd= 3.6V
1.5
1.0
0.5
0.0
Vdd= 3.8V
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–20
0
20
40
60
80
Vdd [V]
Temperature [°C]
3.4.4 EM4 Current Consumption
Figure 3.10. EM4 current consumption.
0.7
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
- 40.0°C
Vdd= 2.0V
Vdd= 2.2V
Vdd= 2.4V
Vdd= 2.6V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.2V
Vdd= 3.4V
Vdd= 3.6V
Vdd= 3.8V
- 15.0°C
0.6
0.5
0.4
0.3
0.2
0.1
0.0
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–20
0
20
40
60
80
Vdd [V]
Temperature [°C]
3.5 Transition between Energy Modes
The transition times are measured from the trigger to the first clock edge in the CPU.
Table 3.5. Energy Modes Transitions
Symbol
Parameter
Min
Typ
Max
Unit
tEM10
Transition time from EM1 to EM0
0
HF-
CORE-
CLK
cycles
tEM20
tEM30
tEM40
Transition time from EM2 to EM0
Transition time from EM3 to EM0
Transition time from EM4 to EM0
2
2
µs
µs
µs
163
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3.6 Power Management
The EFM32WG requires the AVDD_x, VDD_DREG and IOVDD_x pins to be connected together (with
optional filter) at the PCB level. For practical schematic recommendations, please see the application
note, "AN0002 EFM32 Hardware Design Considerations".
Table 3.6. Power Management
Symbol
Parameter
Condition
Min
Typ
Max
Unit
VBODextthr-
BOD threshold on
falling external sup-
ply voltage
1.74
1.96
1.98
1.98
V
VBODextthr+
BOD threshold on
rising external sup-
ply voltage
1.85
V
V
VPORthr+
Power-on Reset
(POR) threshold on
rising external sup-
ply voltage
tRESET
Delay from reset
is released until
program execution
starts
Applies to Power-on Reset,
Brown-out Reset and pin reset.
163
1
µs
CDECOUPLE
Voltage regulator
decoupling capaci-
tor.
X5R capacitor recommended.
Apply between DECOUPLE pin
and GROUND
µF
3.7 Flash
Table 3.7. Flash
Symbol
Parameter
Condition
Min
Typ
Max
Unit
ECFLASH
Flash erase cycles
before failure
20000
cycles
TAMB<150°C
10000
10
h
RETFLASH
Flash data retention TAMB<85°C
TAMB<70°C
years
years
µs
20
tW_PROG
Word (32-bit) pro-
gramming time
20
tPERASE
tDERASE
IERASE
IWRITE
Page erase time
Device erase time
Erase current
20
40
20.4
40.8
20.8 ms
41.6 ms
71 mA
Write current
71 mA
VFLASH
Supply voltage dur-
ing flash erase and
write
1.98
3.8 V
1Measured at 25°C
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3.8 General Purpose Input Output
Table 3.8. GPIO
Symbol
VIOIL
Parameter
Condition
Min
Typ
Max
0.30VDD
Unit
V
Input low voltage
Input high voltage
VIOIH
0.70VDD
V
Sourcing 0.1 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= LOWEST
0.80VDD
0.90VDD
0.85VDD
0.90VDD
V
Sourcing 0.1 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= LOWEST
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Sourcing 1 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= LOW
Sourcing 1 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= LOW
Output high volt-
age (Production test
condition = 3.0V,
DRIVEMODE =
STANDARD)
VIOOH
Sourcing 6 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= STANDARD
0.75VDD
0.85VDD
0.60VDD
0.80VDD
Sourcing 6 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= STANDARD
Sourcing 20 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= HIGH
Sourcing 20 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= HIGH
Sinking 0.1 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= LOWEST
0.20VDD
0.10VDD
0.10VDD
0.05VDD
Sinking 0.1 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= LOWEST
Sinking 1 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= LOW
Output low voltage
(Production test
condition = 3.0V,
DRIVEMODE =
STANDARD)
Sinking 1 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= LOW
VIOOL
Sinking 6 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= STANDARD
0.30VDD
0.20VDD
0.35VDD
Sinking 6 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= STANDARD
Sinking 20 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= HIGH
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Symbol
Parameter
Condition
Min
Typ
Max
0.25VDD
Unit
Sinking 20 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= HIGH
V
IIOLEAK
Input leakage cur-
rent
High Impedance IO connected
to GROUND or Vdd
±0.1
40
±100 nA
RPU
I/O pin pull-up resis-
tor
kOhm
kOhm
Ohm
RPD
I/O pin pull-down re-
sistor
40
RIOESD
Internal ESD series
resistor
200
tIOGLITCH
Pulse width of puls-
es to be removed
by the glitch sup-
pression filter
10
50 ns
GPIO_Px_CTRL DRIVEMODE
= LOWEST and load capaci-
tance CL=12.5-25pF.
20+0.1CL
20+0.1CL
0.10VDD
250 ns
250 ns
V
tIOOF
Output fall time
GPIO_Px_CTRL DRIVEMODE
= LOW and load capacitance
CL=350-600pF
VIOHYST
I/O pin hysteresis
VDD = 1.98 - 3.8 V
(VIOTHR+ - VIOTHR-
)
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Figure 3.11. Typical Low-Level Output Current, 2V Supply Voltage
0.20
0.15
0.10
0.05
0.00
5
4
3
2
1
- 40°C
25°C
85°C
- 40°C
25°C
85°C
0
0.0
0.5
1.0
1.5
2.0
0.0
0.5
1.0
1.5
2.0
Low- Level Output Voltage [V]
Low- Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = LOWEST
GPIO_Px_CTRL DRIVEMODE = LOW
20
45
40
35
30
25
20
15
10
5
15
10
5
- 40°C
25°C
- 40°C
25°C
85°C
85°C
0
0.0
0
0.5
1.0
1.5
2.0
0.0
0.5
1.0
1.5
2.0
Low- Level Output Voltage [V]
Low- Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = STANDARD
GPIO_Px_CTRL DRIVEMODE = HIGH
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Figure 3.12. Typical High-Level Output Current, 2V Supply Voltage
0.00
–0.05
–0.10
–0.15
–0.20
0.0
–0.5
–1.0
–1.5
–2.0
–2.5
- 40°C
25°C
85°C
- 40°C
25°C
85°C
0.0
0.5
1.0
1.5
2.0
0.0
0.5
1.0
1.5
2.0
High- Level Output Voltage [V]
High- Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = LOWEST
GPIO_Px_CTRL DRIVEMODE = LOW
0
0
- 40°C
- 40°C
25°C
85°C
25°C
85°C
–10
–20
–30
–40
–50
–5
–10
–15
–20
0.0
0.5
1.0
1.5
2.0
0.0
0.5
1.0
1.5
2.0
High- Level Output Voltage [V]
High- Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = STANDARD
GPIO_Px_CTRL DRIVEMODE = HIGH
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Figure 3.13. Typical Low-Level Output Current, 3V Supply Voltage
0.5
0.4
0.3
0.2
0.1
0.0
10
8
6
4
2
- 40°C
25°C
85°C
- 40°C
25°C
85°C
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Low- Level Output Voltage [V]
Low- Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = LOWEST
GPIO_Px_CTRL DRIVEMODE = LOW
40
35
30
25
20
15
10
50
40
30
20
10
0
5
- 40°C
- 40°C
25°C
85°C
25°C
85°C
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Low- Level Output Voltage [V]
Low- Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = STANDARD
GPIO_Px_CTRL DRIVEMODE = HIGH
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Figure 3.14. Typical High-Level Output Current, 3V Supply Voltage
0.0
–0.1
–0.2
–0.3
–0.4
–0.5
0
- 40°C
25°C
85°C
- 40°C
25°C
85°C
–1
–2
–3
–4
–5
–6
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
High- Level Output Voltage [V]
High- Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = LOWEST
GPIO_Px_CTRL DRIVEMODE = LOW
0
0
- 40°C
- 40°C
25°C
85°C
25°C
85°C
–10
–20
–30
–40
–50
–10
–20
–30
–40
–50
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
High- Level Output Voltage [V]
High- Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = STANDARD
GPIO_Px_CTRL DRIVEMODE = HIGH
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Figure 3.15. Typical Low-Level Output Current, 3.8V Supply Voltage
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
14
12
10
8
6
4
2
- 40°C
25°C
85°C
- 40°C
25°C
85°C
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Low- Level Output Voltage [V]
Low- Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = LOWEST
GPIO_Px_CTRL DRIVEMODE = LOW
50
40
30
20
10
50
40
30
20
10
0
- 40°C
25°C
- 40°C
25°C
85°C
85°C
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Low- Level Output Voltage [V]
Low- Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = STANDARD
GPIO_Px_CTRL DRIVEMODE = HIGH
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Figure 3.16. Typical High-Level Output Current, 3.8V Supply Voltage
0.0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
0
- 40°C
25°C
85°C
- 40°C
25°C
85°C
–1
–2
–3
–4
–5
–6
–7
–8
–9
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
High- Level Output Voltage [V]
High- Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = LOWEST
GPIO_Px_CTRL DRIVEMODE = LOW
0
0
- 40°C
- 40°C
25°C
85°C
25°C
85°C
–10
–20
–30
–40
–50
–10
–20
–30
–40
–50
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
High- Level Output Voltage [V]
High- Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = STANDARD
GPIO_Px_CTRL DRIVEMODE = HIGH
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3.9 Oscillators
3.9.1 LFXO
Table 3.9. LFXO
Symbol
Parameter
Condition
Min
Typ
Max
Unit
fLFXO
Supported nominal
crystal frequency
32.768
30
kHz
ESRLFXO
Supported crystal
equivalent series re-
sistance (ESR)
120 kOhm
CLFXOL
Supported crystal
external load range
X1
25 pF
nA
ILFXO
Current consump-
tion for core and
buffer after startup.
ESR=30 kOhm, CL=10 pF,
LFXOBOOST in CMU_CTRL is
1
190
400
tLFXO
Start- up time.
ESR=30 kOhm, CL=10 pF,
40% - 60% duty cycle has
been reached, LFXOBOOST in
CMU_CTRL is 1
ms
1See Minimum Load Capacitance (CLFXOL) Requirement For Safe Crystal Startup in energyAware Designer in Simplicity Studio
For safe startup of a given crystal, the energyAware Designer in Simplicity Studio contains a tool to help
users configure both load capacitance and software settings for using the LFXO. For details regarding
the crystal configuration, the reader is referred to application note "AN0016 EFM32 Oscillator Design
Consideration".
3.9.2 HFXO
Table 3.10. HFXO
Symbol
Parameter
Condition
Min
Typ
Max
Unit
fHFXO
Supported nominal
crystal Frequency
4
48 MHz
Crystal frequency 48 MHz
50 Ohm
60 Ohm
1500 Ohm
mS
Supported crystal
ESRHFXO
equivalent series re- Crystal frequency 32 MHz
30
sistance (ESR)
Crystal frequency 4 MHz
400
gmHFXO
The transconduc-
tance of the HFXO
input transistor at
crystal startup
HFXOBOOST in CMU_CTRL
equals 0b11
20
5
CHFXOL
Supported crystal
external load range
25 pF
µA
4 MHz: ESR=400 Ohm,
CL=20 pF, HFXOBOOST in
CMU_CTRL equals 0b11
85
165
400
Current consump-
tion for HFXO after
startup
IHFXO
32 MHz: ESR=30 Ohm,
CL=10 pF, HFXOBOOST in
CMU_CTRL equals 0b11
µA
µs
tHFXO
Startup time
32 MHz: ESR=30 Ohm,
CL=10 pF, HFXOBOOST in
CMU_CTRL equals 0b11
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3.9.3 LFRCO
Table 3.11. LFRCO
Symbol
Parameter
Condition
Min
Typ
Max
Unit
fLFRCO
Oscillation frequen-
cy , VDD= 3.0 V,
TAMB=25°C
31.29
32.768
150
34.28 kHz
tLFRCO
Startup time not in-
cluding software
calibration
µs
ILFRCO
Current consump-
tion
300
1.5
nA
%
TUNESTEPL- Frequency step
for LSB change in
FRCO
TUNING value
Figure 3.17. Calibrated LFRCO Frequency vs Temperature and Supply Voltage
42
40
38
36
34
32
30
42
40
38
36
34
32
30
- 40°C
25°C
85°C
2.0 V
3.0 V
3.8 V
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
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3.9.4 HFRCO
Table 3.12. HFRCO
Symbol
Parameter
Condition
Min
Typ
Max
Unit
28.5 MHz
21.4 MHz
14.3 MHz
11.2 MHz
6.72 MHz
1.25 MHz
28 MHz frequency band
21 MHz frequency band
14 MHz frequency band
11 MHz frequency band
7 MHz frequency band
1 MHz frequency band
fHFRCO = 14 MHz
27.5
20.6
13.7
10.8
6.48
1.15
28.0
21.0
14.0
11.0
6.60
1.20
0.6
Oscillation frequen-
cy, VDD= 3.0 V,
TAMB=25°C
fHFRCO
tHFRCO_settling Settling time after
start-up
Cycles
fHFRCO = 28 MHz
fHFRCO = 21 MHz
fHFRCO = 14 MHz
fHFRCO = 11 MHz
fHFRCO = 6.6 MHz
fHFRCO = 1.2 MHz
fHFRCO = 14 MHz
165
134
106
94
215 µA
175 µA
140 µA
125 µA
105 µA
40 µA
Current consump-
tion
IHFRCO
77
25
DCHFRCO
Duty cycle
48.5
50
51
%
%
TUNESTEPH- Frequency step
0.31
for LSB change in
FRCO
TUNING value
1The TUNING field in the CMU_HFRCOCTRL register may be used to adjust the HFRCO frequency. There is enough adjustment
range to ensure that the frequency bands above 7 MHz will always have some overlap across supply voltage and temperature. By
using a stable frequency reference such as the LFXO or HFXO, a firmware calibration routine can vary the TUNING bits and the
frequency band to maintain the HFRCO frequency at any arbitrary value between 7 MHz and 28 MHz across operating conditions.
Figure 3.18. Calibrated HFRCO 1 MHz Band Frequency vs Supply Voltage and Temperature
1.45
1.40
1.35
1.30
1.25
1.20
1.15
1.10
1.05
1.45
1.40
1.35
1.30
1.25
1.20
1.15
1.10
1.05
- 40°C
25°C
85°C
2.0 V
3.0 V
3.8 V
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
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Figure 3.19. Calibrated HFRCO 7 MHz Band Frequency vs Supply Voltage and Temperature
6.70
6.65
6.60
6.55
6.50
6.45
6.40
6.35
6.30
6.70
6.65
6.60
6.55
6.50
6.45
6.40
6.35
6.30
- 40°C
25°C
85°C
2.0 V
3.0 V
3.8 V
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
Figure 3.20. Calibrated HFRCO 11 MHz Band Frequency vs Supply Voltage and Temperature
11.2
11.1
11.0
10.9
10.8
10.7
10.6
11.2
11.1
11.0
10.9
10.8
10.7
10.6
- 40°C
25°C
85°C
2.0 V
3.0 V
3.8 V
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
Figure 3.21. Calibrated HFRCO 14 MHz Band Frequency vs Supply Voltage and Temperature
14.2
14.1
14.0
13.9
13.8
13.7
13.6
13.5
13.4
14.2
14.1
14.0
13.9
13.8
13.7
13.6
13.5
13.4
- 40°C
25°C
85°C
2.0 V
3.0 V
3.8 V
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
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Figure 3.22. Calibrated HFRCO 21 MHz Band Frequency vs Supply Voltage and Temperature
21.2
21.0
20.8
20.6
20.4
20.2
21.2
21.0
20.8
20.6
20.4
20.2
- 40°C
25°C
85°C
2.0 V
3.0 V
3.8 V
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
Figure 3.23. Calibrated HFRCO 28 MHz Band Frequency vs Supply Voltage and Temperature
28.2
28.0
27.8
27.6
27.4
27.2
27.0
26.8
28.4
28.2
28.0
27.8
27.6
27.4
27.2
27.0
26.8
- 40°C
25°C
85°C
2.0 V
3.0 V
3.8 V
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
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3.9.5 AUXHFRCO
Table 3.13. AUXHFRCO
Symbol
Parameter
Condition
Min
Typ
Max
Unit
28.5 MHz
21.4 MHz
14.3 MHz
11.2 MHz
6.72 MHz
1.25 MHz
28 MHz frequency band
21 MHz frequency band
14 MHz frequency band
11 MHz frequency band
7 MHz frequency band
1 MHz frequency band
fAUXHFRCO = 14 MHz
27.5
20.6
13.7
10.8
6.48
1.15
28.0
21.0
14.0
11.0
6.60
1.20
0.6
Oscillation frequen-
cy, VDD= 3.0 V,
TAMB=25°C
fAUXHFRCO
tAUXHFRCO_settlingSettling time after
start-up
Cycles
DCAUXHFRCO
Duty cycle
fAUXHFRCO = 14 MHz
48.5
50
51 %
TUNESTEPAUX-Frequency step
0.31
%
for LSB change in
HFRCO
TUNING value
1The TUNING field in the CMU_AUXHFRCOCTRL register may be used to adjust the AUXHFRCO frequency. There is enough
adjustment range to ensure that the frequency bands above 7 MHz will always have some overlap across supply voltage and
temperature. By using a stable frequency reference such as the LFXO or HFXO, a firmware calibration routine can vary the
TUNING bits and the frequency band to maintain the AUXHFRCO frequency at any arbitrary value between 7 MHz and 28 MHz
across operating conditions.
3.9.6 ULFRCO
Table 3.14. ULFRCO
Symbol
Parameter
Condition
Min
Typ
Max
Unit
fULFRCO
Oscillation frequen- 25°C, 3V
cy
0.7
1.75 kHz
TCULFRCO
Temperature coeffi-
cient
0.05
%/°C
%/V
VCULFRCO
Supply voltage co-
efficient
-18.2
3.10 Analog Digital Converter (ADC)
Table 3.15. ADC
Symbol
VADCIN
Parameter
Condition
Single ended
Differential
Min
Typ
Max
Unit
0
-VREF/2
1.25
VREF
VREF/2
VDD
V
V
V
Input voltage range
VADCREFIN
Input range of exter-
nal reference volt-
age, single ended
and differential
VADCREFIN_CH7 Input range of ex-
ternal negative ref-
erence voltage on
See VADCREFIN
0
VDD - 1.1
V
V
channel 7
VADCREFIN_CH6 Input range of ex-
ternal positive ref-
See VADCREFIN
0.625
VDD
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Symbol
Parameter
Condition
Min
Typ
Max
Unit
erence voltage on
channel 6
VADCCMIN
Common mode in-
put range
0
VDD
V
IADCIN
Input current
2pF sampling capacitors
<100
65
nA
dB
CMRRADC
Analog input com-
mon mode rejection
ratio
1 MSamples/s, 12 bit, external
reference
351
67
µA
µA
10 kSamples/s 12 bit, internal
1.25 V reference, WARMUP-
MODE in ADCn_CTRL set to
0b00
Average active cur-
rent
10 kSamples/s 12 bit, internal
1.25 V reference, WARMUP-
MODE in ADCn_CTRL set to
0b01
63
64
µA
µA
µA
IADC
10 kSamples/s 12 bit, internal
1.25 V reference, WARMUP-
MODE in ADCn_CTRL set to
0b10
IADCREF
Current consump-
tion of internal volt-
age reference
Internal voltage reference
65
2
CADCIN
RADCIN
RADCFILT
Input capacitance
pF
Input ON resistance
1
MOhm
kOhm
Input RC filter resis-
tance
10
CADCFILT
Input RC filter/de-
coupling capaci-
tance
250
fF
fADCCLK
ADC Clock Fre-
quency
13 MHz
6 bit
7
11
13
1
ADC-
CLK
Cycles
8 bit
ADC-
CLK
Cycles
tADCCONV
Conversion time
Acquisition time
12 bit
ADC-
CLK
Cycles
tADCACQ
Programmable
256 ADC-
CLK
Cycles
tADCACQVDD3
Required acquisi-
tion time for VDD/3
reference
2
µs
Startup time of ref-
erence generator
5
µs
tADCSTART
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Symbol
Parameter
Condition
Min
Typ
Max
Unit
and ADC core in
NORMAL mode
Startup time of ref-
erence generator
and ADC core in
KEEPADCWARM
mode
1
µs
1 MSamples/s, 12 bit, single
ended, internal 1.25V refer-
ence
59
dB
1 MSamples/s, 12 bit, single
ended, internal 2.5V reference
63
65
60
65
54
67
69
62
dB
dB
dB
dB
dB
dB
dB
dB
1 MSamples/s, 12 bit, single
ended, VDD reference
1 MSamples/s, 12 bit, differen-
tial, internal 1.25V reference
1 MSamples/s, 12 bit, differen-
tial, internal 2.5V reference
1 MSamples/s, 12 bit, differen-
tial, 5V reference
1 MSamples/s, 12 bit, differen-
tial, VDD reference
1 MSamples/s, 12 bit, differen-
tial, 2xVDD reference
Signal to Noise Ra-
tio (SNR)
SNRADC
200 kSamples/s, 12 bit, sin-
gle ended, internal 1.25V refer-
ence
200 kSamples/s, 12 bit, single
ended, internal 2.5V reference
63
67
63
66
66
66
70
58
dB
dB
dB
dB
dB
dB
dB
dB
200 kSamples/s, 12 bit, single
ended, VDD reference
200 kSamples/s, 12 bit, differ-
ential, internal 1.25V reference
200 kSamples/s, 12 bit, differ-
ential, internal 2.5V reference
200 kSamples/s, 12 bit, differ-
ential, 5V reference
200 kSamples/s, 12 bit, differ-
ential, VDD reference
63
200 kSamples/s, 12 bit, differ-
ential, 2xVDD reference
1 MSamples/s, 12 bit, single
ended, internal 1.25V refer-
ence
1 MSamples/s, 12 bit, single
ended, internal 2.5V reference
62
64
60
dB
dB
dB
SIgnal-to-Noise
And Distortion-ratio
(SINAD)
SINADADC
1 MSamples/s, 12 bit, single
ended, VDD reference
1 MSamples/s, 12 bit, differen-
tial, internal 1.25V reference
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Symbol
Parameter
Condition
Min
Typ
Max
Unit
1 MSamples/s, 12 bit, differen-
tial, internal 2.5V reference
64
54
66
68
61
dB
1 MSamples/s, 12 bit, differen-
tial, 5V reference
dB
dB
dB
dB
1 MSamples/s, 12 bit, differen-
tial, VDD reference
1 MSamples/s, 12 bit, differen-
tial, 2xVDD reference
200 kSamples/s, 12 bit, sin-
gle ended, internal 1.25V refer-
ence
200 kSamples/s, 12 bit, single
ended, internal 2.5V reference
65
66
63
66
66
66
69
64
dB
dB
dB
dB
dB
dB
dB
dBc
200 kSamples/s, 12 bit, single
ended, VDD reference
200 kSamples/s, 12 bit, differ-
ential, internal 1.25V reference
200 kSamples/s, 12 bit, differ-
ential, internal 2.5V reference
200 kSamples/s, 12 bit, differ-
ential, 5V reference
200 kSamples/s, 12 bit, differ-
ential, VDD reference
62
200 kSamples/s, 12 bit, differ-
ential, 2xVDD reference
1 MSamples/s, 12 bit, single
ended, internal 1.25V refer-
ence
1 MSamples/s, 12 bit, single
ended, internal 2.5V reference
76
73
66
77
76
75
69
75
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
1 MSamples/s, 12 bit, single
ended, VDD reference
1 MSamples/s, 12 bit, differen-
tial, internal 1.25V reference
1 MSamples/s, 12 bit, differen-
tial, internal 2.5V reference
Spurious-Free Dy-
namic Range (SF-
DR)
1 MSamples/s, 12 bit, differen-
tial, VDD reference
SFDRADC
1 MSamples/s, 12 bit, differen-
tial, 2xVDD reference
1 MSamples/s, 12 bit, differen-
tial, 5V reference
200 kSamples/s, 12 bit, sin-
gle ended, internal 1.25V refer-
ence
200 kSamples/s, 12 bit, single
ended, internal 2.5V reference
75
76
dBc
dBc
200 kSamples/s, 12 bit, single
ended, VDD reference
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Symbol
Parameter
Condition
Min
Typ
Max
Unit
200 kSamples/s, 12 bit, differ-
ential, internal 1.25V reference
79
79
78
79
79
dBc
200 kSamples/s, 12 bit, differ-
ential, internal 2.5V reference
dBc
dBc
dBc
dBc
200 kSamples/s, 12 bit, differ-
ential, 5V reference
200 kSamples/s, 12 bit, differ-
ential, VDD reference
68
200 kSamples/s, 12 bit, differ-
ential, 2xVDD reference
After calibration, single ended
After calibration, differential
-3.5
0.3
0.3
3
mV
VADCOFFSET
Offset voltage
mV
-1.92
-6.3
mV/°C
Thermometer out-
put gradient
ADC
Codes/
°C
TGRADADCTH
DNLADC
INLADC
Differential non-lin-
earity (DNL)
-1
±0.7
±1.2
4
LSB
Integral non-linear-
ity (INL), End point
method
±3 LSB
MCADC
No missing codes
11.9991
12
0.012
0.012
0.22
bits
1.25V reference
2.5V reference
1.25V reference
2.5V reference
0.0333 %/°C
0.033 %/°C
0.73 LSB/°C
0.623 LSB/°C
GAINED
Gain error drift
OFFSETED
Offset error drift
0.22
1On the average every ADC will have one missing code, most likely to appear around 2048 +/- n*512 where n can be a value in
the set {-3, -2, -1, 1, 2, 3}. There will be no missing code around 2048, and in spite of the missing code the ADC will be monotonic
at all times so that a response to a slowly increasing input will always be a slowly increasing output. Around the one code that is
missing, the neighbour codes will look wider in the DNL plot. The spectra will show spurs on the level of -78dBc for a full scale
input for chips that have the missing code issue.
2Typical numbers given by abs(Mean) / (85 - 25).
3Max number given by (abs(Mean) + 3x stddev) / (85 - 25).
The integral non-linearity (INL) and differential non-linearity parameters are explained in Figure 3.24 (p.
36) and Figure 3.25 (p. 36) , respectively.
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Figure 3.24. Integral Non-Linearity (INL)
Digital ouput code
INL= |[(VD- VSS)/ VLSBIDEAL] - D| where 0 < D < 2N - 1
4095
4094
4093
4092
Actual ADC
tranfer function
before offset and
gain correction
Actual ADC
tranfer function
after offset and
gain correction
INL Error
(End Point INL)
Ideal transfer
curve
3
2
1
0
VOFFSET
Analog Input
Figure 3.25. Differential Non-Linearity (DNL)
Digital
ouput
DNL= |[(VD+ 1 - VD)/ VLSBIDEAL] - 1| where 0 < D < 2N - 2
code
4095
4094
4093
4092
Full Scale Range
Example: Adjacent
input value VD+ 1
corrresponds to digital
output code D+ 1
Actual transfer
function with one
missing code.
Example: Input value
VD corrresponds to
digital output code D
Code width = 2 LSB
DNL= 1 LSB
Ideal transfer
curve
0.5
LSB
Ideal spacing
between two
adjacent codes
VLSBIDEAL= 1 LSB
5
4
3
2
1
0
Ideal 50%
Transition Point
Ideal Code Center
Analog Input
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3.10.1 Typical performance
Figure 3.26. ADC Frequency Spectrum, Vdd = 3V, Temp = 25°C
1.25V Reference
2XVDDVSS Reference
VDD Reference
2.5V Reference
5VDIFF Reference
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Figure 3.27. ADC Integral Linearity Error vs Code, Vdd = 3V, Temp = 25°C
1.25V Reference
2.5V Reference
2XVDDVSS Reference
5VDIFF Reference
VDD Reference
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Figure 3.28. ADC Differential Linearity Error vs Code, Vdd = 3V, Temp = 25°C
1.25V Reference
2.5V Reference
2XVDDVSS Reference
5VDIFF Reference
VDD Reference
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Figure 3.29. ADC Absolute Offset, Common Mode = Vdd /2
5
4
3
2
1
0
2.0
1.5
Vref= 1V25
VRef= 1V25
Vref= 2V5
VRef= 2V5
Vref= 2XVDDVSS
Vref= 5VDIFF
Vref= VDD
VRef= 2XVDDVSS
VRef= 5VDIFF
VRef= VDD
1.0
0.5
–1
0.0
–2
–3
–4
–0.5
–1.0
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd (V)
Temp (C)
Offset vs Supply Voltage, Temp = 25°C
Offset vs Temperature, Vdd = 3V
Figure 3.30. ADC Dynamic Performance vs Temperature for all ADC References, Vdd = 3V
71
70
69
68
67
66
65
64
63
79.4
79.2
79.0
78.8
78.6
78.4
78.2
78.0
2XVDDV
Vdd
1V25
Vdd
2V5
5VDIFF
2V5
2XVDDV
5VDIFF
1V25
–40
–15
5
25
45
65
85
–40
–15
5
25
45
65
85
Temperature [°C]
Temperature [°C]
Signal to Noise Ratio (SNR)
Spurious-Free Dynamic Range (SFDR)
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Figure 3.31. ADC Temperature sensor readout
2600
2500
2400
2300
2200
2100
Vdd= 2.0
Vdd= 3.0
Vdd= 3.8
–40
–25 –15 –5
5
15 25 35 45 55 65 75 85
Temperature [°C]
3.11 Digital Analog Converter (DAC)
Table 3.16. DAC
Symbol
VDACOUT
VDACCM
Parameter
Condition
Min
Typ
Max
Unit
VDD voltage reference, single
ended
0
-VDD
0
VDD
VDD
VDD
V
Output voltage
range
VDD voltage reference, differ-
ential
V
V
Output common
mode voltage range
500 kSamples/s, 12 bit
4001
2001
171
µA
µA
µA
Active current in-
cluding references
for 2 channels
IDAC
100 kSamples/s, 12 bit
1 kSamples/s 12 bit NORMAL
SRDAC
Sample rate
500 ksam-
ples/s
Continuous Mode
Sample/Hold Mode
Sample/Off Mode
1000 kHz
250 kHz
250 kHz
DAC clock frequen-
cy
fDAC
CYCDACCONV Clock cyckles per
conversion
2
tDACCONV
Conversion time
Settling time
2
µs
µs
dB
tDACSETTLE
5
500 kSamples/s, 12 bit, sin-
gle ended, internal 1.25V refer-
ence
58
Signal to Noise Ra-
tio (SNR)
500 kSamples/s, 12 bit, single
ended, internal 2.5V reference
59
58
dB
dB
SNRDAC
500 kSamples/s, 12 bit, differ-
ential, internal 1.25V reference
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Symbol
Parameter
Condition
Min
Typ
Max
Unit
500 kSamples/s, 12 bit, differ-
ential, internal 2.5V reference
58
59
57
dB
500 kSamples/s, 12 bit, differ-
ential, VDD reference
dB
dB
500 kSamples/s, 12 bit, sin-
gle ended, internal 1.25V refer-
ence
500 kSamples/s, 12 bit, single
ended, internal 2.5V reference
54
56
53
55
62
dB
dB
dB
dB
dBc
Signal to Noise-
SNDRDAC
pulse Distortion Ra- 500 kSamples/s, 12 bit, differ-
tio (SNDR)
ential, internal 1.25V reference
500 kSamples/s, 12 bit, differ-
ential, internal 2.5V reference
500 kSamples/s, 12 bit, differ-
ential, VDD reference
500 kSamples/s, 12 bit, sin-
gle ended, internal 1.25V refer-
ence
500 kSamples/s, 12 bit, single
ended, internal 2.5V reference
56
61
55
60
dBc
dBc
dBc
dBc
Spurious-Free
Dynamic
Range(SFDR)
SFDRDAC
500 kSamples/s, 12 bit, differ-
ential, internal 1.25V reference
500 kSamples/s, 12 bit, differ-
ential, internal 2.5V reference
500 kSamples/s, 12 bit, differ-
ential, VDD reference
After calibration, single ended
After calibration, differential
2
2
9
mV
mV
LSB
VDACOFFSET
DNLDAC
INLDAC
Offset voltage
Differential non-lin-
earity
±1
Integral non-lineari-
ty
±5
12
LSB
bits
MCDAC
No missing codes
1Measured with a static input code and no loading on the output.
3.12 Operational Amplifier (OPAMP)
The electrical characteristics for the Operational Amplifiers are based on simulations.
Table 3.17. OPAMP
Symbol
Parameter
Condition
Min
Typ
Max
Unit
(OPA2)BIASPROG=0xF,
(OPA2)HALFBIAS=0x0, Unity
Gain
370
95
460 µA
IOPAMP
Active Current
(OPA2)BIASPROG=0x7,
(OPA2)HALFBIAS=0x1, Unity
Gain
135 µA
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Symbol
Parameter
Condition
Min
Typ
Max
Unit
25 µA
(OPA2)BIASPROG=0x0,
(OPA2)HALFBIAS=0x1, Unity
Gain
13
(OPA2)BIASPROG=0xF,
(OPA2)HALFBIAS=0x0
101
98
dB
(OPA2)BIASPROG=0x7,
(OPA2)HALFBIAS=0x1
dB
GOL
Open Loop Gain
(OPA2)BIASPROG=0x0,
(OPA2)HALFBIAS=0x1
91
dB
(OPA2)BIASPROG=0xF,
(OPA2)HALFBIAS=0x0
6.1
1.8
0.25
64
MHz
MHz
MHz
°
Gain Bandwidth
Product
(OPA2)BIASPROG=0x7,
(OPA2)HALFBIAS=0x1
GBWOPAMP
(OPA2)BIASPROG=0x0,
(OPA2)HALFBIAS=0x1
(OPA2)BIASPROG=0xF,
(OPA2)HALFBIAS=0x0, CL=75
pF
(OPA2)BIASPROG=0x7,
(OPA2)HALFBIAS=0x1, CL=75
pF
58
58
°
°
PMOPAMP
Phase Margin
(OPA2)BIASPROG=0x0,
(OPA2)HALFBIAS=0x1, CL=75
pF
RINPUT
RLOAD
Input Resistance
Load Resistance
DC Load Current
100
Mohm
Ohm
200
ILOAD_DC
11 mA
OPAxHCMDIS=0
OPAxHCMDIS=1
VSS
VSS
VSS
-13
VDD
V
V
V
VINPUT
Input Voltage
VDD-1.2
VDD
VOUTPUT
Output Voltage
Unity Gain, VSS<Vin<VDD
OPAxHCMDIS=0
,
0
1
11 mV
VOFFSET
Input Offset Voltage
Unity Gain, VSS<Vin<DD-1.2,
OPAxHCMDIS=1
mV
VOFFSET_DRIFT Input Offset Voltage
Drift
0.02 mV/°C
V/µs
(OPA2)BIASPROG=0xF,
(OPA2)HALFBIAS=0x0
3.2
0.8
0.1
101
(OPA2)BIASPROG=0x7,
(OPA2)HALFBIAS=0x1
V/µs
SROPAMP
Slew Rate
(OPA2)BIASPROG=0x0,
(OPA2)HALFBIAS=0x1
V/µs
Vout=1V, RESSEL=0,
0.1 Hz<f<10 kHz, OPAx-
HCMDIS=0
µVRMS
NOPAMP
Voltage Noise
Vout=1V, RESSEL=0,
0.1 Hz<f<10 kHz, OPAx-
HCMDIS=1
141
µVRMS
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Symbol
Parameter
Condition
Min
Typ
Max
Unit
Vout=1V, RESSEL=0, 0.1
Hz<f<1 MHz, OPAxHCMDIS=0
196
229
µVRMS
Vout=1V, RESSEL=0, 0.1
Hz<f<1 MHz, OPAxHCMDIS=1
µVRMS
µVRMS
µVRMS
µVRMS
µVRMS
RESSEL=7, 0.1 Hz<f<10 kHz,
OPAxHCMDIS=0
1230
2130
1630
2590
RESSEL=7, 0.1 Hz<f<10 kHz,
OPAxHCMDIS=1
RESSEL=7, 0.1 Hz<f<1 MHz,
OPAxHCMDIS=0
RESSEL=7, 0.1 Hz<f<1 MHz,
OPAxHCMDIS=1
Figure 3.32. OPAMP Common Mode Rejection Ratio
Figure 3.33. OPAMP Positive Power Supply Rejection Ratio
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Figure 3.34. OPAMP Negative Power Supply Rejection Ratio
Figure 3.35. OPAMP Voltage Noise Spectral Density (Unity Gain) Vout=1V
Figure 3.36. OPAMP Voltage Noise Spectral Density (Non-Unity Gain)
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3.13 Analog Comparator (ACMP)
Table 3.18. ACMP
Symbol
VACMPIN
VACMPCM
Parameter
Condition
Min
Typ
Max
Unit
V
Input voltage range
0
0
VDD
VDD
ACMP Common
V
Mode voltage range
BIASPROG=0b0000, FULL-
BIAS=0 and HALFBIAS=1 in
ACMPn_CTRL register
0.1
2.87
195
0
0.4 µA
15 µA
520 µA
µA
BIASPROG=0b1111, FULL-
BIAS=0 and HALFBIAS=0 in
ACMPn_CTRL register
IACMP
Active current
BIASPROG=0b1111, FULL-
BIAS=1 and HALFBIAS=0 in
ACMPn_CTRL register
Internal voltage reference off.
Using external voltage refer-
ence
Current consump-
tion of internal volt-
age reference
IACMPREF
Internal voltage reference
5
0
µA
VACMPOFFSET Offset voltage
BIASPROG= 0b1010, FULL-
BIAS=0 and HALFBIAS=0 in
ACMPn_CTRL register
-12
12 mV
VACMPHYST
ACMP hysteresis
Programmable
17
39
mV
CSRESSEL=0b00 in
ACMPn_INPUTSEL
kOhm
CSRESSEL=0b01 in
ACMPn_INPUTSEL
71
104
136
kOhm
kOhm
kOhm
Capacitive Sense
Internal Resistance
RCSRES
CSRESSEL=0b10 in
ACMPn_INPUTSEL
CSRESSEL=0b11 in
ACMPn_INPUTSEL
tACMPSTART
Startup time
10 µs
The total ACMP current is the sum of the contributions from the ACMP and its internal voltage reference
as given in Equation 3.1 (p. 46) . IACMPREF is zero if an external voltage reference is used.
Total ACMP Active Current
IACMPTOTAL = IACMP + IACMPREF
(3.1)
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Figure 3.37. ACMP Characteristics, Vdd = 3V, Temp = 25°C, FULLBIAS = 0, HALFBIAS = 1
2.5
2.0
1.5
1.0
0.5
0.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
HYSTSEL= 0.0
HYSTSEL= 2.0
HYSTSEL= 4.0
HYSTSEL= 6.0
0
4
8
12
0
2
4
6
8
10
12
14
ACMP_CTRL_BIASPROG
ACMP_CTRL_BIASPROG
Current consumption, HYSTSEL = 4
Response time
100
80
60
40
20
0
BIASPROG= 0.0
BIASPROG= 4.0
BIASPROG= 8.0
BIASPROG= 12.0
0
1
2
3
4
5
6
7
ACMP_CTRL_HYSTSEL
Hysteresis
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3.14 Voltage Comparator (VCMP)
Table 3.19. VCMP
Symbol
VVCMPIN
VVCMPCM
Parameter
Condition
Min
Typ
Max
Unit
V
Input voltage range
VDD
VDD
VCMP Common
V
Mode voltage range
BIASPROG=0b0000 and
HALFBIAS=1 in VCMPn_CTRL
register
0.3
22
10
0.6 µA
IVCMP
Active current
BIASPROG=0b1111 and
HALFBIAS=0 in VCMPn_CTRL
register. LPREF=0.
35 µA
µs
tVCMPREF
Startup time refer-
ence generator
NORMAL
Single ended
Differential
10
10
61
mV
mV
VVCMPOFFSET Offset voltage
VVCMPHYST
tVCMPSTART
VCMP hysteresis
Startup time
210 mV
10 µs
The VDD trigger level can be configured by setting the TRIGLEVEL field of the VCMP_CTRL register in
accordance with the following equation:
VCMP Trigger Level as a Function of Level Setting
VDD Trigger Level=1.667V+0.034 ×TRIGLEVEL
(3.2)
3.15 I2C
Table 3.20. I2C Standard-mode (Sm)
Symbol
fSCL
Parameter
Min
Typ
Max
Unit
SCL clock frequency
0
4.7
4.0
250
8
1001 kHz
tLOW
SCL clock low time
µs
tHIGH
SCL clock high time
µs
tSU,DAT
tHD,DAT
tSU,STA
tHD,STA
tSU,STO
tBUF
SDA set-up time
ns
SDA hold time
34502,3 ns
Repeated START condition set-up time
(Repeated) START condition hold time
STOP condition set-up time
4.7
4.0
4.0
4.7
µs
µs
µs
µs
Bus free time between a STOP and a START condi-
tion
1For the minimum HFPERCLK frequency required in Standard-mode, see the I2C chapter in the EFM32WG Reference Manual.
2The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW).
3When transmitting data, this number is guaranteed only when I2Cn_CLKDIV < ((3450*10-9 [s] * fHFPERCLK [Hz]) - 4).
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Table 3.21. I2C Fast-mode (Fm)
Symbol
fSCL
Parameter
Min
Typ
Max
Unit
SCL clock frequency
0
1.3
0.6
100
8
4001 kHz
tLOW
SCL clock low time
µs
tHIGH
SCL clock high time
µs
tSU,DAT
tHD,DAT
tSU,STA
tHD,STA
tSU,STO
tBUF
SDA set-up time
ns
SDA hold time
9002,3 ns
Repeated START condition set-up time
(Repeated) START condition hold time
STOP condition set-up time
0.6
0.6
0.6
1.3
µs
µs
µs
µs
Bus free time between a STOP and a START condi-
tion
1For the minimum HFPERCLK frequency required in Fast-mode, see the I2C chapter in the EFM32WG Reference Manual.
2The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW).
3When transmitting data, this number is guaranteed only when I2Cn_CLKDIV < ((900*10-9 [s] * fHFPERCLK [Hz]) - 4).
Table 3.22. I2C Fast-mode Plus (Fm+)
Symbol
fSCL
Parameter
Min
Typ
Max
Unit
SCL clock frequency
0
0.5
10001 kHz
tLOW
SCL clock low time
µs
µs
ns
ns
µs
µs
µs
µs
tHIGH
SCL clock high time
0.26
50
tSU,DAT
tHD,DAT
tSU,STA
tHD,STA
tSU,STO
tBUF
SDA set-up time
SDA hold time
8
Repeated START condition set-up time
(Repeated) START condition hold time
STOP condition set-up time
0.26
0.26
0.26
0.5
Bus free time between a STOP and a START condi-
tion
1For the minimum HFPERCLK frequency required in Fast-mode Plus, see the I2C chapter in the EFM32WG Reference Manual.
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3.16 USART SPI
Figure 3.38. SPI Master Timing
tCS_MO
CS
tSCKL_MO
SCLK
CLKPOL = 0
tSCLK
SCLK
CLKPOL = 1
MOSI
MISO
tSU_MI
tH_MI
Table 3.23. SPI Master Timing
Symbol
Parameter
Condition
Min
2 * tHFPER-
Typ
Max
Unit
1 2
tSCLK
SCLK period
ns
CLK
1 2
tCS_MO
CS to MOSI
-2.00
2.00 ns
1 2
tSCLK_MO
SCLK to MOSI
MISO setup time
MISO hold time
-1.00
36.00
-6.00
3.00 ns
1 2
tSU_MI
IOVDD = 3.0 V
ns
ns
1 2
tH_MI
1Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0)
2Measurement done at 10% and 90% of VDD (figure shows 50% of VDD
)
Table 3.24. SPI Master Timing with SSSEARLY and SMSDELAY
Symbol
Parameter
Condition
Min
2 * tHFPER-
Typ
Max
Unit
1 2
tSCLK
SCLK period
ns
CLK
12
tCS_MO
CS to MOSI
-2.00
2.00 ns
3.00 ns
ns
12
tSCLK_MO
SCLK to MOSI
MISO setup time
MISO hold time
-1.00
-32.00
63.00
12
tSU_MI
IOVDD = 3.0 V
12
tH_MI
ns
1Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0)
2Measurement done at 10% and 90% of VDD (figure shows 50% of VDD
)
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Figure 3.39. SPI Slave Timing
tCS_ACT_MI
CS
tCS_DIS_MI
SCLK
CLKPOL = 0
tSCLK_HI
tSCLK_LO
SCLK
tSU_MO
CLKPOL = 1
tSCLK
tH_MO
MOSI
MISO
tSCLK_MI
Table 3.25. SPI Slave Timing
Symbol
Parameter
Min
Typ
Max
Unit
1 2
tSCLK_sl
tSCLK_hi
tSCLK_lo
SCKL period
6 * tHFPER-
ns
CLK
1 2
1 2
SCLK high period
SCLK low period
3 * tHFPER-
ns
ns
CLK
3 * tHFPER-
CLK
1 2
tCS_ACT_MI
CS active to MISO
CS disable to MISO
MOSI setup time
MOSI hold time
5.00
5.00
5.00
35.00 ns
1 2
tCS_DIS_MI
35.00 ns
1 2
tSU_MO
ns
ns
1 2
tH_MO
2 + 2 * tHF-
PERCLK
1 2
tSCLK_MI
SCLK to MISO
7 + tHFPER-
42 + 2 * ns
tHFPERCLK
CLK
1Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0)
2Measurement done at 10% and 90% of VDD (figure shows 50% of VDD
)
Table 3.26. SPI Slave Timing with SSSEARLY and SMSDELAY
Symbol
Parameter
Min
6 * tHFPER-
Typ
Max
Unit
12
tSCLK_sl
tSCLK_hi
tSCLK_lo
SCKL period
ns
ns
ns
CLK
12
12
SCLK high period
SCLK low period
3 * tHFPER-
CLK
3 * tHFPER-
CLK
12
tCS_ACT_MI
CS active to MISO
CS disable to MISO
MOSI setup time
MOSI hold time
5.00
5.00
5.00
35.00 ns
35.00 ns
ns
12
tCS_DIS_MI
12
tSU_MO
12
tH_MO
2 + 2 * tHF-
ns
PERCLK
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Symbol
Parameter
Min
-264 + tHF-
Typ
Max
Unit
12
tSCLK_MI
SCLK to MISO
-234 + 2 * ns
tHFPERCLK
PERCLK
1Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0)
2Measurement done at 10% and 90% of VDD (figure shows 50% of VDD
)
3.17 Digital Peripherals
Table 3.27. Digital Peripherals
Symbol
Parameter
Condition
Min
Typ
Max
Unit
IUSART
USART current
USART idle current, clock en-
abled
4.0
3.8
µA/
MHz
IUART
UART current
LEUART current
I2C current
UART idle current, clock en-
abled
µA/
MHz
ILEUART
LEUART idle current, clock en-
abled
194.0
7.6
nA
II2C
I2C idle current, clock enabled
µA/
MHz
ITIMER
ILETIMER
IPCNT
TIMER current
LETIMER current
PCNT current
TIMER_0 idle current, clock
enabled
6.5
µA/
MHz
LETIMER idle current, clock
enabled
85.8
91.4
nA
nA
nA
PCNT idle current, clock en-
abled
IRTC
IAES
RTC current
AES current
RTC idle current, clock enabled
AES idle current, clock enabled
54.6
1.8
µA/
MHz
IGPIO
IPRS
IDMA
GPIO current
PRS current
DMA current
GPIO idle current, clock en-
abled
3.4
3.9
µA/
MHz
PRS idle current
µA/
MHz
Clock enable
10.9
µA/
MHz
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4 Pinout and Package
Note
Please refer to the application note "AN0002 EFM32 Hardware Design Considerations" for
guidelines on designing Printed Circuit Boards (PCB's) for the EFM32WG232.
4.1 Pinout
The EFM32WG232 pinout is shown in Figure 4.1 (p. 53) and Table 4.1 (p. 53). Alternate locations
are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/").
Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module
in question.
Figure 4.1. EFM32WG232 Pinout (top view, not to scale)
Table 4.1. Device Pinout
QFP64 Pin#
and Name
Pin Alternate Functionality / Description
Pin Name
Analog
Timers
Communication
Other
LEU0_RX #4
I2C0_SDA #0
PRS_CH0 #0
GPIO_EM4WU0
1
PA0
TIM0_CC0 #0/1/4
CMU_CLK1 #0
PRS_CH1 #0
2
3
PA1
PA2
TIM0_CC1 #0/1
TIM0_CC2 #0/1
I2C0_SCL #0
CMU_CLK0 #0
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QFP64 Pin#
and Name
Pin Alternate Functionality / Description
Pin Name
Analog
Timers
Communication
Other
ETM_TD0 #3
LES_ALTEX2 #0
ETM_TD1 #3
4
5
6
PA3
PA4
PA5
TIM0_CDTI0 #0
TIM0_CDTI1 #0
TIM0_CDTI2 #0
LES_ALTEX3 #0
ETM_TD2 #3
LES_ALTEX4 #0
ETM_TD3 #3
LEU1_TX #1
7
8
IOVDD_0
VSS
Digital IO power supply 0.
Ground
ACMP0_CH0
DAC0_OUT0ALT #0/
OPAMP_OUT0ALT
US0_TX #5
US1_TX #0
I2C0_SDA #4
TIM0_CC1 #4
PCNT0_S0IN #2
LES_CH0 #0
PRS_CH2 #0
9
PC0
PC1
PC2
PC3
PC4
PC5
ACMP0_CH1
DAC0_OUT0ALT #1/
OPAMP_OUT0ALT
US0_RX #5
US1_RX #0
I2C0_SCL #4
TIM0_CC2 #4
PCNT0_S1IN #2
LES_CH1 #0
PRS_CH3 #0
10
11
12
13
14
ACMP0_CH2
DAC0_OUT0ALT #2/
OPAMP_OUT0ALT
TIM0_CDTI0 #4
TIM0_CDTI1 #4
US2_TX #0
US2_RX #0
LES_CH2 #0
LES_CH3 #0
LES_CH4 #0
LES_CH5 #0
ACMP0_CH3
DAC0_OUT0ALT #3/
OPAMP_OUT0ALT
ACMP0_CH4
DAC0_P0 /
OPAMP_P0
TIM0_CDTI2 #4
LETIM0_OUT0 #3
PCNT1_S0IN #0
US2_CLK #0
I2C1_SDA #0
ACMP0_CH5
DAC0_N0 /
OPAMP_N0
LETIM0_OUT1 #3
PCNT1_S1IN #0
US2_CS #0
I2C1_SCL #0
US0_TX #4
US1_CLK #0
15
16
PB7
PB8
LFXTAL_P
LFXTAL_N
TIM1_CC0 #3
TIM1_CC1 #3
US0_RX #4
US1_CS #0
17
18
19
PA8
PA9
TIM2_CC0 #0
TIM2_CC1 #0
TIM2_CC2 #0
PA10
Reset input, active low.
20
21
RESETn
PB11
To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up en-
sure that reset is released.
DAC0_OUT0 /
OPAMP_OUT0
TIM1_CC2 #3
LETIM0_OUT0 #1
I2C1_SDA #1
22
23
VSS
Ground
AVDD_1
Analog power supply 1.
HFXTAL_P
US0_CLK #4/5
LEU0_TX #1
24
25
PB13
PB14
US0_CS #4/5
LEU0_RX #1
HFXTAL_N
26
27
IOVDD_3
AVDD_0
Digital IO power supply 3.
Analog power supply 0.
ADC0_CH0
DAC0_OUT0ALT #4/
OPAMP_OUT0ALT
OPAMP_OUT2 #1
28
29
PD0
PD1
PCNT2_S0IN #0
US1_TX #1
US1_RX #1
ADC0_CH1
DAC0_OUT1ALT #4/
TIM0_CC0 #3
PCNT2_S1IN #0
DBG_SWO #2
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QFP64 Pin#
and Name
Pin Alternate Functionality / Description
Pin Name
Analog
Timers
Communication
Other
OPAMP_OUT1ALT
ADC0_CH2
30
31
PD2
PD3
TIM0_CC1 #3
TIM0_CC2 #3
US1_CLK #1
US1_CS #1
DBG_SWO #3
ETM_TD1 #0/2
ADC0_CH3
OPAMP_N2
ADC0_CH4
OPAMP_P2
32
33
PD4
PD5
LEU0_TX #0
LEU0_RX #0
ETM_TD2 #0/2
ETM_TD3 #0/2
ADC0_CH5
OPAMP_OUT2 #0
ADC0_CH6
DAC0_P1 /
OPAMP_P1
TIM1_CC0 #4
LETIM0_OUT0 #0
PCNT0_S0IN #3
LES_ALTEX0 #0
ACMP0_O #2
ETM_TD0 #0
US1_RX #2
I2C0_SDA #1
34
35
PD6
PD7
CMU_CLK0 #2
LES_ALTEX1 #0
ACMP1_O #2
ADC0_CH7
DAC0_N1 /
OPAMP_N1
TIM1_CC1 #4
LETIM0_OUT1 #0
PCNT0_S1IN #3
US1_TX #2
I2C0_SCL #1
ETM_TCLK #0
36
37
PD8
PC6
BU_VIN
CMU_CLK1 #1
LEU1_TX #0
I2C0_SDA #2
LES_CH6 #0
ETM_TCLK #2
ACMP0_CH6
LEU1_RX #0
I2C0_SCL #2
LES_CH7 #0
ETM_TD0 #2
38
PC7
ACMP0_CH7
39
40
41
VDD_DREG
DECOUPLE
PC8
Power supply for on-chip voltage regulator.
Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin.
ACMP1_CH0
ACMP1_CH1
TIM2_CC0 #2
TIM2_CC1 #2
TIM2_CC2 #2
US0_CS #2
LES_CH8 #0
LES_CH9 #0
GPIO_EM4WU2
42
PC9
US0_CLK #2
43
44
PC10
PC11
ACMP1_CH2
ACMP1_CH3
US0_RX #2
US0_TX #2
LES_CH10 #0
LES_CH11 #0
ACMP1_CH4
DAC0_OUT1ALT #0/
OPAMP_OUT1ALT
CMU_CLK0 #1
LES_CH12 #0
45
46
PC12
PC13
TIM0_CDTI0 #1/3
TIM1_CC0 #0
TIM1_CC2 #4
ACMP1_CH5
DAC0_OUT1ALT #1/
OPAMP_OUT1ALT
LES_CH13 #0
LES_CH14 #0
PCNT0_S0IN #0
ACMP1_CH6
DAC0_OUT1ALT #2/
OPAMP_OUT1ALT
TIM0_CDTI1 #1/3
TIM1_CC1 #0
PCNT0_S1IN #0
47
48
49
50
PC14
PC15
PF0
US0_CS #3
ACMP1_CH7
DAC0_OUT1ALT #3/
OPAMP_OUT1ALT
TIM0_CDTI2 #1/3
TIM1_CC2 #0
LES_CH15 #0
DBG_SWO #1
US0_CLK #3
US1_CLK #2
LEU0_TX #3
I2C0_SDA #5
TIM0_CC0 #5
LETIM0_OUT0 #2
DBG_SWCLK #0/1/2/3
US1_CS #2
LEU0_RX #3
I2C0_SCL #5
TIM0_CC1 #5
LETIM0_OUT1 #2
DBG_SWDIO #0/1/2/3
GPIO_EM4WU3
PF1
ACMP1_O #0
DBG_SWO #0
GPIO_EM4WU4
51
52
PF2
PF3
TIM0_CC2 #5
LEU0_TX #4
PRS_CH0 #1
ETM_TD3 #1
TIM0_CDTI0 #2/5
53
54
PF4
PF5
TIM0_CDTI1 #2/5
TIM0_CDTI2 #2/5
PRS_CH1 #1
PRS_CH2 #1
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QFP64 Pin#
and Name
Pin Alternate Functionality / Description
Pin Name
Analog
Timers
Communication
Other
55
56
57
58
59
IOVDD_5
VSS
Digital IO power supply 5.
Ground
PE8
PCNT2_S0IN #1
PCNT2_S1IN #1
TIM1_CC0 #1
PRS_CH3 #1
BOOT_TX
PE9
PE10
US0_TX #0
US0_RX #0
LES_ALTEX5 #0
BOOT_RX
60
61
PE11
PE12
TIM1_CC1 #1
TIM1_CC2 #1
US0_RX #3
US0_CLK #0
I2C0_SDA #6
CMU_CLK1 #2
LES_ALTEX6 #0
US0_TX #3
US0_CS #0
I2C0_SCL #6
LES_ALTEX7 #0
ACMP0_O #0
GPIO_EM4WU5
62
PE13
63
64
PE14
PE15
TIM3_CC0 #0
TIM3_CC1 #0
LEU0_TX #2
LEU0_RX #2
4.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in
Table 4.2 (p. 56). The table shows the name of the alternate functionality in the first column, followed
by columns showing the possible LOCATION bitfield settings.
Note
Some functionality, such as analog interfaces, do not have alternate settings or a LOCA-
TION bitfield. In these cases, the pinout is shown in the column corresponding to LOCA-
TION 0.
Table 4.2. Alternate functionality overview
Alternate
LOCATION
3
Functionality
ACMP0_CH0
ACMP0_CH1
ACMP0_CH2
ACMP0_CH3
ACMP0_CH4
ACMP0_CH5
ACMP0_CH6
ACMP0_CH7
ACMP0_O
0
1
2
4
5
6
Description
Analog comparator ACMP0, channel 0.
Analog comparator ACMP0, channel 1.
Analog comparator ACMP0, channel 2.
Analog comparator ACMP0, channel 3.
Analog comparator ACMP0, channel 4.
Analog comparator ACMP0, channel 5.
Analog comparator ACMP0, channel 6.
Analog comparator ACMP0, channel 7.
Analog comparator ACMP0, digital output.
Analog comparator ACMP1, channel 0.
Analog comparator ACMP1, channel 1.
Analog comparator ACMP1, channel 2.
Analog comparator ACMP1, channel 3.
Analog comparator ACMP1, channel 4.
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PE13
PC8
PC9
PC10
PC11
PC12
PD6
ACMP1_CH0
ACMP1_CH1
ACMP1_CH2
ACMP1_CH3
ACMP1_CH4
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Alternate
LOCATION
3
Functionality
ACMP1_CH5
ACMP1_CH6
ACMP1_CH7
ACMP1_O
0
PC13
PC14
PC15
PF2
1
2
4
5
6
Description
Analog comparator ACMP1, channel 5.
Analog comparator ACMP1, channel 6.
Analog comparator ACMP1, channel 7.
PD7
Analog comparator ACMP1, digital output.
Analog to digital converter ADC0, input channel number 0.
Analog to digital converter ADC0, input channel number 1.
Analog to digital converter ADC0, input channel number 2.
Analog to digital converter ADC0, input channel number 3.
Analog to digital converter ADC0, input channel number 4.
Analog to digital converter ADC0, input channel number 5.
Analog to digital converter ADC0, input channel number 6.
Analog to digital converter ADC0, input channel number 7.
Bootloader RX
ADC0_CH0
ADC0_CH1
ADC0_CH2
ADC0_CH3
ADC0_CH4
ADC0_CH5
ADC0_CH6
ADC0_CH7
BOOT_RX
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PE11
PE10
PD8
PA2
BOOT_TX
Bootloader TX
BU_VIN
Battery input for Backup Power Domain
CMU_CLK0
CMU_CLK1
PC12
PD8
PD7
Clock Management Unit, clock output number 0.
Clock Management Unit, clock output number 1.
PA1
PE12
DAC0_N0 /
OPAMP_N0
PC5
Operational Amplifier 0 external negative input.
DAC0_N1 /
OPAMP_N1
PD7
PD3
PB11
Operational Amplifier 1 external negative input.
Operational Amplifier 2 external negative input.
OPAMP_N2
DAC0_OUT0 /
OPAMP_OUT0
Digital to Analog Converter DAC0_OUT0 /
OPAMP output channel number 0.
DAC0_OUT0ALT /
OPAMP_OUT0ALT
Digital to Analog Converter DAC0_OUT0ALT /
OPAMP alternative output for channel 0.
PC0
PC1
PC2
PC3
PD0
DAC0_OUT1ALT /
OPAMP_OUT1ALT
Digital to Analog Converter DAC0_OUT1ALT /
OPAMP alternative output for channel 1.
PC12
PD5
PC4
PC13
PD0
PC14
PC15
PD1
OPAMP_OUT2
Operational Amplifier 2 output.
DAC0_P0 /
OPAMP_P0
Operational Amplifier 0 external positive input.
DAC0_P1 /
OPAMP_P1
PD6
PD4
Operational Amplifier 1 external positive input.
OPAMP_P2
Operational Amplifier 2 external positive input.
Debug-interface Serial Wire clock input.
DBG_SWCLK
PF0
PF1
PF2
PF0
PF0
PF1
PD1
PF0
PF1
PD2
Note that this function is enabled to pin out of reset, and has
a built-in pull down.
Debug-interface Serial Wire data input / output.
DBG_SWDIO
DBG_SWO
PF1
Note that this function is enabled to pin out of reset, and has
a built-in pull up.
Debug-interface Serial Wire viewer Output.
PC15
Note that this function is not enabled after reset, and must be
enabled by software to be used.
ETM_TCLK
ETM_TD0
ETM_TD1
ETM_TD2
PD7
PD6
PD3
PD4
PC6
PC7
PD3
PD4
Embedded Trace Module ETM clock .
Embedded Trace Module ETM data 0.
Embedded Trace Module ETM data 1.
Embedded Trace Module ETM data 2.
PA2
PA3
PA4
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Alternate
LOCATION
Functionality
ETM_TD3
0
1
2
3
4
5
6
Description
PD5
PF3
PD5
PA5
Embedded Trace Module ETM data 3.
GPIO_EM4WU0
GPIO_EM4WU2
GPIO_EM4WU3
GPIO_EM4WU4
GPIO_EM4WU5
PA0
PC9
PF1
PF2
PE13
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
High Frequency Crystal negative pin. Also used as external
optional clock input pin.
HFXTAL_N
PB14
HFXTAL_P
I2C0_SCL
PB13
PA1
High Frequency Crystal positive pin.
I2C0 Serial Clock Line input / output.
I2C0 Serial Data input / output.
I2C1 Serial Clock Line input / output.
I2C1 Serial Data input / output.
LESENSE alternate exite output 0.
LESENSE alternate exite output 1.
LESENSE alternate exite output 2.
LESENSE alternate exite output 3.
LESENSE alternate exite output 4.
LESENSE alternate exite output 5.
LESENSE alternate exite output 6.
LESENSE alternate exite output 7.
LESENSE channel 0.
PD7
PD6
PC7
PC6
PC1
PF1
PF0
PE13
PE12
I2C0_SDA
I2C1_SCL
PA0
PC0
PC5
PC4
PD6
PD7
PA3
I2C1_SDA
LES_ALTEX0
LES_ALTEX1
LES_ALTEX2
LES_ALTEX3
LES_ALTEX4
LES_ALTEX5
LES_ALTEX6
LES_ALTEX7
LES_CH0
PB11
PA4
PA5
PE11
PE12
PE13
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
PD6
PD7
PD5
LES_CH1
LESENSE channel 1.
LES_CH2
LESENSE channel 2.
LES_CH3
LESENSE channel 3.
LES_CH4
LESENSE channel 4.
LES_CH5
LESENSE channel 5.
LES_CH6
LESENSE channel 6.
LES_CH7
LESENSE channel 7.
LES_CH8
LESENSE channel 8.
LES_CH9
LESENSE channel 9.
LES_CH10
LES_CH11
LES_CH12
LES_CH13
LES_CH14
LES_CH15
LETIM0_OUT0
LETIM0_OUT1
LEU0_RX
LESENSE channel 10.
LESENSE channel 11.
LESENSE channel 12.
LESENSE channel 13.
LESENSE channel 14.
LESENSE channel 15.
PB11
PF0
PC4
PC5
PF1
Low Energy Timer LETIM0, output channel 0.
Low Energy Timer LETIM0, output channel 1.
LEUART0 Receive input.
PF1
PB14
PB13
PE15
PA0
PF2
LEUART0 Transmit output. Also used as receive input in half
duplex communication.
LEU0_TX
PD4
PE14
PF0
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Alternate
LOCATION
3
Functionality
0
1
2
4
5
6
Description
LEU1_RX
PC7
LEUART1 Receive input.
LEUART1 Transmit output. Also used as receive input in half
duplex communication.
LEU1_TX
PC6
PB8
PA5
Low Frequency Crystal (typically 32.768 kHz) negative pin.
Also used as an optional external clock input pin.
LFXTAL_N
LFXTAL_P
PCNT0_S0IN
PCNT0_S1IN
PCNT1_S0IN
PCNT1_S1IN
PCNT2_S0IN
PCNT2_S1IN
PRS_CH0
PB7
Low Frequency Crystal (typically 32.768 kHz) positive pin.
Pulse Counter PCNT0 input number 0.
PC13
PC14
PC4
PC5
PD0
PD1
PA0
PC0
PC1
PD6
PD7
Pulse Counter PCNT0 input number 1.
Pulse Counter PCNT1 input number 0.
Pulse Counter PCNT1 input number 1.
PE8
Pulse Counter PCNT2 input number 0.
PE9
Pulse Counter PCNT2 input number 1.
PF3
Peripheral Reflex System PRS, channel 0.
Peripheral Reflex System PRS, channel 1.
Peripheral Reflex System PRS, channel 2.
Peripheral Reflex System PRS, channel 3.
Timer 0 Capture Compare input / output channel 0.
Timer 0 Capture Compare input / output channel 1.
Timer 0 Capture Compare input / output channel 2.
Timer 0 Complimentary Deat Time Insertion channel 0.
Timer 0 Complimentary Deat Time Insertion channel 1.
Timer 0 Complimentary Deat Time Insertion channel 2.
Timer 1 Capture Compare input / output channel 0.
Timer 1 Capture Compare input / output channel 1.
Timer 1 Capture Compare input / output channel 2.
Timer 2 Capture Compare input / output channel 0.
Timer 2 Capture Compare input / output channel 1.
Timer 2 Capture Compare input / output channel 2.
Timer 3 Capture Compare input / output channel 0.
Timer 3 Capture Compare input / output channel 1.
USART0 clock input / output.
PRS_CH1
PA1
PF4
PRS_CH2
PC0
PC1
PA0
PF5
PRS_CH3
PE8
TIM0_CC0
TIM0_CC1
TIM0_CC2
TIM0_CDTI0
TIM0_CDTI1
TIM0_CDTI2
TIM1_CC0
TIM1_CC1
TIM1_CC2
TIM2_CC0
TIM2_CC1
TIM2_CC2
TIM3_CC0
TIM3_CC1
US0_CLK
PA0
PD1
PA0
PC0
PF0
PF1
PF2
PF3
PF4
PF5
PA1
PA1
PD2
PA2
PA2
PD3
PC1
PC2
PC3
PC4
PD6
PD7
PC13
PA3
PC13
PC14
PC15
PE10
PE11
PE12
PF3
PF4
PF5
PC13
PC14
PC15
PB7
PA4
PA5
PC13
PC14
PC15
PA8
PB8
PB11
PC8
PC9
PC10
PA9
PA10
PE14
PE15
PE12
PE13
PC9
PC8
PC15
PC14
PB13
PB14
PB13
PB14
US0_CS
USART0 chip select input / output.
USART0 Asynchronous Receive.
US0_RX
US0_TX
PE11
PE10
PC10
PC11
PE12
PE13
PB8
PB7
PC1
PC0
USART0 Synchronous mode Master Input / Slave Output
(MISO).
USART0 Asynchronous Transmit.Also used as receive input
in half duplex communication.
USART0 Synchronous mode Master Output / Slave Input
(MOSI).
US1_CLK
US1_CS
PB7
PB8
PD2
PD3
PF0
PF1
USART1 clock input / output.
USART1 chip select input / output.
USART1 Asynchronous Receive.
US1_RX
PC1
PD1
PD6
USART1 Synchronous mode Master Input / Slave Output
(MISO).
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Alternate
LOCATION
3
Functionality
0
1
2
4
5
6
Description
USART1 Asynchronous Transmit.Also used as receive input
in half duplex communication.
US1_TX
PC0
PD0
PD7
USART1 Synchronous mode Master Output / Slave Input
(MOSI).
US2_CLK
US2_CS
PC4
PC5
USART2 clock input / output.
USART2 chip select input / output.
USART2 Asynchronous Receive.
US2_RX
US2_TX
PC3
PC2
USART2 Synchronous mode Master Input / Slave Output
(MISO).
USART2 Asynchronous Transmit.Also used as receive input
in half duplex communication.
USART2 Synchronous mode Master Output / Slave Input
(MOSI).
4.3 GPIO Pinout Overview
The specific GPIO pins available in EFM32WG232 is shown in Table 4.3 (p. 60). Each GPIO port is
organized as 16-bit ports indicated by letters A through F, and the individual pin on this port in indicated
by a number from 15 down to 0.
Table 4.3. GPIO Pinout
Port
Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin
Pin
0
15
14
13
12
11
10
PA10
-
9
PA9
-
8
7
6
5
PA5
-
4
PA4
-
3
PA3
-
2
PA2
-
1
PA1
-
Port A
Port B
Port C
Port D
Port E
Port F
-
-
-
-
-
-
-
PA8
PB8
PC8
PD8
PE8
-
-
-
PA0
-
PB14 PB13
PB11
PB7
PC7
PD7
-
-
PC6
PD6
-
PC15 PC14 PC13 PC12 PC11 PC10
PC9
-
PC5
PD5
-
PC4
PD4
-
PC3
PD3
-
PC2
PD2
-
PC1
PD1
-
PC0
PD0
-
-
-
-
-
-
-
PE15 PE14 PE13 PE12 PE11 PE10
PE9
-
-
-
-
-
-
-
-
-
PF5
PF4
PF3
PF2
PF1
PF0
4.4 Opamp Pinout Overview
The specific opamp terminals available in EFM32WG232 is shown in Figure 4.2 (p. 61) .
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Figure 4.2. Opamp Pinout
PB11
PB12
OUT0ALT
PC4
PC5
+
PC0
OPA0
-
OUT0
PC1
PC2
PC3
+
PD4
PD3
PC12
PC13
PC14
PC15
PD0
OPA2
-
OUT2
PD6
PD7
OUT1ALT
OUT1
+
OPA1
-
PD1
PD5
4.5 TQFP64 Package
Figure 4.3. TQFP64
Note:
1. All dimensions & tolerancing confirm to ASME Y14.5M-1994.
2. The top package body size may be smaller than the bottom package body size.
3. Datum 'A,B', and 'B' to be determined at datum plane 'H'.
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4. To be determined at seating place 'C'.
5. Dimension 'D1' and 'E1' do not include mold protrusions. Allowable protrusion is 0.25mm per side.
'D1' and 'E1' are maximum plastic body size dimension including mold mismatch. Dimension 'D1' and
'E1' shall be determined at datum plane 'H'.
6. Detail of Pin 1 indicatifier are option all but must be located within the zone indicated.
7. Dimension 'b' does not include dambar protrusion. Allowable dambar protrusion shall not cause the
lead width to exceed the maximum 'b' dimension by more than 0.08 mm. Dambar can not be located
on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm
8. Exact shape of each corner is optional.
9. These dimension apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.
10.All dimensions are in millimeters.
Table 4.4. QFP64 (Dimensions in mm)
DIM
A
MIN
-
NOM
1.10
-
MAX
1.20
0.15
1.05
0.27
0.23
DIM
L1
MIN
NOM
MAX
-
A1
A2
b
0.05
0.95
0.17
0.17
R1
R2
S
0.08
0.08
0.20
0°
-
-
0.20
-
1.00
0.22
0.20
-
-
b1
3.5°
7°
θ
c
C1
D
0.09
0.09
-
0.20
0.16
0°
-
-
θ1
θ2
θ3
-
11°
11°
12°
12°
13°
13°
12.0 BSC
D1
e
10.0 BSC
0.50 BSC
12.0 BSC
10.0 BSC
0.60
E
E1
L
0.45
0.75
The TQFP64 Package is 10 by 10 mm in size and has a 0.5 mm pin pitch.
The TQFP64 Package uses Nickel-Palladium-Gold preplated leadframe.
All EFM32 packages are RoHS compliant and free of Bromine (Br) and Antimony (Sb).
For additional Quality and Environmental information, please see:
http://www.silabs.com/support/quality/pages/default.aspx
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5 PCB Layout and Soldering
5.1 Recommended PCB Layout
Figure 5.1. TQFP64 PCB Land Pattern
a
p8
p7
p6
p1
b
e
c
p2
p5
p3
p4
d
Table 5.1. QFP64 PCB Land Pattern Dimensions (Dimensions in mm)
Symbol
Dim. (mm)
1.60
Symbol
P1
Pin number
Symbol
Pin number
a
b
c
d
e
1
P6
P7
P8
-
48
49
64
-
0.30
P2
16
17
32
33
0.50
P3
11.50
11.50
P4
P5
-
-
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Figure 5.2. TQFP64 PCB Solder Mask
a
b
c
e
d
Table 5.2. QFP64 PCB Solder Mask Dimensions (Dimensions in mm)
Symbol
Dim. (mm)
a
b
c
d
e
1.72
0.42
0.50
11.50
11.50
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Figure 5.3. TQFP64 PCB Stencil Design
a
b
c
e
d
Table 5.3. QFP64 PCB Stencil Design Dimensions (Dimensions in mm)
Symbol
Dim. (mm)
a
b
c
d
e
1.50
0.20
0.50
11.50
11.50
1. The drawings are not to scale.
2. All dimensions are in millimeters.
3. All drawings are subject to change without notice.
4. The PCB Land Pattern drawing is in compliance with IPC-7351B.
5. Stencil thickness 0.125 mm.
6. For detailed pin-positioning, see Figure 4.3 (p. 61) .
5.2 Soldering Information
The latest IPC/JEDEC J-STD-020 recommendations for Pb-Free reflow soldering should be followed.
The packages have a Moisture Sensitivity Level rating of 3, please see the latest IPC/JEDEC J-STD-033
standard for MSL description and level 3 bake conditions.
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6 Chip Marking, Revision and Errata
6.1 Chip Marking
In the illustration below package fields and position are shown.
Figure 6.1. Example Chip Marking (top view)
6.2 Revision
The revision of a chip can be determined from the "Revision" field in Figure 6.1 (p. 66) .
6.3 Errata
Please see the errata document for EFM32WG232 for description and resolution of device erratas. This
document is available in Simplicity Studio and online at:
http://www.silabs.com/support/pages/document-library.aspx?p=MCUs--32-bit
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7 Revision History
7.1 Revision 1.40
June 13th, 2014
Removed "Preliminary" markings.
Corrected single power supply voltage minimum value from 1.85V to 1.98V.
Added AUXHFRCO to blockdiagram and electrical characteristics.
Updated current consumption data.
Updated transition between energy modes data.
Updated power management data.
Updated GPIO data.
Updated LFRCO, HFRCO and ULFRCO data.
Updated ADC data.
Updated DAC data.
Updated OPAMP data.
Updated ACMP data.
Updated VCMP data.
7.2 Revision 1.31
November 21st, 2013
Updated figures.
Updated errata-link.
Updated chip marking.
Added link to Environmental and Quality information.
Re-added missing DAC-data.
7.3 Revision 1.30
September 30th, 2013
Added I2C characterization data.
Added SPI characterization data.
Corrected the DAC and OPAMP2 pin sharing information in the Alternate Functionality Pinout section.
Corrected the ADC resolution from 12, 10 and 6 bit to 12, 8 and 6 bit.
Updated the EM0 and EM1 current consumption numbers. Updated the the EM1 plots and removed
the EM0 plots.
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Updated Environmental information.
Updated trademark, disclaimer and contact information.
Other minor corrections.
7.4 Revision 1.20
June 28th, 2013
Updated power requirements in the Power Management section.
Removed minimum load capacitance figure and table. Added reference to application note.
Other minor corrections.
7.5 Revision 1.10
May 6th, 2013
Updated current consumption table and figures in Electrical characteristics section.
Other minor corrections.
7.6 Revision 1.00
September 11th, 2012
Updated the HFRCO 1 MHz band typical value to 1.2 MHz.
Updated the HFRCO 7 MHz band typical value to 6.6 MHz.
Other minor corrections.
7.7 Revision 0.95
May 3rd, 2012
Updated EM2/EM3 current consumption at 85°C.
7.8 Revision 0.90
February 27th, 2012
Initial preliminary release.
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A Disclaimer and Trademarks
A.1 Disclaimer
Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation
of all peripherals and modules available for system and software implementers using or intending to use
the Silicon Laboratories products. Characterization data, available modules and peripherals, memory
sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and
do vary in different applications. Application examples described herein are for illustrative purposes only.
Silicon Laboratories reserves the right to make changes without further notice and limitation to product
information, specifications, and descriptions herein, and does not give warranties as to the accuracy
or completeness of the included information. Silicon Laboratories shall have no liability for the conse-
quences of use of the information supplied herein. This document does not imply or express copyright
licenses granted hereunder to design or fabricate any integrated circuits. The products must not be
used within any Life Support System without the specific written consent of Silicon Laboratories. A "Life
Support System" is any product or system intended to support or sustain life and/or health, which, if it
fails, can be reasonably expected to result in significant personal injury or death. Silicon Laboratories
products are generally not intended for military applications. Silicon Laboratories products shall under no
circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological
or chemical weapons, or missiles capable of delivering such weapons.
A.2 Trademark Information
Silicon Laboratories Inc., Silicon Laboratories, Silicon Labs, SiLabs and the Silicon Labs logo, CMEMS®,
EFM, EFM32, EFR, Energy Micro, Energy Micro logo and combinations thereof, "the world’s most ener-
gy friendly microcontrollers", Ember®, EZLink®, EZMac®, EZRadio®, EZRadioPRO®, DSPLL®, ISO-
modem®, Precision32®, ProSLIC®, SiPHY®, USBXpress® and others are trademarks or registered
trademarks of Silicon Laboratories Inc. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or reg-
istered trademarks of ARM Holdings. Keil is a registered trademark of ARM Limited. All other products
or brand names mentioned herein are trademarks of their respective holders.
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B Contact Information
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Please visit the Silicon Labs Technical Support web page:
http://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
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Table of Contents
1. Ordering Information .................................................................................................................................. 2
2. System Summary ...................................................................................................................................... 3
2.1. System Introduction ......................................................................................................................... 3
2.2. Configuration Summary .................................................................................................................... 7
2.3. Memory Map ................................................................................................................................. 8
3. Electrical Characteristics ............................................................................................................................. 9
3.1. Test Conditions .............................................................................................................................. 9
3.2. Absolute Maximum Ratings .............................................................................................................. 9
3.3. General Operating Conditions ........................................................................................................... 9
3.4. Current Consumption ..................................................................................................................... 10
3.5. Transition between Energy Modes .................................................................................................... 16
3.6. Power Management ....................................................................................................................... 17
3.7. Flash .......................................................................................................................................... 17
3.8. General Purpose Input Output ......................................................................................................... 18
3.9. Oscillators .................................................................................................................................... 26
3.10. Analog Digital Converter (ADC) ...................................................................................................... 31
3.11. Digital Analog Converter (DAC) ...................................................................................................... 41
3.12. Operational Amplifier (OPAMP) ...................................................................................................... 42
3.13. Analog Comparator (ACMP) .......................................................................................................... 46
3.14. Voltage Comparator (VCMP) ......................................................................................................... 48
3.15. I2C ........................................................................................................................................... 48
3.16. USART SPI ................................................................................................................................ 50
3.17. Digital Peripherals ....................................................................................................................... 52
4. Pinout and Package ................................................................................................................................. 53
4.1. Pinout ......................................................................................................................................... 53
4.2. Alternate Functionality Pinout .......................................................................................................... 56
4.3. GPIO Pinout Overview ................................................................................................................... 60
4.4. Opamp Pinout Overview ................................................................................................................. 60
4.5. TQFP64 Package .......................................................................................................................... 61
5. PCB Layout and Soldering ........................................................................................................................ 63
5.1. Recommended PCB Layout ............................................................................................................ 63
5.2. Soldering Information ..................................................................................................................... 65
6. Chip Marking, Revision and Errata .............................................................................................................. 66
6.1. Chip Marking ................................................................................................................................ 66
6.2. Revision ...................................................................................................................................... 66
6.3. Errata ......................................................................................................................................... 66
7. Revision History ...................................................................................................................................... 67
7.1. Revision 1.40 ............................................................................................................................... 67
7.2. Revision 1.31 ............................................................................................................................... 67
7.3. Revision 1.30 ............................................................................................................................... 67
7.4. Revision 1.20 ............................................................................................................................... 68
7.5. Revision 1.10 ............................................................................................................................... 68
7.6. Revision 1.00 ............................................................................................................................... 68
7.7. Revision 0.95 ............................................................................................................................... 68
7.8. Revision 0.90 ............................................................................................................................... 68
A. Disclaimer and Trademarks ....................................................................................................................... 69
A.1. Disclaimer ................................................................................................................................... 69
A.2. Trademark Information ................................................................................................................... 69
B. Contact Information ................................................................................................................................. 70
B.1. ................................................................................................................................................. 70
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List of Figures
2.1. Block Diagram ....................................................................................................................................... 3
2.2. EFM32WG232 Memory Map with largest RAM and Flash sizes ....................................................................... 8
3.1. EM1 Current consumption with all peripheral clocks disabled and HFXO running at 48MHz ................................. 12
3.2. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 28MHz ............................... 12
3.3. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 21MHz ............................... 13
3.4. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 14MHz ............................... 13
3.5. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 11MHz ............................... 14
3.6. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 6.6MHz .............................. 14
3.7. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 1.2MHz .............................. 15
3.8. EM2 current consumption. RTC prescaled to 1kHz, 32.768 kHz LFRCO. ......................................................... 15
3.9. EM3 current consumption. ..................................................................................................................... 16
3.10. EM4 current consumption. ................................................................................................................... 16
3.11. Typical Low-Level Output Current, 2V Supply Voltage ................................................................................ 20
3.12. Typical High-Level Output Current, 2V Supply Voltage ................................................................................ 21
3.13. Typical Low-Level Output Current, 3V Supply Voltage ................................................................................ 22
3.14. Typical High-Level Output Current, 3V Supply Voltage ................................................................................ 23
3.15. Typical Low-Level Output Current, 3.8V Supply Voltage .............................................................................. 24
3.16. Typical High-Level Output Current, 3.8V Supply Voltage ............................................................................. 25
3.17. Calibrated LFRCO Frequency vs Temperature and Supply Voltage .............................................................. 27
3.18. Calibrated HFRCO 1 MHz Band Frequency vs Supply Voltage and Temperature ............................................ 28
3.19. Calibrated HFRCO 7 MHz Band Frequency vs Supply Voltage and Temperature ............................................ 29
3.20. Calibrated HFRCO 11 MHz Band Frequency vs Supply Voltage and Temperature ........................................... 29
3.21. Calibrated HFRCO 14 MHz Band Frequency vs Supply Voltage and Temperature ........................................... 29
3.22. Calibrated HFRCO 21 MHz Band Frequency vs Supply Voltage and Temperature ........................................... 30
3.23. Calibrated HFRCO 28 MHz Band Frequency vs Supply Voltage and Temperature ........................................... 30
3.24. Integral Non-Linearity (INL) ................................................................................................................... 36
3.25. Differential Non-Linearity (DNL) .............................................................................................................. 36
3.26. ADC Frequency Spectrum, Vdd = 3V, Temp = 25°C ................................................................................. 37
3.27. ADC Integral Linearity Error vs Code, Vdd = 3V, Temp = 25°C ................................................................... 38
3.28. ADC Differential Linearity Error vs Code, Vdd = 3V, Temp = 25°C ............................................................... 39
3.29. ADC Absolute Offset, Common Mode = Vdd /2 ........................................................................................ 40
3.30. ADC Dynamic Performance vs Temperature for all ADC References, Vdd = 3V .............................................. 40
3.31. ADC Temperature sensor readout ......................................................................................................... 41
3.32. OPAMP Common Mode Rejection Ratio ................................................................................................. 44
3.33. OPAMP Positive Power Supply Rejection Ratio ........................................................................................ 44
3.34. OPAMP Negative Power Supply Rejection Ratio ...................................................................................... 45
3.35. OPAMP Voltage Noise Spectral Density (Unity Gain) Vout=1V ..................................................................... 45
3.36. OPAMP Voltage Noise Spectral Density (Non-Unity Gain) .......................................................................... 45
3.37. ACMP Characteristics, Vdd = 3V, Temp = 25°C, FULLBIAS = 0, HALFBIAS = 1 ............................................. 47
3.38. SPI Master Timing ............................................................................................................................... 50
3.39. SPI Slave Timing ................................................................................................................................ 51
4.1. EFM32WG232 Pinout (top view, not to scale) ............................................................................................. 53
4.2. Opamp Pinout ...................................................................................................................................... 61
4.3. TQFP64 .............................................................................................................................................. 61
5.1. TQFP64 PCB Land Pattern ..................................................................................................................... 63
5.2. TQFP64 PCB Solder Mask ..................................................................................................................... 64
5.3. TQFP64 PCB Stencil Design ................................................................................................................... 65
6.1. Example Chip Marking (top view) ............................................................................................................. 66
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List of Tables
1.1. Ordering Information ................................................................................................................................ 2
2.1. Configuration Summary ............................................................................................................................ 7
3.1. Absolute Maximum Ratings ...................................................................................................................... 9
3.2. General Operating Conditions ................................................................................................................... 9
3.3. Environmental ....................................................................................................................................... 10
3.4. Current Consumption ............................................................................................................................. 10
3.5. Energy Modes Transitions ...................................................................................................................... 16
3.6. Power Management ............................................................................................................................... 17
3.7. Flash .................................................................................................................................................. 17
3.8. GPIO .................................................................................................................................................. 18
3.9. LFXO .................................................................................................................................................. 26
3.10. HFXO ................................................................................................................................................ 26
3.11. LFRCO .............................................................................................................................................. 27
3.12. HFRCO ............................................................................................................................................. 28
3.13. AUXHFRCO ....................................................................................................................................... 31
3.14. ULFRCO ............................................................................................................................................ 31
3.15. ADC .................................................................................................................................................. 31
3.16. DAC .................................................................................................................................................. 41
3.17. OPAMP ............................................................................................................................................. 42
3.18. ACMP ............................................................................................................................................... 46
3.19. VCMP ............................................................................................................................................... 48
3.20. I2C Standard-mode (Sm) ...................................................................................................................... 48
3.21. I2C Fast-mode (Fm) ............................................................................................................................ 49
3.22. I2C Fast-mode Plus (Fm+) .................................................................................................................... 49
3.23. SPI Master Timing ............................................................................................................................... 50
3.24. SPI Master Timing with SSSEARLY and SMSDELAY ................................................................................. 50
3.25. SPI Slave Timing ................................................................................................................................ 51
3.26. SPI Slave Timing with SSSEARLY and SMSDELAY .................................................................................. 51
3.27. Digital Peripherals ............................................................................................................................... 52
4.1. Device Pinout ....................................................................................................................................... 53
4.2. Alternate functionality overview ................................................................................................................ 56
4.3. GPIO Pinout ........................................................................................................................................ 60
4.4. QFP64 (Dimensions in mm) .................................................................................................................... 62
5.1. QFP64 PCB Land Pattern Dimensions (Dimensions in mm) .......................................................................... 63
5.2. QFP64 PCB Solder Mask Dimensions (Dimensions in mm) ........................................................................... 64
5.3. QFP64 PCB Stencil Design Dimensions (Dimensions in mm) ........................................................................ 65
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List of Equations
3.1. Total ACMP Active Current ..................................................................................................................... 46
3.2. VCMP Trigger Level as a Function of Level Setting ..................................................................................... 48
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