EFR32BG1B232F256GJ43-C0 [SILICON]
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EFR32BG1 Blue Gecko Bluetooth® Smart
SoC CSP Family Data Sheet
The Blue Gecko Bluetooth Smart family of SoCs is part of the
KEY FEATURES
Wireless Gecko portfolio. Blue Gecko SoCs are ideal for enabling
energy-friendly Bluetooth Smart networking for IoT devices.
• 32-bit ARM® Cortex®-M4 core with 40
MHz maximum operating frequency
The single-die solution provides industry-leading energy efficiency, ultra-fast wakeup
times, a scalable power amplifier, an integrated balun and no-compromise MCU fea-
tures.
• Scalable Memory and Radio configuration
options available in footprint-compatible
CSP packaging
• 12-channel Peripheral Reflex System
enabling autonomous interaction of MCU
peripherals
Blue Gecko applications include:
• IoT Sensors and End Devices
• Health and Wellness
• Autonomous Hardware Crypto Accelerator
and Random Number Generator
• Home and Building Automation
• Accessories
• Integrated 2.4 GHz balun and PA with up
to 19.5 dBm transmit power
• Integrated DC-DC with RF noise mitigation
• Human Interface Devices
• Metering
• Also Available: Certified modules with
compatible tools and software
• Commercial and Retail Lighting and Sensing
Core / Memory
Clock Management
Energy Management
Other
High Frequency
Crystal
Oscillator
High Frequency
RC Oscillator
Voltage
CRYPTO
Voltage Monitor
Regulator
ARM CortexTM M4 processor
Memory
with DSP extensions and FPU
Protection Unit
Auxiliary High
Frequency RC
Oscillator
Low Frequency
RC Oscillator
DC-DC
Power-On Reset
Converter
CRC
Low Frequency
Crystal
Oscillator
Ultra Low
Frequency RC
Oscillator
Flash Program
RAM Memory
Memory
Brown-Out
Detector
Debug Interface
DMA Controller
32-bit bus
Peripheral Reflex System
Radio Transceiver
Serial
I/O Ports
Timers and Triggers
Analog I/F
Interfaces
External
Interrupts
RFSENSE
BALUN
DEMOD
USART
Timer/Counter
Protocol Timer
ADC
Low Energy
UARTTM
General
Purpose I/O
Low Energy
Timer
Analog
Comparator
IFADC
AGC
PGA
I
Watchdog Timer
LNA
RF Frontend
Real Time
Counter and
Calendar
I2C
Pin Reset
Pulse Counter
IDAC
PA
Frequency
Synthesizer
Q
MOD
Pin Wakeup
Cryotimer
Lowest power mode with peripheral operational:
EM0—Active EM1—Sleep
EM2—Deep Sleep
EM3—Stop
EM4—Hibernate
EM4—Shutoff
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This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Silicon
Laboratories Confidential. Information contained herein is covered under non-disclosure agreement (NDA).
Preliminary Rev. 1.1
EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Feature List
1. Feature List
The EFR32BG1 highlighted features are listed below.
• Low Power Wireless System-on-Chip.
• Wide selection of MCU peripherals
High Performance 32-bit 40 MHz ARM Cortex®-M4 with
DSP instruction and floating-point unit for efficient signal
processing
•
• 12-bit 1 Msps SAR Analog to Digital Converter (ADC)
• 2× Analog Comparator (ACMP)
• Digital to Analog Current Converter (IDAC)
• Up to 256 kB flash program memory
• Up to 32 kB RAM data memory
• 2.4 GHz radio operation
• Up to 19 pins connected to analog channels (APORT)
shared between Analog Comparators, ADC, and IDAC
• Up to 19 General Purpose I/O pins with output state reten-
tion and asynchronous interrupts
• TX power up to 19.5 dBm
• 8 Channel DMA Controller
• Low Energy Consumption
• 12 Channel Peripheral Reflex System (PRS)
• 2×16-bit Timer/Counter
• 8.7 mA RX current at 2.4 GHz
• 8.2 mA TX current @ 0 dBm output power at 2.4 GHz
• 63 μA/MHz in Active Mode (EM0)
• 3 + 4 Compare/Capture/PWM channels
• 32-bit Real Time Counter and Calendar
• 16-bit Low Energy Timer for waveform generation
• 2.5 μA EM2 DeepSleep current (full RAM retention and
RTCC running from LFXO)
• 0.58 μA EM4H Hibernate Mode (128 byte RAM retention)
• 32-bit Ultra Low Energy Timer/Counter for periodic wake-up
from any Energy Mode
• Wake on Radio with signal strength detection, preamble
pattern detection, frame detection and timeout
• 16-bit Pulse Counter with asynchronous operation
• Watchdog Timer with dedicated RC oscillator @ 50nA
• 2×Universal Synchronous/Asynchronous Receiver/Trans-
mitter (UART/SPI/SmartCard (ISO 7816)/IrDA/I2S)
• High Receiver Performance
• -91 dBm sensitivity @ 1 Mbit/s GFSK (2.4GHz)
• Supported Modulation Format
• GFSK
Low Energy UART (LEUART™)
I2C interface with SMBus support and address recognition
in EM3 Stop
•
•
• 2-FSK / 4-FSK with fully configurable shaping (EFR32BG1P
OPNs)
• Shaped OQPSK / (G)MSK (EFR32BG1P OPNs)
• Configurable DSSS and FEC (EFR32BG1P OPNs)
• Supported Protocol:
• Wide Operating Range
• 1.85 V to 3.8 V single power supply
• Integrated DC-DC, down to 1.8 V output with up to 200 mA
load current for system
Bluetooth® Smart
•
• -40 °C to 85 °C
• Proprietary Protocols (EFR32BG1P OPNs)
• Support for Internet Security
• General Purpose CRC
• 43-pin CSP 3.3x3.14 mm Package
• Random Number Generation
• Hardware Cryptographic Acceleration for AES 128/256,
SHA-1, SHA-2 (SHA-224 and SHA-256) and ECC
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Preliminary Rev. 1.1 | 1
EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Ordering Information
2. Ordering Information
Ordering Code
Protocol Stack
Frequency Band
@ Max TX Power
2.4 GHz @ 19.5 dBm
Flash
(kB)
RAM (kB)
EFR32BG1P332F256GJ43-C0
• Bluetooth Smart
• Proprietary
256
32
EFR32BG1B232F256GJ43-C0
EFR32BG1V132F256GJ43-C0
Bluetooth Smart
Bluetooth Smart
2.4 GHz @ 10.5 dBm
2.4 GHz @ 0 dBm
256
256
32
16
EFR32 X G 1 P 132 F 256 G M 32 – C0 R
Tape and Reel (Optional)
Revision
Pin Count
Package – M (QFN), J (CSP)
Temperature Grade – G (-40 to +85 °C), -I (-40 to +125 °C)
Flash Memory Size in kB
Memory Type (Flash)
Feature Set Code – r2r1r0
r2: Reserved
r1: RF Type – 3 (TRX), 2 (RX), 1 (TX)
r0: Frequency Band – 1 (Sub-GHz), 2 (2.4 GHz), 3 (Dual-Band)
Performance Grade – P (Performance), B (Basic), V (Value)
Series
Gecko
Family – M (Mighty), B (Blue), F (Flex)
Wireless Gecko 32-bit
Figure 2.1. OPN Decoder
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Preliminary Rev. 1.1 | 2
EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
System Overview
3. System Overview
3.1 Introduction
The EFR32 product family combines an energy-friendly MCU with a highly integrated radio transceiver. The devices are well suited for
any battery operated application as well as other systems requiring high performance and low energy consumption. This section gives a
short introduction to the full radio and MCU system. The detailed functional description can be found in the EFR32 Reference Manual.
A block diagram of the EFR32BG1 family is shown in Figure 3.1 Detailed EFR32BG1 Block Diagram on page 3. The diagram shows
a superset of features available on the family, which vary by OPN. For more information about specific device features, consult Order-
ing Information.
Port I/O Configuration
Radio Transciever
DEMOD
Digital Peripherals
RFSENSE
BALUN
RF Frontend
PGA
IFADC
AGC
LETIMER
I
IOVDD
LNA
TIMER
2G4RF_IOP
2G4RF_ION
PA
Frequency
Synthesizer
Q
CRYOTIMER
PCNT
MOD
Port A
Drivers
PAn
RTC / RTCC
USART
Port
Mapper
Energy Management
ARM Cortex-M4 Core
Port B
PAVDD
RFVDD
PBn
PCn
PDn
PFn
Drivers
Up to 256 KB ISP Flash
Program Memory
LEUART
I2C
IOVDD
AVDD
Up to 32 KB RAM
Memory Protection Unit
Floating Point Unit
DMA Controller
Voltage
Monitor
CRYPTO
CRC
Port C
Drivers
A
H
B
A
P
B
DVDD
bypass
Port D
Drivers
VREGVDD
VREGSW
Analog Peripherals
DC-DC
Converter
Voltage
Regulator
Serial Wire Debug /
Programming
Internal
Reference
IDAC
DECOUPLE
Watchdog
Timer
Port F
Drivers
VDD
VREF
VSS
VREGVSS
RFVSS
Brown Out /
Power-On
Reset
Clock Management
VDD
12-bit ADC
PAVSS
ULFRCO
AUXHFRCO
LFRCO
Reset
Management
Unit
RESETn
Temp
Sensor
HFRCO
LFXO
LFXTAL_P / N
+
-
HFXTAL_P
HFXTAL_N
HFXO
Analog Comparator
Figure 3.1. Detailed EFR32BG1 Block Diagram
3.2 Radio
The Blue Gecko family features a radio transceiver supporting Bluetooth Smart® and proprietary short range wireless protocols.
3.2.1 Antenna Interface
The 2.4 GHz antenna interface consists of two pins (2G4RF_IOP and 2G4RF_ION) that interface directly to the on-chip BALUN. The
2G4RF_ION pin should be grounded externally.
The external components and power supply connections for the antenna interface typical applications are shown in the RF Matching
Networks section.
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Preliminary Rev. 1.1 | 3
EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
System Overview
3.2.2 Fractional-N Frequency Synthesizer
The EFR32BG1 contains a high performance, low phase noise, fully integrated fractional-N frequency synthesizer. The synthesizer is
used in receive mode to generate the LO frequency used by the down-conversion mixer. It is also used in transmit mode to directly
generate the modulated RF carrier.
The fractional-N architecture provides excellent phase noise performance combined with frequency resolution better than 100 Hz, with
low energy consumption. The synthesizer has fast frequency settling which allows very short receiver and transmitter wake up times to
optimize system energy consumption.
3.2.3 Receiver Architecture
The EFR32BG1 uses a low-IF receiver architecture, consisting of a Low-Noise Amplifier (LNA) followed by an I/Q down-conversion mix-
er, employing a crystal reference. The I/Q signals are further filtered and amplified before being sampled by the IF analog-to-digital
converter (IFADC).
The IF frequency is configurable from 150 kHz to 1371 kHz. The IF can further be configured for high-side or low-side injection, provid-
ing flexibility with respect to known interferers at the image frequency.
The Automatic Gain Control (AGC) module adjusts the receiver gain to optimize performance and avoid saturation for excellent selec-
tivity and blocking performance. Devices are production-calibrated to improve image rejection performance.
Demodulation is performed in the digital domain. The demodulator performs configurable decimation and channel filtering to allow re-
ceive bandwidths ranging from 0.1 to 2530 kHz. High carrier frequency and baud rate offsets are tolerated by active estimation and
compensation. Advanced features supporting high quality communication under adverse conditions include forward error correction by
block and convolutional coding as well as Direct Sequence Spread Spectrum (DSSS).
A Received Signal Strength Indicator (RSSI) is available for signal quality metrics, for level-based proximity detection, and for RF chan-
nel access by Collision Avoidance (CA) or Listen Before Talk (LBT) algorithms. An RSSI capture value is associated with each received
frame and the dynamic RSSI measurement can be monitored throughout reception.
3.2.4 Transmitter Architecture
The EFR32BG1 uses a direct-conversion transmitter architecture. For constant envelope modulation formats, the modulator controls
phase and frequency modulation in the frequency synthesizer. Transmit symbols or chips are optionally shaped by a digital shaping
filter. The shaping filter is fully configurable, including the BT product, and can be used to implement Gaussian or Raised Cosine shap-
ing.
Carrier Sense Multiple Access - Collision Avoidance (CSMA-CA) or Listen Before Talk (LBT) algorithms can be automatically timed by
the EFR32BG1. These algorithms are typically defined by regulatory standards to improve inter-operability in a given bandwidth be-
tween devices that otherwise lack synchronized RF channel access.
3.2.5 Wake on Radio
The Wake on Radio feature allows flexible, autonomous RF sensing, qualification, and demodulation without required MCU activity, us-
ing a subsystem of the EFR32BG1 including the Radio Controller (RAC), Peripheral Reflex System (PRS), and Low Energy peripherals.
3.2.6 RFSENSE
The RFSENSE module generates a system wakeup interrupt upon detection of wideband RF energy at the antenna interface, providing
true RF wakeup capabilities from low energy modes including EM2, EM3 and EM4.
RFSENSE triggers on a relatively strong RF signal and is available in the lowest energy modes, allowing exceptionally low energy con-
sumption. RFSENSE does not demodulate or otherwise qualify the received signal, but software may respond to the wakeup event by
enabling normal RF reception.
Various strategies for optimizing power consumption and system response time in presence of false alarms may be employed using
available timer peripherals.
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Preliminary Rev. 1.1 | 4
EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
System Overview
3.2.7 Flexible Frame Handling
EFR32BG1 has an extensive and flexible frame handling support for easy implementation of even complex communication protocols.
The Frame Controller (FRC) supports all low level and timing critical tasks together with the Radio Controller and Modulator/Demodula-
tor:
• Highly adjustable preamble length
• Up to 2 simultaneous synchronization words, each up to 32 bits and providing separate interrupts
• Frame disassembly and address matching (filtering) to accept or reject frames
• Automatic ACK frame assembly and transmission
• Fully flexible CRC generation and verification:
• Multiple CRC values can be embedded in a single frame
• 8, 16, 24 or 32-bit CRC value
• Configurable CRC bit and byte ordering
• Selectable bit-ordering (least significant or most significant bit first)
• Optional data whitening
• Optional Forward Error Correction (FEC), including convolutional encoding / decoding and block encoding / decoding
• Half rate convolutional encoder and decoder with constraint lengths from 2 to 7 and optional puncturing
• Optional symbol interleaving, typically used in combination with FEC
• Symbol coding, such as Manchester or DSSS, or biphase space encoding using FEC hardware
• UART encoding over air, with start and stop bit insertion / removal
• Test mode support, such as modulated or unmodulated carrier output
• Received frame timestamping
3.2.8 Packet and State Trace
The EFR32BG1 Frame Controller has a packet and state trace unit that provides valuable information during the development phase. It
features:
• Non-intrusive trace of transmit data, receive data and state information
• Data observability on a single-pin UART data output, or on a two-pin SPI data output
• Configurable data output bitrate / baudrate
• Multiplexed transmitted data, received data and state / meta information in a single serial data stream
3.2.9 Data Buffering
The EFR32BG1 features an advanced Radio Buffer Controller (BUFC) capable of handling up to 4 buffers of adjustable size from 64
bytes to 4096 bytes. Each buffer can be used for RX, TX or both. The buffer data is located in RAM, enabling zero-copy operations.
3.2.10 Radio Controller (RAC)
The Radio Controller controls the top level state of the radio subsystem in the EFR32BG1. It performs the following tasks:
• Precisely-timed control of enabling and disabling of the receiver and transmitter circuitry
• Run-time calibration of receiver, transmitter and frequency synthesizer
• Detailed frame transmission timing, including optional LBT or CSMA-CA
3.2.11 Random Number Generator
The Frame Controller (FRC) implements a random number generator that uses entropy gathered from noise in the RF receive chain.
The data is suitable for use in cryptographic applications.
Output from the random number generator can be used either directly or as a seed or entropy source for software-based random num-
ber generator algorithms such as Fortuna.
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Preliminary Rev. 1.1 | 5
EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
System Overview
3.3 Power
The EFR32BG1 has an Energy Management Unit (EMU) and efficient integrated regulators to generate internal supply voltages. Only a
single external supply voltage is required, from which all internal voltages are created. An optional integrated DC-DC buck regulator can
be utilized to further reduce the current consumption. The DC-DC regulator requires one external inductor and one external capacitor.
AVDD and VREGVDD need to be 1.85 V or higher for the MCU to operate across all conditions; however the rest of the system will
operate down to 1.62 V, including the digital supply and I/O. This means that the device is fully compatible with 1.8 V components.
Running from a sufficiently high supply, the device can use the DC-DC to regulate voltage not only for itself, but also for other PCB
components, supplying up to a total of 200 mA.
3.3.1 Energy Management Unit (EMU)
The Energy Management Unit manages transitions of energy modes in the device. Each energy mode defines which peripherals and
features are available and the amount of current the device consumes. The EMU can also be used to turn off the power to unused RAM
blocks, and it contains control registers for the dc-dc regulator and the Voltage Monitor (VMON). The VMON is used to monitor multiple
supply voltages. It has multiple channels which can be programmed individually by the user to determine if a sensed supply has fallen
below a chosen threshold.
3.3.2 DC-DC Converter
The DC-DC buck converter covers a wide range of load currents and provides up to 90% efficiency in energy modes EM0, EM1, EM2
and EM3, and can supply up to 200 mA to the device and surrounding PCB components. Patented RF noise mitigation allows operation
of the DC-DC converter without degrading sensitivity of radio components. Protection features include programmable current limiting,
short-circuit protection, and dead-time protection. The DC-DC converter may also enter bypass mode when the input voltage is too low
for efficient operation. In bypass mode, the DC-DC input supply is internally connected directly to its output through a low resistance
switch. Bypass mode also supports in-rush current limiting to prevent input supply voltage droops due to excessive output current tran-
sients.
3.4 General Purpose Input/Output (GPIO)
EFR32BG1 has up to 19 General Purpose Input/Output pins. Each GPIO pin can be individually configured as either an output or input.
More advanced configurations including open-drain, open-source, and glitch-filtering can be configured for each individual GPIO pin.
The GPIO pins can be overridden by peripheral connections, like SPI communication. Each peripheral connection can be routed to sev-
eral GPIO pins on the device. The input value of a GPIO pin can be routed through the Peripheral Reflex System to other peripherals.
The GPIO subsystem supports asynchronous external pin interrupts.
3.5 Clocking
3.5.1 Clock Management Unit (CMU)
The Clock Management Unit controls oscillators and clocks in the EFR32BG1. Individual enabling and disabling of clocks to all periph-
eral modules is performed by the CMU. The CMU also controls enabling and configuration of the oscillators. A high degree of flexibility
allows software to optimize energy consumption in any specific application by minimizing power dissipation in unused peripherals and
oscillators.
3.5.2 Internal and External Oscillators
The EFR32BG1 supports two crystal oscillators and fully integrates four RC oscillators, listed below.
• A high frequency crystal oscillator (HFXO) with integrated load capacitors, tunable in small steps, provides a precise timing refer-
ence for the MCU. Crystal frequencies in the range from 38 to 40 MHz are supported. An external clock source such as a TCXO can
also be applied to the HFXO input for improved accuracy over temperature.
• A 32.768 kHz crystal oscillator (LFXO) provides an accurate timing reference for low energy modes.
• An integrated high frequency RC oscillator (HFRCO) is available for the MCU system, when crystal accuracy is not required. The
HFRCO employs fast startup at minimal energy consumption combined with a wide frequency range.
• An integrated auxilliary high frequency RC oscillator (AUXHFRCO) is available for timing the general-purpose ADC and the Serial
Wire debug port with a wide frequency range.
• An integrated low frequency 32.768 kHz RC oscillator (LFRCO) can be used as a timing reference in low energy modes, when crys-
tal accuracy is not required.
• An integrated ultra-low frequency 1 kHz RC oscillator (ULFRCO) is available to provide a timing reference at the lowest energy con-
sumption in low energy modes.
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EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
System Overview
3.6 Counters/Timers and PWM
3.6.1 Timer/Counter (TIMER)
TIMER peripherals keep track of timing, count events, generate PWM outputs and trigger timed actions in other peripherals through the
PRS system. The core of each TIMER is a 16-bit counter with up to 4 compare/capture channels. Each channel is configurable in one
of three modes. In capture mode, the counter state is stored in a buffer at a selected input event. In compare mode, the channel output
reflects the comparison of the counter to a programmed threshold value. In PWM mode, the TIMER supports generation of pulse-width
modulation (PWM) outputs of arbitrary waveforms defined by the sequence of values written to the compare registers, with optional
dead-time insertion available in timer unit TIMER_0 only.
3.6.2 Real Time Counter and Calendar (RTCC)
The Real Time Counter and Calendar (RTCC) is a 32-bit counter providing timekeeping in all energy modes. The RTCC includes a
Binary Coded Decimal (BCD) calendar mode for easy time and date keeping. The RTCC can be clocked by any of the on-board oscilla-
tors with the exception of the AUXHFRCO, and it is capable of providing system wake-up at user defined instances. When receiving
frames, the RTCC value can be used for timestamping. The RTCC includes 128 bytes of general purpose data retention, allowing easy
and convenient data storage in all energy modes.
3.6.3 Low Energy Timer (LETIMER)
The unique LETIMER is a 16-bit timer that is available in energy mode EM2 Deep Sleep in addition to EM1 Sleep and EM0 Active. This
allows it to be used for timing and output generation when most of the device is powered down, allowing simple tasks to be performed
while the power consumption of the system is kept at an absolute minimum. The LETIMER can be used to output a variety of wave-
forms with minimal software intervention. The LETIMER is connected to the Real Time Counter and Calendar (RTCC), and can be con-
figured to start counting on compare matches from the RTCC.
3.6.4 Ultra Low Power Wake-up Timer (CRYOTIMER)
The CRYOTIMER is a 32-bit counter that is capable of running in all energy modes. It can be clocked by either the 32.768 kHz crystal
oscillator (LFXO), the 32.768 kHz RC oscillator (LFRCO), or the 1 kHz RC oscillator (ULFRCO). It can provide periodic Wakeup events
and PRS signals which can be used to wake up peripherals from any energy mode. The CRYOTIMER provides a wide range of inter-
rupt periods, facilitating flexible ultra-low energy operation.
3.6.5 Pulse Counter (PCNT)
The Pulse Counter (PCNT) peripheral can be used for counting pulses on a single input or to decode quadrature encoded inputs. The
clock for PCNT is selectable from either an external source on pin PCTNn_S0IN or from an internal timing reference, selectable from
among any of the internal oscillators, except the AUXHFRCO. The module may operate in energy mode EM0 Active, EM1 Sleep, EM2
Deep Sleep, and EM3 Stop.
3.6.6 Watchdog Timer (WDOG)
The watchdog timer can act both as an independent watchdog or as a watchdog synchronous with the CPU clock. It has windowed
monitoring capabilities, and can generate a reset or different interrupts depending on the failure mode of the system. The watchdog can
also monitor autonomous systems driven by PRS.
3.7 Communications and Other Digital Peripherals
3.7.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
The Universal Synchronous/Asynchronous Receiver/Transmitter is a flexible serial I/O module. It supports full duplex asynchronous
UART communication with hardware flow control as well as RS-485, SPI, MicroWire and 3-wire. It can also interface with devices sup-
porting:
• ISO7816 SmartCards
• IrDA
I2S
•
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Preliminary Rev. 1.1 | 7
EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
System Overview
3.7.2 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART)
The unique LEUARTTM provides two-way UART communication on a strict power budget. Only a 32.768 kHz clock is needed to allow
UART communication up to 9600 baud. The LEUART includes all necessary hardware to make asynchronous serial communication
possible with a minimum of software intervention and energy consumption.
3.7.3 Inter-Integrated Circuit Interface (I2C)
The I2C module provides an interface between the MCU and a serial I2C bus. It is capable of acting as both a master and a slave and
supports multi-master buses. Standard-mode, fast-mode and fast-mode plus speeds are supported, allowing transmission rates from 10
kbit/s up to 1 Mbit/s. Slave arbitration and timeouts are also available, allowing implementation of an SMBus-compliant system. The
interface provided to software by the I2C module allows precise timing control of the transmission process and highly automated trans-
fers. Automatic recognition of slave addresses is provided in active and low energy modes.
3.7.4 Peripheral Reflex System (PRS)
The Peripheral Reflex System provides a communication network between different peripheral modules without software involvement.
Peripheral modules producing Reflex signals are called producers. The PRS routes Reflex signals from producers to consumer periph-
erals which in turn perform actions in response. Edge triggers and other functionality can be applied by the PRS. The PRS allows pe-
ripheral to act autonomously without waking the MCU core, saving power.
3.8 Security Features
3.8.1 GPCRC (General Purpose Cyclic Redundancy Check)
The GPCRC module implements a Cyclic Redundancy Check (CRC) function. It supports both 32-bit and 16-bit polynomials. The sup-
ported 32-bit polynomial is 0x04C11DB7 (IEEE 802.3), while the 16-bit polynomial can be programmed to any value, depending on the
needs of the application.
3.8.2 Crypto Accelerator (CRYPTO)
The Crypto Accelerator is a fast and energy-efficient autonomous hardware encryption and decryption accelerator. EFR32 devices sup-
port AES encryption and decryption with 128- or 256-bit keys, ECC over both GF(P) and GF(2m), SHA-1 and SHA-2 (SHA-224 and
SHA-256).
Supported block cipher modes of operation for AES include: ECB, CTR, CBC, PCBC, CFB, OFB, GCM, CBC-MAC, GMAC and CCM.
Supported ECC NIST recommended curves include P-192, P-224, P-256, K-163, K-233, B-163 and B-233.
The CRYPTO is tightly linked to the Radio Buffer Controller (BUFC) enabling fast and efficient autonomous cipher operations on data
buffer content. It allows fast processing of GCM (AES), ECC and SHA with little CPU intervention. CRYPTO also provides trigger sig-
nals for DMA read and write operations.
3.9 Analog
3.9.1 Analog Port (APORT)
The Analog Port (APORT) is an analog interconnect matrix allowing access to many analog modules on a flexible selection of pins.
Each APORT bus consists of analog switches connected to a common wire. Since many clients can operate differentially, buses are
grouped by X/Y pairs.
3.9.2 Analog Comparator (ACMP)
The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is high-
er. Inputs are selected from among internal references and external pins. The tradeoff between response time and current consumption
is configurable by software. Two 6-bit reference dividers allow for a wide range of internally-programmable reference sources. The
ACMP can also be used to monitor the supply voltage. An interrupt can be generated when the supply falls below or rises above the
programmable threshold.
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EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
System Overview
3.9.3 Analog to Digital Converter (ADC)
The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits at up to 1 Msps. The output
sample resolution is configurable and additional resolution is possible using integrated hardware for averaging over multiple samples.
The ADC includes integrated voltage references and an integrated temperature sensor. Inputs are selectable from a wide range of
sources, including pins configurable as either single-ended or differential.
3.9.4 Digital to Analog Current Converter (IDAC)
The Digital to Analog Current Converter can source or sink a configurable constant current. This current can be driven on an output pin
or routed to the selected ADC input pin for capacitive sensing. The full-scale current is programmable between 0.05 µA and 64 µA with
several ranges consisting of various step sizes.
3.10 Reset Management Unit (RMU)
The RMU is responsible for handling reset of the EFR32BG1. A wide range of reset sources are available, including several power
supply monitors, pin reset, software controlled reset, core lockup reset, and watchdog reset.
3.11 Core and Memory
3.11.1 Processor Core
The ARM Cortex-M processor includes a 32-bit RISC processor integrating the following features and tasks in the system:
• ARM Cortex-M4 RISC processor achieving 1.25 Dhrystone MIPS/MHz
• Memory Protection Unit (MPU) supporting up to 8 memory segments
• Up to 256 kB flash program memory
• Up to 32 kB RAM data memory
• Configuration and event handling of all modules
• 2-pin Serial-Wire debug interface
3.11.2 Memory System Controller (MSC)
The Memory System Controller (MSC) is the program memory unit of the microcontroller. The flash memory is readable and writable
from both the Cortex-M and DMA. The flash memory is divided into two blocks; the main block and the information block. Program code
is normally written to the main block, whereas the information block is available for special user data and flash lock bits. There is also a
read-only page in the information block containing system and device calibration data. Read and write operations are supported in en-
ergy modes EM0 Active and EM1 Sleep.
3.11.3 Linked Direct Memory Access Controller (LDMA)
The Linked Direct Memory Access (LDMA) controller features 8 channels capable of performing memory operations independently of
software. This reduces both energy consumption and software workload. The LDMA allows operations to be linked together and stag-
ed, enabling sophisticated operations to be implemented.
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EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
System Overview
3.12 Memory Map
The EFR32BG1 memory map is shown in the figures below. RAM and flash sizes are for the largest memory configuration.
Figure 3.2. EFR32BG1 Memory Map — Core Peripherals and Code Space
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EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
System Overview
Figure 3.3. EFR32BG1 Memory Map — Peripherals
3.13 Configuration Summary
The features of the EFR32BG1 are a subset of the feature set described in the device reference manual. The table below describes
device specific implementation of the features. Remaining modules support full configuration.
Table 3.1. Configuration Summary
Module
USART0
USART1
Configuration
Pin Connections
IrDA SmartCard
US0_TX, US0_RX, US0_CLK, US0_CS
US1_TX, US1_RX, US1_CLK, US1_CS
IrDA I2S SmartCard
with DTI.
TIMER0
TIMER1
TIM0_CC[2:0], TIM0_CDTI[2:0]
TIM1_CC[3:0]
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EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Electrical Specifications
4. Electrical Specifications
4.1 Electrical Characteristics
All electrical parameters in all tables are specified under the following conditions, unless stated otherwise:
• Typical values are based on TAMB=25 °C and VDD= 3.3 V, by production test and/or technology characterization.
• Radio performance numbers are measured in conducted mode, based on Silicon Laboratories reference designs using output pow-
er-specific external RF impedance-matching networks for interfacing to a 50 Ω antenna.
• Minimum and maximum values represent the worst conditions across supply voltage, process variation, and operating temperature,
unless stated otherwise.
Refer to Table 4.2 General Operating Conditions on page 14 for more details about operational supply and temperature limits.
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EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Electrical Specifications
4.1.1 Absolute Maximum Ratings
Stresses above those listed below may cause permanent damage to the device. This is a stress rating only and functional operation of
the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure
to maximum rating conditions for extended periods may affect device reliability. For more information on the available quality and relia-
bility data, see the Quality and Reliability Monitor Report at http://www.silabs.com/support/quality/pages/default.aspx.
Table 4.1. Absolute Maximum Ratings
Parameter
Symbol
Test Condition
Min
-50
0
Typ
—
Max
150
3.8
1
Unit
°C
Storage temperature range
TSTG
External main supply voltage VDDMAX
—
V
External main supply voltage VDDRAMPMAX
ramp rate
—
—
V / μs
Voltage on any 5V tolerant
GPIO pin1
VDIGPIN
-0.3
-0.3
—
—
Min of 5.25
and IOVDD
+2
V
V
Voltage on non-5V tolerant
GPIO pins
IOVDD+0.3
Voltage on HFXO pins
VHFXOPIN
-0.3
—
—
—
1.4
10
V
Input RF level on pins
2G4RF_IOP and
2G4RF_ION
PRFMAX2G4
dBm
Voltage differential between VMAXDIFF2G4
RF pins (2G4RF_IOP -
2G4RF_ION)
-50
—
—
50
mV
V
Absolute Voltage on RF pins VMAX2G4
2G4RF_IOP and
-0.3
3.3
2G4RF_ION
Total current into VDD power IVDDMAX
lines (source)
—
—
—
—
200
200
mA
mA
Total current into VSS
ground lines (sink)
IVSSMAX
Current per I/O pin (sink)
IIOMAX
—
—
—
—
—
—
—
—
50
50
mA
mA
mA
mA
Current per I/O pin (source)
Current for all I/O pins (sink) IIOALLMAX
200
200
Current for all I/O pins
(source)
Voltage difference between
AVDD and VREGVDD
ΔVDD
—
—
—
0.3
V
Junction Temperature
TJ
-40
105
°C
Note:
1. When a GPIO pin is routed to the analog module through the APORT, the maximum voltage = IOVDD.
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EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Electrical Specifications
4.1.2 Operating Conditions
When assigning supply sources, the following requirements must be observed:
• VREGVDD must be the highest voltage in the system
• VREGVDD = AVDD
• DVDD ≤ AVDD
• IOVDD ≤ AVDD
• RFVDD ≤ AVDD
• PAVDD ≤ AVDD
4.1.2.1 General Operating Conditions
Table 4.2. General Operating Conditions
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Operating temperature range TOP
-G temperature grade, Ambient
Temperature
-40
25
85
°C
AVDD Supply voltage1
VAVDD
1.85
3.3
3.8
V
VREGVDD Operating supply VVREGVDD
voltage1 2
DCDC in regulation
2.4
3.3
3.3
3.3
3.8
3.8
3.8
V
V
V
DCDC in bypass, 50mA load
1.85
1.85
DCDC not in use. DVDD external-
ly shorted to VREGVDD
VREGVDD Current
IVREGVDD
VRFVDD
DCDC in bypass
—
—
—
200
mA
V
RFVDD Operating supply
voltage
1.62
VVREGVDD
DVDD Operating supply volt- VDVDD
age
1.62
1.62
1.62
—
—
—
—
—
VVREGVDD
VVREGVDD
VVREGVDD
0.1
V
V
V
V
PAVDD Operating supply
voltage
VPAVDD
VIOVDD
dVDD
IOVDD Operating supply
voltage
Difference between AVDD
and VREGVDD, ABS(AVDD-
VREGVDD)
0 wait-states (MODE = WS0) 3
1 wait-states (MODE = WS1) 3
HFCLK frequency
fCORE
—
—
—
26
40
MHz
MHz
38.4
Note:
1. VREGVDD must be tied to AVDD. Both VREGVDD and AVDD minimum voltages must be satisfied for the part to operate.
2. The minimum voltage required in bypass mode is calculated using RBYP from the DCDC specification table. Requirements for
other loads can be calculated as VDVDD_min+ILOAD * RBYP_max
3. In MSC_READCTRL register
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EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Electrical Specifications
4.1.3 DC-DC Converter
Test conditions: LDCDC=4.7 µH (Murata LQH3NPN4R7MM0L), CDCDC=1.0 µF (Murata GRM188R71A105KA61D), VDCDC_I=3.3 V,
VDCDC_O=1.8 V, IDCDC_LOAD=50 mA, Heavy Drive configuration, FDCDC_LN=7 MHz, unless otherwise indicated.
Table 4.3. DC-DC Converter
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Input voltage range
VDCDC_I
Bypass mode, IDCDC_LOAD = 50
mA
1.85
—
VVREGVDD_
V
MAX
Low noise (LN) mode, 1.8 V out-
put, IDCDC_LOAD = 100 mA, or
Low power (LP) mode, 1.8 V out-
put, IDCDC_LOAD = 10 mA
2.4
—
VVREGVDD_
V
MAX
Low noise (LN) mode, 1.8 V out-
put, IDCDC_LOAD = 200 mA
2.6
1.8
—
—
VVREGVDD_
V
V
MAX
Output voltage programma- VDCDC_O
ble range1
VVREGVDD
Regulation DC Accuracy
ACCDC
Low noise (LN) mode, 1.8 V target
output
1.7
—
—
1.9
2.2
V
V
Regulation Window2
WINREG
Low power (LP) mode,
LPCMPBIAS3 = 0, 1.8 V target
output, IDCDC_LOAD ≤ 75 μA
1.63
Low power (LP) mode,
1.63
—
2.1
V
LPCMPBIAS3 = 3, 1.8 V target
output, IDCDC_LOAD ≤ 10 mA
Steady-state output ripple
VR
Radio disabled.
—
—
3
—
mVpp
mV
CCM Mode (LNFORCECCM3 =
1), Load changes between 0 mA
and 100 mA
Output voltage under/over-
shoot
VOV
—
150
DCM Mode (LNFORCECCM3 =
0), Load changes between 0 mA
and 10 mA
—
—
150
mV
Overshoot during LP to LN
CCM/DCM mode transitions com-
pared to DC level in LN mode
—
—
200
50
—
—
mV
mV
Undershoot during BYP/LP to LN
CCM (LNFORCECCM3 = 1) mode
transitions compared to DC level
in LN mode
Undershoot during BYP/LP to LN
—
125
—
mV
DCM (LNFORCECCM3 = 0) mode
transitions compared to DC level
in LN mode
DC line regulation
DC load regulation
VREG
Input changes between
VVREGVDD_MAX and 2.4 V
—
—
0.1
0.1
—
—
%
%
IREG
Load changes between 0 mA and
100 mA in CCM mode
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EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Max load current
ILOAD_MAX
Low noise (LN) mode, Heavy
Drive4
—
—
200
mA
Low noise (LN) mode, Medium
Drive4
—
—
—
—
—
—
—
—
100
50
mA
mA
μA
Low noise (LN) mode, Light
Drive4
Low power (LP) mode,
LPCMPBIAS3 = 0
75
Low power (LP) mode,
LPCMPBIAS3 = 3
10
mA
DCDC nominal output ca-
pacitor
CDCDC
25% tolerance
1
1
1
μF
μH
Ω
DCDC nominal output induc- LDCDC
tor
20% tolerance
4.7
—
4.7
1.2
4.7
2.5
Resistance in Bypass mode RBYP
Note:
1. Due to internal dropout, the DC-DC output will never be able to reach its input voltage, VVREGVDD
2. LP mode controller is a hysteretic controller that maintains the output voltage within the specified limits
3. In EMU_DCDCMISCCTRL register
4. Drive levels are defined by configuration of the PFETCNT and NFETCNT registers. Light Drive: PFETCNT=NFETCNT=3; Medi-
um Drive: PFETCNT=NFETCNT=7; Heavy Drive: PFETCNT=NFETCNT=15.
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EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Electrical Specifications
4.1.4 Current Consumption
4.1.4.1 Current Consumption 3.3 V without DC-DC Converter
Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = DVDD = RFVDD = PAVDD = 3.3 V. TOP = 25 °C.
EMU_PWRCFG_PWRCG=NODCDC. EMU_DCDCCTRL_DCDCMODE=BYPASS. Minimum and maximum values in this table repre-
sent the worst conditions across supply voltage and process variation at TOP = 25 °C. See Figure 5.1 EFR32BG1 Typical Application
Circuit: Direct Supply Configuration without DC-DC converter on page 64.
Table 4.4. Current Consumption 3.3V without DC/DC
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Current consumption in EM0 IACTIVE
Active mode with all periph-
erals disabled
38.4 MHz crystal, CPU running
while loop from flash1
—
130
—
μA/MHz
38 MHz HFRCO, CPU running
Prime from flash
—
—
—
—
—
—
88
100
112
102
222
65
—
105
—
μA/MHz
μA/MHz
μA/MHz
μA/MHz
μA/MHz
μA/MHz
38 MHz HFRCO, CPU running
while loop from flash
38 MHz HFRCO, CPU running
CoreMark from flash
26 MHz HFRCO, CPU running
while loop from flash
106
350
—
1 MHz HFRCO, CPU running
while loop from flash
38.4 MHz crystal1
38 MHz HFRCO
26 MHz HFRCO
1 MHz HFRCO
Current consumption in EM1 IEM1
Sleep mode with all peripher-
als disabled
—
—
—
—
35
37
38
41
μA/MHz
μA/MHz
μA/MHz
μA
157
3.3
275
—
Current consumption in EM2 IEM2
Deep Sleep mode.
Full RAM retention and RTCC
running from LFXO
4 kB RAM retention and RTCC
running from LFRCO
—
—
—
—
3
6.3
6
μA
μA
μA
μA
Current consumption in EM3 IEM3
Stop mode
Full RAM retention and CRYO-
TIMER running from ULFRCO
2.8
1.1
0.65
Current consumption in
EM4H Hibernate mode
IEM4
128 byte RAM retention, RTCC
running from LFXO
—
—
128 byte RAM retention, CRYO-
TIMER running from ULFRCO
128 byte RAM retention, no RTCC
no RAM retention, no RTCC
—
—
0.65
0.04
1.3
μA
μA
Current consumption in
EM4S Shutoff mode
IEM4S
0.11
Note:
1. CMU_HFXOCTRL_LOWPOWER=0
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EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Electrical Specifications
4.1.4.2 Current Consumption 3.3 V using DC-DC Converter
Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD = 1.8 V DC-DC
output. TOP = 25 °C. Minimum and maximum values in this table represent the worst conditions across supply voltage and process
variation at TOP = 25 °C. See Figure 5.2 EFR32BG1 Typical Application Circuit: Configuration with DC-DC converter (PAVDD from
VDCDC) on page 64.
Table 4.5. Current Consumption 3.3V with DC-DC
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Current consumption in EM0 IACTIVE
Active mode with all periph-
erals disabled, DCDC in Low
Noise DCM mode1.
38.4 MHz crystal, CPU running
while loop from flash2
—
88
—
μA/MHz
38 MHz HFRCO, CPU running
Prime from flash
—
—
—
—
—
63
71
78
76
98
—
—
—
—
—
μA/MHz
μA/MHz
μA/MHz
μA/MHz
μA/MHz
38 MHz HFRCO, CPU running
while loop from flash
38 MHz HFRCO, CPU running
CoreMark from flash
26 MHz HFRCO, CPU running
while loop from flash
Current consumption in EM0
Active mode with all periph-
erals disabled, DCDC in Low
Noise CCM mode3.
38.4 MHz crystal, CPU running
while loop from flash2
38 MHz HFRCO, CPU running
Prime from flash
—
—
—
—
—
75
81
88
94
49
—
—
—
—
—
μA/MHz
μA/MHz
μA/MHz
μA/MHz
μA/MHz
38 MHz HFRCO, CPU running
while loop from flash
38 MHz HFRCO, CPU running
CoreMark from flash
26 MHz HFRCO, CPU running
while loop from flash
38.4 MHz crystal2
38 MHz HFRCO
26 MHz HFRCO
Current consumption in EM1 IEM1
Sleep mode with all peripher-
als disabled, DCDC in Low
Noise DCM mode1.
—
—
—
32
38
61
—
—
—
μA/MHz
μA/MHz
μA/MHz
38.4 MHz crystal2
38 MHz HFRCO
26 MHz HFRCO
Current consumption in EM1
Sleep mode with all peripher-
als disabled, DCDC in Low
Noise CCM mode3.
—
—
—
45
58
—
—
—
μA/MHz
μA/MHz
μA
Current consumption in EM2 IEM2
Deep Sleep mode. DCDC in
Low Power mode4.
Full RAM retention and RTCC
running from LFXO
2.5
4 kB RAM retention and RTCC
running from LFRCO
—
—
—
—
—
2.3
2.1
—
—
—
—
—
μA
μA
μA
μA
μA
Current consumption in EM3 IEM3
Stop mode
Full RAM retention and CRYO-
TIMER running from ULFRCO
Current consumption in
EM4H Hibernate mode
IEM4
128 byte RAM retention, RTCC
running from LFXO
0.86
0.58
0.58
128 byte RAM retention, CRYO-
TIMER running from ULFRCO
128 byte RAM retention, no RTCC
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Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Current consumption in
EM4S Shutoff mode
IEM4S
no RAM retention, no RTCC
—
0.04
—
μA
Note:
1. DCDC Low Noise DCM Mode = Light Drive (PFETCNT=NFETCNT=3), F=3.0 MHz (RCOBAND=0), ANASW=DVDD
2. CMU_HFXOCTRL_LOWPOWER=0
3. DCDC Low Noise CCM Mode = Light Drive (PFETCNT=NFETCNT=3), F=6.4 MHz (RCOBAND=4), ANASW=DVDD
4. DCDC Low Power Mode = Medium Drive (PFETCNT=NFETCNT=7), LPOSCDIV=1, LPBIAS=3, LPCILIMSEL=1, ANASW=DVDD
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Electrical Specifications
4.1.4.3 Current Consumption 1.85 V without DC-DC Converter
Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = DVDD = RFVDD = PAVDD = 1.85 V. TOP = 25 °C.
EMU_PWRCFG_PWRCG=NODCDC. EMU_DCDCCTRL_DCDCMODE=BYPASS. Minimum and maximum values in this table repre-
sent the worst conditions across supply voltage and process variation at TOP = 25 °C. See Figure 5.1 EFR32BG1 Typical Application
Circuit: Direct Supply Configuration without DC-DC converter on page 64.
Table 4.6. Current Consumption 1.85V without DC/DC
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Current consumption in EM0 IACTIVE
Active mode with all periph-
erals disabled
38.4 MHz crystal, CPU running
while loop from flash1
—
131
—
μA/MHz
38 MHz HFRCO, CPU running
Prime from flash
—
—
—
—
—
—
88
100
112
102
220
65
—
—
—
—
—
—
μA/MHz
μA/MHz
μA/MHz
μA/MHz
μA/MHz
μA/MHz
38 MHz HFRCO, CPU running
while loop from flash
38 MHz HFRCO, CPU running
CoreMark from flash
26 MHz HFRCO, CPU running
while loop from flash
1 MHz HFRCO, CPU running
while loop from flash
38.4 MHz crystal1
38 MHz HFRCO
26 MHz HFRCO
1 MHz HFRCO
Current consumption in EM1 IEM1
Sleep mode with all peripher-
als disabled
—
—
—
—
35
37
—
—
—
—
μA/MHz
μA/MHz
μA/MHz
μA
154
3.2
Current consumption in EM2 IEM2
Deep Sleep mode
Full RAM retention and RTCC
running from LFXO
4 kB RAM retention and RTCC
running from LFRCO
—
—
—
—
2.8
2.7
1
—
—
—
—
μA
μA
μA
μA
Current consumption in EM3 IEM3
Stop mode
Full RAM retention and CRYO-
TIMER running from ULFRCO
Current consumption in
EM4H Hibernate mode
IEM4
128 byte RAM retention, RTCC
running from LFXO
128 byte RAM retention, CRYO-
TIMER running from ULFRCO
0.62
128 byte RAM retention, no RTCC
No RAM retention, no RTCC
—
—
0.62
0.02
—
—
μA
μA
Current consumption in
EM4S Shutoff mode
IEM4S
Note:
1. CMU_HFXOCTRL_LOWPOWER=0
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EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Electrical Specifications
4.1.4.4 Current Consumption Using Radio
Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD. TOP = 25 °C.
Minimum and maximum values in this table represent the worst conditions across supply voltage and process variation at TOP = 25 °C.
See Figure 5.2 EFR32BG1 Typical Application Circuit: Configuration with DC-DC converter (PAVDD from VDCDC) on page 64 or
Figure 5.1 EFR32BG1 Typical Application Circuit: Direct Supply Configuration without DC-DC converter on page 64.
Table 4.7. Current Consumption Using Radio 3.3 V with DC-DC
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Current consumption in re-
ceive mode, active packet
reception (MCU in EM1 @
38.4 MHz, peripheral clocks
disabled)
IRX
1 Mbit/s, 2GFSK, F = 2.4 GHz,
Radio clock prescaled by 4
—
8.7
—
mA
Current consumption in
transmit mode (MCU in EM1
@ 38.4 MHz, peripheral
clocks disabled)
ITX
F = 2.4 GHz, CW, 0 dBm output
power, Radio clock prescaled by 3
—
—
—
—
—
8.2
—
—
—
—
—
mA
mA
mA
mA
mA
F = 2.4 GHz, CW, 3 dBm output
power
16.5
23.3
32.7
83.9
F = 2.4 GHz, CW, 8 dBm output
power
F = 2.4 GHz, CW, 10.5 dBm out-
put power
F = 2.4 GHz, CW, 16.5 dBm out-
put power, PAVDD connected di-
rectly to external 3.3V supply
F = 2.4 GHz, CW, 19.5 dBm out-
put power, PAVDD connected di-
rectly to external 3.3V supply
—
—
126.7
51
—
—
mA
nA
RFSENSE current consump- IRFSENSE
tion
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EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Electrical Specifications
4.1.5 Wake up times
Table 4.8. Wake up times
Parameter
Symbol
Test Condition
Min
—
Typ
10.7
3
Max
—
Unit
μs
Wake up from EM2 Deep
Sleep
tEM2_WU
Code execution from flash
Code execution from RAM
Executing from flash
—
—
μs
Wakeup time from EM1
Sleep
tEM1_WU
—
3
—
AHB
Clocks
Executing from RAM
—
3
—
AHB
Clocks
Wake up from EM3 Stop
tEM3_WU
Executing from flash
Executing from RAM
Executing from flash
—
—
—
10.7
3
—
—
—
μs
μs
μs
Wake up from EM4H Hiber- tEM4H_WU
nate1
60
Wake up from EM4S Shut-
off1
tEM4S_WU
—
290
—
μs
Note:
1. Time from wakeup request until first instruction is executed. Wakeup results in device reset.
4.1.6 Brown Out Detector
Table 4.9. Brown Out Detector
Parameter
Symbol
Test Condition
DVDD rising
Min
—
Typ
—
Max
1.62
—
Unit
V
DVDDBOD threshold
VDVDDBOD
DVDD falling
1.35
—
—
V
DVDD BOD hysteresis
DVDD response time
AVDD BOD threshold
VDVDDBOD_HYST
24
2.4
—
—
mV
μs
V
tDVDDBOD_DELAY Supply drops at 0.1V/μs rate
—
—
VAVDDBOD
AVDD rising
AVDD falling
—
1.85
—
1.62
—
—
V
AVDD BOD hysteresis
AVDD response time
EM4 BOD threshold
VAVDDBOD_HYST
21
2.4
—
—
mV
μs
V
tAVDDBOD_DELAY Supply drops at 0.1V/μs rate
—
—
VEM4DBOD
AVDD rising
AVDD falling
—
1.7
—
1.45
—
—
V
EM4 BOD hysteresis
EM4 response time
VEM4BOD_HYST
46
300
—
mV
μs
tEM4BOD_DELAY Supply drops at 0.1V/μs rate
—
—
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Preliminary Rev. 1.1 | 22
EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Electrical Specifications
4.1.7 Frequency Synthesizer Characteristics
Table 4.10. Frequency Synthesizer Characteristics
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
RF Synthesizer Frequency
range
FRANGE_2400
2.4 GHz frequency range
2400
—
2483.5
MHz
LO tuning frequency resolu- FRES_2400
tion with 38.4 MHz crystal
2400 - 2483.5 MHz
—
—
—
—
73
Hz
Maximum frequency devia-
tion with 38.4 MHz crystal
ΔFMAX_2400
1677
kHz
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Preliminary Rev. 1.1 | 23
EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Electrical Specifications
4.1.8 2.4 GHz RF Transceiver Characteristics
4.1.8.1 RF Transmitter General Characteristics for the 2.4 GHz Band
Unless otherwise indicated, typical conditions are: TOP = 25 °C,VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4MHz. RF center frequency 2.45 GHz. Test circuit according to
Figure 5.2 EFR32BG1 Typical Application Circuit: Configuration with DC-DC converter (PAVDD from VDCDC) on page 64 and Fig-
ure 5.4 Typical 2.4 GHz RF impedance-matching network circuits on page 65.
Table 4.11. RF Transmitter General Characteristics for 2.4 GHz Band
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Maximum TX power1
POUTMAX
19.5 dBm-rated part numbers.
PAVDD connected directly to ex-
ternal 3.3V supply2
—
19.5
—
dBm
10.5 dBm-rated part numbers
0 dBm-rated part numbers
CW
—
—
10.5
0
—
—
—
—
—
dBm
dBm
dBm
dB
Minimum active TX Power
Output power step size
POUTMIN
-30
1
POUTSTEP
-5 dBm< Output power < 0 dBm
—
—
0 dBm < output power <
POUTMAX
0.5
dB
Output power variation vs
supply at POUTMAX
POUTVAR_V
1.85 V < VVREGVDD < 3.3 V,
PAVDD connected directly to ex-
ternal supply, for output power >
10.5 dBm.
—
4.5
3.8
—
dB
dB
1.85 V < VVREGVDD < 3.3 V,
PAVDD connected directly to ex-
ternal supply, for output power =
10.5 dBm.
—
—
1.85 V < VVREGVDD < 3.3 V using
DC-DC converter
—
—
2.2
1.5
1.5
0.4
—
—
—
dB
dB
Output power variation vs
temperature at POUTMAX
POUTVAR_T
From -40 to +85 °C, PAVDD con-
nected to DC-DC output
From -40 to +85 °C, PAVDD con-
nected to external supply
—
—
dB
Output power variation vs RF POUTVAR_F
frequency at POUTMAX
Over RF tuning frequency range
—
—
dB
RF tuning frequency range
FRANGE
2400
2483.5
MHz
Note:
1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices cov-
ered in this datasheet can be found in the Max TX Power column of 2. Ordering Information
2. For Bluetooth, the Maximum TX power on Channel 2456 is limited to +15 dBm to comply with In-band Spurious emissions.
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Preliminary Rev. 1.1 | 24
EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Electrical Specifications
4.1.8.2 RF Receiver General Characteristics for the 2.4 GHz Band
Unless otherwise indicated, typical conditions are: TOP = 25 °C,VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4MHz. RF center frequency 2.440 GHz. Test circuit according
to Figure 5.2 EFR32BG1 Typical Application Circuit: Configuration with DC-DC converter (PAVDD from VDCDC) on page 64 and
Figure 5.4 Typical 2.4 GHz RF impedance-matching network circuits on page 65.
Table 4.12. RF Receiver General Characteristics for 2.4 GHz Band
Parameter
Symbol
FRANGE
SPURRX
Test Condition
Min
2400
—
Typ
—
Max
2483.5
—
Unit
MHz
dBm
dBm
dBm
RF tuning frequency range
Receive mode maximum
spurious emission
30 MHz to 1 GHz
1 GHz to 12 GHz
-57
—
-47
—
Max spurious emissions dur- SPURRX_FCC
ing active receive mode, per
FCC Part 15.109(a)
216 MHz to 960 MHz, Conducted
Measurement
—
-55.2
—
Above 960 MHz, Conducted
Measurement
—
—
-47.2
-24
—
—
dBm
dBm
Level above which
RFSENSE will trigger1
RFSENSETRIG
RFSENSETHRES
SENS2GFSK
CW at 2.45 GHz
Level below which
RFSENSE will not trigger1
—
-50
—
dBm
2 Mbps 2GFSK signal2
250 kbps 2GFSK signal
1% PER Sensitivity
—
—
-89.2
-99.1
—
—
dBm
dBm
0.1% BER Sensitivity
Note:
1. RFSENSE performance is only valid from 0 to 85 °C. RFSENSE should be disabled outside this temperature range.
2. Channel at 2420 MHz will have degraded sensitivity. Sensitivity could be as high as -83dBm on this channel.
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Preliminary Rev. 1.1 | 25
EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Electrical Specifications
4.1.8.3 RF Transmitter Characteristics for Bluetooth Smart in the 2.4 GHz Band
Unless otherwise indicated, typical conditions are: TOP = 25 °C,VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4MHz. RF center frequency 2.44 GHz. Test circuit according to
Figure 5.2 EFR32BG1 Typical Application Circuit: Configuration with DC-DC converter (PAVDD from VDCDC) on page 64 and Fig-
ure 5.4 Typical 2.4 GHz RF impedance-matching network circuits on page 65.
Table 4.13. RF Transmitter Characteristics for Bluetooth Smart in the 2.4GHz Band
Parameter
Symbol
TXBW
Test Condition
Min
—
Typ
740
-6.5
Max
—
Unit
Transmit 6dB bandwidth
Power spectral density limit
kHz
PSDLIMIT
Per FCC part 15.247 at 10 dBm
Per FCC part 15.247 at 20 dBm
—
—
dBm/
3kHz
—
—
—
-2.6
10
—
—
—
dBm/
3kHz
Per ETSI 300.328 at 10 dBm/1
MHz
dBm
Occupied channel bandwidth OCPETSI328
per ETSI EN300.328
99% BW at highest and lowest
channels in band
1.1
MHz
In-band spurious emissions SPURINB
at 10 dBm, with allowed ex-
ceptions1
At ±2 MHz
At ±3 MHz
—
—
-39.8
-42.1
—
—
dBm
dBm
In-band spurious emissions
at 20 dBm, with allowed ex-
ceptions1 2
At ±2 MHz
At ±3 MHz
—
—
—
—
-20
-30
dBm
dBm
Emissions of harmonics out- SPURHRM_FCC 2nd,3rd, 5, 6, 8, 9,10 harmonics;
—
-47
—
dBm
of-band, per FCC part
15.247
continuous transmission of modu-
lated carrier
Spurious emissions out-of-
band, per FCC part 15.247,
excluding harmonics cap-
tured in SPURHARM,FCC. Re-
stricted Bands
SPUROOB_FCC
Above 2.483 GHz or below 2.4
GHz; continuous transmission of
modulated carrier3
—
-47
—
dBm
Spurious emissions out-of-
band, per FCC part 15.247,
excluding harmonics cap-
Above 2.483 GHz or below 2.4
GHz; continuous transmission of
modulated carrier
—
-26
—
dBc
tured in SPURHARM,FCC
.
Non Restricted Bands
Spurious emissions out-of-
band; per ETSI 300.328
SPURETSI328
[2400-BW to 2400] MHz, [2483.5
to 2483.5+BW] MHz
—
—
-16
-26
—
—
dBm
dBm
[2400-2BW to 2400-BW] MHz,
[2483.5+BW to 2483.5+2BW]
MHz per ETSI 300.328
Spurious emissions per ETSI SPURETSI440
EN300.440
47-74 MHz,87.5-108 MHz,
174-230 MHz, 470-862 MHz
—
-60
—
dBm
25-1000 MHz
1-12 GHz
—
—
-42
-36
—
—
dBm
dBm
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Preliminary Rev. 1.1 | 26
EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Electrical Specifications
Parameter
Note:
Symbol
Test Condition
Min
Typ
Max
Unit
1. Per Bluetooth Core_4.2, Section 3.2.2, exceptions are allowed in up to three bands of 1 MHz width, centered on a frequency
which is an integer multiple of 1 MHz. These exceptions shall have an absolute value of -20 dBm or less.
2. For 2456 MHz, a maximum output power of 15 dBm is used to achieve this value.
3. For 2480 MHz, a maximum duty cycle of 20% is used to achieve this value.
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Preliminary Rev. 1.1 | 27
EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Electrical Specifications
4.1.8.4 RF Receiver Characteristics for Bluetooth Smart in the 2.4 GHz Band
Unless otherwise indicated, typical conditions are: TOP = 25 °C,VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4MHz. RF center frequency 2.440 GHz. Test circuit according
to Figure 5.2 EFR32BG1 Typical Application Circuit: Configuration with DC-DC converter (PAVDD from VDCDC) on page 64 and
Figure 5.4 Typical 2.4 GHz RF impedance-matching network circuits on page 65.
Table 4.14. RF Receiver Characteristics for Bluetooth Smart in the 2.4GHz Band
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Signal is reference signal1. Packet
length is 20 bytes.
Max usable receiver input
level, 0.1% BER
SAT
—
10
—
dBm
Sensitivity, 0.1% BER2
Signal is reference signal1. Using
DC-DC converter
SENS
—
—
-91
—
—
dBm
dBm
With non-ideal signals as speci-
fied in RF-PHY.TS.4.2.2, section
4.6.1
-90.2
Signal to co-channel interfer- C/ICC
er, 0.1% BER
Desired signal 3 dB above refer-
ence sensitivity
—
—
8.3
—
—
dB
dB
N+1 adjacent channel (1
MHz) selectivity, 0.1% BER,
with allowable exceptions.
Desired is reference signal at
-67 dBm
C/I1+
Interferer is reference signal at +1
MHz offset. Desired frequency
2402 MHz ≤ Fc ≤ 2480 MHz
-3.3
N-1 adjacent channel (1
MHz) selectivity, 0.1% BER,
with allowable exceptions.
Desired is reference signal at
-67 dBm
C/I1-
Interferer is reference signal at -1
MHz offset. Desired frequency
2402 MHz ≤ Fc ≤ 2480 MHz
—
1.3
—
dB
Alternate (2 MHz) selectivity, C/I2
0.1% BER, with allowable
exceptions. Desired is refer-
ence signal at -67 dBm
Interferer is reference signal at ± 2
MHz offset. Desired frequency
2402 MHz ≤ Fc ≤ 2480 MHz
—
—
-39.5
-43.8
—
—
dB
dB
Alternate (3 MHz) selectivity, C/I3
0.1% BER, with allowable
exceptions. Desired is refer-
ence signal at -67 dBm
Interferer is reference signal at ±3
MHz offset. Desired frequency
2404 MHz ≤ Fc ≤ 2480 MHz
Selectivity to image frequen- C/IIM
cy, 0.1% BER. Desired is ref-
erence signal at -67 dBm
Interferer is reference signal at im-
age frequency with 1 MHz preci-
sion
—
—
-29
—
—
dB
dB
Selectivity to image frequen- C/IIM+1
cy +1 MHz, 0.1% BER. De-
sired is reference signal at
-67 dBm
Interferer is reference signal at im-
age frequency +1 MHz with 1
MHz precision
-43.6
Blocking, 0.1% BER, Desired BLOCKOOB
is reference signal at -67
dBm. Interferer is CW in
OOB range.
Interferer frequency 30 MHz ≤ f ≤
2000 MHz
—
—
—
—
-27
-32
-32
-27
—
—
—
—
dBm
dBm
dBm
dBm
Interferer frequency 2003 MHz ≤ f
≤ 2399 MHz
Interferer frequency 2484 MHz ≤ f
≤ 2997 MHz
Interferer frequency 3 GHz ≤ f ≤
12.75 GHz
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Preliminary Rev. 1.1 | 28
EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Intermodulation performance IM
Per Core_4.1, Vol 6, Part A, Sec-
tion 4.4 with n = 3
—
-25.8
—
dBm
Upper limit of input power
range over which RSSI reso-
lution is maintained
RSSIMAX
4
—
—
—
—
-101
0.5
dBm
dBm
dB
Lower limit of input power
range over which RSSI reso-
lution is maintained
RSSIMIN
RSSIRES
—
—
RSSI resolution
Over RSSIMIN to RSSIMAX
Note:
1. Reference signal is defined 2GFSK at -67 dBm, Modulation index = 0.5, BT = 0.5, Bit rate = 1 Mbps, desired data = PRBS9;
interferer data = PRBS15; frequency accuracy better than 1 ppm
2. Receive sensitivity on Bluetooth Smart channel 26 is -86 dBm
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Preliminary Rev. 1.1 | 29
EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Electrical Specifications
4.1.8.5 RF Transmitter Characteristics for 802.15.4 O-QPSK DSSS in the 2.4 GHz Band
Unless otherwise indicated, typical conditions are: T=25 °C,VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD. RFVDD
and PAVDD path is filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 2.45 GHz. Test circuit according to Figure
5.2 EFR32BG1 Typical Application Circuit: Configuration with DC-DC converter (PAVDD from VDCDC) on page 64 and Figure
5.4 Typical 2.4 GHz RF impedance-matching network circuits on page 65.
Table 4.15. RF Transmitter Characteristics for 802.15.4 DSSS-OQPSK in the 2.4GHz Band
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Error vector magnitude (off- EVM
set EVM), per
802.15.4-2011, not including
2415 MHz channel1
Average across frequency. Signal
is DSSS-OQPSK reference pack-
et2
—
5.5
—
% rms
Power spectral density limit
PSDLIMIT
Relative, at carrier ±3.5 MHz
—
—
-26
-36
—
—
dBc
Absolute, at carrier ±3.5 MHz3
Per FCC part 15.247
dBm
—
—
-4.2
12
—
—
dBm/
3kHz
Output power level which meets
10dBm/MHz ETSI 300.328 speci-
fication
dBm
Occupied channel bandwidth OCPETSI328
per ETSI EN300.328
99% BW at highest and lowest
channels in band
—
—
2.25
—
—
MHz
dBm
Spurious emissions of har-
monics in restricted bands
per FCC Part 15.205/15.209,
Emissions taken at
SPURHRM_FCC_ Continuous transmission of modu-
-45.8
lated carrier
R
Pout_Max power level of
19.5 dBm, PAVDD connec-
ted to external 3.3 V supply,
Test Frequency is 2450 MHz
Spurious emissions of har-
monics in harmonics in non-
restricted bands per FCC
Part 15.247/15.35, Emis-
sions taken at Pout_Max
power level of 19.5 dBm,
PAVDD connected to exter-
nal 3.3 V supply, Test Fre-
quency is 2450 MHz
SPURHRM_FCC_
—
-26
—
dBc
NRR
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Preliminary Rev. 1.1 | 30
EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Spurious emissions out-of-
band in restricted bands
(30-88 MHz), per FCC part
15.205/15.209, Emissions
taken at Pout_Max power
level of 19.5 dBm, PAVDD
connected to external 3.3 V
supply, Test Frequency =
2450 MHz
SPUROOB_FCC_ Above 2.483 GHz or below 2.4
—
-52
—
dBm
GHz; continuous transmission of
R
modulated carrier4
Spurious emissions out-of-
band in restricted bands
(88-216 MHz), per FCC part
15.205/15.209, Emissions
taken at Pout_Max power
level of 19.5 dBm, PAVDD
connected to external 3.3 V
supply, Test Frequency =
2450 MHz
—
—
—
—
-62
-57
-48
-26
—
—
—
—
dBm
dBm
dBm
dBc
Spurious emissions out-of-
band in restricted bands
(216-960 MHz), per FCC
part 15.205/15.209, Emis-
sions taken at Pout_Max
power level of 19.5 dBm,
PAVDD connected to exter-
nal 3.3 V supply, Test Fre-
quency = 2450 MHz
Spurious emissions out-of-
band in restricted bands
(>960 MHz), per FCC part
15.205/15.209, Emissions
taken at Pout_Max power
level of 19.5 dBm, PAVDD
connected to external 3.3 V
supply, Test Frequency =
2450 MHz
Spurious emissions out-of-
band in non-restricted bands
per FCC Part 15.247, Emis-
sions taken at Pout_Max
power level of 19.5 dBm,
PAVDD connected to exter-
nal 3.3 V supply, Test Fre-
quency = 2450 MHz
SPUROOB_FCC_ Above 2.483 GHz or below 2.4
GHz; continuous transmission of
NR
modulated carrier
Spurious emissions out-of-
band; per ETSI 300.3285
SPURETSI328
[2400-BW to 2400], [2483.5 to
2483.5+BW];
—
—
-16
-26
—
—
dBm
dBm
[2400-2BW to 2400-BW],
[2483.5+BW to 2483.5+2BW]; per
ETSI 300.328
Spurious emissions per ETSI SPURETSI440
EN300.4405
47-74 MHz,87.5-108 MHz,
174-230 MHz, 470-862 MHz
—
—
—
-60
-42
-36
—
—
—
dBm
dBm
dBm
25-1000 MHz, excluding above
frequencies
1G-14G
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Preliminary Rev. 1.1 | 31
EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Electrical Specifications
Parameter
Note:
Symbol
Test Condition
Min
Typ
Max
Unit
1. Typical EVM for the 2415 MHz channel is 7.9%
2. Reference packet is defined as 20 octet PSDU, modulated according to 802.15.4-2011 DSSS-OQPSK in the 2.4GHz band, with
pseudo-random packet data content
3. For 2415 MHz, a maximum duty cycle of 50% is used to achieve this value.
4. For 2480 MHz, a maximum duty cycle of 20% is used to achieve this value.
5. Specified at maximum power output level of 10 dBm
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EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Electrical Specifications
4.1.8.6 RF Receiver Characteristics for 802.15.4 O-QPSK DSSS in the 2.4 GHz Band
Unless otherwise indicated, typical conditions are: T=25 °C,VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD. RFVDD
and PAVDD path is filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 2.445 GHz. Test circuit according to Figure
5.2 EFR32BG1 Typical Application Circuit: Configuration with DC-DC converter (PAVDD from VDCDC) on page 64 and Figure
5.4 Typical 2.4 GHz RF impedance-matching network circuits on page 65.
Table 4.16. RF Receiver Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Signal is reference signal1. Packet
length is 20 octets.
Max usable receiver input
level, 1% PER
SAT
—
10
—
dBm
Sensitivity, 1% PER2
SENS
Signal is reference signal. Packet
length is 20 octets. Using DC-DC
converter.
—
—
-101
-101
—
—
dBm
dBm
Signal is reference signal. Packet
length is 20 octets. Without DC-
DC converter.
Co-channel interferer rejec- CCR
tion, 1% PER
Desired signal 10 dB above sensi-
tivity limit
—
—
—
-2.6
33.75
52.2
—
—
—
dB
dB
dB
High-side adjacent channel
rejection, 1% PER. Desired
is reference signal at 3dB
above reference sensitivity
ACR+1
Interferer is reference signal at +1
channel-spacing.
Interferer is filtered reference sig-
nal4 at +1 channel-spacing.
level3
Interferer is CW at +1 channel-
spacing.5
—
58.6
—
dB
Low-side adjacent channel
rejection, 1% PER. Desired
is reference signal at 3dB
above reference sensitivity
ACR-1
ACR2
IR
Interferer is reference signal at -1
channel-spacing.
—
—
35
—
—
dB
dB
Interferer is filtered reference sig-
nal4 at -1 channel-spacing.
54.7
level3
Interferer is CW at -1 channel-
spacing.
—
—
—
60.1
45.9
56.8
—
—
—
dB
dB
dB
Alternate channel rejection,
1% PER. Desired is refer-
ence signal at 3dB above
reference sensitivity level3
Interferer is reference signal at ±2
channel-spacing
Interferer is filtered reference sig-
nal4 at ±2 channel-spacing
Interferer is CW at ±2 channel-
spacing
—
—
65.5
40.8
—
—
dB
dB
Interferer is CW in image band5
Image rejection, 1% PER,
Desired is reference signal at
3dB above reference sensi-
tivity level3
Blocking rejection of all other BLOCK
channels. 1% PER, Desired
is reference signal at 3dB
above reference sensitivity
level3. Interferer is reference
signal.
Interferer frequency < Desired fre-
quency - 3 channel-spacing
—
—
57.2
57.9
—
—
dB
dB
Interferer frequency > Desired fre-
quency + 3 channel-spacing
Blocking rejection of 802.11g BLOCK80211G
signal centered at +12MHz
or -13MHz
Desired is reference signal at 6dB
above reference sensitivity level3
—
51.6
—
dB
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Preliminary Rev. 1.1 | 33
EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Upper limit of input power
range over which RSSI reso-
lution is maintained
RSSIMAX
5
—
—
dBm
Lower limit of input power
range over which RSSI reso-
lution is maintained
RSSIMIN
—
—
-98
dBm
RSSI resolution
RSSIRES
RSSILIN
over RSSIMIN to RSSIMAX
—
—
0.25
±1
—
—
dB
dB
RSSI accuracy in the linear
region as defined by
802.15.4-2003
Note:
1. Reference signal is defined as O-QPSK DSSS per 802.15.4, Frequency range = 2400-2483.5 MHz, Symbol rate = 62.5 ksym-
bols/s
2. Receive sensitivity on 802.15.4 channel 14 is -98 dBm
3. Reference sensitivity level is -85 dBm
4. Filter is characterized as a symmetric bandpass centered on the adjacent channel having a 3dB bandwidth of 4.6 MHz and stop-
band rejection better than 26 dB beyond 3.15 MHz from the adjacent carrier.
5. Due to low-IF frequency, there is some overlap of adjacent channel and image channel bands. Adjacent channel CW blocker
tests place the Interferer center frequency at the Desired frequency ±5 MHz on the channel raster, whereas the image rejection
test places the CW interferer near the image frequency of the Desired signal carrier, regardless of the channel raster.
4.1.9 Modem Features
Table 4.17. Modem Features
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Receive Bandwidth
RXBandwidth
Configurable range with 38.4 MHz
crystal
0.1
—
2530
kHz
IF Frequency
IFFreq
Configurable range with 38.4 MHz
crystal. Selected steps available.
150
—
1371
kHz
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4.1.10 Oscillators
4.1.10.1 LFXO
Table 4.18. LFXO
Parameter
Symbol
Test Condition
Min
—
Typ
32.768
—
Max
—
Unit
kHz
kΩ
Crystal frequency
fLFXO
Supported crystal equivalent ESRLFXO
series resistance (ESR)
—
70
Supported range of crystal
load capacitance 1
CLFXO_CL
6
8
—
—
18
40
pF
pF
On-chip tuning cap range 2
CLFXO_T
On each of LFXTAL_N and
LFXTAL_P pins
On-chip tuning cap step size SSLFXO
—
—
0.25
273
—
—
pF
nA
ESR = 70 kΩ, CL = 7 pF, GAIN4 =
3, AGC4 = 1
Current consumption after
startup 3
ILFXO
ESR=70 kΩ, CL = 7 pF, GAIN4 =
2
Start- up time
tLFXO
—
308
—
ms
Note:
1. Total load capacitance as seen by the crystal
2. The effective load capacitance seen by the crystal will be CLFXO_T /2. This is because each XTAL pin has a tuning cap and the
two caps will be seen in series by the crystal.
3. Block is supplied by AVDD if ANASW = 0, or DVDD if ANASW=1 in EMU_PWRCTRL register
4. In CMU_LFXOCTRL register
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4.1.10.2 HFXO
Table 4.19. HFXO
Parameter
Symbol
Test Condition
Min
38
Typ
38.4
—
Max
40
Unit
MHz
Ω
Crystal Frequency
fHFXO
Supported crystal equivalent ESRHFXO
series resistance (ESR)
Crystal frequency 38.4 MHz
—
60
Supported range of crystal
load capacitance 1
CHFXO_CL
6
—
12
pF
On-chip tuning cap range 2
CHFXO_T
SSHFXO
tHFXO
On each of HFXTAL_N and
HFXTAL_P pins
9
20
0.04
300
—
25
—
—
40
pF
pF
On-chip tuning capacitance
step
—
Startup time
38.4 MHz, ESR = 50 Ω, CL = 10
pF
—
μs
Frequency Tolerance for the FTHFXO
crystal
38.4 MHz, ESR = 50 Ω, CL = 10
pF
-40
ppm
Note:
1. Total load capacitance as seen by the crystal
2. The effective load capacitance seen by the crystal will be CHFXO_T /2. This is because each XTAL pin has a tuning cap and the
two caps will be seen in series by the crystal.
4.1.10.3 LFRCO
Table 4.20. LFRCO
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Oscillation frequency
fLFRCO
ENVREF = 1 in
26.2
32.768
34.5
kHz
CMU_LFRCOCTRL
ENVREF = 0 in
26.2
32.768
34.5
kHz
CMU_LFRCOCTRL
Startup time
tLFRCO
ILFRCO
—
—
500
342
—
—
μs
Current consumption 1
ENVREF = 1 in
CMU_LFRCOCTRL
nA
ENVREF = 0 in
—
494
—
nA
CMU_LFRCOCTRL
Note:
1. Block is supplied by AVDD if ANASW = 0, or DVDD if ANASW=1 in EMU_PWRCTRL register
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EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Electrical Specifications
4.1.10.4 HFRCO and AUXHFRCO
Table 4.21. HFRCO and AUXHFRCO
Parameter
Symbol
fHFRCO_ACC
Test Condition
Min
Typ
Max
Unit
Frequency Accuracy
Any frequency band, across sup-
ply voltage and temperature
-10
—
3
%
Start-up time
tHFRCO
fHFRCO ≥ 19 MHz
4 < fHFRCO < 19 MHz
fHFRCO ≤ 4 MHz
fHFRCO = 38 MHz
fHFRCO = 32 MHz
fHFRCO = 26 MHz
fHFRCO = 19 MHz
fHFRCO = 16 MHz
fHFRCO = 13 MHz
fHFRCO = 7 MHz
fHFRCO = 4 MHz
fHFRCO = 2 MHz
fHFRCO = 1 MHz
Coarse (% of period)
Fine (% of period)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
300
1
—
—
ns
μs
2.5
204
171
147
126
110
100
81
—
μs
Current consumption on all
supplies
IHFRCO
228
190
164
138
120
110
91
μA
μA
μA
μA
μA
μA
μA
33
35
μA
31
35
μA
30
35
μA
Step size
SSHFRCO
0.8
0.1
0.2
—
%
—
%
Period Jitter
PJHFRCO
—
% RMS
4.1.10.5 ULFRCO
Table 4.22. ULFRCO
Test Condition
Parameter
Symbol
Min
Typ
Max
Unit
Oscillation frequency
fULFRCO
0.8
1
1.05
kHz
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EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Electrical Specifications
4.1.11 Flash Memory Characteristics
Table 4.23. Flash Memory Characteristics1
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Flash erase cycles before
failure
ECFLASH
10000
—
—
cycles
Flash data retention
RETFLASH
tW_PROG
10
20
—
—
years
μs
Word (32-bit) programming
time
26
40
Page erase time
Mass erase time
tPERASE
tMERASE
tDERASE
IERASE
20
20
—
—
—
27
27
60
—
—
40
40
74
3
ms
ms
ms
mA
mA
Device erase time2
Page erase current3
Mass or Device erase cur-
rent3
5
Write current3
IWRITE
—
—
3
mA
Note:
1. Flash data retention information is published in the Quarterly Quality and Reliability Report.
2. Device erase is issued over the AAP interface and erases all flash, SRAM, the Lock Bit (LB) page, and the User data page Lock
Word (ULW)
3. Measured at 25°C
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EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
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4.1.12 GPIO
Table 4.24. GPIO
Parameter
Symbol
VIOIL
Test Condition
Min
—
Typ
—
Max
IOVDD*0.3
—
Unit
V
Input low voltage
Input high voltage
VIOIH
IOVDD*0.7
IOVDD*0.8
—
V
Output high voltage relative VIOOH
to IOVDD
Sourcing 3 mA, IOVDD ≥ 3 V,
DRIVESTRENGTH1 = WEAK
—
—
V
Sourcing 1.2 mA, IOVDD ≥ 1.62
V,
IOVDD*0.6
—
—
V
DRIVESTRENGTH1 = WEAK
Sourcing 20 mA, IOVDD ≥ 3 V,
IOVDD*0.8
—
—
—
—
—
—
0.1
—
V
V
DRIVESTRENGTH1 = STRONG
Sourcing 8 mA, IOVDD ≥ 1.62 V,
IOVDD*0.6
—
DRIVESTRENGTH1 = STRONG
Sinking 3 mA, IOVDD ≥ 3 V,
Output low voltage relative to VIOOL
IOVDD
—
—
—
—
—
IOVDD*0.2
IOVDD*0.4
IOVDD*0.2
IOVDD*0.4
30
V
DRIVESTRENGTH1 = WEAK
Sinking 1.2 mA, IOVDD ≥ 1.62 V,
V
DRIVESTRENGTH1 = WEAK
Sinking 20 mA, IOVDD ≥ 3 V,
V
DRIVESTRENGTH1 = STRONG
Sinking 8 mA, IOVDD ≥ 1.62 V,
V
DRIVESTRENGTH1 = STRONG
Input leakage current
IIOLEAK
All GPIO except LFXO pins, GPIO
≤ IOVDD
nA
LFXO Pins, GPIO ≤ IOVDD
—
—
0.1
3.3
50
15
nA
μA
Input leakage current on
I5VTOLLEAK
IOVDD < GPIO ≤ IOVDD + 2 V
5VTOL pads above IOVDD
I/O pin pull-up resistor
RPU
30
30
20
43
43
25
65
65
35
kΩ
kΩ
ns
I/O pin pull-down resistor
RPD
Pulse width of pulses re-
moved by the glitch suppres-
sion filter
tIOGLITCH
Output fall time, From 70%
to 30% of VIO
tIOOF
CL = 50 pF,
—
—
1.8
4.5
—
—
ns
ns
DRIVESTRENGTH1 = STRONG,
SLEWRATE1 = 0x6
CL = 50 pF,
DRIVESTRENGTH1 = WEAK,
SLEWRATE1 = 0x6
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EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Output rise time, From 30% tIOOR
to 70% of VIO
CL = 50 pF,
—
2.2
—
ns
DRIVESTRENGTH1 = STRONG,
SLEWRATE = 0x61
CL = 50 pF,
—
7.4
—
ns
DRIVESTRENGTH1 = WEAK,
SLEWRATE1 = 0x6
Note:
1. In GPIO_Pn_CTRL register
4.1.13 VMON
Table 4.25. VMON
Test Condition
Parameter
Symbol
IVMON
Min
Typ
Max
Unit
VMON Supply Current
In EM0 or EM1, 1 supply moni-
tored
—
5.8
8.26
μA
In EM0 or EM1, 4 supplies moni-
tored
—
—
—
11.8
62
16.8
—
μA
nA
nA
In EM2, EM3 or EM4, 1 supply
monitored
In EM2, EM3 or EM4, 4 supplies
monitored
99
—
VMON Loading of Monitored ISENSE
Supply
In EM0 or EM1
—
—
2
2
—
—
3.4
—
—
—
—
μA
nA
V
In EM2, EM3 or EM4
Threshold range
VVMON_RANGE
1.62
—
—
Threshold step size
NVMON_STESP
Coarse
200
20
460
26
mV
mV
ns
Fine
—
Response time
Hysteresis
tVMON_RES
Supply drops at 1V/μs rate
—
VVMON_HYST
—
mV
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EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
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4.1.14 ADC
Table 4.26. ADC
Parameter
Symbol
Test Condition
Min
Typ
—
Max
12
Unit
Bits
V
Resolution
VRESOLUTION
VADCIN
6
0
Input voltage range
Single ended
Differential
—
2*VREF
VREF
VAVDD
-VREF
1
—
V
Input range of external refer- VADCREFIN_P
ence voltage, single ended
and differential
—
V
Power supply rejection1
PSRRADC
At DC
At DC
—
—
80
80
—
—
dB
dB
Analog input common mode CMRRADC
rejection ratio
Current from all supplies, us- IADC_CONTI-
1 Msps / 16 MHz ADCCLK,
—
301
350
μA
ing internal reference buffer.
Continous operation. WAR-
MUPMODE2 = KEEPADC-
WARM
NOUS_LP
BIASPROG = 0, GPBIASACC = 1
3
250 ksps / 4 MHz ADCCLK, BIA-
SPROG = 6, GPBIASACC = 1 3
—
—
149
91
—
—
μA
μA
62.5 ksps / 1 MHz ADCCLK,
BIASPROG = 15, GPBIASACC =
1 3
Current from all supplies, us- IADC_NORMAL_LP 35 ksps / 16 MHz ADCCLK,
ing internal reference buffer.
—
—
—
—
—
51
9
—
—
—
—
—
μA
μA
μA
μA
μA
BIASPROG = 0, GPBIASACC = 1
Duty-cycled operation. WAR-
MUPMODE2 = NORMAL
3
5 ksps / 16 MHz ADCCLK
BIASPROG = 0, GPBIASACC = 1
3
Current from all supplies, us- IADC_STAND-
125 ksps / 16 MHz ADCCLK,
117
79
ing internal reference buffer.
Duty-cycled operation.
AWARMUPMODE2 = KEEP-
INSTANDBY or KEEPIN-
SLOWACC
BY_LP
BIASPROG = 0, GPBIASACC = 1
3
35 ksps / 16 MHz ADCCLK,
BIASPROG = 0, GPBIASACC = 1
3
Current from all supplies, us- IADC_CONTI-
1 Msps / 16 MHz ADCCLK,
345
ing internal reference buffer.
Continous operation. WAR-
MUPMODE2 = KEEPADC-
WARM
NOUS_HP
BIASPROG = 0, GPBIASACC = 0
3
250 ksps / 4 MHz ADCCLK, BIA-
SPROG = 6, GPBIASACC = 0 3
—
—
191
132
—
—
μA
μA
62.5 ksps / 1 MHz ADCCLK,
BIASPROG = 15, GPBIASACC =
0 3
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EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Current from all supplies, us- IADC_NORMAL_HP 35 ksps / 16 MHz ADCCLK,
ing internal reference buffer.
—
102
—
μA
BIASPROG = 0, GPBIASACC = 0
Duty-cycled operation. WAR-
3
MUPMODE2 = NORMAL
5 ksps / 16 MHz ADCCLK
—
—
—
17
—
—
—
μA
μA
μA
BIASPROG = 0, GPBIASACC = 0
3
Current from all supplies, us- IADC_STAND-
125 ksps / 16 MHz ADCCLK,
162
123
ing internal reference buffer.
BY_HP
BIASPROG = 0, GPBIASACC = 0
3
Duty-cycled operation.
AWARMUPMODE2 = KEEP-
INSTANDBY or KEEPIN-
SLOWACC
35 ksps / 16 MHz ADCCLK,
BIASPROG = 0, GPBIASACC = 0
3
Current from HFPERCLK
ADC Clock Frequency
Throughput rate
IADC_CLK
fADCCLK
fADCRATE
tADCCONV
HFPERCLK = 16 MHz
—
—
—
—
—
—
—
140
—
—
7
—
16
1
μA
MHz
Msps
cycles
cycles
cycles
μs
Conversion time4
6 bit
8 bit
12 bit
—
—
—
5
9
13
—
WARMUPMODE2 = NORMAL
Startup time of reference
generator and ADC core
tADCSTART
WARMUPMODE2 = KEEPIN-
STANDBY
—
—
2
μs
WARMUPMODE2 = KEEPINSLO-
WACC
—
—
1
μs
SNDR at 1Msps and fin
10kHz
=
SNDRADC
Internal reference, 2.5 V full-scale,
differential (-1.25, 1.25)
58
—
—
—
67
68
—
—
—
—
dB
dB
dB
μV
vrefp_in = 1.25 V direct mode with
2.5 V full-scale, differential
Spurious-Free Dynamic
Range (SFDR)
SFDRADC
1 MSamples/s, 10 kHz full-scale
sine wave
75
Input referred ADC noise,
rms
VREF_NOISE
Including quantization noise and
distortion
380
Offset Error
VADCOFFSETERR
VADC_GAIN
-3
—
—
-1
0.25
-0.2
-1
3
5
LSB
%
Gain error in ADC
Using internal reference
Using external reference
—
2
%
Differential non-linearity
(DNL)
DNLADC
INLADC
12 bit resolution, No Missing Co-
des
—
LSB
Integral non-linearity (INL),
End point method
12 bit resolution
-6
—
6
LSB
Temperature Sensor Slope
VTS_SLOPE
—
-1.84
—
mV/°C
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EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Electrical Specifications
Parameter
Note:
Symbol
Test Condition
Min
Typ
Max
Unit
1. PSRR is referenced to AVDD when ANASW=0 and to DVDD when ANASW=1 in EMU_PWRCTRL
2. In ADCn_CNTL register
3. In ADCn_BIASPROG register
4. Derived from ADCCLK
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EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
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4.1.15 IDAC
Table 4.27. IDAC
Parameter
Symbol
Test Condition
Min
—
Typ
4
Max
—
Unit
-
Number of Ranges
Output Current
NIDAC_RANGES
IIDAC_OUT
RANGSEL1 = RANGE0
RANGSEL1 = RANGE1
RANGSEL1 = RANGE2
RANGSEL1 = RANGE3
0.05
—
1.6
μA
1.6
0.5
2
—
—
—
32
4.7
16
64
—
μA
μA
μA
Linear steps within each
range
NIDAC_STEPS
—
RANGSEL1 = RANGE0
RANGSEL1 = RANGE1
RANGSEL1 = RANGE2
RANGSEL1 = RANGE3
Step size
SSIDAC
—
—
—
—
-5
50
100
500
2
—
—
—
—
2
nA
nA
nA
μA
%
Total Accuracy, STEPSEL1 =
0x10
ACCIDAC
EM0 or EM1, AVDD=3.3 V, T = 25
°C
—
EM0 or EM1
-18
—
—
-2
22
—
%
%
EM2 or EM3, Source mode,
RANGSEL1 = RANGE0,
AVDD=3.3 V, T = 25 °C
EM2 or EM3, Source mode,
RANGSEL1 = RANGE1,
AVDD=3.3 V, T = 25 °C
—
—
—
—
—
—
—
—
-1.7
-0.8
-0.5
-0.7
-0.6
-0.5
-0.5
5
—
—
—
—
—
—
—
—
%
%
%
%
%
%
%
μs
EM2 or EM3, Source mode,
RANGSEL1 = RANGE2,
AVDD=3.3 V, T = 25 °C
EM2 or EM3, Source mode,
RANGSEL1 = RANGE3,
AVDD=3.3 V, T = 25 °C
EM2 or EM3, Sink mode, RANG-
SEL1 = RANGE0, AVDD=3.3 V, T
= 25 °C
EM2 or EM3, Sink mode, RANG-
SEL1 = RANGE1, AVDD=3.3 V, T
= 25 °C
EM2 or EM3, Sink mode, RANG-
SEL1 = RANGE2, AVDD=3.3 V, T
= 25 °C
EM2 or EM3, Sink mode, RANG-
SEL1 = RANGE3, AVDD=3.3 V, T
= 25 °C
Start up time
tIDAC_SU
Output within 1% of steady state
value
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EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
—
Typ
5
Max
—
Unit
μs
Settling time, (output settled tIDAC_SETTLE
within 1% of steady state val-
ue)
Range setting is changed
Step value is changed
—
1
—
μs
Current consumption in EM0 IIDAC
or EM1 2
Source mode, excluding output
current
—
—
—
8.9
12
13
16
—
μA
μA
μA
Sink mode, excluding output cur-
rent
Current consumption in EM2
or EM32
Source mode, excluding output
current, duty cycle mode, T = 25
°C
1.04
Sink mode, excluding output cur-
rent, duty cycle mode, T = 25 °C
—
—
1.08
8.9
—
—
μA
μA
Source mode, excluding output
current, duty cycle mode, T ≥ 85
°C
Sink mode, excluding output cur-
rent, duty cycle mode, T ≥ 85 °C
—
—
12
—
—
μA
%
Output voltage compliance in ICOMP_SRC
source mode, source current
change relative to current
sourced at 0 V
RANGESEL1=0, output voltage =
min(VIOVDD, VAVDD2-100 mv)
0.04
RANGESEL1=1, output voltage =
min(VIOVDD, VAVDD2-100 mV)
—
—
—
0.02
0.02
0.02
—
—
—
%
%
%
RANGESEL1=2, output voltage =
min(VIOVDD, VAVDD2-150 mV)
RANGESEL1=3, output voltage =
min(VIOVDD, VAVDD2-250 mV)
Output voltage compliance in ICOMP_SINK
sink mode, sink current
change relative to current
sunk at IOVDD
RANGESEL1=0, output voltage =
100 mV
—
—
—
—
0.18
0.12
0.08
0.02
—
—
—
—
%
%
%
%
RANGESEL1=1, output voltage =
100 mV
RANGESEL1=2, output voltage =
150 mV
RANGESEL1=3, output voltage =
250 mV
Note:
1. In IDAC_CURPROG register
2. The IDAC is supplied by either AVDD, DVDD, or IOVDD based on the setting of ANASW in the EMU_PWRCTRL register and
PWRSEL in the IDAC_CTRL register. Setting PWRSEL to 1 selects IOVDD. With PWRSEL cleared to 0, ANASW selects be-
tween AVDD (0) and DVDD (1).
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EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
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4.1.16 Analog Comparator (ACMP)
Table 4.28. ACMP
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Input voltage range
VACMPIN
ACMPVDD =
ACMPn_CTRL_PWRSEL 1
0
—
VACMPVDD
V
BIASPROG2 ≤ 0x10 or FULL-
BIAS2 = 0
Supply Voltage
VACMPVDD
1.85
2.1
—
—
VVREGVDD_
V
V
MAX
0x10 < BIASPROG2 ≤ 0x20 and
FULLBIAS2 = 1
VVREGVDD_
MAX
BIASPROG2 = 1, FULLBIAS2 = 0
Active current not including
voltage reference
IACMP
—
—
50
—
—
nA
nA
BIASPROG2 = 0x10, FULLBIAS2
= 0
306
BIASPROG2 = 0x20, FULLBIAS2
= 1
—
—
74
50
95
—
μA
nA
Current consumption of inter- IACMPREF
nal voltage reference
VLP selected as input using 2.5 V
Reference / 4 (0.625 V)
VLP selected as input using VDD
—
—
20
—
—
nA
μA
VBDIV selected as input using
1.25 V reference / 1
4.1
VADIV selected as input using
VDD/1
—
2.4
—
μA
HYSTSEL3 = HYST0
HYSTSEL3 = HYST1
HYSTSEL3 = HYST2
HYSTSEL3 = HYST3
HYSTSEL3 = HYST4
HYSTSEL3 = HYST5
HYSTSEL3 = HYST6
HYSTSEL3 = HYST7
HYSTSEL3 = HYST8
HYSTSEL3 = HYST9
HYSTSEL3 = HYST10
HYSTSEL3 = HYST11
HYSTSEL3 = HYST12
HYSTSEL3 = HYST13
HYSTSEL3 = HYST14
HYSTSEL3 = HYST15
Hysteresis (VCM = 1.25 V,
BIASPROG2 = 0x10, FULL-
BIAS2 = 1)
VACMPHYST
-1.75
10
0
1.75
26
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
18
32
44
55
65
77
86
0
21
46
27
63
32
80
38
100
121
148
4
43
47
-4
-27
-47
-64
-78
-93
-113
-135
-18
-32
-43
-54
-64
-74
-85
-10
-18
-27
-32
-37
-42
-47
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EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Comparator delay4
BIASPROG2 = 1, FULLBIAS2 = 0
tACMPDELAY
—
30
—
μs
BIASPROG2 = 0x10, FULLBIAS2
= 0
—
3.7
35
—
—
—
35
μs
BIASPROG2 = 0x20, FULLBIAS2
= 1
—
ns
BIASPROG2 =0x10, FULLBIAS2
= 1
Offset voltage
VACMPOFFSET
-35
mV
Reference Voltage
VACMPREF
Internal 1.25 V reference
Internal 2.5 V reference
1
2
1.25
2.5
inf
1.47
2.8
—
V
V
CSRESSEL5 = 0
CSRESSEL5 = 1
CSRESSEL5 = 2
CSRESSEL5 = 3
CSRESSEL5 = 4
CSRESSEL5 = 5
CSRESSEL5 = 6
CSRESSEL5 = 7
Capacitive Sense Internal
Resistance
RCSRES
—
kΩ
—
—
—
—
—
—
—
15
27
—
—
—
—
—
—
—
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
39
51
102
164
239
Note:
1. ACMPVDD is a supply chosen by the setting in ACMPn_CTRL_PWRSEL and may be IOVDD, AVDD or DVDD
2. In ACMPn_CTRL register
3. In ACMPn_HYSTERESIS register
4. ±100 mV differential drive
5. In ACMPn_INPUTSEL register
The total ACMP current is the sum of the contributions from the ACMP and its internal voltage reference as given as:
IACMPTOTAL = IACMP + IACMPREF
IACMPREF is zero if an external voltage reference is used.
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EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Electrical Specifications
4.1.17 I2C
I2C Standard-mode (Sm)
Table 4.29. I2C Standard-mode (Sm)1
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SCL clock frequency2
SCL clock low time
SCL clock high time
SDA set-up time
fSCL
0
—
100
kHz
tLOW
4.7
4
—
—
—
—
—
—
—
μs
μs
ns
ns
μs
tHIGH
tSU,DAT
tHD,DAT
250
100
4.7
—
SDA hold time3
3450
—
Repeated START condition tSU,STA
set-up time
(Repeated) START condition tHD,STA
hold time
4
—
—
μs
STOP condition set-up time tSU,STO
4
—
—
—
—
μs
μs
Bus free time between a
tBUF
4.7
STOP and START condition
Note:
1. For CLHR set to 0 in the I2Cn_CTRL register
2. For the minimum HFPERCLK frequency required in Standard-mode, refer to the I2C chapter in the reference manual
3. The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW
)
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EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Electrical Specifications
I2C Fast-mode (Fm)
Parameter
Table 4.30. I2C Fast-mode (Fm)1
Symbol
Test Condition
Min
Typ
Max
Unit
SCL clock frequency2
SCL clock low time
SCL clock high time
SDA set-up time
fSCL
0
—
400
kHz
tLOW
1.3
0.6
—
—
—
—
—
—
—
μs
μs
ns
ns
μs
tHIGH
tSU,DAT
tHD,DAT
100
100
0.6
—
SDA hold time3
900
—
Repeated START condition tSU,STA
set-up time
(Repeated) START condition tHD,STA
hold time
0.6
—
—
μs
STOP condition set-up time tSU,STO
0.6
1.3
—
—
—
—
μs
μs
Bus free time between a
tBUF
STOP and START condition
Note:
1. For CLHR set to 1 in the I2Cn_CTRL register
2. For the minimum HFPERCLK frequency required in Fast-mode, refer to the I2C chapter in the reference manual
3. The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW
)
I2C Fast-mode Plus (Fm+)
Table 4.31. I2C Fast-mode Plus (Fm+)1
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SCL clock frequency2
SCL clock low time
SCL clock high time
SDA set-up time
fSCL
0
—
1000
kHz
tLOW
0.5
0.26
50
—
—
—
—
—
—
—
—
—
—
μs
μs
ns
ns
μs
tHIGH
tSU,DAT
tHD,DAT
SDA hold time
100
0.26
Repeated START condition tSU,STA
set-up time
(Repeated) START condition tHD,STA
hold time
0.26
—
—
μs
STOP condition set-up time tSU,STO
0.26
0.5
—
—
—
—
μs
μs
Bus free time between a
tBUF
STOP and START condition
Note:
1. For CLHR set to 0 or 1 in the I2Cn_CTRL register
2. For the minimum HFPERCLK frequency required in Fast-mode Plus, refer to the I2C chapter in the reference manual
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EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Electrical Specifications
4.1.18 USART SPI
SPI Master Timing
Table 4.32. SPI Master Timing
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SCLK period 1 2
tSCLK
2 *
tHFPERCLK
—
—
ns
CS to MOSI 1 2
tCS_MO
tSCLK_MO
tSU_MI
0
3
—
—
8
ns
ns
SCLK to MOSI 1 2
MISO setup time 1 2
20
IOVDD = 1.62 V
IOVDD = 3.0 V
56
37
6
—
—
—
—
—
—
ns
ns
ns
MISO hold time 1 2
tH_MI
Note:
1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0)
2. Measurement done with 8 pF output loading at 10% and 90% of VDD (figure shows 50% of VDD
)
tCS_MO
CS
tSCKL_MO
SCLK
CLKPOL = 0
tSCLK
SCLK
CLKPOL = 1
MOSI
MISO
tSU_MI
tH_MI
Figure 4.1. SPI Master Timing Diagram
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EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Electrical Specifications
SPI Slave Timing
Table 4.33. SPI Slave Timing
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SCKL period 1 2
tSCLK_sl
2 *
tHFPERCLK
—
—
ns
SCLK high period1 2
SCLK low period 1 2
tSCLK_hi
3 *
tHFPERCLK
—
—
—
—
ns
ns
tSCLK_lo
3 *
tHFPERCLK
CS active to MISO 1 2
CS disable to MISO 1 2
MOSI setup time 1 2
MOSI hold time 1 2
tCS_ACT_MI
tCS_DIS_MI
tSU_MO
4
4
4
—
—
—
—
50
50
—
—
ns
ns
ns
ns
tH_MO
3 + 2 *
tHFPERCLK
SCLK to MISO 1 2
tSCLK_MI
16 +
tHFPERCLK
—
66 + 2 *
tHFPERCLK
ns
Note:
1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0)
2. Measurement done with 8 pF output loading at 10% and 90% of VDD (figure shows 50% of VDD
)
tCS_ACT_MI
CS
tCS_DIS_MI
SCLK
CLKPOL = 0
tSCLK_HI
tSCLK_LO
SCLK
tSU_MO
CLKPOL = 1
tSCLK
tH_MO
MOSI
MISO
tSCLK_MI
Figure 4.2. SPI Slave Timing Diagram
4.2 Typical Performance Curves
Typical performance curves indicate typical characterized performance under the stated conditions.
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EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Electrical Specifications
4.2.1 Supply Current
Figure 4.3. EM0 Active Mode Typical Supply Current
Figure 4.4. EM1 Sleep Mode Typical Supply Current
Typical supply current for EM2, EM3 and EM4H using standard software libraries from Silicon Laboratories.
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EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Electrical Specifications
Figure 4.5. EM2, EM3, EM4H and EM4S Typical Supply Current
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EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Electrical Specifications
4.2.2 DC-DC Converter
Default test conditions: CCM mode, LDCDC = 4.7 μH, CDCDC = 1.0 μF, VDCDC_I = 3.3 V, VDCDC_O = 1.8 V, FDCDC_LN = 7 MHz
Figure 4.6. DC-DC Converter Typical Performance Characteristics
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EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Electrical Specifications
Load Step Response in LN (CCM) mode
(Heavy Drive)
LN (CCM) and LP mode transition (load: 5mA)
DVDD
DVDD
60mV/div
offset:1.8V
50mV/div
offset:1.8V
100mA
ILOAD
1mA
VSW
2V/div
offset:1.8V
10μs/div
100μs/div
Figure 4.7. DC-DC Converter Transition Waveforms
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EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Electrical Specifications
4.2.3 Internal Oscillators
Figure 4.8. HFRCO and AUXHFRCO Typical Performance at 38 MHz
Figure 4.9. HFRCO and AUXHFRCO Typical Performance at 32 MHz
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EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Electrical Specifications
Figure 4.10. HFRCO and AUXHFRCO Typical Performance at 26 MHz
Figure 4.11. HFRCO and AUXHFRCO Typical Performance at 19 MHz
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EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Electrical Specifications
Figure 4.12. HFRCO and AUXHFRCO Typical Performance at 16 MHz
Figure 4.13. HFRCO and AUXHFRCO Typical Performance at 13 MHz
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EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Electrical Specifications
Figure 4.14. HFRCO and AUXHFRCO Typical Performance at 7 MHz
Figure 4.15. HFRCO and AUXHFRCO Typical Performance at 4 MHz
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EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Electrical Specifications
Figure 4.16. HFRCO and AUXHFRCO Typical Performance at 2 MHz
Figure 4.17. HFRCO and AUXHFRCO Typical Performance at 1 MHz
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EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Electrical Specifications
Figure 4.18. LFRCO Typical Performance at 32.768 kHz
Figure 4.19. ULFRCO Typical Performance at 1 kHz
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EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Electrical Specifications
4.2.4 2.4 GHz Radio
Figure 4.20. 2.4 GHz RF Transmitter Output Power
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EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Electrical Specifications
Figure 4.21. 2.4 GHz RF Receiver Sensitivity
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EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Typical Connection Diagrams
5. Typical Connection Diagrams
5.1 Power
Typical power supply connections for direct supply, without using the internal DC-DC converter, are shown in the following figure.
VDD
Main
Supply
+
–
VREGVDD
AVDD
IOVDD
VREGSW
HFXTAL_N
HFXTAL_P
LFXTAL_N
LFXTAL_P
VREGVSS
DVDD
DECOUPLE
RFVDD
PAVDD
Figure 5.1. EFR32BG1 Typical Application Circuit: Direct Supply Configuration without DC-DC converter
Typical power supply circuits using the internal DC-DC converter are shown below. The MCU operates from the DC-DC converter sup-
ply. For low RF transmit power applications less than 13dBm, the RF PA may be supplied by the DC-DC converter. For OPNs support-
ing high power RF transmission, the RF PA must be directly supplied by VDD for RF transmit power greater than 13 dBm.
VDD
Main
Supply
+
–
VREGVDD
AVDD
IOVDD
VDCDC
VREGSW
HFXTAL_N
HFXTAL_P
LFXTAL_N
LFXTAL_P
VREGVSS
DVDD
DECOUPLE
RFVDD
PAVDD
Figure 5.2. EFR32BG1 Typical Application Circuit: Configuration with DC-DC converter (PAVDD from VDCDC)
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EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Typical Connection Diagrams
VDD
Main
Supply
+
–
VREGVDD
AVDD
IOVDD
VDCDC
VREGSW
HFXTAL_N
HFXTAL_P
LFXTAL_N
LFXTAL_P
VREGVSS
DVDD
DECOUPLE
RFVDD
PAVDD
Figure 5.3. EFR32BG1 Typical Application Circuit: Configuration with DC-DC converter (PAVDD from VDD)
5.2 RF Matching Networks
Typical RF matching network circuit diagrams are shown in Figure 5.4 Typical 2.4 GHz RF impedance-matching network circuits on
page 65 for applications in the 2.4GHz band. Application-specific component values can be found in the EFR32 Reference Manual.
For low RF transmit power applications less than 13dBm, the two-element match is recommended. For OPNs supporting high power
RF transmission, the four-element match is recommended for high RF transmit power (> 13dBm).
4-Element Match for 2.4GHz Band
2-Element Match for 2.4GHz Band
PAVDD
PAVDD
PAVDD
PAVDD
2G4RF_IOP
2G4RF_ION
L0
L0
L1
2G4RF_IOP
2G4RF_ION
50Ω
50Ω
C0
C0
C1
Figure 5.4. Typical 2.4 GHz RF impedance-matching network circuits
5.3 Other Connections
Other components or connections may be required to meet the system-level requirements. Application Note AN0002: "Hardware De-
sign Considerations" contains detailed information on these connections. Application Notes can be accessed on the Silicon Labs web-
site (www.silabs.com/32bit-appnotes).
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EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Pin Definitions
6. Pin Definitions
6.1 EFR32BG1 CSP43 2.4 GHz Definition
Figure 6.1. EFR32BG1 CSP43 2.4 GHz Pinout
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Preliminary Rev. 1.1 | 66
EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Pin Definitions
Table 6.1. CSP43 2.4 GHz Device Pinout
CSP Pin# and Name
Pin Alternate Functionality / Description
Timers Communication Radio
Pin
Pin Name
#
Analog
Other
A1
A2
A3
A4
VREGSW
VREGVDD
DECOUPLE
IOVDD
DCDC regulator switching node
Voltage regulator VDD input
Decouple output for on-chip voltage regulator. An external decoupling capacitor is required at this pin.
Digital IO power supply.
US0_TX #24
TIM0_CC0 #24
TIM0_CC1 #23
TIM0_CC2 #22
TIM0_CDTI0 #21
TIM0_CDTI1 #20
TIM0_CDTI2 #19
TIM1_CC0 #24
US0_RX #23
US0_CLK #22
US0_CS #21
US0_CTS #20
US0_RTS #19
US1_TX #24
US1_RX #23
US1_CLK #22
US1_CS #21
US1_CTS #20
US1_RTS #19
LEU0_TX #24
LEU0_RX #23
I2C0_SDA #24
I2C0_SCL #23
FRC_DCLK #24
FRC_DOUT #23
FRC_DFRAME #22
MODEM_DCLK #24
MODEM_DIN #23
MODEM_DOUT #22
PRS_CH0 #0
PRS_CH1 #7
PRS_CH2 #6
PRS_CH3 #5
ACMP0_O #24
ACMP1_O #24
BUSAX
BUSBY
A6
PF0
TIM1_CC1 #23
TIM1_CC2 #22
TIM1_CC3 #21 LE-
TIM0_OUT0 #24
LETIM0_OUT1 #23
PCNT0_S0IN #24
PCNT0_S1IN #23
MODEM_ANT0 #21 DBG_SWCLKTCK
MODEM_ANT1 #20
#0
US0_TX #25
US0_RX #24
US0_CLK #23
US0_CS #22
US0_CTS #21
US0_RTS #20
US1_TX #25
US1_RX #24
US1_CLK #23
US1_CS #22
US1_CTS #21
US1_RTS #20
LEU0_TX #25
LEU0_RX #24
I2C0_SDA #25
I2C0_SCL #24
TIM0_CC0 #25
TIM0_CC1 #24
TIM0_CC2 #23
TIM0_CDTI0 #22
TIM0_CDTI1 #21
TIM0_CDTI2 #20
TIM1_CC0 #25
FRC_DCLK #25
FRC_DOUT #24
FRC_DFRAME #23
MODEM_DCLK #25
MODEM_DIN #24
MODEM_DOUT #23
PRS_CH0 #1
PRS_CH1 #0
PRS_CH2 #7
PRS_CH3 #6
ACMP0_O #25
ACMP1_O #25
BUSAY
BUSBX
A7
PF1
TIM1_CC1 #24
TIM1_CC2 #23
TIM1_CC3 #22 LE-
TIM0_OUT0 #25
LETIM0_OUT1 #24
PCNT0_S0IN #25
PCNT0_S1IN #24
MODEM_ANT0 #22 DBG_SWDIOTMS
MODEM_ANT1 #21
#0
B1
VREGVSS
Voltage regulator VSS
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EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Pin Definitions
CSP Pin# and Name
Pin Alternate Functionality / Description
Timers Communication Radio
Pin
Pin Name
#
Analog
Other
US0_TX #10
US0_RX #9
US0_CLK #8
US0_CS #7
TIM0_CC0 #10
TIM0_CC1 #9
TIM0_CC2 #8
TIM0_CDTI0 #7
TIM0_CDTI1 #6
TIM0_CDTI2 #5
TIM1_CC0 #10
TIM1_CC1 #9
US0_CTS #6
US0_RTS #5
US1_TX #10
US1_RX #9
US1_CLK #8
US1_CS #7
US1_CTS #6
US1_RTS #5
LEU0_TX #10
LEU0_RX #9
I2C0_SDA #10
I2C0_SCL #9
FRC_DCLK #10
FRC_DOUT #9
CMU_CLK0 #1
PRS_CH6 #10
PRS_CH7 #9
PRS_CH8 #8
PRS_CH9 #7
ACMP0_O #10
ACMP1_O #10
LFXTAL_P
BUSCY
FRC_DFRAME #8
MODEM_DCLK #10
MODEM_DIN #9
MODEM_DOUT #8
MODEM_ANT0 #7
MODEM_ANT1 #6
B2
B3
B4
PB15
DVDD
PC6
TIM1_CC2 #8
BUSDX
TIM1_CC3 #7 LE-
TIM0_OUT0 #10
LETIM0_OUT1 #9
PCNT0_S0IN #10
PCNT0_S1IN #9
Digital power supply.
US0_TX #11
US0_RX #10
US0_CLK #9
US0_CS #8
US0_CTS #7
US0_RTS #6
US1_TX #11
US1_RX #10
US1_CLK #9
US1_CS #8
US1_CTS #7
US1_RTS #6
LEU0_TX #11
LEU0_RX #10
I2C0_SDA #11
I2C0_SCL #10
TIM0_CC0 #11
TIM0_CC1 #10
TIM0_CC2 #9
TIM0_CDTI0 #8
TIM0_CDTI1 #7
TIM0_CDTI2 #6
TIM1_CC0 #11
TIM1_CC1 #10
TIM1_CC2 #9
TIM1_CC3 #8 LE-
TIM0_OUT0 #11
LETIM0_OUT1 #10
PCNT0_S0IN #11
PCNT0_S1IN #10
FRC_DCLK #11
FRC_DOUT #10
CMU_CLK0 #2
PRS_CH0 #8
PRS_CH9 #11
PRS_CH10 #0
PRS_CH11 #5
ACMP0_O #11
ACMP1_O #11
FRC_DFRAME #9
MODEM_DCLK #11
MODEM_DIN #10
MODEM_DOUT #9
MODEM_ANT0 #8
MODEM_ANT1 #7
BUSAX
BUSBY
US0_TX #14
US0_RX #13
US0_CLK #12
US0_CS #11
US0_CTS #10
US0_RTS #9
US1_TX #14
US1_RX #13
US1_CLK #12
US1_CS #11
US1_CTS #10
US1_RTS #9
LEU0_TX #14
LEU0_RX #13
I2C0_SDA #14
I2C0_SCL #13
TIM0_CC0 #14
TIM0_CC1 #13
TIM0_CC2 #12
TIM0_CDTI0 #11
TIM0_CDTI1 #10
TIM0_CDTI2 #9
TIM1_CC0 #14
FRC_DCLK #14
FRC_DOUT #13
PRS_CH0 #11
PRS_CH9 #14
PRS_CH10 #3
PRS_CH11 #2
ACMP0_O #14
ACMP1_O #14
FRC_DFRAME #12
MODEM_DCLK #14
MODEM_DIN #13
MODEM_DOUT #12
MODEM_ANT0 #11
MODEM_ANT1 #10
BUSAY
BUSBX
B5
PC9
TIM1_CC1 #13
TIM1_CC2 #12
TIM1_CC3 #11 LE-
TIM0_OUT0 #14
LETIM0_OUT1 #13
PCNT0_S0IN #14
PCNT0_S1IN #13
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EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Pin Definitions
CSP Pin# and Name
Pin Alternate Functionality / Description
Timers Communication Radio
Pin
Pin Name
#
Analog
Other
US0_TX #26
US0_RX #25
US0_CLK #24
US0_CS #23
US0_CTS #22
US0_RTS #21
US1_TX #26
US1_RX #25
US1_CLK #24
US1_CS #23
US1_CTS #22
US1_RTS #21
LEU0_TX #26
LEU0_RX #25
I2C0_SDA #26
I2C0_SCL #25
TIM0_CC0 #26
TIM0_CC1 #25
TIM0_CC2 #24
TIM0_CDTI0 #23
TIM0_CDTI1 #22
TIM0_CDTI2 #21
TIM1_CC0 #26
CMU_CLK0 #6
PRS_CH0 #2
PRS_CH1 #1
PRS_CH2 #0
PRS_CH3 #7
ACMP0_O #26
ACMP1_O #26
DBG_TDO #0
DBG_SWO #0
GPIO_EM4WU0
FRC_DCLK #26
FRC_DOUT #25
FRC_DFRAME #24
MODEM_DCLK #26
MODEM_DIN #25
MODEM_DOUT #24
MODEM_ANT0 #23
MODEM_ANT1 #22
BUSAX
BUSBY
B6
PF2
TIM1_CC1 #25
TIM1_CC2 #24
TIM1_CC3 #23 LE-
TIM0_OUT0 #26
LETIM0_OUT1 #25
PCNT0_S0IN #26
PCNT0_S1IN #25
US0_TX #27
US0_RX #26
US0_CLK #25
US0_CS #24
US0_CTS #23
US0_RTS #22
US1_TX #27
US1_RX #26
US1_CLK #25
US1_CS #24
US1_CTS #23
US1_RTS #22
LEU0_TX #27
LEU0_RX #26
I2C0_SDA #27
I2C0_SCL #26
TIM0_CC0 #27
TIM0_CC1 #26
TIM0_CC2 #25
TIM0_CDTI0 #24
TIM0_CDTI1 #23
TIM0_CDTI2 #22
TIM1_CC0 #27
FRC_DCLK #27
FRC_DOUT #26
CMU_CLK1 #6
PRS_CH0 #3
PRS_CH1 #2
PRS_CH2 #1
PRS_CH3 #0
ACMP0_O #27
ACMP1_O #27
DBG_TDI #0
FRC_DFRAME #25
MODEM_DCLK #27
MODEM_DIN #26
MODEM_DOUT #25
MODEM_ANT0 #24
MODEM_ANT1 #23
BUSAY
BUSBX
B7
C1
C2
PF3
AVDD
PB14
TIM1_CC1 #26
TIM1_CC2 #25
TIM1_CC3 #24 LE-
TIM0_OUT0 #27
LETIM0_OUT1 #26
PCNT0_S0IN #27
PCNT0_S1IN #26
Analog power supply.
US0_TX #9
US0_RX #8
US0_CLK #7
US0_CS #6
US0_CTS #5
US0_RTS #4
US1_TX #9
US1_RX #8
US1_CLK #7
US1_CS #6
US1_CTS #5
US1_RTS #4
LEU0_TX #9
LEU0_RX #8
I2C0_SDA #9
I2C0_SCL #8
TIM0_CC0 #9
TIM0_CC1 #8
TIM0_CC2 #7
TIM0_CDTI0 #6
TIM0_CDTI1 #5
TIM0_CDTI2 #4
TIM1_CC0 #9
FRC_DCLK #9
FRC_DOUT #8
CMU_CLK1 #1
PRS_CH6 #9
PRS_CH7 #8
PRS_CH8 #7
PRS_CH9 #6
ACMP0_O #9
ACMP1_O #9
LFXTAL_N
BUSCX
FRC_DFRAME #7
MODEM_DCLK #9
MODEM_DIN #8
MODEM_DOUT #7
MODEM_ANT0 #6
MODEM_ANT1 #5
TIM1_CC1 #8
TIM1_CC2 #7
BUSDY
TIM1_CC3 #6 LE-
TIM0_OUT0 #9 LE-
TIM0_OUT1 #8
PCNT0_S0IN #9
PCNT0_S1IN #8
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EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Pin Definitions
CSP Pin# and Name
Pin Alternate Functionality / Description
Timers Communication Radio
Pin
Pin Name
#
Analog
Other
US0_TX #8
US0_RX #7
US0_CLK #6
US0_CS #5
US0_CTS #4
US0_RTS #3
US1_TX #8
US1_RX #7
US1_CLK #6
US1_CS #5
US1_CTS #4
US1_RTS #3
LEU0_TX #8
LEU0_RX #7
I2C0_SDA #8
I2C0_SCL #7
TIM0_CC0 #8
TIM0_CC1 #7
TIM0_CC2 #6
TIM0_CDTI0 #5
TIM0_CDTI1 #4
TIM0_CDTI2 #3
TIM1_CC0 #8
FRC_DCLK #8
FRC_DOUT #7
PRS_CH6 #8
PRS_CH7 #7
PRS_CH8 #6
PRS_CH9 #5
ACMP0_O #8
ACMP1_O #8
DBG_SWO #1
GPIO_EM4WU9
FRC_DFRAME #6
MODEM_DCLK #8
MODEM_DIN #7
MODEM_DOUT #6
MODEM_ANT0 #5
MODEM_ANT1 #4
BUSCY
BUSDX
C3
C4
C5
PB13
PC7
PC8
TIM1_CC1 #7
TIM1_CC2 #6
TIM1_CC3 #5 LE-
TIM0_OUT0 #8 LE-
TIM0_OUT1 #7
PCNT0_S0IN #8
PCNT0_S1IN #7
US0_TX #12
US0_RX #11
US0_CLK #10
US0_CS #9
US0_CTS #8
US0_RTS #7
US1_TX #12
US1_RX #11
US1_CLK #10
US1_CS #9
US1_CTS #8
US1_RTS #7
LEU0_TX #12
LEU0_RX #11
I2C0_SDA #12
I2C0_SCL #11
TIM0_CC0 #12
TIM0_CC1 #11
TIM0_CC2 #10
TIM0_CDTI0 #9
TIM0_CDTI1 #8
TIM0_CDTI2 #7
TIM1_CC0 #12
TIM1_CC1 #11
TIM1_CC2 #10
TIM1_CC3 #9 LE-
TIM0_OUT0 #12
LETIM0_OUT1 #11
PCNT0_S0IN #12
PCNT0_S1IN #11
FRC_DCLK #12
FRC_DOUT #11
CMU_CLK1 #2
PRS_CH0 #9
PRS_CH9 #12
PRS_CH10 #1
PRS_CH11 #0
ACMP0_O #12
ACMP1_O #12
FRC_DFRAME #10
MODEM_DCLK #12
MODEM_DIN #11
MODEM_DOUT #10
MODEM_ANT0 #9
MODEM_ANT1 #8
BUSAY
BUSBX
US0_TX #13
US0_RX #12
US0_CLK #11
US0_CS #10
US0_CTS #9
US0_RTS #8
US1_TX #13
US1_RX #12
US1_CLK #11
US1_CS #10
US1_CTS #9
US1_RTS #8
LEU0_TX #13
LEU0_RX #12
I2C0_SDA #13
I2C0_SCL #12
TIM0_CC0 #13
TIM0_CC1 #12
TIM0_CC2 #11
TIM0_CDTI0 #10
TIM0_CDTI1 #9
TIM0_CDTI2 #8
TIM1_CC0 #13
TIM1_CC1 #12
TIM1_CC2 #11
TIM1_CC3 #10 LE-
TIM0_OUT0 #13
LETIM0_OUT1 #12
PCNT0_S0IN #13
PCNT0_S1IN #12
FRC_DCLK #13
FRC_DOUT #12
PRS_CH0 #10
PRS_CH9 #13
PRS_CH10 #2
PRS_CH11 #1
ACMP0_O #13
ACMP1_O #13
FRC_DFRAME #11
MODEM_DCLK #13
MODEM_DIN #12
MODEM_DOUT #11
MODEM_ANT0 #10
MODEM_ANT1 #9
BUSAX
BUSBY
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EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Pin Definitions
CSP Pin# and Name
Pin Alternate Functionality / Description
Timers Communication Radio
Pin
Pin Name
#
Analog
Other
US0_TX #28
US0_RX #27
US0_CLK #26
US0_CS #25
US0_CTS #24
US0_RTS #23
US1_TX #28
US1_RX #27
US1_CLK #26
US1_CS #25
US1_CTS #24
US1_RTS #23
LEU0_TX #28
LEU0_RX #27
I2C0_SDA #28
I2C0_SCL #27
TIM0_CC0 #28
TIM0_CC1 #27
TIM0_CC2 #26
TIM0_CDTI0 #25
TIM0_CDTI1 #24
TIM0_CDTI2 #23
TIM1_CC0 #28
FRC_DCLK #28
FRC_DOUT #27
PRS_CH0 #4
PRS_CH1 #3
PRS_CH2 #2
PRS_CH3 #1
ACMP0_O #28
ACMP1_O #28
FRC_DFRAME #26
MODEM_DCLK #28
MODEM_DIN #27
MODEM_DOUT #26
MODEM_ANT0 #25
MODEM_ANT1 #24
BUSAX
BUSBY
C6
C7
D1
PF4
TIM1_CC1 #27
TIM1_CC2 #26
TIM1_CC3 #25 LE-
TIM0_OUT0 #28
LETIM0_OUT1 #27
PCNT0_S0IN #28
PCNT0_S1IN #27
US0_TX #29
US0_RX #28
US0_CLK #27
US0_CS #26
US0_CTS #25
US0_RTS #24
US1_TX #29
US1_RX #28
US1_CLK #27
US1_CS #26
US1_CTS #25
US1_RTS #24
LEU0_TX #29
LEU0_RX #28
I2C0_SDA #29
I2C0_SCL #28
TIM0_CC0 #29
TIM0_CC1 #28
TIM0_CC2 #27
TIM0_CDTI0 #26
TIM0_CDTI1 #25
TIM0_CDTI2 #24
TIM1_CC0 #29
FRC_DCLK #29
FRC_DOUT #28
PRS_CH0 #5
PRS_CH1 #4
PRS_CH2 #3
PRS_CH3 #2
ACMP0_O #29
ACMP1_O #29
FRC_DFRAME #27
MODEM_DCLK #29
MODEM_DIN #28
MODEM_DOUT #27
MODEM_ANT0 #26
MODEM_ANT1 #25
BUSAY
BUSBX
PF5
TIM1_CC1 #28
TIM1_CC2 #27
TIM1_CC3 #26 LE-
TIM0_OUT0 #29
LETIM0_OUT1 #28
PCNT0_S0IN #29
PCNT0_S1IN #28
US0_TX #7
US0_RX #6
US0_CLK #5
US0_CS #4
US0_CTS #3
US0_RTS #2
US1_TX #7
US1_RX #6
US1_CLK #5
US1_CS #4
US1_CTS #3
US1_RTS #2
LEU0_TX #7
LEU0_RX #6
I2C0_SDA #7
I2C0_SCL #6
TIM0_CC0 #7
TIM0_CC1 #6
TIM0_CC2 #5
TIM0_CDTI0 #4
TIM0_CDTI1 #3
TIM0_CDTI2 #2
TIM1_CC0 #7
FRC_DCLK #7
FRC_DOUT #6
PRS_CH6 #7
PRS_CH7 #6
PRS_CH8 #5
PRS_CH9 #4
ACMP0_O #7
ACMP1_O #7
FRC_DFRAME #5
MODEM_DCLK #7
MODEM_DIN #6
MODEM_DOUT #5
MODEM_ANT0 #4
MODEM_ANT1 #3
BUSCX
BUSDY
PB12
TIM1_CC1 #6
TIM1_CC2 #5
TIM1_CC3 #4 LE-
TIM0_OUT0 #7 LE-
TIM0_OUT1 #6
PCNT0_S0IN #7
PCNT0_S1IN #6
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EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Pin Definitions
CSP Pin# and Name
Pin Alternate Functionality / Description
Timers Communication Radio
Pin
Pin Name
#
Analog
Other
US0_TX #6
US0_RX #5
US0_CLK #4
US0_CS #3
US0_CTS #2
US0_RTS #1
US1_TX #6
US1_RX #5
US1_CLK #4
US1_CS #3
US1_CTS #2
US1_RTS #1
LEU0_TX #6
LEU0_RX #5
I2C0_SDA #6
I2C0_SCL #5
TIM0_CC0 #6
TIM0_CC1 #5
TIM0_CC2 #4
TIM0_CDTI0 #3
TIM0_CDTI1 #2
TIM0_CDTI2 #1
TIM1_CC0 #6
FRC_DCLK #6
FRC_DOUT #5
PRS_CH6 #6
PRS_CH7 #5
PRS_CH8 #4
PRS_CH9 #3
ACMP0_O #6
ACMP1_O #6
FRC_DFRAME #4
MODEM_DCLK #6
MODEM_DIN #5
MODEM_DOUT #4
MODEM_ANT0 #3
MODEM_ANT1 #2
BUSCY
BUSDX
D2
PB11
TIM1_CC1 #5
TIM1_CC2 #4
TIM1_CC3 #3 LE-
TIM0_OUT0 #6 LE-
TIM0_OUT1 #5
PCNT0_S0IN #6
PCNT0_S1IN #5
US0_TX #1
US0_RX #0
TIM0_CC0 #1
TIM0_CC1 #0
US0_CLK #31
US0_CS #30
US0_CTS #29
US0_RTS #28
US1_TX #1
TIM0_CC2 #31
TIM0_CDTI0 #30
TIM0_CDTI1 #29
TIM0_CDTI2 #28
TIM1_CC0 #1
FRC_DCLK #1
FRC_DOUT #0
FRC_DFRAME #31
MODEM_DCLK #1
MODEM_DIN #0
MODEM_DOUT #31
MODEM_ANT0 #30
MODEM_ANT1 #29
CMU_CLK0 #0
PRS_CH6 #1
PRS_CH7 #0
PRS_CH8 #10
PRS_CH9 #9
ACMP0_O #1
ACMP1_O #1
ADC0_EXTP
BUSCY
US1_RX #0
D3
D4
D5
PA1
TIM1_CC1 #0
US1_CLK #31
US1_CS #30
US1_CTS #29
US1_RTS #28
LEU0_TX #1
LEU0_RX #0
I2C0_SDA #1
I2C0_SCL #0
TIM1_CC2 #31
TIM1_CC3 #30 LE-
TIM0_OUT0 #1 LE-
TIM0_OUT1 #0
PCNT0_S0IN #1
PCNT0_S1IN #0
BUSDX
VSS
Ground
US0_TX #15
US0_RX #14
US0_CLK #13
US0_CS #12
US0_CTS #11
US0_RTS #10
US1_TX #15
US1_RX #14
US1_CLK #13
US1_CS #12
US1_CTS #11
US1_RTS #10
LEU0_TX #15
LEU0_RX #14
I2C0_SDA #15
I2C0_SCL #14
TIM0_CC0 #15
TIM0_CC1 #14
TIM0_CC2 #13
TIM0_CDTI0 #12
TIM0_CDTI1 #11
TIM0_CDTI2 #10
TIM1_CC0 #15
FRC_DCLK #15
FRC_DOUT #14
CMU_CLK1 #3
PRS_CH0 #12
PRS_CH9 #15
PRS_CH10 #4
PRS_CH11 #3
ACMP0_O #15
ACMP1_O #15
GPIO_EM4WU12
FRC_DFRAME #13
MODEM_DCLK #15
MODEM_DIN #14
MODEM_DOUT #13
MODEM_ANT0 #12
MODEM_ANT1 #11
BUSAX
BUSBY
PC10
TIM1_CC1 #14
TIM1_CC2 #13
TIM1_CC3 #12 LE-
TIM0_OUT0 #15
LETIM0_OUT1 #14
PCNT0_S0IN #15
PCNT0_S1IN #14
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Preliminary Rev. 1.1 | 72
EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Pin Definitions
CSP Pin# and Name
Pin Alternate Functionality / Description
Timers Communication Radio
Pin
Pin Name
#
Analog
Other
US0_TX #16
US0_RX #15
US0_CLK #14
US0_CS #13
US0_CTS #12
US0_RTS #11
US1_TX #16
US1_RX #15
US1_CLK #14
US1_CS #13
US1_CTS #12
US1_RTS #11
LEU0_TX #16
LEU0_RX #15
I2C0_SDA #16
I2C0_SCL #15
TIM0_CC0 #16
TIM0_CC1 #15
TIM0_CC2 #14
TIM0_CDTI0 #13
TIM0_CDTI1 #12
TIM0_CDTI2 #11
TIM1_CC0 #16
FRC_DCLK #16
FRC_DOUT #15
CMU_CLK0 #3
PRS_CH0 #13
PRS_CH9 #16
PRS_CH10 #5
PRS_CH11 #4
ACMP0_O #16
ACMP1_O #16
DBG_SWO #3
FRC_DFRAME #14
MODEM_DCLK #16
MODEM_DIN #15
MODEM_DOUT #14
MODEM_ANT0 #13
MODEM_ANT1 #12
BUSAY
BUSBX
D6
D7
E1
PC11
RFVDD
PA0
TIM1_CC1 #15
TIM1_CC2 #14
TIM1_CC3 #13 LE-
TIM0_OUT0 #16
LETIM0_OUT1 #15
PCNT0_S0IN #16
PCNT0_S1IN #15
Radio power supply
US0_TX #0
US0_RX #31
US0_CLK #30
US0_CS #29
US0_CTS #28
US0_RTS #27
US1_TX #0
US1_RX #31
US1_CLK #30
US1_CS #29
US1_CTS #28
US1_RTS #27
LEU0_TX #0
LEU0_RX #31
I2C0_SDA #0
I2C0_SCL #31
TIM0_CC0 #0
TIM0_CC1 #31
TIM0_CC2 #30
TIM0_CDTI0 #29
TIM0_CDTI1 #28
TIM0_CDTI2 #27
TIM1_CC0 #0
TIM1_CC1 #31
TIM1_CC2 #30
TIM1_CC3 #29 LE-
TIM0_OUT0 #0 LE-
TIM0_OUT1 #31
PCNT0_S0IN #0
PCNT0_S1IN #31
FRC_DCLK #0
FRC_DOUT #31
CMU_CLK1 #0
PRS_CH6 #0
PRS_CH7 #10
PRS_CH8 #9
PRS_CH9 #8
ACMP0_O #0
ACMP1_O #0
ADC0_EXTN
BUSCX
FRC_DFRAME #30
MODEM_DCLK #0
MODEM_DIN #31
MODEM_DOUT #30
MODEM_ANT0 #29
MODEM_ANT1 #28
BUSDY
E2
E3
E4
E5
E6
E7
F1
F2
F3
F4
F5
F6
F7
G1
VSS
VSS
Ground
Ground
Ground
Ground
Ground
VSS
VSS
VSS
HFXTAL_N
VSS
High Frequency Crystal input pin.
Ground
2G4RF_IOP
2G4RF_ION
PAVSS
RFVSS
VSS
2.4 GHz Differential RF input/output, positive path.
2.4 GHz Differential RF input/output, negative path. This pin should be externally grounded.
Power Amplifier (PA) voltage regulator VSS
Radio Ground
Ground
HFXTAL_P
PAVDD
High Frequency Crystal output pin.
Power Amplifier (PA) voltage regulator VDD input
Reset input, active low.To apply an external reset source to this pin, it is required to only drive this pin low
during reset, and let the internal pull-up ensure that reset is released.
G7
RESETn
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EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Pin Definitions
6.1.1 EFR32BG1 CSP43 2.4 GHz GPIO Overview
The GPIO pins are organized as 16-bit ports indicated by letters (A, B, C...), and the individual pins on each port are indicated by a
number from 15 down to 0.
Table 6.2. CSP43 2.4 GHz GPIO Pinout
Port
Pin
15
Pin
14
Pin
13
Pin
12
Pin
11
Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0
10
Port A
Port B
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PA1 PA0
PB13 PB12 PB11
(5V) (5V) (5V)
PB15 PB14
-
-
-
-
PC11 PC10 PC9 PC8 PC7 PC6
(5V) (5V) (5V) (5V) (5V) (5V)
Port C
Port F
-
-
-
-
-
-
-
-
-
-
-
-
PF5 PF4 PF3 PF2 PF1 PF0
(5V) (5V) (5V) (5V) (5V) (5V)
-
-
-
-
-
-
Note:
1. GPIO with 5V tolerance are indicated by (5V).
2. The pins PB13, PB12, and PB11 will not be 5V tolerant on all future devices. In order to preserve upgrade options with full hard-
ware compatibility, do not use these pins with 5V domains.
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EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Pin Definitions
6.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. The following table shows the name of the alter-
nate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.
Table 6.3. Alternate functionality overview
Alternate
LOCATION
Functionality
0 - 3
4 - 7
8 - 11
12 - 15
16 - 19
20 - 23
24 - 27
28 - 31
Description
0: PA0
1: PA1
8: PB13
9: PB14
10: PB15 14: PC9
12: PC7
13: PC8
16: PC11
24: PF0
25: PF1
26: PF2
27: PF3
28: PF4
29: PF5
Analog comparator
ACMP0, digital out-
put.
ACMP0_O
6: PB11
7: PB12
11: PC6
15: PC10
0: PA0
1: PA1
8: PB13
9: PB14
10: PB15 14: PC9
11: PC6 15: PC10
12: PC7
13: PC8
16: PC11
24: PF0
25: PF1
26: PF2
27: PF3
28: PF4
29: PF5
Analog comparator
ACMP1, digital out-
put.
ACMP1_O
6: PB11
7: PB12
0: PA0
0: PA1
Analog to digital
converter ADC0 ex-
ternal reference in-
put negative pin
ADC0_EXTN
ADC0_EXTP
CMU_CLK0
CMU_CLK1
Analog to digital
converter ADC0 ex-
ternal reference in-
put positive pin
0: PA1
Clock Management
Unit, clock output
number 0.
1: PB15
2: PC6
3: PC11
6: PF2
6: PF3
0: PA0
Clock Management
Unit, clock output
number 1.
1: PB14
2: PC7
3: PC10
Debug-interface
Serial Wire clock
input and JTAG
Test Clock.
0: PF0
DBG_SWCLKTCK
Note that this func-
tion is enabled to
the pin out of reset,
and has a built-in
pull down.
Debug-interface
Serial Wire data in-
put / output and
JTAG Test Mode
Select.
0: PF1
DBG_SWDIOTMS
Note that this func-
tion is enabled to
the pin out of reset,
and has a built-in
pull up.
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EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0 - 3
4 - 7
8 - 11
12 - 15
16 - 19
20 - 23
24 - 27
28 - 31
Description
Debug-interface
Serial Wire viewer
Output.
0: PF2
Note that this func-
tion is not enabled
after reset, and
must be enabled by
software to be
used.
1: PB13
DBG_SWO
3: PC11
Debug-interface
JTAG Test Data In.
0: PF3
Note that this func-
tion is enabled to
pin out of reset,
and has a built-in
pull up.
DBG_TDI
Debug-interface
JTAG Test Data
Out.
0: PF2
DBG_TDO
Note that this func-
tion is enabled to
pin out of reset.
0: PA0
1: PA1
8: PB13
9: PB14
10: PB15 14: PC9
12: PC7
13: PC8
16: PC11
24: PF0
25: PF1
26: PF2
27: PF3
28: PF4
29: PF5
Frame Controller,
Data Sniffer Clock.
FRC_DCLK
6: PB11
7: PB12
11: PC6
15: PC10
4: PB11
5: PB12
6: PB13
7: PB14
8: PB15
9: PC6
10: PC7
11: PC8
12: PC9
13: PC10
14: PC11
24: PF2
25: PF3
26: PF4
27: PF5
Frame Controller,
Data Sniffer Frame
active
FRC_DFRAME
FRC_DOUT
22: PF0
23: PF1
30: PA0
31: PA1
0: PA1
0: PF2
0: PB13
0: PC10
0: PA1
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
14: PC10
15: PC11
24: PF1
25: PF2
26: PF3
27: PF4
28: PF5
Frame Controller,
Data Sniffer Out-
put.
5: PB11
6: PB12
7: PB13
23: PF0
31: PA0
Pin can be used to
wake the system
up from EM4
GPIO_EM4WU0
GPIO_EM4WU9
GPIO_EM4WU12
I2C0_SCL
Pin can be used to
wake the system
up from EM4
Pin can be used to
wake the system
up from EM4
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
14: PC10
15: PC11
24: PF1
25: PF2
26: PF3
27: PF4
28: PF5
31: PA0
5: PB11
6: PB12
7: PB13
I2C0 Serial Clock
Line input / output.
23: PF0
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EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0 - 3
4 - 7
8 - 11
12 - 15
16 - 19
20 - 23
24 - 27
28 - 31
Description
0: PA0
1: PA1
8: PB13
9: PB14
10: PB15 14: PC9
12: PC7
13: PC8
16: PC11
24: PF0
25: PF1
26: PF2
27: PF3
28: PF4
29: PF5
I2C0 Serial Data in-
put / output.
I2C0_SDA
6: PB11
7: PB12
11: PC6
15: PC10
0: PA0
1: PA1
8: PB13
9: PB14
10: PB15 14: PC9
12: PC7
13: PC8
16: PC11
24: PF0
25: PF1
26: PF2
27: PF3
28: PF4
29: PF5
Low Energy Timer
LETIM0, output
channel 0.
LETIM0_OUT0
LETIM0_OUT1
LEU0_RX
6: PB11
7: PB12
11: PC6
15: PC10
0: PA1
0: PA1
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
14: PC10
15: PC11
24: PF1
25: PF2
26: PF3
27: PF4
28: PF5
Low Energy Timer
LETIM0, output
channel 1.
5: PB11
6: PB12
7: PB13
23: PF0
23: PF0
31: PA0
28: PF5
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
14: PC10
15: PC11
24: PF1
25: PF2
26: PF3
27: PF4
5: PB11
6: PB12
7: PB13
LEUART0 Receive
input.
31: PA0
LEUART0 Transmit
output. Also used
as receive input in
half duplex commu-
nication.
0: PA0
1: PA1
8: PB13
9: PB14
10: PB15 14: PC9
12: PC7
13: PC8
16: PC11
24: PF0
25: PF1
26: PF2
27: PF3
28: PF4
29: PF5
LEU0_TX
6: PB11
7: PB12
11: PC6
15: PC10
Low Frequency
Crystal (typically
32.768 kHz) nega-
tive pin. Also used
as an optional ex-
ternal clock input
pin.
0: PB14
0: PB15
LFXTAL_N
Low Frequency
Crystal (typically
32.768 kHz) posi-
tive pin.
LFXTAL_P
4: PB12
5: PB13
6: PB14
7: PB15
8: PC6
9: PC7
10: PC8
11: PC9
12: PC10
13: PC11
24: PF3
25: PF4
26: PF5
MODEM antenna
control output 0,
used for antenna
diversity.
21: PF0
22: PF1
23: PF2
29: PA0
30: PA1
MODEM_ANT0
MODEM_ANT1
MODEM_DCLK
MODEM_DIN
MODEM_DOUT
3: PB11
4: PB13
5: PB14
6: PB15
7: PC6
8: PC7
9: PC8
10: PC9
11: PC10
12: PC11
20: PF0
21: PF1
22: PF2
23: PF3
24: PF4
25: PF5
28: PA0
29: PA1
MODEM antenna
control output 1,
used for antenna
diversity.
2: PB11
3: PB12
0: PA0
1: PA1
8: PB13
9: PB14
10: PB15 14: PC9
12: PC7
13: PC8
16: PC11
24: PF0
25: PF1
26: PF2
27: PF3
28: PF4
29: PF5
MODEM data clock
out.
6: PB11
7: PB12
11: PC6
15: PC10
0: PA1
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
14: PC10
15: PC11
24: PF1
25: PF2
26: PF3
27: PF4
28: PF5
31: PA0
5: PB11
6: PB12
7: PB13
MODEM data in.
MODEM data out.
23: PF0
4: PB11
5: PB12
6: PB13
7: PB14
8: PB15
9: PC6
10: PC7
11: PC8
12: PC9
13: PC10
14: PC11
24: PF2
25: PF3
26: PF4
27: PF5
22: PF0
23: PF1
30: PA0
31: PA1
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Preliminary Rev. 1.1 | 77
EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0 - 3
4 - 7
8 - 11
12 - 15
16 - 19
20 - 23
24 - 27
28 - 31
Description
0: PA0
1: PA1
8: PB13
9: PB14
10: PB15 14: PC9
12: PC7
13: PC8
16: PC11
24: PF0
25: PF1
26: PF2
27: PF3
28: PF4
29: PF5
Pulse Counter
PCNT0 input num-
ber 0.
PCNT0_S0IN
PCNT0_S1IN
PRS_CH0
PRS_CH1
PRS_CH2
PRS_CH3
PRS_CH6
PRS_CH7
PRS_CH8
PRS_CH9
PRS_CH10
PRS_CH11
TIM0_CC0
6: PB11
7: PB12
11: PC6
15: PC10
0: PA1
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
14: PC10
15: PC11
24: PF1
25: PF2
26: PF3
27: PF4
28: PF5
31: PA0
Pulse Counter
PCNT0 input num-
ber 1.
5: PB11
6: PB12
7: PB13
23: PF0
0: PF0
1: PF1
2: PF2
3: PF3
4: PF4
5: PF5
8: PC6
9: PC7
10: PC8
11: PC9
12: PC10
13: PC11
Peripheral Reflex
System PRS, chan-
nel 0.
0: PF1
1: PF2
2: PF3
3: PF4
4: PF5
7: PF0
Peripheral Reflex
System PRS, chan-
nel 1.
0: PF2
1: PF3
2: PF4
3: PF5
Peripheral Reflex
System PRS, chan-
nel 2.
6: PF0
7: PF1
0: PF3
1: PF4
2: PF5
Peripheral Reflex
System PRS, chan-
nel 3.
5: PF0
6: PF1
7: PF2
0: PA0
1: PA1
8: PB13
9: PB14
10: PB15
Peripheral Reflex
System PRS, chan-
nel 6.
6: PB11
7: PB12
0: PA1
8: PB14
9: PB15
10: PA0
Peripheral Reflex
System PRS, chan-
nel 7.
5: PB11
6: PB12
7: PB13
4: PB11
5: PB12
6: PB13
7: PB14
8: PB15
9: PA0
10: PA1
Peripheral Reflex
System PRS, chan-
nel 8.
4: PB12
5: PB13
6: PB14
7: PB15
8: PA0
9: PA1
12: PC7
13: PC8
14: PC9
15: PC10
16: PC11
Peripheral Reflex
System PRS, chan-
nel 9.
3: PB11
11: PC6
0: PC6
1: PC7
2: PC8
3: PC9
4: PC10
5: PC11
Peripheral Reflex
System PRS, chan-
nel 10.
0: PC7
1: PC8
2: PC9
3: PC10
4: PC11
5: PC6
Peripheral Reflex
System PRS, chan-
nel 11.
0: PA0
1: PA1
8: PB13
9: PB14
10: PB15 14: PC9
11: PC6 15: PC10
12: PC7
13: PC8
16: PC11
24: PF0
25: PF1
26: PF2
27: PF3
28: PF4
29: PF5
Timer 0 Capture
Compare input /
output channel 0.
6: PB11
7: PB12
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Preliminary Rev. 1.1 | 78
EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0 - 3
4 - 7
8 - 11
12 - 15
16 - 19
20 - 23
24 - 27
28 - 31
Description
0: PA1
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
14: PC10
15: PC11
24: PF1
25: PF2
26: PF3
27: PF4
28: PF5
Timer 0 Capture
Compare input /
output channel 1.
5: PB11
6: PB12
7: PB13
TIM0_CC1
TIM0_CC2
TIM0_CDTI0
TIM0_CDTI1
TIM0_CDTI2
TIM1_CC0
TIM1_CC1
TIM1_CC2
TIM1_CC3
US0_CLK
US0_CS
23: PF0
31: PA0
4: PB11
5: PB12
6: PB13
7: PB14
8: PB15
9: PC6
10: PC7
11: PC8
12: PC9
13: PC10
14: PC11
24: PF2
25: PF3
26: PF4
27: PF5
Timer 0 Capture
Compare input /
output channel 2.
22: PF0
23: PF1
30: PA0
31: PA1
4: PB12
5: PB13
6: PB14
7: PB15
8: PC6
9: PC7
10: PC8
11: PC9
12: PC10
13: PC11
24: PF3
25: PF4
26: PF5
Timer 0 Compli-
mentary Dead Time
Insertion channel 0.
21: PF0
22: PF1
23: PF2
29: PA0
30: PA1
3: PB11
4: PB13
5: PB14
6: PB15
7: PC6
8: PC7
9: PC8
10: PC9
11: PC10
12: PC11
20: PF0
21: PF1
22: PF2
23: PF3
24: PF4
25: PF5
28: PA0
29: PA1
Timer 0 Compli-
mentary Dead Time
Insertion channel 1.
2: PB11
3: PB12
4: PB14
5: PB15
6: PC6
7: PC7
8: PC8
9: PC9
10: PC10
11: PC11
20: PF1
21: PF2
22: PF3
23: PF4
24: PF5
27: PA0
28: PA1
Timer 0 Compli-
mentary Dead Time
Insertion channel 2.
1: PB11
2: PB12
3: PB13
19: PF0
0: PA0
1: PA1
8: PB13
9: PB14
10: PB15 14: PC9
12: PC7
13: PC8
16: PC11
24: PF0
25: PF1
26: PF2
27: PF3
28: PF4
29: PF5
Timer 1 Capture
Compare input /
output channel 0.
6: PB11
7: PB12
11: PC6
15: PC10
0: PA1
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
14: PC10
15: PC11
24: PF1
25: PF2
26: PF3
27: PF4
28: PF5
31: PA0
Timer 1 Capture
Compare input /
output channel 1.
5: PB11
6: PB12
7: PB13
23: PF0
4: PB11
5: PB12
6: PB13
7: PB14
8: PB15
9: PC6
10: PC7
11: PC8
12: PC9
13: PC10
14: PC11
24: PF2
25: PF3
26: PF4
27: PF5
Timer 1 Capture
Compare input /
output channel 2.
22: PF0
23: PF1
30: PA0
31: PA1
4: PB12
5: PB13
6: PB14
7: PB15
8: PC6
9: PC7
10: PC8
11: PC9
12: PC10
13: PC11
24: PF3
25: PF4
26: PF5
Timer 1 Capture
Compare input /
output channel 3.
21: PF0
22: PF1
23: PF2
29: PA0
30: PA1
3: PB11
4: PB11
5: PB12
6: PB13
7: PB14
8: PB15
9: PC6
10: PC7
11: PC8
12: PC9
13: PC10
14: PC11
24: PF2
25: PF3
26: PF4
27: PF5
USART0 clock in-
put / output.
22: PF0
23: PF1
30: PA0
31: PA1
4: PB12
5: PB13
6: PB14
7: PB15
8: PC6
9: PC7
10: PC8
11: PC9
12: PC10
13: PC11
24: PF3
25: PF4
26: PF5
21: PF0
22: PF1
23: PF2
29: PA0
30: PA1
USART0 chip se-
lect input / output.
3: PB11
4: PB13
5: PB14
6: PB15
7: PC6
8: PC7
9: PC8
10: PC9
11: PC10
12: PC11
20: PF0
21: PF1
22: PF2
23: PF3
24: PF4
25: PF5
28: PA0
29: PA1
USART0 Clear To
Send hardware
flow control input.
US0_CTS
US0_RTS
2: PB11
3: PB12
4: PB14
5: PB15
6: PC6
7: PC7
8: PC8
9: PC9
10: PC10
11: PC11
20: PF1
21: PF2
22: PF3
23: PF4
24: PF5
27: PA0
28: PA1
USART0 Request
To Send hardware
flow control output.
1: PB11
2: PB12
3: PB13
19: PF0
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Preliminary Rev. 1.1 | 79
EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0 - 3
4 - 7
8 - 11
12 - 15
16 - 19
20 - 23
24 - 27
28 - 31
28: PF5
31: PA0
Description
USART0 Asynchro-
nous Receive.
0: PA1
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
14: PC10
15: PC11
24: PF1
25: PF2
26: PF3
27: PF4
5: PB11
6: PB12
7: PB13
USART0 Synchro-
nous mode Master
Input / Slave Out-
put (MISO).
US0_RX
23: PF0
USART0 Asynchro-
nous Transmit. Al-
so used as receive
input in half duplex
communication.
0: PA0
1: PA1
8: PB13
9: PB14
10: PB15 14: PC9
12: PC7
13: PC8
16: PC11
24: PF0
25: PF1
26: PF2
27: PF3
28: PF4
29: PF5
US0_TX
6: PB11
7: PB12
USART0 Synchro-
nous mode Master
Output / Slave In-
put (MOSI).
11: PC6
15: PC10
4: PB11
5: PB12
6: PB13
7: PB14
8: PB15
9: PC6
10: PC7
11: PC8
12: PC9
13: PC10
14: PC11
24: PF2
25: PF3
26: PF4
27: PF5
USART1 clock in-
put / output.
US1_CLK
US1_CS
22: PF0
23: PF1
30: PA0
31: PA1
4: PB12
5: PB13
6: PB14
7: PB15
8: PC6
9: PC7
10: PC8
11: PC9
12: PC10
13: PC11
24: PF3
25: PF4
26: PF5
21: PF0
22: PF1
23: PF2
29: PA0
30: PA1
USART1 chip se-
lect input / output.
3: PB11
4: PB13
5: PB14
6: PB15
7: PC6
8: PC7
9: PC8
10: PC9
11: PC10
12: PC11
20: PF0
21: PF1
22: PF2
23: PF3
24: PF4
25: PF5
28: PA0
29: PA1
USART1 Clear To
Send hardware
flow control input.
US1_CTS
US1_RTS
2: PB11
3: PB12
4: PB14
5: PB15
6: PC6
7: PC7
8: PC8
9: PC9
10: PC10
11: PC11
20: PF1
21: PF2
22: PF3
23: PF4
24: PF5
27: PA0
28: PA1
USART1 Request
To Send hardware
flow control output.
1: PB11
2: PB12
3: PB13
19: PF0
USART1 Asynchro-
nous Receive.
0: PA1
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
14: PC10
15: PC11
24: PF1
25: PF2
26: PF3
27: PF4
28: PF5
31: PA0
5: PB11
6: PB12
7: PB13
USART1 Synchro-
nous mode Master
Input / Slave Out-
put (MISO).
US1_RX
23: PF0
USART1 Asynchro-
nous Transmit. Al-
so used as receive
input in half duplex
communication.
0: PA0
1: PA1
8: PB13
9: PB14
10: PB15 14: PC9
11: PC6 15: PC10
12: PC7
13: PC8
16: PC11
24: PF0
25: PF1
26: PF2
27: PF3
28: PF4
29: PF5
US1_TX
6: PB11
7: PB12
USART1 Synchro-
nous mode Master
Output / Slave In-
put (MOSI).
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Preliminary Rev. 1.1 | 80
EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Pin Definitions
6.3 Analog Port (APORT) Client Maps
The Analog Port (APORT) is an infrastructure used to connect chip pins with on-chip analog clients such as analog comparators, ADCs,
DACs, etc. The APORT consists of a set of shared buses, switches, and control logic needed to configurably implement the signal rout-
ing. A complete description of APORT functionality can be found in the Reference Manual.
Client maps for each analog circuit using the APORT are shown in the following tables. The maps are organized by bus, and show the
peripheral's port connection, the shared bus, and the connection from specific bus channel numbers to GPIO pins.
In general, enumerations for the pin selection field in an analog peripheral's register can be determined by finding the desired pin con-
nection in the table and then combining the value in the Port column (APORT__), and the channel identifier (CH__). For example, if pin
PF7 is available on port APORT2X as CH23, the register field enumeration to connect to PF7 would be APORT2XCH23. The shared
bus used by this connection is indicated in the Bus column.
Table 6.4. ACMP0 Bus and Pin Mapping
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Preliminary Rev. 1.1 | 81
EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Pin Definitions
Table 6.5. ACMP1 Bus and Pin Mapping
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Preliminary Rev. 1.1 | 82
EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Pin Definitions
Table 6.6. ADC0 Bus and Pin Mapping
Table 6.7. IDAC0 Bus and Pin Mapping
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Preliminary Rev. 1.1 | 83
EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
CSP Package Specifications
7. CSP Package Specifications
7.1 CSP Package Dimensions
Figure 7.1. CSP Package Drawing
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Preliminary Rev. 1.1 | 84
EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
CSP Package Specifications
Table 7.1. CSP Package Dimensions
Dimension
Min
0.480
0.175
0.270
0.022
3.260
3.108
0.240
—
Typ
0.510
0.190
0.295
0.025
3.295
3.143
0.270
2.400
2.400
0.447
0.302
0.448
0.441
0.400
0.10
Max
0.540
0.205
0.320
0.028
3.320
3.168
0.300
—
A
A1
c
c1
D
E
b
D1
E1
D2
E2
D3
E3
e
—
—
—
—
—
—
—
—
—
—
—
—
aaa
bbb
ccc
ddd
eee
Note:
0.10
0.03
0.15
0.05
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. Primary datum “C” and seating plane are defined by the spherical crowns of the solder balls.
4. Dimension “b” is measured at the maximum solder bump diameter, parallel to primary datum “C”.
5. Minimum bump pitch 0.4mm.
6. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
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Preliminary Rev. 1.1 | 85
EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
CSP Package Specifications
7.2 CSP PCB Land Pattern
Figure 7.2. CSP PCB Land Pattern Drawing
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Preliminary Rev. 1.1 | 86
EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
CSP Package Specifications
Table 7.2. CSP PCB Land Pattern Dimensions
Dimension
Typ
0.20
2.40
2.40
0.40
0.40
X
C1
C2
E1
E2
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
6. The stencil thickness should be 0.075 mm (3 mils).
7. A stencil of square aperture (0.22 x 0.22 mm) is recommended.
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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Preliminary Rev. 1.1 | 87
EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
CSP Package Specifications
7.3 CSP Package Marking
PPPPPPPPP
TTTTTT
YYWW #
Figure 7.3. CSP Package Marking
The package marking consists of:
• PPPPPPPPP – The part number designation.
1. Family Code (B | M | F)
2. G (Gecko)
3. Series (1, 2,...)
4. Performance Grade (P | B | V)
5. Feature Code (1 to 7)
6. TRX Code (3 = TXRX | 2= RX | 1 = TX)
7. Band (2 = 2.4 GHz)
8. Flash (G = 256K | F = 128K | E = 64K | D = 32K)
9. Temperature Grade (G = -40 to 85)
• TTTTTT – A trace or manufacturing code. The first letter is the device revision.
• YY – The last 2 digits of the assembly year.
• WW – The 2-digit workweek when the device was assembled.
• # – Bootloader revision number.
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Preliminary Rev. 1.1 | 88
EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet
Revision History
8. Revision History
8.1 Revision 1.1
2016-Oct-26
• Ordering Information: Removed Encryption column. All products in family include full encryption capabilites. Previously EFR32BG1V
devices listed as "AES only".
• System Overview Sections: Minor wording and typographical error fixes.
• Electrical Characteristics: Minor wording and typographical error fixes.
• "Current Consumption 3.3V with DC-DC" table in Electrical Characteristics: Typical values for EM2 and EM3 current updated with
correct values from silicon characterization.
• Pinout tables: APORT channel details removed from "Analog" column. This information is now found in the APORT client map sec-
tions.
• Updated APORT client map sections.
8.2 Revision 0.98
2016-July-6
• All OPNs changed to rev C0. Note the following:
• All OPNs ending in -B0 are Engineering Samples based on an older revision of silicon and are being removed from the OPN
table. These older revisions should be used for evaluation only and will not be supported for production.
• OPNs ending in -C0 are the Current Revision of Silicon and are intended for production.
• Updated OPN table to new format.
• Updated OPN decoder figure to include extended family options.
• Added supported modulation formats and protocols to feature list for P-grade devices.
• Electrical specification tables updated with latest characterization data and production test limits.
• Added graphs in typical performance curves for supply current, oscillator frequency and RF.
• Updated DC-DC graphs in typical performance section.
• Typical connection diagram formatting updated.
• Pinout diagram formatting updated.
• Removed BOOT_TX and BOOT_RX alternate functions from pin function tables.
• Updated package marking diagram with latest inclusive version.
8.3 Revision 0.3
2015-11-2
Initial release of CSP package document.
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Preliminary Rev. 1.1 | 89
Table of Contents
1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.2 Radio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.2.1 Antenna Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.2.2 Fractional-N Frequency Synthesizer. . . . . . . . . . . . . . . . . . . . . . 4
3.2.3 Receiver Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2.4 Transmitter Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2.5 Wake on Radio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2.6 RFSENSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2.7 Flexible Frame Handling. . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2.8 Packet and State Trace . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2.9 Data Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2.10 Radio Controller (RAC). . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2.11 Random Number Generator . . . . . . . . . . . . . . . . . . . . . . . . 5
3.3 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.3.1 Energy Management Unit (EMU) . . . . . . . . . . . . . . . . . . . . . . . 6
3.3.2 DC-DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.4 General Purpose Input/Output (GPIO). . . . . . . . . . . . . . . . . . . . . . 6
3.5 Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.5.1 Clock Management Unit (CMU) . . . . . . . . . . . . . . . . . . . . . . . 6
3.5.2 Internal and External Oscillators . . . . . . . . . . . . . . . . . . . . . . . 6
3.6 Counters/Timers and PWM . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.6.1 Timer/Counter (TIMER) . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.6.2 Real Time Counter and Calendar (RTCC) . . . . . . . . . . . . . . . . . . . . 7
3.6.3 Low Energy Timer (LETIMER). . . . . . . . . . . . . . . . . . . . . . . . 7
3.6.4 Ultra Low Power Wake-up Timer (CRYOTIMER) . . . . . . . . . . . . . . . . . 7
3.6.5 Pulse Counter (PCNT) . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.6.6 Watchdog Timer (WDOG) . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.7 Communications and Other Digital Peripherals . . . . . . . . . . . . . . . . . . . 7
3.7.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) . . . . . . . . . . 7
3.7.2 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART) . . . . . . . . . . 8
2
3.7.3 Inter-Integrated Circuit Interface (I C) . . . . . . . . . . . . . . . . . . . . . 8
3.7.4 Peripheral Reflex System (PRS) . . . . . . . . . . . . . . . . . . . . . . . 8
3.8 Security Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.8.1 GPCRC (General Purpose Cyclic Redundancy Check) . . . . . . . . . . . . . . . 8
3.8.2 Crypto Accelerator (CRYPTO). . . . . . . . . . . . . . . . . . . . . . . . 8
3.9 Analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.9.1 Analog Port (APORT) . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.9.2 Analog Comparator (ACMP) . . . . . . . . . . . . . . . . . . . . . . . . 8
3.9.3 Analog to Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . 9
3.9.4 Digital to Analog Current Converter (IDAC) . . . . . . . . . . . . . . . . . . . 9
Table of Contents 90
3.10 Reset Management Unit (RMU) . . . . . . . . . . . . . . . . . . . . . . . 9
3.11 Core and Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.11.1 Processor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.11.2 Memory System Controller (MSC) . . . . . . . . . . . . . . . . . . . . . . 9
3.11.3 Linked Direct Memory Access Controller (LDMA) . . . . . . . . . . . . . . . . . 9
3.12 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.13 Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . .11
4. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .12
4.1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . .13
4.1.2 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . .14
4.1.2.1 General Operating Conditions . . . . . . . . . . . . . . . . . . . . . . .14
4.1.3 DC-DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
4.1.4 Current Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.1.4.1 Current Consumption 3.3 V without DC-DC Converter . . . . . . . . . . . . . . .17
4.1.4.2 Current Consumption 3.3 V using DC-DC Converter . . . . . . . . . . . . . . .18
4.1.4.3 Current Consumption 1.85 V without DC-DC Converter . . . . . . . . . . . . . .20
4.1.4.4 Current Consumption Using Radio . . . . . . . . . . . . . . . . . . . . .21
4.1.5 Wake up times . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4.1.6 Brown Out Detector . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4.1.7 Frequency Synthesizer Characteristics . . . . . . . . . . . . . . . . . . . . .23
4.1.8 2.4 GHz RF Transceiver Characteristics . . . . . . . . . . . . . . . . . . . .24
4.1.8.1 RF Transmitter General Characteristics for the 2.4 GHz Band . . . . . . . . . . . .24
4.1.8.2 RF Receiver General Characteristics for the 2.4 GHz Band . . . . . . . . . . . . .25
4.1.8.3 RF Transmitter Characteristics for Bluetooth Smart in the 2.4 GHz Band . . . . . . . . .26
4.1.8.4 RF Receiver Characteristics for Bluetooth Smart in the 2.4 GHz Band. . . . . . . . . .28
4.1.8.5 RF Transmitter Characteristics for 802.15.4 O-QPSK DSSS in the 2.4 GHz Band . . . . . .30
4.1.8.6 RF Receiver Characteristics for 802.15.4 O-QPSK DSSS in the 2.4 GHz Band. . . . . . .33
4.1.9 Modem Features . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
4.1.10 Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
4.1.10.1 LFXO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
4.1.10.2 HFXO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
4.1.10.3 LFRCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
4.1.10.4 HFRCO and AUXHFRCO . . . . . . . . . . . . . . . . . . . . . . . .37
4.1.10.5 ULFRCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
4.1.11 Flash Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . .38
4.1.12 GPIO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
4.1.13 VMON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
4.1.14 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
4.1.15 IDAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
4.1.16 Analog Comparator (ACMP) . . . . . . . . . . . . . . . . . . . . . . . .46
4.1.17 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
4.1.18 USART SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
4.2 Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . .51
4.2.1 Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
4.2.2 DC-DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
4.2.3 Internal Oscillators. . . . . . . . . . . . . . . . . . . . . . . . . . . .56
4.2.4 2.4 GHz Radio . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Table of Contents 91
5. Typical Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . 64
5.1 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
5.2 RF Matching Networks . . . . . . . . . . . . . . . . . . . . . . . . . . .65
5.3 Other Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
6. Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.1 EFR32BG1 CSP43 2.4 GHz Definition . . . . . . . . . . . . . . . . . . . . .66
6.1.1 EFR32BG1 CSP43 2.4 GHz GPIO Overview . . . . . . . . . . . . . . . . . . .74
6.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . . . .75
6.3 Analog Port (APORT) Client Maps . . . . . . . . . . . . . . . . . . . . . . .81
7. CSP Package Specifications . . . . . . . . . . . . . . . . . . . . . . . . 84
7.1 CSP Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . .84
7.2 CSP PCB Land Pattern. . . . . . . . . . . . . . . . . . . . . . . . . . .86
7.3 CSP Package Marking . . . . . . . . . . . . . . . . . . . . . . . . . . .88
8. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
8.1 Revision 1.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
8.2 Revision 0.98 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
8.3 Revision 0.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table of Contents 92
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Disclaimer
Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or
intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical"
parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes
without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included
information. Silicon Labs shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses granted
hereunder to design or fabricate any integrated circuits. The products are not designed or authorized to be used within any Life Support System without the specific written consent of
Silicon Labs. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant personal
injury or death. Silicon Labs products are not designed or authorized for military applications. Silicon Labs products shall under no circumstances be used in weapons of mass
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Silicon Laboratories Inc.® , Silicon Laboratories®, Silicon Labs®, SiLabs® and the Silicon Labs logo®, Bluegiga®, Bluegiga Logo®, Clockbuilder®, CMEMS®, DSPLL®, EFM®, EFM32®,
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