EFR32FG12P232F1024GL125-B [SILICON]
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet;型号: | EFR32FG12P232F1024GL125-B |
厂家: | SILICON |
描述: | EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet |
文件: | 总183页 (文件大小:2766K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
EFR32FG12 Flex Gecko Proprietary
Protocol SoC Family Data Sheet
The Flex Gecko proprietary protocol family of SoCs is part of the
KEY FEATURES
Wireless Gecko portfolio. Flex Gecko SoCs are ideal for enabling
energy-friendly proprietary protocol networking for IoT devices.
• 32-bit ARM® Cortex®-M4 core with 40
MHz maximum operating frequency
The single-die solution provides industry-leading energy efficiency, ultra-fast wakeup
times, a scalable power amplifier, an integrated balun and no-compromise MCU fea-
tures.
• Up to 1 MB of flash and 256 kB of RAM
• Pin-compatible with EFR32FG1 QFN48
devices (exceptions apply for 5V-tolerant
pins)
Flex Gecko applications include:
• 12-channel Peripheral Reflex System,
Low-Energy Sensor Interface & Multi-
channel Capacitive Sense Interface
• Home and Building Automation and Security
• Metering
• Autonomous Hardware Crypto Accelerator
and True Random Number Generator
• Electronic Shelf Labels
• Industrial Automation
• Integrated PA with up to 19 dBm transmit
power for 2.4 GHz and 20 dBm for Sub-
GHz radios
• Commercial and Retail Lighting and Sensing
• Integrated balun for 2.4 GHz
• Robust peripheral set and up to 65 GPIO
Core / Memory
Clock Management
Energy Management
Other
CRYPTO
CRC
High Frequency
Crystal
Oscillator
High Frequency
RC Oscillator
Voltage
Voltage Monitor
Power-On Reset
Regulator
ARM CortexTM M4 processor
Memory
with DSP extensions and FPU
Protection Unit
Auxiliary High
Frequency RC
Oscillator
Low Frequency
RC Oscillator
DC-DC
Converter
True Random
Number Generator
Low Frequency
Crystal
Oscillator
Ultra Low
Frequency RC
Oscillator
Flash Program
RAM Memory
Memory
Debug Interface
with ETM
LDMA
Controller
Brown-Out
Detector
SMU
32-bit bus
Peripheral Reflex System
Radio Transceiver
Serial
I/O Ports
Timers and Triggers
Analog I/F
Interfaces
RFSENSE
Sub GHz
LNA
DEMOD
ADC
I
External
Interrupts
USART
Timer/Counter
Protocol Timer
RF Frontend
Analog
Comparator
IFADC
AGC
PGA
PA
Low Energy
UARTTM
General
Purpose I/O
Low Energy
Timer
Watchdog Timer
Q
IDAC
To Sub GHz
receive I/Q
mixers and PA
Real Time
Counter and
Calendar
RFSENSE
BALUN
Capacitive Sense
I2C
Pin Reset
Pulse Counter
2.4 GHz
LNA
I
Frequency
Synthesizer
MOD
VDAC
RF Frontend
Low Energy
Sensor Interface
Pin Wakeup
Cryotimer
Op-Amp
PA
To 2.4 GHz receive
I/Q mixers and PA
To Sub GHz
and 2.4 GHz PA
Q
Lowest power mode with peripheral operational:
EM0—Active EM1—Sleep
EM2—Deep Sleep
EM3—Stop
EM4—Hibernate
EM4—Shutoff
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Rev. 1.0
Table of Contents
1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.2 Radio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.2.1 Antenna Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.2.2 Fractional-N Frequency Synthesizer. . . . . . . . . . . . . . . . . . . . . . 4
3.2.3 Receiver Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2.4 Transmitter Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2.5 Wake on Radio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2.6 RFSENSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2.7 Flexible Frame Handling. . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2.8 Packet and State Trace . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2.9 Data Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2.10 Radio Controller (RAC). . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2.11 Random Number Generator . . . . . . . . . . . . . . . . . . . . . . . . 5
3.3 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.3.1 Energy Management Unit (EMU) . . . . . . . . . . . . . . . . . . . . . . . 6
3.3.2 DC-DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.3.3 Power Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.4 General Purpose Input/Output (GPIO). . . . . . . . . . . . . . . . . . . . . . 7
3.5 Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.5.1 Clock Management Unit (CMU) . . . . . . . . . . . . . . . . . . . . . . . 7
3.5.2 Internal and External Oscillators . . . . . . . . . . . . . . . . . . . . . . . 7
3.6 Counters/Timers and PWM . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.6.1 Timer/Counter (TIMER) . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.6.2 Wide Timer/Counter (WTIMER) . . . . . . . . . . . . . . . . . . . . . . . 7
3.6.3 Real Time Counter and Calendar (RTCC) . . . . . . . . . . . . . . . . . . . . 7
3.6.4 Low Energy Timer (LETIMER). . . . . . . . . . . . . . . . . . . . . . . . 8
3.6.5 Ultra Low Power Wake-up Timer (CRYOTIMER) . . . . . . . . . . . . . . . . . 8
3.6.6 Pulse Counter (PCNT) . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.6.7 Watchdog Timer (WDOG) . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.7 Communications and Other Digital Peripherals . . . . . . . . . . . . . . . . . . . 8
3.7.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) . . . . . . . . . . 8
3.7.2 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART) . . . . . . . . . . 8
2
3.7.3 Inter-Integrated Circuit Interface (I C) . . . . . . . . . . . . . . . . . . . . . 8
3.7.4 Peripheral Reflex System (PRS) . . . . . . . . . . . . . . . . . . . . . . . 8
3.7.5 Low Energy Sensor Interface (LESENSE). . . . . . . . . . . . . . . . . . . . 9
3.8 Security Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.8.1 GPCRC (General Purpose Cyclic Redundancy Check) . . . . . . . . . . . . . . . 9
3.8.2 Crypto Accelerator (CRYPTO). . . . . . . . . . . . . . . . . . . . . . . . 9
3.8.3 True Random Number Generator (TRNG). . . . . . . . . . . . . . . . . . . . 9
3.8.4 Security Management Unit (SMU) . . . . . . . . . . . . . . . . . . . . . . 9
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3.9 Analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.9.1 Analog Port (APORT) . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.9.2 Analog Comparator (ACMP) . . . . . . . . . . . . . . . . . . . . . . . . 9
3.9.3 Analog to Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . .10
3.9.4 Capacitive Sense (CSEN) . . . . . . . . . . . . . . . . . . . . . . . . .10
3.9.5 Digital to Analog Current Converter (IDAC) . . . . . . . . . . . . . . . . . . .10
3.9.6 Digital to Analog Converter (VDAC) . . . . . . . . . . . . . . . . . . . . . .10
3.9.7 Operational Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.10 Reset Management Unit (RMU) . . . . . . . . . . . . . . . . . . . . . . .10
3.11 Core and Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.11.1 Processor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.11.2 Memory System Controller (MSC) . . . . . . . . . . . . . . . . . . . . . .11
3.11.3 Linked Direct Memory Access Controller (LDMA) . . . . . . . . . . . . . . . . .11
3.12 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.13 Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . .14
4. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .15
4.1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . .16
4.1.2 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.1.2.1 General Operating Conditions . . . . . . . . . . . . . . . . . . . . . . .18
4.1.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.1.4 DC-DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.1.5 Current Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . .22
4.1.5.1 Current Consumption 3.3 V without DC-DC Converter . . . . . . . . . . . . . . .22
4.1.5.2 Current Consumption 3.3 V using DC-DC Converter . . . . . . . . . . . . . . .24
4.1.5.3 Current Consumption 1.8 V without DC-DC Converter . . . . . . . . . . . . . . .26
4.1.5.4 Current Consumption Using Radio 3.3 V with DC-DC . . . . . . . . . . . . . . .28
4.1.6 Wake Up Times . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
4.1.7 Brown Out Detector (BOD) . . . . . . . . . . . . . . . . . . . . . . . . .31
4.1.8 Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . .32
4.1.9 2.4 GHz RF Transceiver Characteristics . . . . . . . . . . . . . . . . . . . .33
4.1.9.1 RF Transmitter General Characteristics for 2.4 GHz Band. . . . . . . . . . . . . .33
4.1.9.2 RF Receiver General Characteristics for 2.4 GHz Band . . . . . . . . . . . . . .34
4.1.9.3 RF Transmitter Characteristics for 1Mbps 2GFSK in the 2.4GHz Band, 1 Mbps Data Rate . . .35
4.1.9.4 RF Receiver Characteristics for 1Mbps 2GFSK in the 2.4GHz Band, 1 Mbps Data Rate. . . .36
4.1.9.5 RF Transmitter Characteristics for 1Mbps 2GFSK in the 2.4GHz Band, 2 Mbps Data Rate . . .37
4.1.9.6 RF Receiver Characteristics for 1Mbps 2GFSK in the 2.4GHz Band, 2 Mbps Data Rate. . . .38
4.1.9.7 RF Transmitter Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band . . . . . .39
4.1.9.8 RF Receiver Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band . . . . . . .41
4.1.10 Sub-GHz RF Transceiver Characteristics . . . . . . . . . . . . . . . . . . .43
4.1.10.1 Sub-GHz RF Transmitter characteristics for 915 MHz Band . . . . . . . . . . . . .44
4.1.10.2 Sub-GHz RF Receiver Characteristics for 915 MHz Band . . . . . . . . . . . . .46
4.1.10.3 Sub-GHz RF Transmitter characteristics for 868 MHz Band . . . . . . . . . . . . .49
4.1.10.4 Sub-GHz RF Receiver Characteristics for 868 MHz Band . . . . . . . . . . . . .51
4.1.10.5 Sub-GHz RF Transmitter characteristics for 490 MHz Band . . . . . . . . . . . . .53
4.1.10.6 Sub-GHz RF Receiver Characteristics for 490 MHz Band . . . . . . . . . . . . .54
4.1.10.7 Sub-GHz RF Transmitter characteristics for 433 MHz Band . . . . . . . . . . . . .56
4.1.10.8 Sub-GHz RF Receiver Characteristics for 433 MHz Band . . . . . . . . . . . . .58
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4.1.10.9 Sub-GHz RF Transmitter characteristics for 315 MHz Band . . . . . . . . . . . . .61
4.1.10.10 Sub-GHz RF Receiver Characteristics for 315 MHz Band . . . . . . . . . . . . .62
4.1.10.11 Sub-GHz RF Transmitter Characteristics for 169 MHz Band . . . . . . . . . . . .64
4.1.10.12 Sub-GHz RF Receiver Characteristics for 169 MHz Band . . . . . . . . . . . . .65
4.1.11 Modem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
4.1.12 Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
4.1.12.1 Low-Frequency Crystal Oscillator (LFXO) . . . . . . . . . . . . . . . . . . .67
4.1.12.2 High-Frequency Crystal Oscillator (HFXO) . . . . . . . . . . . . . . . . . .68
4.1.12.3 Low-Frequency RC Oscillator (LFRCO) . . . . . . . . . . . . . . . . . . .68
4.1.12.4 High-Frequency RC Oscillator (HFRCO) . . . . . . . . . . . . . . . . . . .69
4.1.12.5 Auxiliary High-Frequency RC Oscillator (AUXHFRCO) . . . . . . . . . . . . . .70
4.1.12.6 Ultra-low Frequency RC Oscillator (ULFRCO) . . . . . . . . . . . . . . . . .70
4.1.13 Flash Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . .71
4.1.14 General-Purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . .72
4.1.15 Voltage Monitor (VMON) . . . . . . . . . . . . . . . . . . . . . . . . .74
4.1.16 Analog to Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . .75
4.1.17 Analog Comparator (ACMP) . . . . . . . . . . . . . . . . . . . . . . . .77
4.1.18 Digital to Analog Converter (VDAC) . . . . . . . . . . . . . . . . . . . . .80
4.1.19 Current Digital to Analog Converter (IDAC) . . . . . . . . . . . . . . . . . . .83
4.1.20 Capacitive Sense (CSEN). . . . . . . . . . . . . . . . . . . . . . . . .85
4.1.21 Operational Amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . .87
4.1.22 Pulse Counter (PCNT) . . . . . . . . . . . . . . . . . . . . . . . . . .90
4.1.23 Analog Port (APORT) . . . . . . . . . . . . . . . . . . . . . . . . . .90
4.1.24 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
4.1.24.1 I2C Standard-mode (Sm) . . . . . . . . . . . . . . . . . . . . . . . .91
4.1.24.2 I2C Fast-mode (Fm) . . . . . . . . . . . . . . . . . . . . . . . . . .92
4.1.24.3 I2C Fast-mode Plus (Fm+) . . . . . . . . . . . . . . . . . . . . . . . .93
4.1.25 USART SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
4.2 Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . .95
4.2.1 Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
4.2.2 DC-DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.2.3 2.4 GHz Radio . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
5. Typical Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . .105
5.1 Power
5.2 RF Matching Networks . . . . . . . . . . . . . . . . . . . . . . . . . . 107
5.3 Other Connections . . . . . . . . . . . . . . . . . . . . . . . . . . .108
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1. 05
6. Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
6.1 BGA125 2.4 GHz and Sub-GHz Device Pinout . . . . . . . . . . . . . . . . . . 109
6.2 BGA125 2.4 GHz Device Pinout . . . . . . . . . . . . . . . . . . . . . . . 112
6.3 BGA125 Sub-GHz Device Pinout
. . . . . . . . . . . . . . . . . . . . . .115
. . . . . . . . . . . . . . . . . .118
6.4 QFN48 2.4 GHz and Sub-GHz Device Pinout
6.5 QFN48 2.4 GHz Device Pinout . . . . . . . . . . . . . . . . . . . . . . .120
6.6 QFN48 Sub-GHz Device Pinout . . . . . . . . . . . . . . . . . . . . . . . 122
6.7 GPIO Functionality Table . . . . . . . . . . . . . . . . . . . . . . . . . 124
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6.8 Alternate Functionality Overview
. . . . . . . . . . . . . . . . . . . . . 1.45
6.9 Analog Port (APORT) Client Maps . . . . . . . . . . . . . . . . . . . . . . 158
7. BGA125 Package Specifications . . . . . . . . . . . . . . . . . . . . . . .167
7.1 BGA125 Package Dimensions
7.2 BGA125 PCB Land Pattern
7.3 BGA125 Package Marking
. . . . . . . . . . . . . . . . . . . . . . .167
. . . . . . . . . . . . . . . . . . . . . . . .169
. . . . . . . . . . . . . . . . . . . . . . . 1.71
8. QFN48 Package Specifications. . . . . . . . . . . . . . . . . . . . . . . . 172
8.1 QFN48 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 172
8.2 QFN48 PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . 174
8.3 QFN48 Package Marking . . . . . . . . . . . . . . . . . . . . . . . . . 176
9. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
9.1 Revision 1.0
9.2 Revision 0.6
9.3 Revision 0.5
9.4 Revision 0.2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1. 77
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1. 77
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1. 77
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1. 77
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Rev. 1.0
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Feature List
1. Feature List
The EFR32FG12 highlighted features are listed below.
• Low Power Wireless System-on-Chip.
• Wide selection of MCU peripherals
• 12-bit 1 Msps SAR Analog to Digital Converter (ADC)
• 2×Analog Comparator (ACMP)
High Performance 32-bit 40 MHz ARM Cortex®-M4 with
DSP instruction and floating-point unit for efficient signal
processing
•
• 2×Digital to Analog Converter (VDAC)
• 3×Operational Amplifier (Opamp)
• Embedded Trace Macrocell (ETM) for advanced debugging
• Up to 1024 kB flash program memory
• Digital to Analog Current Converter (IDAC)
• Low-Energy Sensor Interface (LESENSE)
• Multi-channel Capacitive Sense Interface (CSEN)
• Up to 256 kB RAM data memory
• 2.4 GHz and Sub-GHz radio operation
• TX power up to 19 dBm
• Up to 54 pins connected to analog channels (APORT)
shared between analog peripherals
• Low Energy Consumption
• 10.0 mA RX current at 2.4 GHz (1 Mbps GFSK)
• 10.8 mA RX current at 2.4 GHz (250 kbps O-QPSK DSSS)
• 8.5 mA TX current @ 0 dBm output power at 2.4 GHz
• 70 μA/MHz in Active Mode (EM0)
• Up to 65 General Purpose I/O pins with output state reten-
tion and asynchronous interrupts
• 8 Channel DMA Controller
• 12 Channel Peripheral Reflex System (PRS)
• 2×16-bit Timer/Counter
• 1.5 μA EM2 DeepSleep current (16 kB RAM retention and
RTCC running from LFRCO)
• 3 + 4 Compare/Capture/PWM channels
• 2×32-bit Timer/Counter
• Wake on Radio with signal strength detection, preamble
pattern detection, frame detection and timeout
• 3 + 4 Compare/Capture/PWM channels
• 32-bit Real Time Counter and Calendar
• 16-bit Low Energy Timer for waveform generation
• High Receiver Performance
• -95.2 dBm sensitivity @ 1 Mbit/s GFSK
• -91.3 dBm sensitivity @ 2 Mbit/s GFSK
• -120.6 dBm sensitivity at 2.4 kbps GFSK (868 MHz)
• Supported Modulation Formats
• 2-FSK / 4-FSK with fully configurable shaping
• Shaped OQPSK / (G)MSK
• 32-bit Ultra Low Energy Timer/Counter for periodic wake-up
from any Energy Mode
• 3×16-bit Pulse Counter with asynchronous operation
• 2×Watchdog Timer with dedicated RC oscillator
• 4×Universal Synchronous/Asynchronous Receiver/Trans-
mitter (UART/SPI/SmartCard (ISO 7816)/IrDA/I2S)
• Configurable DSSS and FEC
• BPSK / DBPSK TX
Low Energy UART (LEUART™)
2×I2C interface with SMBus support and address recogni-
tion in EM3 Stop
•
•
• OOK / ASK
• Supported Protocols:
• Proprietary Protocols
• Wide Operating Range
• Wireless M-Bus
• 1.8 V to 3.8 V single power supply
• Low Power Wide Area Networks
• Support for Internet Security
• General Purpose CRC
• Integrated DC-DC, down to 1.8 V output with up to 200 mA
load current for system
• -40 °C to 85 °C
• QFN48 7x7 mm Package
• BGA125 7x7 mm Package
• True Random Number Generator
• Hardware Cryptographic Acceleration for AES 128/256,
SHA-1, SHA-2 (SHA-224 and SHA-256) and ECC
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Rev. 1.0 | 1
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Ordering Information
2. Ordering Information
Table 2.1. Ordering Information
Frequency Band
@ Max TX Power
2.4 GHz @ 19 dBm
Flash
(kB)
RAM
(kB)
Ordering Code
Protocol Stack
GPIO
Package
EFR32FG12P433F1024GL125-B
Proprietary
•
1024
256
65
BGA125
• Sub-GHz @ 20 dBm
EFR32FG12P433F1024GM48-B
Proprietary
•
2.4 GHz @ 19 dBm
1024
256
28
QFN48
• Sub-GHz @ 20 dBm
EFR32FG12P432F1024GL125-B
EFR32FG12P432F1024GM48-B
EFR32FG12P431F1024GL125-B
EFR32FG12P431F1024GM48-B
EFR32FG12P232F1024GL125-B
EFR32FG12P232F1024GM48-B
EFR32FG12P231F1024GL125-B
EFR32FG12P231F1024GM48-B
Proprietary
Proprietary
Proprietary
Proprietary
Proprietary
Proprietary
Proprietary
Proprietary
2.4 GHz @ 19 dBm
2.4 GHz @ 19 dBm
Sub-GHz @ 20 dBm
Sub-GHz @ 20 dBm
2.4 GHz @ 19 dBm
2.4 GHz @ 19 dBm
Sub-GHz @ 20 dBm
Sub-GHz @ 20 dBm
1024
1024
1024
1024
1024
1024
1024
1024
256
256
256
256
128
128
128
128
65
31
65
31
65
31
65
31
BGA125
QFN48
BGA125
QFN48
BGA125
QFN48
BGA125
QFN48
EFR32 X G 1 2 P 132 F 1024 G L 125 – A R
Tape and Reel (Optional)
Revision
Pin Count
Package – M (QFN), L (BGA)
Temperature Grade – G (-40 to +85 °C), -I (-40 to +125 °C)
Flash Memory Size in kB
Memory Type (Flash)
Feature Set Code – r2r1r0
r2: Reserved
r1: RF Type – 3 (TRX), 2 (RX), 1 (TX)
r0: Frequency Band – 1 (Sub-GHz), 2 (2.4 GHz), 3 (Dual-Band)
Performance Grade – P (Performance), B (Basic), V (Value)
Device Configuration
Series
Gecko
Family – M (Mighty), B (Blue), F (Flex)
Wireless Gecko 32-bit
Figure 2.1. OPN Decoder
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
System Overview
3. System Overview
3.1 Introduction
The EFR32 product family combines an energy-friendly MCU with a highly integrated radio transceiver. The devices are well suited for
any battery operated application as well as other systems requiring high performance and low energy consumption. This section gives a
short introduction to the full radio and MCU system. The detailed functional description can be found in the EFR32xG12 Wireless
Gecko Reference Manual.
A block diagram of the EFR32FG12 family is shown in Figure 3.1 Detailed EFR32FG12 Block Diagram on page 3. The diagram
shows a superset of features available on the family, which vary by OPN. For more information about specific device features, consult
Ordering Information.
Radio Transceiver
Port I/O Configuration
Digital Peripherals
IOVDD
Sub-GHz RF
SUBGRF_IP
SUBGRF_IN
SUBGRF_OP
SUBGRF_ON
I
DEMOD
IFADC
AGC
LNA
LETIMER
PA
Port A
Drivers
PGA
Q
PAn
TIMER
CRYOTIMER
PCNT
RFSENSE
BALUN
2.4 GHz RF
I
Frequency
LNA
Synthesizer
Port B
Drivers
PBn
PCn
PDn
PFn
2G4RF_IOP
2G4RF_ION
To RF
MOD
PA
Frontend
Circuits
RTC / RTCC
USART
Q
Port
Mapper
Port C
Drivers
LEUART
I2C
Reset
Management
Unit
ARM Cortex-M4 Core
RESETn
Port D
Serial Wire
and ETM
Debug /
Up to 1024 KB ISP Flash
Program Memory
CRYPTO
CRC
Drivers
Debug Signals
(shared w/GPIO)
Brown Out /
Power-On
Reset
A
H
B
A
P
B
Up to 256 KB RAM
Memory Protection Unit
Floating Point Unit
LDMA Controller
Programming
Port F
Drivers
LESENSE
Energy Management
Analog Peripherals
Port I
Drivers
PAVDD
RFVDD
IOVDD
AVDD
PIn
IDAC
Voltage
Monitor
Port J
Drivers
-
+
Watchdog
Timer
PJn
VDAC
DVDD
bypass
Op-Amp
VDD
Internal
Reference
Port K
Drivers
Clock Management
PKn
VREGVDD
VREGSW
DC-DC
Converter
Voltage
Regulator
ULFRCO
AUXHFRCO
LFRCO
12-bit ADC
DECOUPLE
Temp
Sense
LFXTAL_P
LFXTAL_N
HFXTAL_P
HFXTAL_N
LFXO
HFRCO
HFXO
Capacitive
Sense
+
-
Analog Comparator
Figure 3.1. Detailed EFR32FG12 Block Diagram
3.2 Radio
The Flex Gecko family features a radio transceiver supporting proprietary wireless protocols.
3.2.1 Antenna Interface
The 2.4 GHz antenna interface consists of two pins (2G4RF_IOP and 2G4RF_ION) that interface directly to the on-chip BALUN. The
2G4RF_ION pin should be grounded externally.
The external components and power supply connections for the antenna interface typical applications are shown in the RF Matching
Networks section.
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
System Overview
3.2.2 Fractional-N Frequency Synthesizer
The EFR32FG12 contains a high performance, low phase noise, fully integrated fractional-N frequency synthesizer. The synthesizer is
used in receive mode to generate the LO frequency used by the down-conversion mixer. It is also used in transmit mode to directly
generate the modulated RF carrier.
The fractional-N architecture provides excellent phase noise performance combined with frequency resolution better than 100 Hz, with
low energy consumption. The synthesizer has fast frequency settling which allows very short receiver and transmitter wake up times to
optimize system energy consumption.
3.2.3 Receiver Architecture
The EFR32FG12 uses a low-IF receiver architecture, consisting of a Low-Noise Amplifier (LNA) followed by an I/Q down-conversion
mixer, employing a crystal reference. The I/Q signals are further filtered and amplified before being sampled by the IF analog-to-digital
converter (IFADC).
The IF frequency is configurable from 70 kHz to 1.4 MHz. The IF can further be configured for high-side or low-side injection, providing
flexibility with respect to known interferers at the image frequency.
The Automatic Gain Control (AGC) module adjusts the receiver gain to optimize performance and avoid saturation for excellent selec-
tivity and blocking performance. The 2.4 GHz radio is calibrated at production to improve image rejection performance. The sub-GHz
radio can be calibrated on-demand by the user for the desired frequency band.
Demodulation is performed in the digital domain. The demodulator performs configurable decimation and channel filtering to allow re-
ceive bandwidths ranging from 0.1 to 2530 kHz. High carrier frequency and baud rate offsets are tolerated by active estimation and
compensation. Advanced features supporting high quality communication under adverse conditions include forward error correction by
block and convolutional coding as well as Direct Sequence Spread Spectrum (DSSS).
A Received Signal Strength Indicator (RSSI) is available for signal quality metrics, for level-based proximity detection, and for RF chan-
nel access by Collision Avoidance (CA) or Listen Before Talk (LBT) algorithms. An RSSI capture value is associated with each received
frame and the dynamic RSSI measurement can be monitored throughout reception.
3.2.4 Transmitter Architecture
The EFR32FG12 uses a direct-conversion transmitter architecture. For constant envelope modulation formats, the modulator controls
phase and frequency modulation in the frequency synthesizer. Transmit symbols or chips are optionally shaped by a digital shaping
filter. The shaping filter is fully configurable, including the BT product, and can be used to implement Gaussian or Raised Cosine shap-
ing.
Carrier Sense Multiple Access - Collision Avoidance (CSMA-CA) or Listen Before Talk (LBT) algorithms can be automatically timed by
the EFR32FG12. These algorithms are typically defined by regulatory standards to improve inter-operability in a given bandwidth be-
tween devices that otherwise lack synchronized RF channel access.
3.2.5 Wake on Radio
The Wake on Radio feature allows flexible, autonomous RF sensing, qualification, and demodulation without required MCU activity, us-
ing a subsystem of the EFR32FG12 including the Radio Controller (RAC), Peripheral Reflex System (PRS), and Low Energy peripher-
als.
3.2.6 RFSENSE
The RFSENSE module generates a system wakeup interrupt upon detection of wideband RF energy at the antenna interface, providing
true RF wakeup capabilities from low energy modes including EM2, EM3 and EM4.
RFSENSE triggers on a relatively strong RF signal and is available in the lowest energy modes, allowing exceptionally low energy con-
sumption. RFSENSE does not demodulate or otherwise qualify the received signal, but software may respond to the wakeup event by
enabling normal RF reception.
Various strategies for optimizing power consumption and system response time in presence of false alarms may be employed using
available timer peripherals.
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
System Overview
3.2.7 Flexible Frame Handling
EFR32FG12 has an extensive and flexible frame handling support for easy implementation of even complex communication protocols.
The Frame Controller (FRC) supports all low level and timing critical tasks together with the Radio Controller and Modulator/Demodula-
tor:
• Highly adjustable preamble length
• Up to 2 simultaneous synchronization words, each up to 32 bits and providing separate interrupts
• Frame disassembly and address matching (filtering) to accept or reject frames
• Automatic ACK frame assembly and transmission
• Fully flexible CRC generation and verification:
• Multiple CRC values can be embedded in a single frame
• 8, 16, 24 or 32-bit CRC value
• Configurable CRC bit and byte ordering
• Selectable bit-ordering (least significant or most significant bit first)
• Optional data whitening
• Optional Forward Error Correction (FEC), including convolutional encoding / decoding and block encoding / decoding
• Half rate convolutional encoder and decoder with constraint lengths from 2 to 7 and optional puncturing
• Optional symbol interleaving, typically used in combination with FEC
• Symbol coding, such as Manchester or DSSS, or biphase space encoding using FEC hardware
• UART encoding over air, with start and stop bit insertion / removal
• Test mode support, such as modulated or unmodulated carrier output
• Received frame timestamping
3.2.8 Packet and State Trace
The EFR32FG12 Frame Controller has a packet and state trace unit that provides valuable information during the development phase.
It features:
• Non-intrusive trace of transmit data, receive data and state information
• Data observability on a single-pin UART data output, or on a two-pin SPI data output
• Configurable data output bitrate / baudrate
• Multiplexed transmitted data, received data and state / meta information in a single serial data stream
3.2.9 Data Buffering
The EFR32FG12 features an advanced Radio Buffer Controller (BUFC) capable of handling up to 4 buffers of adjustable size from 64
bytes to 4096 bytes. Each buffer can be used for RX, TX or both. The buffer data is located in RAM, enabling zero-copy operations.
3.2.10 Radio Controller (RAC)
The Radio Controller controls the top level state of the radio subsystem in the EFR32FG12. It performs the following tasks:
• Precisely-timed control of enabling and disabling of the receiver and transmitter circuitry
• Run-time calibration of receiver, transmitter and frequency synthesizer
• Detailed frame transmission timing, including optional LBT or CSMA-CA
3.2.11 Random Number Generator
The Frame Controller (FRC) implements a random number generator that uses entropy gathered from noise in the RF receive chain.
The data is suitable for use in cryptographic applications.
Output from the random number generator can be used either directly or as a seed or entropy source for software-based random num-
ber generator algorithms such as Fortuna.
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
System Overview
3.3 Power
The EFR32FG12 has an Energy Management Unit (EMU) and efficient integrated regulators to generate internal supply voltages. Only
a single external supply voltage is required, from which all internal voltages are created. An optional integrated DC-DC buck regulator
can be utilized to further reduce the current consumption. The DC-DC regulator requires one external inductor and one external capaci-
tor.
The EFR32FG12 device family includes support for internal supply voltage scaling, as well as two different power domains groups for
peripherals. These enhancements allow for further supply current reductions and lower overall power consumption.
AVDD and VREGVDD need to be 1.8 V or higher for the MCU to operate across all conditions; however the rest of the system will
operate down to 1.62 V, including the digital supply and I/O. This means that the device is fully compatible with 1.8 V components.
Running from a sufficiently high supply, the device can use the DC-DC to regulate voltage not only for itself, but also for other PCB
components, supplying up to a total of 200 mA.
3.3.1 Energy Management Unit (EMU)
The Energy Management Unit manages transitions of energy modes in the device. Each energy mode defines which peripherals and
features are available and the amount of current the device consumes. The EMU can also be used to turn off the power to unused RAM
blocks, and it contains control registers for the DC-DC regulator and the Voltage Monitor (VMON). The VMON is used to monitor multi-
ple supply voltages. It has multiple channels which can be programmed individually by the user to determine if a sensed supply has
fallen below a chosen threshold.
3.3.2 DC-DC Converter
The DC-DC buck converter covers a wide range of load currents and provides up to 90% efficiency in energy modes EM0, EM1, EM2
and EM3, and can supply up to 200 mA to the device and surrounding PCB components. Patented RF noise mitigation allows operation
of the DC-DC converter without degrading sensitivity of radio components. Protection features include programmable current limiting,
short-circuit protection, and dead-time protection. The DC-DC converter may also enter bypass mode when the input voltage is too low
for efficient operation. In bypass mode, the DC-DC input supply is internally connected directly to its output through a low resistance
switch. Bypass mode also supports in-rush current limiting to prevent input supply voltage droops due to excessive output current tran-
sients.
3.3.3 Power Domains
The EFR32FG12 has two peripheral power domains for operation in EM2 and lower. If all of the peripherals in a peripheral power do-
main are configured as unused, the power domain for that group will be powered off in the low-power mode, reducing the overall cur-
rent consumption of the device.
Table 3.1. Peripheral Power Subdomains
Peripheral Power Domain 1
Peripheral Power Domain 2
ACMP0
ACMP1
PCNT1
PCNT2
CSEN
DAC0
PCNT0
ADC0
LETIMER0
LESENSE
APORT
LEUART0
I2C0
-
-
-
I2C1
IDAC
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
System Overview
3.4 General Purpose Input/Output (GPIO)
EFR32FG12 has up to 65 General Purpose Input/Output pins. Each GPIO pin can be individually configured as either an output or in-
put. More advanced configurations including open-drain, open-source, and glitch-filtering can be configured for each individual GPIO
pin. The GPIO pins can be overridden by peripheral connections, like SPI communication. Each peripheral connection can be routed to
several GPIO pins on the device. The input value of a GPIO pin can be routed through the Peripheral Reflex System to other peripher-
als. The GPIO subsystem supports asynchronous external pin interrupts.
3.5 Clocking
3.5.1 Clock Management Unit (CMU)
The Clock Management Unit controls oscillators and clocks in the EFR32FG12. Individual enabling and disabling of clocks to all periph-
eral modules is performed by the CMU. The CMU also controls enabling and configuration of the oscillators. A high degree of flexibility
allows software to optimize energy consumption in any specific application by minimizing power dissipation in unused peripherals and
oscillators.
3.5.2 Internal and External Oscillators
The EFR32FG12 supports two crystal oscillators and fully integrates four RC oscillators, listed below.
• A high frequency crystal oscillator (HFXO) with integrated load capacitors, tunable in small steps, provides a precise timing refer-
ence for the MCU. Crystal frequencies in the range from 38 to 40 MHz are supported. An external clock source such as a TCXO can
also be applied to the HFXO input for improved accuracy over temperature.
• A 32.768 kHz crystal oscillator (LFXO) provides an accurate timing reference for low energy modes.
• An integrated high frequency RC oscillator (HFRCO) is available for the MCU system, when crystal accuracy is not required. The
HFRCO employs fast startup at minimal energy consumption combined with a wide frequency range.
• An integrated auxilliary high frequency RC oscillator (AUXHFRCO) is available for timing the general-purpose ADC and the Serial
Wire debug port with a wide frequency range.
• An integrated low frequency 32.768 kHz RC oscillator (LFRCO) can be used as a timing reference in low energy modes, when crys-
tal accuracy is not required.
• An integrated ultra-low frequency 1 kHz RC oscillator (ULFRCO) is available to provide a timing reference at the lowest energy con-
sumption in low energy modes.
3.6 Counters/Timers and PWM
3.6.1 Timer/Counter (TIMER)
TIMER peripherals keep track of timing, count events, generate PWM outputs and trigger timed actions in other peripherals through the
PRS system. The core of each TIMER is a 16-bit counter with up to 4 compare/capture channels. Each channel is configurable in one
of three modes. In capture mode, the counter state is stored in a buffer at a selected input event. In compare mode, the channel output
reflects the comparison of the counter to a programmed threshold value. In PWM mode, the TIMER supports generation of pulse-width
modulation (PWM) outputs of arbitrary waveforms defined by the sequence of values written to the compare registers, with optional
dead-time insertion available in timer unit TIMER_0 only.
3.6.2 Wide Timer/Counter (WTIMER)
WTIMER peripherals function just as TIMER peripherals, but are 32 bits wide. They keep track of timing, count events, generate PWM
outputs and trigger timed actions in other peripherals through the PRS system. The core of each WTIMER is a 32-bit counter with up to
4 compare/capture channels. Each channel is configurable in one of three modes. In capture mode, the counter state is stored in a
buffer at a selected input event. In compare mode, the channel output reflects the comparison of the counter to a programmed thresh-
old value. In PWM mode, the WTIMER supports generation of pulse-width modulation (PWM) outputs of arbitrary waveforms defined by
the sequence of values written to the compare registers, with optional dead-time insertion available in timer unit WTIMER_0 only.
3.6.3 Real Time Counter and Calendar (RTCC)
The Real Time Counter and Calendar (RTCC) is a 32-bit counter providing timekeeping in all energy modes. The RTCC includes a
Binary Coded Decimal (BCD) calendar mode for easy time and date keeping. The RTCC can be clocked by any of the on-board oscilla-
tors with the exception of the AUXHFRCO, and it is capable of providing system wake-up at user defined instances. When receiving
frames, the RTCC value can be used for timestamping. The RTCC includes 128 bytes of general purpose data retention, allowing easy
and convenient data storage in all energy modes.
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
System Overview
3.6.4 Low Energy Timer (LETIMER)
The unique LETIMER is a 16-bit timer that is available in energy mode EM2 Deep Sleep in addition to EM1 Sleep and EM0 Active. This
allows it to be used for timing and output generation when most of the device is powered down, allowing simple tasks to be performed
while the power consumption of the system is kept at an absolute minimum. The LETIMER can be used to output a variety of wave-
forms with minimal software intervention. The LETIMER is connected to the Real Time Counter and Calendar (RTCC), and can be con-
figured to start counting on compare matches from the RTCC.
3.6.5 Ultra Low Power Wake-up Timer (CRYOTIMER)
The CRYOTIMER is a 32-bit counter that is capable of running in all energy modes. It can be clocked by either the 32.768 kHz crystal
oscillator (LFXO), the 32.768 kHz RC oscillator (LFRCO), or the 1 kHz RC oscillator (ULFRCO). It can provide periodic Wakeup events
and PRS signals which can be used to wake up peripherals from any energy mode. The CRYOTIMER provides a wide range of inter-
rupt periods, facilitating flexible ultra-low energy operation.
3.6.6 Pulse Counter (PCNT)
The Pulse Counter (PCNT) peripheral can be used for counting pulses on a single input or to decode quadrature encoded inputs. The
clock for PCNT is selectable from either an external source on pin PCTNn_S0IN or from an internal timing reference, selectable from
among any of the internal oscillators, except the AUXHFRCO. The module may operate in energy mode EM0 Active, EM1 Sleep, EM2
Deep Sleep, and EM3 Stop.
3.6.7 Watchdog Timer (WDOG)
The watchdog timer can act both as an independent watchdog or as a watchdog synchronous with the CPU clock. It has windowed
monitoring capabilities, and can generate a reset or different interrupts depending on the failure mode of the system. The watchdog can
also monitor autonomous systems driven by PRS.
3.7 Communications and Other Digital Peripherals
3.7.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
The Universal Synchronous/Asynchronous Receiver/Transmitter is a flexible serial I/O module. It supports full duplex asynchronous
UART communication with hardware flow control as well as RS-485, SPI, MicroWire and 3-wire. It can also interface with devices sup-
porting:
• ISO7816 SmartCards
• IrDA
I2S
•
3.7.2 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART)
The unique LEUARTTM provides two-way UART communication on a strict power budget. Only a 32.768 kHz clock is needed to allow
UART communication up to 9600 baud. The LEUART includes all necessary hardware to make asynchronous serial communication
possible with a minimum of software intervention and energy consumption.
3.7.3 Inter-Integrated Circuit Interface (I2C)
The I2C module provides an interface between the MCU and a serial I2C bus. It is capable of acting as both a master and a slave and
supports multi-master buses. Standard-mode, fast-mode and fast-mode plus speeds are supported, allowing transmission rates from 10
kbit/s up to 1 Mbit/s. Slave arbitration and timeouts are also available, allowing implementation of an SMBus-compliant system. The
interface provided to software by the I2C module allows precise timing control of the transmission process and highly automated trans-
fers. Automatic recognition of slave addresses is provided in active and low energy modes.
3.7.4 Peripheral Reflex System (PRS)
The Peripheral Reflex System provides a communication network between different peripheral modules without software involvement.
Peripheral modules producing Reflex signals are called producers. The PRS routes Reflex signals from producers to consumer periph-
erals which in turn perform actions in response. Edge triggers and other functionality such as simple logic operations (AND, OR, NOT)
can be applied by the PRS to the signals. The PRS allows peripheral to act autonomously without waking the MCU core, saving power.
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
System Overview
3.7.5 Low Energy Sensor Interface (LESENSE)
The Low Energy Sensor Interface LESENSETM is a highly configurable sensor interface with support for up to 16 individually configura-
ble sensors. By controlling the analog comparators, ADC, and DAC, LESENSE is capable of supporting a wide range of sensors and
measurement schemes, and can for instance measure LC sensors, resistive sensors and capacitive sensors. LESENSE also includes a
programmable finite state machine which enables simple processing of measurement results without CPU intervention. LESENSE is
available in energy mode EM2, in addition to EM0 and EM1, making it ideal for sensor monitoring in applications with a strict energy
budget.
3.8 Security Features
3.8.1 GPCRC (General Purpose Cyclic Redundancy Check)
The GPCRC module implements a Cyclic Redundancy Check (CRC) function. It supports both 32-bit and 16-bit polynomials. The sup-
ported 32-bit polynomial is 0x04C11DB7 (IEEE 802.3), while the 16-bit polynomial can be programmed to any value, depending on the
needs of the application.
3.8.2 Crypto Accelerator (CRYPTO)
The Crypto Accelerator is a fast and energy-efficient autonomous hardware encryption and decryption accelerator. EFR32 devices sup-
port AES encryption and decryption with 128- or 256-bit keys, ECC over both GF(P) and GF(2m), SHA-1 and SHA-2 (SHA-224 and
SHA-256).
Supported block cipher modes of operation for AES include: ECB, CTR, CBC, PCBC, CFB, OFB, GCM, CBC-MAC, GMAC and CCM.
Supported ECC NIST recommended curves include P-192, P-224, P-256, K-163, K-233, B-163 and B-233.
The CRYPTO is tightly linked to the Radio Buffer Controller (BUFC) enabling fast and efficient autonomous cipher operations on data
buffer content. It allows fast processing of GCM (AES), ECC and SHA with little CPU intervention. CRYPTO also provides trigger sig-
nals for DMA read and write operations.
3.8.3 True Random Number Generator (TRNG)
The TRNG module is a non-deterministic random number generator based on a full hardware solution. The TRNG is validated with
NIST800-22 and AIS-31 test suites as well as being suitable for FIPS 140-2 certification (for the purposes of cryptographic key genera-
tion).
3.8.4 Security Management Unit (SMU)
The Security Management Unit (SMU) allows software to set up fine-grained security for peripheral access, which is not possible in the
Memory Protection Unit (MPU). Peripherals may be secured by hardware on an individual basis, such that only priveleged accesses to
the peripheral's register interface will be allowed. When an access fault occurs, the SMU reports the specific peripheral involved and
can optionally generate an interrupt.
3.9 Analog
3.9.1 Analog Port (APORT)
The Analog Port (APORT) is an analog interconnect matrix allowing access to many analog modules on a flexible selection of pins.
Each APORT bus consists of analog switches connected to a common wire. Since many clients can operate differentially, buses are
grouped by X/Y pairs.
3.9.2 Analog Comparator (ACMP)
The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is high-
er. Inputs are selected from among internal references and external pins. The tradeoff between response time and current consumption
is configurable by software. Two 6-bit reference dividers allow for a wide range of internally-programmable reference sources. The
ACMP can also be used to monitor the supply voltage. An interrupt can be generated when the supply falls below or rises above the
programmable threshold.
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System Overview
3.9.3 Analog to Digital Converter (ADC)
The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits at up to 1 Msps. The output
sample resolution is configurable and additional resolution is possible using integrated hardware for averaging over multiple samples.
The ADC includes integrated voltage references and an integrated temperature sensor. Inputs are selectable from a wide range of
sources, including pins configurable as either single-ended or differential.
3.9.4 Capacitive Sense (CSEN)
The CSEN module is a dedicated Capacitive Sensing block for implementing touch-sensitive user interface elements such a switches
and sliders. The CSEN module uses a charge ramping measurement technique, which provides robust sensing even in adverse condi-
tions including radiated noise and moisture. The module can be configured to take measurements on a single port pin or scan through
multiple pins and store results to memory through DMA. Several channels can also be shorted together to measure the combined ca-
pacitance or implement wake-on-touch from very low energy modes. Hardware includes a digital accumulator and an averaging filter,
as well as digital threshold comparators to reduce software overhead.
3.9.5 Digital to Analog Current Converter (IDAC)
The Digital to Analog Current Converter can source or sink a configurable constant current. This current can be driven on an output pin
or routed to the selected ADC input pin for capacitive sensing. The full-scale current is programmable between 0.05 µA and 64 µA with
several ranges consisting of various step sizes.
3.9.6 Digital to Analog Converter (VDAC)
The Digital to Analog Converter (VDAC) can convert a digital value to an analog output voltage. The VDAC is a fully differential, 500
ksps, 12-bit converter. The opamps are used in conjunction with the VDAC, to provide output buffering. One opamp is used per single-
ended channel, or two opamps are used to provide differential outputs. The VDAC may be used for a number of different applications
such as sensor interfaces or sound output. The VDAC can generate high-resolution analog signals while the MCU is operating at low
frequencies and with low total power consumption. Using DMA and a timer, the VDAC can be used to generate waveforms without any
CPU intervention. The VDAC is available in all energy modes down to and including EM3.
3.9.7 Operational Amplifiers
The opamps are low power amplifiers with a high degree of flexibility targeting a wide variety of standard opamp application areas. With
flexible built-in programming for gain and interconnection they can be configured to support multiple common opamp functions. All pins
are also available externally for filter configurations. Each opamp has a rail to rail input and a rail to rail output. They can be used in
conjunction with the VDAC module or in stand-alone configurations. The opamps save energy, PCB space, and cost as compared with
standalone opamps because they are integrated on-chip.
3.10 Reset Management Unit (RMU)
The RMU is responsible for handling reset of the EFR32FG12. A wide range of reset sources are available, including several power
supply monitors, pin reset, software controlled reset, core lockup reset, and watchdog reset.
3.11 Core and Memory
3.11.1 Processor Core
The ARM Cortex-M processor includes a 32-bit RISC processor integrating the following features and tasks in the system:
• ARM Cortex-M4 RISC processor achieving 1.25 Dhrystone MIPS/MHz
• Memory Protection Unit (MPU) supporting up to 8 memory segments
• Up to 1024 kB flash program memory
• Up to 256 kB RAM data memory
• Configuration and event handling of all modules
• 2-pin Serial-Wire debug interface
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System Overview
3.11.2 Memory System Controller (MSC)
The Memory System Controller (MSC) is the program memory unit of the microcontroller. The flash memory is readable and writable
from both the Cortex-M and DMA. The flash memory is divided into two blocks; the main block and the information block. Program code
is normally written to the main block, whereas the information block is available for special user data and flash lock bits. There is also a
read-only page in the information block containing system and device calibration data. Read and write operations are supported in en-
ergy modes EM0 Active and EM1 Sleep.
3.11.3 Linked Direct Memory Access Controller (LDMA)
The Linked Direct Memory Access (LDMA) controller allows the system to perform memory operations independently of software. This
reduces both energy consumption and software workload. The LDMA allows operations to be linked together and staged, enabling so-
phisticated operations to be implemented.
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Rev. 1.0 | 11
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
System Overview
3.12 Memory Map
The EFR32FG12 memory map is shown in the figures below. RAM and flash sizes are for the largest memory configuration.
Figure 3.2. EFR32FG12 Memory Map — Core Peripherals and Code Space
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Rev. 1.0 | 12
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
System Overview
Figure 3.3. EFR32FG12 Memory Map — Peripherals
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Rev. 1.0 | 13
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
System Overview
3.13 Configuration Summary
The features of the EFR32FG12 are a subset of the feature set described in the device reference manual. The table below describes
device specific implementation of the features. Remaining modules support full configuration.
Table 3.2. Configuration Summary
Module
USART0
USART1
Configuration
Pin Connections
IrDA SmartCard
US0_TX, US0_RX, US0_CLK, US0_CS
US1_TX, US1_RX, US1_CLK, US1_CS
IrDA I2S SmartCard
IrDA SmartCard
USART2
USART3
US2_TX, US2_RX, US2_CLK, US2_CS
US3_TX, US3_RX, US3_CLK, US3_CS
IrDA I2S SmartCard
TIMER0
with DTI
TIM0_CC[2:0], TIM0_CDTI[2:0]
TIM1_CC[3:0]
TIMER1
-
WTIMER0
WTIMER1
with DTI
-
WTIM0_CC[2:0], WTIM0_CDTI[2:0]
WTIM1_CC[3:0]
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Rev. 1.0 | 14
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
4. Electrical Specifications
4.1 Electrical Characteristics
All electrical parameters in all tables are specified under the following conditions, unless stated otherwise:
• Typical values are based on TAMB=25 °C and VDD= 3.3 V, by production test and/or technology characterization.
• Radio performance numbers are measured in conducted mode, based on Silicon Laboratories reference designs using output pow-
er-specific external RF impedance-matching networks for interfacing to a 50 Ω antenna.
• Minimum and maximum values represent the worst conditions across supply voltage, process variation, and operating temperature,
unless stated otherwise.
Refer to 4.1.2.1 General Operating Conditions for more details about operational supply and temperature limits.
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Rev. 1.0 | 15
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
4.1.1 Absolute Maximum Ratings
Stresses above those listed below may cause permanent damage to the device. This is a stress rating only and functional operation of
the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure
to maximum rating conditions for extended periods may affect device reliability. For more information on the available quality and relia-
bility data, see the Quality and Reliability Monitor Report at http://www.silabs.com/support/quality/pages/default.aspx.
Table 4.1. Absolute Maximum Ratings
Parameter
Symbol
TSTG
Test Condition
Min
-50
-0.3
—
Typ
—
Max
150
3.8
1
Unit
°C
Storage temperature range
Voltage on any supply pin
VDDMAX
VDDRAMPMAX
—
V
Voltage ramp rate on any
supply pin
—
V / μs
5V tolerant GPIO pins1
DC voltage on any GPIO pin VDIGPIN
-0.3
—
Min of 5.25
and IOVDD
+2
V
Non-5V tolerant GPIO pins
-0.3
-0.3
—
—
—
—
IOVDD+0.3
V
V
Voltage on HFXO pins
VHFXOPIN
1.4
10
Input RF level on pins
2G4RF_IOP and
2G4RF_ION
PRFMAX2G4
dBm
Voltage differential between VMAXDIFF2G4
RF pins (2G4RF_IOP -
2G4RF_ION)
-50
—
—
50
mV
V
Absolute voltage on RF pins VMAX2G4
2G4RF_IOP and
-0.3
3.3
2G4RF_ION
Absolute voltage on Sub-
GHz RF pins
VMAXSUBG
Pins SUBGRF_OP and
SUBGRF_ON
-0.3
-0.3
—
—
—
—
3.3
0.3
200
V
V
Pins SUBGRF_IP and
SUBGRF_IN,
Total current into VDD power IVDDMAX
lines
Source
mA
Total current into VSS
ground lines
IVSSMAX
IIOMAX
IIOALLMAX
TJ
Sink
—
—
—
—
—
—
-40
—
—
—
—
—
—
—
200
200
50
mA
mA
mA
mA
mA
mA
°C
Sink
Current per I/O pin
Sink
Source
Sink
50
Current for all I/O pins
200
200
105
Source
-G grade devices
Junction temperature
Note:
1. When a GPIO pin is routed to the analog module through the APORT, the maximum voltage = IOVDD.
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Rev. 1.0 | 16
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
4.1.2 Operating Conditions
When assigning supply sources, the following requirements must be observed:
• VREGVDD must be the highest voltage in the system
• VREGVDD = AVDD
• DVDD ≤ AVDD
• IOVDD ≤ AVDD
• RFVDD ≤ AVDD
• PAVDD ≤ AVDD
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Rev. 1.0 | 17
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
4.1.2.1 General Operating Conditions
Table 4.2. General Operating Conditions
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Operating ambient tempera- TA
ture range
-G temperature grade
-40
25
85
°C
AVDD supply voltage3
VAVDD
1.8
3.3
3.8
V
VREGVDD operating supply VVREGVDD
voltage3 1
DCDC in regulation
2.4
1.8
1.8
3.3
3.3
3.3
3.8
3.8
3.8
V
V
V
DCDC in bypass 50mA load
DCDC not in use. DVDD external-
ly shorted to VREGVDD
VREGVDD current
IVREGVDD
VRFVDD
DCDC in bypass
—
—
—
200
mA
V
RFVDD operating supply
voltage
1.62
VVREGVDD
DVDD operating supply volt- VDVDD
age
1.62
1.62
1.62
0.75
—
—
VVREGVDD
VVREGVDD
VVREGVDD
2.75
V
V
PAVDD operating supply
voltage
VPAVDD
IOVDD operating supply volt- VIOVDD
age (All IOVDD pins)
—
V
DECOUPLE output capaci-
tor4
CDECOUPLE
1.0
μF
Difference between AVDD
dVDD
—
—
0.1
V
and VREGVDD, ABS(AVDD-
VREGVDD)2
HFCORECLK frequency
fCORE
VSCALE2, MODE = WS1
VSCALE0, MODE = WS0
VSCALE2
—
—
—
—
—
—
—
—
40
20
40
20
MHz
MHz
MHz
MHz
HFCLK frequency
fHFCLK
VSCALE0
Note:
1. The minimum voltage required in bypass mode is calculated using RBYP from the DCDC specification table. Requirements for
other loads can be calculated as VDVDD_min+ILOAD * RBYP_max
.
2. AVDD and VREGVDD pins should be physically shorted.
3. VREGVDD must be tied to AVDD. Both VREGVDD and AVDD minimum voltages must be satisfied for the part to operate. .
4. The system designer should consult the characteristic specs of the capacitor used on DECOUPLE to ensure its capacitance val-
ue stays within the specified bounds across temperature and DC bias.
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Rev. 1.0 | 18
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
4.1.3 Thermal Characteristics
Table 4.3. Thermal Characteristics
Parameter
Symbol
THETAJA
Test Condition
Min
Typ
Max
Unit
Thermal Resistance
QFN48 Package, 2-Layer PCB,
Air velocity = 0 m/s
—
75.7
—
°C/W
QFN48 Package, 2-Layer PCB,
Air velocity = 1 m/s
—
—
—
—
—
—
—
—
—
—
—
61.5
55.4
30.2
26.3
24.9
90.7
73.7
66.4
45
—
—
—
—
—
—
—
—
—
—
—
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
QFN48 Package, 2-Layer PCB,
Air velocity = 2 m/s
QFN48 Package, 4-Layer PCB,
Air velocity = 0 m/s
QFN48 Package, 4-Layer PCB,
Air velocity = 1 m/s
QFN48 Package, 4-Layer PCB,
Air velocity = 2 m/s
BGA125 Package, 2-Layer PCB,
Air velocity = 0 m/s
BGA125 Package, 2-Layer PCB,
Air velocity = 1 m/s
BGA125 Package, 2-Layer PCB,
Air velocity = 2 m/s
BGA125 Package, 4-Layer PCB,
Air velocity = 0 m/s
BGA125 Package, 4-Layer PCB,
Air velocity = 1 m/s
39.6
37.6
BGA125 Package, 4-Layer PCB,
Air velocity = 2 m/s
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Rev. 1.0 | 19
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
4.1.4 DC-DC Converter
Test conditions: L_DCDC=4.7 μH (Murata LQH3NPN4R7MM0L), C_DCDC=4.7 μF (Samsung CL10B475KQ8NQNC), V_DCDC_I=3.3
V, V_DCDC_O=1.8 V, I_DCDC_LOAD=50 mA, Heavy Drive configuration, F_DCDC_LN=7 MHz, unless otherwise indicated.
Table 4.4. DC-DC Converter
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Input voltage range
VDCDC_I
Bypass mode, IDCDC_LOAD = 50
mA
1.8
—
VVREGVDD_
V
MAX
Low noise (LN) mode, 1.8 V out-
put, IDCDC_LOAD = 100 mA, or
Low power (LP) mode, 1.8 V out-
put, IDCDC_LOAD = 10 mA
2.4
—
VVREGVDD_
V
MAX
Low noise (LN) mode, 1.8 V out-
put, IDCDC_LOAD = 200 mA
2.6
1.8
—
—
VVREGVDD_
V
V
MAX
Output voltage programma- VDCDC_O
ble range1
VVREGVDD
Regulation DC accuracy
ACCDC
Low Noise (LN) mode, 1.8 V tar-
get output
1.7
—
—
1.9
2.2
V
V
Regulation window4
WINREG
Low Power (LP) mode,
LPCMPBIASEMxx3 = 0, 1.8 V tar-
get output, IDCDC_LOAD ≤ 75 μA
1.63
Low Power (LP) mode,
1.63
—
2.1
V
LPCMPBIASEMxx3 = 3, 1.8 V tar-
get output, IDCDC_LOAD ≤ 10 mA
Steady-state output ripple
VR
Radio disabled
—
—
3
—
mVpp
mV
CCM Mode (LNFORCECCM3 =
1), Load changes between 0 mA
and 100 mA
Output voltage under/over-
shoot
VOV
25
60
DCM Mode (LNFORCECCM3 =
0), Load changes between 0 mA
and 10 mA
—
45
90
mV
Overshoot during LP to LN
CCM/DCM mode transitions com-
pared to DC level in LN mode
—
—
200
40
—
—
mV
mV
Undershoot during BYP/LP to LN
CCM (LNFORCECCM3 = 1) mode
transitions compared to DC level
in LN mode
Undershoot during BYP/LP to LN
—
100
—
mV
DCM (LNFORCECCM3 = 0) mode
transitions compared to DC level
in LN mode
DC line regulation
DC load regulation
VREG
Input changes between
VVREGVDD_MAX and 2.4 V
—
—
0.1
0.1
—
—
%
%
IREG
Load changes between 0 mA and
100 mA in CCM mode
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Max load current
ILOAD_MAX
Low noise (LN) mode, Heavy
Drive2
—
—
200
mA
Low noise (LN) mode, Medium
Drive2
—
—
—
—
1
—
—
100
50
mA
mA
μA
Low noise (LN) mode, Light
Drive2
Low power (LP) mode,
LPCMPBIASEMxx3 = 0
—
75
Low power (LP) mode,
LPCMPBIASEMxx3 = 3
—
10
mA
μF
DCDC nominal output ca-
pacitor5
CDCDC
25% tolerance
4.7
4.7
DCDC nominal output induc- LDCDC
tor
20% tolerance
4.7
—
4.7
1.2
4.7
2.5
μH
Ω
Resistance in Bypass mode RBYP
Note:
1. Due to internal dropout, the DC-DC output will never be able to reach its input voltage, VVREGVDD
.
2. Drive levels are defined by configuration of the PFETCNT and NFETCNT registers. Light Drive: PFETCNT=NFETCNT=3; Medi-
um Drive: PFETCNT=NFETCNT=7; Heavy Drive: PFETCNT=NFETCNT=15.
3. LPCMPBIASEMxx refers to either LPCMPBIASEM234H in the EMU_DCDCMISCCTRL register or LPCMPBIASEM01 in the
EMU_DCDCLOEM01CFG register, depending on the energy mode.
4. LP mode controller is a hysteretic controller that maintains the output voltage withinthe specified limits.
5. Output voltage under/over-shoot and regulation are specified with CDCDC 4.7 μF. Different control loop settings must be used if
CDCDC is lower than 4.7 μF.
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Rev. 1.0 | 21
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
4.1.5 Current Consumption
4.1.5.1 Current Consumption 3.3 V without DC-DC Converter
Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = DVDD = RFVDD = PAVDD = 3.3 V. T = 25 °C. DCDC is off.
Minimum and maximum values in this table represent the worst conditions across supply voltage and process variation at T = 25 °C.
Table 4.5. Current Consumption 3.3 V without DC-DC Converter
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Current consumption in EM0 IACTIVE
mode with all peripherals dis-
abled
38.4 MHz crystal, CPU running
while loop from flash1
—
130
—
μA/MHz
38 MHz HFRCO, CPU running
Prime from flash
—
—
—
—
—
—
—
—
99
99
—
105
—
μA/MHz
μA/MHz
μA/MHz
μA/MHz
μA/MHz
μA/MHz
μA/MHz
μA/MHz
38 MHz HFRCO, CPU running
while loop from flash
38 MHz HFRCO, CPU running
CoreMark from flash
124
102
280
88
26 MHz HFRCO, CPU running
while loop from flash
108
435
—
1 MHz HFRCO, CPU running
while loop from flash
Current consumption in EM0 IACTIVE_VS
mode with all peripherals dis-
abled and voltage scaling
enabled
19 MHz HFRCO, CPU running
while loop from flash
1 MHz HFRCO, CPU running
while loop from flash
234
80
—
38.4 MHz crystal1
38 MHz HFRCO
26 MHz HFRCO
1 MHz HFRCO
19 MHz HFRCO
1 MHz HFRCO
Current consumption in EM1 IEM1
mode with all peripherals dis-
abled
—
—
—
—
—
—
50
52
54
58
μA/MHz
μA/MHz
μA/MHz
μA/MHz
μA/MHz
230
47
400
—
Current consumption in EM1 IEM1_VS
mode with all peripherals dis-
abled and voltage scaling
enabled
193
—
Current consumption in EM2 IEM2_VS
mode, with voltage scaling
enabled
Full 256 kB RAM retention and
RTCC running from LFXO
—
—
—
2.9
3.2
2.1
—
—
μA
μA
μA
Full 256 kB RAM retention and
RTCC running from LFRCO
16 kB (1 bank) RAM retention and
RTCC running from LFRCO2
3.5
Current consumption in EM3 IEM3_VS
mode, with voltage scaling
enabled
Full 256 kB RAM retention and
CRYOTIMER running from ULFR-
CO
—
2.56
4.8
μA
Current consumption in
EM4H mode, with voltage
scaling enabled
IEM4H_VS
128 byte RAM retention, RTCC
running from LFXO
—
—
—
1.0
—
—
μA
μA
μA
128 byte RAM retention, CRYO-
TIMER running from ULFRCO
0.45
0.43
128 byte RAM retention, no RTCC
0.9
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Rev. 1.0 | 22
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Current consumption in
EM4S mode
IEM4S
No RAM retention, no RTCC
—
0.04
0.1
μA
Note:
1. CMU_HFXOCTRL_LOWPOWER=0.
2. CMU_LFRCOCTRL_ENVREF = 1, CMU_LFRCOCTRL_VREFUPDATE = 1
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Rev. 1.0 | 23
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
4.1.5.2 Current Consumption 3.3 V using DC-DC Converter
Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD = 1.8 V DC-DC
output. T = 25 °C. Minimum and maximum values in this table represent the worst conditions across supply voltage and process varia-
tion at T = 25 °C.
Table 4.6. Current Consumption 3.3 V using DC-DC Converter
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Current consumption in EM0 IACTIVE_DCM
mode with all peripherals dis-
abled, DCDC in Low Noise
DCM mode2
38.4 MHz crystal, CPU running
while loop from flash4
—
88
—
μA/MHz
38 MHz HFRCO, CPU running
Prime from flash
—
—
—
—
—
—
70
70
—
—
—
—
—
—
μA/MHz
μA/MHz
μA/MHz
μA/MHz
μA/MHz
μA/MHz
38 MHz HFRCO, CPU running
while loop from flash
38 MHz HFRCO, CPU running
CoreMark from flash
85
26 MHz HFRCO, CPU running
while loop from flash
77
1 MHz HFRCO, CPU running
while loop from flash
636
98
Current consumption in EM0 IACTIVE_CCM
mode with all peripherals dis-
abled, DCDC in Low Noise
CCM mode1
38.4 MHz crystal, CPU running
while loop from flash4
38 MHz HFRCO, CPU running
Prime from flash
—
—
—
—
—
—
—
81
82
—
—
—
—
—
—
—
μA/MHz
μA/MHz
μA/MHz
μA/MHz
μA/MHz
μA/MHz
μA/MHz
38 MHz HFRCO, CPU running
while loop from flash
38 MHz HFRCO, CPU running
CoreMark from flash
95
26 MHz HFRCO, CPU running
while loop from flash
95
1 MHz HFRCO, CPU running
while loop from flash
1155
101
1128
Current consumption in EM0 IACTIVE_CCM_VS 19 MHz HFRCO, CPU running
mode with all peripherals dis-
abled and voltage scaling
enabled, DCDC in Low
Noise CCM mode1
while loop from flash
1 MHz HFRCO, CPU running
while loop from flash
38.4 MHz crystal4
38 MHz HFRCO
26 MHz HFRCO
1 MHz HFRCO
19 MHz HFRCO
1 MHz HFRCO
Current consumption in EM1 IEM1_DCM
mode with all peripherals dis-
abled, DCDC in Low Noise
—
59
—
μA/MHz
—
—
—
—
—
41
48
—
—
—
—
—
μA/MHz
μA/MHz
μA/MHz
μA/MHz
μA/MHz
DCM mode2
610
52
Current consumption in EM1 IEM1_DCM_VS
mode with all peripherals dis-
abled and voltage scaling
587
enabled, DCDC in Low
Noise DCM mode2
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Rev. 1.0 | 24
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Current consumption in EM2 IEM2_VS
mode, with voltage scaling
enabled, DCDC in LP mode3
Full 256 kB RAM retention and
RTCC running from LFXO
—
2.1
—
μA
Full 256 kB RAM retention and
RTCC running from LFRCO
—
—
2.2
1.5
—
—
μA
μA
16 kB (1 bank) RAM retention and
RTCC running from LFRCO5
Current consumption in EM3 IEM3_VS
mode, with voltage scaling
enabled
Full 256 kB RAM retention and
CRYOTIMER running from ULFR-
CO
—
1.81
—
μA
Current consumption in
EM4H mode, with voltage
scaling enabled
IEM4H_VS
128 byte RAM retention, RTCC
running from LFXO
—
—
0.69
0.39
—
—
μA
μA
128 byte RAM retention, CRYO-
TIMER running from ULFRCO
128 byte RAM retention, no RTCC
No RAM retention, no RTCC
—
—
0.39
0.06
—
—
μA
μA
Current consumption in
EM4S mode
IEM4S
Note:
1. DCDC Low Noise CCM Mode = Light Drive (PFETCNT=NFETCNT=3), F=6.4 MHz (RCOBAND=4), ANASW=DVDD.
2. DCDC Low Noise DCM Mode = Light Drive (PFETCNT=NFETCNT=3), F=3.0 MHz (RCOBAND=0), ANASW=DVDD.
3. DCDC Low Power Mode = Medium Drive (PFETCNT=NFETCNT=7), LPOSCDIV=1, LPCMPBIASEM234H=0, LPCLIMILIM-
SEL=1, ANASW=DVDD.
4. CMU_HFXOCTRL_LOWPOWER=0.
5. CMU_LFRCOCTRL_ENVREF = 1, CMU_LFRCOCTRL_VREFUPDATE = 1
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Rev. 1.0 | 25
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
4.1.5.3 Current Consumption 1.8 V without DC-DC Converter
Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = DVDD = RFVDD = PAVDD = 1.8 V. T = 25 °C. DCDC is off.
Minimum and maximum values in this table represent the worst conditions across supply voltage and process variation at T = 25 °C.
Table 4.7. Current Consumption 1.8 V without DC-DC Converter
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Current consumption in EM0 IACTIVE
mode with all peripherals dis-
abled
38.4 MHz crystal, CPU running
while loop from flash1
—
130
—
μA/MHz
38 MHz HFRCO, CPU running
Prime from flash
—
—
—
—
—
—
—
—
99
99
—
—
—
—
—
—
—
—
μA/MHz
μA/MHz
μA/MHz
μA/MHz
μA/MHz
μA/MHz
μA/MHz
μA/MHz
38 MHz HFRCO, CPU running
while loop from flash
38 MHz HFRCO, CPU running
CoreMark from flash
124
102
277
87
26 MHz HFRCO, CPU running
while loop from flash
1 MHz HFRCO, CPU running
while loop from flash
Current consumption in EM0 IACTIVE_VS
mode with all peripherals dis-
abled and voltage scaling
enabled
19 MHz HFRCO, CPU running
while loop from flash
1 MHz HFRCO, CPU running
while loop from flash
231
80
38.4 MHz crystal1
38 MHz HFRCO
26 MHz HFRCO
1 MHz HFRCO
19 MHz HFRCO
1 MHz HFRCO
Current consumption in EM1 IEM1
mode with all peripherals dis-
abled
—
—
—
—
—
50
52
—
—
—
—
—
μA/MHz
μA/MHz
μA/MHz
μA/MHz
μA/MHz
227
47
Current consumption in EM1 IEM1_VS
mode with all peripherals dis-
abled and voltage scaling
enabled
190
Current consumption in EM2 IEM2_VS
mode, with voltage scaling
enabled
Full 256 kB RAM retention and
RTCC running from LFXO
—
—
—
2.8
3.0
1.9
—
—
—
μA
μA
μA
Full 256 kB RAM retention and
RTCC running from LFRCO
16 kB (1 bank) RAM retention and
RTCC running from LFRCO2
Current consumption in EM3 IEM3_VS
mode, with voltage scaling
enabled
Full 256 kB RAM retention and
CRYOTIMER running from ULFR-
CO
—
2.47
—
μA
Current consumption in
EM4H mode, with voltage
scaling enabled
IEM4H_VS
128 byte RAM retention, RTCC
running from LFXO
—
—
0.91
0.35
—
—
μA
μA
128 byte RAM retention, CRYO-
TIMER running from ULFRCO
128 byte RAM retention, no RTCC
no RAM retention, no RTCC
—
—
0.35
0.04
—
—
μA
μA
Current consumption in
EM4S mode
IEM4S
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
Parameter
Note:
Symbol
Test Condition
Min
Typ
Max
Unit
1. CMU_HFXOCTRL_LOWPOWER=0.
2. CMU_LFRCOCTRL_ENVREF = 1, CMU_LFRCOCTRL_VREFUPDATE = 1
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Rev. 1.0 | 27
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
4.1.5.4 Current Consumption Using Radio 3.3 V with DC-DC
Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD = 1.8 V. T = 25
°C. Minimum and maximum values in this table represent the worst conditions across supply voltage and process variation at T = 25
°C.
Table 4.8. Current Consumption Using Radio 3.3 V with DC-DC
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Current consumption in re-
ceive mode, active packet
reception (MCU in EM1 @
38.4 MHz, peripheral clocks
disabled)
IRX_ACTIVE
500 kbit/s, 2GFSK, F = 915 MHz,
Radio clock prescaled by 4
—
9.3
10.2
mA
38.4 kbit/s, 2GFSK, F = 868 MHz,
Radio clock prescaled by 4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
8.6
8.6
10.2
10.2
10.2
10.2
10.2
—
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
38.4 kbit/s, 2GFSK, F = 490 MHz,
Radio clock prescaled by 4
50 kbit/s, 2GFSK, F = 433 MHz,
Radio clock prescaled by 4
8.6
38.4 kbit/s, 2GFSK, F = 315 MHz,
Radio clock prescaled by 4
8.6
38.4 kbit/s, 2GFSK, F = 169 MHz,
Radio clock prescaled by 4
8.4
1 Mbit/s, 2GFSK, F = 2.4 GHz,
Radio clock prescaled by 4
10.0
11.5
10.8
10.2
9.5
2 Mbit/s, 2GFSK, F = 2.4 GHz,
Radio clock prescaled by 4
—
802.15.4 receiving frame, F = 2.4
GHz, Radio clock prescaled by 3
—
Current consumption in re-
ceive mode, listening for
packet (MCU in EM1 @ 38.4
MHz, peripheral clocks disa-
bled)
IRX_LISTEN
500 kbit/s, 2GFSK, F = 915 MHz,
No radio clock prescaling
11
38.4 kbit/s, 2GFSK, F = 868 MHz,
No radio clock prescaling
11
38.4 kbit/s, 2GFSK, F = 490 MHz,
No radio clock prescaling
9.5
11
50 kbit/s, 2GFSK, F = 433 MHz,
No radio clock prescaling
9.5
11
38.4 kbit/s, 2GFSK, F = 315 MHz,
No radio clock prescaling
9.4
11
38.4 kbit/s, 2GFSK, F = 169 MHz,
No radio clock prescaling
9.3
11
1 Mbit/s, 2GFSK, F = 2.4 GHz, No
radio clock prescaling
10.9
11.9
12.3
—
2 Mbit/s, 2GFSK, F = 2.4 GHz, No
radio clock prescaling
—
802.15.4, F = 2.4 GHz, No radio
clock prescaling
—
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Rev. 1.0 | 28
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Current consumption in
transmit mode (MCU in EM1
@ 38.4 MHz, peripheral
clocks disabled)
ITX
F = 915 MHz, CW, 20 dBm
match, PAVDD connected directly
to external 3.3V supply
—
90.2
134.3
mA
F = 915 MHz, CW, 14 dBm
match, PAVDD connected to
DCDC output
—
—
—
—
—
—
—
—
36
42.5
106.7
41
mA
mA
mA
mA
mA
mA
mA
mA
F = 868 MHz, CW, 20 dBm
match, PAVDD connected directly
to external 3.3V supply
79.7
35.3
93.8
20.3
34
F = 868 MHz, CW, 14 dBm
match, PAVDD connected to
DCDC output
F = 490 MHz, CW, 20 dBm
match, PAVDD connected directly
to external 3.3V supply
125.4
24
F = 433 MHz, CW, 10 dBm
match, PAVDD connected to
DCDC output
F = 433 MHz, CW, 14 dBm
match, PAVDD connected to
DCDC output
41.5
42
F = 315 MHz, CW, 14 dBm
match, PAVDD connected to
DCDC output
33.5
88.6
F = 169 MHz, CW, 20 dBm
match, PAVDD connected directly
to external 3.3V supply
116.7
F = 2.4 GHz, CW, 0 dBm output
power, Radio clock prescaled by 3
—
—
—
—
—
—
8.5
9.5
16.5
26
—
—
—
—
—
—
mA
mA
mA
mA
mA
mA
F = 2.4 GHz, CW, 0 dBm output
power, Radio clock prescaled by 1
F = 2.4 GHz, CW, 3 dBm output
power
F = 2.4 GHz, CW, 8 dBm output
power
F = 2.4 GHz, CW, 10.5 dBm out-
put power
34
F = 2.4 GHz, CW, 16.5 dBm out-
put power, PAVDD connected di-
rectly to external 3.3V supply
86
F = 2.4 GHz, CW, 19.5 dBm out-
put power, PAVDD connected di-
rectly to external 3.3V supply
—
131
—
mA
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Rev. 1.0 | 29
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
4.1.6 Wake Up Times
Table 4.9. Wake Up Times
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Wakeup time from EM1
tEM1_WU
—
3
—
AHB
Clocks
Wake up from EM2
Wake up from EM3
tEM2_WU
Code execution from flash
Code execution from RAM
Code execution from flash
Code execution from RAM
Executing from flash
—
—
—
—
—
10.1
3.2
—
—
—
—
—
μs
μs
μs
μs
μs
tEM3_WU
10.1
3.2
Wake up from EM4H1
Wake up from EM4S1
tEM4H_WU
tEM4S_WU
tRESET
80
Executing from flash
—
291
—
μs
Time from release of reset
source to first instruction ex-
ectution
Soft Pin Reset released
Any other reset released
—
—
43
—
—
μs
μs
350
Power mode scaling time
tSCALE
VSCALE0 to VSCALE2, HFCLK =
19 MHz4 2
—
—
31.8
4.3
—
—
μs
μs
VSCALE2 to VSCALE0, HFCLK =
19 MHz3
Note:
1. Time from wakeup request until first instruction is executed. Wakeup results in device reset.
2. VSCALE0 to VSCALE2 voltage change transitions occur at a rate of 10 mV/μs for approximately 20 μs. During this transition,
peak currents will be dependent on the value of the DECOUPLE output capacitor, from 35 mA (with a 1 μF capacitor) to 70 mA
(with a 2.7 μF capacitor).
3. Scaling down from VSCALE2 to VSCALE0 requires approximately 2.8 μs + 29 HFCLKs.
4. Scaling up from VSCALE0 to VSCALE2 requires approximately 30.3 μs + 28 HFCLKs.
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Rev. 1.0 | 30
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
4.1.7 Brown Out Detector (BOD)
Table 4.10. Brown Out Detector (BOD)
Parameter
Symbol
Test Condition
Min
—
Typ
—
Max
1.62
—
Unit
V
DVDD BOD threshold
VDVDDBOD
DVDD rising
DVDD falling (EM0/EM1)
DVDD falling (EM2/EM3)
1.35
1.3
—
—
V
—
—
V
DVDD BOD hysteresis
DVDD BOD response time
AVDD BOD threshold
VDVDDBOD_HYST
18
2.4
—
—
mV
μs
V
tDVDDBOD_DELAY Supply drops at 0.1V/μs rate
—
—
VAVDDBOD
AVDD rising
—
1.8
—
AVDD falling (EM0/EM1)
AVDD falling (EM2/EM3)
1.62
1.53
—
—
V
—
—
V
AVDD BOD hysteresis
AVDD BOD response time
EM4 BOD threshold
VAVDDBOD_HYST
20
2.4
—
—
mV
μs
V
tAVDDBOD_DELAY Supply drops at 0.1V/μs rate
—
—
VEM4DBOD
AVDD rising
AVDD falling
—
1.7
—
1.45
—
—
V
EM4 BOD hysteresis
VEM4BOD_HYST
25
300
—
mV
μs
EM4 BOD response time
tEM4BOD_DELAY Supply drops at 0.1V/μs rate
—
—
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Rev. 1.0 | 31
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
4.1.8 Frequency Synthesizer
Table 4.11. Frequency Synthesizer
Parameter
Symbol
Test Condition
2400 - 2483.5 MHz
779 - 956 MHz
584 - 717 MHz
358 - 574 MHz
191 - 358 MHz
110 - 191 MHz
2400 - 2483.5 MHz
779 - 956 MHz
584 - 717 MHz
358 - 574 MHz
191 - 358 MHz
110 - 191 MHz
2400 - 2483.5 MHz
779 - 956 MHz
584 - 717 MHz
358 - 574 MHz
191 - 358 MHz
110 - 191 MHz
2400 - 2483.5 MHz
779 - 956 MHz
584 - 717 MHz
358 - 574 MHz
191 - 358 MHz
110 - 191 MHz
Min
2400
779
584
358
191
110
—
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
2483.5
956
717
574
358
191
73
Unit
MHz
MHz
MHz
MHz
MHz
MHz
Hz
RF synthesizer frequency
range
fRANGE
LO tuning frequency resolu- fRES
tion with 38.4 MHz crystal
—
24
Hz
—
18.3
12.2
7.3
Hz
—
Hz
—
Hz
—
4.6
Hz
Frequency deviation resolu- dfRES
tion with 38.4 MHz crystal
—
73
Hz
—
24
Hz
—
18.3
12.2
7.3
Hz
—
Hz
—
Hz
—
4.6
Hz
Maximum frequency devia-
tion with 38.4 MHz crystal
dfMAX
—
1677
559
419
280
167
105
kHz
kHz
kHz
kHz
kHz
kHz
—
—
—
—
—
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Rev. 1.0 | 32
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
4.1.9 2.4 GHz RF Transceiver Characteristics
4.1.9.1 RF Transmitter General Characteristics for 2.4 GHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 2.45 GHz.
Table 4.12. RF Transmitter General Characteristics for 2.4 GHz Band
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Maximum TX power1
POUTMAX
19.5 dBm-rated part numbers.
PAVDD connected directly to ex-
ternal 3.3V supply
—
19.5
—
dBm
Minimum active TX Power
Output power step size
POUTMIN
CW
-30
1
—
—
—
dBm
dB
POUTSTEP
-5 dBm< Output power < 0 dBm
—
—
0 dBm < output power <
POUTMAX
0.5
dB
Output power variation vs
supply at POUTMAX
POUTVAR_V
1.8 V < VVREGVDD < 3.3 V,
PAVDD connected directly to ex-
ternal supply, for output power >
10.5 dBm.
—
4.5
—
dB
1.8 V < VVREGVDD < 3.3 V using
DC-DC converter
—
—
2.2
1.5
1.5
0.4
—
—
—
dB
dB
Output power variation vs
temperature at POUTMAX
POUTVAR_T
From -40 to +85 °C, PAVDD con-
nected to DC-DC output
From -40 to +85 °C, PAVDD con-
nected to external supply
—
—
dB
Output power variation vs RF POUTVAR_F
frequency at POUTMAX
Over RF tuning frequency range
—
—
dB
RF tuning frequency range
FRANGE
2400
2483.5
MHz
Note:
1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices cov-
ered in this datasheet can be found in the Max TX Power column of the Ordering Information Table. .
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Rev. 1.0 | 33
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
4.1.9.2 RF Receiver General Characteristics for 2.4 GHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 2.45 GHz.
Table 4.13. RF Receiver General Characteristics for 2.4 GHz Band
Parameter
Symbol
FRANGE
SPURRX
Test Condition
Min
2400
—
Typ
—
Max
2483.5
—
Unit
MHz
dBm
dBm
dBm
RF tuning frequency range
Receive mode maximum
spurious emission
30 MHz to 1 GHz
1 GHz to 12 GHz
-57
—
-47
—
Max spurious emissions dur- SPURRX_FCC
ing active receive mode, per
FCC Part 15.109(a)
216 MHz to 960 MHz, Conducted
Measurement
—
-55.2
—
Above 960 MHz, Conducted
Measurement
—
—
-47.2
-24
—
—
dBm
dBm
Level above which
RFSENSE will trigger1
RFSENSETRIG
CW at 2.45 GHz
Level below which
RFSENSE will not trigger1
RFSENSETHRES CW at 2.45 GHz
—
-50
—
dBm
1% PER sensitivity
SENS2GFSK
2 Mbps 2GFSK signal
250 kbps 2GFSK signal
—
—
-89.6
—
—
dBm
dBm
-100.7
Note:
1. RFSENSE performance is only valid from 0 to 85 °C. RFSENSE should be disabled outside this temperature range.
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Rev. 1.0 | 34
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
4.1.9.3 RF Transmitter Characteristics for 1Mbps 2GFSK in the 2.4GHz Band, 1 Mbps Data Rate
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4MHz. RF center frequency 2.45 GHz. Maximum duty cycle of
85%.
Table 4.14. RF Transmitter Characteristics for 1Mbps 2GFSK in the 2.4GHz Band, 1 Mbps Data Rate
Parameter
Symbol
TXBW
Test Condition
Min
—
Typ
781
-8.4
Max
—
Unit
Transmit 6dB bandwidth
Power spectral density limit
10 dBm
kHz
PSDLIMIT
Per FCC part 15.247 at 10 dBm
—
—
dBm/
3kHz
Per FCC part 15.247 at 20 dBm
—
—
—
—
-0.4
10.1
1.1
—
—
—
—
dBm/
3kHz
Per ETSI 300.328 at 10 dBm/1
MHz
dBm
MHz
dBm
Occupied channel bandwidth OCPETSI328
per ETSI EN300.328
99% BW at highest and lowest
channels in band, 10 dBm
Emissions of harmonics out- SPURHRM_FCC 2nd,3rd, 5, 6, 8, 9,10 harmonics;
-47
of-band, per FCC part
15.247
continuous transmission of modu-
lated carrier
Spurious emissions out-of-
band, per FCC part 15.247,
excluding harmonics cap-
SPUROOB_FCC
Above 2.483 GHz or below 2.4
GHz; continuous transmission of
—
—
-47
-26
—
—
dBm
dBc
CW carrier, Restricted Bands1 2
tured in SPURHARM,FCC
.
Above 2.483 GHz or below 2.4
GHz; continuous transmission of
CW carrier, Non-Restricted Bands
Emissions taken at
Pout_Max power level of
19.5 dBm, PAVDD connec-
ted to external 3.3 V supply
Spurious emissions out-of-
band; per ETSI 300.328
SPURETSI328
[2400-BW to 2400] MHz, [2483.5
to 2483.5+BW] MHz
—
—
-16
-26
—
—
dBm
dBm
[2400-2BW to 2400-BW] MHz,
[2483.5+BW to 2483.5+2BW]
MHz per ETSI 300.328
Spurious emissions per ETSI SPURETSI440
EN300.440
47-74 MHz,87.5-108 MHz,
174-230 MHz, 470-862 MHz
—
-60
—
dBm
25-1000 MHz
1-12 GHz
—
—
-42
-36
—
—
dBm
dBm
Note:
1. For 2476 MHz, 1.5 dB of power backoff is used to achieve this value.
2. For 2478 MHz, 4.2 dB of power backoff is used to achieve this value.
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Rev. 1.0 | 35
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
4.1.9.4 RF Receiver Characteristics for 1Mbps 2GFSK in the 2.4GHz Band, 1 Mbps Data Rate
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4MHz. RF center frequency 2.45 GHz.
Table 4.15. RF Receiver Characteristics for 1Mbps 2GFSK in the 2.4GHz Band, 1 Mbps Data Rate
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Signal is reference signal1. Packet
length is 20 bytes.
Max usable receiver input
level, 0.1% BER
SAT
—
10
—
dBm
Signal is reference signal1. Using
DC-DC converter.
Sensitivity, 0.1% BER
SENS
—
-95.2
—
dBm
Signal to co-channel interfer- C/ICC
er, 0.1% BER
Desired signal 3 dB above refer-
ence sensitivity.
—
—
8.3
—
—
dB
dB
N+1 adjacent channel selec- C/I1+
tivity, 0.1% BER, with allowa-
ble exceptions. Desired is
Interferer is reference signal at +1
MHz offset. Desired frequency
2402 MHz ≤ Fc ≤ 2480 MHz
-6.5
reference signal at -67 dBm
N-1 adjacent channel selec- C/I1-
tivity, 0.1% BER, with allowa-
ble exceptions. Desired is
Interferer is reference signal at -1
MHz offset. Desired frequency
2402 MHz ≤ Fc ≤ 2480 MHz
—
—
—
-5.5
-44.5
-46.4
—
—
—
dB
dB
dB
reference signal at -67 dBm
Alternate selectivity, 0.1%
BER, with allowable excep-
tions. Desired is reference
signal at -67 dBm
C/I2
Interferer is reference signal at ± 2
MHz offset. Desired frequency
2402 MHz ≤ Fc ≤ 2480 MHz
Alternate selectivity, 0.1%
BER, with allowable excep-
tions. Desired is reference
signal at -67 dBm
C/I3
Interferer is reference signal at ± 3
MHz offset. Desired frequency
2404 MHz ≤ Fc ≤ 2480 MHz
Selectivity to image frequen- C/IIM
cy, 0.1% BER. Desired is ref-
erence signal at -67 dBm
Interferer is reference signal at im-
age frequency with 1 MHz preci-
sion
—
—
-39.8
-47
—
—
dB
dB
Selectivity to image frequen- C/IIM+1
cy ± 1 MHz, 0.1% BER. De-
sired is reference signal at
-67 dBm
Interferer is reference signal at im-
age frequency ± 1 MHz with 1
MHz precision
Blocking, 0.1% BER, Desired BLOCKOOB
is reference signal at -67
dBm. Interferer is CW in
OOB range
Interferer frequency 30 MHz ≤ f ≤
2000 MHz
—
—
—
—
-27
-32
-32
-27
—
—
—
—
dBm
dBm
dBm
dBm
Interferer frequency 2003 MHz ≤ f
≤ 2399 MHz
Interferer frequency 2484 MHz ≤ f
≤ 2997 MHz
Interferer frequency 3 GHz ≤ f ≤
12.75 GHz
Note:
1. Reference signal is defined 2GFSK at -67 dBm, Modulation index = 0.5, BT = 0.5, Bit rate = 1 Mbps, desired data = PRBS9;
interferer data = PRBS15; frequency accuracy better than 1 ppm.
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Rev. 1.0 | 36
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
4.1.9.5 RF Transmitter Characteristics for 1Mbps 2GFSK in the 2.4GHz Band, 2 Mbps Data Rate
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4MHz. RF center frequency 2.45 GHz. Maximum duty cycle of
85%.
Table 4.16. RF Transmitter Characteristics for 1Mbps 2GFSK in the 2.4GHz Band, 2 Mbps Data Rate
Parameter
Symbol
TXBW
Test Condition
Min
—
Typ
1404
-12.3
Max
—
Unit
Transmit 6dB bandwidth
Power spectral density limit
10 dBm
kHz
PSDLIMIT
Per FCC part 15.247 at 10 dBm
—
—
dBm/
3kHz
Per FCC part 15.247 at 20 dBm
—
—
—
—
-4.0
11.3
2.1
—
—
—
—
dBm/
3kHz
Per ETSI 300.328 at 10 dBm/1
MHz
dBm
MHz
dBm
Occupied channel bandwidth OCPETSI328
per ETSI EN300.328
99% BW at highest and lowest
channels in band, 10 dBm
Emissions of harmonics out- SPURHRM_FCC 2nd,3rd, 5, 6, 8, 9,10 harmonics;
-47
of-band, per FCC part
15.247
continuous transmission of modu-
lated carrier
Spurious emissions out-of-
band, per FCC part 15.247,
excluding harmonics cap-
SPUROOB_FCC
Above 2.483 GHz or below 2.4
GHz; continuous transmission of
—
—
-47
-26
—
—
dBm
dBc
CW carrier, Restricted Bands1 2 3
4
tured in SPURHARM,FCC
.
Emissions taken at
Above 2.483 GHz or below 2.4
GHz; continuous transmission of
CW carrier, Non-Restricted Bands
Pout_Max power level of
19.5 dBm, PAVDD connec-
ted to external 3.3 V supply
Spurious emissions out-of-
band; per ETSI 300.328
SPURETSI328
[2400-BW to 2400] MHz, [2483.5
to 2483.5+BW] MHz
—
—
-16
-26
—
—
dBm
dBm
[2400-2BW to 2400-BW] MHz,
[2483.5+BW to 2483.5+2BW]
MHz per ETSI 300.328
Spurious emissions per ETSI SPURETSI440
EN300.440
47-74 MHz,87.5-108 MHz,
174-230 MHz, 470-862 MHz
—
-60
—
dBm
25-1000 MHz
1-12 GHz
—
—
-42
-36
—
—
dBm
dBm
Note:
1. For 2472 MHz, 1.3 dB of power backoff is used to achieve this value.
2. For 2474 MHz, 3.8 dB of power backoff is used to achieve this value.
3. For 2476 MHz, 7 dB of power backoff is used to achieve this value.
4. For 2478 MHz, 11.2 dB of power backoff is used to achieve this value.
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
4.1.9.6 RF Receiver Characteristics for 1Mbps 2GFSK in the 2.4GHz Band, 2 Mbps Data Rate
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4MHz. RF center frequency 2.45 GHz1.
Table 4.17. RF Receiver Characteristics for 1Mbps 2GFSK in the 2.4GHz Band, 2 Mbps Data Rate
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Signal is reference signal2. Packet
length is 20 bytes.
Max usable receiver input
level, 0.1% BER
SAT
—
5
—
dBm
Signal is reference signal2. Using
DC-DC converter.
Sensitivity, 0.1% BER
SENS
—
-91.3
—
dBm
Signal to co-channel interfer- C/ICC
er, 0.1% BER
Desired signal 3 dB above refer-
ence sensitivity.
—
—
7.3
—
—
dB
dB
N+1 adjacent channel selec- C/I1+
tivity, 0.1% BER, with allowa-
ble exceptions. Desired is
Interferer is reference signal at +2
MHz offset. Desired frequency
2402 MHz ≤ Fc ≤ 2480 MHz
-10.4
reference signal at -67 dBm
N-1 adjacent channel selec- C/I1-
tivity, 0.1% BER, with allowa-
ble exceptions. Desired is
Interferer is reference signal at -2
MHz offset. Desired frequency
2402 MHz ≤ Fc ≤ 2480 MHz
—
—
—
-13.9
-40.9
-43.7
—
—
—
dB
dB
dB
reference signal at -67 dBm
Alternate selectivity, 0.1%
BER, with allowable excep-
tions. Desired is reference
signal at -67 dBm
C/I2
Interferer is reference signal at ± 4
MHz offset. Desired frequency
2402 MHz ≤ Fc ≤ 2480 MHz
Alternate selectivity, 0.1%
BER, with allowable excep-
tions. Desired is reference
signal at -67 dBm
C/I3
Interferer is reference signal at ± 6
MHz offset. Desired frequency
2404 MHz ≤ Fc ≤ 2480 MHz
Selectivity to image frequen- C/IIM
cy, 0.1% BER. Desired is ref-
erence signal at -67 dBm
Interferer is reference signal at im-
age frequency with 1 MHz preci-
sion
—
—
-10.4
-40.9
—
—
dB
dB
Selectivity to image frequen- C/IIM+1
cy ± 2 MHz, 0.1% BER. De-
sired is reference signal at
-67 dBm
Interferer is reference signal at im-
age frequency ± 2 MHz with 2
MHz precision
Blocking, 0.1% BER, Desired BLOCKOOB
is reference signal at -67
dBm. Interferer is CW in
OOB range
Interferer frequency 30 MHz ≤ f ≤
2000 MHz
—
—
—
—
-27
-32
-32
-27
—
—
—
—
dBm
dBm
dBm
dBm
Interferer frequency 2003 MHz ≤ f
≤ 2399 MHz
Interferer frequency 2484 MHz ≤ f
≤ 2997 MHz
Interferer frequency 3 GHz ≤ f ≤
12.75 GHz
Note:
1. For the BLE 2Mbps in-band blocking performance, there may be up to 5 spurious response channels where the requirement of
30.8% PER is not met and therefore an exception will need to be taken for each of these frequencies to meet the requirements of
the BLE standard.
2. Reference signal is defined 2GFSK at -67 dBm, Modulation index = 0.5, BT = 0.5, Bit rate = 2 Mbps, desired data = PRBS9;
interferer data = PRBS15; frequency accuracy better than 1 ppm.
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
4.1.9.7 RF Transmitter Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 2.45 GHz. Maximum duty cycle of
66%.
Table 4.18. RF Transmitter Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Error vector magnitude (off- EVM
set EVM), per
802.15.4-2011, not including
2415 MHz channel
Average across frequency. Signal
is DSSS-OQPSK reference pack-
et1
—
3.8
—
% rms
Power spectral density limit
PSDLIMIT
Relative, at carrier ± 3.5 MHz,
19.5 dBm output power level
—
—
-26
-36
—
—
dBc/
100kHz
Absolute, at carrier ± 3.5 MHz,
19.5 dBm output power level3
dBm/
100kHz
Per FCC part 15.247, 19.5 dBm
output power level
—
-4
—
dBm/
3kHz
ETSI
—
—
12.1
2.25
—
—
dBm
MHz
Occupied channel bandwidth OCPETSI328
per ETSI EN300.328
99% BW at highest and lowest
channels in band
Spurious emissions of har-
monics in restricted bands
per FCC Part 15.205/15.209,
Emissions taken at
SPURHRM_FCC_ Continuous transmission of modu-
—
-45.8
—
dBm
lated carrier
R
Pout_Max power level of
19.5 dBm, PAVDD connec-
ted to external 3.3 V supply,
Test Frequency is 2450 MHz
Spurious emissions of har-
monics in non-restricted
bands per FCC Part
SPURHRM_FCC_ Continuous transmission of modu-
—
-26
—
dBc
lated carrier
NRR
15.247/15.35, Emissions tak-
en at Pout_Max power level
of 19.5 dBm, PAVDD con-
nected to external 3.3 V sup-
ply, Test Frequency is 2450
MHz
Spurious emissions out-of-
band (above 2.483 GHz or
below 2.4 GHz) in restricted
bands, per FCC part
15.205/15.209, Emissions
taken at Pout_Max power
level of 19.5 dBm, PAVDD
connected to external 3.3 V
supply, Test Frequency =
2450 MHz
SPUROOB_FCC_ Restricted bands 30-88 MHz; con-
—
—
—
—
-61
-58
-55
-47
—
—
—
—
dBm
dBm
dBm
dBm
tinuous transmission of modulated
R
carrier
Restricted bands 88-216 MHz;
continuous transmission of modu-
lated carrier
Restricted bands 216-960 MHz;
continuous transmission of modu-
lated carrier
Restricted bands >960 MHz; con-
tinuous transmission of modulated
carrier4 5
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Spurious emissions out-of-
band in non-restricted bands
per FCC Part 15.247, Emis-
sions taken at Pout_Max
power level of 19.5 dBm,
PAVDD connected to exter-
nal 3.3 V supply, Test Fre-
quency = 2450 MHz
SPUROOB_FCC_ Above 2.483 GHz or below 2.4
—
-26
—
dBc
GHz; continuous transmission of
NR
modulated carrier
Spurious emissions out-of-
band; per ETSI 300.3282
SPURETSI328
[2400-BW to 2400], [2483.5 to
2483.5+BW];
—
—
-16
-26
—
—
dBm
dBm
[2400-2BW to 2400-BW],
[2483.5+BW to 2483.5+2BW]; per
ETSI 300.328
Spurious emissions per ETSI SPURETSI440
EN300.4402
47-74 MHz,87.5-108 MHz,
174-230 MHz, 470-862 MHz
—
—
—
-60
-42
-36
—
—
—
dBm
dBm
dBm
25-1000 MHz, excluding above
frequencies
1G-14G
Note:
1. Reference packet is defined as 20 octet PSDU, modulated according to 802.15.4-2011 DSSS-OQPSK in the 2.4GHz band, with
pseudo-random packet data content.
2. Specified at maximum power output level of 10 dBm.
3. For 2415 MHz, 2 dB of power backoff is used to achieve this value.
4. For 2475 MHz, 2 dB of power backoff is used to achieve this value.
5. For 2480 MHz, 13 dB of power backoff is used to achieve this value.
silabs.com | Building a more connected world.
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
4.1.9.8 RF Receiver Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 2.45 GHz.
Table 4.19. RF Receiver Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Signal is reference signal3. Packet
length is 20 octets.
Max usable receiver input
level, 1% PER
SAT
—
10
—
dBm
Sensitivity, 1% PER
SENS
Signal is reference signal. Packet
length is 20 octets. Using DC-DC
converter.
—
—
-102.7
-102.7
—
—
dBm
dBm
Signal is reference signal. Packet
length is 20 octets. Without DC-
DC converter.
Co-channel interferer rejec- CCR
tion, 1% PER
Desired signal 3 dB above sensi-
tivity limit
—
—
—
-4.6
40.7
47
—
—
—
dB
dB
dB
High-side adjacent channel
rejection, 1% PER. Desired
is reference signal at 3dB
above reference sensitivity
ACRP1
Interferer is reference signal at +1
channel-spacing.
Interferer is filtered reference sig-
nal1 at +1 channel-spacing.
level4
Interferer is CW at +1 channel-
spacing2.
—
54.3
—
dB
Low-side adjacent channel
rejection, 1% PER. Desired
is reference signal at 3dB
above reference sensitivity
ACRM1
ACR2
IR
Interferer is reference signal at -1
channel-spacing.
—
—
40.8
47.5
—
—
dB
dB
Interferer is filtered reference sig-
nal1 at -1 channel-spacing.
level4
Interferer is CW at -1 channel-
spacing.
—
—
—
56.5
51.5
53.7
—
—
—
dB
dB
dB
Alternate channel rejection,
1% PER. Desired is refer-
ence signal at 3dB above
reference sensitivity level4
Interferer is reference signal at ± 2
channel-spacing
Interferer is filtered reference sig-
nal1 at ± 2 channel-spacing
Interferer is CW at ± 2 channel-
spacing
—
—
62.4
50.4
—
—
dB
dB
Interferer is CW in image band2
Image rejection , 1% PER,
Desired is reference signal at
3dB above reference sensi-
tivity level4
Blocking rejection of all other BLOCK
channels. 1% PER, Desired
is reference signal at 3dB
above reference sensitivity
level4. Interferer is reference
signal
Interferer frequency < Desired fre-
quency - 3 channel-spacing
—
—
58.5
56.4
—
—
dB
dB
Interferer frequency > Desired fre-
quency + 3 channel-spacing
Blocking rejection of 802.11g BLOCK80211G
signal centered at +12MHz
or -13MHz
Desired is reference signal at 6dB
above reference sensitivity level4
—
53
—
dB
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Rev. 1.0 | 41
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Upper limit of input power
range over which RSSI reso-
lution is maintained
RSSIMAX
—
—
5
dBm
Lower limit of input power
range over which RSSI reso-
lution is maintained
RSSIMIN
-98
—
—
dBm
RSSI resolution
RSSIRES
RSSILIN
over RSSIMIN to RSSIMAX
—
—
0.25
+/-6
—
—
dB
dB
RSSI accuracy in the linear
region as defined by
802.15.4-2003
Note:
1. Filter is characterized as a symmetric bandpass centered on the adjacent channel having a 3dB bandwidth of 4.6 MHz and stop-
band rejection better than 26 dB beyond 3.15 MHz from the adjacent carrier.
2. Due to low-IF frequency, there is some overlap of adjacent channel and image channel bands. Adjacent channel CW blocker
tests place the Interferer center frequency at the Desired frequency ± 5 MHz on the channel raster, whereas the image rejection
test places the CW interferer near the image frequency of the Desired signal carrier, regardless of the channel raster.
3. Reference signal is defined as O-QPSK DSSS per 802.15.4, Frequency range = 2400-2483.5 MHz, Symbol rate = 62.5 ksym-
bols/s.
4. Reference sensitivity level is -85 dBm.
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
4.1.10 Sub-GHz RF Transceiver Characteristics
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Rev. 1.0 | 43
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
4.1.10.1 Sub-GHz RF Transmitter characteristics for 915 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 915 MHz.
Table 4.20. Sub-GHz RF Transmitter characteristics for 915 MHz Band
Parameter
Symbol
FRANGE
Test Condition
Min
902
18
Typ
—
Max
930
Unit
MHz
dBm
RF tuning frequency range
Maximum TX Power1
POUTMAX
PAVDD connected directly to ex-
ternal 3.3V supply, 20 dBm output
power setting
19.8
23.3
PAVDD connected to DC-DC out-
put, 14 dBm output power setting
12.6
14.2
16.1
dBm
Minimum active TX Power
Output power step size
POUTMIN
—
—
—
-45.5
0.5
—
—
—
dBm
dB
POUTSTEP
POUTVAR_V
output power > 0 dBm
Output power variation vs
supply at POUTMAX
1.8 V < VVREGVDD < 3.3 V,
PAVDD connected to external
supply
4.8
dB
1.8 V < VVREGVDD < 3.3 V,
PAVDD connected to DC-DC out-
put
—
1.9
—
dB
Output power variation vs
temperature, peak to peak
POUTVAR_T
-40 to +85C with PAVDD connec-
ted to external supply
—
—
—
—
—
—
0.6
0.7
0.2
0.3
-45
-26
1.3
1.4
0.6
0.6
-42
-20
dB
dB
-40 to +85C with PAVDD connec-
ted to DC-DC output
Output power variation vs RF POUTVAR_F
frequency
PAVDD connected to external
supply
dB
PAVDD connected to DC-DC out-
put
dB
Spurious emissions of har-
monics at 20 dBm output
power, Conducted measure-
ment, 20dBm match, PAVDD
= 3.3V, Test Frequency =
915 MHz
SPURHARM_FCC In restricted bands, per FCC Part
dBm
dBc
15.205 / 15.209
_20
In non-restricted bands, per FCC
Part 15.231
Spurious emissions out-of-
band at 20 dBm output pow-
er, Conducted measurement,
20dBm match, PAVDD =
3.3V, Test Frequency = 915
MHz
SPUROOB_FCC_ In non-restricted bands, per FCC
—
—
—
—
-26
-52
-61
-58
-20
-46
-56
-52
dBc
dBm
dBm
dBm
Part 15.231
20
In restricted bands (30-88 MHz),
per FCC Part 15.205 / 15.209
In restricted bands (88-216 MHz),
per FCC Part 15.205 / 15.209
In restricted bands (216-960
MHz), per FCC Part 15.205 /
15.209
In restricted bands (>960 MHz),
per FCC Part 15.205 / 15.209
—
-47
-42
dBm
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Rev. 1.0 | 44
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Spurious emissions of har-
monics at 14 dBm output
SPURHARM_FCC In restricted bands, per FCC Part
—
-47
-42
dBm
15.205 / 15.209
_14
power, Conducted measure-
ment, 14dBm match, PAVDD
connected to DC-DC output,
Test Frequency = 915 MHz
In non-restricted bands, per FCC
Part 15.231
—
-26
-20
dBc
Spurious emissions out-of-
band at 14 dBm output pow-
er, Conducted measurement,
14dBm match, PAVDD con-
nected to DC-DC output,
SPUROOB_FCC_ In non-restricted bands, per FCC
—
—
—
—
-26
-52
-61
-58
-20
-46
-56
-52
dBc
dBm
dBm
dBm
Part 15.231
14
In restricted bands (30-88 MHz),
per FCC Part 15.205 / 15.209
Test Frequency = 915 MHz
In restricted bands (88-216 MHz),
per FCC Part 15.205 / 15.209
In restricted bands (216-960
MHz), per FCC Part 15.205 /
15.209
In restricted bands (>960 MHz),
per FCC Part 15.205 / 15.209
—
—
-45
1.0
-42
2.8
dBm
Error vector magnitude (off- EVM
set EVM), per 802.15.4-2011
Signal is DSSS-OQPSK reference
packet. Modulated according to
802.15.4-2011 DSSS-OQPSK in
the 915MHz band, with pseudo-
random packet data content.
PAVDD connected to external
3.3V supply.
%rms
Power spectral density limit
PSD
Relative, at carrier ± 1.2 MHz.
Average spectral power shall be
measured using a 100kHz resolu-
tion bandwidth. The reference lev-
el shall be the highest average
spectral power measured within ±
600kHz of the carrier frequency.
PAVDD connected to external
3.3V supply.
—
-37.1
-24.8
dBc/
100kHz
Absolute, at carrier ± 1.2 MHz.
Average spectral power shall be
measured using a 100kHz resolu-
tion bandwidth. PAVDD connec-
ted to external 3.3V supply.
—
-24.2
-20
dBm/
100kHz
Note:
1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices cov-
ered in this datasheet can be found in the Max TX Power column of the Ordering Information Table. .
silabs.com | Building a more connected world.
Rev. 1.0 | 45
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
4.1.10.2 Sub-GHz RF Receiver Characteristics for 915 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 915 MHz.
Table 4.21. Sub-GHz RF Receiver Characteristics for 915 MHz Band
Parameter
Symbol
Test Condition
Min
902
—
Typ
—
Max
930
—
Unit
MHz
dBm
Tuning frequency range
FRANGE
Max usable input level, 0.1% SAT500K
BER
Desired is reference 500 kbps
GFSK signal4
10
Sensitivity
SENS
Desired is reference 4.8 kbps
OOK signal3, 20% PER
—
—
—
—
—
—
—
—
—
-105.2
-126.2
-108.2
-105.1
-98.2
-95.2
-28.1
-50
-100.7
—
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dB
Desired is reference 600 bps
GFSK signal6, 0.1% BER
Desired is reference 50 kbps
GFSK signal5, 0.1% BER
-104.2
-101.5
-93.2
-91
Desired is reference 100 kbps
GFSK signal1, 0.1% BER
Desired is reference 500 kbps
GFSK signal4, 0.1% BER
Desired is reference 400 kbps
GFSK signal2, 1% PER
Level above which
RFSENSE will trigger7
RFSENSETRIG
CW at 915 MHz
—
Level below which
RFSENSE will not trigger7
RFSENSETHRES CW at 915 MHz
—
Desired is 4.8 kbps OOK signal3
at 3dB above sensitivity level,
20% PER
Adjacent channel selectivity, C/I1
Interferer is CW at ± 1 ×
channel-spacing
48.1
—
Desired is 600 bps GFSK signal6
at 3dB above sensitivity level,
0.1% BER
—
—
—
—
—
71.4
49.8
51.1
48.1
41.4
—
—
—
—
—
dB
dB
dB
dB
dB
Desired is 50 kbps GFSK signal5
at 3dB above sensitivity level,
0.1% BER
Desired is 100 kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
Desired is 500 kbps GFSK signal4
at 3dB above sensitivity level,
0.1% BER
Desired is 400 kbps 4GFSK sig-
nal2 at 3dB above sensitivity level,
0.1% BER
silabs.com | Building a more connected world.
Rev. 1.0 | 46
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Desired is 4.8 kbps OOK signal3
at 3dB above sensitivity level,
20% PER
Alternate channel selectivity, C/I2
Interferer is CW at ± 2 ×
channel-spacing
—
56.3
—
dB
Desired is 600 bps GFSK signal6
at 3dB above sensitivity level,
0.1% BER
—
—
—
—
—
—
—
—
—
—
74.7
55.8
56.4
51.8
46.8
48.4
54.9
49.1
47.9
42.8
—
—
—
—
—
—
—
—
—
—
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Desired is 50 kbps GFSK signal5
at 3dB above sensitivity level,
0.1% BER
Desired is 100 kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
Desired is 500 kbps GFSK signal4
at 3dB above sensitivity level,
0.1% BER
Desired is 400 kbps 4GFSK sig-
nal2 at 3dB above sensitivity level,
0.1% BER
Desired is 4.8 kbps OOK signal3
at 3dB above sensitivity level,
20% PER
Image rejection, Interferer is C/IIMAGE
CW at image frequency
Desired is 50 kbps GFSK signal5
at 3dB above sensitivity level,
0.1% BER
Desired is 100 kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
Desired is 500 kbps GFSK signal4
at 3dB above sensitivity level,
0.1% BER
Desired is 400 kbps 4GFSK sig-
nal2 at 3dB above sensitivity level,
0.1% BER
Blocking selectivity, 0.1%
BER. Desired is 100 kbps
GFSK signal at 3dB above
sensitivity level
C/IBLOCKER
Interferer CW at Desired ± 1 MHz
Interferer CW at Desired ± 2 MHz
—
—
—
58.7
62.5
76.4
—
—
—
dB
dB
dB
Interferer CW at Desired ± 10
MHz
Desired is 100 kbps GFSK signal1
at 3dB above sensitivity level
Intermod selectivity, 0.1%
BER. CW interferers at 400
kHz and 800 kHz offsets
C/IIM
—
—
45
—
—
5
dB
Upper limit of input power
range over which RSSI reso-
lution is maintained
RSSIMAX
RSSIMIN
RSSIRES
dBm
dBm
dBm
Lower limit of input power
range over which RSSI reso-
lution is maintained
-98
—
—
—
—
RSSI resolution
Over RSSIMIN to RSSIMAX range
0.25
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Rev. 1.0 | 47
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
216-960 MHz
Min
—
Typ
-55
-47
Max
-49.2
-41.2
Unit
dBm
dBm
Max spurious emissions dur- SPURRX_FCC
ing active receive mode, per
FCC Part 15.109(a)
Above 960 MHz
—
Max spurious emissions dur- SPURRX_ARIB
ing active receive mode,per
ARIB STD-T108 Section 3.3
Below 710 MHz, RBW=100kHz
710-900 MHz, RBW=1MHz
900-915 MHz, RBW=100kHz
915-930 MHz, RBW=100kHz
930-1000 MHz, RBW=100kHz
Above 1000 MHz, RBW=1MHz
—
—
—
—
—
—
-60
-61
-61
-61
-60
-53
-54
-55
-55
-55
-54
-47
dBm
dBm
dBm
dBm
dBm
dBm
Note:
1. Definition of reference signal is 100 kbps 2GFSK, BT=0.5, Δf = 50 kHz, RX channel BW = 198.024 kHz, channel spacing = 400
kHz.
2. Definition of reference signal is 400 kbps 4GFSK, BT=0.5, inner deviation = 33.3 kHz, RX channel BW = 368.920 kHz, channel
spacing = 600 kHz.
3. Definition of reference signal is 4.8 kbps OOK, RX channel BW = 306.036 kHz, channel spacing = 500 kHz.
4. Definition of reference signal is 500 kbps 2GFSK, BT=0.5, Δf = 175 kHz, RX channel BW = 835.076 kHz, channel spacing = 1
MHz.
5. Definition of reference signal is 50 kbps 2GFSK, BT=0.5, Δf = 25 kHz, RX channel BW = 99.012 kHz, channel spacing = 200 kHz.
6. Definition of reference signal is 600 bps 2GFSK, BT=0.5, Δf = 0.3 kHz, RX channel BW = 1.2 kHz, channel spacing = 300 kHz.
7. RFSENSE performance is only valid from 0 to 85 °C. RFSENSE should be disabled outside this temperature range.
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Rev. 1.0 | 48
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
4.1.10.3 Sub-GHz RF Transmitter characteristics for 868 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 868 MHz.
Table 4.22. Sub-GHz RF Transmitter characteristics for 868 MHz Band
Parameter
Symbol
FRANGE
Test Condition
Min
863
17.1
Typ
—
Max
876
Unit
MHz
dBm
RF tuning frequency range
Maximum TX Power1
POUTMAX
PAVDD connected directly to ex-
ternal 3.3V supply, 20 dBm output
power setting
19.3
22.9
PAVDD connected to DC-DC out-
put, 14 dBm output power setting
11.4
13.7
16.5
dBm
Minimum active TX Power
Output power step size
POUTMIN
—
—
—
-43.5
0.5
5
—
—
—
dBm
dB
POUTSTEP
output power > 0 dBm
Output power variation vs
supply at POUTMAX
POUTVAR_V_NO 1.8 V < VVREGVDD < 3.3 V,
dB
PAVDD connected to external
supply
DCDC
1.8 V < VVREGVDD < 3.3 V,
PAVDD connected to DC-DC out-
put
—
2
—
dB
Output power variation vs
temperature, peak to peak
POUTVAR_T
-40 to +85C with PAVDD connec-
ted to external supply
—
—
—
—
—
0.6
0.5
0.2
0.2
-35
0.9
1.2
0.6
0.8
-30
dB
dB
-40 to +85C with PAVDD connec-
ted to DC-DC output
Output power variation vs RF POUTVAR_F_NO PAVDD connected to external
frequency
dB
supply
DCDC
PAVDD connected to DC-DC out-
put
dB
Spurious emissions of har-
monics, Conducted meas-
urement, PAVDD connected
to DC-DC output
SPURHARM_ETSI Per ETSI EN 300-220, Section
7.8.2.1
dBm
Spurious emissions out-of-
band, Conducted measure-
ment, PAVDD connected to
DC-DC output
SPUROOB_ETSI Per ETSI EN 300-220, Section
7.8.2.1 (47-74 MHz, 87.5-118
MHz, 174-230 MHz, and 470-862
MHz)
—
-59
-54
dBm
Per ETSI EN 300-220, Section
7.8.2.1 (other frequencies below 1
GHz)
—
—
—
-60
-36
5.7
-36
-30
—
dBm
dBm
Per ETSI EN 300-220, Section
7.8.2.1 (frequencies above 1
GHz)
Error vector magnitude (off- EVM
set EVM), per 802.15.4-2015
Signal is DSSS-BPSK reference
packet. Modulated according to
802.15.4-2015 DSSS-BPSK in the
868MHz band, with pseudo-ran-
dom packet data content. PAVDD
connected to external 3.3V supply
%rms
silabs.com | Building a more connected world.
Rev. 1.0 | 49
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
Parameter
Note:
Symbol
Test Condition
Min
Typ
Max
Unit
1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices cov-
ered in this datasheet can be found in the Max TX Power column of the Ordering Information Table. .
silabs.com | Building a more connected world.
Rev. 1.0 | 50
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
4.1.10.4 Sub-GHz RF Receiver Characteristics for 868 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 868 MHz.
Table 4.23. Sub-GHz RF Receiver Characteristics for 868 MHz Band
Parameter
Symbol
Test Condition
Min
863
—
Typ
—
Max
876
—
Unit
MHz
dBm
Tuning frequency range
FRANGE
Max usable input level, 0.1% SAT2k4
BER
Desired is reference 2.4 kbps
GFSK signal1
10
Max usable input level, 0.1% SAT38k4
BER
Desired is reference 38.4 kbps
GFSK signal2
—
—
10
—
—
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dB
Sensitivity
SENS
Desired is reference 2.4 kbps
GFSK signal1, 0.1% BER
-120.6
-109.5
-96.4
-110.6
-28.1
-50
Desired is reference 38.4 kbps
GFSK signal2, 0.1% BER
—
-105.4
—
Desired is reference 500 kbps
GFSK signal3, 0.1% BER
—
Desired is reference BPSK sig-
nal4, 1% PER
—
—
Level above which
RFSENSE will trigger5
RFSENSETRIG
CW at 868 MHz
—
—
Level below which
RFSENSE will not trigger5
RFSENSETHRES CW at 868 MHz
—
—
Desired is 2.4 kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
Adjacent channel selectivity, C/I1
Interferer is CW at ± 1 ×
channel-spacing
44.5
56.9
—
Desired is 38.4kbps GFSK signal2
at 3dB above sensitivity level,
0.1% BER
35.4
—
43
—
—
—
—
—
dB
dB
dB
dB
dB
Desired is 2.4kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
Alternate channel selectivity, C/I2
Interferer is CW at ± 2 ×
channel-spacing
56.8
48.2
50.2
48.7
Desired is 38.4kbps GFSK signal2
at 3dB above sensitivity level,
0.1% BER
—
Desired is 2.4kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
Image rejection, Interferer is C/IIMAGE
CW at image frequency
—
Desired is 38.4kbps GFSK signal2
at 3dB above sensitivity level,
0.1% BER
—
Blocking selectivity, 0.1%
BER. Desired is 2.4 kbps
GFSK signal1 at 3 dB above
sensitivity level
C/IBLOCKER
Interferer CW at Desired ± 1 MHz
Interferer CW at Desired ± 2 MHz
—
—
—
72.1
77.5
90.4
—
—
—
dB
dB
dB
Interferer CW at Desired ± 10
MHz
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Rev. 1.0 | 51
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Upper limit of input power
range over which RSSI reso-
lution is maintained
RSSIMAX
—
—
5
dBm
Lower limit of input power
range over which RSSI reso-
lution is maintained
RSSIMIN
RSSIRES
-98
—
—
dBm
RSSI resolution
Over RSSIMIN to RSSIMAX range
30 MHz to 1 GHz
—
—
—
0.25
-63
—
dBm
dBm
dBm
Max spurious emissions dur- SPURRX
ing active receive mode
-57
-47
1 GHz to 12 GHz
-53
Note:
1. Definition of reference signal is 2.4 kbps 2GFSK, BT=0.5, Δf = 1.2 kHz, RX channel BW = 4.797 kHz, channel spacing = 12.5
kHz.
2. Definition of reference signal is 38.4 kbps 2GFSK, BT=0.5, Δf = 20 kHz, RX channel BW = 74.809 kHz, channel spacing = 100
kHz.
3. Definition of reference signal is 500 kbps 2GFSK, BT=0.5, Δf = 125 kHz, RX channel BW = 753.320 kHz.
4. Definition of reference signal is 20 kbps BPSK
5. RFSENSE performance is only valid from 0 to 85 °C. RFSENSE should be disabled outside this temperature range.
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
4.1.10.5 Sub-GHz RF Transmitter characteristics for 490 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 490 MHz.
Table 4.24. Sub-GHz RF Transmitter characteristics for 490 MHz Band
Parameter
Symbol
FRANGE
Test Condition
Min
470
18.1
Typ
—
Max
510
Unit
MHz
dBm
RF tuning frequency range
Maximum TX Power1
POUTMAX
PAVDD connected directly to ex-
ternal 3.3V supply
20.3
23.7
Minimum active TX Power
Output power step size
POUTMIN
-44.9
0.5
—
—
—
dBm
dB
POUTSTEP
POUTVAR_V
output power > 0 dBm
—
—
Output power variation vs
supply, peak to peak
at 20 dBm;1.8 V < VVREGVDD
3.3 V, PAVDD connected directly
to external supply
<
4.3
dB
Output power variation vs
temperature, peak to peak
POUTVAR_T
-40 to +85C at 20 dBm
—
—
—
0.2
0.2
-40
0.9
0.4
-36
dB
dB
Output power variation vs RF POUTVAR_F
frequency
Harmonic emissions, 20
dBm output power setting,
490 MHz
SPURHARM_CN Per China SRW Requirement,
Section 2.1, frequencies below
1GHz
dBm
Per China SRW Requirement,
Section 2.1, frequencies above
1GHz
—
—
-36
-54
-30
—
dBm
dBm
Spurious emissions, 20 dBm SPUROOB_CN
Per China SRW Requirement,
Section 3 (48.5-72.5MHz,
output power setting, 490
MHz
76-108MHz, 167-223MHz,
470-556MHz, and 606-798MHz)
Per China SRW Requirement,
Section 2.1 (other frequencies be-
low 1GHz)
—
—
-42
-36
—
—
dBm
dBm
Per China SRW Requirement,
Section 2.1 (frequencies above
1GHz)
Note:
1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices cov-
ered in this datasheet can be found in the Max TX Power column of the Ordering Information Table. .
silabs.com | Building a more connected world.
Rev. 1.0 | 53
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
4.1.10.6 Sub-GHz RF Receiver Characteristics for 490 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 490 MHz.
Table 4.25. Sub-GHz RF Receiver Characteristics for 490 MHz Band
Parameter
Symbol
Test Condition
Min
470
—
Typ
—
Max
510
—
Unit
dBm
dBm
Tuning frequency range
FRANGE
Max usable input level, 0.1% SAT2k4
BER
Desired is reference 2.4 kbps
GFSK signal3
10
Max usable input level, 0.1% SAT38k4
BER
Desired is reference 38.4 kbps
GFSK signal4
—
—
—
—
—
—
—
48
10
—
—
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dB
Sensitivity
SENS
Desired is reference 2.4 kbps
GFSK signal3, 0.1% BER
-122.2
-111.4
-116.8
-107.3
-28.1
-50
Desired is reference 38.4 kbps
GFSK signal4, 0.1% BER
-108.9
-113.9
-104.7
—
Desired is reference 10 kbps
GFSK signal2, 0.1% BER
Desired is reference 100 kbps
GFSK signal1, 0.1% BER
Level above which
RFSENSE will trigger5
RFSENSETRIG
CW at 490 MHz
Level below which
RFSENSE will not trigger5
RFSENSETHRES CW at 490 MHz
—
Desired is 2.4 kbps GFSK signal3
at 3dB above sensitivity level,
0.1% BER
Adjacent channel selectivity, C/I1
Interferer is CW at ± 1 ×
channel-spacing
60.3
—
Desired is 38.4kbps GFSK signal4
at 3dB above sensitivity level,
0.1% BER
38.3
—
45.6
60.4
52.6
56.5
54.1
—
—
—
—
—
dB
dB
dB
dB
dB
Desired is 2.4kbps GFSK signal3
at 3dB above sensitivity level,
0.1% BER
Alternate channel selectivity, C/I2
Interferer is CW at ± 2 ×
channel-spacing
Desired is 38.4kbps GFSK signal4
at 3dB above sensitivity level,
0.1% BER
—
Desired is 2.4kbps GFSK signal3
at 3dB above sensitivity level,
0.1% BER
Image rejection, Interferer is C/IIMAGE
CW at image frequency
—
Desired is 38.4kbps GFSK signal4
at 3dB above sensitivity level,
0.1% BER
—
Blocking selectivity, 0.1%
BER. Desired is 2.4 kbps
GFSK signal3 at 3 dB above
sensitivity level
C/IBLOCKER
Interferer CW at Desired ± 1 MHz
Interferer CW at Desired ± 2 MHz
—
—
—
73.9
75.4
90.2
—
—
—
dB
dB
dB
Interferer CW at Desired ± 10
MHz
silabs.com | Building a more connected world.
Rev. 1.0 | 54
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Upper limit of input power
range over which RSSI reso-
lution is maintained
RSSIMAX
—
—
5
dBm
Lower limit of input power
range over which RSSI reso-
lution is maintained
RSSIMIN
RSSIRES
-98
—
—
dBm
RSSI resolution
Over RSSIMIN to RSSIMAX range
30 MHz to 1 GHz
—
—
—
0.25
-53
—
dBm
dBm
dBm
Max spurious emissions dur- SPURRX
ing active receive mode
-47
-47
1 GHz to 12 GHz
-53
Note:
1. Definition of reference signal is 100 kbps 2GFSK, BT=0.5, Δf = 50 kHz, RX channel BW = 198.024 kHz.
2. Definition of reference signal is 10 kbps 2GFSK, BT=0.5, Δf = 5 kHz, RX channel BW = 21.038 kHz.
3. Definition of reference signal is 2.4 kbps 2GFSK, BT=0.5, Δf = 1.2 kHz, RX channel BW = 4.798 kHz, channel spacing = 12.5
kHz.
4. Definition of reference signal is 38.4 kbps 2GFSK, BT=0.5, Δf = 20 kHz, RX channel BW = 74.809 kHz, channel spacing = 100
kHz.
5. RFSENSE performance is only valid from 0 to 85 °C. RFSENSE should be disabled outside this temperature range.
silabs.com | Building a more connected world.
Rev. 1.0 | 55
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
4.1.10.7 Sub-GHz RF Transmitter characteristics for 433 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 433 MHz.
Table 4.26. Sub-GHz RF Transmitter characteristics for 433 MHz Band
Parameter
Symbol
FRANGE
Test Condition
Min
426
12.5
Typ
—
Max
445
Unit
MHz
dBm
RF tuning frequency range
Maximum TX Power1
POUTMAX
PAVDD connected to DCDC out-
put, 14dBm output power
15.1
17.4
PAVDD connected to DCDC out-
put, 10dBm output power
8.3
10.6
13.3
dBm
Minimum active TX Power
Output power step size
POTMIN
—
—
—
-42
0.5
1.7
—
—
—
dBm
dB
POUTSTEP
POUTVAR_V
output power > 0 dBm
Output power variation vs
supply, peak to peak, Pout =
10dBm
At 10 dBm;1.8 V < VVREGVDD
3.3 V, PAVDD = DC-DC output
<
dB
Output power variation vs
temperature, peak to peak,
Pout= 10dBm
POUTVAR_T
-40 to +85C at 10dBm
—
0.5
1.2
dB
Output power variation vs RF POUTVAR_F
frequency, Pout = 10dBm
—
—
—
0.1
-47
-26
0.2
-42
-20
dB
Spurious emissions of har-
monics FCC, Conducted
measurement, 14dBm
match, PAVDD connected to
DCDC output, Test Frequen-
cy = 434 MHz
SPURHARM_FCC In restricted bands, per FCC Part
15.205 / 15.209
dBm
dBc
In non-restricted bands, per FCC
Part 15.231
Spurious emissions out-of-
band FCC, Conducted
measurement, 14dBm
match, PAVDD connected to
DCDC output, Test Frequen-
cy = 434 MHz
SPUROOB_FCC
In non-restricted bands, per FCC
Part 15.231
—
—
—
—
-26
-52
-61
-58
-20
-46
-56
-52
dBc
dBm
dBm
dBm
In restricted bands (30-88 MHz),
per FCC Part 15.205 / 15.209
In restricted bands (88-216 MHz),
per FCC Part 15.205 / 15.209
In restricted bands (216-960
MHz), per FCC Part 15.205 /
15.209
In restricted bands (>960 MHz),
per FCC Part 15.205 / 15.209
—
—
—
-47
-42
-36
-42
-36
-30
dBm
dBm
dBm
Spurious emissions of har-
monics ETSI, Conducted
measurement, 14dBm
match, PAVDD connected to
DCDC output, Test Frequen-
cy = 434 MHz
SPURHARM_ETSI Per ETSI EN 300-220, Section
7.8.2.1 (frequencies below 1Ghz)
Per ETSI EN 300-220, Section
7.8.2.1 (frequencies above 1Ghz)
silabs.com | Building a more connected world.
Rev. 1.0 | 56
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Spurious emissions out-of-
band ETSI, Conducted
measurement, 14dBm
match, PAVDD connected to
DCDC output, Test Frequen-
cy = 434 MHz
SPUROOB_ETSI Per ETSI EN 300-220, Section
7.8.2.1 (47-74 MHz, 87.5-118
MHz, 174-230 MHz, and 470-862
MHz)
—
-60
-54
dBm
Per ETSI EN 300-220, Section
7.8.2.1 (other frequencies below 1
GHz)
—
—
-42
-36
-36
-30
dBm
dBm
Per ETSI EN 300-220, Section
7.8.2.1 (frequencies above 1
GHz)
Note:
1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices cov-
ered in this datasheet can be found in the Max TX Power column of the Ordering Information Table. .
silabs.com | Building a more connected world.
Rev. 1.0 | 57
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
4.1.10.8 Sub-GHz RF Receiver Characteristics for 433 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 433 MHz.
Table 4.27. Sub-GHz RF Receiver Characteristics for 433 MHz Band
Parameter
Symbol
Test Condition
Min
426
—
Typ
—
Max
445
—
Unit
MHz
dBm
Tuning frequency range
FRANGE
Max usable input level, 0.1% SAT2k4
BER
Desired is reference 2.4 kbps
GFSK signal2
10
Max usable input level, 0.1% SAT50k
BER
Desired is reference 50 kbps
GFSK signal4
—
—
—
—
—
—
—
—
—
10
—
—
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dB
Sensitivity
SENS
Desired is reference 4.8 kbps
OOK signal3, 20% PER
-107.4
-107.3
-110.3
-123.1
-112.6
-28.1
-50
Desired is reference 100 kbps
GFSK signal1, 0.1% BER
-105
-107.2
—
Desired is reference 50 kbps
GFSK signal4, 0.1% BER
Desired is reference 2.4 kbps
GFSK signal2, 0.1% BER
Desired is reference 9.6 kbps
GFSK signal5, 1% PER
-109
—
Level above which
RFSENSE will trigger6
RFSENSETRIG
CW at 433 MHz
Level below which
RFSENSE will not trigger6
RFSENSETHRES CW at 433 MHz
—
Desired is 4.8 kbps OOK signal3
at 3dB above sensitivity level,
20% PER
Adjacent channel selectivity, C/I1
Interferer is CW at ± 1 ×
channel-spacing
51.6
—
Desired is 100 kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
35
47
44.1
61.5
53.1
35.7
—
—
—
—
dB
dB
dB
dB
Desired is 2.4 kbps GFSK signal2
at 3dB above sensitivity level,
0.1% BER
Desired is 50 kbps GFSK signal4
at 3dB above sensitivity level,
0.1% BER
45.6
—
Desired is 9.6 kbps 4GFSK sig-
nal5 at 3dB above sensitivity level,
1% PER
silabs.com | Building a more connected world.
Rev. 1.0 | 58
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Desired is 4.8 kbps OOK signal3
at 3dB above sensitivity level,
20% PER
Alternate channel selectivity, C/I2
Interferer is CW at ± 2 ×
channel-spacing
—
57.8
—
dB
Desired is 100 kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
—
—
—
—
—
—
—
—
—
54.6
62.4
58.1
50.6
46.5
51.7
57.5
54.4
48
—
—
—
—
—
—
—
—
—
dB
dB
dB
dB
dB
dB
dB
dB
dB
Desired is 2.4 kbps GFSK signal2
at 3dB above sensitivity level,
0.1% BER
Desired is 50 kbps GFSK signal4
at 3dB above sensitivity level,
0.1% BER
Desired is 9.6 kbps 4GFSK sig-
nal5 at 3dB above sensitivity level,
1% PER
Desired is 4.8 kbps OOK signal3
at 3dB above sensitivity level,
20% PER
Image rejection, Interferer is C/IIMAGE
CW at image frequency
Desired is 100 kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
Desired is 2.4 kbps GFSK signal2
at 3dB above sensitivity level,
0.1% BER
Desired is 50 kbps GFSK signal4
at 3dB above sensitivity level,
0.1% BER
Desired is 9.6 kbps 4GFSK sig-
nal5 at 3dB above sensitivity level,
1% PER
Blocking selectivity, 0.1%
BER. Desired is 2.4 kbps
GFSK signal2 at 3dB above
sensitivity level
C/IBLOCKER
Interferer CW at Desired ± 1 MHz
Interferer CW at Desired ± 2 MHz
—
—
—
75.7
77.2
92
—
—
—
dB
dB
dB
Interferer CW at Desired ± 10
MHz
Desired is 2.4 kbps GFSK signal2
at 3dB above sensitivity level
Intermod selectivity, 0.1%
BER. CW interferers at 12.5
kHz and 25 kHz offsets
C/IIM
—
—
58.8
—
—
5
dB
Upper limit of input power
range over which RSSI reso-
lution is maintained
RSSIMAX
RSSIMIN
RSSIRES
dBm
dBm
Lower limit of input power
range over which RSSI reso-
lution is maintained
-98
—
—
RSSI resolution
Over RSSIMIN to RSSIMAX range
216-960 MHz
—
—
—
0.25
-55
—
dBm
dBm
dBm
Max spurious emissions dur- SPURRX_FCC
ing active receive mode, per
FCC Part 15.109(a)
-49
-41
Above 960 MHz
-47
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Below 1000 MHz
Above 1000 MHz
Min
—
Typ
-63
-53
Max
-57
Unit
dBm
dBm
Max spurious emissions dur- SPURRX_ETSI
ing active receive mode, per
ETSI 300-220 Section 8.6
—
-47
Max spurious emissions dur- SPURRX_ARIB
ing active receive mode, per
ARIB STD T67 Section
Below 710 MHz, RBW=100kHz
—
-60
-54
dBm
3.3(5)
Note:
1. Definition of reference signal is 100 kbps 2GFSK, BT=0.5, Δf = 50 kHz, RX channel BW = 198.024 kHz, channel spacing = 200
kHz.
2. Definition of reference signal is 2.4 kbps 2GFSK, BT=0.5, Δf = 1.2 kHz, RX channel BW = 4.798 kHz, channel spacing = 12.5
kHz.
3. Definition of reference signal is 4.8 kbps OOK, RX channel BW = 306.036 kHz, channel spacing = 500 kHz.
4. Definition of reference signal is 50 kbps 2GFSK, BT=0.5, Δf = 25 kHz, RX channel BW = 99.012 kHz, channel spacing = 200 kHz.
5. Definition of reference signal is 9.6 kbps 4GFSK, BT=0.5, inner deviation = 0.8 kHz, RX channel BW = 8.5 kHz, channel spacing
= 12.5 kHz.
6. RFSENSE performance is only valid from 0 to 85 °C. RFSENSE should be disabled outside this temperature range.
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
4.1.10.9 Sub-GHz RF Transmitter characteristics for 315 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 315 MHz.
Table 4.28. Sub-GHz RF Transmitter characteristics for 315 MHz Band
Parameter
Symbol
FRANGE
Test Condition
Min
195
13.8
Typ
—
Max
358
Unit
MHz
dBm
RF tuning frequency range
Maximum TX Power1
POUTMAX
PAVDD connected to DC-DC out-
put
17.2
21.1
Minimum active TX Power
Output power step size
POUTMIN
-43.9
0.5
—
—
—
dBm
dB
POUTSTEP
POUTVAR_V
output power > 0 dBm
—
—
Output power variation vs
supply
1.8 V < VVREGVDD < 3.3 V,
PAVDD = DC-DC output
1.8
dB
Output power variation vs
temperature
POUTVAR_T
—
—
—
—
0.5
0.1
-47
-26
1.2
0.7
-42
-20
dB
dB
Output power variation vs RF POUTVAR_F
frequency
Spurious emissions of har-
monics at 14 dBm output
power, Conducted measure-
ment, 14dBm match, PAVDD
connected to DC-DC output,
Test Frequency = 315 MHz
SPURHARM_FCC In restricted bands, per FCC Part
15.205 / 15.209
dBm
dBc
In non-restricted bands, per FCC
Part 15.231
Spurious emissions out-of-
band at 14 dBm output pow-
er, Conducted measurement,
14dBm match, PAVDD con-
nected to DC-DC output,
SPUROOB_FCC
In non-restricted bands, per FCC
Part 15.231
—
—
—
—
-26
-52
-61
-58
-20
-46
-56
-52
dBc
dBm
dBm
dBm
In restricted bands (30-88 MHz),
per FCC Part 15.205 / 15.209
Test Frequency = 315 MHz
In restricted bands (88-216 MHz),
per FCC Part 15.205 / 15.209
In restricted bands (216-960
MHz), per FCC Part 15.205 /
15.209
In restricted bands (>960 MHz),
per FCC Part 15.205 / 15.209
—
-47
-42
dBm
Note:
1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices cov-
ered in this datasheet can be found in the Max TX Power column of the Ordering Information Table. .
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
4.1.10.10 Sub-GHz RF Receiver Characteristics for 315 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 315 MHz.
Table 4.29. Sub-GHz RF Receiver Characteristics for 315 MHz Band
Parameter
Symbol
Test Condition
Min
195
—
Typ
—
Max
358
—
Unit
dBm
dBm
Tuning frequency range
FRANGE
Max usable input level, 0.1% SAT2k4
BER
Desired is reference 2.4 kbps
GFSK signal1
10
Max usable input level, 0.1% SAT38k4
BER
Desired is reference 38.4 kbps
GFSK signal2
—
—
10
—
-120.7
-108.6
-95.5
—
dBm
dBm
dBm
dBm
dBm
dBm
dB
Sensitivity
SENS
Desired is reference 2.4 kbps
GFSK signal1, 0.1% BER
-123.2
-111.4
-98.8
-28.1
-50
Desired is reference 38.4 kbps
GFSK signal2, 0.1% BER
—
Desired is reference 500 kbps
GFSK signal3, 0.1% BER
—
Level above which
RFSENSE will trigger4
RFSENSETRIG
CW at 315 MHz
—
Level below which
RFSENSE will not trigger4
RFSENSETHRES CW at 315 MHz
—
—
Desired is 2.4 kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
Adjacent channel selectivity, C/I1
Interferer is CW at ± 1 ×
channel-spacing
54.1
63.6
—
Desired is 38.4kbps GFSK signal2
at 3dB above sensitivity level,
0.1% BER
—
—
—
49.9
64.2
56.2
—
—
—
dB
dB
dB
Desired is 2.4kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
Alternate channel selectivity, C/I2
Interferer is CW at ± 2 ×
channel-spacing
Desired is 38.4kbps GFSK signal2
at 3dB above sensitivity level2,
0.1% BER
Desired is 2.4kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
Image rejection, Interferer is C/IIMAGE
CW at image frequency
—
—
53
—
—
dB
dB
Desired is 38.4kbps GFSK signal2
at 3dB above sensitivity level,
0.1% BER
51.4
Blocking selectivity, 0.1%
BER. Desired is 2.4 kbps
GFSK signal1 at 3 dB above
sensitivity level
C/IBLOCKER
Interferer CW at Desired ± 1 MHz
Interferer CW at Desired ± 2 MHz
—
—
75
—
—
—
dB
dB
dB
76.5
91.9
Interferer CW at Desired ± 10
MHz
72.6
Upper limit of input power
range over which RSSI reso-
lution is maintained
RSSIMAX
—
—
5
dBm
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Lower limit of input power
range over which RSSI reso-
lution is maintained
RSSIMIN
-98
—
—
dBm
RSSI resolution
RSSIRES
Over RSSIMIN to RSSIMAX range
216-960 MHz
—
—
—
0.25
-63
—
dBm
dBm
dBm
Max spurious emissions dur- SPURRX_FCC
ing active receive mode, per
FCC Part 15.109(a)
-57
-47
Above 960MHz
-53
Note:
1. Definition of reference signal is 2.4 kbps 2GFSK, BT=0.5, Δf = 1.2 kHz, RX channel BW = 4.798 kHz, channel spacing = 12.5
kHz.
2. Definition of reference signal is 38.4 kbps 2GFSK, BT=0.5, Δf = 20 kHz, RX channel BW = 74.809 kHz, channel spacing = 100
kHz.
3. Definition of reference signal is 500 kbps 2GFSK, BT=0.5, Δf = 125 kHz, RX channel BW = 753.320 kHz.
4. RFSENSE performance is only valid from 0 to 85 °C. RFSENSE should be disabled outside this temperature range.
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
4.1.10.11 Sub-GHz RF Transmitter Characteristics for 169 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 169 MHz.
Table 4.30. Sub-GHz RF Transmitter Characteristics for 169 MHz Band
Parameter
Symbol
FRANGE
Test Condition
Min
169
18.1
Typ
—
Max
170
Unit
MHz
dBm
RF tuning frequency range
Maximum TX Power1
POUTMAX
PAVDD connected to external 3.3
V supply
19.7
22.4
Minimum active TX Power
Output power step size
POUTMIN
-42.6
0.5
—
—
dBm
dB
POUTSTEP
POUTVAR_V
output power > 0 dBm
—
—
Output power variation vs
supply, peak to peak
1.8 V < VVREGVDD < 3.3 V,
PAVDD connected to external
supply
4.8
5.0
dB
Output power variation vs
temperature, peak to peak
POUTVAR_T
-40 to +85C at 20dBm
—
—
0.6
-42
1.2
—
dB
Spurious emissions of har-
monics, Conducted meas-
urement, PAVDD = 3.3V
SPURHARM_ETSI Per ETSI EN 300-220, Section
7.8.2.1 (47-74 MHz, 87.5-118
MHz, 174-230 MHz, and 470-862
MHz)
dBm
Per ETSI EN 300-220, Section
7.8.2.1 (other frequencies below 1
GHz)2
—
—
—
-38
-36
-42
—
—
dBm
dBm
dBm
Per ETSI EN 300-220, Section
7.8.2.1 (frequencies above 1
GHz)2
Spurious emissions out-of-
band, Conducted measure-
ment, PAVDD = 3.3V
SPUROOB_ETSI Per ETSI EN 300-220, Section
7.8.2.1 (47-74 MHz, 87.5-118
MHz, 174-230 MHz, and 470-862
MHz)
-36
Per ETSI EN 300-220, Section
7.8.2.1 (other frequencies below 1
GHz)
—
—
-42
-36
-36
-30
dBm
dBm
Per ETSI EN 300-220, Section
7.8.2.1 (frequencies above 1
GHz)
Note:
1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices cov-
ered in this datasheet can be found in the Max TX Power column of the Ordering Information Table. .
2. Typical value marginally passes specification. Additional margin can be obtained by increasing the order of the harmonic filter.
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
4.1.10.12 Sub-GHz RF Receiver Characteristics for 169 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 169 MHz.
Table 4.31. Sub-GHz RF Receiver Characteristics for 169 MHz Band
Parameter
Symbol
Test Condition
Min
169
—
Typ
—
Max
170
—
Unit
dBm
dBm
Tuning frequency range
FRANGE
Max usable input level, 0.1% SAT2k4
BER
Desired is reference 2.4 kbps
GFSK signal1
10
Max usable input level, 0.1% SAT38k4
BER
Desired is reference 38.4 kbps
GFSK signal2
—
—
—
—
—
—
—
10
-124
-112.2
-99.2
-28.1
-50
—
—
dBm
dBm
dBm
dBm
dBm
dBm
dB
Sensitivity
SENS
Desired is reference 2.4 kbps
GFSK signal1, 0.1% BER
Desired is reference 38.4 kbps
GFSK signal2, 0.1% BER
-108
-96
—
Desired is reference 500 kbps
GFSK signal3, 0.1% BER
Level above which
RFSENSE will trigger4
RFSENSETRIG
CW at 169 MHz
Level below which
RFSENSE will not trigger4
RFSENSETHRES CW at 169 MHz
—
Desired is 2.4 kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
Adjacent channel selectivity, C/I1
Interferer is CW at ± 1 x
channel-spacing
64.8
—
Desired is 38.4kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
43.3
—
51.4
67.4
60.6
47.1
47.1
—
—
—
—
—
dB
dB
dB
dB
dB
Desired is 2.4kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
Alternate channel selectivity, C/I2
Interferer is CW at ± 2 x
channel-spacing
Desired is 38.4kbps GFSK signal2
at 3dB above sensitivity level,
0.1% BER
—
Desired is 2.4kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
Image rejection, Interferer is C/IIMAGE
CW at image frequency
—
Desired is 38.4kbps GFSK signal2
at 3dB above sensitivity level,
0.1% BER
—
Blocking selectivity, 0.1%
BER. Desired is 2.4 kbps
GFSK signal1 at 3 dB above
sensitivity level
C/IBLOCKER
Interferer CW at Desired ± 1 MHz
Interferer CW at Desired ± 2 MHz
—
—
80
73.4
75
—
—
—
dB
dB
dB
Interferer CW at Desired ± 10
MHz
90.1
Upper limit of input power
range over which RSSI reso-
lution is maintained
RSSIMAX
—
—
5
dBm
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Lower limit of input power
range over which RSSI reso-
lution is maintained
RSSIMIN
-98
—
—
dBm
RSSI resolution
RSSIRES
Over RSSIMIN to RSSIMAX range
30 MHz to 1 GHz
—
—
—
0.25
-63
—
dBm
dBm
dBm
Max spurious emissions dur- SPURRX
ing active receive mode
-57
-47
1 GHz to 12 GHz
-53
Note:
1. Definition of reference signal is 2.4 kbps 2GFSK, BT=0.5, Δf = 1.2 kHz, RX channel BW = 4.798 kHz, channel spacing = 12.5
kHz.
2. Definition of reference signal is 38.4 kbps 2GFSK, BT=0.5, Δf = 20 kHz, RX channel BW = 74.809 kHz, channel spacing = 100
kHz.
3. Definition of reference signal is 500 kbps 2GFSK, BT=0.5, Δf = 125 kHz, RX channel BW = 753.320 kHz.
4. RFSENSE performance is only valid from 0 to 85 °C. RFSENSE should be disabled outside this temperature range.
4.1.11 Modem
Table 4.32. Modem
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Receive bandwidth
BWRX
Configurable range with 38.4 MHz
crystal
0.1
—
2530
kHz
IF frequency
fIF
Configurable range with 38.4 MHz
crystal. Selected steps available.
150
—
1371
kHz
DSSS symbol length
DSSS bits per symbol
SLDSSS
Configurable in steps of 1 chip
Configurable
2
1
—
—
32
4
chips
BPSDSSS
bits/
symbol
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
4.1.12 Oscillators
4.1.12.1 Low-Frequency Crystal Oscillator (LFXO)
Table 4.33. Low-Frequency Crystal Oscillator (LFXO)
Parameter
Symbol
Test Condition
Min
—
Typ
32.768
—
Max
—
Unit
kHz
kΩ
Crystal frequency
fLFXO
Supported crystal equivalent ESRLFXO
series resistance (ESR)
—
70
Supported range of crystal
load capacitance 1
CLFXO_CL
6
8
—
—
18
40
pF
pF
On-chip tuning cap range 2
CLFXO_T
On each of LFXTAL_N and
LFXTAL_P pins
On-chip tuning cap step size SSLFXO
—
—
0.25
273
—
—
pF
nA
Current consumption after
startup 3
ILFXO
ESR = 70 kOhm, CL = 7 pF,
GAIN4 = 2, AGC4 = 1
Start- up time
tLFXO
ESR = 70 kOhm, CL = 7 pF,
GAIN4 = 2
—
308
—
ms
Note:
1. Total load capacitance as seen by the crystal.
2. The effective load capacitance seen by the crystal will be CLFXO_T /2. This is because each XTAL pin has a tuning cap and the
two caps will be seen in series by the crystal.
3. Block is supplied by AVDD if ANASW = 0, or DVDD if ANASW=1 in EMU_PWRCTRL register.
4. In CMU_LFXOCTRL register.
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
4.1.12.2 High-Frequency Crystal Oscillator (HFXO)
Table 4.34. High-Frequency Crystal Oscillator (HFXO)
Parameter
Symbol
Test Condition
Min
38
Typ
38.4
—
Max
40
Unit
MHz
Ω
Crystal frequency
fHFXO
Supported crystal equivalent ESRHFXO_38M4 Crystal frequency 38.4 MHz
series resistance (ESR)
—
60
Supported range of crystal
load capacitance 1
CHFXO_CL
6
—
12
pF
On-chip tuning cap range 2
CHFXO_T
SSHFXO
tHFXO
On each of HFXTAL_N and
HFXTAL_P pins
9
20
0.04
300
—
25
—
—
40
pF
pF
On-chip tuning capacitance
step
—
Startup time
38.4 MHz, ESR = 50 Ohm, CL =
10 pF
—
μs
Frequency tolerance for the FTHFXO
crystal
38.4 MHz, ESR = 50 Ohm, CL =
10 pF
-40
ppm
Note:
1. Total load capacitance as seen by the crystal.
2. The effective load capacitance seen by the crystal will be CHFXO_T /2. This is because each XTAL pin has a tuning cap and the
two caps will be seen in series by the crystal.
4.1.12.3 Low-Frequency RC Oscillator (LFRCO)
Table 4.35. Low-Frequency RC Oscillator (LFRCO)
Parameter
Symbol
Test Condition
ENVREF2 = 1
ENVREF2 = 0
Min
Typ
Max
Unit
Oscillation frequency
fLFRCO
31.3
32.768
33.6
kHz
31.3
—
32.768
500
33.4
—
kHz
μs
Startup time
tLFRCO
ILFRCO
Current consumption 1
ENVREF = 1 in
CMU_LFRCOCTRL
—
370
—
nA
ENVREF = 0 in
—
520
—
nA
CMU_LFRCOCTRL
Note:
1. Block is supplied by AVDD if ANASW = 0, or DVDD if ANASW=1 in EMU_PWRCTRL register.
2. In CMU_LFRCOCTRL register.
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
4.1.12.4 High-Frequency RC Oscillator (HFRCO)
Table 4.36. High-Frequency RC Oscillator (HFRCO)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Frequency accuracy
fHFRCO_ACC
At production calibrated frequen-
cies, across supply voltage and
temperature
-2.5
—
2.5
%
Start-up time
tHFRCO
fHFRCO ≥ 19 MHz
4 < fHFRCO < 19 MHz
fHFRCO ≤ 4 MHz
fHFRCO = 38 MHz
fHFRCO = 32 MHz
fHFRCO = 26 MHz
fHFRCO = 19 MHz
fHFRCO = 16 MHz
fHFRCO = 13 MHz
fHFRCO = 7 MHz
fHFRCO = 4 MHz
fHFRCO = 2 MHz
fHFRCO = 1 MHz
—
—
—
—
—
—
—
—
—
—
—
—
—
—
300
1
—
—
ns
μs
2.5
244
204
173
143
123
110
85
—
μs
Current consumption on all
supplies
IHFRCO
265
222
188
156
136
124
94
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
%
32
37
28
34
26
31
Coarse trim step size (% of
period)
SSHFRCO_COARS
0.8
—
E
Fine trim step size (% of pe- SSHFRCO_FINE
riod)
—
—
0.1
0.2
—
—
%
Period jitter
PJHFRCO
% RMS
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
4.1.12.5 Auxiliary High-Frequency RC Oscillator (AUXHFRCO)
Table 4.37. Auxiliary High-Frequency RC Oscillator (AUXHFRCO)
Parameter
Symbol
Test Condition
Min
-3
Typ
Max
Unit
Frequency accuracy
fAUXHFRCO_ACC At production calibrated frequen-
—
3
%
cies, across supply voltage and
temperature
Start-up time
tAUXHFRCO
fAUXHFRCO ≥ 19 MHz
4 < fAUXHFRCO < 19 MHz
fAUXHFRCO ≤ 4 MHz
fAUXHFRCO = 38 MHz
fAUXHFRCO = 32 MHz
fAUXHFRCO = 26 MHz
fAUXHFRCO = 19 MHz
fAUXHFRCO = 16 MHz
fAUXHFRCO = 13 MHz
fAUXHFRCO = 7 MHz
fAUXHFRCO = 4 MHz
fAUXHFRCO = 2 MHz
fAUXHFRCO = 1 MHz
—
—
—
—
—
—
—
—
—
—
—
—
—
—
400
1.4
2.5
193
157
135
108
100
77
—
—
ns
μs
—
μs
Current consumption on all
supplies
IAUXHFRCO
213
175
151
122
113
88
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
%
53
63
29
36
28
34
27
31
Coarse trim step size (% of
period)
SSAUXHFR-
0.8
—
CO_COARSE
Fine trim step size (% of pe- SSAUXHFR-
—
—
0.1
0.2
—
—
%
riod)
CO_FINE
Period jitter
PJAUXHFRCO
% RMS
4.1.12.6 Ultra-low Frequency RC Oscillator (ULFRCO)
Table 4.38. Ultra-low Frequency RC Oscillator (ULFRCO)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Oscillation frequency
fULFRCO
0.95
1
1.07
kHz
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
4.1.13 Flash Memory Characteristics3
Table 4.39. Flash Memory Characteristics3
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Flash erase cycles before
failure
ECFLASH
10000
—
—
cycles
Flash data retention
RETFLASH
tW_PROG
10
20
—
—
years
μs
Word (32-bit) programming
time
Burst write, 128 words, average
time per word
24.4
30
Single word
60
20
20
68.4
26.4
26.5
80
35
35
μs
ms
ms
Page erase time
Mass erase time1
Device erase time2
Page erase current4
Write current4
tPERASE
tMERASE
tDERASE
IERASE
—
—
69
—
—
—
100
1.6
3.8
3.6
ms
mA
mA
V
IWRITE
—
Supply voltage during flash
erase and write
VFLASH
1.62
Note:
1. Mass erase is issued by the CPU and erases all flash.
2. Device erase is issued over the AAP interface and erases all flash, SRAM, the Lock Bit (LB) page, and the User data page Lock
Word (ULW).
3. Flash data retention information is published in the Quarterly Quality and Reliability Report.
4. Measured at 25 °C.
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
4.1.14 General-Purpose I/O (GPIO)
Table 4.40. General-Purpose I/O (GPIO)
Parameter
Symbol
Test Condition
GPIO pins
Min
—
Typ
—
Max
IOVDD*0.3
—
Unit
V
Input low voltage
Input high voltage
VIL
VIH
GPIO pins
IOVDD*0.7
IOVDD*0.8
—
V
Output high voltage relative VOH
to IOVDD
Sourcing 3 mA, IOVDD ≥ 3 V,
—
—
V
DRIVESTRENGTH1 = WEAK
Sourcing 1.2 mA, IOVDD ≥ 1.62
V,
IOVDD*0.6
—
—
V
DRIVESTRENGTH1 = WEAK
Sourcing 20 mA, IOVDD ≥ 3 V,
IOVDD*0.8
—
—
—
—
—
—
0.1
—
V
V
DRIVESTRENGTH1 = STRONG
Sourcing 8 mA, IOVDD ≥ 1.62 V,
IOVDD*0.6
—
DRIVESTRENGTH1 = STRONG
Sinking 3 mA, IOVDD ≥ 3 V,
Output low voltage relative to VOL
IOVDD
—
—
—
—
—
IOVDD*0.2
IOVDD*0.4
IOVDD*0.2
IOVDD*0.4
30
V
DRIVESTRENGTH1 = WEAK
Sinking 1.2 mA, IOVDD ≥ 1.62 V,
V
DRIVESTRENGTH1 = WEAK
Sinking 20 mA, IOVDD ≥ 3 V,
V
DRIVESTRENGTH1 = STRONG
Sinking 8 mA, IOVDD ≥ 1.62 V,
V
DRIVESTRENGTH1 = STRONG
Input leakage current
IIOLEAK
All GPIO except LFXO pins, GPIO
≤ IOVDD
nA
LFXO Pins, GPIO ≤ IOVDD
—
—
0.1
3.3
50
15
nA
μA
Input leakage current on
I5VTOLLEAK
IOVDD < GPIO ≤ IOVDD + 2 V
5VTOL pads above IOVDD
I/O pin pull-up/pull-down re- RPUD
sistor
30
15
40
25
65
45
kΩ
ns
Pulse width of pulses re-
moved by the glitch suppres-
sion filter
tIOGLITCH
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Output fall time, From 70%
to 30% of VIO
tIOOF
CL = 50 pF,
—
1.8
—
ns
DRIVESTRENGTH1 = STRONG,
SLEWRATE1 = 0x6
CL = 50 pF,
—
—
—
4.5
2.2
7.4
—
—
—
ns
ns
ns
DRIVESTRENGTH1 = WEAK,
SLEWRATE1 = 0x6
CL = 50 pF,
Output rise time, From 30% tIOOR
to 70% of VIO
DRIVESTRENGTH1 = STRONG,
SLEWRATE = 0x61
CL = 50 pF,
DRIVESTRENGTH1 = WEAK,
SLEWRATE1 = 0x6
Note:
1. In GPIO_Pn_CTRL register.
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
4.1.15 Voltage Monitor (VMON)
Table 4.41. Voltage Monitor (VMON)
Parameter
Symbol
IVMON
Test Condition
Min
Typ
Max
Unit
Supply current (including
I_SENSE)
In EM0 or EM1, 1 supply moni-
tored
—
6.3
10
μA
In EM0 or EM1, 4 supplies moni-
tored
—
—
—
—
—
12.5
62
17
—
—
—
—
μA
nA
nA
nA
nA
In EM2, EM3 or EM4, 1 supply
monitored and above threshol
In EM2, EM3 or EM4, 1 supply
monitored and below threshold
62
In EM2, EM3 or EM4, 4 supplies
monitored and all above threshold
99
In EM2, EM3 or EM4, 4 supplies
monitored and all below threshold
99
Loading of monitored supply ISENSE
In EM0 or EM1
—
—
2
2
—
—
3.4
—
—
—
—
μA
nA
V
In EM2, EM3 or EM4
Threshold range
VVMON_RANGE
1.62
—
—
Threshold step size
NVMON_STESP
Coarse
200
20
460
26
mV
mV
ns
Fine
—
Response time
Hysteresis
tVMON_RES
Supply drops at 1V/μs rate
—
VVMON_HYST
—
mV
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
4.1.16 Analog to Digital Converter (ADC)
Table 4.42. Analog to Digital Converter (ADC)
Parameter
Symbol
Test Condition
Min
Typ
—
Max
12
Unit
Bits
V
Resolution
VRESOLUTION
VADCIN
6
—
Input voltage range
Single ended
Differential
—
VFS
-VFS/2
1
—
VFS/2
VAVDD
V
Input range of external refer- VADCREFIN_P
ence voltage, single ended
and differential
—
V
Power supply rejection2
PSRRADC
At DC
At DC
—
—
80
80
—
—
dB
dB
Analog input common mode CMRRADC
rejection ratio
Current from all supplies, us- IADC_CONTI-
1 Msps / 16 MHz ADCCLK, BIA-
SPROG = 0, GPBIASACC = 1 3
—
—
—
—
—
—
—
270
125
80
315
—
—
—
—
—
—
μA
μA
μA
μA
μA
μA
μA
ing internal reference buffer.
NOUS_LP
Continous operation. WAR-
MUPMODE4 = KEEPADC-
WARM
250 ksps / 4 MHz ADCCLK, BIA-
SPROG = 6, GPBIASACC = 1 3
62.5 ksps / 1 MHz ADCCLK, BIA-
SPROG = 15, GPBIASACC = 1 3
Current from all supplies, us- IADC_NORMAL_LP 35 ksps / 16 MHz ADCCLK, BIA-
45
SPROG = 0, GPBIASACC = 1 3
ing internal reference buffer.
Duty-cycled operation. WAR-
MUPMODE4 = NORMAL
5 ksps / 16 MHz ADCCLK BIA-
SPROG = 0, GPBIASACC = 1 3
8
Current from all supplies, us- IADC_STAND-
125 ksps / 16 MHz ADCCLK, BIA-
SPROG = 0, GPBIASACC = 1 3
105
70
ing internal reference buffer.
BY_LP
Duty-cycled operation.
35 ksps / 16 MHz ADCCLK, BIA-
SPROG = 0, GPBIASACC = 1 3
AWARMUPMODE4 = KEEP-
INSTANDBY or KEEPIN-
SLOWACC
Current from all supplies, us- IADC_CONTI-
1 Msps / 16 MHz ADCCLK, BIA-
SPROG = 0, GPBIASACC = 0 3
—
—
—
—
—
—
—
325
175
125
85
—
—
—
—
—
—
—
μA
μA
μA
μA
μA
μA
μA
ing internal reference buffer.
NOUS_HP
Continous operation. WAR-
MUPMODE4 = KEEPADC-
WARM
250 ksps / 4 MHz ADCCLK, BIA-
SPROG = 6, GPBIASACC = 0 3
62.5 ksps / 1 MHz ADCCLK, BIA-
SPROG = 15, GPBIASACC = 0 3
Current from all supplies, us- IADC_NORMAL_HP 35 ksps / 16 MHz ADCCLK, BIA-
SPROG = 0, GPBIASACC = 0 3
ing internal reference buffer.
Duty-cycled operation. WAR-
MUPMODE4 = NORMAL
5 ksps / 16 MHz ADCCLK BIA-
SPROG = 0, GPBIASACC = 0 3
16
Current from all supplies, us- IADC_STAND-
125 ksps / 16 MHz ADCCLK, BIA-
SPROG = 0, GPBIASACC = 0 3
160
125
ing internal reference buffer.
BY_HP
Duty-cycled operation.
35 ksps / 16 MHz ADCCLK, BIA-
SPROG = 0, GPBIASACC = 0 3
AWARMUPMODE4 = KEEP-
INSTANDBY or KEEPIN-
SLOWACC
Current from HFPERCLK
IADC_CLK
HFPERCLK = 16 MHz
—
160
—
μA
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
fADCCLK
Test Condition
Min
—
Typ
—
—
7
Max
16
1
Unit
MHz
ADC clock frequency
Throughput rate
fADCRATE
tADCCONV
—
Msps
cycles
cycles
cycles
μs
Conversion time1
6 bit
8 bit
12 bit
—
—
—
—
5
—
9
—
13
—
WARMUPMODE4 = NORMAL
Startup time of reference
generator and ADC core
tADCSTART
—
WARMUPMODE4 = KEEPIN-
STANDBY
—
—
58
—
—
—
67
68
2
μs
μs
dB
dB
WARMUPMODE4 = KEEPINSLO-
WACC
1
Internal reference6, differential
measurement
SNDR at 1Msps and fIN
10kHz
=
SNDRADC
—
—
External reference5, differential
measurement
Spurious-free dynamic range SFDRADC
(SFDR)
1 MSamples/s, 10 kHz full-scale
sine wave
—
-1
-6
75
—
—
—
2
dB
Differential non-linearity
(DNL)
DNLADC
12 bit resolution, No missing co-
des
LSB
LSB
Integral non-linearity (INL),
End point method
INLADC
12 bit resolution
6
Offset error
VADCOFFSETERR
VADCGAIN
-3
—
—
—
0
3
LSB
%
Gain error in ADC
Using internal reference
Using external reference
-0.2
-1
3.5
—
—
%
Temperature sensor slope
VTS_SLOPE
-1.84
mV/°C
Note:
1. Derived from ADCCLK.
2. PSRR is referenced to AVDD when ANASW=0 and to DVDD when ANASW=1 in EMU_PWRCTRL.
3. In ADCn_BIASPROG register.
4. In ADCn_CNTL register.
5. External reference is 1.25 V applied externally to ADCnEXTREFP, with the selection CONF in the SINGLECTRL_REF or
SCANCTRL_REF register field and VREFP in the SINGLECTRLX_VREFSEL or SCANCTRLX_VREFSEL field. The differential
input range with this configuration is ± 1.25 V.
6. Internal reference option used corresponds to selection 2V5 in the SINGLECTRL_REF or SCANCTRL_REF register field. The
differential input range with this configuration is ± 1.25 V. Typical value is characterized using full-scale sine wave input. Minimum
value is production-tested using sine wave input at 1.5 dB lower than full scale.
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
4.1.17 Analog Comparator (ACMP)
Table 4.43. Analog Comparator (ACMP)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Input voltage range
VACMPIN
ACMPVDD =
ACMPn_CTRL_PWRSEL 1
—
—
VACMPVDD
V
BIASPROG4 ≤ 0x10 or FULL-
BIAS4 = 0
Supply voltage
VACMPVDD
1.8
2.1
—
—
VVREGVDD_
V
V
MAX
0x10 < BIASPROG4 ≤ 0x20 and
FULLBIAS4 = 1
VVREGVDD_
MAX
BIASPROG4 = 1, FULLBIAS4 = 0
Active current not including
voltage reference2
IACMP
—
—
50
—
—
nA
nA
BIASPROG4 = 0x10, FULLBIAS4
= 0
306
BIASPROG4 = 0x02, FULLBIAS4
= 1
—
—
—
6.5
75
50
—
92
—
μA
μA
nA
BIASPROG4 = 0x20, FULLBIAS4
= 1
Current consumption of inter- IACMPREF
nal voltage reference2
VLP selected as input using 2.5 V
Reference / 4 (0.625 V)
VLP selected as input using VDD
—
—
20
—
—
nA
μA
VBDIV selected as input using
1.25 V reference / 1
4.1
VADIV selected as input using
VDD/1
—
2.4
—
μA
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
HYSTSEL5 = HYST0
HYSTSEL5 = HYST1
HYSTSEL5 = HYST2
HYSTSEL5 = HYST3
HYSTSEL5 = HYST4
HYSTSEL5 = HYST5
HYSTSEL5 = HYST6
HYSTSEL5 = HYST7
HYSTSEL5 = HYST8
HYSTSEL5 = HYST9
HYSTSEL5 = HYST10
HYSTSEL5 = HYST11
HYSTSEL5 = HYST12
HYSTSEL5 = HYST13
HYSTSEL5 = HYST14
HYSTSEL5 = HYST15
BIASPROG4 = 1, FULLBIAS4 = 0
Hysteresis (VCM = 1.25 V,
BIASPROG4 = 0x10, FULL-
BIAS4 = 1)
VACMPHYST
-3
0
3
mV
5
12
18
33
27
50
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
μs
17
46
65
23
57
82
26
68
98
30
79
130
150
3
34
90
-3
0
-27
-50
-65
-82
-98
-130
-150
—
-18
-33
-45
-57
-67
-78
-88
30
-5
-12
-17
-23
-26
-30
-34
—
Comparator delay3
tACMPDELAY
BIASPROG4 = 0x10, FULLBIAS4
= 0
—
3.7
—
μs
BIASPROG4 = 0x02, FULLBIAS4
= 1
—
—
360
35
—
—
35
ns
ns
BIASPROG4 = 0x20, FULLBIAS4
= 1
BIASPROG4 =0x10, FULLBIAS4
= 1
Offset voltage
VACMPOFFSET
-35
—
mV
Reference voltage
VACMPREF
Internal 1.25 V reference
Internal 2.5 V reference
1
2
1.25
2.5
inf
1.47
2.8
—
V
V
CSRESSEL6 = 0
CSRESSEL6 = 1
CSRESSEL6 = 2
CSRESSEL6 = 3
CSRESSEL6 = 4
CSRESSEL6 = 5
CSRESSEL6 = 6
CSRESSEL6 = 7
Capacitive sense internal re- RCSRES
sistance
—
kΩ
—
—
—
—
—
—
—
15
27
—
—
—
—
—
—
—
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
39
51
100
162
235
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
Parameter
Note:
Symbol
Test Condition
Min
Typ
Max
Unit
1. ACMPVDD is a supply chosen by the setting in ACMPn_CTRL_PWRSEL and may be IOVDD, AVDD or DVDD.
2. The total ACMP current is the sum of the contributions from the ACMP and its internal voltage reference. IACMPTOTAL = IACMP
IACMPREF
+
.
3. ± 100 mV differential drive.
4. In ACMPn_CTRL register.
5. In ACMPn_HYSTERESIS register.
6. In ACMPn_INPUTSEL register.
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
4.1.18 Digital to Analog Converter (VDAC)
DRIVESTRENGTH = 2 unless otherwise specified. Primary VDAC output.
Table 4.44. Digital to Analog Converter (VDAC)
Parameter
Symbol
Test Condition
Single-Ended
Min
Typ
—
Max
Unit
V
Output voltage
VDACOUT
0
VVREF
VVREF
Differential2
-VVREF
—
—
V
Current consumption includ- IDAC
ing references (2 channels)1
500 ksps, 12-bit, DRIVES-
TRENGTH = 2, REFSEL = 4
396
72
—
—
—
μA
μA
μA
44.1 ksps, 12-bit, DRIVES-
TRENGTH = 1, REFSEL = 4
—
—
200 Hz refresh rate, 12-bit Sam-
ple-Off mode in EM2, DRIVES-
TRENGTH = 2, BGRREQTIME =
1, EM2REFENTIME = 9, REFSEL
= 4, SETTLETIME = 0x0A, WAR-
MUPTIME = 0x02
1.2
Current from HFPERCLK4
Sample rate
IDAC_CLK
—
—
—
2
5.8
—
—
500
1
μA/MHz
ksps
MHz
μs
SRDAC
DAC clock frequency
Conversion time
Settling time
fDAC
—
tDACCONV
tDACSETTLE
tDACSTARTUP
fDAC = 1MHz
—
—
50% fs step settling to 5 LSB
—
—
2.5
—
—
μs
Startup time
Enable to 90% fs output, settling
to 10 LSB
12
μs
Output impedance
ROUT
DRIVESTRENGTH = 2, 0.4 V ≤
VOUT ≤ VOPA - 0.4 V, -8 mA <
IOUT < 8 mA, Full supply range
—
—
—
—
—
2
2
—
—
—
—
—
Ω
Ω
DRIVESTRENGTH = 0 or 1, 0.4 V
≤ VOUT ≤ VOPA - 0.4 V, -400 μA <
IOUT < 400 μA, Full supply range
DRIVESTRENGTH = 2, 0.1 V ≤
VOUT ≤ VOPA - 0.1 V, -2 mA <
IOUT < 2 mA, Full supply range
2
Ω
DRIVESTRENGTH = 0 or 1, 0.1 V
≤ VOUT ≤ VOPA - 0.1 V, -100 μA <
IOUT < 100 μA, Full supply range
2
Ω
Power supply rejection ratio6
PSRR
Vout = 50% fs. DC
65.5
dB
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Signal to noise and distortion SNDRDAC
ratio (1 kHz sine wave),
Noise band limited to 250
kHz
500 ksps, single-ended, internal
1.25V reference
—
60.4
—
dB
500 ksps, single-ended, internal
2.5V reference
—
—
—
—
—
—
—
—
—
—
—
61.6
64.0
63.3
64.4
65.8
65.3
66.7
70.0
67.8
69.0
68.5
—
—
—
—
—
—
—
—
—
—
—
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
500 ksps, single-ended, 3.3V
VDD reference
500 ksps, differential, internal
1.25V reference
500 ksps, differential, internal
2.5V reference
500 ksps, differential, 3.3V VDD
reference
Signal to noise and distortion SNDRDAC_BAND 500 ksps, single-ended, internal
ratio (1 kHz sine wave),
Noise band limited to 22 kHz
1.25V reference
500 ksps, single-ended, internal
2.5V reference
500 ksps, single-ended, 3.3V
VDD reference
500 ksps, differential, internal
1.25V reference
500 ksps, differential, internal
2.5V reference
500 ksps, differential, 3.3V VDD
reference
Total harmonic distortion
THD
—
70.2
—
—
1
dB
Differential non-linearity3
Intergral non-linearity
DNLDAC
-0.99
LSB
INLDAC
-4
-8
—
—
—
4
8
LSB
mV
mV
Offset error5
VOFFSET
T = 25 °C
Across operating temperature
range
-25
25
Gain error5
VGAIN
T = 25 °C, Low-noise internal ref-
erence (REFSEL = 1V25LN or
2V5LN)
-1.5
—
1.5
%
T = 25 °C, Internal reference (RE-
FSEL = 1V25 or 2V5)
-5
—
—
—
5
%
%
%
T = 25 °C, External reference
(REFSEL = VDD or EXT)
-1.5
-3.5
1.5
3.5
Across operating temperature
range, Low-noise internal refer-
ence (REFSEL = 1V25LN or
2V5LN)
Across operating temperature
range, Internal reference (RE-
FSEL = 1V25 or 2V5)
-7.5
-1.5
—
—
7.5
1.5
%
%
Across operating temperature
range, External reference (RE-
FSEL = VDD or EXT)
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
External load capactiance,
OUTSCALE=0
CLOAD
—
—
75
pF
Note:
1. Supply current specifications are for VDAC circuitry operating with static output only and do not include current required to drive
the load.
2. In differential mode, the output is defined as the difference between two single-ended outputs. Absolute voltage on each output is
limited to the single-ended range.
3. Entire range is monotonic and has no missing codes.
4. Current from HFPERCLK is dependent on HFPERCLK frequency. This current contributes to the total supply current used when
the clock to the DAC module is enabled in the CMU.
5. Gain is calculated by measuring the slope from 10% to 90% of full scale. Offset is calculated by comparing actual VDAC output at
10% of full scale to ideal VDAC output at 10% of full scale with the measured gain.
6. PSRR calculated as 20 * log10(ΔVDD / ΔVOUT), VDAC output at 90% of full scale
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
4.1.19 Current Digital to Analog Converter (IDAC)
Table 4.45. Current Digital to Analog Converter (IDAC)
Parameter
Symbol
Test Condition
Min
—
Typ
4
Max
—
Unit
-
Number of ranges
Output current
NIDAC_RANGES
IIDAC_OUT
RANGSEL1 = RANGE0
RANGSEL1 = RANGE1
RANGSEL1 = RANGE2
RANGSEL1 = RANGE3
0.05
—
1.6
μA
1.6
0.5
2
—
—
—
32
4.7
16
64
—
μA
μA
μA
Linear steps within each
range
NIDAC_STEPS
—
RANGSEL1 = RANGE0
RANGSEL1 = RANGE1
RANGSEL1 = RANGE2
RANGSEL1 = RANGE3
Step size
SSIDAC
—
—
—
—
-3
50
100
500
2
—
—
—
—
3
nA
nA
nA
μA
%
Total accuracy, STEPSEL1 =
0x80
ACCIDAC
EM0 or EM1, AVDD=3.3 V, T = 25
°C
—
EM0 or EM1, Across operating
temperature range
-18
—
—
-2
22
—
%
%
EM2 or EM3, Source mode,
RANGSEL1 = RANGE0,
AVDD=3.3 V, T = 25 °C
EM2 or EM3, Source mode,
RANGSEL1 = RANGE1,
AVDD=3.3 V, T = 25 °C
—
—
—
—
—
—
—
—
-1.7
-0.8
-0.5
-0.7
-0.6
-0.5
-0.5
5
—
—
—
—
—
—
—
—
%
EM2 or EM3, Source mode,
RANGSEL1 = RANGE2,
AVDD=3.3 V, T = 25 °C
%
EM2 or EM3, Source mode,
RANGSEL1 = RANGE3,
AVDD=3.3 V, T = 25 °C
%
EM2 or EM3, Sink mode, RANG-
SEL1 = RANGE0, AVDD=3.3 V, T
= 25 °C
%
EM2 or EM3, Sink mode, RANG-
SEL1 = RANGE1, AVDD=3.3 V, T
= 25 °C
%
EM2 or EM3, Sink mode, RANG-
SEL1 = RANGE2, AVDD=3.3 V, T
= 25 °C
%
EM2 or EM3, Sink mode, RANG-
SEL1 = RANGE3, AVDD=3.3 V, T
= 25 °C
%
μs
Start up time
tIDAC_SU
Output within 1% of steady state
value
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
—
Typ
5
Max
—
Unit
μs
Settling time, (output settled tIDAC_SETTLE
within 1% of steady state val-
ue),
Range setting is changed
Step value is changed
—
1
—
μs
Current consumption2
IIDAC
EM0 or EM1 Source mode, ex-
cluding output current, Across op-
erating temperature range
—
11
18
μA
EM0 or EM1 Sink mode, exclud-
ing output current, Across operat-
ing temperature range
—
13
21
μA
EM2 or EM3 Source mode, ex-
cluding output current, T = 25 °C
—
—
—
—
—
0.023
0.041
11
—
—
—
—
—
μA
μA
μA
μA
%
EM2 or EM3 Sink mode, exclud-
ing output current, T = 25 °C
EM2 or EM3 Source mode, ex-
cluding output current, T ≥ 85 °C
EM2 or EM3 Sink mode, exclud-
ing output current, T ≥ 85 °C
13
Output voltage compliance in ICOMP_SRC
source mode, source current
change relative to current
sourced at 0 V
RANGESEL1=0, output voltage =
min(VIOVDD, VAVDD2-100 mv)
0.11
RANGESEL1=1, output voltage =
min(VIOVDD, VAVDD2-100 mV)
—
—
—
0.06
0.04
0.03
—
—
—
%
%
%
RANGESEL1=2, output voltage =
min(VIOVDD, VAVDD2-150 mV)
RANGESEL1=3, output voltage =
min(VIOVDD, VAVDD2-250 mV)
Output voltage compliance in ICOMP_SINK
sink mode, sink current
change relative to current
sunk at IOVDD
RANGESEL1=0, output voltage =
100 mV
—
—
—
—
0.12
0.05
0.04
0.03
—
—
—
—
%
%
%
%
RANGESEL1=1, output voltage =
100 mV
RANGESEL1=2, output voltage =
150 mV
RANGESEL1=3, output voltage =
250 mV
Note:
1. In IDAC_CURPROG register.
2. The IDAC is supplied by either AVDD, DVDD, or IOVDD based on the setting of ANASW in the EMU_PWRCTRL register and
PWRSEL in the IDAC_CTRL register. Setting PWRSEL to 1 selects IOVDD. With PWRSEL cleared to 0, ANASW selects be-
tween AVDD (0) and DVDD (1).
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
4.1.20 Capacitive Sense (CSEN)
Table 4.46. Capacitive Sense (CSEN)
Parameter
Symbol
tCNV
Test Condition
Min
—
Typ
20.2
26.4
1.55
Max
—
Unit
μs
Single conversion time (1x
accumulation)
12-bit SAR Conversions
16-bit SAR Conversions
—
—
μs
Delta Modulation Conversion (sin-
gle comparison)
—
—
μs
Maximum external capactive CEXTMAX
load
CS0CG=7 (Gain = 1x), including
routing parasitics
—
—
—
—
68
680
1
—
—
—
—
pF
pF
kΩ
nA
CS0CG=0 (Gain = 10x), including
routing parasitics
Maximum external series im- REXTMAX
pedance
Supply current, EM2 bonded ICSEN_BOND
conversions, WARMUP-
MODE=NORMAL, WAR-
MUPCNT=0
12-bit SAR conversions, 20 ms
conversion rate, CS0CG=7 (Gain
= 1x), 10 channels bonded (total
capacitance of 330 pF)1
326
Delta Modulation conversions, 20
ms conversion rate, CS0CG=7
(Gain = 1x), 10 channels bonded
—
—
—
226
33
—
—
—
nA
nA
nA
(total capacitance of 330 pF)1
12-bit SAR conversions, 200 ms
conversion rate, CS0CG=7 (Gain
= 1x), 10 channels bonded (total
capacitance of 330 pF)1
Delta Modulation conversions,
200 ms conversion rate,
25
CS0CG=7 (Gain = 1x), 10 chan-
nels bonded (total capacitance of
330 pF)1
Supply current, EM2 scan
conversions, WARMUP-
MODE=NORMAL, WAR-
MUPCNT=0
ICSEN_EM2
12-bit SAR conversions, 20 ms
scan rate, CS0CG=0 (Gain =
—
—
690
515
—
—
nA
nA
10x), 8 samples per scan1
Delta Modulation conversions, 20
ms scan rate, 8 comparisons per
sample (DMCR = 1, DMR = 2),
CS0CG=0 (Gain = 10x), 8 sam-
ples per scan1
12-bit SAR conversions, 200 ms
scan rate, CS0CG=0 (Gain =
—
—
79
57
—
—
nA
nA
10x), 8 samples per scan1
Delta Modulation conversions,
200 ms scan rate, 8 comparisons
per sample (DMCR = 1, DMR =
2), CS0CG=0 (Gain = 10x), 8
samples per scan1
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Supply current, continuous
conversions, WARMUP-
MODE=KEEPCSENWARM
ICSEN_ACTIVE
SAR or Delta Modulation conver-
sions of 33 pF capacitor,
CS0CG=0 (Gain = 10x), always
on
—
90.5
—
μA
HFPERCLK supply current
ICSEN_HFPERCLK Current contribution from
HFPERCLK when clock to CSEN
block is enabled.
—
2.25
—
μA/MHz
Note:
1. Current is specified with a total external capacitance of 33 pF per channel. Average current is dependent on how long the module
is actively sampling channels within the scan period, and scales with the number of samples acquired. Supply current for a specif-
ic application can be estimated by multiplying the current per sample by the total number of samples per period (total_current =
single_sample_current * (number_of_channels * accumulation)).
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
4.1.21 Operational Amplifier (OPAMP)
Unless otherwise indicated, specified conditions are: Non-inverting input configuration, VDD = 3.3 V, DRIVESTRENGTH = 2, MAIN-
OUTEN = 1, CLOAD = 75 pF with OUTSCALE = 0, or CLOAD = 37.5 pF with OUTSCALE = 1. Unit gain buffer and 3X-gain connection as
specified in table footnotes8 1
.
Table 4.47. Operational Amplifier (OPAMP)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Supply voltage
VOPA
HCMDIS = 0, Rail-to-rail input
range
2
—
3.8
V
HCMDIS = 1
1.62
—
—
3.8
V
V
Input voltage
VIN
HCMDIS = 0, Rail-to-rail input
range
VVSS
VOPA
HCMDIS = 1
VVSS
100
VVSS
—
—
—
VOPA-1.2
—
V
MΩ
V
Input impedance
Output voltage
RIN
VOUT
CLOAD
—
VOPA
75
Load capacitance2
OUTSCALE = 0
OUTSCALE = 1
—
pF
pF
Ω
—
—
37.5
—
Output impedance
ROUT
DRIVESTRENGTH = 2 or 3, 0.4 V
≤ VOUT ≤ VOPA - 0.4 V, -8 mA <
IOUT < 8 mA, Buffer connection,
Full supply range
—
0.25
DRIVESTRENGTH = 0 or 1, 0.4 V
≤ VOUT ≤ VOPA - 0.4 V, -400 μA <
IOUT < 400 μA, Buffer connection,
Full supply range
—
—
—
0.6
0.4
1
—
—
—
Ω
Ω
Ω
DRIVESTRENGTH = 2 or 3, 0.1 V
≤ VOUT ≤ VOPA - 0.1 V, -2 mA <
IOUT < 2 mA, Buffer connection,
Full supply range
DRIVESTRENGTH = 0 or 1, 0.1 V
≤ VOUT ≤ VOPA - 0.1 V, -100 μA <
IOUT < 100 μA, Buffer connection,
Full supply range
Internal closed-loop gain
Active current4
GCL
Buffer connection
3x Gain connection
16x Gain connection
0.99
2.93
15.07
—
1
1.01
3.05
16.33
—
-
-
2.99
15.7
580
-
IOPA
DRIVESTRENGTH = 3, OUT-
SCALE = 0
μA
DRIVESTRENGTH = 2, OUT-
SCALE = 0
—
—
—
176
13
—
—
—
μA
μA
μA
DRIVESTRENGTH = 1, OUT-
SCALE = 0
DRIVESTRENGTH = 0, OUT-
SCALE = 0
4.7
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
—
Typ
135
137
121
109
3.38
Max
—
Unit
dB
Open-loop gain
GOL
DRIVESTRENGTH = 3
DRIVESTRENGTH = 2
DRIVESTRENGTH = 1
DRIVESTRENGTH = 0
—
—
dB
—
—
dB
—
—
dB
Loop unit-gain frequency7
UGF
DRIVESTRENGTH = 3, Buffer
connection
—
—
MHz
DRIVESTRENGTH = 2, Buffer
connection
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.9
132
34
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MHz
kHz
DRIVESTRENGTH = 1, Buffer
connection
DRIVESTRENGTH = 0, Buffer
connection
kHz
DRIVESTRENGTH = 3, 3x Gain
connection
2.57
0.71
113
28
MHz
MHz
kHz
DRIVESTRENGTH = 2, 3x Gain
connection
DRIVESTRENGTH = 1, 3x Gain
connection
DRIVESTRENGTH = 0, 3x Gain
connection
kHz
Phase margin
PM
DRIVESTRENGTH = 3, Buffer
connection
67
°
DRIVESTRENGTH = 2, Buffer
connection
69
°
DRIVESTRENGTH = 1, Buffer
connection
63
°
DRIVESTRENGTH = 0, Buffer
connection
68
°
Output voltage noise
NOUT
DRIVESTRENGTH = 3, Buffer
connection, 10 Hz - 10 MHz
146
163
170
176
313
271
247
245
μVrms
μVrms
μVrms
μVrms
μVrms
μVrms
μVrms
μVrms
DRIVESTRENGTH = 2, Buffer
connection, 10 Hz - 10 MHz
DRIVESTRENGTH = 1, Buffer
connection, 10 Hz - 1 MHz
DRIVESTRENGTH = 0, Buffer
connection, 10 Hz - 1 MHz
DRIVESTRENGTH = 3, 3x Gain
connection, 10 Hz - 10 MHz
DRIVESTRENGTH = 2, 3x Gain
connection, 10 Hz - 10 MHz
DRIVESTRENGTH = 1, 3x Gain
connection, 10 Hz - 1 MHz
DRIVESTRENGTH = 0, 3x Gain
connection, 10 Hz - 1 MHz
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Slew rate5
SR
DRIVESTRENGTH = 3,
INCBW=13
—
4.7
—
V/μs
DRIVESTRENGTH = 3,
INCBW=0
—
—
1.5
—
—
V/μs
V/μs
DRIVESTRENGTH = 2,
INCBW=13
1.27
DRIVESTRENGTH = 2,
INCBW=0
—
—
0.42
0.17
—
—
V/μs
V/μs
DRIVESTRENGTH = 1,
INCBW=13
DRIVESTRENGTH = 1,
INCBW=0
—
—
0.058
0.044
—
—
V/μs
V/μs
DRIVESTRENGTH = 0,
INCBW=13
DRIVESTRENGTH = 0,
INCBW=0
—
0.015
—
V/μs
Startup time6
TSTART
VOSI
DRIVESTRENGTH = 2
—
-2
—
—
12
2
μs
Input offset voltage
DRIVESTRENGTH = 2 or 3, T =
25 °C
mV
DRIVESTRENGTH = 1 or 0, T =
25 °C
-2
—
—
2
mV
mV
DRIVESTRENGTH = 2 or 3,
across operating temperature
range
-12
12
DRIVESTRENGTH = 1 or 0,
across operating temperature
range
-30
—
30
mV
DC power supply rejection
ratio9
PSRRDC
Input referred
—
—
—
70
70
90
—
—
—
dB
dB
dB
DC common-mode rejection CMRRDC
ratio9
Input referred
Total harmonic distortion
THDOPA
DRIVESTRENGTH = 2, 3x Gain
connection, 1 kHz, VOUT = 0.1 V
to VOPA - 0.1 V
DRIVESTRENGTH = 0, 3x Gain
connection, 0.1 kHz, VOUT = 0.1 V
to VOPA - 0.1 V
—
90
—
dB
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
Parameter
Note:
Symbol
Test Condition
Min
Typ
Max
Unit
1. Specified configuration for 3X-Gain configuration is: INCBW = 1, HCMDIS = 1, RESINSEL = VSS, VINPUT = 0.5 V, VOUTPUT = 1.5
V. Nominal voltage gain is 3.
2. If the maximum CLOAD is exceeded, an isolation resistor is required for stability. See AN0038 for more information.
3. When INCBW is set to 1 the OPAMP bandwidth is increased. This is allowed only when the non-inverting close-loop gain is ≥ 3,
or the OPAMP may not be stable.
4. Current into the load resistor is excluded. When the OPAMP is connected with closed-loop gain > 1, there will be extra current to
drive the resistor feedback network. The internal resistor feedback network has total resistance of 143.5 kOhm, which will cause
another ~10 μA current when the OPAMP drives 1.5 V between output and ground.
5. Step between 0.2V and VOPA-0.2V, 10%-90% rising/falling range.
6. From enable to output settled. In sample-and-off mode, RC network after OPAMP will contribute extra delay. Settling error < 1mV.
7. In unit gain connection, UGF is the gain-bandwidth product of the OPAMP. In 3x Gain connection, UGF is the gain-bandwidth
product of the OPAMP and 1/3 attenuation of the feedback network.
8. Specified configuration for Unit gain buffer configuration is: INCBW = 0, HCMDIS = 0, RESINSEL = DISABLE. VINPUT = 0.5 V,
VOUTPUT = 0.5 V.
9. When HCMDIS=1 and input common mode transitions the region from VOPA-1.4V to VOPA-1V, input offset will change. PSRR
and CMRR specifications do not apply to this transition region.
4.1.22 Pulse Counter (PCNT)
Table 4.48. Pulse Counter (PCNT)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Input frequency
FIN
Asynchronous Single and Quad-
rature Modes
—
—
20
MHz
Sampled Modes with Debounce
filter set to 0.
—
—
8
kHz
4.1.23 Analog Port (APORT)
Table 4.49. Analog Port (APORT)
Parameter
Symbol
Test Condition
Min
—
Typ
7
Max
—
Unit
μA
Supply current2 1
IAPORT
Operation in EM0/EM1
Operation in EM2/EM3
—
915
—
nA
Note:
1. Specified current is for continuous APORT operation. In applications where the APORT is not requested continuously (e.g. peri-
odic ACMP requests from LESENSE in EM2), the average current requirements can be estimated by mutiplying the duty cycle of
the requests by the specified continuous current number.
2. Supply current increase that occurs when an analog peripheral requests access to APORT. This current is not included in repor-
ted module currents. Additional peripherals requesting access to APORT do not incur further current.
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
4.1.24 I2C
4.1.24.1 I2C Standard-mode (Sm)1
Table 4.50. I2C Standard-mode (Sm)1
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SCL clock frequency2
SCL clock low time
SCL clock high time
SDA set-up time
fSCL
0
—
100
kHz
tLOW
4.7
4
—
—
—
—
—
—
—
μs
μs
ns
ns
μs
tHIGH
tSU_DAT
tHD_DAT
250
100
4.7
—
SDA hold time3
3450
—
Repeated START condition tSU_STA
set-up time
(Repeated) START condition tHD_STA
hold time
4
—
—
μs
STOP condition set-up time tSU_STO
4
—
—
—
—
μs
μs
Bus free time between a
tBUF
4.7
STOP and START condition
Note:
1. For CLHR set to 0 in the I2Cn_CTRL register.
2. For the minimum HFPERCLK frequency required in Standard-mode, refer to the I2C chapter in the reference manual.
3. The maximum SDA hold time (tHD_DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW).
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
4.1.24.2 I2C Fast-mode (Fm)1
Table 4.51. I2C Fast-mode (Fm)1
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SCL clock frequency2
SCL clock low time
SCL clock high time
SDA set-up time
fSCL
0
—
400
kHz
tLOW
1.3
0.6
—
—
—
—
—
—
—
μs
μs
ns
ns
μs
tHIGH
tSU_DAT
tHD_DAT
100
100
0.6
—
SDA hold time3
900
—
Repeated START condition tSU_STA
set-up time
(Repeated) START condition tHD_STA
hold time
0.6
—
—
μs
STOP condition set-up time tSU_STO
0.6
1.3
—
—
—
—
μs
μs
Bus free time between a
tBUF
STOP and START condition
Note:
1. For CLHR set to 1 in the I2Cn_CTRL register.
2. For the minimum HFPERCLK frequency required in Fast-mode, refer to the I2C chapter in the reference manual.
3. The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW).
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
4.1.24.3 I2C Fast-mode Plus (Fm+)1
Table 4.52. I2C Fast-mode Plus (Fm+)1
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SCL clock frequency2
SCL clock low time
SCL clock high time
SDA set-up time
fSCL
0
—
1000
kHz
tLOW
0.5
0.26
50
—
—
—
—
—
—
—
—
—
—
μs
μs
ns
ns
μs
tHIGH
tSU_DAT
tHD_DAT
SDA hold time
100
0.26
Repeated START condition tSU_STA
set-up time
(Repeated) START condition tHD_STA
hold time
0.26
—
—
μs
STOP condition set-up time tSU_STO
0.26
0.5
—
—
—
—
μs
μs
Bus free time between a
tBUF
STOP and START condition
Note:
1. For CLHR set to 0 or 1 in the I2Cn_CTRL register.
2. For the minimum HFPERCLK frequency required in Fast-mode Plus, refer to the I2C chapter in the reference manual.
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
4.1.25 USART SPI
SPI Master Timing
Table 4.53. SPI Master Timing
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SCLK period 1 3 2
tSCLK
2 *
tHFPERCLK
—
—
ns
CS to MOSI 1 3
tCS_MO
tSCLK_MO
tSU_MI
-14.5
-8.5
—
—
13.5
8
ns
ns
SCLK to MOSI 1 3
MISO setup time 1 3
IOVDD = 1.62 V
IOVDD = 3.0 V
92
42
—
—
—
—
—
—
ns
ns
ns
MISO hold time 1 3
tH_MI
-10
Note:
1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0).
2. tHFPERCLK is one period of the selected HFPERCLK.
3. Measurement done with 8 pF output loading at 10% and 90% of VDD (figure shows 50% of VDD).
tCS_MO
CS
tSCKL_MO
SCLK
CLKPOL = 0
tSCLK
SCLK
CLKPOL = 1
MOSI
MISO
tSU_MI
tH_MI
Figure 4.1. SPI Master Timing Diagram
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
SPI Slave Timing
Table 4.54. SPI Slave Timing
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SCLK period 1 3 2
tSCLK
6 *
tHFPERCLK
—
—
ns
SCLK high time1 3 2
SCLK low time1 3 2
tSCLK_HI
2.5 *
tHFPERCLK
—
—
—
—
ns
ns
tSCLK_LO
2.5 *
tHFPERCLK
CS active to MISO 1 3
CS disable to MISO 1 3
MOSI setup time 1 3
MOSI hold time 1 3 2
SCLK to MISO 1 3 2
tCS_ACT_MI
tCS_DIS_MI
tSU_MO
4
4
8
7
—
—
—
—
—
70
50
—
—
ns
ns
ns
ns
ns
tH_MO
tSCLK_MI
10 + 1.5 *
tHFPERCLK
65 + 2.5 *
tHFPERCLK
Note:
1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0).
2. tHFPERCLK is one period of the selected HFPERCLK.
3. Measurement done with 8 pF output loading at 10% and 90% of VDD (figure shows 50% of VDD).
tCS_ACT_MI
CS
tCS_DIS_MI
SCLK
CLKPOL = 0
tSCLK_HI
tSCLK_LO
SCLK
tSU_MO
CLKPOL = 1
tSCLK
tH_MO
MOSI
MISO
tSCLK_MI
Figure 4.2. SPI Slave Timing Diagram
4.2 Typical Performance Curves
Typical performance curves indicate typical characterized performance under the stated conditions.
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Electrical Specifications
4.2.1 Supply Current
Figure 4.3. EM0 Active Mode Typical Supply Current vs. Temperature
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Electrical Specifications
Figure 4.4. EM1 Sleep Mode Typical Supply Current vs. Temperature
Typical supply current for EM2, EM3 and EM4H using standard software libraries from Silicon Laboratories.
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Electrical Specifications
Figure 4.5. EM2, EM3, EM4H and EM4S Typical Supply Current vs. Temperature
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Electrical Specifications
Figure 4.6. EM0 and EM1 Mode Typical Supply Current vs. Supply
Typical supply current for EM2, EM3 and EM4H using standard software libraries from Silicon Laboratories.
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Electrical Specifications
Figure 4.7. EM2, EM3, EM4H and EM4S Typical Supply Current vs. Supply
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Electrical Specifications
4.2.2 DC-DC Converter
Default test conditions: CCM mode, LDCDC = 4.7 μH, CDCDC = 4.7 μF, VDCDC_I = 3.3 V, VDCDC_O = 1.8 V, FDCDC_LN = 7 MHz
Figure 4.8. DC-DC Converter Typical Performance Characteristics
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Electrical Specifications
Load Step Response in LN (CCM) mode
(Heavy Drive)
LN (CCM) and LP mode transition (load: 5mA)
DVDD
DVDD
20mV/div
offset:1.8V
60mV/div
offset:1.8V
100mA
ILOAD
1mA
VSW
2V/div
offset:1.8V
10μs/div
100μs/div
Figure 4.9. DC-DC Converter Transition Waveforms
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Electrical Specifications
4.2.3 2.4 GHz Radio
Figure 4.10. 2.4 GHz RF Transmitter Output Power
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Electrical Specifications
Figure 4.11. 2.4 GHz RF Receiver Sensitivity
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Typical Connection Diagrams
5. Typical Connection Diagrams
5.1 Power
Typical power supply connections for direct supply, without using the internal DC-DC converter, are shown in the following figure.
VDD
Main
Supply
+
–
VREGVDD
AVDD
IOVDD
VREGSW
HFXTAL_N
HFXTAL_P
LFXTAL_N
LFXTAL_P
VREGVSS
DVDD
DECOUPLE
RFVDD
PAVDD
Figure 5.1. EFR32FG12 Typical Application Circuit: Direct Supply Configuration without DC-DC converter
Typical power supply circuits using the internal DC-DC converter are shown below. The MCU operates from the DC-DC converter sup-
ply. For low RF transmit power applications less than 13dBm, the RF PA may be supplied by the DC-DC converter. For OPNs support-
ing high power RF transmission, the RF PA must be directly supplied by VDD for RF transmit power greater than 13 dBm.
VDD
Main
Supply
+
–
VREGVDD
AVDD
IOVDD
VDCDC
VREGSW
HFXTAL_N
HFXTAL_P
LFXTAL_N
LFXTAL_P
VREGVSS
DVDD
DECOUPLE
RFVDD
PAVDD
Figure 5.2. EFR32FG12 Typical Application Circuit: Configuration with DC-DC converter (PAVDD from VDCDC)
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Typical Connection Diagrams
VDD
Main
Supply
+
–
VREGVDD
AVDD
IOVDD
VDCDC
VREGSW
HFXTAL_N
HFXTAL_P
LFXTAL_N
LFXTAL_P
VREGVSS
DVDD
DECOUPLE
RFVDD
PAVDD
Figure 5.3. EFR32FG12 Typical Application Circuit: Configuration with DC-DC converter (PAVDD from VDD)
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Typical Connection Diagrams
5.2 RF Matching Networks
Typical RF matching network circuit diagrams are shown in Figure 5.4 Typical 2.4 GHz RF impedance-matching network circuits on
page 107 for applications in the 2.4GHz band, and in Figure 5.5 Typical Sub-GHz RF impedance-matching network circuits on page
108 for applications in the sub-GHz band. Application-specific component values can be found in the EFR32 Reference Manual. For
low RF transmit power applications less than 13dBm, the two-element match is recommended. For OPNs supporting high power RF
transmission, the four-element match is recommended for high RF transmit power (> 13dBm).
Typical RF matching network circuit diagrams are shown in Figure 5.5 Typical Sub-GHz RF impedance-matching network circuits on
page 108 for applications in the sub-GHz band. Application-specific component values can be found in the EFR32 Reference Manual.
For low RF transmit power applications less than 13dBm, the two-element match is recommended. For OPNs supporting high power
RF transmission, the four-element match is recommended for high RF transmit power (> 13dBm).
4-Element Match for 2.4GHz Band
2-Element Match for 2.4GHz Band
PAVDD
PAVDD
PAVDD
PAVDD
2G4RF_IOP
2G4RF_ION
L0
L0
L1
2G4RF_IOP
2G4RF_ION
50Ω
50Ω
C0
C0
C1
Figure 5.4. Typical 2.4 GHz RF impedance-matching network circuits
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Typical Connection Diagrams
Sub-GHz Match Topology I (169-450 MHz)
PAVDD
L1
L2
C0
L3
C5
L5
L6
L7
SUBGRF_IN
SUBGRF_IP
50Ω
C2
C3
C4
C7
C8
C9
C10
L0
C1
L4
C6
BAL1
SUBGRF_ON
SUBGRF_OP
Sub-GHz Match Topology 2 (450-915 MHz)
C0
L0
L3
PAVDD
L5
L6
SUBGRF_IN
50Ω
C4
C7
C8
C9
SUBGRF_IP
L4
BAL1
C1
SUBGRF_ON
SUBGRF_OP
Figure 5.5. Typical Sub-GHz RF impedance-matching network circuits
5.3 Other Connections
Other components or connections may be required to meet the system-level requirements. Application Note AN0002: "Hardware De-
sign Considerations" contains detailed information on these connections. Application Notes can be accessed on the Silicon Labs web-
site (www.silabs.com/32bit-appnotes).
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
6. Pin Definitions
6.1 BGA125 2.4 GHz and Sub-GHz Device Pinout
Figure 6.1. BGA125 2.4 GHz and Sub-GHz Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the sup-
ported features for each GPIO pin, see 6.7 GPIO Functionality Table or 6.8 Alternate Functionality Overview.
Table 6.1. BGA125 2.4 GHz and Sub-GHz Device Pinout
Pin Name
PF3
Pins Description
A1 GPIO (5V)
A3 GPIO (5V)
A5 GPIO (5V)
A7 GPIO (5V)
Pin Name
PF1
Pins Description
A2 GPIO (5V)
A4 GPIO (5V)
A6 GPIO (5V)
A8 GPIO (5V)
PC5
PC3
PC0
PC11
PC7
PC9
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Pin Definitions
Pin Name
DECOUPLE
VREGVDD
VREGVSS
Pins Description
Decouple output for on-chip voltage regu-
A9 lator. An external decoupling capacitor is
required at this pin.
Pin Name
Pins Description
DVDD
VREGSW
PF8
A10 Digital power supply.
A12 DCDC regulator switching node
B1 GPIO (5V)
A11 Voltage regulator VDD input
A13
B11 Voltage regulator VSS
B12
PF2
PC4
PJ14
PC8
B2 GPIO (5V)
B4 GPIO (5V)
B6 GPIO (5V)
B8 GPIO (5V)
B10
PF0
PC1
B3 GPIO (5V)
B5 GPIO (5V)
B7 GPIO (5V)
B9 GPIO (5V)
PC10
PC6
F2
F11
IOVDD
Digital IO power supply.
AVDD
B13 Analog power supply.
M12
PF11
PF9
C1 GPIO (5V)
C3 GPIO (5V)
C6 GPIO (5V)
C11 GPIO
PF10
PC2
C2 GPIO (5V)
C5 GPIO (5V)
C10 GPIO
PJ15
PB14
PB12
PF13
PB11
PB9
PB15
PB13
PF14
PF12
PB10
PK1
C12 GPIO
C13 GPIO
D1 GPIO (5V)
D3 GPIO (5V)
D12 GPIO (5V)
E1 GPIO (5V)
E3 GPIO (5V)
D2 GPIO (5V)
D11 GPIO
D13 GPIO (5V)
E2 GPIO
PK0
PF15
E5
E6
E7
E8
E9
F5
F6
F7
F8
F9
G5
G6
G7
G8 Ground
G9
H5
H6
H7
H8
H9
J5
VSS
PB8
E12 GPIO (5V)
J6
J7
J8
J9
K2
L2
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
Pin Name
PB7
Pins Description
E13 GPIO (5V)
F12 GPIO (5V)
G1 GPIO (5V)
G11 GPIO (5V)
G13 GPIO (5V)
H2 GPIO (5V)
Pin Name
Pins Description
F1 GPIO (5V)
F13 GPIO (5V)
G2 GPIO (5V)
G12 GPIO (5V)
H1 GPIO (5V)
H12 GPIO (5V)
J1
PK2
PI3
PB6
PF5
PF4
PI1
PI2
PI0
PF7
PA9
PF6
PA8
H13 GPIO (5V)
RFVDD
Radio power supply
J2
PA7
PA5
PA4
J11 GPIO (5V)
J13 GPIO (5V)
K12 GPIO
PA6
HFXTAL_N
PA3
J12 GPIO (5V)
K1 High Frequency Crystal input pin.
K13 GPIO
Brown-Out Detector Enable. This pin may
L10
HFXTAL_P
PA2
L1 High Frequency Crystal output pin.
L12 GPIO
BODEN
PA1
be left disconnected or tied to AVDD.
L13 GPIO
Reset input, active low. To apply an exter-
nal reset source to this pin, it is required to
M1 only drive this pin low during reset, and let
the internal pull-up ensure that reset is re-
leased.
M2
M3
RESETn
PAVSS
RFVSS
M4 Radio Ground
M5
N5
M6 Power Amplifier (PA) voltage regulator
M7 VSS
M8 Power Amplifier (PA) voltage regulator
N8 VDD input
PAVDD
PD9
M9 GPIO (5V)
PD11
PA0
M10 GPIO (5V)
PD13
M11 GPIO
M13 GPIO
Sub GHz Differential RF output, positive
path.
Sub GHz Differential RF output, negative
path.
SUBGRF_OP N1
SUBGRF_ON N2
Sub GHz Differential RF input, positive
path.
Sub GHz Differential RF input, negative
path.
SUBGRF_IP
2G4RF_ION
N3
SUBGRF_IN
2G4RF_IOP
N4
N7
2.4 GHz Differential RF input/output, nega-
N6 tive path. This pin should be externally
grounded.
2.4 GHz Differential RF input/output, posi-
tive path.
PD8
PD12
N9 GPIO (5V)
N11 GPIO (5V)
N13 GPIO
PD10
PD14
N10 GPIO (5V)
N12 GPIO
PD15
Note:
1. GPIO with 5V tolerance are indicated by (5V).
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Pin Definitions
6.2 BGA125 2.4 GHz Device Pinout
Figure 6.2. BGA125 2.4 GHz Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the sup-
ported features for each GPIO pin, see 6.7 GPIO Functionality Table or 6.8 Alternate Functionality Overview.
Table 6.2. BGA125 2.4 GHz Device Pinout
Pin Name
PF3
Pins Description
A1 GPIO (5V)
A3 GPIO (5V)
A5 GPIO (5V)
A7 GPIO (5V)
Pin Name
PF1
Pins Description
A2 GPIO (5V)
A4 GPIO (5V)
A6 GPIO (5V)
A8 GPIO (5V)
PC5
PC3
PC0
PC11
PC7
PC9
Decouple output for on-chip voltage regu-
DECOUPLE
VREGVDD
A9 lator. An external decoupling capacitor is
required at this pin.
DVDD
A10 Digital power supply.
A11 Voltage regulator VDD input
VREGSW
A12 DCDC regulator switching node
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Pin Definitions
Pin Name
Pins Description
Pin Name
Pins Description
A13
VREGVSS
B11 Voltage regulator VSS
B12
PF8
B1 GPIO (5V)
PF2
PC4
PJ14
PC8
B2 GPIO (5V)
B4 GPIO (5V)
B6 GPIO (5V)
B8 GPIO (5V)
B10
PF0
PC1
B3 GPIO (5V)
B5 GPIO (5V)
B7 GPIO (5V)
B9 GPIO (5V)
PC10
PC6
F2
F11
IOVDD
Digital IO power supply.
AVDD
B13 Analog power supply.
M12
PF11
PF9
C1 GPIO (5V)
C3 GPIO (5V)
C6 GPIO (5V)
C11 GPIO
PF10
PC2
C2 GPIO (5V)
C5 GPIO (5V)
C10 GPIO
PJ15
PB14
PB12
PF13
PB11
PB9
PB15
PB13
PF14
PF12
PB10
PK1
C12 GPIO
C13 GPIO
D1 GPIO (5V)
D3 GPIO (5V)
D12 GPIO (5V)
E1 GPIO (5V)
E3 GPIO (5V)
D2 GPIO (5V)
D11 GPIO
D13 GPIO (5V)
E2 GPIO
PK0
PF15
E5
E6
E7
E8
E9
F5
F6
F7
F8
F9
G5
G6
G7
G8 Ground
G9
H5
H6
H7
H8
H9
J5
VSS
PB8
E12 GPIO (5V)
J6
J7
J8
J9
K2
L2
PB7
PB6
PF5
E13 GPIO (5V)
F12 GPIO (5V)
G1 GPIO (5V)
PK2
PI3
F1 GPIO (5V)
F13 GPIO (5V)
G2 GPIO (5V)
PF4
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Pin Definitions
Pin Name
PI2
Pins Description
G11 GPIO (5V)
G13 GPIO (5V)
H2 GPIO (5V)
Pin Name
Pins Description
G12 GPIO (5V)
H1 GPIO (5V)
H12 GPIO (5V)
J1
PI1
PF7
PA9
PI0
PF6
PA8
H13 GPIO (5V)
RFVDD
Radio power supply
J2
PA7
PA5
PA4
J11 GPIO (5V)
J13 GPIO (5V)
K12 GPIO
PA6
HFXTAL_N
PA3
J12 GPIO (5V)
K1 High Frequency Crystal input pin.
K13 GPIO
Brown-Out Detector Enable. This pin may
L10
HFXTAL_P
PA2
L1 High Frequency Crystal output pin.
L12 GPIO
BODEN
PA1
be left disconnected or tied to AVDD.
L13 GPIO
Reset input, active low. To apply an exter-
nal reset source to this pin, it is required to
M1 only drive this pin low during reset, and let
the internal pull-up ensure that reset is re-
leased.
M2
M3
RESETn
PAVSS
RFVSS
M4 Radio Ground
M5
N5
M6 Power Amplifier (PA) voltage regulator
M7 VSS
M8 Power Amplifier (PA) voltage regulator
N8 VDD input
PAVDD
PD9
M9 GPIO (5V)
M11 GPIO
N1
PD11
PA0
M10 GPIO (5V)
M13 GPIO
PD13
2.4 GHz Differential RF input/output, nega-
N6 tive path. This pin should be externally
grounded.
N2
N3
N4
NC
No Connect.
2G4RF_ION
2.4 GHz Differential RF input/output, posi-
tive path.
2G4RF_IOP
N7
PD8
N9 GPIO (5V)
PD10
PD14
N10 GPIO (5V)
N12 GPIO
PD12
PD15
N11 GPIO (5V)
N13 GPIO
Note:
1. GPIO with 5V tolerance are indicated by (5V).
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Pin Definitions
6.3 BGA125 Sub-GHz Device Pinout
Figure 6.3. BGA125 Sub-GHz Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the sup-
ported features for each GPIO pin, see 6.7 GPIO Functionality Table or 6.8 Alternate Functionality Overview.
Table 6.3. BGA125 Sub-GHz Device Pinout
Pin Name
PF3
Pins Description
A1 GPIO (5V)
A3 GPIO (5V)
A5 GPIO (5V)
A7 GPIO (5V)
Pin Name
PF1
Pins Description
A2 GPIO (5V)
A4 GPIO (5V)
A6 GPIO (5V)
A8 GPIO (5V)
PC5
PC3
PC0
PC11
PC7
PC9
Decouple output for on-chip voltage regu-
DECOUPLE
VREGVDD
A9 lator. An external decoupling capacitor is
required at this pin.
DVDD
A10 Digital power supply.
A11 Voltage regulator VDD input
VREGSW
A12 DCDC regulator switching node
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
Pin Name
Pins Description
Pin Name
Pins Description
A13
VREGVSS
B11 Voltage regulator VSS
B12
PF8
B1 GPIO (5V)
PF2
PC4
PJ14
PC8
B2 GPIO (5V)
B4 GPIO (5V)
B6 GPIO (5V)
B8 GPIO (5V)
B10
PF0
PC1
B3 GPIO (5V)
B5 GPIO (5V)
B7 GPIO (5V)
B9 GPIO (5V)
PC10
PC6
F2
F11
IOVDD
Digital IO power supply.
AVDD
B13 Analog power supply.
M12
PF11
PF9
C1 GPIO (5V)
C3 GPIO (5V)
C6 GPIO (5V)
C11 GPIO
PF10
PC2
C2 GPIO (5V)
C5 GPIO (5V)
C10 GPIO
PJ15
PB14
PB12
PF13
PB11
PB9
PB15
PB13
PF14
PF12
PB10
PK1
C12 GPIO
C13 GPIO
D1 GPIO (5V)
D3 GPIO (5V)
D12 GPIO (5V)
E1 GPIO (5V)
E3 GPIO (5V)
D2 GPIO (5V)
D11 GPIO
D13 GPIO (5V)
E2 GPIO
PK0
PF15
E5
E6
E7
E8
E9
F5
F6
F7
F8
F9
G5
G6
G7
G8
G9 Ground
H5
H6
H7
H8
H9
J5
VSS
PB8
E12 GPIO (5V)
J6
J7
J8
J9
K2
L2
M6
M7
PB7
PB6
E13 GPIO (5V)
F12 GPIO (5V)
PK2
PI3
F1 GPIO (5V)
F13 GPIO (5V)
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Pin Definitions
Pin Name
PF5
Pins Description
G1 GPIO (5V)
G11 GPIO (5V)
G13 GPIO (5V)
H2 GPIO (5V)
Pin Name
Pins Description
G2 GPIO (5V)
G12 GPIO (5V)
H1 GPIO (5V)
H12 GPIO (5V)
J1
PF4
PI1
PI2
PI0
PF7
PA9
PF6
PA8
H13 GPIO (5V)
RFVDD
Radio power supply
J2
PA7
PA5
PA4
J11 GPIO (5V)
J13 GPIO (5V)
K12 GPIO
PA6
HFXTAL_N
PA3
J12 GPIO (5V)
K1 High Frequency Crystal input pin.
K13 GPIO
Brown-Out Detector Enable. This pin may
L10
HFXTAL_P
PA2
L1 High Frequency Crystal output pin.
L12 GPIO
BODEN
PA1
be left disconnected or tied to AVDD.
L13 GPIO
Reset input, active low. To apply an exter-
nal reset source to this pin, it is required to
M1 only drive this pin low during reset, and let
the internal pull-up ensure that reset is re-
leased.
M2
M3
RESETn
NC
RFVSS
M4 Radio Ground
M5
N5
M8
N6
N7
No Connect.
PD9
M9 GPIO (5V)
N8
PD11
PA0
M10 GPIO (5V)
PD13
M11 GPIO
Sub GHz Differential RF output, positive
path.
M13 GPIO
SUBGRF_OP N1
Sub GHz Differential RF output, negative
path.
Sub GHz Differential RF input, positive
path.
SUBGRF_ON N2
SUBGRF_IP
PD8
N3
Sub GHz Differential RF input, negative
path.
SUBGRF_IN
N4
N9 GPIO (5V)
PD10
PD14
N10 GPIO (5V)
N12 GPIO
PD12
PD15
N11 GPIO (5V)
N13 GPIO
Note:
1. GPIO with 5V tolerance are indicated by (5V).
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Pin Definitions
6.4 QFN48 2.4 GHz and Sub-GHz Device Pinout
Figure 6.4. QFN48 2.4 GHz and Sub-GHz Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the sup-
ported features for each GPIO pin, see 6.7 GPIO Functionality Table or 6.8 Alternate Functionality Overview.
Table 6.4. QFN48 2.4 GHz and Sub-GHz Device Pinout
Pin Name
VSS
Pins Description
Pin Name
PF0
Pins Description
0
2
4
6
8
Ground
1
3
5
7
9
GPIO (5V)
PF1
GPIO (5V)
GPIO (5V)
GPIO (5V)
GPIO (5V)
PF2
GPIO (5V)
PF3
PF4
GPIO (5V)
PF5
PF6
GPIO (5V)
PF7
RFVDD
HFXTAL_P
Radio power supply
HFXTAL_N
10 High Frequency Crystal input pin.
11 High Frequency Crystal output pin.
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
Pin Name
Pins Description
Reset input, active low. To apply an exter-
Pin Name
Pins Description
nal reset source to this pin, it is required to
12 only drive this pin low during reset, and let
the internal pull-up ensure that reset is re-
leased.
Sub GHz Differential RF output, positive
path.
RESETn
SUBGRF_OP 13
Sub GHz Differential RF output, negative
path.
Sub GHz Differential RF input, positive
path.
SUBGRF_ON 14
SUBGRF_IP
RFVSS
15
Sub GHz Differential RF input, negative
path.
SUBGRF_IN
PAVSS
16
18
20
17 Radio Ground
2.4 GHz Differential RF input/output, nega-
19 tive path. This pin should be externally
grounded.
Power Amplifier (PA) voltage regulator
VSS
2G4RF_ION
PAVDD
2.4 GHz Differential RF input/output, posi-
tive path.
Power Amplifier (PA) voltage regulator
VDD input
2G4RF_IOP
21
PD13
PD15
PA1
22 GPIO
PD14
PA0
23 GPIO
24 GPIO
25 GPIO
26 GPIO
PA2
27 GPIO
PA3
28 GPIO
PA4
29 GPIO
PA5
30 GPIO (5V)
32 GPIO
PB11
31 GPIO
PB12
AVDD
PB15
VREGSW
PB13
33 GPIO
34 Analog power supply.
36 GPIO
PB14
35 GPIO
VREGVSS
VREGVDD
37 Voltage regulator VSS
39 Voltage regulator VDD input
38 DCDC regulator switching node
Decouple output for on-chip voltage regu-
41 lator. An external decoupling capacitor is
required at this pin.
DVDD
40 Digital power supply.
DECOUPLE
IOVDD
PC7
42 Digital IO power supply.
44 GPIO (5V)
PC6
PC8
43 GPIO (5V)
45 GPIO (5V)
47 GPIO (5V)
PC9
46 GPIO (5V)
PC10
PC11
Note:
48 GPIO (5V)
1. GPIO with 5V tolerance are indicated by (5V).
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
6.5 QFN48 2.4 GHz Device Pinout
Figure 6.5. QFN48 2.4 GHz Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the sup-
ported features for each GPIO pin, see 6.7 GPIO Functionality Table or 6.8 Alternate Functionality Overview.
Table 6.5. QFN48 2.4 GHz Device Pinout
Pin Name
VSS
Pins Description
Pin Name
PF0
Pins Description
0
2
4
6
8
Ground
1
3
5
7
9
GPIO (5V)
PF1
GPIO (5V)
GPIO (5V)
GPIO (5V)
GPIO (5V)
PF2
GPIO (5V)
PF3
PF4
GPIO (5V)
PF5
PF6
GPIO (5V)
PF7
RFVDD
HFXTAL_P
Radio power supply
HFXTAL_N
10 High Frequency Crystal input pin.
11 High Frequency Crystal output pin.
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
Pin Name
Pins Description
Reset input, active low. To apply an exter-
Pin Name
Pins Description
nal reset source to this pin, it is required to
12 only drive this pin low during reset, and let
the internal pull-up ensure that reset is re-
leased.
RESETn
NC
13 No Connect.
Power Amplifier (PA) voltage regulator
VSS
RFVSS
2G4RF_ION
PAVDD
14 Radio Ground
PAVSS
2G4RF_IOP
PD10
15
17
2.4 GHz Differential RF input/output, nega-
16 tive path. This pin should be externally
grounded.
2.4 GHz Differential RF input/output, posi-
tive path.
Power Amplifier (PA) voltage regulator
VDD input
18
19 GPIO (5V)
PD11
PD13
PD15
PA1
20 GPIO (5V)
22 GPIO
PD12
PD14
21 GPIO (5V)
23 GPIO
24 GPIO
PA0
25 GPIO
26 GPIO
PA2
27 GPIO
PA3
28 GPIO
PA4
29 GPIO
PA5
30 GPIO (5V)
32 GPIO
PB11
31 GPIO
PB12
AVDD
PB15
VREGSW
PB13
33 GPIO
34 Analog power supply.
36 GPIO
PB14
35 GPIO
VREGVSS
VREGVDD
37 Voltage regulator VSS
39 Voltage regulator VDD input
38 DCDC regulator switching node
Decouple output for on-chip voltage regu-
41 lator. An external decoupling capacitor is
required at this pin.
DVDD
40 Digital power supply.
DECOUPLE
IOVDD
PC7
42 Digital IO power supply.
44 GPIO (5V)
PC6
PC8
43 GPIO (5V)
45 GPIO (5V)
47 GPIO (5V)
PC9
46 GPIO (5V)
PC10
PC11
48 GPIO (5V)
Note:
1. GPIO with 5V tolerance are indicated by (5V).
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
6.6 QFN48 Sub-GHz Device Pinout
Figure 6.6. QFN48 Sub-GHz Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the sup-
ported features for each GPIO pin, see 6.7 GPIO Functionality Table or 6.8 Alternate Functionality Overview.
Table 6.6. QFN48 Sub-GHz Device Pinout
Pin Name
VSS
Pins Description
Pin Name
PF0
Pins Description
0
2
4
6
8
Ground
1
3
5
7
9
GPIO (5V)
PF1
GPIO (5V)
GPIO (5V)
GPIO (5V)
GPIO (5V)
PF2
GPIO (5V)
PF3
PF4
GPIO (5V)
PF5
PF6
GPIO (5V)
PF7
RFVDD
HFXTAL_P
Radio power supply
HFXTAL_N
10 High Frequency Crystal input pin.
11 High Frequency Crystal output pin.
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
Pin Name
Pins Description
Reset input, active low. To apply an exter-
Pin Name
Pins Description
nal reset source to this pin, it is required to
12 only drive this pin low during reset, and let
the internal pull-up ensure that reset is re-
leased.
Sub GHz Differential RF output, positive
path.
RESETn
SUBGRF_OP 13
Sub GHz Differential RF output, negative
path.
Sub GHz Differential RF input, positive
path.
SUBGRF_ON 14
SUBGRF_IP
RFVSS
15
Sub GHz Differential RF input, negative
path.
SUBGRF_IN
16
17 Radio Ground
PD9
PD11
PD13
PD15
PA1
18 GPIO (5V)
20 GPIO (5V)
22 GPIO
PD10
PD12
19 GPIO (5V)
21 GPIO (5V)
23 GPIO
PD14
24 GPIO
PA0
25 GPIO
26 GPIO
PA2
27 GPIO
PA3
28 GPIO
PA4
29 GPIO
PA5
30 GPIO (5V)
32 GPIO
PB11
31 GPIO
PB12
AVDD
PB15
VREGSW
PB13
33 GPIO
34 Analog power supply.
36 GPIO
PB14
35 GPIO
VREGVSS
VREGVDD
37 Voltage regulator VSS
39 Voltage regulator VDD input
38 DCDC regulator switching node
Decouple output for on-chip voltage regu-
41 lator. An external decoupling capacitor is
required at this pin.
DVDD
40 Digital power supply.
DECOUPLE
IOVDD
PC7
42 Digital IO power supply.
44 GPIO (5V)
PC6
PC8
43 GPIO (5V)
45 GPIO (5V)
47 GPIO (5V)
PC9
46 GPIO (5V)
PC10
PC11
48 GPIO (5V)
Note:
1. GPIO with 5V tolerance are indicated by (5V).
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
6.7 GPIO Functionality Table
A wide selection of alternate functionality is available for multiplexing to various pins. The following table shows the name of each GPIO
pin, followed by the functionality available on that pin. Refer to 6.8 Alternate Functionality Overview for a list of GPIO locations available
for each function.
Table 6.7. GPIO Functionality Table
GPIO Name
Pin Alternate Functionality / Description
Analog
Timers
Communication
Radio
Other
US0_TX #27
US0_RX #26
US0_CLK #25
US0_CS #24
US0_CTS #23
US0_RTS #22
US1_TX #27
US1_RX #26
US1_CLK #25
US1_CS #24
US1_CTS #23
US1_RTS #22
US2_TX #16
US2_RX #15
US2_CLK #14
US2_CS #13
US2_CTS #12
US2_RTS #11
LEU0_TX #27
LEU0_RX #26
I2C0_SDA #27
I2C0_SCL #26
TIM0_CC0 #27
TIM0_CC1 #26
TIM0_CC2 #25
TIM0_CDTI0 #24
TIM0_CDTI1 #23
TIM0_CDTI2 #22
TIM1_CC0 #27
TIM1_CC1 #26
TIM1_CC2 #25
TIM1_CC3 #24
WTIM0_CDTI2 #31
WTIM1_CC0 #27
WTIM1_CC1 #25
WTIM1_CC2 #23
WTIM1_CC3 #21 LE-
TIM0_OUT0 #27 LE-
TIM0_OUT1 #26
PCNT0_S0IN #27
PCNT0_S1IN #26
FRC_DCLK #27
FRC_DOUT #26
CMU_CLK1 #6
PRS_CH0 #3
PRS_CH1 #2
PRS_CH2 #1
PRS_CH3 #0
ACMP0_O #27
ACMP1_O #27
DBG_TDI
FRC_DFRAME #25
MODEM_DCLK #27
MODEM_DIN #26
MODEM_DOUT #25
MODEM_ANT0 #24
MODEM_ANT1 #23
PF3
BUSAY BUSBX
US0_TX #25
US0_RX #24
US0_CLK #23
US0_CS #22
US0_CTS #21
US0_RTS #20
US1_TX #25
US1_RX #24
US1_CLK #23
US1_CS #22
US1_CTS #21
US1_RTS #20
US2_TX #15
US2_RX #14
US2_CLK #13
US2_CS #12
US2_CTS #11
US2_RTS #10
LEU0_TX #25
LEU0_RX #24
I2C0_SDA #25
I2C0_SCL #24
TIM0_CC0 #25
TIM0_CC1 #24
TIM0_CC2 #23
TIM0_CDTI0 #22
TIM0_CDTI1 #21
TIM0_CDTI2 #20
TIM1_CC0 #25
TIM1_CC1 #24
TIM1_CC2 #23
TIM1_CC3 #22
WTIM0_CDTI1 #31
WTIM0_CDTI2 #29
WTIM1_CC0 #25
WTIM1_CC1 #23
WTIM1_CC2 #21
WTIM1_CC3 #19 LE-
TIM0_OUT0 #25 LE-
TIM0_OUT1 #24
PCNT0_S0IN #25
PCNT0_S1IN #24
FRC_DCLK #25
FRC_DOUT #24
PRS_CH0 #1
PRS_CH1 #0
PRS_CH2 #7
PRS_CH3 #6
ACMP0_O #25
ACMP1_O #25
DBG_SWDIOTMS
BOOT_RX
FRC_DFRAME #23
MODEM_DCLK #25
MODEM_DIN #24
MODEM_DOUT #23
MODEM_ANT0 #22
MODEM_ANT1 #21
PF1
BUSAY BUSBX
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
Timers
Communication
Radio
Other
WTIM0_CC0 #25
WTIM0_CC1 #23
WTIM0_CC2 #21
WTIM0_CDTI0 #17
WTIM0_CDTI1 #15
WTIM0_CDTI2 #13
WTIM1_CC0 #9
WTIM1_CC1 #7
WTIM1_CC2 #5
WTIM1_CC3 #3
PCNT1_S0IN #18
PCNT1_S1IN #17
PCNT2_S0IN #18
PCNT2_S1IN #17
US3_TX #23
US3_RX #22
US3_CLK #21
US3_CS #20
US3_CTS #19
US3_RTS #18
I2C1_SDA #18
I2C1_SCL #17
PC5
BUSAY BUSBX
WTIM0_CC0 #23
WTIM0_CC1 #21
WTIM0_CC2 #19
WTIM0_CDTI0 #15
WTIM0_CDTI1 #13
WTIM0_CDTI2 #11
WTIM1_CC0 #7
WTIM1_CC1 #5
WTIM1_CC2 #3
WTIM1_CC3 #1
PCNT1_S0IN #16
PCNT1_S1IN #15
PCNT2_S0IN #16
PCNT2_S1IN #15
US3_TX #21
US3_RX #20
US3_CLK #19
US3_CS #18
US3_CTS #17
US3_RTS #16
I2C1_SDA #16
I2C1_SCL #15
PC3
BUSAY BUSBX
WTIM0_CC0 #20
WTIM0_CC1 #18
WTIM0_CC2 #16
WTIM0_CDTI0 #12
WTIM0_CDTI1 #10
WTIM0_CDTI2 #8
WTIM1_CC0 #4
WTIM1_CC1 #2
WTIM1_CC2 #0
PCNT1_S0IN #13
PCNT1_S1IN #12
PCNT2_S0IN #13
PCNT2_S1IN #12
US3_TX #18
US3_RX #17
US3_CLK #16
US3_CS #15
US3_CTS #14
US3_RTS #13
I2C1_SDA #13
I2C1_SCL #12
PC0
BUSBY BUSAX
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
Timers
Communication
Radio
Other
TIM0_CC0 #16
TIM0_CC1 #15
TIM0_CC2 #14
TIM0_CDTI0 #13
TIM0_CDTI1 #12
TIM0_CDTI2 #11
TIM1_CC0 #16
TIM1_CC1 #15
TIM1_CC2 #14
US0_TX #16
US0_RX #15
US0_CLK #14
US0_CS #13
US0_CTS #12
US0_RTS #11
US1_TX #16
US1_RX #15
US1_CLK #14
US1_CS #13
US1_CTS #12
US1_RTS #11
LEU0_TX #16
LEU0_RX #15
I2C0_SDA #16
I2C0_SCL #15
I2C1_SDA #20
I2C1_SCL #19
TIM1_CC3 #13
FRC_DCLK #16
FRC_DOUT #15
CMU_CLK0 #3
PRS_CH0 #13
PRS_CH9 #16
PRS_CH10 #5
PRS_CH11 #4
ACMP0_O #16
ACMP1_O #16
DBG_SWO #3
WTIM0_CC0 #31
WTIM0_CC1 #29
WTIM0_CC2 #27
WTIM0_CDTI0 #23
WTIM0_CDTI1 #21
WTIM0_CDTI2 #19
WTIM1_CC0 #15
WTIM1_CC1 #13
WTIM1_CC2 #11
WTIM1_CC3 #9 LE-
TIM0_OUT0 #16 LE-
TIM0_OUT1 #15
PCNT0_S0IN #16
PCNT0_S1IN #15
PCNT2_S0IN #20
PCNT2_S1IN #19
FRC_DFRAME #14
MODEM_DCLK #16
MODEM_DIN #15
MODEM_DOUT #14
MODEM_ANT0 #13
MODEM_ANT1 #12
PC11
BUSAY BUSBX
TIM0_CC0 #14
TIM0_CC1 #13
TIM0_CC2 #12
TIM0_CDTI0 #11
TIM0_CDTI1 #10
TIM0_CDTI2 #9
TIM1_CC0 #14
TIM1_CC1 #13
TIM1_CC2 #12
US0_TX #14
US0_RX #13
US0_CLK #12
US0_CS #11
US0_CTS #10
US0_RTS #9
US1_TX #14
US1_RX #13
US1_CLK #12
US1_CS #11
US1_CTS #10
US1_RTS #9
LEU0_TX #14
LEU0_RX #13
I2C0_SDA #14
I2C0_SCL #13
FRC_DCLK #14
FRC_DOUT #13
PRS_CH0 #11
PRS_CH9 #14
PRS_CH10 #3
PRS_CH11 #2
ACMP0_O #14
ACMP1_O #14
ETM_TD2 #3
TIM1_CC3 #11
WTIM0_CC0 #29
WTIM0_CC1 #27
WTIM0_CC2 #25
WTIM0_CDTI0 #21
WTIM0_CDTI1 #19
WTIM0_CDTI2 #17
WTIM1_CC0 #13
WTIM1_CC1 #11
WTIM1_CC2 #9
WTIM1_CC3 #7 LE-
TIM0_OUT0 #14 LE-
TIM0_OUT1 #13
PCNT0_S0IN #14
PCNT0_S1IN #13
FRC_DFRAME #12
MODEM_DCLK #14
MODEM_DIN #13
MODEM_DOUT #12
MODEM_ANT0 #11
MODEM_ANT1 #10
PC9
BUSAY BUSBX
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
Timers
Communication
Radio
Other
TIM0_CC0 #12
TIM0_CC1 #11
TIM0_CC2 #10
TIM0_CDTI0 #9
TIM0_CDTI1 #8
TIM0_CDTI2 #7
TIM1_CC0 #12
US0_TX #12
US0_RX #11
US0_CLK #10
US0_CS #9
TIM1_CC1 #11
TIM1_CC2 #10
TIM1_CC3 #9
US0_CTS #8
US0_RTS #7
US1_TX #12
US1_RX #11
US1_CLK #10
US1_CS #9
US1_CTS #8
US1_RTS #7
LEU0_TX #12
LEU0_RX #11
I2C0_SDA #12
I2C0_SCL #11
FRC_DCLK #12
FRC_DOUT #11
CMU_CLK1 #2
PRS_CH0 #9
PRS_CH9 #12
PRS_CH10 #1
PRS_CH11 #0
ACMP0_O #12
ACMP1_O #12
ETM_TD0 #3
WTIM0_CC0 #27
WTIM0_CC1 #25
WTIM0_CC2 #23
WTIM0_CDTI0 #19
WTIM0_CDTI1 #17
WTIM0_CDTI2 #15
WTIM1_CC0 #11
WTIM1_CC1 #9
WTIM1_CC2 #7
WTIM1_CC3 #5 LE-
TIM0_OUT0 #12 LE-
TIM0_OUT1 #11
PCNT0_S0IN #12
PCNT0_S1IN #11
FRC_DFRAME #10
MODEM_DCLK #12
MODEM_DIN #11
MODEM_DOUT #10
MODEM_ANT0 #9
MODEM_ANT1 #8
PC7
BUSAY BUSBX
US2_TX #21
US2_RX #20
US2_CLK #19
US2_CS #18
US2_CTS #17
US2_RTS #16
I2C1_SDA #21
I2C1_SCL #20
WTIM1_CC1 #30
WTIM1_CC2 #28
WTIM1_CC3 #26
PCNT1_S0IN #21
PCNT1_S1IN #20
PCNT2_S0IN #21
PCNT2_S1IN #20
PF8
BUSBY BUSAX
ETM_TCLK #0
TIM0_CC0 #26
TIM0_CC1 #25
TIM0_CC2 #24
TIM0_CDTI0 #23
TIM0_CDTI1 #22
TIM0_CDTI2 #21
TIM1_CC0 #26
TIM1_CC1 #25
TIM1_CC2 #24
TIM1_CC3 #23
WTIM0_CDTI2 #30
WTIM1_CC0 #26
WTIM1_CC1 #24
WTIM1_CC2 #22
WTIM1_CC3 #20 LE-
TIM0_OUT0 #26 LE-
TIM0_OUT1 #25
PCNT0_S0IN #26
PCNT0_S1IN #25
US0_TX #26
US0_RX #25
US0_CLK #24
US0_CS #23
US0_CTS #22
US0_RTS #21
US1_TX #26
US1_RX #25
US1_CLK #24
US1_CS #23
US1_CTS #22
US1_RTS #21
LEU0_TX #26
LEU0_RX #25
I2C0_SDA #26
I2C0_SCL #25
CMU_CLK0 #6
PRS_CH0 #2
PRS_CH1 #1
PRS_CH2 #0
PRS_CH3 #7
ACMP0_O #26
ACMP1_O #26
DBG_TDO
FRC_DCLK #26
FRC_DOUT #25
FRC_DFRAME #24
MODEM_DCLK #26
MODEM_DIN #25
MODEM_DOUT #24
MODEM_ANT0 #23
MODEM_ANT1 #22
PF2
BUSBY BUSAX
DBG_SWO #0
GPIO_EM4WU0
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
Timers
Communication
Radio
Other
US0_TX #24
US0_RX #23
US0_CLK #22
US0_CS #21
US0_CTS #20
US0_RTS #19
US1_TX #24
US1_RX #23
US1_CLK #22
US1_CS #21
US1_CTS #20
US1_RTS #19
US2_TX #14
US2_RX #13
US2_CLK #12
US2_CS #11
US2_CTS #10
US2_RTS #9
LEU0_TX #24
LEU0_RX #23
I2C0_SDA #24
I2C0_SCL #23
TIM0_CC0 #24
TIM0_CC1 #23
TIM0_CC2 #22
TIM0_CDTI0 #21
TIM0_CDTI1 #20
TIM0_CDTI2 #19
TIM1_CC0 #24
TIM1_CC1 #23
TIM1_CC2 #22
TIM1_CC3 #21
WTIM0_CDTI1 #30
WTIM0_CDTI2 #28
WTIM1_CC0 #24
WTIM1_CC1 #22
WTIM1_CC2 #20
WTIM1_CC3 #18 LE-
TIM0_OUT0 #24 LE-
TIM0_OUT1 #23
PCNT0_S0IN #24
PCNT0_S1IN #23
FRC_DCLK #24
FRC_DOUT #23
PRS_CH0 #0
PRS_CH1 #7
PRS_CH2 #6
PRS_CH3 #5
ACMP0_O #24
ACMP1_O #24
DBG_SWCLKTCK
BOOT_TX
FRC_DFRAME #22
MODEM_DCLK #24
MODEM_DIN #23
MODEM_DOUT #22
MODEM_ANT0 #21
MODEM_ANT1 #20
PF0
BUSBY BUSAX
WTIM0_CC0 #24
WTIM0_CC1 #22
WTIM0_CC2 #20
WTIM0_CDTI0 #16
WTIM0_CDTI1 #14
WTIM0_CDTI2 #12
WTIM1_CC0 #8
WTIM1_CC1 #6
WTIM1_CC2 #4
WTIM1_CC3 #2
PCNT1_S0IN #17
PCNT1_S1IN #16
PCNT2_S0IN #17
PCNT2_S1IN #16
US3_TX #22
US3_RX #21
US3_CLK #20
US3_CS #19
US3_CTS #18
US3_RTS #17
I2C1_SDA #17
I2C1_SCL #16
PC4
BUSBY BUSAX
WTIM0_CC0 #21
WTIM0_CC1 #19
WTIM0_CC2 #17
WTIM0_CDTI0 #13
WTIM0_CDTI1 #11
WTIM0_CDTI2 #9
WTIM1_CC0 #5
WTIM1_CC1 #3
WTIM1_CC2 #1
PCNT1_S0IN #14
PCNT1_S1IN #13
PCNT2_S0IN #14
PCNT2_S1IN #13
US3_TX #19
US3_RX #18
US3_CLK #17
US3_CS #16
US3_CTS #15
US3_RTS #14
I2C1_SDA #14
I2C1_SCL #13
PC1
BUSAY BUSBX
US3_TX #16
US3_RX #15
US3_CLK #14
US3_CS #13
US3_CTS #12
US3_RTS #11
I2C1_SDA #11
I2C1_SCL #10
PCNT1_S0IN #11
PCNT1_S1IN #10
PCNT2_S0IN #11
PCNT2_S1IN #10
BUSACMP1Y BU-
SACMP1X
PJ14
LES_ALTEX2
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
Timers
Communication
Radio
Other
TIM0_CC0 #15
TIM0_CC1 #14
TIM0_CC2 #13
TIM0_CDTI0 #12
TIM0_CDTI1 #11
TIM0_CDTI2 #10
TIM1_CC0 #15
TIM1_CC1 #14
TIM1_CC2 #13
US0_TX #15
US0_RX #14
US0_CLK #13
US0_CS #12
US0_CTS #11
US0_RTS #10
US1_TX #15
US1_RX #14
US1_CLK #13
US1_CS #12
US1_CTS #11
US1_RTS #10
LEU0_TX #15
LEU0_RX #14
I2C0_SDA #15
I2C0_SCL #14
I2C1_SDA #19
I2C1_SCL #18
CMU_CLK1 #3
PRS_CH0 #12
PRS_CH9 #15
PRS_CH10 #4
PRS_CH11 #3
ACMP0_O #15
ACMP1_O #15
ETM_TD3 #3
TIM1_CC3 #12
FRC_DCLK #15
FRC_DOUT #14
WTIM0_CC0 #30
WTIM0_CC1 #28
WTIM0_CC2 #26
WTIM0_CDTI0 #22
WTIM0_CDTI1 #20
WTIM0_CDTI2 #18
WTIM1_CC0 #14
WTIM1_CC1 #12
WTIM1_CC2 #10
WTIM1_CC3 #8 LE-
TIM0_OUT0 #15 LE-
TIM0_OUT1 #14
PCNT0_S0IN #15
PCNT0_S1IN #14
PCNT2_S0IN #19
PCNT2_S1IN #18
FRC_DFRAME #13
MODEM_DCLK #15
MODEM_DIN #14
MODEM_DOUT #13
MODEM_ANT0 #12
MODEM_ANT1 #11
PC10
BUSBY BUSAX
GPIO_EM4WU12
TIM0_CC0 #13
TIM0_CC1 #12
TIM0_CC2 #11
TIM0_CDTI0 #10
TIM0_CDTI1 #9
TIM0_CDTI2 #8
TIM1_CC0 #13
TIM1_CC1 #12
TIM1_CC2 #11
US0_TX #13
US0_RX #12
US0_CLK #11
US0_CS #10
US0_CTS #9
US0_RTS #8
US1_TX #13
US1_RX #12
US1_CLK #11
US1_CS #10
US1_CTS #9
US1_RTS #8
LEU0_TX #13
LEU0_RX #12
I2C0_SDA #13
I2C0_SCL #12
FRC_DCLK #13
FRC_DOUT #12
PRS_CH0 #10
PRS_CH9 #13
PRS_CH10 #2
PRS_CH11 #1
ACMP0_O #13
ACMP1_O #13
ETM_TD1 #3
TIM1_CC3 #10
WTIM0_CC0 #28
WTIM0_CC1 #26
WTIM0_CC2 #24
WTIM0_CDTI0 #20
WTIM0_CDTI1 #18
WTIM0_CDTI2 #16
WTIM1_CC0 #12
WTIM1_CC1 #10
WTIM1_CC2 #8
WTIM1_CC3 #6 LE-
TIM0_OUT0 #13 LE-
TIM0_OUT1 #12
PCNT0_S0IN #13
PCNT0_S1IN #12
FRC_DFRAME #11
MODEM_DCLK #13
MODEM_DIN #12
MODEM_DOUT #11
MODEM_ANT0 #10
MODEM_ANT1 #9
PC8
BUSBY BUSAX
silabs.com | Building a more connected world.
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
Timers
Communication
Radio
Other
TIM0_CC0 #11
TIM0_CC1 #10
TIM0_CC2 #9
TIM0_CDTI0 #8
TIM0_CDTI1 #7
TIM0_CDTI2 #6
TIM1_CC0 #11
US0_TX #11
US0_RX #10
US0_CLK #9
US0_CS #8
TIM1_CC1 #10
CMU_CLK0 #2
CMU_CLKI0 #2
PRS_CH0 #8
PRS_CH9 #11
PRS_CH10 #0
PRS_CH11 #5
ACMP0_O #11
ACMP1_O #11
ETM_TCLK #3
TIM1_CC2 #9
TIM1_CC3 #8
US0_CTS #7
US0_RTS #6
US1_TX #11
US1_RX #10
US1_CLK #9
US1_CS #8
US1_CTS #7
US1_RTS #6
LEU0_TX #11
LEU0_RX #10
I2C0_SDA #11
I2C0_SCL #10
FRC_DCLK #11
FRC_DOUT #10
WTIM0_CC0 #26
WTIM0_CC1 #24
WTIM0_CC2 #22
WTIM0_CDTI0 #18
WTIM0_CDTI1 #16
WTIM0_CDTI2 #14
WTIM1_CC0 #10
WTIM1_CC1 #8
WTIM1_CC2 #6
WTIM1_CC3 #4 LE-
TIM0_OUT0 #11 LE-
TIM0_OUT1 #10
PCNT0_S0IN #11
PCNT0_S1IN #10
FRC_DFRAME #9
MODEM_DCLK #11
MODEM_DIN #10
MODEM_DOUT #9
MODEM_ANT0 #8
MODEM_ANT1 #7
PC6
BUSBY BUSAX
US2_TX #24
US2_RX #23
US2_CLK #22
US2_CS #21
US2_CTS #20
US2_RTS #19
US3_TX #24
US3_RX #23
US3_CLK #22
US3_CS #21
US3_CTS #20
US3_RTS #19
I2C1_SDA #24
I2C1_SCL #23
WTIM1_CC2 #31
WTIM1_CC3 #29
PCNT1_S0IN #24
PCNT1_S1IN #23
PCNT2_S0IN #24
PCNT2_S1IN #23
PF11
BUSAY BUSBX
ETM_TD2 #0
US2_TX #23
US2_RX #22
US2_CLK #21
US2_CS #20
US2_CTS #19
US2_RTS #18
I2C1_SDA #23
I2C1_SCL #22
WTIM1_CC2 #30
WTIM1_CC3 #28
PCNT1_S0IN #23
PCNT1_S1IN #22
PCNT2_S0IN #23
PCNT2_S1IN #22
PF10
BUSBY BUSAX
ETM_TD1 #0
US2_TX #22
US2_RX #21
US2_CLK #20
US2_CS #19
US2_CTS #18
US2_RTS #17
I2C1_SDA #22
I2C1_SCL #21
WTIM1_CC1 #31
WTIM1_CC2 #29
WTIM1_CC3 #27
PCNT1_S0IN #22
PCNT1_S1IN #21
PCNT2_S0IN #22
PCNT2_S1IN #21
PF9
BUSAY BUSBX
ETM_TD0 #0
silabs.com | Building a more connected world.
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
Timers
Communication
Radio
Other
WTIM0_CC0 #22
WTIM0_CC1 #20
WTIM0_CC2 #18
WTIM0_CDTI0 #14
WTIM0_CDTI1 #12
WTIM0_CDTI2 #10
WTIM1_CC0 #6
WTIM1_CC1 #4
WTIM1_CC2 #2
WTIM1_CC3 #0
PCNT1_S0IN #15
PCNT1_S1IN #14
PCNT2_S0IN #15
PCNT2_S1IN #14
US3_TX #20
US3_RX #19
US3_CLK #18
US3_CS #17
US3_CTS #16
US3_RTS #15
I2C1_SDA #15
I2C1_SCL #14
PC2
BUSBY BUSAX
US3_TX #17
US3_RX #16
US3_CLK #15
US3_CS #14
US3_CTS #13
US3_RTS #12
I2C1_SDA #12
I2C1_SCL #11
PCNT1_S0IN #12
PCNT1_S1IN #11
PCNT2_S0IN #12
PCNT2_S1IN #11
BUSACMP1Y BU-
SACMP1X
PJ15
LES_ALTEX3
TIM0_CC0 #10
TIM0_CC1 #9
TIM0_CC2 #8
TIM0_CDTI0 #7
TIM0_CDTI1 #6
TIM0_CDTI2 #5
TIM1_CC0 #10
TIM1_CC1 #9
US0_TX #10
US0_RX #9
US0_CLK #8
US0_CS #7
US0_CTS #6
US0_RTS #5
US1_TX #10
US1_RX #9
US1_CLK #8
US1_CS #7
US1_CTS #6
US1_RTS #5
LEU0_TX #10
LEU0_RX #9
I2C0_SDA #10
I2C0_SCL #9
FRC_DCLK #10
FRC_DOUT #9
CMU_CLK0 #1
PRS_CH6 #10
PRS_CH7 #9
PRS_CH8 #8
PRS_CH9 #7
ACMP0_O #10
ACMP1_O #10
TIM1_CC2 #8
TIM1_CC3 #7
FRC_DFRAME #8
MODEM_DCLK #10
MODEM_DIN #9
MODEM_DOUT #8
MODEM_ANT0 #7
MODEM_ANT1 #6
BUSCY BUSDX
LFXTAL_P
WTIM0_CC0 #19
WTIM0_CC1 #17
WTIM0_CC2 #15
WTIM0_CDTI0 #11
WTIM0_CDTI1 #9
WTIM0_CDTI2 #7
WTIM1_CC0 #3
WTIM1_CC1 #1 LE-
TIM0_OUT0 #10 LE-
TIM0_OUT1 #9
PCNT0_S0IN #10
PCNT0_S1IN #9
PB15
silabs.com | Building a more connected world.
Rev. 1.0 | 131
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
Timers
Communication
Radio
Other
TIM0_CC0 #9
TIM0_CC1 #8
TIM0_CC2 #7
TIM0_CDTI0 #6
TIM0_CDTI1 #5
TIM0_CDTI2 #4
TIM1_CC0 #9
US0_TX #9 US0_RX
#8 US0_CLK #7
US0_CS #6
TIM1_CC1 #8
TIM1_CC2 #7
TIM1_CC3 #6
US0_CTS #5
US0_RTS #4
US1_TX #9 US1_RX
#8 US1_CLK #7
US1_CS #6
FRC_DCLK #9
FRC_DOUT #8
CMU_CLK1 #1
PRS_CH6 #9
PRS_CH7 #8
PRS_CH8 #7
PRS_CH9 #6
ACMP0_O #9
ACMP1_O #9
FRC_DFRAME #7
MODEM_DCLK #9
MODEM_DIN #8
MODEM_DOUT #7
MODEM_ANT0 #6
MODEM_ANT1 #5
BUSDY BUSCX
LFXTAL_N
WTIM0_CC0 #18
WTIM0_CC1 #16
WTIM0_CC2 #14
WTIM0_CDTI0 #10
WTIM0_CDTI1 #8
WTIM0_CDTI2 #6
WTIM1_CC0 #2
WTIM1_CC1 #0 LE-
TIM0_OUT0 #9 LE-
TIM0_OUT1 #8
PCNT0_S0IN #9
PCNT0_S1IN #8
PB14
US1_CTS #5
US1_RTS #4
LEU0_TX #9
LEU0_RX #8
I2C0_SDA #9
I2C0_SCL #8
TIM0_CC0 #8
TIM0_CC1 #7
TIM0_CC2 #6
TIM0_CDTI0 #5
TIM0_CDTI1 #4
TIM0_CDTI2 #3
TIM1_CC0 #8
TIM1_CC1 #7
TIM1_CC2 #6
US0_TX #8 US0_RX
#7 US0_CLK #6
US0_CS #5
US0_CTS #4
US0_RTS #3
US1_TX #8 US1_RX
#7 US1_CLK #6
US1_CS #5
CMU_CLKI0 #0
PRS_CH6 #8
PRS_CH7 #7
PRS_CH8 #6
PRS_CH9 #5
ACMP0_O #8
ACMP1_O #8
DBG_SWO #1
GPIO_EM4WU9
FRC_DCLK #8
FRC_DOUT #7
FRC_DFRAME #6
MODEM_DCLK #8
MODEM_DIN #7
MODEM_DOUT #6
MODEM_ANT0 #5
MODEM_ANT1 #4
TIM1_CC3 #5
BUSCY BUSDX
OPA2_N
PB13
WTIM0_CC0 #17
WTIM0_CC1 #15
WTIM0_CC2 #13
WTIM0_CDTI0 #9
WTIM0_CDTI1 #7
WTIM0_CDTI2 #5
WTIM1_CC0 #1 LE-
TIM0_OUT0 #8 LE-
TIM0_OUT1 #7
PCNT0_S0IN #8
PCNT0_S1IN #7
US1_CTS #4
US1_RTS #3
LEU0_TX #8
LEU0_RX #7
I2C0_SDA #8
I2C0_SCL #7
silabs.com | Building a more connected world.
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
Timers
Communication
Radio
Other
TIM0_CC0 #7
TIM0_CC1 #6
TIM0_CC2 #5
TIM0_CDTI0 #4
TIM0_CDTI1 #3
TIM0_CDTI2 #2
TIM1_CC0 #7
TIM1_CC1 #6
TIM1_CC2 #5
US0_TX #7 US0_RX
#6 US0_CLK #5
US0_CS #4
US0_CTS #3
US0_RTS #2
US1_TX #7 US1_RX
#6 US1_CLK #5
US1_CS #4
FRC_DCLK #7
FRC_DOUT #6
PRS_CH6 #7
PRS_CH7 #6
PRS_CH8 #5
PRS_CH9 #4
ACMP0_O #7
ACMP1_O #7
FRC_DFRAME #5
MODEM_DCLK #7
MODEM_DIN #6
MODEM_DOUT #5
MODEM_ANT0 #4
MODEM_ANT1 #3
TIM1_CC3 #4
BUSDY BUSCX
OPA2_OUT
PB12
WTIM0_CC0 #16
WTIM0_CC1 #14
WTIM0_CC2 #12
WTIM0_CDTI0 #8
WTIM0_CDTI1 #6
WTIM0_CDTI2 #4
WTIM1_CC0 #0 LE-
TIM0_OUT0 #7 LE-
TIM0_OUT1 #6
PCNT0_S0IN #7
PCNT0_S1IN #6
US1_CTS #3
US1_RTS #2
LEU0_TX #7
LEU0_RX #6
I2C0_SDA #7
I2C0_SCL #6
US2_TX #27
US2_RX #26
US2_CLK #25
US2_CS #24
US2_CTS #23
US2_RTS #22
US3_TX #27
US3_RX #26
US3_CLK #25
US3_CS #24
US3_CTS #23
US3_RTS #22
I2C1_SDA #27
I2C1_SCL #26
PCNT1_S0IN #27
PCNT1_S1IN #26
PCNT2_S0IN #27
PCNT2_S1IN #26
PF14
BUSBY BUSAX
US2_TX #26
US2_RX #25
US2_CLK #24
US2_CS #23
US2_CTS #22
US2_RTS #21
US3_TX #26
US3_RX #25
US3_CLK #24
US3_CS #23
US3_CTS #22
US3_RTS #21
I2C1_SDA #26
I2C1_SCL #25
WTIM1_CC3 #31
PCNT1_S0IN #26
PCNT1_S1IN #25
PCNT2_S0IN #26
PCNT2_S1IN #25
PF13
BUSAY BUSBX
silabs.com | Building a more connected world.
Rev. 1.0 | 133
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
Timers
Communication
Radio
Other
US2_TX #25
US2_RX #24
US2_CLK #23
US2_CS #22
US2_CTS #21
US2_RTS #20
US3_TX #25
US3_RX #24
US3_CLK #23
US3_CS #22
US3_CTS #21
US3_RTS #20
I2C1_SDA #25
I2C1_SCL #24
WTIM1_CC3 #30
PCNT1_S0IN #25
PCNT1_S1IN #24
PCNT2_S0IN #25
PCNT2_S1IN #24
PF12
BUSBY BUSAX
ETM_TD3 #0
TIM0_CC0 #6
TIM0_CC1 #5
TIM0_CC2 #4
US0_TX #6 US0_RX
#5 US0_CLK #4
US0_CS #3
TIM0_CDTI0 #3
TIM0_CDTI1 #2
TIM0_CDTI2 #1
TIM1_CC0 #6
US0_CTS #2
US0_RTS #1
US1_TX #6 US1_RX
#5 US1_CLK #4
US1_CS #3
FRC_DCLK #6
FRC_DOUT #5
TIM1_CC1 #5
PRS_CH6 #6
PRS_CH7 #5
PRS_CH8 #4
PRS_CH9 #3
ACMP0_O #6
ACMP1_O #6
TIM1_CC2 #4
TIM1_CC3 #3
US1_CTS #2
US1_RTS #1
US3_TX #15
US3_RX #14
US3_CLK #13
US3_CS #12
US3_CTS #11
US3_RTS #10
LEU0_TX #6
FRC_DFRAME #4
MODEM_DCLK #6
MODEM_DIN #5
MODEM_DOUT #4
MODEM_ANT0 #3
MODEM_ANT1 #2
BUSCY BUSDX
OPA2_P
PB11
WTIM0_CC0 #15
WTIM0_CC1 #13
WTIM0_CC2 #11
WTIM0_CDTI0 #7
WTIM0_CDTI1 #5
WTIM0_CDTI2 #3
LETIM0_OUT0 #6
LETIM0_OUT1 #5
PCNT0_S0IN #6
PCNT0_S1IN #5
LEU0_RX #5
I2C0_SDA #6
I2C0_SCL #5
US2_TX #13
US2_RX #12
US2_CLK #11
US2_CS #10
US2_CTS #9
US2_RTS #8
US3_TX #14
US3_RX #13
US3_CLK #12
US3_CS #11
US3_CTS #10
US3_RTS #9
I2C1_SDA #10
I2C1_SCL #9
WTIM0_CC0 #14
WTIM0_CC1 #12
WTIM0_CC2 #10
WTIM0_CDTI0 #6
WTIM0_CDTI1 #4
WTIM0_CDTI2 #2
PCNT1_S0IN #10
PCNT1_S1IN #9
PCNT2_S0IN #10
PCNT2_S1IN #9
OPA2_OUTALT #1
BUSDY BUSCX
PB10
silabs.com | Building a more connected world.
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
Timers
Communication
Radio
Other
US2_TX #12
US2_RX #11
US2_CLK #10
US2_CS #9
WTIM0_CC0 #13
WTIM0_CC1 #11
WTIM0_CC2 #9
WTIM0_CDTI0 #5
WTIM0_CDTI1 #3
WTIM0_CDTI2 #1
PCNT1_S0IN #9
PCNT1_S1IN #8
PCNT2_S0IN #9
PCNT2_S1IN #8
US2_CTS #8
US2_RTS #7
US3_TX #13
US3_RX #12
US3_CLK #11
US3_CS #10
US3_CTS #9
US3_RTS #8
I2C1_SDA #9
I2C1_SCL #8
OPA2_OUTALT #0
BUSCY BUSDX
PB9
US2_TX #30
US2_RX #29
US2_CLK #28
US2_CS #27
US2_CTS #26
US2_RTS #25
US3_TX #30
US3_RX #29
US3_CLK #28
US3_CS #27
US3_CTS #26
US3_RTS #25
I2C1_SDA #30
I2C1_SCL #29
PCNT1_S0IN #30
PCNT1_S1IN #29
PCNT2_S0IN #30
PCNT2_S1IN #29
PK1
US2_TX #29
US2_RX #28
US2_CLK #27
US2_CS #26
US2_CTS #25
US2_RTS #24
US3_TX #29
US3_RX #28
US3_CLK #27
US3_CS #26
US3_CTS #25
US3_RTS #24
I2C1_SDA #29
I2C1_SCL #28
PCNT1_S0IN #29
PCNT1_S1IN #28
PCNT2_S0IN #29
PCNT2_S1IN #28
PK0
IDAC0_OUT
US2_TX #28
US2_RX #27
US2_CLK #26
US2_CS #25
US2_CTS #24
US2_RTS #23
US3_TX #28
US3_RX #27
US3_CLK #26
US3_CS #25
US3_CTS #24
US3_RTS #23
I2C1_SDA #28
I2C1_SCL #27
PCNT1_S0IN #28
PCNT1_S1IN #27
PCNT2_S0IN #28
PCNT2_S1IN #27
PF15
BUSAY BUSBX
silabs.com | Building a more connected world.
Rev. 1.0 | 135
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
Timers
Communication
Radio
Other
US2_TX #11
US2_RX #10
US2_CLK #9
US2_CS #8
US2_CTS #7
US2_RTS #6
US3_TX #12
US3_RX #11
US3_CLK #10
US3_CS #9
WTIM0_CC0 #12
WTIM0_CC1 #10
WTIM0_CC2 #8
WTIM0_CDTI0 #4
WTIM0_CDTI1 #2
WTIM0_CDTI2 #0
PCNT1_S0IN #8
PCNT1_S1IN #7
PCNT2_S0IN #8
PCNT2_S1IN #7
PB8
BUSDY BUSCX
ETM_TD3 #2
US3_CTS #8
US3_RTS #7
I2C1_SDA #8
I2C1_SCL #7
US2_TX #10
US2_RX #9
US2_CLK #8
US2_CS #7
US2_CTS #6
US2_RTS #5
US3_TX #11
US3_RX #10
US3_CLK #9
US3_CS #8
US3_CTS #7
US3_RTS #6
I2C1_SDA #7
I2C1_SCL #6
WTIM0_CC0 #11
WTIM0_CC1 #9
WTIM0_CC2 #7
WTIM0_CDTI0 #3
WTIM0_CDTI1 #1
PCNT1_S0IN #7
PCNT1_S1IN #6
PCNT2_S0IN #7
PCNT2_S1IN #6
PB7
BUSCY BUSDX
ETM_TD2 #2
US2_TX #31
US2_RX #30
US2_CLK #29
US2_CS #28
US2_CTS #27
US2_RTS #26
US3_TX #31
US3_RX #30
US3_CLK #29
US3_CS #28
US3_CTS #27
US3_RTS #26
I2C1_SDA #31
I2C1_SCL #30
PCNT1_S0IN #31
PCNT1_S1IN #30
PCNT2_S0IN #31
PCNT2_S1IN #30
PK2
US2_TX #9 US2_RX
#8 US2_CLK #7
US2_CS #6
WTIM0_CC0 #10
WTIM0_CC1 #8
WTIM0_CC2 #6
WTIM0_CDTI0 #2
WTIM0_CDTI1 #0
PCNT1_S0IN #6
PCNT1_S1IN #5
PCNT2_S0IN #6
PCNT2_S1IN #5
US2_CTS #5
US2_RTS #4
US3_TX #10
US3_RX #9
US3_CLK #8
US3_CS #7
US3_CTS #6
US3_RTS #5
I2C1_SDA #6
I2C1_SCL #5
CMU_CLKI0 #3
ETM_TD1 #2
PB6
BUSDY BUSCX
silabs.com | Building a more connected world.
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
Timers
Communication
Radio
Other
US2_TX #8 US2_RX
#7 US2_CLK #6
US2_CS #5
US2_CTS #4
PCNT1_S0IN #5
PCNT1_S1IN #4
PCNT2_S0IN #5
PCNT2_S1IN #4
US2_RTS #3
BUSADC0Y BU-
SADC0X
US3_TX #9 US3_RX
#8 US3_CLK #7
US3_CS #6
LES_ALTEX7
ETM_TD0 #2
PI3
US3_CTS #5
US3_RTS #4
I2C1_SDA #5
I2C1_SCL #4
US0_TX #29
US0_RX #28
US0_CLK #27
US0_CS #26
US0_CTS #25
US0_RTS #24
US1_TX #29
US1_RX #28
US1_CLK #27
US1_CS #26
US1_CTS #25
US1_RTS #24
US2_TX #18
US2_RX #17
US2_CLK #16
US2_CS #15
US2_CTS #14
US2_RTS #13
LEU0_TX #29
LEU0_RX #28
I2C0_SDA #29
I2C0_SCL #28
TIM0_CC0 #29
TIM0_CC1 #28
TIM0_CC2 #27
TIM0_CDTI0 #26
TIM0_CDTI1 #25
TIM0_CDTI2 #24
TIM1_CC0 #29
TIM1_CC1 #28
TIM1_CC2 #27
TIM1_CC3 #26
WTIM1_CC0 #29
WTIM1_CC1 #27
WTIM1_CC2 #25
WTIM1_CC3 #23 LE-
TIM0_OUT0 #29 LE-
TIM0_OUT1 #28
PCNT0_S0IN #29
PCNT0_S1IN #28
FRC_DCLK #29
FRC_DOUT #28
PRS_CH0 #5
PRS_CH1 #4
PRS_CH2 #3
PRS_CH3 #2
ACMP0_O #29
ACMP1_O #29
FRC_DFRAME #27
MODEM_DCLK #29
MODEM_DIN #28
MODEM_DOUT #27
MODEM_ANT0 #26
MODEM_ANT1 #25
PF5
BUSAY BUSBX
US0_TX #28
US0_RX #27
US0_CLK #26
US0_CS #25
US0_CTS #24
US0_RTS #23
US1_TX #28
US1_RX #27
US1_CLK #26
US1_CS #25
US1_CTS #24
US1_RTS #23
US2_TX #17
US2_RX #16
US2_CLK #15
US2_CS #14
US2_CTS #13
US2_RTS #12
LEU0_TX #28
LEU0_RX #27
I2C0_SDA #28
I2C0_SCL #27
TIM0_CC0 #28
TIM0_CC1 #27
TIM0_CC2 #26
TIM0_CDTI0 #25
TIM0_CDTI1 #24
TIM0_CDTI2 #23
TIM1_CC0 #28
TIM1_CC1 #27
TIM1_CC2 #26
TIM1_CC3 #25
WTIM1_CC0 #28
WTIM1_CC1 #26
WTIM1_CC2 #24
WTIM1_CC3 #22 LE-
TIM0_OUT0 #28 LE-
TIM0_OUT1 #27
PCNT0_S0IN #28
PCNT0_S1IN #27
FRC_DCLK #28
FRC_DOUT #27
PRS_CH0 #4
PRS_CH1 #3
PRS_CH2 #2
PRS_CH3 #1
ACMP0_O #28
ACMP1_O #28
FRC_DFRAME #26
MODEM_DCLK #28
MODEM_DIN #27
MODEM_DOUT #26
MODEM_ANT0 #25
MODEM_ANT1 #24
PF4
BUSBY BUSAX
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
Timers
Communication
Radio
Other
US2_TX #7 US2_RX
#6 US2_CLK #5
US2_CS #4
US2_CTS #3
PCNT1_S0IN #4
PCNT1_S1IN #3
PCNT2_S0IN #4
PCNT2_S1IN #3
US2_RTS #2
BUSADC0Y BU-
SADC0X
US3_TX #8 US3_RX
#7 US3_CLK #6
US3_CS #5
LES_ALTEX6
ETM_TCLK #2
PI2
US3_CTS #4
US3_RTS #3
I2C1_SDA #4
I2C1_SCL #3
US2_TX #6 US2_RX
#5 US2_CLK #4
US2_CS #3
BUSADC0Y BU-
SADC0X
PI1
PI0
LES_ALTEX5
LES_ALTEX4
US2_CTS #2
US2_RTS #1
US2_TX #5 US2_RX
#4 US2_CLK #3
US2_CS #2
BUSADC0Y BU-
SADC0X
US2_CTS #1
US2_RTS #0
US0_TX #31
US0_RX #30
US0_CLK #29
US0_CS #28
US0_CTS #27
US0_RTS #26
US1_TX #31
US1_RX #30
US1_CLK #29
US1_CS #28
US1_CTS #27
US1_RTS #26
US2_TX #20
US2_RX #19
US2_CLK #18
US2_CS #17
US2_CTS #16
US2_RTS #15
LEU0_TX #31
LEU0_RX #30
I2C0_SDA #31
I2C0_SCL #30
TIM0_CC0 #31
TIM0_CC1 #30
TIM0_CC2 #29
TIM0_CDTI0 #28
TIM0_CDTI1 #27
TIM0_CDTI2 #26
TIM1_CC0 #31
TIM1_CC1 #30
TIM1_CC2 #29
TIM1_CC3 #28
WTIM1_CC0 #31
WTIM1_CC1 #29
WTIM1_CC2 #27
WTIM1_CC3 #25 LE-
TIM0_OUT0 #31 LE-
TIM0_OUT1 #30
PCNT0_S0IN #31
PCNT0_S1IN #30
PCNT1_S0IN #20
PCNT1_S1IN #19
CMU_CLKI0 #1
CMU_CLK0 #7
PRS_CH0 #7
PRS_CH1 #6
PRS_CH2 #5
PRS_CH3 #4
ACMP0_O #31
ACMP1_O #31
GPIO_EM4WU1
FRC_DCLK #31
FRC_DOUT #30
FRC_DFRAME #29
MODEM_DCLK #31
MODEM_DIN #30
MODEM_DOUT #29
MODEM_ANT0 #28
MODEM_ANT1 #27
PF7
BUSAY BUSBX
silabs.com | Building a more connected world.
Rev. 1.0 | 138
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
Timers
Communication
Radio
Other
US0_TX #30
US0_RX #29
US0_CLK #28
US0_CS #27
US0_CTS #26
US0_RTS #25
US1_TX #30
US1_RX #29
US1_CLK #28
US1_CS #27
US1_CTS #26
US1_RTS #25
US2_TX #19
US2_RX #18
US2_CLK #17
US2_CS #16
US2_CTS #15
US2_RTS #14
LEU0_TX #30
LEU0_RX #29
I2C0_SDA #30
I2C0_SCL #29
TIM0_CC0 #30
TIM0_CC1 #29
TIM0_CC2 #28
TIM0_CDTI0 #27
TIM0_CDTI1 #26
TIM0_CDTI2 #25
TIM1_CC0 #30
TIM1_CC1 #29
TIM1_CC2 #28
TIM1_CC3 #27
WTIM1_CC0 #30
WTIM1_CC1 #28
WTIM1_CC2 #26
WTIM1_CC3 #24 LE-
TIM0_OUT0 #30 LE-
TIM0_OUT1 #29
PCNT0_S0IN #30
PCNT0_S1IN #29
PCNT1_S0IN #19
PCNT1_S1IN #18
FRC_DCLK #30
FRC_DOUT #29
CMU_CLK1 #7
PRS_CH0 #6
PRS_CH1 #5
PRS_CH2 #4
PRS_CH3 #3
ACMP0_O #30
ACMP1_O #30
FRC_DFRAME #28
MODEM_DCLK #30
MODEM_DIN #29
MODEM_DOUT #28
MODEM_ANT0 #27
MODEM_ANT1 #26
PF6
BUSBY BUSAX
WTIM0_CC0 #9
WTIM0_CC1 #7
WTIM0_CC2 #5
WTIM0_CDTI0 #1
PCNT1_S0IN #3
PCNT1_S1IN #2
PCNT2_S0IN #3
PCNT2_S1IN #2
US2_TX #4 US2_RX
#3 US2_CLK #2
US2_CS #1
BUSACMP0Y BU-
SACMP0X
LES_ALTEX1
ETM_TD3 #1
PA9
US2_CTS #0
US2_RTS #31
I2C1_SDA #3
I2C1_SCL #2
WTIM0_CC0 #8
WTIM0_CC1 #6
WTIM0_CC2 #4
WTIM0_CDTI0 #0
PCNT1_S0IN #2
PCNT1_S1IN #1
PCNT2_S0IN #2
PCNT2_S1IN #1
US2_TX #3 US2_RX
#2 US2_CLK #1
US2_CS #0
BUSACMP0Y BU-
SACMP0X
LES_ALTEX0
ETM_TD2 #1
PA8
US2_CTS #31
US2_RTS #30
I2C1_SDA #2
I2C1_SCL #1
WTIM0_CC0 #7
WTIM0_CC1 #5
WTIM0_CC2 #3
PCNT1_S0IN #1
PCNT1_S1IN #0
PCNT2_S0IN #1
PCNT2_S1IN #0
US2_TX #2 US2_RX
#1 US2_CLK #0
US2_CS #31
LES_CH15
ETM_TD1 #1
PA7
PA6
BUSCY BUSDX
BUSDY BUSCX
US2_CTS #30
US2_RTS #29
I2C1_SDA #1
I2C1_SCL #0
WTIM0_CC0 #6
WTIM0_CC1 #4
WTIM0_CC2 #2
PCNT1_S0IN #0
PCNT1_S1IN #31
PCNT2_S0IN #0
PCNT2_S1IN #31
US2_TX #1 US2_RX
#0 US2_CLK #31
US2_CS #30
LES_CH14
ETM_TD0 #1
US2_CTS #29
US2_RTS #28
I2C1_SDA #0
I2C1_SCL #31
silabs.com | Building a more connected world.
Rev. 1.0 | 139
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
Timers
Communication
Radio
Other
US0_TX #5 US0_RX
#4 US0_CLK #3
US0_CS #2
TIM0_CC0 #5
TIM0_CC1 #4
TIM0_CC2 #3
US0_CTS #1
TIM0_CDTI0 #2
TIM0_CDTI1 #1
TIM0_CDTI2 #0
TIM1_CC0 #5
TIM1_CC1 #4
TIM1_CC2 #3
US0_RTS #0
US1_TX #5 US1_RX
#4 US1_CLK #3
US1_CS #2
US1_CTS #1
US1_RTS #0
US2_TX #0 US2_RX
#31 US2_CLK #30
US2_CS #29
CMU_CLKI0 #4
PRS_CH6 #5
PRS_CH7 #4
PRS_CH8 #3
PRS_CH9 #2
ACMP0_O #5
ACMP1_O #5
LES_CH13
FRC_DCLK #5
FRC_DOUT #4
FRC_DFRAME #3
MODEM_DCLK #5
MODEM_DIN #4
MODEM_DOUT #3
MODEM_ANT0 #2
MODEM_ANT1 #1
VDAC0_OUT0ALT /
OPA0_OUTALT #0
BUSCY BUSDX
PA5
TIM1_CC3 #2
WTIM0_CC0 #5
WTIM0_CC1 #3
WTIM0_CC2 #1 LE-
TIM0_OUT0 #5 LE-
TIM0_OUT1 #4
PCNT0_S0IN #5
PCNT0_S1IN #4
US2_CTS #28
US2_RTS #27
LEU0_TX #5
LEU0_RX #4
I2C0_SDA #5
I2C0_SCL #4
ETM_TCLK #1
TIM0_CC0 #4
TIM0_CC1 #3
TIM0_CC2 #2
TIM0_CDTI0 #1
TIM0_CDTI1 #0
TIM0_CDTI2 #31
TIM1_CC0 #4
TIM1_CC1 #3
TIM1_CC2 #2
TIM1_CC3 #1
WTIM0_CC0 #4
WTIM0_CC1 #2
WTIM0_CC2 #0 LE-
TIM0_OUT0 #4 LE-
TIM0_OUT1 #3
PCNT0_S0IN #4
PCNT0_S1IN #3
US0_TX #4 US0_RX
#3 US0_CLK #2
US0_CS #1
US0_CTS #0
FRC_DCLK #4
FRC_DOUT #3
PRS_CH6 #4
PRS_CH7 #3
PRS_CH8 #2
PRS_CH9 #1
ACMP0_O #4
ACMP1_O #4
LES_CH12
US0_RTS #31
US1_TX #4 US1_RX
#3 US1_CLK #2
US1_CS #1
VDAC0_OUT1ALT /
OPA1_OUTALT #2
BUSDY BUSCX
OPA0_N
FRC_DFRAME #2
MODEM_DCLK #4
MODEM_DIN #3
MODEM_DOUT #2
MODEM_ANT0 #1
MODEM_ANT1 #0
PA4
US1_CTS #0
US1_RTS #31
LEU0_TX #4
LEU0_RX #3
I2C0_SDA #4
I2C0_SCL #3
TIM0_CC0 #3
TIM0_CC1 #2
TIM0_CC2 #1
TIM0_CDTI0 #0
TIM0_CDTI1 #31
TIM0_CDTI2 #30
TIM1_CC0 #3
US0_TX #3 US0_RX
#2 US0_CLK #1
US0_CS #0
US0_CTS #31
US0_RTS #30
US1_TX #3 US1_RX
#2 US1_CLK #1
US1_CS #0
FRC_DCLK #3
FRC_DOUT #2
PRS_CH6 #3
PRS_CH7 #2
PRS_CH8 #1
PRS_CH9 #0
ACMP0_O #3
ACMP1_O #3
LES_CH11
FRC_DFRAME #1
MODEM_DCLK #3
MODEM_DIN #2
MODEM_DOUT #1
MODEM_ANT0 #0
MODEM_ANT1 #31
BUSCY BUSDX
VDAC0_OUT0 /
OPA0_OUT
TIM1_CC1 #2
TIM1_CC2 #1
PA3
TIM1_CC3 #0
US1_CTS #31
US1_RTS #30
LEU0_TX #3
LEU0_RX #2
I2C0_SDA #3
I2C0_SCL #2
WTIM0_CC0 #3
WTIM0_CC1 #1 LE-
TIM0_OUT0 #3 LE-
TIM0_OUT1 #2
PCNT0_S0IN #3
PCNT0_S1IN #2
GPIO_EM4WU8
silabs.com | Building a more connected world.
Rev. 1.0 | 140
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
Timers
Communication
Radio
Other
TIM0_CC0 #2
TIM0_CC1 #1
TIM0_CC2 #0
TIM0_CDTI0 #31
TIM0_CDTI1 #30
TIM0_CDTI2 #29
TIM1_CC0 #2
US0_TX #2 US0_RX
#1 US0_CLK #0
US0_CS #31
US0_CTS #30
US0_RTS #29
US1_TX #2 US1_RX
#1 US1_CLK #0
US1_CS #31
FRC_DCLK #2
FRC_DOUT #1
PRS_CH6 #2
PRS_CH7 #1
PRS_CH8 #0
PRS_CH9 #10
ACMP0_O #2
ACMP1_O #2
LES_CH10
VDAC0_OUT1ALT /
OPA1_OUTALT #1
BUSDY BUSCX
OPA0_P
FRC_DFRAME #0
MODEM_DCLK #2
MODEM_DIN #1
MODEM_DOUT #0
MODEM_ANT0 #31
MODEM_ANT1 #30
TIM1_CC1 #1
TIM1_CC2 #0
PA2
TIM1_CC3 #31
WTIM0_CC0 #2
WTIM0_CC1 #0 LE-
TIM0_OUT0 #2 LE-
TIM0_OUT1 #1
PCNT0_S0IN #2
PCNT0_S1IN #1
US1_CTS #30
US1_RTS #29
LEU0_TX #2
LEU0_RX #1
I2C0_SDA #2
I2C0_SCL #1
TIM0_CC0 #1
TIM0_CC1 #0
US0_TX #1 US0_RX
#0 US0_CLK #31
US0_CS #30
US0_CTS #29
US0_RTS #28
US1_TX #1 US1_RX FRC_DFRAME #31
#0 US1_CLK #31
US1_CS #30
US1_CTS #29
US1_RTS #28
LEU0_TX #1
LEU0_RX #0
I2C0_SDA #1
I2C0_SCL #0
TIM0_CC2 #31
TIM0_CDTI0 #30
TIM0_CDTI1 #29
TIM0_CDTI2 #28
TIM1_CC0 #1
FRC_DCLK #1
FRC_DOUT #0
CMU_CLK0 #0
PRS_CH6 #1
PRS_CH7 #0
PRS_CH8 #10
PRS_CH9 #9
ACMP0_O #1
ACMP1_O #1
LES_CH9
BUSCY BUSDX
ADC0_EXTP
VDAC0_EXT
MODEM_DCLK #1
MODEM_DIN #0
MODEM_DOUT #31
MODEM_ANT0 #30
MODEM_ANT1 #29
PA1
TIM1_CC1 #0
TIM1_CC2 #31
TIM1_CC3 #30
WTIM0_CC0 #1 LE-
TIM0_OUT0 #1 LE-
TIM0_OUT1 #0
PCNT0_S0IN #1
PCNT0_S1IN #0
TIM0_CC0 #17
TIM0_CC1 #16
TIM0_CC2 #15
TIM0_CDTI0 #14
TIM0_CDTI1 #13
TIM0_CDTI2 #12
TIM1_CC0 #17
TIM1_CC1 #16
TIM1_CC2 #15
TIM1_CC3 #14
WTIM0_CC1 #31
WTIM0_CC2 #29
WTIM0_CDTI0 #25
US0_TX #17
US0_RX #16
US0_CLK #15
US0_CS #14
US0_CTS #13
US0_RTS #12
US1_TX #17
US1_RX #16
US1_CLK #15
US1_CS #14
US1_CTS #13
US1_RTS #12
FRC_DCLK #17
FRC_DOUT #16
CMU_CLK0 #4
PRS_CH3 #8
PRS_CH4 #0
PRS_CH5 #6
PRS_CH6 #11
ACMP0_O #17
ACMP1_O #17
LES_CH1
FRC_DFRAME #15
MODEM_DCLK #17
MODEM_DIN #16
MODEM_DOUT #15
MODEM_ANT0 #14
MODEM_ANT1 #13
PD9
BUSCY BUSDX
WTIM0_CDTI1 #23 US3_TX #1 US3_RX
WTIM0_CDTI2 #21
WTIM1_CC0 #17
WTIM1_CC1 #15
WTIM1_CC2 #13
WTIM1_CC3 #11 LE-
TIM0_OUT0 #17 LE-
TIM0_OUT1 #16
#0 US3_CLK #31
US3_CS #30
US3_CTS #29
US3_RTS #28
LEU0_TX #17
LEU0_RX #16
I2C0_SDA #17
I2C0_SCL #16
PCNT0_S0IN #17
PCNT0_S1IN #16
silabs.com | Building a more connected world.
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
Timers
Communication
Radio
Other
TIM0_CC0 #19
TIM0_CC1 #18
TIM0_CC2 #17
TIM0_CDTI0 #16
TIM0_CDTI1 #15
TIM0_CDTI2 #14
TIM1_CC0 #19
TIM1_CC1 #18
TIM1_CC2 #17
TIM1_CC3 #16
US0_TX #19
US0_RX #18
US0_CLK #17
US0_CS #16
US0_CTS #15
US0_RTS #14
US1_TX #19
US1_RX #18
US1_CLK #17
US1_CS #16
FRC_DCLK #19
FRC_DOUT #18
PRS_CH3 #10
PRS_CH4 #2
PRS_CH5 #1
PRS_CH6 #13
ACMP0_O #19
ACMP1_O #19
LES_CH3
FRC_DFRAME #17
MODEM_DCLK #19
MODEM_DIN #18
MODEM_DOUT #17
MODEM_ANT0 #16
MODEM_ANT1 #15
WTIM0_CC2 #31
WTIM0_CDTI0 #27
WTIM0_CDTI1 #25
WTIM0_CDTI2 #23
WTIM1_CC0 #19
WTIM1_CC1 #17
WTIM1_CC2 #15
WTIM1_CC3 #13 LE-
TIM0_OUT0 #19 LE-
TIM0_OUT1 #18
PCNT0_S0IN #19
PCNT0_S1IN #18
PD11
BUSCY BUSDX
US1_CTS #15
US1_RTS #14
US3_TX #3 US3_RX
#2 US3_CLK #1
US3_CS #0
US3_CTS #31
US3_RTS #30
LEU0_TX #19
LEU0_RX #18
I2C0_SDA #19
I2C0_SCL #18
TIM0_CC0 #21
TIM0_CC1 #20
TIM0_CC2 #19
TIM0_CDTI0 #18
TIM0_CDTI1 #17
TIM0_CDTI2 #16
TIM1_CC0 #21
TIM1_CC1 #20
TIM1_CC2 #19
TIM1_CC3 #18
WTIM0_CDTI0 #29
WTIM0_CDTI1 #27
US0_TX #21
US0_RX #20
US0_CLK #19
US0_CS #18
US0_CTS #17
US0_RTS #16
US1_TX #21
US1_RX #20
US1_CLK #19
US1_CS #18
US1_CTS #17
US1_RTS #16
FRC_DCLK #21
FRC_DOUT #20
PRS_CH3 #12
PRS_CH4 #4
PRS_CH5 #3
PRS_CH6 #15
ACMP0_O #21
ACMP1_O #21
LES_CH5
VDAC0_OUT0ALT /
OPA0_OUTALT #1
BUSCY BUSDX
OPA1_P
FRC_DFRAME #19
MODEM_DCLK #21
MODEM_DIN #20
MODEM_DOUT #19
MODEM_ANT0 #18
MODEM_ANT1 #17
PD13
WTIM0_CDTI2 #25 US3_TX #5 US3_RX
WTIM1_CC0 #21
WTIM1_CC1 #19
WTIM1_CC2 #17
WTIM1_CC3 #15 LE-
TIM0_OUT0 #21 LE-
TIM0_OUT1 #20
#4 US3_CLK #3
US3_CS #2
US3_CTS #1
US3_RTS #0
LEU0_TX #21
LEU0_RX #20
I2C0_SDA #21
I2C0_SCL #20
PCNT0_S0IN #21
PCNT0_S1IN #20
TIM0_CC0 #0
TIM0_CC1 #31
TIM0_CC2 #30
TIM0_CDTI0 #29
TIM0_CDTI1 #28
TIM0_CDTI2 #27
TIM1_CC0 #0
TIM1_CC1 #31
TIM1_CC2 #30
TIM1_CC3 #29
WTIM0_CC0 #0 LE-
TIM0_OUT0 #0 LE-
TIM0_OUT1 #31
PCNT0_S0IN #0
PCNT0_S1IN #31
US0_TX #0 US0_RX
#31 US0_CLK #30
US0_CS #29
US0_CTS #28
US0_RTS #27
US1_TX #0 US1_RX FRC_DFRAME #30
#31 US1_CLK #30
US1_CS #29
FRC_DCLK #0
FRC_DOUT #31
CMU_CLK1 #0
PRS_CH6 #0
PRS_CH7 #10
PRS_CH8 #9
PRS_CH9 #8
ACMP0_O #0
ACMP1_O #0
LES_CH8
BUSDY BUSCX
ADC0_EXTN
MODEM_DCLK #0
MODEM_DIN #31
MODEM_DOUT #30
MODEM_ANT0 #29
MODEM_ANT1 #28
PA0
US1_CTS #28
US1_RTS #27
LEU0_TX #0
LEU0_RX #31
I2C0_SDA #0
I2C0_SCL #31
silabs.com | Building a more connected world.
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
Timers
Communication
Radio
Other
WTIM0_CC1 #30
WTIM0_CC2 #28
WTIM0_CDTI0 #24 US3_TX #0 US3_RX
WTIM0_CDTI1 #22
WTIM0_CDTI2 #20
WTIM1_CC0 #16
WTIM1_CC1 #14
WTIM1_CC2 #12
WTIM1_CC3 #10
#31 US3_CLK #30
US3_CS #29
US3_CTS #28
US3_RTS #27
PD8
BUSDY BUSCX
LES_CH0
TIM0_CC0 #18
TIM0_CC1 #17
TIM0_CC2 #16
TIM0_CDTI0 #15
TIM0_CDTI1 #14
TIM0_CDTI2 #13
TIM1_CC0 #18
TIM1_CC1 #17
TIM1_CC2 #16
TIM1_CC3 #15
US0_TX #18
US0_RX #17
US0_CLK #16
US0_CS #15
US0_CTS #14
US0_RTS #13
US1_TX #18
US1_RX #17
US1_CLK #16
US1_CS #15
FRC_DCLK #18
FRC_DOUT #17
CMU_CLK1 #4
PRS_CH3 #9
PRS_CH4 #1
PRS_CH5 #0
PRS_CH6 #12
ACMP0_O #18
ACMP1_O #18
LES_CH2
FRC_DFRAME #16
MODEM_DCLK #18
MODEM_DIN #17
MODEM_DOUT #16
MODEM_ANT0 #15
MODEM_ANT1 #14
WTIM0_CC2 #30
WTIM0_CDTI0 #26
WTIM0_CDTI1 #24
WTIM0_CDTI2 #22
WTIM1_CC0 #18
WTIM1_CC1 #16
WTIM1_CC2 #14
WTIM1_CC3 #12 LE-
TIM0_OUT0 #18 LE-
TIM0_OUT1 #17
PCNT0_S0IN #18
PCNT0_S1IN #17
PD10
BUSDY BUSCX
US1_CTS #14
US1_RTS #13
US3_TX #2 US3_RX
#1 US3_CLK #0
US3_CS #31
US3_CTS #30
US3_RTS #29
LEU0_TX #18
LEU0_RX #17
I2C0_SDA #18
I2C0_SCL #17
TIM0_CC0 #20
TIM0_CC1 #19
TIM0_CC2 #18
TIM0_CDTI0 #17
TIM0_CDTI1 #16
TIM0_CDTI2 #15
TIM1_CC0 #20
TIM1_CC1 #19
TIM1_CC2 #18
TIM1_CC3 #17
WTIM0_CDTI0 #28
WTIM0_CDTI1 #26
US0_TX #20
US0_RX #19
US0_CLK #18
US0_CS #17
US0_CTS #16
US0_RTS #15
US1_TX #20
US1_RX #19
US1_CLK #18
US1_CS #17
US1_CTS #16
US1_RTS #15
FRC_DCLK #20
FRC_DOUT #19
PRS_CH3 #11
PRS_CH4 #3
PRS_CH5 #2
PRS_CH6 #14
ACMP0_O #20
ACMP1_O #20
LES_CH4
FRC_DFRAME #18
MODEM_DCLK #20
MODEM_DIN #19
MODEM_DOUT #18
MODEM_ANT0 #17
MODEM_ANT1 #16
VDAC0_OUT1ALT /
OPA1_OUTALT #0
BUSDY BUSCX
PD12
WTIM0_CDTI2 #24 US3_TX #4 US3_RX
WTIM1_CC0 #20
WTIM1_CC1 #18
WTIM1_CC2 #16
WTIM1_CC3 #14 LE-
TIM0_OUT0 #20 LE-
TIM0_OUT1 #19
#3 US3_CLK #2
US3_CS #1
US3_CTS #0
US3_RTS #31
LEU0_TX #20
LEU0_RX #19
I2C0_SDA #20
I2C0_SCL #19
PCNT0_S0IN #20
PCNT0_S1IN #19
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
Timers
Communication
Radio
Other
TIM0_CC0 #22
TIM0_CC1 #21
TIM0_CC2 #20
TIM0_CDTI0 #19
TIM0_CDTI1 #18
TIM0_CDTI2 #17
TIM1_CC0 #22
TIM1_CC1 #21
TIM1_CC2 #20
TIM1_CC3 #19
WTIM0_CDTI0 #30
WTIM0_CDTI1 #28
US0_TX #22
US0_RX #21
US0_CLK #20
US0_CS #19
US0_CTS #18
US0_RTS #17
US1_TX #22
US1_RX #21
US1_CLK #20
US1_CS #19
US1_CTS #18
US1_RTS #17
CMU_CLK0 #5
PRS_CH3 #13
PRS_CH4 #5
PRS_CH5 #4
PRS_CH6 #16
ACMP0_O #22
ACMP1_O #22
LES_CH6
FRC_DCLK #22
FRC_DOUT #21
FRC_DFRAME #20
MODEM_DCLK #22
MODEM_DIN #21
MODEM_DOUT #20
MODEM_ANT0 #19
MODEM_ANT1 #18
BUSDY BUSCX
VDAC0_OUT1 /
OPA1_OUT
PD14
WTIM0_CDTI2 #26 US3_TX #6 US3_RX
WTIM1_CC0 #22
WTIM1_CC1 #20
WTIM1_CC2 #18
WTIM1_CC3 #16 LE-
TIM0_OUT0 #22 LE-
TIM0_OUT1 #21
#5 US3_CLK #4
US3_CS #3
GPIO_EM4WU4
US3_CTS #2
US3_RTS #1
LEU0_TX #22
LEU0_RX #21
I2C0_SDA #22
I2C0_SCL #21
PCNT0_S0IN #22
PCNT0_S1IN #21
TIM0_CC0 #23
TIM0_CC1 #22
TIM0_CC2 #21
TIM0_CDTI0 #20
TIM0_CDTI1 #19
TIM0_CDTI2 #18
TIM1_CC0 #23
TIM1_CC1 #22
TIM1_CC2 #21
TIM1_CC3 #20
WTIM0_CDTI0 #31
WTIM0_CDTI1 #29
US0_TX #23
US0_RX #22
US0_CLK #21
US0_CS #20
US0_CTS #19
US0_RTS #18
US1_TX #23
US1_RX #22
US1_CLK #21
US1_CS #20
US1_CTS #19
US1_RTS #18
CMU_CLK1 #5
PRS_CH3 #14
PRS_CH4 #6
PRS_CH5 #5
PRS_CH6 #17
ACMP0_O #23
ACMP1_O #23
LES_CH7
FRC_DCLK #23
FRC_DOUT #22
VDAC0_OUT0ALT /
OPA0_OUTALT #2
BUSCY BUSDX
OPA1_N
FRC_DFRAME #21
MODEM_DCLK #23
MODEM_DIN #22
MODEM_DOUT #21
MODEM_ANT0 #20
MODEM_ANT1 #19
PD15
WTIM0_CDTI2 #27 US3_TX #7 US3_RX
WTIM1_CC0 #23
WTIM1_CC1 #21
WTIM1_CC2 #19
WTIM1_CC3 #17 LE-
TIM0_OUT0 #23 LE-
TIM0_OUT1 #22
#6 US3_CLK #5
US3_CS #4
DBG_SWO #2
US3_CTS #3
US3_RTS #2
LEU0_TX #23
LEU0_RX #22
I2C0_SDA #23
I2C0_SCL #22
PCNT0_S0IN #23
PCNT0_S1IN #22
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
6.8 Alternate Functionality Overview
A wide selection of alternate functionality is available for multiplexing to various pins. The following table shows the name of the alter-
nate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings and the associated GPIO
pin. Refer to 6.7 GPIO Functionality Table for a list of functions available on each GPIO pin.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.
Table 6.8. Alternate Functionality Overview
Alternate
LOCATION
12 - 15 16 - 19
16: PC11 20: PD12 24: PF0
Functionality
0 - 3
4 - 7
8 - 11
20 - 23
24 - 27
28 - 31
Description
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
12: PC7
13: PC8
28: PF4
29: PF5
30: PF6
31: PF7
Analog comparator
ACMP0, digital out-
put.
17: PD9 21: PD13 25: PF1
18: PD10 22: PD14 26: PF2
15: PC10 19: PD11 23: PD15 27: PF3
ACMP0_O
ACMP1_O
ADC0_EXTN
ADC0_EXTP
BOOT_RX
BOOT_TX
10: PB15 14: PC9
11: PC6
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
12: PC7
16: PC11 20: PD12 24: PF0
17: PD9 21: PD13 25: PF1
18: PD10 22: PD14 26: PF2
15: PC10 19: PD11 23: PD15 27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
Analog comparator
ACMP1, digital out-
put.
13: PC8
10: PB15 14: PC9
11: PC6
0: PA0
0: PA1
0: PF1
0: PF0
Analog to digital
converter ADC0 ex-
ternal reference in-
put negative pin.
Analog to digital
converter ADC0 ex-
ternal reference in-
put positive pin.
Bootloader RX.
Bootloader TX.
0: PA1
4: PD9
5: PD14
6: PF2
7: PF7
Clock Management
Unit, clock output
number 0.
1: PB15
2: PC6
3: PC11
CMU_CLK0
CMU_CLK1
CMU_CLKI0
0: PA0
4: PD10
5: PD15
6: PF3
Clock Management
Unit, clock output
number 1.
1: PB14
2: PC7
3: PC10
7: PF6
0: PB13
1: PF7
2: PC6
3: PB6
4: PA5
Clock Management
Unit, clock output
number I0.
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
Alternate
LOCATION
12 - 15 16 - 19
Functionality
0 - 3
4 - 7
8 - 11
20 - 23
24 - 27
28 - 31
Description
0: PF0
Debug-interface
Serial Wire clock
input and JTAG
Test Clock.
DBG_SWCLKTCK
DBG_SWDIOTMS
DBG_SWO
Note that this func-
tion is enabled to
the pin out of reset,
and has a built-in
pull down.
0: PF1
Debug-interface
Serial Wire data in-
put / output and
JTAG Test Mode
Select.
Note that this func-
tion is enabled to
the pin out of reset,
and has a built-in
pull up.
0: PF2
Debug-interface
Serial Wire viewer
Output.
1: PB13
2: PD15
3: PC11
Note that this func-
tion is not enabled
after reset, and
must be enabled by
software to be
used.
0: PF3
Debug-interface
JTAG Test Data In.
Note that this func-
tion is enabled to
pin out of reset,
and has a built-in
pull up.
DBG_TDI
0: PF2
Debug-interface
JTAG Test Data
Out.
DBG_TDO
Note that this func-
tion is enabled to
pin out of reset.
0: PF8
1: PA5
2: PI2
Embedded Trace
Module ETM clock .
ETM_TCLK
ETM_TD0
ETM_TD1
3: PC6
0: PF9
1: PA6
2: PI3
Embedded Trace
Module ETM data
0.
3: PC7
0: PF10
1: PA7
2: PB6
3: PC8
Embedded Trace
Module ETM data
1.
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
Alternate
LOCATION
12 - 15 16 - 19
Functionality
0 - 3
4 - 7
8 - 11
20 - 23
24 - 27
28 - 31
Description
0: PF11
1: PA8
2: PB7
3: PC9
Embedded Trace
Module ETM data
2.
ETM_TD2
0: PF12
1: PA9
2: PB8
3: PC10
Embedded Trace
Module ETM data
3.
ETM_TD3
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15 14: PC9
12: PC7
13: PC8
16: PC11 20: PD12 24: PF0
17: PD9 21: PD13 25: PF1
18: PD10 22: PD14 26: PF2
15: PC10 19: PD11 23: PD15 27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
Frame Controller,
Data Sniffer Clock.
FRC_DCLK
11: PC6
0: PA2
1: PA3
2: PA4
3: PA5
4: PB11
5: PB12
6: PB13
7: PB14
8: PB15
9: PC6
10: PC7
11: PC8
12: PC9 16: PD10 20: PD14 24: PF2
13: PC10 17: PD11 21: PD15 25: PF3
28: PF6
29: PF7
30: PA0
31: PA1
Frame Controller,
Data Sniffer Frame
active
FRC_DFRAME
FRC_DOUT
14: PC11 18: PD12 22: PF0
26: PF4
27: PF5
15: PD9
19: PD13 23: PF1
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
16: PD9 20: PD13 24: PF1
17: PD10 21: PD14 25: PF2
28: PF5
29: PF6
30: PF7
31: PA0
Frame Controller,
Data Sniffer Out-
put.
5: PB11
6: PB12
7: PB13
14: PC10 18: PD11 22: PD15 26: PF3
15: PC11 19: PD12 23: PF0 27: PF4
0: PF2
Pin can be used to
wake the system
up from EM4
GPIO_EM4WU0
GPIO_EM4WU1
GPIO_EM4WU4
GPIO_EM4WU8
GPIO_EM4WU9
GPIO_EM4WU12
I2C0_SCL
0: PF7
Pin can be used to
wake the system
up from EM4
0: PD14
0: PA3
0: PB13
0: PC10
Pin can be used to
wake the system
up from EM4
Pin can be used to
wake the system
up from EM4
Pin can be used to
wake the system
up from EM4
Pin can be used to
wake the system
up from EM4
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
16: PD9
17: PD10 21: PD14 25: PF2
20: PD13 24: PF1
28: PF5
29: PF6
30: PF7
31: PA0
5: PB11
6: PB12
7: PB13
I2C0 Serial Clock
Line input / output.
14: PC10 18: PD11 22: PD15 26: PF3
15: PC11 19: PD12 23: PF0 27: PF4
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15 14: PC9
11: PC6
12: PC7
13: PC8
16: PC11 20: PD12 24: PF0
17: PD9 21: PD13 25: PF1
18: PD10 22: PD14 26: PF2
15: PC10 19: PD11 23: PD15 27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
I2C0 Serial Data in-
put / output.
I2C0_SDA
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0 - 3
4 - 7
4: PI3
5: PB6
6: PB7
7: PB8
8 - 11
12 - 15
16 - 19
20 - 23
24 - 27
28 - 31
Description
0: PA7
1: PA8
2: PA9
3: PI2
8: PB9
9: PB10
10: PJ14 14: PC2
11: PJ15 15: PC3
12: PC0
13: PC1
16: PC4
17: PC5
20: PF8
21: PF9
24: PF12 28: PK0
25: PF13 29: PK1
I2C1 Serial Clock
Line input / output.
I2C1_SCL
18: PC10 22: PF10 26: PF14 30: PK2
19: PC11 23: PF11 27: PF15 31: PA6
0: PA6
1: PA7
2: PA8
3: PA9
4: PI2
5: PI3
6: PB6
7: PB7
8: PB8
9: PB9
10: PB10 14: PC1
11: PJ14 15: PC2
12: PJ15 16: PC3
20: PC11 24: PF11 28: PF15
13: PC0
17: PC4
18: PC5
21: PF8
22: PF9
25: PF12 29: PK0
26: PF13 30: PK1
I2C1 Serial Data in-
put / output.
I2C1_SDA
19: PC10 23: PF10 27: PF14 31: PK2
0: PK0
0: PA8
0: PA9
0: PJ14
0: PJ15
0: PI0
IDAC0_OUT
LES_ALTEX0
LES_ALTEX1
LES_ALTEX2
LES_ALTEX3
LES_ALTEX4
LES_ALTEX5
LES_ALTEX6
LES_ALTEX7
LES_CH0
IDAC0 output.
LESENSE alternate
excite output 0.
LESENSE alternate
excite output 1.
LESENSE alternate
excite output 2.
LESENSE alternate
excite output 3.
LESENSE alternate
excite output 4.
0: PI1
LESENSE alternate
excite output 5.
0: PI2
LESENSE alternate
excite output 6.
0: PI3
LESENSE alternate
excite output 7.
0: PD8
0: PD9
LESENSE channel
0.
LESENSE channel
1.
LES_CH1
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
Alternate
LOCATION
12 - 15 16 - 19
Functionality
0 - 3
4 - 7
8 - 11
20 - 23
24 - 27
28 - 31
Description
0: PD10
LESENSE channel
2.
LES_CH2
LES_CH3
LES_CH4
LES_CH5
LES_CH6
LES_CH7
LES_CH8
LES_CH9
LES_CH10
LES_CH11
LES_CH12
LES_CH13
LES_CH14
0: PD11
0: PD12
0: PD13
0: PD14
0: PD15
0: PA0
0: PA1
0: PA2
0: PA3
0: PA4
0: PA5
0: PA6
LESENSE channel
3.
LESENSE channel
4.
LESENSE channel
5.
LESENSE channel
6.
LESENSE channel
7.
LESENSE channel
8.
LESENSE channel
9.
LESENSE channel
10.
LESENSE channel
11.
LESENSE channel
12.
LESENSE channel
13.
LESENSE channel
14.
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
Alternate
LOCATION
12 - 15 16 - 19
Functionality
0 - 3
4 - 7
8 - 11
20 - 23
24 - 27
28 - 31
Description
0: PA7
LESENSE channel
15.
LES_CH15
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15 14: PC9
12: PC7
13: PC8
16: PC11 20: PD12 24: PF0
17: PD9 21: PD13 25: PF1
18: PD10 22: PD14 26: PF2
15: PC10 19: PD11 23: PD15 27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
Low Energy Timer
LETIM0, output
channel 0.
LETIM0_OUT0
LETIM0_OUT1
LEU0_RX
11: PC6
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
16: PD9
20: PD13 24: PF1
28: PF5
29: PF6
30: PF7
31: PA0
Low Energy Timer
LETIM0, output
channel 1.
5: PB11
6: PB12
7: PB13
17: PD10 21: PD14 25: PF2
14: PC10 18: PD11 22: PD15 26: PF3
15: PC11 19: PD12 23: PF0 27: PF4
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
16: PD9
20: PD13 24: PF1
28: PF5
29: PF6
30: PF7
31: PA0
5: PB11
6: PB12
7: PB13
17: PD10 21: PD14 25: PF2
LEUART0 Receive
input.
14: PC10 18: PD11 22: PD15 26: PF3
15: PC11 19: PD12 23: PF0 27: PF4
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15 14: PC9
12: PC7
13: PC8
16: PC11 20: PD12 24: PF0
17: PD9 21: PD13 25: PF1
18: PD10 22: PD14 26: PF2
15: PC10 19: PD11 23: PD15 27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
LEUART0 Transmit
output. Also used
as receive input in
half duplex commu-
nication.
LEU0_TX
11: PC6
0: PB14
Low Frequency
Crystal (typically
32.768 kHz) nega-
tive pin. Also used
as an optional ex-
ternal clock input
pin.
LFXTAL_N
0: PB15
Low Frequency
Crystal (typically
32.768 kHz) posi-
tive pin.
LFXTAL_P
0: PA3
1: PA4
2: PA5
3: PB11
4: PB12
5: PB13
6: PB14
7: PB15
8: PC6
9: PC7
10: PC8
11: PC9
12: PC10 16: PD11 20: PD15 24: PF3
28: PF7
29: PA0
30: PA1
31: PA2
MODEM antenna
control output 0,
used for antenna
diversity.
13: PC11 17: PD12 21: PF0
14: PD9 18: PD13 22: PF1
15: PD10 19: PD14 23: PF2
25: PF4
26: PF5
27: PF6
MODEM_ANT0
MODEM_ANT1
MODEM_DCLK
MODEM_DIN
MODEM_DOUT
0: PA4
1: PA5
2: PB11
3: PB12
4: PB13
5: PB14
6: PB15
7: PC6
8: PC7
9: PC8
10: PC9
12: PC11 16: PD12 20: PF0
24: PF4
25: PF5
26: PF6
27: PF7
28: PA0
29: PA1
30: PA2
31: PA3
MODEM antenna
control output 1,
used for antenna
diversity.
13: PD9
17: PD13 21: PF1
14: PD10 18: PD14 22: PF2
11: PC10 15: PD11 19: PD15 23: PF3
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15 14: PC9
12: PC7
16: PC11 20: PD12 24: PF0
17: PD9 21: PD13 25: PF1
18: PD10 22: PD14 26: PF2
15: PC10 19: PD11 23: PD15 27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
13: PC8
MODEM data clock
out.
11: PC6
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
16: PD9
17: PD10 21: PD14 25: PF2
20: PD13 24: PF1
28: PF5
29: PF6
30: PF7
31: PA0
5: PB11
6: PB12
7: PB13
MODEM data in.
MODEM data out.
14: PC10 18: PD11 22: PD15 26: PF3
15: PC11 19: PD12 23: PF0 27: PF4
0: PA2
1: PA3
2: PA4
3: PA5
4: PB11
5: PB12
6: PB13
7: PB14
8: PB15
9: PC6
10: PC7
11: PC8
12: PC9 16: PD10 20: PD14 24: PF2
13: PC10 17: PD11 21: PD15 25: PF3
28: PF6
29: PF7
30: PA0
31: PA1
14: PC11 18: PD12 22: PF0
15: PD9 19: PD13 23: PF1
26: PF4
27: PF5
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
Alternate
LOCATION
12 - 15 16 - 19
Functionality
0 - 3
4 - 7
8 - 11
20 - 23
24 - 27
28 - 31
Description
0: PA4
Operational Amplifi-
er 0 external nega-
tive input.
OPA0_N
0: PA2
Operational Amplifi-
er 0 external posi-
tive input.
OPA0_P
0: PD15
0: PD13
0: PB13
0: PB12
Operational Amplifi-
er 1 external nega-
tive input.
OPA1_N
Operational Amplifi-
er 1 external posi-
tive input.
OPA1_P
Operational Amplifi-
er 2 external nega-
tive input.
OPA2_N
Operational Amplifi-
er 2 output.
OPA2_OUT
OPA2_OUTALT
OPA2_P
0: PB9
1: PB10
Operational Amplifi-
er 2 alternative out-
put.
0: PB11
Operational Amplifi-
er 2 external posi-
tive input.
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15 14: PC9
12: PC7
13: PC8
16: PC11 20: PD12 24: PF0
17: PD9 21: PD13 25: PF1
18: PD10 22: PD14 26: PF2
15: PC10 19: PD11 23: PD15 27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
Pulse Counter
PCNT0 input num-
ber 0.
PCNT0_S0IN
PCNT0_S1IN
PCNT1_S0IN
PCNT1_S1IN
PCNT2_S0IN
11: PC6
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
16: PD9
20: PD13 24: PF1
28: PF5
29: PF6
30: PF7
31: PA0
Pulse Counter
PCNT0 input num-
ber 1.
5: PB11
6: PB12
7: PB13
17: PD10 21: PD14 25: PF2
14: PC10 18: PD11 22: PD15 26: PF3
15: PC11 19: PD12 23: PF0 27: PF4
0: PA6
1: PA7
2: PA8
3: PA9
4: PI2
5: PI3
6: PB6
7: PB7
8: PB8
9: PB9
10: PB10 14: PC1
11: PJ14 15: PC2
12: PJ15 16: PC3
13: PC0
20: PF7
21: PF8
22: PF9
24: PF11 28: PF15
25: PF12 29: PK0
26: PF13 30: PK1
Pulse Counter
PCNT1 input num-
ber 0.
17: PC4
18: PC5
19: PF6
23: PF10 27: PF14 31: PK2
0: PA7
1: PA8
2: PA9
3: PI2
4: PI3
8: PB9
9: PB10
10: PJ14 14: PC2
11: PJ15 15: PC3
12: PC0
13: PC1
16: PC4
17: PC5
18: PF6
19: PF7
20: PF8
21: PF9
22: PF10 26: PF14 30: PK2
23: PF11 27: PF15 31: PA6
24: PF12 28: PK0
25: PF13 29: PK1
Pulse Counter
PCNT1 input num-
ber 1.
5: PB6
6: PB7
7: PB8
0: PA6
1: PA7
2: PA8
3: PA9
4: PI2
5: PI3
6: PB6
7: PB7
8: PB8
9: PB9
10: PB10 14: PC1
11: PJ14 15: PC2
12: PJ15 16: PC3
13: PC0
20: PC11 24: PF11 28: PF15
Pulse Counter
PCNT2 input num-
ber 0.
17: PC4
18: PC5
21: PF8
22: PF9
25: PF12 29: PK0
26: PF13 30: PK1
19: PC10 23: PF10 27: PF14 31: PK2
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0 - 3
4 - 7
4: PI3
5: PB6
6: PB7
7: PB8
8 - 11
12 - 15
16 - 19
20 - 23
24 - 27
28 - 31
Description
0: PA7
1: PA8
2: PA9
3: PI2
8: PB9
9: PB10
10: PJ14 14: PC2
11: PJ15 15: PC3
12: PC0
13: PC1
16: PC4
17: PC5
20: PF8
21: PF9
24: PF12 28: PK0
25: PF13 29: PK1
Pulse Counter
PCNT2 input num-
ber 1.
PCNT2_S1IN
PRS_CH0
PRS_CH1
PRS_CH2
PRS_CH3
PRS_CH4
PRS_CH5
PRS_CH6
PRS_CH7
PRS_CH8
PRS_CH9
PRS_CH10
PRS_CH11
18: PC10 22: PF10 26: PF14 30: PK2
19: PC11 23: PF11 27: PF15 31: PA6
0: PF0
1: PF1
2: PF2
3: PF3
4: PF4
5: PF5
6: PF6
7: PF7
8: PC6
9: PC7
10: PC8
11: PC9
12: PC10
13: PC11
Peripheral Reflex
System PRS, chan-
nel 0.
0: PF1
1: PF2
2: PF3
3: PF4
4: PF5
5: PF6
6: PF7
7: PF0
Peripheral Reflex
System PRS, chan-
nel 1.
0: PF2
1: PF3
2: PF4
3: PF5
4: PF6
5: PF7
6: PF0
7: PF1
Peripheral Reflex
System PRS, chan-
nel 2.
0: PF3
1: PF4
2: PF5
3: PF6
4: PF7
5: PF0
6: PF1
7: PF2
8: PD9
9: PD10
10: PD11 14: PD15
11: PD12
12: PD13
13: PD14
Peripheral Reflex
System PRS, chan-
nel 3.
0: PD9
4: PD13
5: PD14
6: PD15
Peripheral Reflex
System PRS, chan-
nel 4.
1: PD10
2: PD11
3: PD12
0: PD10
1: PD11
2: PD12
3: PD13
4: PD14
5: PD15
6: PD9
Peripheral Reflex
System PRS, chan-
nel 5.
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15 14: PD12
12: PD10 16: PD14
13: PD11 17: PD15
Peripheral Reflex
System PRS, chan-
nel 6.
11: PD9
15: PD13
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
8: PB14
9: PB15
10: PA0
Peripheral Reflex
System PRS, chan-
nel 7.
5: PB11
6: PB12
7: PB13
0: PA2
1: PA3
2: PA4
3: PA5
4: PB11
5: PB12
6: PB13
7: PB14
8: PB15
9: PA0
10: PA1
Peripheral Reflex
System PRS, chan-
nel 8.
0: PA3
1: PA4
2: PA5
3: PB11
4: PB12
5: PB13
6: PB14
7: PB15
8: PA0
9: PA1
10: PA2
11: PC6
12: PC7
13: PC8
14: PC9
15: PC10
16: PC11
Peripheral Reflex
System PRS, chan-
nel 9.
0: PC6
1: PC7
2: PC8
3: PC9
4: PC10
5: PC11
Peripheral Reflex
System PRS, chan-
nel 10.
0: PC7
1: PC8
2: PC9
3: PC10
4: PC11
5: PC6
Peripheral Reflex
System PRS, chan-
nel 11.
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Rev. 1.0 | 152
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
Alternate
LOCATION
12 - 15 16 - 19
16: PC11 20: PD12 24: PF0
Functionality
0 - 3
4 - 7
8 - 11
20 - 23
24 - 27
28 - 31
Description
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
12: PC7
13: PC8
28: PF4
29: PF5
30: PF6
31: PF7
Timer 0 Capture
Compare input /
output channel 0.
17: PD9 21: PD13 25: PF1
18: PD10 22: PD14 26: PF2
15: PC10 19: PD11 23: PD15 27: PF3
TIM0_CC0
TIM0_CC1
TIM0_CC2
TIM0_CDTI0
TIM0_CDTI1
TIM0_CDTI2
TIM1_CC0
TIM1_CC1
TIM1_CC2
TIM1_CC3
US0_CLK
10: PB15 14: PC9
11: PC6
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
16: PD9
17: PD10 21: PD14 25: PF2
20: PD13 24: PF1
28: PF5
29: PF6
30: PF7
31: PA0
Timer 0 Capture
Compare input /
output channel 1.
5: PB11
6: PB12
7: PB13
14: PC10 18: PD11 22: PD15 26: PF3
15: PC11 19: PD12 23: PF0 27: PF4
0: PA2
1: PA3
2: PA4
3: PA5
4: PB11
5: PB12
6: PB13
7: PB14
8: PB15
9: PC6
10: PC7
11: PC8
12: PC9 16: PD10 20: PD14 24: PF2
13: PC10 17: PD11 21: PD15 25: PF3
28: PF6
29: PF7
30: PA0
31: PA1
Timer 0 Capture
Compare input /
output channel 2.
14: PC11 18: PD12 22: PF0
15: PD9 19: PD13 23: PF1
26: PF4
27: PF5
0: PA3
1: PA4
2: PA5
3: PB11
4: PB12
5: PB13
6: PB14
7: PB15
8: PC6
9: PC7
10: PC8
11: PC9
12: PC10 16: PD11 20: PD15 24: PF3
28: PF7
29: PA0
30: PA1
31: PA2
Timer 0 Compli-
mentary Dead Time
Insertion channel 0.
13: PC11 17: PD12 21: PF0
14: PD9 18: PD13 22: PF1
15: PD10 19: PD14 23: PF2
25: PF4
26: PF5
27: PF6
0: PA4
1: PA5
2: PB11
3: PB12
4: PB13
5: PB14
6: PB15
7: PC6
8: PC7
9: PC8
10: PC9
12: PC11 16: PD12 20: PF0
24: PF4
25: PF5
26: PF6
27: PF7
28: PA0
29: PA1
30: PA2
31: PA3
Timer 0 Compli-
mentary Dead Time
Insertion channel 1.
13: PD9
17: PD13 21: PF1
14: PD10 18: PD14 22: PF2
11: PC10 15: PD11 19: PD15 23: PF3
0: PA5
4: PB14
5: PB15
6: PC6
7: PC7
8: PC8
9: PC9
12: PD9
13: PD10 17: PD14 21: PF2
10: PC10 14: PD11 18: PD15 22: PF3
11: PC11 15: PD12 19: PF0 23: PF4
16: PD13 20: PF1
24: PF5
25: PF6
26: PF7
27: PA0
28: PA1
29: PA2
30: PA3
31: PA4
Timer 0 Compli-
mentary Dead Time
Insertion channel 2.
1: PB11
2: PB12
3: PB13
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
12: PC7
16: PC11 20: PD12 24: PF0
17: PD9 21: PD13 25: PF1
18: PD10 22: PD14 26: PF2
15: PC10 19: PD11 23: PD15 27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
Timer 1 Capture
Compare input /
output channel 0.
13: PC8
10: PB15 14: PC9
11: PC6
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
16: PD9
17: PD10 21: PD14 25: PF2
20: PD13 24: PF1
28: PF5
29: PF6
30: PF7
31: PA0
Timer 1 Capture
Compare input /
output channel 1.
5: PB11
6: PB12
7: PB13
14: PC10 18: PD11 22: PD15 26: PF3
15: PC11 19: PD12 23: PF0 27: PF4
0: PA2
1: PA3
2: PA4
3: PA5
4: PB11
5: PB12
6: PB13
7: PB14
8: PB15
9: PC6
10: PC7
11: PC8
12: PC9 16: PD10 20: PD14 24: PF2
13: PC10 17: PD11 21: PD15 25: PF3
28: PF6
29: PF7
30: PA0
31: PA1
Timer 1 Capture
Compare input /
output channel 2.
14: PC11 18: PD12 22: PF0
15: PD9 19: PD13 23: PF1
26: PF4
27: PF5
0: PA3
1: PA4
2: PA5
3: PB11
4: PB12
5: PB13
6: PB14
7: PB15
8: PC6
9: PC7
10: PC8
11: PC9
12: PC10 16: PD11 20: PD15 24: PF3
28: PF7
29: PA0
30: PA1
31: PA2
Timer 1 Capture
Compare input /
output channel 3.
13: PC11 17: PD12 21: PF0
14: PD9 18: PD13 22: PF1
15: PD10 19: PD14 23: PF2
25: PF4
26: PF5
27: PF6
0: PA2
1: PA3
2: PA4
3: PA5
4: PB11
5: PB12
6: PB13
7: PB14
8: PB15
9: PC6
10: PC7
11: PC8
12: PC9
16: PD10 20: PD14 24: PF2
28: PF6
29: PF7
30: PA0
31: PA1
13: PC10 17: PD11 21: PD15 25: PF3
USART0 clock in-
put / output.
14: PC11 18: PD12 22: PF0
15: PD9 19: PD13 23: PF1
26: PF4
27: PF5
0: PA3
1: PA4
2: PA5
3: PB11
4: PB12
5: PB13
6: PB14
7: PB15
8: PC6
9: PC7
10: PC8
11: PC9
12: PC10 16: PD11 20: PD15 24: PF3
28: PF7
29: PA0
30: PA1
31: PA2
13: PC11 17: PD12 21: PF0
14: PD9 18: PD13 22: PF1
25: PF4
26: PF5
27: PF6
USART0 chip se-
lect input / output.
US0_CS
15: PD10 19: PD14 23: PF2
0: PA4
1: PA5
2: PB11
3: PB12
4: PB13
5: PB14
6: PB15
7: PC6
8: PC7
9: PC8
10: PC9
12: PC11 16: PD12 20: PF0
24: PF4
25: PF5
26: PF6
27: PF7
28: PA0
29: PA1
30: PA2
31: PA3
USART0 Clear To
Send hardware
flow control input.
13: PD9
17: PD13 21: PF1
US0_CTS
14: PD10 18: PD14 22: PF2
11: PC10 15: PD11 19: PD15 23: PF3
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Rev. 1.0 | 153
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
Alternate
LOCATION
12 - 15 16 - 19
12: PD9 16: PD13 20: PF1
Functionality
0 - 3
4 - 7
8 - 11
20 - 23
24 - 27
28 - 31
Description
0: PA5
4: PB14
5: PB15
6: PC6
7: PC7
8: PC8
9: PC9
24: PF5
25: PF6
26: PF7
27: PA0
28: PA1
29: PA2
30: PA3
31: PA4
USART0 Request
To Send hardware
flow control output.
1: PB11
2: PB12
3: PB13
13: PD10 17: PD14 21: PF2
US0_RTS
US0_RX
10: PC10 14: PD11 18: PD15 22: PF3
11: PC11 15: PD12 19: PF0 23: PF4
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
16: PD9
17: PD10 21: PD14 25: PF2
20: PD13 24: PF1
28: PF5
29: PF6
30: PF7
31: PA0
USART0 Asynchro-
nous Receive.
5: PB11
6: PB12
7: PB13
14: PC10 18: PD11 22: PD15 26: PF3
15: PC11 19: PD12 23: PF0 27: PF4
USART0 Synchro-
nous mode Master
Input / Slave Out-
put (MISO).
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15 14: PC9
12: PC7
13: PC8
16: PC11 20: PD12 24: PF0
17: PD9 21: PD13 25: PF1
18: PD10 22: PD14 26: PF2
15: PC10 19: PD11 23: PD15 27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
USART0 Asynchro-
nous Transmit. Al-
so used as receive
input in half duplex
communication.
11: PC6
US0_TX
USART0 Synchro-
nous mode Master
Output / Slave In-
put (MOSI).
0: PA2
1: PA3
2: PA4
3: PA5
4: PB11
5: PB12
6: PB13
7: PB14
8: PB15
9: PC6
10: PC7
11: PC8
12: PC9
16: PD10 20: PD14 24: PF2
28: PF6
29: PF7
30: PA0
31: PA1
13: PC10 17: PD11 21: PD15 25: PF3
14: PC11 18: PD12 22: PF0
15: PD9 19: PD13 23: PF1
USART1 clock in-
put / output.
US1_CLK
US1_CS
26: PF4
27: PF5
0: PA3
1: PA4
2: PA5
3: PB11
4: PB12
5: PB13
6: PB14
7: PB15
8: PC6
9: PC7
10: PC8
11: PC9
12: PC10 16: PD11 20: PD15 24: PF3
13: PC11 17: PD12 21: PF0
14: PD9 18: PD13 22: PF1
28: PF7
29: PA0
30: PA1
31: PA2
25: PF4
26: PF5
27: PF6
USART1 chip se-
lect input / output.
15: PD10 19: PD14 23: PF2
0: PA4
1: PA5
2: PB11
3: PB12
4: PB13
5: PB14
6: PB15
7: PC6
8: PC7
9: PC8
10: PC9
12: PC11 16: PD12 20: PF0
24: PF4
25: PF5
26: PF6
27: PF7
28: PA0
29: PA1
30: PA2
31: PA3
USART1 Clear To
Send hardware
flow control input.
13: PD9
17: PD13 21: PF1
US1_CTS
US1_RTS
14: PD10 18: PD14 22: PF2
11: PC10 15: PD11 19: PD15 23: PF3
0: PA5
4: PB14
5: PB15
6: PC6
7: PC7
8: PC8
9: PC9
12: PD9
16: PD13 20: PF1
24: PF5
25: PF6
26: PF7
27: PA0
28: PA1
29: PA2
30: PA3
31: PA4
USART1 Request
To Send hardware
flow control output.
1: PB11
2: PB12
3: PB13
13: PD10 17: PD14 21: PF2
10: PC10 14: PD11 18: PD15 22: PF3
11: PC11 15: PD12 19: PF0 23: PF4
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
16: PD9
17: PD10 21: PD14 25: PF2
20: PD13 24: PF1
28: PF5
29: PF6
30: PF7
31: PA0
USART1 Asynchro-
nous Receive.
5: PB11
6: PB12
7: PB13
14: PC10 18: PD11 22: PD15 26: PF3
15: PC11 19: PD12 23: PF0 27: PF4
USART1 Synchro-
nous mode Master
Input / Slave Out-
put (MISO).
US1_RX
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15 14: PC9
11: PC6
12: PC7
13: PC8
16: PC11 20: PD12 24: PF0
17: PD9 21: PD13 25: PF1
18: PD10 22: PD14 26: PF2
15: PC10 19: PD11 23: PD15 27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
USART1 Asynchro-
nous Transmit. Al-
so used as receive
input in half duplex
communication.
US1_TX
USART1 Synchro-
nous mode Master
Output / Slave In-
put (MOSI).
silabs.com | Building a more connected world.
Rev. 1.0 | 154
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0 - 3
4 - 7
4: PI1
5: PI2
6: PI3
7: PB6
8 - 11
12 - 15
16 - 19
20 - 23
24 - 27
28 - 31
Description
0: PA7
1: PA8
2: PA9
3: PI0
8: PB7
9: PB8
10: PB9
12: PF0
13: PF1
14: PF3
16: PF5
17: PF6
18: PF7
19: PF8
20: PF9
21: PF10 25: PF14 29: PK2
22: PF11 26: PF15 30: PA5
24: PF13 28: PK1
USART2 clock in-
put / output.
US2_CLK
US2_CS
11: PB10 15: PF4
23: PF12 27: PK0
31: PA6
0: PA8
1: PA9
2: PI0
3: PI1
4: PI2
5: PI3
6: PB6
7: PB7
8: PB8
9: PB9
10: PB10 14: PF4
12: PF1
13: PF3
16: PF6
17: PF7
18: PF8
19: PF9
20: PF10 24: PF14 28: PK2
21: PF11 25: PF15 29: PA5
22: PF12 26: PK0
23: PF13 27: PK1
USART2 chip se-
lect input / output.
30: PA6
31: PA7
11: PF0
15: PF5
0: PA9
1: PI0
2: PI1
3: PI2
4: PI3
8: PB9
12: PF3
13: PF4
14: PF5
15: PF6
16: PF7
17: PF8
18: PF9
20: PF11 24: PF15 28: PA5
USART2 Clear To
Send hardware
flow control input.
5: PB6
6: PB7
7: PB8
9: PB10
10: PF0
11: PF1
21: PF12 25: PK0
22: PF13 26: PK1
29: PA6
30: PA7
31: PA8
US2_CTS
US2_RTS
19: PF10 23: PF14 27: PK2
0: PI0
1: PI1
2: PI2
3: PI3
4: PB6
5: PB7
6: PB8
7: PB9
8: PB10
9: PF0
10: PF1
11: PF3
12: PF4
13: PF5
14: PF6
15: PF7
16: PF8
17: PF9
18: PF10 22: PF14 26: PK2
19: PF11 23: PF15 27: PA5
20: PF12 24: PK0
21: PF13 25: PK1
28: PA6
29: PA7
30: PA8
31: PA9
USART2 Request
To Send hardware
flow control output.
0: PA6
1: PA7
2: PA8
3: PA9
4: PI0
5: PI1
6: PI2
7: PI3
8: PB6
9: PB7
10: PB8
11: PB9
12: PB10 16: PF4
20: PF8
21: PF9
22: PF10 26: PF14 30: PK2
23: PF11 27: PF15 31: PA5
24: PF12 28: PK0
25: PF13 29: PK1
USART2 Asynchro-
nous Receive.
13: PF0
14: PF1
15: PF3
17: PF5
18: PF6
19: PF7
USART2 Synchro-
nous mode Master
Input / Slave Out-
put (MISO).
US2_RX
0: PA5
1: PA6
2: PA7
3: PA8
4: PA9
5: PI0
6: PI1
7: PI2
8: PI3
12: PB9
13: PB10 17: PF4
14: PF0
15: PF1
16: PF3
20: PF7
21: PF8
22: PF9
24: PF11 28: PF15 USART2 Asynchro-
9: PB6
10: PB7
11: PB8
25: PF12 29: PK0
26: PF13 30: PK1
nous Transmit. Al-
so used as receive
input in half duplex
communication.
18: PF5
19: PF6
23: PF10 27: PF14 31: PK2
US2_TX
USART2 Synchro-
nous mode Master
Output / Slave In-
put (MOSI).
0: PD10
1: PD11
2: PD12
3: PD13
4: PD14
5: PD15
6: PI2
8: PB6
9: PB7
10: PB8
11: PB9
12: PB10 16: PC0
13: PB11 17: PC1
14: PJ14 18: PC2
15: PJ15 19: PC3
20: PC4
21: PC5
22: PF11 26: PF15 30: PD8
23: PF12 27: PK0 31: PD9
24: PF13 28: PK1
25: PF14 29: PK2
USART3 clock in-
put / output.
US3_CLK
US3_CS
7: PI3
0: PD11
1: PD12
2: PD13
3: PD14
4: PD15
5: PI2
6: PI3
8: PB7
9: PB8
10: PB9
12: PB11 16: PC1
13: PJ14 17: PC2
14: PJ15 18: PC3
20: PC5 24: PF14 28: PK2
21: PF11 25: PF15 29: PD8
22: PF12 26: PK0
23: PF13 27: PK1
USART3 chip se-
lect input / output.
30: PD9
31: PD10
7: PB6
11: PB10 15: PC0
19: PC4
0: PD12
1: PD13
2: PD14
3: PD15
4: PI2
5: PI3
6: PB6
7: PB7
8: PB8
9: PB9
10: PB10 14: PC0
11: PB11 15: PC1
12: PJ14 16: PC2
13: PJ15 17: PC3
20: PF11 24: PF15 28: PD8
USART3 Clear To
Send hardware
flow control input.
21: PF12 25: PK0
22: PF13 26: PK1
23: PF14 27: PK2
29: PD9
30: PD10
31: PD11
US3_CTS
US3_RTS
18: PC4
19: PC5
0: PD13
1: PD14
2: PD15
3: PI2
4: PI3
8: PB9
9: PB10
10: PB11 14: PC1
11: PJ14 15: PC2
12: PJ15 16: PC3
20: PF12 24: PK0
21: PF13 25: PK1
22: PF14 26: PK2
28: PD9
USART3 Request
To Send hardware
flow control output.
5: PB6
6: PB7
7: PB8
13: PC0
17: PC4
18: PC5
29: PD10
30: PD11
31: PD12
19: PF11 23: PF15 27: PD8
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
Alternate
LOCATION
12 - 15 16 - 19
12: PB9 16: PJ15 20: PC3
Functionality
0 - 3
4 - 7
8 - 11
8: PI3
9: PB6
10: PB7
11: PB8
20 - 23
24 - 27
28 - 31
Description
0: PD9
4: PD13
5: PD14
6: PD15
7: PI2
24: PF12 28: PK0
25: PF13 29: PK1
26: PF14 30: PK2
USART3 Asynchro-
nous Receive.
1: PD10
2: PD11
3: PD12
13: PB10 17: PC0
14: PB11 18: PC1
15: PJ14 19: PC2
21: PC4
22: PC5
23: PF11 27: PF15 31: PD8
USART3 Synchro-
nous mode Master
Input / Slave Out-
put (MISO).
US3_RX
0: PD8
1: PD9
2: PD10
3: PD11
4: PD12
5: PD13
6: PD14
7: PD15
8: PI2
9: PI3
10: PB6
11: PB7
12: PB8
13: PB9
14: PB10 18: PC0
15: PB11 19: PC1
16: PJ14 20: PC2
17: PJ15 21: PC3
24: PF11 28: PF15 USART3 Asynchro-
25: PF12 29: PK0
26: PF13 30: PK1
27: PF14 31: PK2
nous Transmit. Al-
so used as receive
input in half duplex
communication.
22: PC4
23: PC5
US3_TX
USART3 Synchro-
nous mode Master
Output / Slave In-
put (MOSI).
0: PA1
0: PA3
Digital to analog
converter VDAC0
external reference
input pin.
VDAC0_EXT
Digital to Analog
Converter DAC0
output channel
number 0.
VDAC0_OUT0 /
OPA0_OUT
0: PA5
1: PD13
2: PD15
Digital to Analog
Converter DAC0 al-
ternative output for
channel 0.
VDAC0_OUT0AL
T / OPA0_OUT-
ALT
0: PD14
Digital to Analog
Converter DAC0
output channel
number 1.
VDAC0_OUT1 /
OPA1_OUT
0: PD12
1: PA2
2: PA4
Digital to Analog
Converter DAC0 al-
ternative output for
channel 1.
VDAC0_OUT1AL
T / OPA1_OUT-
ALT
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PA6
7: PA7
8: PA8
9: PA9
10: PB6
11: PB7
12: PB8
13: PB9
14: PB10 18: PB14 22: PC2
15: PB11 19: PB15 23: PC3
16: PB12 20: PC0
17: PB13 21: PC1
24: PC4
25: PC5
26: PC6
27: PC7
28: PC8
29: PC9
30: PC10 put / output channel
31: PC11 0.
Wide timer 0 Cap-
ture Compare in-
WTIM0_CC0
WTIM0_CC1
WTIM0_CC2
WTIM0_CDTI0
0: PA2
1: PA3
2: PA4
3: PA5
4: PA6
5: PA7
6: PA8
7: PA9
8: PB6
9: PB7
10: PB8
11: PB9
12: PB10 16: PB14 20: PC2
13: PB11 17: PB15 21: PC3
14: PB12 18: PC0
15: PB13 19: PC1
24: PC6
25: PC7
26: PC8
27: PC9
28: PC10 Wide timer 0 Cap-
29: PC11 ture Compare in-
30: PD8
31: PD9
22: PC4
23: PC5
put / output channel
1.
0: PA4
1: PA5
2: PA6
3: PA7
4: PA8
5: PA9
6: PB6
7: PB7
8: PB8
9: PB9
12: PB12 16: PC0
13: PB13 17: PC1
20: PC4
21: PC5
22: PC6
23: PC7
24: PC8
25: PC9
28: PD8
29: PD9
Wide timer 0 Cap-
ture Compare in-
10: PB10 14: PB14 18: PC2
11: PB11 15: PB15 19: PC3
26: PC10 30: PD10 put / output channel
27: PC11 31: PD11 2.
0: PA8
1: PA9
2: PB6
3: PB7
4: PB8
5: PB9
6: PB10
7: PB11
8: PB12
9: PB13
10: PB14 14: PC2
11: PB15 15: PC3
12: PC0
13: PC1
16: PC4
17: PC5
18: PC6
19: PC7
20: PC8
21: PC9
24: PD8
25: PD9
28: PD12 Wide timer 0 Com-
29: PD13 plimentary Dead
22: PC10 26: PD10 30: PD14 Time Insertion
23: PC11 27: PD11 31: PD15 channel 0.
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0 - 3
4 - 7
8 - 11
12 - 15
16 - 19
20 - 23
24 - 27
28 - 31
Description
0: PB6
1: PB7
2: PB8
3: PB9
4: PB10
5: PB11
6: PB12
7: PB13
8: PB14
9: PB15
10: PC0
11: PC1
12: PC2
13: PC3
14: PC4
15: PC5
16: PC6
17: PC7
18: PC8
19: PC9
20: PC10 24: PD10 28: PD14 Wide timer 0 Com-
21: PC11 25: PD11 29: PD15 plimentary Dead
WTIM0_CDTI1
WTIM0_CDTI2
WTIM1_CC0
WTIM1_CC1
WTIM1_CC2
WTIM1_CC3
22: PD8
23: PD9
26: PD12 30: PF0
27: PD13 31: PF1
Time Insertion
channel 1.
0: PB8
1: PB9
2: PB10
3: PB11
4: PB12
5: PB13
6: PB14
7: PB15
8: PC0
9: PC1
10: PC2
11: PC3
12: PC4
13: PC5
14: PC6
15: PC7
16: PC8
17: PC9
20: PD8
21: PD9
24: PD12 28: PF0
25: PD13 29: PF1
Wide timer 0 Com-
plimentary Dead
Time Insertion
channel 2.
18: PC10 22: PD10 26: PD14 30: PF2
19: PC11 23: PD11 27: PD15 31: PF3
0: PB12
1: PB13
2: PB14
3: PB15
4: PC0
5: PC1
6: PC2
7: PC3
8: PC4
9: PC5
10: PC6
11: PC7
12: PC8
13: PC9
16: PD8
17: PD9
20: PD12 24: PF0
21: PD13 25: PF1
28: PF4
29: PF5
30: PF6
31: PF7
Wide timer 1 Cap-
ture Compare in-
put / output channel
0.
14: PC10 18: PD10 22: PD14 26: PF2
15: PC11 19: PD11 23: PD15 27: PF3
0: PB14
1: PB15
2: PC0
3: PC1
4: PC2
5: PC3
6: PC4
7: PC5
8: PC6
9: PC7
10: PC8
11: PC9
12: PC10 16: PD10 20: PD14 24: PF2
13: PC11 17: PD11 21: PD15 25: PF3
14: PD8
15: PD9
28: PF6
29: PF7
30: PF8
31: PF9
Wide timer 1 Cap-
ture Compare in-
put / output channel
1.
18: PD12 22: PF0
19: PD13 23: PF1
26: PF4
27: PF5
0: PC0
1: PC1
2: PC2
3: PC3
4: PC4
5: PC5
6: PC6
7: PC7
8: PC8
9: PC9
12: PD8
13: PD9
16: PD12 20: PF0
17: PD13 21: PF1
24: PF4
25: PF5
26: PF6
27: PF7
28: PF8
29: PF9
30: PF10 put / output channel
31: PF11 2.
Wide timer 1 Cap-
ture Compare in-
10: PC10 14: PD10 18: PD14 22: PF2
11: PC11 15: PD11 19: PD15 23: PF3
0: PC2
1: PC3
2: PC4
3: PC5
4: PC6
5: PC7
6: PC8
7: PC9
8: PC10
9: PC11
10: PD8
11: PD9
12: PD10 16: PD14 20: PF2
13: PD11 17: PD15 21: PF3
14: PD12 18: PF0
15: PD13 19: PF1
24: PF6
25: PF7
26: PF8
27: PF9
28: PF10 Wide timer 1 Cap-
29: PF11 ture Compare in-
30: PF12 put / output channel
31: PF13 3.
22: PF4
23: PF5
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
6.9 Analog Port (APORT) Client Maps
The Analog Port (APORT) is an infrastructure used to connect chip pins with on-chip analog clients such as analog comparators, ADCs,
DACs, etc. The APORT consists of a set of shared buses, switches, and control logic needed to configurably implement the signal rout-
ing. Figure 6.7 APORT Connection Diagram on page 158 Shows the APORT routing for this device family. A complete description of
APORT functionality can be found in the Reference Manual.
1X
IDAC0
1Y
ACMP1X
ACMP1Y
PB15
0X
1X
2X
3X
4X
PB14
PB13
PF0
PF1
0X
1X
2X
3X
4X
POS
NEG
POS
NEG
OPA2_N
OUT2
ACMP0
PF2
0Y
1Y
2Y
3Y
4Y
PB12
PB11
ACMP1
0Y
1Y
2Y
3Y
4Y
PF3
PF8
PF9
OPA2_P
PF10
PF11
PF12
PF13
PF14
PF15
PK0
PK1
PK2
PF4
PB10
PB9
VDAC0_OPA2ALT
VDAC0_OPA2ALT
OUT2ALT
OUT2ALT
0X
1X
2X
3X
4X
POS
NEG
PB8
PB7
0Y
1Y
2Y
3Y
4Y
PB6
ADC0
PI3
PI2
EXTP
EXTN
PI1
OPA1_P
1X
2X
3X
4X
PI0
POS
NEG
OPA0_P
1X
2X
3X
4X
PF5
PA9
POS
NEG
PF6
PA8
OPA1_N
1Y
2Y
3Y
4Y
PF7
PA7 LESENSE
PA6 LESENSE
OPA0_N
1Y
2Y
OPA1
OPA0
3Y
4Y
PA5 LESENSE
PA4 LESENSE
PA3 LESENSE
PA2 LESENSE
OUT1
OUT1ALT
OUT1
VDAC0_OUT0ALT
VDAC0_OUT1ALT
OUT0ALT
OUT1ALT
OUT0
OUT0ALT
OUT1
OUT2
OUT3
OUT
OUT2
OUT3
OUT4
OUT
OPA0_INN0
OPA0_N
OUT4
OPA0_OUT
OUT0
VDAC0_OUT1ALT
OUT1ALT
OPA2_P
1X
POS
NEG
OPA0_INP0
ADC0_EXTP
2X
3X
4X
OPA0_P
PA1 LESENSE
PA0 LESENSE
ADC_EXTP
OPA2_N
1Y
2Y
3Y
4Y
ADC0_EXTN
OPA0ALT
ADC_EXTN
OUT0ALT
OPA2
PD15 LESENSE
OPA1_INN0
OUT2
OUT2ALT
OUT1
OPA1N
OUT
OUT2
OUT3
OUT4
1X
1Y
3X
3Y
CEXT
CSEN
2X
2Y
nX, nY
APORTnX, APORTnY
CEXT_SENSE
4X
4Y
AX, BY, …
BUSAX, BUSBY, ...
ADC0X,
ADC0Y
BUSADC0X,
BUSADC0Y
ACMP0X,
BUSACMP0X,
ACMP1Y, … BUSACMP1Y, ...
Figure 6.7. APORT Connection Diagram
Client maps for each analog circuit using the APORT are shown in the following tables. The maps are organized by bus, and show the
peripheral's port connection, the shared bus, and the connection from specific bus channel numbers to GPIO pins.
In general, enumerations for the pin selection field in an analog peripheral's register can be determined by finding the desired pin con-
nection in the table and then combining the value in the Port column (APORT__), and the channel identifier (CH__). For example, if pin
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
PF7 is available on port APORT2X as CH23, the register field enumeration to connect to PF7 would be APORT2XCH23. The shared
bus used by this connection is indicated in the Bus column.
Table 6.9. ACMP0 Bus and Pin Mapping
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
Table 6.10. ACMP1 Bus and Pin Mapping
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
Table 6.11. ADC0 Bus and Pin Mapping
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
Table 6.12. CSEN Bus and Pin Mapping
CEXT
CEXT_SENSE
Table 6.13. IDAC0 Bus and Pin Mapping
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
Table 6.14. VDAC0 / OPA Bus and Pin Mapping
OPA0_N
OPA0_P
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
OPA1_N
OPA1_P
OPA2_N
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
OPA2_OUT
OPA2_P
VDAC0_OUT0 / OPA0_OUT
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
VDAC0_OUT1 / OPA1_OUT
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
BGA125 Package Specifications
7. BGA125 Package Specifications
7.1 BGA125 Package Dimensions
Figure 7.1. BGA125 Package Drawing
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
BGA125 Package Specifications
Table 7.1. BGA125 Package Dimensions
Dimension
Min
0.80
0.16
0.61
0.17
6.90
6.90
---
Typ
0.87
0.21
0.66
0.21
7.00
7.00
6.00
6.00
0.50
0.30
0.10
0.10
0.08
0.15
0.05
Max
0.94
0.26
0.71
0.25
7.10
7.10
---
A
A1
A2
c
D
E
D1
E1
e
---
---
---
---
b
0.25
0.35
aaa
bbb
ddd
eee
fff
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
BGA125 Package Specifications
7.2 BGA125 PCB Land Pattern
Figure 7.2. BGA125 PCB Land Pattern Drawing
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
BGA125 Package Specifications
Table 7.2. BGA125 PCB Land Pattern Dimensions
Dimension
Min
Nom
0.25
6.00
6.00
0.5
Max
X
C1
C2
E1
E2
0.5
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
6. The stencil thickness should be 0.125 mm (5 mils).
7. The ratio of stencil aperture to land pad size should be 1:1.
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
BGA125 Package Specifications
7.3 BGA125 Package Marking
EFR32
PPPPPPPPPP
YYWWTTTTTT
Figure 7.3. BGA125 Package Marking
The package marking consists of:
• PPPPPPPPP – The part number designation.
1. Family Code (B | M | F)
2. G (Gecko)
3. Series (1, 2,...)
4. Device Configuration (1, 2,...)
5. Performance Grade (P | B | V)
6. Feature Code (1 to 7)
7. TRX Code (3 = TXRX | 2= RX | 1 = TX)
8. Band (1 = Sub-GHz | 2 = 2.4 GHz | 3 = Dual-band)
9. Flash (J = 1024K | H = 512K | G = 256K | F = 128K | E = 64K | D = 32K)
10. Temperature Grade (G = -40 to 85 | I = -40 to 125)
• YY – The last 2 digits of the assembly year.
• WW – The 2-digit workweek when the device was assembled.
• TTTTTT – A trace or manufacturing code. The first letter is the device revision.
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
QFN48 Package Specifications
8. QFN48 Package Specifications
8.1 QFN48 Package Dimensions
Figure 8.1. QFN48 Package Drawing
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
QFN48 Package Specifications
Table 8.1. QFN48 Package Dimensions
Dimension
Min
0.80
0.00
Typ
0.85
Max
0.90
0.05
A
A1
A3
b
0.02
0.20 REF
0.25
0.18
6.90
6.90
5.15
5.15
0.30
7.10
7.10
5.45
5.45
D
7.00
E
7.00
D2
E2
e
5.30
5.30
0.50 BSC
0.40
L
0.30
0.20
0.09
0.50
—
K
—
R
—
—
aaa
bbb
ccc
ddd
eee
fff
0.15
0.10
0.10
0.05
0.08
0.10
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220, Variation VKKD-4.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
QFN48 Package Specifications
8.2 QFN48 PCB Land Pattern
Figure 8.2. QFN48 PCB Land Pattern Drawing
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
QFN48 Package Specifications
Table 8.2. QFN48 PCB Land Pattern Dimensions
Dimension
Typ
6.01
6.01
4.70
4.70
0.50
0.26
0.86
S1
S
L1
W1
e
W
L
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size can be 1:1 for all perimeter pads.
7. A 4x4 array of 0.75 mm square openings on a 1.00 mm pitch can be used for the center ground pad.
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
QFN48 Package Specifications
8.3 QFN48 Package Marking
EFR32
PPPPPPPPPP
YYWWTTTTTT
Figure 8.3. QFN48 Package Marking
The package marking consists of:
• PPPPPPPPP – The part number designation.
1. Family Code (B | M | F)
2. G (Gecko)
3. Series (1, 2,...)
4. Device Configuration (1, 2,...)
5. Performance Grade (P | B | V)
6. Feature Code (1 to 7)
7. TRX Code (3 = TXRX | 2= RX | 1 = TX)
8. Band (1 = Sub-GHz | 2 = 2.4 GHz | 3 = Dual-band)
9. Flash (J = 1024K | H = 512K | G = 256K | F = 128K | E = 64K | D = 32K)
10. Temperature Grade (G = -40 to 85 | I = -40 to 125)
• YY – The last 2 digits of the assembly year.
• WW – The 2-digit workweek when the device was assembled.
• TTTTTT – A trace or manufacturing code. The first letter is the device revision.
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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Revision History
9. Revision History
9.1 Revision 1.0
2017-04-14
• Added Thermal Characteristics table.
• Finalized specification tables. All tables were updated with latest characterization data and production test limits.
• Updated typical performance graphs for DC-DC.
• Minor typographical, clarity, and consistency improvements.
• Condensed pin function tables with new formatting.
9.2 Revision 0.6
2017-02-23
• Updated 2 Mbps 2GFSK receiver specifications with latest characteriztion data.
• Added table-wide conditions to 2GFSK 1 Mbps and 2 Mbps receiver tables.
• Clarified opamp noise measurement conditions in electrical spec table.
9.3 Revision 0.5
2017-02-03
• New corporate stylesheet applied.
• Updated device block diagrams on front page and in System Overview.
• Updated Feature List with latest characterization numbers.
• "Bluetooth Smart" changed to "Bluetooth Low Energy" throughout document.
• All OPNs changed to revision B.
• Minor typographical corrections and clarifications in System Overview.
• Electrical Characteristics Table Changes
• All specification tables updated with latest characterization data and production test limits.
• Split 2.4 GHz 2GFSK tables into separate tables for 1 Mbps and 2 Mbps data rates.
• Split HFRCO/AUXHFRCO table into separate tables for HFRCO and AUXHFRCO.
• OPAMP, CSEN, and VDAC specification line items updated to match test conditions.
• Added tables for Analog Port (APORT) and Pulse Counter (PCNT).
• Added Typical Performance Curves for supply current, DCDC, and RF parameters.
• Added missing alternate functions and descriptions to Pinout and Alternate Function tables.
• Added APORT Connection Diagram.
• Corrected Package Marking description for QFN48 and BGA125.
• Corrected Package Marking diagram for QFN48.
9.4 Revision 0.2
2016-09-21
Initial release.
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Rev. 1.0 | 177
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