EFR32FG1P132F64GM48-B0 [SILICON]
EFR32FG1 Flex Gecko Proprietary Protocol SoC Family Data Sheet;型号: | EFR32FG1P132F64GM48-B0 |
厂家: | SILICON |
描述: | EFR32FG1 Flex Gecko Proprietary Protocol SoC Family Data Sheet |
文件: | 总101页 (文件大小:4166K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
EFR32FG1 Flex Gecko Proprietary
Protocol SoC Family Data Sheet
The Flex Gecko proprietary protocol family of SoCs is part of the
KEY FEATURES
Wireless Gecko portfolio. Flex Gecko SoCs are ideal for enabling
energy-friendly proprietary protocol networking for IoT devices.
• 32-bit ARM® Cortex®-M4 core with 40
MHz maximum operating frequency
The single-die solution provides industry-leading energy efficiency, ultra-fast wakeup
times, a scalable power amplifier, an integrated balun and no-compromise MCU fea-
tures.
• Scalable Memory and Radio configuration
options available in several footprint
compatible QFN packages
• 12-channel Peripheral Reflex System
enabling autonomous interaction of MCU
peripherals
Flex Gecko applications include:
• Commercial and Retail
• Home and Building Automation and Security
• Metering
• Autonomous Hardware Crypto Accelerator
and Random Number Generator
• Integrated 2.4 GHz balun and PA with up
to 19.5 dBm transmit power
• Electronic Shelf Labels
• Industrial Automation
• Integrated DC-DC with RF noise mitigation
Core / Memory
Clock Management
Energy Management
Other
High Frequency
Crystal
Oscillator
High Frequency
RC Oscillator
Voltage
CRYPTO
Voltage Monitor
Regulator
ARM CortexTM M4 processor
Memory
with DSP extensions and FPU
Protection Unit
Auxiliary High
Frequency RC
Oscillator
Low Frequency
RC Oscillator
DC-DC
Power-On Reset
Converter
CRC
Low Frequency
Crystal
Oscillator
Ultra Low
Frequency RC
Oscillator
Flash Program
RAM Memory
Memory
Brown-Out
Detector
Debug Interface
DMA Controller
32-bit bus
Peripheral Reflex System
Radio Transceiver
Serial
I/O Ports
Timers and Triggers
Analog I/F
Interfaces
External
Interrupts
RFSENSE
BALUN
DEMOD
USART
Timer/Counter
Protocol Timer
ADC
Low Energy
UARTTM
General
Purpose I/O
Low Energy
Timer
Analog
Comparator
IFADC
AGC
PGA
I
Watchdog Timer
LNA
RF Frontend
Real Time
Counter and
Calendar
I2C
Pin Reset
Pulse Counter
IDAC
PA
Frequency
Synthesizer
Q
MOD
Pin Wakeup
Cryotimer
Lowest power mode with peripheral operational:
EM0—Active EM1—Sleep
EM2—Deep Sleep
EM3—Stop
EM4—Hibernate
EM4—Shutoff
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This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Preliminary Rev. 0.9
EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Feature List
1. Feature List
The EFR32FG1 highlighted features are listed below.
• Low Power Wireless System-on-Chip.
• Wide selection of MCU peripherals
High Performance 32-bit 40 MHz ARM Cortex®-M4 with
DSP instruction and floating-point unit for efficient signal
processing
•
• 12-bit 1 Msps SAR Analog to Digital Converter (ADC)
• 2× Analog Comparator (ACMP)
• Digital to Analog Current Converter (IDAC)
• Up to 256 kB flash program memory
• Up to 32 kB RAM data memory
• 2.4 GHz radio operation
• Up to 31 pins connected to analog channels (APORT)
shared between Analog Comparators, ADC, and IDAC
• Up to 31 General Purpose I/O pins with output state reten-
tion and asynchronous interrupts
• TX power up to 19.5 dBm
• 8 Channel DMA Controller
• Low Energy Consumption
• 12 Channel Peripheral Reflex System (PRS)
• 2×16-bit Timer/Counter
• 8.7 mA RX current at 2.4 GHz
• 8.8 mA TX current @ 0 dBm output power at 2.4 GHz
• 63 μA/MHz in Active Mode (EM0)
• 3 + 4 Compare/Capture/PWM channels
• 32-bit Real Time Counter and Calendar
• 16-bit Low Energy Timer for waveform generation
• 1.4 μA EM2 DeepSleep current (full RAM retention and
RTCC running from LFXO)
• 1.1 μA EM3 Stop current (State/RAM retention)
• 32-bit Ultra Low Energy Timer/Counter for periodic wake-up
from any Energy Mode
• Wake on Radio with signal strength detection, preamble
pattern detection, frame detection and timeout
• 16-bit Pulse Counter with asynchronous operation
• Watchdog Timer with dedicated RC oscillator @ 50nA
• 2×Universal Synchronous/Asynchronous Receiver/Trans-
mitter (UART/SPI/SmartCard (ISO 7816)/IrDA/I2S)
• High Receiver Performance
• -94 dBm sensitivity @ 1 Mbit/s GFSK (2.4GHz)
• Supported Modulation Formats
• 2-FSK / 4-FSK with fully configurable shaping
• Shaped OQPSK / (G)MSK
Low Energy UART (LEUART™)
I2C interface with SMBus support and address recognition
in EM3 Stop
•
•
• Configurable DSSS and FEC
• Supported Protocols:
• Wide Operating Range
• 2.4 GHz Proprietary Protocols
• Support for Internet Security
• General Purpose CRC
• 1.85 V to 3.8 V single power supply
• Integrated DC-DC, down to 1.8 V output with up to 200 mA
load current for system
• -40 °C to 85 °C
• Random Number Generator
• QFN32 5x5 mm Package
• QFN48 7x7 mm Package
• Hardware Cryptographic Acceleration for AES 128/256,
SHA-1, SHA-2 (SHA-224 and SHA-256) and ECC
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Preliminary Rev. 0.9 | 1
EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Ordering Information
2. Ordering Information
Ordering Code
Protocol Stack
Frequency Max TX Encryption
Flash
(KB)
RAM
(KB)
GPIO Package
Band
Power
(dBm)
EFR32FG1P132F256GM48-B0*
EFR32FG1P132F256GM32-B0*
EFR32FG1P132F128GM48-B0*
EFR32FG1P132F128GM32-B0*
EFR32FG1P132F64GM48-B0*
EFR32FG1P132F64GM32-B0*
EFR32FG1V132F256GM48-B0*
EFR32FG1V132F256GM32-B0*
EFR32FG1V132F128GM48-B0*
EFR32FG1V132F128GM32-B0*
EFR32FG1V132F64GM48-B0*
EFR32FG1V132F64GM32-B0*
EFR32FG1V132F32GM48-B0*
Proprietary
Proprietary
Proprietary
Proprietary
Proprietary
Proprietary
Proprietary
Proprietary
Proprietary
Proprietary
Proprietary
Proprietary
Proprietary
Proprietary
2.4 GHz
2.4 GHz
2.4 GHz
2.4 GHz
2.4 GHz
2.4 GHz
2.4 GHz
2.4 GHz
2.4 GHz
2.4 GHz
2.4 GHz
2.4 GHz
2.4 GHz
2.4 GHz
19.5
19.5
19.5
19.5
19.5
19.5
16.5
16.5
16.5
16.5
16.5
16.5
16.5
16.5
Full
256
256
128
128
64
32
32
32
32
16
16
32
32
16
16
16
16
8
31
16
31
16
31
16
31
16
31
16
31
16
31
16
QFN48
QFN32
QFN48
QFN32
QFN48
QFN32
QFN48
QFN32
QFN48
QFN32
QFN48
QFN32
QFN48
QFN32
Full
Full
Full
Full
Full
64
AES only
AES only
AES only
AES only
AES only
AES only
AES only
AES only
256
256
128
128
64
64
32
EFR32FG1V132F32GM32-B0*
* Engineering Samples
32
8
EFR32 X G 1 P 132 F 256 G M 32 – B0 R
Tape and Reel (Optional)
Revision
Pin Count
Package – M (QFN), J (CSP)
Temperature Grade – G (-40 to +85 °C), -I (-40 to +125 °C)
Flash Memory Size in kB
Memory Type (Flash)
Feature Set Code – r2r1r0
r2: Reserved
r1: RF Type – 3 (TRX), 2 (RX), 1 (TX)
r0: Frequency Band – 1 (Sub-GHz), 2 (2.4 GHz), 3 (Dual-Band)
Performance Grade – P (Performance), B (Basic), V (Value)
Generation
Gecko
Family – M (Mighty), B (Blue), F (Flex)
Wireless Gecko 32-bit
Figure 2.1. OPN Decoder
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Preliminary Rev. 0.9 | 2
EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
System Overview
3. System Overview
3.1 Introduction
The EFR32 product family combines an energy-friendly MCU with a highly integrated radio transceiver. The devices are well suited for
any battery operated application as well as other systems requiring high performance and low energy consumption. This section gives a
short introduction to the full radio and MCU system. The detailed functional description can be found in the EFR32 Reference Manual.
A block diagram of the EFR32FG1 family is shown in Figure 3.1 Detailed EFR32FG1 Block Diagram on page 3. The diagram shows
a superset of features available on the family, which vary by OPN. For more information about specific device features, consult Order-
ing Information.
Port I/O Configuration
Radio Transciever
DEMOD
Digital Peripherals
RFSENSE
BALUN
RF Frontend
PGA
IFADC
AGC
LETIMER
I
IOVDD
LNA
TIMER
2G4RF_IOP
2G4RF_ION
PA
Frequency
Synthesizer
Q
CRYOTIMER
PCNT
MOD
Port A
Drivers
PAn
RTC / RTCC
USART
Port
Mapper
Energy Management
ARM Cortex-M4 Core
Port B
PAVDD
RFVDD
PBn
PCn
PDn
PFn
Drivers
Up to 256 KB ISP Flash
Program Memory
LEUART
I2C
IOVDD
AVDD
Up to 32 KB RAM
Memory Protection Unit
Floating Point Unit
DMA Controller
Voltage
Monitor
CRYPTO
CRC
Port C
Drivers
A
H
B
A
P
B
DVDD
bypass
Port D
Drivers
VREGVDD
VREGSW
Analog Peripherals
DC-DC
Converter
Voltage
Regulator
Serial Wire Debug /
Programming
Internal
Reference
IDAC
DECOUPLE
Watchdog
Timer
Port F
Drivers
VDD
VREF
VSS
VREGVSS
RFVSS
Brown Out /
Power-On
Reset
Clock Management
VDD
12-bit ADC
PAVSS
ULFRCO
AUXHFRCO
LFRCO
Reset
Management
Unit
RESETn
Temp
Sensor
HFRCO
LFXO
LFXTAL_P / N
+
-
HFXTAL_P
HFXTAL_N
HFXO
Analog Comparator
Figure 3.1. Detailed EFR32FG1 Block Diagram
3.2 Radio
The Flex Gecko family features a radio transceiver supporting proprietary wireless protocols.
3.2.1 Antenna Interface
The 2.4 GHz antenna interface consists of two pins (2G4RF_IOP and 2G4RF_ION) that interface directly to the on-chip BALUN. The
2G4RF_ION pin should be grounded externally.
The external components and power supply connections for the antenna interface typical applications are shown in the RF Matching
Networks section.
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Preliminary Rev. 0.9 | 3
EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
System Overview
3.2.2 Fractional-N Frequency Synthesizer
The EFR32FG1 contains a high performance, low phase noise, fully integrated fractional-N frequency synthesizer. The synthesizer is
used in receive mode to generate the LO frequency used by the down-conversion mixer. It is also used in transmit mode to directly
generate the modulated RF carrier.
The fractional-N architecture provides excellent phase noise performance combined with frequency resolution better than 100 Hz, with
low energy consumption. The synthesizer has fast frequency settling which allows very short receiver and transmitter wake up times to
optimize system energy consumption.
3.2.3 Receiver Architecture
The EFR32FG1 uses a low-IF receiver architecture, consisting of a Low-Noise Amplifier (LNA) followed by an I/Q down-conversion mix-
er, employing a crystal reference. The I/Q signals are further filtered and amplified before being sampled by the IF analog-to-digital
converter (IFADC).
The IF frequency is configurable from 150 kHz to 1371 kHz. The IF can further be configured for high-side or low-side injection, provid-
ing flexibility with respect to known interferers at the image frequency.
The Automatic Gain Control (AGC) module adjusts the receiver gain to optimize performance and avoid saturation for excellent selec-
tivity and blocking performance. Devices are production-calibrated to improve image rejection performance.
Demodulation is performed in the digital domain. The demodulator performs configurable decimation and channel filtering to allow re-
ceive bandwidths ranging from 0.1 to 2530 kHz. High carrier frequency and baud rate offsets are tolerated by active estimation and
compensation. Advanced features supporting high quality communication under adverse conditions include forward error correction by
block and convolutional coding as well as Direct Sequence Spread Spectrum (DSSS).
A Received Signal Strength Indicator (RSSI) is available for signal quality metrics, for level-based proximity detection, and for RF chan-
nel access by Collision Avoidance (CA) or Listen Before Talk (LBT) algorithms. An RSSI capture value is associated with each received
frame and the dynamic RSSI measurement can be monitored throughout reception.
The EFR32FG1 features integrated support for antenna diversity to improve link budget, using complementary control outputs to an
external switch. Internal configurable hardware controls automatic switching between antennae during RF receive detection operations.
3.2.4 Transmitter Architecture
The EFR32FG1 uses a direct-conversion transmitter architecture. For constant envelope modulation formats, the modulator controls
phase and frequency modulation in the frequency synthesizer. Transmit symbols or chips are optionally shaped by a digital shaping
filter. The shaping filter is fully configurable, including the BT product, and can be used to implement Gaussian or Raised Cosine shap-
ing.
Carrier Sense Multiple Access - Collision Avoidance (CSMA-CA) or Listen Before Talk (LBT) algorithms can be automatically timed by
the EFR32FG1. These algorithms are typically defined by regulatory standards to improve inter-operability in a given bandwidth be-
tween devices that otherwise lack synchronized RF channel access.
3.2.5 Wake on Radio
The Wake on Radio feature allows flexible, autonomous RF sensing, qualification, and demodulation without required MCU activity, us-
ing a subsystem of the EFR32FG1 including the Radio Controller (RAC), Peripheral Reflex System (PRS), and Low Energy peripherals.
3.2.6 RFSENSE
The RFSENSE module generates a system wakeup interrupt upon detection of wideband RF energy at the antenna interface, providing
true RF wakeup capabilities from low energy modes including EM2, EM3 and EM4.
RFSENSE triggers on a relatively strong RF signal and is available in the lowest energy modes, allowing exceptionally low energy con-
sumption. RFSENSE does not demodulate or otherwise qualify the received signal, but software may respond to the wakeup event by
enabling normal RF reception.
Various strategies for optimizing power consumption and system response time in presence of false alarms may be employed using
available timer peripherals.
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
System Overview
3.2.7 Flexible Frame Handling
EFR32FG1 has an extensive and flexible frame handling support for easy implementation of even complex communication protocols.
The Frame Controller (FRC) supports all low level and timing critical tasks together with the Radio Controller and Modulator/Demodula-
tor:
• Highly adjustable preamble length
• Up to 2 simultaneous synchronization words, each up to 32 bits and providing separate interrupts
• Frame disassembly and address matching (filtering) to accept or reject frames
• Automatic ACK frame assembly and transmission
• Fully flexible CRC generation and verification:
• Multiple CRC values can be embedded in a single frame
• 8, 16, 24 or 32-bit CRC value
• Configurable CRC bit and byte ordering
• Selectable bit-ordering (least significant or most significant bit first)
• Optional data whitening
• Optional Forward Error Correction (FEC), including convolutional encoding / decoding and block encoding / decoding
• Half rate convolutional encoder and decoder with constraint lengths from 2 to 7 and optional puncturing
• Optional symbol interleaving, typically used in combination with FEC
• Symbol coding, such as Manchester or DSSS, or biphase space encoding using FEC hardware
• UART encoding over air, with start and stop bit insertion / removal
• Test mode support, such as modulated or unmodulated carrier output
• Received frame timestamping
3.2.8 Packet and State Trace
The EFR32FG1 Frame Controller has a packet and state trace unit that provides valuable information during the development phase. It
features:
• Non-intrusive trace of transmit data, receive data and state information
• Data observability on a single-pin UART data output, or on a two-pin SPI data output
• Configurable data output bitrate / baudrate
• Multiplexed transmitted data, received data and state / meta information in a single serial data stream
3.2.9 Data Buffering
The EFR32FG1 features an advanced Radio Buffer Controller (BUFC) capable of handling up to 4 buffers of adjustable size from 64
bytes to 4096 bytes. Each buffer can be used for RX, TX or both. The buffer data is located in RAM, enabling zero-copy operations.
3.2.10 Radio Controller (RAC)
The Radio Controller controls the top level state of the radio subsystem in the EFR32FG1. It performs the following tasks:
• Precisely-timed control of enabling and disabling of the receiver and transmitter circuitry
• Run-time calibration of receiver, transmitter and frequency synthesizer
• Detailed frame transmission timing, including optional LBT or CSMA-CA
3.2.11 Random Number Generator
The Frame Controller (FRC) implements a random number generator that uses entropy gathered from noise in the RF receive chain.
The data is suitable for use in cryptographic applications.
Output from the random number generator can be used either directly or as a seed or entropy source for software-based random num-
ber generator algorithms such as Fortuna.
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Preliminary Rev. 0.9 | 5
EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
System Overview
3.3 Power
The EFR32FG1 has an Energy Management Unit (EMU) and efficient integrated regulators to generate internal supply voltages. Only a
single external supply voltage is required, from which all internal voltages are created. An optional integrated DC-DC buck regulator can
be utilized to further reduce the current consumption. The DC-DC regulator requires one external inductor and one external capacitor.
AVDD and VREGVDD need to be 1.85 V or higher for the MCU to operate across all conditions; however the rest of the system will
operate down to 1.62 V, including the digital supply and I/O. This means that the device is fully compatible with 1.8 V components.
Running from a sufficiently high supply, the device can use the DC-DC to regulate voltage not only for itself, but also for other PCB
components, supplying up to a total of 200 mA.
3.3.1 Energy Management Unit (EMU)
The Energy Management Unit manages transitions of energy modes in the device. Each energy mode defines which peripherals and
features are available and the amount of current the device consumes. The EMU can also be used to turn off the power to unused RAM
blocks, and it contains control registers for the dc-dc regulator and the Voltage Monitor (VMON). The VMON is used to monitor multiple
supply voltages. It has multiple channels which can be programmed individually by the user to determine if a sensed supply has fallen
below a chosen threshold.
3.3.2 DC-DC Converter
The DC-DC buck converter covers a wide range of load currents and provides up to 90% efficiency in energy modes EM0, EM1, EM2
and EM3, and can supply up to 200 mA to the device and surrounding PCB components. Patented RF noise mitigation allows operation
of the DC-DC converter without degrading sensitivity of radio components. Protection features include programmable current limiting,
short-circuit protection, and dead-time protection. The DC-DC converter may also enter bypass mode when the input voltage is too low
for efficient operation. In bypass mode, the DC-DC input supply is internally connected directly to its output through a low resistance
switch. Bypass mode also supports in-rush current limiting to prevent input supply voltage droops due to excessive output current tran-
sients.
3.4 General Purpose Input/Output (GPIO)
EFR32FG1 has up to 31 General Purpose Input/Output pins. Each GPIO pin can be individually configured as either an output or input.
More advanced configurations including open-drain, open-source, and glitch-filtering can be configured for each individual GPIO pin.
The GPIO pins can be overridden by peripheral connections, like SPI communication. Each peripheral connection can be routed to sev-
eral GPIO pins on the device. The input value of a GPIO pin can be routed through the Peripheral Reflex System to other peripherals.
The GPIO subsystem supports asynchronous external pin interrupts.
3.5 Clocking
3.5.1 Clock Management Unit (CMU)
The Clock Management Unit controls oscillators and clocks in the EFR32FG1. Individual enabling and disabling of clocks to all periph-
eral modules is perfomed by the CMU. The CMU also controls enabling and configuration of the oscillators. A high degree of flexibility
allows software to optimize energy consumption in any specific application by minimizing power dissipation in unused peripherals and
oscillators.
3.5.2 Internal and External Oscillators
The EFR32FG1 supports two crystal oscillators and fully integrates four RC oscillators, listed below.
• A high frequency crystal oscillator (HFXO) with integrated load capacitors, tunable in small steps, provides a precise timing refer-
ence for the MCU. Crystal frequencies in the range from 38 to 40 MHz are supported. An external clock source such as a TCXO can
also be applied to the HFXO input for improved accuracy over temperature.
• A 32.768 kHz crystal oscillator (LFXO) provides an accurate timing reference for low energy modes.
• An integrated high frequency RC oscillator (HFRCO) is available for the MCU system, when crystal accuracy is not required. The
HFRCO employs fast startup at minimal energy consumption combined with a wide frequency range.
• An integrated auxilliary high frequency RC oscillator (AUXHFRCO) is available for timing the general-purpose ADC and the Serial
Wire debug port with a wide frequency range.
• An integrated low frequency 32.768 kHz RC oscillator (LFRCO) can be used as a timing reference in low energy modes, when crys-
tal accuracy is not required.
• An integrated ultra-low frequency 1 kHz RC oscillator (ULFRCO) is available to provide a timing reference at the lowest energy con-
sumption in low energy modes.
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
System Overview
3.6 Counters/Timers and PWM
3.6.1 Timer/Counter (TIMER)
TIMER peripherals keep track of timing, count events, generate PWM outputs and trigger timed actions in other peripherals through the
PRS system. The core of each TIMER is a 16-bit counter with up to 4 compare/capture channels. Each channel is configurable in one
of three modes. In capture mode, the counter state is stored in a buffer at a selected input event. In compare mode, the channel output
reflects the comparison of the counter to a programmed threshold value. In PWM mode, the TIMER supports generation of pulse-width
modulation (PWM) outputs of arbitrary waveforms defined by the sequence of values written to the compare registers, with optional
dead-time insertion available in timer unit TIMER_0 only.
3.6.2 Real Time Counter and Calendar (RTCC)
The Real Time Counter and Calendar (RTCC) is a 32-bit counter providing timekeeping in all energy modes. The RTCC includes a
Binary Coded Decimal (BCD) calendar mode for easy time and date keeping. The RTCC can be clocked by any of the on-board oscilla-
tors with the exception of the AUXHFRCO, and it is capable of providing system wake-up at user defined instances. When receiving
frames, the RTCC value can be used for timestamping. The RTCC includes 128 bytes of general purpose data retention, allowing easy
and convenient data storage in all energy modes.
3.6.3 Low Energy Timer (LETIMER)
The unique LETIMER is a 16-bit timer that is available in energy mode EM2 Deep Sleep in addition to EM1 Sleep and EM0 Active. This
allows it to be used for timing and output generation when most of the device is powered down, allowing simple tasks to be performed
while the power consumption of the system is kept at an absolute minimum. The LETIMER can be used to output a variety of wave-
forms with minimal software intervention. The LETIMER is connected to the Real Time Counter and Calendar (RTCC), and can be con-
figured to start counting on compare matches from the RTCC.
3.6.4 Ultra Low Power Wake-up Timer (CRYOTIMER)
The CRYOTIMER is a 32-bit counter that is capable of running in all energy modes. It can be clocked by either the 32.768 kHz crystal
oscillator (LFXO), the 32.768 kHz RC oscillator (LFRCO), or the 1 kHz RC oscillator (ULFRCO). It can provide periodic Wakeup events
and PRS signals which can be used to wake up peripherals from any energy mode. The CRYOTIMER provides a wide range of inter-
rupt periods, facilitating flexible ultra-low energy operation.
3.6.5 Pulse Counter (PCNT)
The Pulse Counter (PCNT) peripheral can be used for counting pulses on a single input or to decode quadrature encoded inputs. The
clock for PCNT is selectable from either an external source on pin PCTNn_S0IN or from an internal timing reference, selectable from
among any of the internal oscillators, except the AUXHFRCO. The module may operate in energy mode EM0 Active, EM1 Sleep, EM2
Deep Sleep, and EM3 Stop.
3.6.6 Watchdog Timer (WDOG)
The watchdog timer can act both as an independent watchdog or as a watchdog synchronous with the CPU clock. It has windowed
monitoring capabilities, and can generate a reset or different interrupts depending on the failure mode of the system. The watchdog can
also monitor autonomous systems driven by PRS.
3.7 Communications and Other Digital Peripherals
3.7.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
The Universal Synchronous/Asynchronous Receiver/Transmitter is a flexible serial I/O module. It supports full duplex asynchronous
UART communication with hardware flow control as well as RS-485, SPI, MicroWire and 3-wire. It can also interface with devices sup-
porting:
• ISO7816 SmartCards
• IrDA
I2S
•
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Preliminary Rev. 0.9 | 7
EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
System Overview
3.7.2 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART)
The unique LEUARTTM provides two-way UART communication on a strict power budget. Only a 32.768 kHz clock is needed to allow
UART communication up to 9600 baud. The LEUART includes all necessary hardware to make asynchronous serial communication
possible with a minimum of software intervention and energy consumption.
3.7.3 Inter-Integrated Circuit Interface (I2C)
The I2C module provides an interface between the MCU and a serial I2C bus. It is capable of acting as both a master and a slave and
supports multi-master buses. Standard-mode, fast-mode and fast-mode plus speeds are supported, allowing transmission rates from 10
kbit/s up to 1 Mbit/s. Slave arbitration and timeouts are also available, allowing implementation of an SMBus-compliant system. The
interface provided to software by the I2C module allows precise timing control of the transmission process and highly automated trans-
fers. Automatic recognition of slave addresses is provided in active and low energy modes.
3.7.4 Peripheral Reflex System (PRS)
The Peripheral Reflex System provides a communication network between different peripheral modules without software involvement.
Peripheral modules producing Reflex signals are called producers. The PRS routes Reflex signals from producers to consumer periph-
erals which in turn perform actions in response. Edge triggers and other functionality can be applied by the PRS. The PRS allows pe-
ripheral to act autonomously without waking the MCU core, saving power.
3.8 Security Features
3.8.1 GPCRC (General Purpose Cyclic Redundancy Check)
The GPCRC module implements a Cyclic Redundancy Check (CRC) function. It supports both 32-bit and 16-bit polynomials. The sup-
ported 32-bit polynomial is 0x04C11DB7 (IEEE 802.3), while the 16-bit polynomial can be programmed to any value, depending on the
needs of the application.
3.8.2 Crypto Accelerator (CRYPTO)
The Crypto Accelerator is a fast and energy-efficient autonomous hardware encryption and decryption accelerator. EFR32 devices sup-
port various levels of hardware-accelerated encryption, depending on the part number. The Ordering Information Table specifies wheth-
er this part has full or AES-only crypto support. AES-only devices support AES encryption and decryption with 128- or 256-bit keys.
Full crypto support adds ECC over both GF(P) and GF(2m), SHA-1 and SHA-2 (SHA-224 and SHA-256).
Supported modes of operation for AES include: ECB, CTR, CBC, PCBC, CFB, OFB, CBC-MAC, GMAC and CCM.
Supported ECC NIST recommended curves include P-192, P-224, P-256, K-163, K-233, B-163 and B-233.
The CRYPTO is tightly linked to the Radio Buffer Controller (BUFC) enabling fast and efficient autonomous cipher operations on data
buffer content. It allows fast processing of GCM (AES), ECC and SHA with little CPU intervention. CRYPTO also provides trigger sig-
nals for DMA read and write operations.
3.9 Analog
3.9.1 Analog Port (APORT)
The Analog Port (APORT) is an analog interconnect matrix allowing access to analog modules ADC, ACMP, and IDAC on a flexible
selection of pins. Each APORT bus consists of analog switches connected to a common wire. Since many clients can operate differen-
tially, buses are grouped by X/Y pairs.
3.9.2 Analog Comparator (ACMP)
The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is high-
er. Inputs are selected from among internal references and external pins. The tradeoff between response time and current consumption
is configurable by software. Two 6-bit reference dividers allow for a wide range of internally-programmable reference sources. The
ACMP can also be used to monitor the supply voltage. An interrupt can be generated when the supply falls below or rises above the
programmable threshold.
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3.9.3 Analog to Digital Converter (ADC)
The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits at up to 1 MSamples/s. The
output sample resolution is configurable and additional resolution is possible using integrated hardware for averaging over multiple
samples. The ADC includes integrated voltage references and an integrated temperature sensor. Inputs are selectable from a wide
range of sources, including pins configurable as either single-ended or differential.
3.9.4 Digital to Analog Current Converter (IDAC)
The Digital to Analog Current Converter can source or sink a configurable constant current. This current can be driven on an output pin
or routed to the selected ADC input pin for capacitive sensing. The current is programmable between 0.05 µA and 64 µA with several
ranges with various step sizes.
3.10 Reset Management Unit (RMU)
The RMU is responsible for handling reset of the EFR32FG1. A wide range of reset sources are available, including several power
supply monitors, pin reset, software controlled reset, core lockup reset and watchdog reset.
3.11 Core and Memory
3.11.1 Processor Core
The ARM Cortex-M processor includes a 32-bit RISC processor integrating the following features and tasks in the system:
• ARM Cortex-M4 RISC processor achieving 1.25 Dhrystone MIPS/MHz
• Memory Protection Unit (MPU) supporting up to 8 memory segments
• Up to 256 KB flash program memory
• Up to 32 KB RAM data memory
• Configuration and event handling of all modules
• 2-pin Serial-Wire debug interface
3.11.2 Memory System Controller (MSC)
The Memory System Controller (MSC) is the program memory unit of the microcontroller. The flash memory is readable and writable
from both the Cortex-M and DMA. The flash memory is divided into two blocks; the main block and the information block. Program code
is normally written to the main block, whereas the information block is available for special user data and flash lock bits. There is also a
read-only page in the information block containing system and device calibration data. Read and write operations are supported in en-
ergy modes EM0 Active and EM1 Sleep.
3.11.3 Linked Direct Memory Access Controller (LDMA)
The Linked Direct Memory Access (LDMA) controller features 8 channels capable of performing memory operations independently of
software. This reduces both energy consumption and software workload. The LDMA allows operations to be linked together and stag-
ed, enabling sophisticated operations to be implemented.
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3.12 Memory Map
The EFR32FG1 memory map is shown in the figures below. RAM and flash sizes are for the largest memory configuration.
Figure 3.2. EFR32FG1 Memory Map — Core Peripherals and Code Space
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Figure 3.3. EFR32FG1 Memory Map — Peripherals
3.13 Configuration Summary
The features of the EFR32FG1 are a subset of the feature set described in the device reference manual. The table below describes
device specific implementation of the features. Remaining modules support full configuration.
Table 3.1. Configuration Summary
Module
USART0
USART1
Configuration
Pin Connections
IrDA SmartCard
US0_TX, US0_RX, US0_CLK, US0_CS
US1_TX, US1_RX, US1_CLK, US1_CS
IrDA I2S SmartCard
with DTI.
TIMER0
TIMER1
TIM0_CC[2:0], TIM0_CDTI[2:0]
TIM1_CC[3:0]
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Electrical Specifications
4. Electrical Specifications
4.1 Electrical Characteristics
All electrical parameters in all tables are specified under the following conditions, unless stated otherwise:
• Typical values are based on TAMB=25 °C and VDD= 3.3 V, by production test and/or technology characterization.
• Radio performance numbers are measured in conducted mode, based on Silicon Laboratories reference designs using output pow-
er-specific external RF impedance-matching networks for interfacing to a 50 Ω antenna.
• Minimum and maximum values represent the worst conditions across supply voltage, process variation, and an operating tempera-
ture of -40 to +85 °C, unless stated otherwise.
Refer to Table 4.2 General Operating Conditions on page 14 for more details about operational supply and temperature limits.
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4.1.1 Absolute Maximum Ratings
Stresses above those listed below may cause permanent damage to the device. This is a stress rating only and functional operation of
the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure
to maximum rating conditions for extended periods may affect device reliability. For more information on the available quality and relia-
bility data, see the Quality and Reliability Monitor Report at http://www.silabs.com/support/quality/pages/default.aspx.
Table 4.1. Absolute Maximum Ratings
Parameter
Symbol
Test Condition
Min
-50
0
Typ
—
Max
150
3.8
1
Unit
°C
Storage temperature range
TSTG
External main supply voltage VDDMAX
—
V
External main supply voltage VDDRAMPMAX
ramp rate
—
—
V / μs
Voltage on any 5V tolerant
GPIO pin1
VDIGPIN
-0.3
-0.3
—
—
Min of 5.25
and IOVDD
+2
V
V
Voltage on non-5V tolerant
GPIO pins
IOVDD+0.3
Voltage on HFXO pins
VHFXOPIN
-0.3
—
—
—
1.4
10
V
Input RF level on pins
2G4RF_IOP and
2G4RF_ION
PRFMAX2G4
dBm
Voltage differential between VMAX2G4
RF pins (2G4RF_IOP -
2G4RF_ION)
-50
-0.3
—
—
—
—
50
3.3
200
mV
V
Absolute Voltage on RF pins VMAXDIFF2G4
2G4RF_IOP and
2G4RF_ION
Total current into VSS ground IVSSMAX
lines (sink)
mA
Current per I/O pin (sink)
IIOMAX
—
—
—
—
—
—
—
—
50
50
mA
mA
mA
mA
Current per I/O pin (source)
Current for all I/O pins (sink) IIOALLMAX
200
200
Current for all I/O pins
(source)
Voltage difference between
AVDD and VREGVDD
ΔVDD
—
—
0.3
V
Note:
1. When a GPIO pin is routed to the analog module through the APORT, the maximum voltage = IOVDD.
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Electrical Specifications
4.1.2 Operating Conditions
When assigning supply sources, the following requirements must be observed:
• VREGVDD must be the highest voltage in the system
• VREGVDD = AVDD
• DVDD ≤ AVDD
• IOVDD ≤ AVDD
• RFVDD ≤ AVDD
• PAVDD ≤ AVDD
4.1.2.1 General Operating Conditions
Table 4.2. General Operating Conditions
Parameter
Symbol
Test Condition
Min
-40
Typ
25
Max
85
Unit
°C
Operating temperature range TOP
-G temperature grade
AVDD Supply voltage1
VAVDD
1.85
3.3
3.8
V
VREGVDD Operating supply VVREGVDD
voltage12
DCDC in regulation
2.4
3.3
3.3
3.3
3.8
3.8
3.8
V
V
V
DCDC in bypass 50mA load
TBD
1.85
DCDC not in use. DVDD external-
ly shorted to VREGVDD
RFVDD Operating supply
voltage
VRFVDD
1.62
1.62
1.62
1.62
—
—
—
—
—
—
VVREGVDD
VVREGVDD
VVREGVDD
VVREGVDD
0.1
V
V
V
V
V
DVDD Operating supply volt- VDVDD
age
PAVDD Operating supply
voltage
VPAVDD
VIOVDD
dVDD
IOVDD Operating supply
voltage
Difference between AVDD
and VREGVDD, ABS(AVDD-
VREGVDD)
0 wait-states (MODE = WS0) 3
1 wait-states (MODE = WS1) 3
HFCLK frequency
fCORE
—
—
—
26
40
MHz
MHz
38.4
Note:
1. VREGVDD must be tied to AVDD. Both VREGVDD and AVDD minimum voltages must be satisfied for the part to operate.
2. The minimum voltage required in bypass mode is calculated using RBYP from the DCDC specification table. Requirements for
other loads can be calculated as VDVDD_min+ILOAD * RBYP_max
3. in MSC_READCTRL register
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4.1.3 Thermal Characteristics
Table 4.3. Thermal Characteristics
Parameter
Symbol
THETAJA
Test Condition
Min
Typ
Max
Unit
Thermal Resistance
QFN32 Package, 2-Layer PCB,
Air velocity = 0 m/s
—
79
—
°C/W
QFN32 Package, 2-Layer PCB,
Air velocity = 1 m/s
—
—
—
—
—
—
—
—
—
—
—
62.2
54.1
32
—
—
—
—
—
—
—
—
—
—
—
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
QFN32 Package, 2-Layer PCB,
Air velocity = 2 m/s
QFN32 Package, 4-Layer PCB,
Air velocity = 0 m/s
QFN32 Package, 4-Layer PCB,
Air velocity = 1 m/s
28.1
26.9
64.5
51.6
47.7
26.2
23.1
22.1
QFN32 Package, 4-Layer PCB,
Air velocity = 2 m/s
QFN48 Package, 2-Layer PCB,
Air velocity = 0 m/s
QFN48 Package, 2-Layer PCB,
Air velocity = 1 m/s
QFN48 Package, 2-Layer PCB,
Air velocity = 2 m/s
QFN48 Package, 4-Layer PCB,
Air velocity = 0 m/s
QFN48 Package, 4-Layer PCB,
Air velocity = 1 m/s
QFN48 Package, 4-Layer PCB,
Air velocity = 2 m/s
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Electrical Specifications
4.1.4 DC-DC Converter
Test conditions: LDCDC=4.7 µH, CDCDC=1.0 µF (Murata GRM188R71A105KA61D), VDCDC_I=3.3 V, VDCDC_O=1.8 V, IDCDC_LOAD=50
mA, Heavy Drive configuration, FDCDC_LN=8 MHz, unless otherwise indicated.
Table 4.4. DC-DC Converter
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Input voltage range
VDCDC_I
Bypass mode, Strong Bypass with
PMOS enabled, assumes inductor
DCR of 140 mOhms, IDCDC_LOAD
= 50 mA
TBD
—
3.8
V
Low noise (LN) mode, 1.8 V out-
put, IDCDC_LOAD = 100 mA, or
Low power (LP) mode, 1.8 V out-
put, IDCDC_LOAD = 10 mA
2.4
—
3.8
V
Low noise (LN) mode, 1.8 V out-
put, IDCDC_LOAD = 200 mA
TBD
TBD
TBD
TBD
—
1.8
—
3.8
—
V
V
Output voltage programma- VDCDC_O
ble range
1.8V configuration
Regulation DC Accuracy
ACCDC
Low noise (LN) mode, 1.8 V target
output
TBD
TBD
mV
mV
Low power (LP) mode,
—
LPCMPBIAS1 = 0, 1.8 V target
output, IDCDC_LOAD = 200 μA
Low power (LP) mode,
TBD
—
TBD
mV
LPCMPBIAS1 = 3, 1.8 V target
output, IDCDC_LOAD = 10 mA
Steady-state output ripple
VR
Radio disabled.
—
—
3
—
mVpp
mV
CCM Mode (LNFORCECCM1 =
1), Load changes between 0 mA
and 100 mA
Output voltage under/over-
shoot
VOV
—
150
DCM Mode (LNFORCECCM1 =
0), Load changes between 0 mA
and 10 mA
—
—
150
mV
DC line regulation
DC load regulation
Max load current
VREG
Input changes between 3.8 V and
2.4 V
—
—
0.1
0.1
—
—
%
%
IREG
Load changes between 0 mA and
100 mA in CCM mode
Low noise (LN) Heavy Drive2
ILOAD_MAX
—
—
—
—
200
100
mA
mA
Low noise (LN) mode, Medium
Drive2
Low noise (LN) mode, Light
Drive2
—
—
—
—
50
10
mA
mA
Low power (LP) mode,
LPCMPBIAS1 = 3
DCDC output capacitor
DCDC output inductor
CDCDC
LDCDC
25% tolerance
20% tolerance
TBD
—
1
TBD
—
μF
μH
4.7
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Parameter
Symbol
Test Condition
BYPPFETEN = 0
BYPPFETEN = 1
Min
TBD
TBD
Typ
1.2
0.8
Max
TBD
TBD
Unit
Ω
Resistance in Bypass mode RBYP
Ω
Note:
1. In EMU_DCDCMISCCTRL register
2. Drive levels are defined by configuration of the PFETCNT and NFETCNT registers. Light Drive: PFETCNT=NFETCNT=3; Medi-
um Drive: PFETCNT=NFETCNT=7; Heavy Drive: PFETCNT=NFETCNT=15.
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4.1.5 Current Consumption
4.1.5.1 Current Consumption 1.85 V without DC-DC Converter
Unless otherwise indicated VREGVDD = AVDD = DVDD = RFVDD = PAVDD= 1.85 V. EMU_PWRCFG_PWRCG=NODCDC.
EMU_DCDCCTRL_DCDCMODE=BYPASS. See Figure 5.1 EFR32FG1 Typical Application Circuit: Direct Supply Configuration without
DC-DC converter on page 48.
Table 4.5. Current Consumption 1.85V without DC/DC
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Current consumption in EM0 IACTIVE
Active mode with radio disa-
38.4 MHz crystal, CPU running
while loop from flash
—
128
—
μA/MHz
bled, All peripherals disabled
38 MHz HFRCO, CPU running
Prime from flash
—
—
—
—
—
87
—
—
—
—
—
μA/MHz
μA/MHz
μA/MHz
μA/MHz
μA/MHz
38 MHz HFRCO, CPU running
while loop from flash
103
112
105
235
38 MHz HFRCO, CPU running
CoreMark from flash
26 MHz HFRCO, CPU running
while loop from flash
1 MHz HFRCO, CPU running
while loop from flash
Current consumption in EM1 IEM1
Sleep mode with radio disa-
bled. All peripherals disabled
38.4 MHz crystal
38 MHz HFRCO
26 MHz HFRCO
1 MHz HFRCO
—
—
—
—
—
61
35
—
—
—
—
—
μA/MHz
μA/MHz
μA/MHz
μA/MHz
μA
37
167
3.36
Current consumption in EM2 IEM2
Deep Sleep mode.
Full RAM retention and RTCC
running from LFXO
4 kB RAM retention and RTCC
running from LFRCO
—
—
—
—
3.13
2.84
1.08
0.64
—
—
—
—
μA
μA
μA
μA
Current consumption in EM3 IEM3
Stop mode
Full RAM retention and CRYO-
TIMER running from ULFRCO
Current consumption in
EM4H Hibernate mode
IEM4
128 byte RAM retention, RTCC
running from LFXO
128 byte RAM retention, CRYO-
TIMER running from ULFRCO
128 byte RAM retention, no RTCC
No RAM retention, no RTCC
—
—
0.63
0.02
—
—
μA
μA
Current consumption in
EM4S Shutoff mode
IEM4S
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4.1.5.2 Current Consumption 3.3 V without DC-DC Converter
Unless otherwise indicated VREGVDD = AVDD = DVDD = RFVDD = PAVDD= 3.3 V. EMU_PWRCFG_PWRCG=NODCDC.
EMU_DCDCCTRL_DCDCMODE=BYPASS. See Figure 5.3 EFR32FG1 Typical Application Circuit: Configuration with DC-DC Coverter
(PAVDD from VDD) on page 49.
Table 4.6. Current Consumption 3.3V without DC/DC
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Current consumption in EM0 IACTIVE
Active mode with radio disa-
38.4 MHz crystal, CPU running
while loop from flash
—
129
—
μA/MHz
bled, All peripherals disabled
38 MHz HFRCO, CPU running
Prime from flash
—
—
—
—
—
87
—
—
—
—
—
μA/MHz
μA/MHz
μA/MHz
μA/MHz
μA/MHz
38 MHz HFRCO, CPU running
while loop from flash
103
112
105
237
38 MHz HFRCO, CPU running
CoreMark from flash
26 MHz HFRCO, CPU running
while loop from flash
1 MHz HFRCO, CPU running
while loop from flash
Current consumption in EM1 IEM1
Sleep mode with radio disa-
bled. All peripherals disabled
38.4 MHz crystal
38 MHz HFRCO
26 MHz HFRCO
1 MHz HFRCO
—
—
—
—
—
61
35
—
—
—
—
—
μA/MHz
μA/MHz
μA/MHz
μA/MHz
μA
37
170
3.47
Current consumption in EM2 IEM2
Deep Sleep mode.
Full RAM retention and RTCC
running from LFXO
4 kB RAM retention and RTCC
running from LFRCO
—
—
—
—
3.35
2.92
1.13
0.67
—
—
—
—
μA
μA
μA
μA
Current consumption in EM3 IEM3
Stop mode
Full RAM retention and CRYO-
TIMER running from ULFRCO
Current consumption in
EM4H Hibernate mode
IEM4
128 byte RAM retention, RTCC
running from LFXO
128 byte RAM retention, CRYO-
TIMER running from ULFRCO
128 byte RAM retention, no RTCC
no RAM retention, no RTCC
—
—
0.66
0.04
—
—
μA
μA
Current consumption in
EM4S Shutoff mode
IEM4S
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4.1.5.3 Current Consumption 3.3 V using DC-DC Converter
Unless otherwise indicated VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD= 1.8 V DC-DC output. See Figure 5.2
EFR32FG1 Typical Application Circuit: Configuration with DC-DC Coverter (PAVDD from VDCDC) on page 48.
Table 4.7. Current Consumption 3.3V with DC/DC
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Current consumption in EM0 IACTIVE
Active mode with radio disa-
bled. All peripherals disa-
bled, DCDC in LowNoise
mode
38.4 MHz crystal, CPU running
while loop from flash.
—
87
—
μA/MHz
38 MHz HFRCO, CPU running
Prime from flash
—
—
—
—
63
72
78
79
—
—
—
—
μA/MHz
μA/MHz
μA/MHz
μA/MHz
38 MHz HFRCO, CPU running
while loop from flash
38 MHz HFRCO, CPU running
CoreMark from flash
26 MHz HFRCO, CPU running
while loop from flash
Current consumption in EM1 IEM1
Sleep mode with radio disa-
bled. All peripherals disa-
bled, DCDC in LowPower
mode.
38.4 MHz crystal
38 MHz HFRCO
26 MHz HFRCO
1 MHz HFRCO
—
—
—
—
—
39
23
—
—
—
—
—
μA/MHz
μA/MHz
μA/MHz
μA/MHz
μA
25
142
1.4
Current consumption in EM2 IEM2
Deep Sleep mode.
Full RAM retention and RTCC
running from LFXO
4 kB RAM retention and RTCC
running from LFRCO
—
—
—
—
1.4
1.1
0.9
0.6
—
—
—
—
μA
μA
μA
μA
Current consumption in EM3 IEM3
Stop mode
Full RAM retention and CRYO-
TIMER running from ULFRCO
Current consumption in
EM4H Hibernate mode
IEM4
128 byte RAM retention, RTCC
running from LFXO
128 byte RAM retention, CRYO-
TIMER running from ULFRCO
128 byte RAM retention, no RTCC
no RAM retention, no RTCC
—
—
0.6
—
—
μA
μA
Current consumption in
EM4S Shutoff mode
IEM4S
0.03
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Electrical Specifications
4.1.5.4 Current Consumption Using Radio
Unless otherwise indicated VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD. See Figure 5.2 EFR32FG1 Typical
Application Circuit: Configuration with DC-DC Coverter (PAVDD from VDCDC) on page 48 or Figure 5.3 EFR32FG1 Typical Applica-
tion Circuit: Configuration with DC-DC Coverter (PAVDD from VDD) on page 49.
Table 4.8. Current Consumption Using Radio 3.3 V with DC-DC
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Current consumption in re-
ceive mode, active packet
reception (MCU in EM1 @
38.4 MHz, peripheral clocks
disabled)
IRX
1 Mbit/s, 2GFSK, F = 2.4 GHz,
Radio clock prescaled by 4
—
8.7
—
mA
Current consumption in
transmit mode (MCU in EM1
@ 38.4 MHz, peripheral
clocks disabled)
ITX
CW, 0 dBm, F = 2.4 GHz, Radio
clock prescaled by 3
—
8.8
—
mA
CW, 3 dBm, F = 2.4 GHz
CW, 8 dBm, F = 2.4 GHz
CW, 10.5 dBm, F = 2.4 GHz
—
—
—
—
17.6
26.1
34.1
88
—
—
—
—
mA
mA
mA
mA
CW, 16.5 dBm, F = 2.4 GHz,
PAVDD connected directly to ex-
ternal 3.3V supply
CW, 19.5 dBm, F = 2.4 GHz,
PAVDD connected directly to ex-
ternal 3.3V supply
—
—
133
51
—
—
mA
nA
RFSENSE current consump- IRFSENSE
tion
4.1.6 Wake up times
Table 4.9. Wake up times
Parameter
Symbol
Test Condition
Min
—
Typ
10.7
3
Max
—
Unit
μs
Wake up from EM2 Deep
Sleep
tEM2_WU
Code execution from flash
Code execution from RAM
Executing from flash
—
—
μs
Wakeup time from EM1
Sleep
tEM1_WU
—
3
—
AHB
Clocks
Executing from RAM
—
3
—
AHB
Clocks
Wake up from EM3 Stop
tEM3_WU
Executing from flash
Executing from RAM
Executing from flash
—
—
—
10.7
3
—
—
—
μs
μs
μs
Wake up from EM4H Hiber- tEM4H_WU
nate 1
60
Wake up from EM4S Shut-
off1
tEM4S_WU
—
290
—
μs
Note:
1. Time from wakeup request until first instruction is executed. Wakeup results in device reset.
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
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4.1.7 Brown Out Detector
Table 4.10. Brown Out Detector
Parameter
Symbol
Test Condition
DVDD rising
Min
—
Typ
—
Max
TBD
—
Unit
V
DVDDBOD threshold
VDVDDBOD
DVDD falling
TBD
—
—
V
DVDD BOD hysteresis
DVDD response time
AVDD BOD threshold
VDVDDBOD_HYST
24
2.4
—
—
mV
μs
V
tDVDDBOD_DELAY Supply drops at 0.1V/μs rate
—
—
VAVDDBOD
AVDD rising
AVDD falling
—
1.85
—
TBD
—
—
V
AVDD BOD hysteresis
AVDD response time
EM4 BOD threshold
VAVDDBOD_HYST
21
2.4
—
—
mV
μs
V
tAVDDBOD_DELAY Supply drops at 0.1V/μs rate
—
—
VEM4DBOD
AVDD rising
AVDD falling
—
TBD
—
TBD
—
—
V
EM4 BOD hysteresis
EM4 response time
VEM4BOD_HYST
46
300
—
mV
μs
tEM4BOD_DELAY Supply drops at 0.1V/μs rate
—
—
4.1.8 Frequency Synthesizer Characteristics
Table 4.11. Frequency Synthesizer Characteristics
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
RF Synthesizer Frequency
range
FRANGE_2400
2.4 GHz frequency range
2400
—
2483.5
MHz
LO tuning frequency resolu- FRES_2400
tion with 38.4 MHz crystal
2400 - 2483.5 MHz
—
—
—
—
73
Hz
Maximum frequency devia-
tion with 38.4 MHz crystal
ΔFMAX_2400
1677
kHz
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
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4.1.9 2.4 GHz RF Transceiver Characteristics
4.1.9.1 RF Transmitter General Characteristics for the 2.4 GHz Band
Unless otherwise indicated T=25C,VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD. RFVDD and PAVDD path is
filtered using ferrites. Crystal frequency=38.4MHz. RF center frequency 2.45 GHz. Test circuit according to Figure 5.2 EFR32FG1
Typical Application Circuit: Configuration with DC-DC Coverter (PAVDD from VDCDC) on page 48 and Figure 5.4 Typical 2.4 GHz RF
impedance-matching network circuits on page 49.
Table 4.12. RF Transmitter General Characteristics for 2.4 GHz Band
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Maximum TX power1
POUTMAX
19.5 dBm-rated part numbers.
PAVDD connected directly to ex-
ternal 3.3V supply
—
19.5
—
dBm
16.5 dBm-rated part numbers.
PAVDD connected directly to ex-
ternal 3.3V supply
—
16.5
—
dBm
Minimum active TX Power
Output power step size
POUTMIN
CW
-30
1
—
—
—
dBm
dB
POUTSTEP
-5 dBm< Output power < 0 dBm
—
—
0 dBm < output power <
POUTMAX
0.5
dB
Output power variation vs
supply at POUTMAX
POUTVAR_V
1.85 V < VVREGVDD < 3.3 V with-
out DC-DC converter, operation at
higher than 10.5 dBm.
—
4.5
—
dB
1.85 V < VVREGVDD < 3.3 V using
DC-DC converter
—
—
2.1
1.4
1.4
0.5
—
—
—
dB
dB
Output power variation vs
temperature at POUTMAX
POUTVAR_T
From -40 to +85 °C, PAVDD con-
nected to DCDC output
From -40 to +85 °C, PAVDD con-
nected to external supply
—
—
dB
Output power variation vs RF POUTVAR_F
frequency at POUTMAX
Over RF tuning frequency range
—
—
dB
RF tuning frequency range
FRANGE
2400
2483.5
MHz
Note:
1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices cov-
ered in this datasheet can be found in the Max TX Power column of 2. Ordering Information
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
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4.1.9.2 RF Receiver General Characteristics for the 2.4 GHz Band
Unless otherwise indicated T=25C,VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD. RFVDD and PAVDD path is
filtered using ferrites. Crystal frequency=38.4MHz. RF center frequency 2.440 GHz. Test circuit according to Figure 5.2 EFR32FG1
Typical Application Circuit: Configuration with DC-DC Coverter (PAVDD from VDCDC) on page 48 and Figure 5.4 Typical 2.4 GHz RF
impedance-matching network circuits on page 49.
Table 4.13. RF Receiver General Characteristics for 2.4 GHz Band
Parameter
Symbol
FRANGE
SPURRX
Test Condition
Min
2400
—
Typ
—
Max
2483.5
—
Unit
MHz
dBm
dBm
dBm
RF tuning frequency range
Receive mode maximum
spurious emission
30 MHz to 1 GHz
1 GHz to 12 GHz
CW at 2.45 GHz
-57
-47
-24
—
—
Level above which
RFSENSE will trigger
RFSENSETRIG
RFSENSETHRES
SENS2GFSK
—
—
Level below which
RFSENSE will not trigger
—
-50
—
dBm
1% PER Sensitivity
0.1% BER Sensitivity
2 Mbps 2GFSK signal
250 kbps 2GFSK signal
—
—
-90.5
-99.2
—
—
dBm
dBm
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
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4.1.9.3 RF Transmitter Characteristics for 1Mbps 2GFSK in the 2.4 GHz Band
Unless otherwise indicated T=25C,VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD. RFVDD and PAVDD path is
filtered using ferrites. Crystal frequency=38.4MHz. RF center frequency 2.44 GHz. Test circuit according to Figure 5.2 EFR32FG1
Typical Application Circuit: Configuration with DC-DC Coverter (PAVDD from VDCDC) on page 48 and Figure 5.4 Typical 2.4 GHz RF
impedance-matching network circuits on page 49.
Table 4.14. RF Transmitter Characteristics for 1Mbps 2GFSK in the 2.4GHz Band
Parameter
Symbol
TXBW
Test Condition
Min
—
Typ
740
-6.5
Max
—
Unit
Transmit 6dB bandwidth
Power spectral density limit
kHz
PSDLIMIT
Per FCC part 15.247
—
—
dBm/
3kHz
Per ETSI 300.328 at 10 dBm/1
MHz
—
—
—
10
1.1
—
—
—
dBm
MHz
dBm
Occupied channel bandwidth OCPETSI328
per ETSI EN300.328
99% BW at highest and lowest
channels in band
Emissions of harmonics out- SPURHRM_FCC 2nd,3rd, 5, 6, 8, 9,10 harmonics;
-47.3
of-band, per FCC part
15.247
continuous transmission of modu-
lated carrier
Spurious emissions out-of-
band, per FCC part 15.247,
excluding harmonics cap-
tured in SPURHARM,FCC. Re-
stricted Bands
SPUROOB_FCC
Above 2.483 GHz or below 2.4
GHz; continuous transmission of
—
—
-47
-26
—
—
dBm
dBc
modulated carrier1
Spurious emissions out-of-
band, per FCC part 15.247,
excluding harmonics cap-
Above 2.483 GHz or below 2.4
GHz; continuous transmission of
modulated carrier
tured in SPURHARM,FCC
.
Non Restricted Bands
Spurious emissions out-of-
band; per ETSI 300.328
SPURETSI328
[2400-BW to 2400] MHz, [2483.5
to 2483.5+BW] MHz
—
—
-16
-26
—
—
dBm
dBm
[2400-2BW to 2400-BW] MHz,
[2483.5+BW to 2483.5+2BW]
MHz per ETSI 300.328
Spurious emissions per ETSI SPURETSI440
EN300.440
47-74 MHz,87.5-108 MHz,
174-230 MHz, 470-862 MHz
—
-60
—
dBm
25-1000 MHz
1-12 GHz
—
—
-42
-36
—
—
dBm
dBm
Note:
1. For 2480 Mhz, a maximum duty cycle of 20% is used to achieve this value.
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
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4.1.9.4 RF Receiver Characteristics for 1Mbps 2GFSK in the 2.4 GHz Band
Unless otherwise indicated T=25C,VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD. RFVDD and PAVDD path is
filtered using ferrites. Crystal frequency=38.4MHz. RF center frequency 2.440 GHz. Test circuit according to Figure 5.2 EFR32FG1
Typical Application Circuit: Configuration with DC-DC Coverter (PAVDD from VDCDC) on page 48 and Figure 5.4 Typical 2.4 GHz RF
impedance-matching network circuits on page 49.
Table 4.15. RF Receiver Characteristics for 1Mbps 2GFSK in the 2.4GHz Band
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Signal is reference signal1. Packet
length is 20 bytes.
Max usable receiver input
level, 0.1% BER
SAT
—
10
—
dBm
Signal is reference signal1. Using
DC-DC converter
Sensitivity, 0.1% BER
SENS
—
-94
—
dBm
Signal to co-channel interfer- C/ICC
er, 0.1% BER
Desired signal 3 dB above refer-
ence sensitivity
—
—
8.3
-3
—
—
dB
dB
N+1 adjacent channel (1
MHz) selectivity, 0.1% BER,
with allowable exceptions.
Desired is reference signal at
-67 dBm
C/I1+
Interferer is reference signal at +1
MHz offset. Desired frequency
2402 MHz ≤ Fc ≤ 2480 MHz
N-1 adjacent channel (1
MHz) selectivity, 0.1% BER,
with allowable exceptions.
Desired is reference signal at
-67 dBm
C/I1-
Interferer is reference signal at -1
MHz offset. Desired frequency
2402 MHz ≤ Fc ≤ 2480 MHz
—
-0.5
—
dB
Alternate (2 MHz) selectivity, C/I2
0.1% BER, with allowable
exceptions. Desired is refer-
ence signal at -67 dBm
Interferer is reference signal at ± 2
MHz offset. Desired frequency
2402 MHz ≤ Fc ≤ 2480 MHz
—
—
-43
—
—
dB
dB
Alternate (3 MHz) selectivity, C/I3
0.1% BER, with allowable
exceptions. Desired is refer-
ence signal at -67 dBm
Interferer is reference signal at ±3
MHz offset. Desired frequency
2404 MHz ≤ Fc ≤ 2480 MHz
-46.7
Selectivity to image frequen- C/IIM
cy, 0.1% BER. Desired is ref-
erence signal at -67 dBm
Interferer is reference signal at im-
age frequency with 1 MHz preci-
sion
—
—
-38.7
-48.2
—
—
dB
dB
Selectivity to image frequen- C/IIM+1
cy +1 MHz, 0.1% BER. De-
sired is reference signal at
-67 dBm
Interferer is reference signal at im-
age frequency +1 MHz with 1
MHz precision
Blocking, 0.1% BER, Desired BLOCKOOB
is reference signal at -67
dBm. Interferer is CW in
OOB range.
Interferer frequency 30 MHz ≤ f ≤
2000 MHz
—
—
—
—
-27
-32
-32
-27
—
—
—
—
dBm
dBm
dBm
dBm
Interferer frequency 2003 MHz ≤ f
≤ 2399 MHz
Interferer frequency 2484 MHz ≤ f
≤ 2997 MHz
Interferer frequency 3 GHz ≤ f ≤
12.75 GHz
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Upper limit of input power
range over which RSSI reso-
lution is maintained
RSSIMAX
4
—
—
dBm
Lower limit of input power
range over which RSSI reso-
lution is maintained
RSSIMIN
RSSIRES
—
—
—
—
-101
0.5
dBm
dB
RSSI resolution
Over RSSIMIN to RSSIMAX
Note:
1. Reference signal is defined 2GFSK at -67 dBm, Modulation index = 0.5, BT = 0.5, Bit rate = 1 Mbps, desired data = PRBS9;
interferer data = PRBS15; frequency accuracy better than 1 ppm
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
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4.1.9.5 RF Transmitter Characteristics for 802.15.4 O-QPSK DSSS in the 2.4 GHz Band
Unless otherwise indicated T=25 °C,VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD. RFVDD and PAVDD path is
filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 2.45 GHz. Test circuit according to Figure 5.2 EFR32FG1
Typical Application Circuit: Configuration with DC-DC Coverter (PAVDD from VDCDC) on page 48 and Figure 5.4 Typical 2.4 GHz RF
impedance-matching network circuits on page 49
Table 4.16. RF Transmitter Characteristics for 802.15.4 DSSS-OQPSK in the 2.4GHz Band
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Error vector magnitude (off- EVM
set EVM), per 802.15.4-2011
Average across frequency. Signal
is DSSS-OQPSK reference pack-
et1
—
6.1
—
% rms
Power spectral density limit
PSDLIMIT
Relative, at carrier ±3.5 MHz
—
—
-26
-36
—
—
dBc
Absolute, at carrier ±3.5 MHz2
Per FCC part 15.247
dBm
—
—
-3.8
12
—
—
dBm/
3kHz
Output power level which meets
10dBm/MHz ETSI 300.328 speci-
fication
dBm
Occupied channel bandwidth OCPETSI328
per ETSI EN300.328
99% BW at highest and lowest
channels in band
—
—
2.25
—
—
MHz
dBm
Emissions of harmonics out- SPURHRM_FCC 2nd,3rd, 5, 6,8,9,10 harmonics;
-49.7
of-band, per FCC part
15.247
continuous transmission of modu-
lated carrier
Spurious emissions out-of-
band, per FCC part 15.247,
excluding harmonics. Re-
stricted Bands
SPUROOB_FCC
Above 2.483 GHz or below 2.4
GHz; continuous transmission of
—
—
-47
—
—
dBm
dBc
modulated carrier3
Spurious emissions out-of-
band, per FCC part 15.247,
excluding harmonics, Non
Restricted Bands
Above 2.483 GHz or below 2.4
GHz; continuous transmission of
modulated carrier
-35.4
Spurious emissions out-of-
band; per ETSI 300.3284
SPURETSI328
[2400-BW to 2400], [2483.5 to
2483.5+BW];
—
—
-36.6
-41.7
—
—
dBm
dBm
[2400-2BW to 2400-BW],
[2483.5+BW to 2483.5+2BW]; per
ETSI 300.328
Spurious emissions per ETSI SPURETSI440
EN300.4404
47-74 MHz,87.5-108 MHz,
174-230 MHz, 470-862 MHz
—
-60
—
dBm
25-1000 MHz,
1G-24G
—
—
-42
-36
—
—
dBm
dBm
Note:
1. Reference packet is defined as 20 octet PSDU, modulated according to 802.15.4-2011 DSSS-OQPSK in the 2.4GHz band, with
pseudo-random packet data content
2. For 2415 Mhz, a maximum duty cycle of 50% is used to achieve this value.
3. For 2480 Mhz, a maximum duty cycle of 20% is used to achieve this value.
4. Specified at maximum power output level of 10 dBm
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
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4.1.9.6 RF Receiver Characteristics for 802.15.4 O-QPSK DSSS in the 2.4 GHz Band
Unless otherwise indicated T=25 °C,VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD. RFVDD and PAVDD path is
filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 2.445 GHz. Test circuit according to Figure 5.2 EFR32FG1
Typical Application Circuit: Configuration with DC-DC Coverter (PAVDD from VDCDC) on page 48 and Figure 5.4 Typical 2.4 GHz RF
impedance-matching network circuits on page 49
Table 4.17. RF Receiver Characteristics for 801.15.4 DSSS-OQPSK in the 2.4 GHz Band
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Signal is reference signal1. Packet
length is 20 octets.
Max usable receiver input
level, 1% PER
SAT
—
10
—
dBm
Sensitivity, 1% PER
SENS
Signal is reference signal. Packet
length is 20 octets. Using DC-DC
converter.
—
—
-101
-101
—
—
dBm
dBm
Signal is reference signal. Packet
length is 20 octets. Without DC-
DC converter.
Co-channel interferer rejec- CCR
tion, 1% PER
Desired signal 10 dB above sensi-
tivity limit
—
—
—
-2.6
33.75
52.2
—
—
—
dB
dB
dB
High-side adjacent channel
rejection, 1% PER. Desired
is reference signal at 3dB
above reference sensitivity
ACR+1
Interferer is reference signal at +1
channel-spacing.
Interferer is filtered reference sig-
nal3 at +1 channel-spacing.
level2
Interferer is CW at +1 channel-
spacing.4
—
58.6
—
dB
Low-side adjacent channel
rejection, 1% PER. Desired
is reference signal at 3dB
above reference sensitivity
ACR-1
ACR2
IR
Interferer is reference signal at -1
channel-spacing.
—
—
35
—
—
dB
dB
Interferer is filtered reference sig-
nal3 at -1 channel-spacing.
54.7
level2
Interferer is CW at -1 channel-
spacing.
—
—
—
60.1
45.9
56.8
—
—
—
dB
dB
dB
Alternate channel rejection,
1% PER. Desired is refer-
ence signal at 3dB above
reference sensitivity level2
Interferer is reference signal at ±2
channel-spacing
Interferer is filtered reference sig-
nal3 at ±2 channel-spacing
Interferer is CW at ±2 channel-
spacing
—
—
65.5
49.3
—
—
dB
dB
Interferer is CW in image band4
Image rejection , 1% PER,
Desired is reference signal at
3dB above reference sensi-
tivity level2
Blocking rejection of all other BLOCK
channels. 1% PER, Desired
is reference signal at 3dB
above reference sensitivity
level2. Interferer is reference
signal.
Interferer frequency < Desired fre-
quency - 3 channel-spacing
—
—
57.2
57.9
—
—
dB
dB
Interferer frequency > Desired fre-
quency + 3 channel-spacing
Blocking rejection of 802.11g BLOCK80211G
signal centered at +12MHz
or -13MHz
Desired is reference signal at 6dB
above reference sensitivity level2
—
51.6
—
dB
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Upper limit of input power
range over which RSSI reso-
lution is maintained
RSSIMAX
5
—
—
dBm
Lower limit of input power
range over which RSSI reso-
lution is maintained
RSSIMIN
RSSIRES
—
—
-98
dBm
RSSI resolution
over RSSIMIN to RSSIMAX
—
—
0.25
0.5
—
—
dB
dB
RSSI linearity as defined by RSSILIN
802.15.4-2003
Note:
1. Reference signal is defined as O-QPSK DSSS per 802.15.4, Frequency range = 2400-2483.5 MHz, Symbol rate = 62.5 ksym-
bols/s
2. Reference sensitivity level is -85 dBm
3. Filter is characterized as a symmetric bandpass centered on the adjacent channel having a 3dB bandwidth of 4.6 MHz and stop-
band rejection better than 26 dB beyond 3.15 MHz from the adjacent carrier.
4. Due to low-IF frequency, there is some overlap of adjacent channel and image channel bands. Adjacent channel CW blocker
tests place the Interferer center frequency at the Desired frequency ±5 MHz on the channel raster, whereas the image rejection
test places the CW interferer near the image frequency of the Desired signal carrier, regardless of the channel raster.
4.1.10 Modem Features
Table 4.18. Modem Features
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Receive Bandwidth
RXBandwidth
Configurable range with 38.4 MHz
crystal
0.1
—
2530
kHz
IF Frequency
IFFreq
Configurable range with 38.4 MHz
crystal. Selected steps available.
150
—
1371
kHz
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
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4.1.11 Oscillators
4.1.11.1 LFXO
Table 4.19. LFXO
Parameter
Symbol
Test Condition
Min
—
Typ
32.768
—
Max
—
Unit
kHz
kΩ
Crystal frequency
fLFXO
Supported crystal equivalent ESRLFXO
series resistance (ESR)
—
70
Supported range of crystal
load capacitance 1
CLFXO_CL
6
8
—
—
18
40
pF
pF
On-chip tuning cap range 2
CLFXO_T
On each of LFXTAL_N and
LFXTAL_P pins
On-chip tuning cap step size SSLFXO
—
—
0.25
273
—
—
pF
nA
ESR = 30 kΩ, CL=12.5 pF, GAIN4
= 3, AGC4 = 1
Current consumption after
startup 3
ILFXO
ESR=30 kΩ, CL=12.5 pF, GAIN4
=2
Start- up time
tLFXO
—
308
—
ms
Note:
1. Total load capacitance as seen by the crystal
2. The effective load capacitance seen by the crystal will be CLFXO_T /2. This is because each XTAL pin has a tuning cap and the
two caps will be seen in series by the crystal.
3. Block is supplied by AVDD if ANASW = 0, or DVDD if ANASW=1 in EMU_PWRCTRL register
4. In CMU_LFXOCTRL register
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4.1.11.2 HFXO
Table 4.20. HFXO
Parameter
Symbol
Test Condition
Min
38
Typ
38.4
—
Max
40
Unit
MHz
Ω
Crystal Frequency
fHFXO
Supported crystal equivalent ESRHFXO
series resistance (ESR)
Crystal frequency 38.4 MHz
—
60
Supported range of crystal
load capacitance 1
CHFXO_CL
6
—
12
pF
On-chip tuning cap range 2
CHFXO_T
SSHFXO
tHFXO
On each of HFXTAL_N and
HFXTAL_P pins
9
20
25
—
—
pF
pF
μs
On-chip tuning capacitance
step
—
—
0.04
300
Startup time
38.4 MHz: ESR=50 Ω, CL = 10
pF, BOOST3 = 2
Frequency Tolerance for the FTHFXO
crystal
38.4 MHz, ESR = 50 Ω, CL = 10
pF
-40
—
40
ppm
Note:
1. Total load capacitance as seen by the crystal
2. The effective load capacitance seen by the crystal will be CHFXO_T /2. This is because each XTAL pin has a tuning cap and the
two caps will be seen in series by the crystal.
3. In CMU_HFXOCTRL register
4.1.11.3 LFRCO
Table 4.21. LFRCO
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Oscillation frequency
fLFRCO
ENVREF = 1 in
TBD
32.768
TBD
kHz
CMU_LFRCOCTRL
ENVREF = 0 in
TBD
32.768
TBD
kHz
CMU_LFRCOCTRL
Startup time
tLFRCO
ILFRCO
—
—
500
342
—
—
μs
Current consumption 1
ENVREF = 1 in
CMU_LFRCOCTRL
nA
ENVREF = 0 in
—
494
—
nA
CMU_LFRCOCTRL
Note:
1. Block is supplied by AVDD if ANASW = 0, or DVDD if ANASW=1 in EMU_PWRCTRL register
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Electrical Specifications
4.1.11.4 HFRCO and AUXHFRCO
Table 4.22. HFRCO and AUXHFRCO
Parameter
Symbol
Test Condition
Min
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
—
Typ
38
32
26
19
16
13
7
Max
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
—
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ns
Oscillation frequency
fHFRCO
38 MHz frequency band
32 MHz frequency band
26 MHz frequency band
19 MHz frequency band
16 MHz frequency band
13 MHz frequency band
7 MHz frequency band
4 MHz frequency band
2 MHz frequency band
1 MHz frequency band
fHFRCO ≥ 19 MHz
4 < fHFRCO < 19 MHz
fHFRCO ≤ 4 MHz
4
2
1
Start-up time
tHFRCO
300
1
—
—
μs
—
2.5
43
37
31
25
22
19
12
10
8
—
μs
Current consumption on
DVDD
IHFRCODIG
fHFRCO = 38 MHz
fHFRCO = 32 MHz
fHFRCO = 26 MHz
fHFRCO = 19 MHz
fHFRCO = 16 MHz
fHFRCO = 13 MHz
fHFRCO = 7 MHz
—
—
μA
—
—
μA
—
—
μA
—
TBD
—
μA
—
μA
—
—
μA
—
—
μA
fHFRCO = 4 MHz
—
—
μA
fHFRCO = 2 MHz
—
—
μA
fHFRCO = 1 MHz
—
7
—
μA
Current consumption on
AVDD 1
IHFRCOANA
fHFRCO = 38 MHz
fHFRCO = 32 MHz
fHFRCO = 26 MHz
fHFRCO = 19 MHz
fHFRCO = 16 MHz
fHFRCO = 13 MHz
fHFRCO = 7 MHz
—
161
134
116
101
88
81
69
23
23
23
—
μA
—
—
μA
—
—
μA
—
TBD
—
μA
—
μA
—
—
μA
—
—
μA
fHFRCO = 4 MHz
—
—
μA
fHFRCO = 2 MHz
—
—
μA
fHFRCO = 1 MHz
—
—
μA
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
—
Typ
0.8
0.1
0.2
Max
—
Unit
%
Step size
SSHFRCO
Coarse (% of period)
Fine (% of period)
—
—
%
Period Jitter
PJHFRCO
—
—
% RMS
Note:
1. Current consumption on DVDD instead if ANASW=1 in EMU_PWRCTRL register
4.1.11.5 ULFRCO
Table 4.23. ULFRCO
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Oscillation frequency
fULFRCO
TBD
1
TBD
kHz
4.1.12 Flash Memory Characteristics
Table 4.24. Flash Memory Characteristics1
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Flash erase cycles before
failure
ECFLASH
10000
—
—
cycles
Flash data retention
RETFLASH
tW_PROG
TAMB<85°C
10
20
—
—
years
μs
Word (32-bit) programming
time
26
40
Page erase time
Mass erase time
tPERASE
tMERASE
tDERASE
IERASE
20
20
—
—
—
27
27
60
—
—
40
40
TBD
3
ms
ms
ms
mA
mA
Device erase time2
Page erase current3
Mass or Device erase cur-
rent3
5
Write current3
IWRITE
—
—
3
mA
Note:
1. Flash data retention information is published in the Quarterly Quality and Reliability Report.
2. Device erase is issued over the AAP interface and erases all flash, SRAM, the Lock Bit (LB) page, and the User data page Lock
Word (ULW)
3. Measured at 25°C
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Electrical Specifications
4.1.13 GPIO
Table 4.25. GPIO
Parameter
Symbol
VIOIL
Test Condition
Min
—
Typ
—
Max
IOVDD*0.3
—
Unit
V
Input low voltage
Input high voltage
VIOIH
IOVDD*0.7
IOVDD*0.8
—
V
Output high voltage relative VIOOH
to IOVDD
Sourcing 3 mA, VDD ≥ 3 V,
—
—
V
DRIVESTRENGTH1 = WEAK
Sourcing 1.2 mA, VDD ≥ 1.62 V,
IOVDD*0.6
—
—
—
—
—
—
—
—
V
V
V
V
V
V
V
DRIVESTRENGTH1 = WEAK
Sourcing 20 mA, VDD ≥ 3 V,
IOVDD*0.8
—
DRIVESTRENGTH1 = STRONG
Sourcing 8 mA, VDD ≥ 1.62 V,
IOVDD*0.6
—
DRIVESTRENGTH1 = STRONG
Sinking 3 mA, VDD ≥ 3 V,
Output low voltage relative to VIOOL
IOVDD
—
—
—
—
IOVDD*0.2
IOVDD*0.4
IOVDD*0.2
IOVDD*0.4
DRIVESTRENGTH1 = WEAK
Sinking 1.2 mA, VDD ≥ 1.62 V,
DRIVESTRENGTH1 = WEAK
Sinking 20 mA, VDD ≥ 3 V,
DRIVESTRENGTH1 = STRONG
Sinking 8 mA, VDD ≥ 1.62 V,
DRIVESTRENGTH1 = STRONG
GPIO ≤ IOVDD
Input leakage current
IIOLEAK
—
—
0.1
3.3
TBD
15
nA
μA
Input leakage current on
I5VTOLLEAK
IOVDD < GPIO ≤ IOVDD + 2 V
5VTOL pads above IOVDD
I/O pin pull-up resistor
RPU
TBD
TBD
TBD
43
43
25
TBD
TBD
TBD
kΩ
kΩ
ns
I/O pin pull-down resistor
RPD
Pulse width of pulses re-
moved by the glitch suppres-
sion filter
tIOGLITCH
Output fall time, From 70%
to 30% of VIO
tIOOF
CL = 50 pF,
—
—
1.8
4.5
—
—
ns
ns
DRIVESTRENGTH1 = STRONG,
SLEWRATE1 = 0x6
CL = 50 pF,
DRIVESTRENGTH1 = WEAK,
SLEWRATE1 = 0x6
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Output rise time, From 30% tIOOR
to 70% of VIO
CL = 50 pF,
—
2.2
—
ns
DRIVESTRENGTH1 = STRONG,
SLEWRATE = 0x61
CL = 50 pF,
—
7.4
—
ns
DRIVESTRENGTH1 = WEAK,
SLEWRATE1 = 0x6
Note:
1. In GPIO_Pn_CTRL register
4.1.14 VMON
Table 4.26. VMON
Test Condition
Parameter
Symbol
IVMON
Min
Typ
Max
Unit
VMON Supply Current
In EM0 or EM1, 1 supply moni-
tored
—
5.8
—
μA
In EM0 or EM1, 4 supplies moni-
tored
—
—
—
11.8
62
—
—
—
μA
nA
nA
In EM2, EM3 or EM4, 1 supply
monitored
In EM2, EM3 or EM4, 4 supplies
monitored
99
VMON Loading of Monitored ISENSE
Supply
In EM0 or EM1
—
—
2
2
—
—
μA
nA
V
In EM2, EM3 or EM4
Threshold range
VVMON_RANGE
TBD
—
—
TBD
—
Threshold step size
NVMON_STESP
Coarse
200
20
460
26
mV
mV
ns
Fine
—
—
Response time
Hysteresis
tVMON_RES
Supply drops at 1V/μs rate
—
—
VVMON_HYST
—
—
mV
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Electrical Specifications
4.1.15 ADC
Table 4.27. ADC
Parameter
Symbol
Test Condition
Min
Typ
—
Max
12
Unit
Bits
V
Resolution
VRESOLUTION
VADCIN
6
0
Input voltage range
Single ended
Differential
—
2*VREF
VREF
VAVDD
-VREF
1
—
V
Input range of external refer- VADCREFIN_P
ence voltage, single ended
and differential
—
V
Power supply rejection1
PSRRADC
At DC
At DC
—
—
80
80
—
—
dB
dB
Analog input common mode CMRRADC
rejection ratio
Current on DVDD, using in- IADCDIG_CONTI-
1 Msps / 16 MHz ADCCLK,
BIASPROG3 = 0
—
40
—
μA
ternal reference buffer. Con-
NOUS
tinous operation. WARMUP-
MODE2 = KEEPADCWARM
250 ksps / 4 MHz ADCCLK, BIA-
SPROG3 = 6
—
—
15
9
—
—
μA
μA
62.5 ksps / 1 MHz ADCCLK,
BIASPROG3 = 15
Current on DVDD, using in- IADCDIG_NORMAL 35 ksps / 16 MHz ADCCLK,
ternal reference buffer. Duty-
cycled operation. WARMUP-
—
—
—
—
—
40
5
—
—
—
—
—
μA
μA
μA
μA
μA
BIASPROG3 = 0
MODE2 = NORMAL
5 ksps / 16 MHz ADCCLK
BIASPROG3 = 0
Current on DVDD, using in- IADCDIG_STAND- 125 ksps / 16 MHz ADCCLK,
12
6
ternal reference buffer. Duty-
cycled operation. AWAR-
BY
BIASPROG3 = 0
MUPMODE2 = KEEPIN-
35 ksps / 16 MHz ADCCLK,
STANDBY or KEEPINSLO-
WACC
BIASPROG3 = 0
Current on AVDD4, using in-
ternal reference buffer. Con-
tinous operation. WARMUP-
IADCANA_CONTI- 1 Msps / 16 MHz ADCCLK,
286
NOUS
BIASPROG3 = 0
MODE2 = KEEPADCWARM
250 ksps / 4 MHz ADCCLK, BIA-
SPROG3 = 6
—
—
155
102
—
—
μA
μA
62.5 ksps / 1 MHz ADCCLK,
BIASPROG3 = 15
Current on AVDD4 , using in-
ternal reference buffer. Duty-
cycled operation. WARMUP-
IADCANA_NORMAL 35 ksps / 16 MHz ADCCLK,
—
—
35
5
—
—
μA
μA
BIASPROG3 = 0
MODE2 = NORMAL
5 ksps / 16 MHz ADCCLK,
BIASPROG3 = 0
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Current on AVDD4, using in-
ternal reference buffer. Duty-
cycled operation. WARMUP-
IADCANA_STAND- 125 ksps / 16 MHz ADCCLK,
—
110
—
μA
BY
BIASPROG3 = 0
MODE2 = KEEPINSTANDBY
or KEEPINSLOWACC
35 ksps / 16 MHz ADCCLK,
—
80
—
μA
BIASPROG3 = 0
ADC Clock Frequency
Throughput rate
fADCCLK
—
—
—
—
—
—
—
—
7
16
1
MHz
Msps
cycles
cycles
cycles
μs
fADCRATE
Conversion time5
tADCCONV
6 bit
8 bit
12 bit
—
—
—
5
9
13
—
WARMUPMODE2 = NORMAL
Startup time of reference
generator and ADC core in
NORMAL mode
tADCSTART
WARMUPMODE2 = KEEPIN-
From standby mode
—
—
1
μs
STANDBY or KEEPINSLOWACC
SNDR at 1Msps and fin
10kHz
=
SNDRADC
Internal reference, 2.5 V full-scale,
differential (-1.25, 1.25)
TBD
—
67
68
—
—
—
—
dB
dB
dB
μV
vrefp_in = 1.25 V direct mode with
2.5 V full-scale, differential
Spurious-Free Dynamic
Range (SFDR)
SFDRADC
1 MSamples/s, 10 kHz full-scale
sine wave
—
75
Input referred ADC noise,
rms
VREF_NOISE
Including quantization noise and
distortion
—
380
Offset Error
VADCOFFSETERR
VADC_GAIN
TBD
—
1
-0.2
-1
TBD
TBD
—
LSB
%
Gain error in ADC
Using internal reference
Using external reference
12 bit resolution
—
%
Differential non-linearity
(DNL)
DNLADC
INLADC
-1
—
TBD
LSB
Integral non-linearity (INL),
End point method
12 bit resolution
TBD
—
—
TBD
—
LSB
Temperature Sensor Slope
VTS_SLOPE
-1.84
mV/°C
Note:
1. PSRR is referenced to AVDD when ANASW=0 and to DVDD when ANASW=1 in EMU_PWRCTRL
2. In ADCn_CNTL register
3. In ADCn_BIASPROG register
4. Current consumption on DVDD instead if ANASW=1 in EMU_PWRCTRL register
5. Derived from ADCCLK
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Preliminary Rev. 0.9 | 38
EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Electrical Specifications
4.1.16 IDAC
Table 4.28. IDAC
Parameter
Symbol
Test Condition
Min
—
Typ
4
Max
—
Unit
-
Number of Ranges
Output Current
NIDAC_RANGES
IIDAC_OUT
RANGSEL1 = RANGE0
RANGSEL1 = RANGE1
RANGSEL1 = RANGE2
RANGSEL1 = RANGE3
0.05
—
1.6
μA
1.6
0.5
2
—
—
—
32
4.7
16
64
—
μA
μA
μA
Linear steps within each
range
NIDAC_STEPS
—
RANGSEL1 = RANGE0
RANGSEL1 = RANGE1
RANGSEL1 = RANGE2
RANGSEL1 = RANGE3
Step size
SSIDAC
—
—
50
100
500
2
—
—
nA
nA
nA
μA
%
—
—
—
—
Total Accuracy, STEPSEL1 =
0x10
ACCIDAC
EM0 or EM1, AVDD=3.3 V, T = 25
°C
TBD
—
TBD
EM0 or EM1
EM2 or EM3
TBD
TBD
—
—
—
5
TBD
TBD
—
%
%
Start up time
tIDAC_SU
Output within 1% of steady state
value
μs
Settling time, (output settled tIDAC_SETTLE
within 1% of steady state val-
ue)
Range setting is changed
Step value is changed
—
—
5
1
—
—
μs
μs
Current consumption in EM0 IIDAC
or EM1 2
Source mode, excluding output
current
—
—
—
8.9
12
—
—
—
μA
μA
%
Sink mode, excluding output cur-
rent
Output voltage compliance in ICOMP_SRC
source mode, source current
change relative to current
sourced at 0 V
RANGESEL1=0, output voltage =
min(VIOVDD, VAVDD2-100 mv)
0.16
RANGESEL1=1, output voltage =
min(VIOVDD, VAVDD2-100 mV)
—
—
—
0.08
0.03
0.03
—
—
—
%
%
%
RANGESEL1=2, output voltage =
min(VIOVDD, VAVDD2-150 mV)
RANGESEL1=3, output voltage =
min(VIOVDD, VAVDD2-250 mV)
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Output voltage compliance in ICOMP_SINK
sink mode, sink current
RANGESEL1=0, output voltage =
100 mV
—
0.82
—
%
change relative to current
sunk at IOVDD
RANGESEL1=1, output voltage =
100 mV
—
—
—
0.65
0.4
—
—
—
%
%
%
RANGESEL1=2, output voltage =
150 mV
RANGESEL1=3, output voltage =
250 mV
0.25
Note:
1. In IDAC_CURPROG register
2. The IDAC is supplied by either AVDD, DVDD, or IOVDD based on the setting of ANASW in the EMU_PWRCTRL register and
PWRSEL in the IDAC_CTRL register. Setting PWRSEL to 1 selects IOVDD. With PWRSEL cleared to 0, ANASW selects be-
tween AVDD (0) and DVDD (1).
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Electrical Specifications
4.1.17 Analog Comparator (ACMP)
Table 4.29. ACMP
Parameter
Symbol
VACMPIN
Test Condition
Min
Typ
Max
Unit
Input voltage range
CMPVDD =
ACMPn_CTRL_PWRSEL 1
0
—
CMPVDD
V
BIASPROG2 = 1, FULLBIAS2 = 0
Active current not including
voltage reference
IACMP
—
—
50
—
—
nA
nA
BIASPROG2 = 0x10, FULLBIAS2
= 0
306
BIASPROG2 = 0x20, FULLBIAS2
= 1
—
—
74
50
TBD
—
μA
nA
Current consumption of inter- IACMPREF
nal voltage reference,
VLP selected as input using 2.5 V
Reference / 4 (0.625 V)
VLP selected as input using VDD
—
—
20
—
—
nA
μA
VBDIV selected as input using
1.25 V reference / 1
4.1
VADIV selected as input using
VDD/1
—
2.4
—
μA
HYSTSEL3 = HYST0
HYSTSEL3 = HYST1
HYSTSEL3 = HYST2
HYSTSEL3 = HYST3
HYSTSEL3 = HYST4
HYSTSEL3 = HYST5
HYSTSEL3 = HYST6
HYSTSEL3 = HYST7
Hysteresis
VACMPHYST
—
—
—
—
—
—
—
—
—
0
TBD
—
mV
mV
mV
mV
mV
mV
mV
mV
μs
12
22
30
36
41
47
52
30
—
—
—
—
—
—
BIASPROG2 = 1, FULLBIAS2 = 0
4
Comparator delay
tACMPDELAY
—
BIASPROG2 = 0x10, FULLBIAS2
= 0 4
—
—
—
3.7
35
—
—
—
μs
ns
BIASPROG2 = 0x20, FULLBIAS2
= 1 4
BIASPROG2 =0x20, FULLBIAS2
= 1 4
Offset voltage
VACMPOFFSET
TBD
mV
Reference Voltage
VACMPREF
Internal 1.25 V reference
Internal 2.5 V reference
TBD
TBD
1.25
2.5
TBD
TBD
V
V
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
CSRESSEL5 = 0
CSRESSEL5 = 1
CSRESSEL5 = 2
CSRESSEL5 = 3
CSRESSEL5 = 4
CSRESSEL5 = 5
CSRESSEL5 = 6
CSRESSEL5 = 7
Min
Typ
Max
Unit
Capacitive Sense Internal
Resistance
RCSRES
—
inf
—
kΩ
—
—
—
—
—
—
—
15
27
—
—
—
—
—
—
—
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
39
51
102
164
239
Note:
1. CMPVDD is a supply chosen by the setting in ACMPn_CTRL_PWRSEL and may be IOVDD, AVDD or DVDD
2. In ACMPn_CTRL register
3. In ACMPn_HYSTERESIS register
4. ± 100 mV differential
5. In ACMPn_INPUTSEL register
The total ACMP current is the sum of the contributions from the ACMP and its internal voltage reference as given as:
IACMPTOTAL = IACMP + IACMPREF
IACMPREF is zero if an external voltage reference is used.
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Electrical Specifications
4.1.18 I2C
I2C Standard-mode (Sm)
Table 4.30. I2C Standard-mode (Sm)1
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SCL clock frequency2
SCL clock low time
SCL clock high time
SDA set-up time
fSCL
0
—
100
kHz
tLOW
4.7
4
—
—
—
—
—
—
—
μs
μs
ns
ns
μs
tHIGH
tSU,DAT
tHD,DAT
250
100
4.7
—
SDA hold time3
3450
—
Repeated START condition tSU,STA
set-up time
(Repeated) START condition tHD,STA
hold time
4
—
—
μs
STOP condition set-up time tSU,STO
4
—
—
—
—
μs
μs
Bus free time between a
tBUF
4.7
STOP and START condition
Note:
1. For CLHR set to 0 in the I2Cn_CTRL register
2. For the minimum HFPERCLK frequency required in Standard-mode, refer to the I2C chapter in the reference manual
3. The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW
)
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Electrical Specifications
I2C Fast-mode (Fm)
Parameter
Table 4.31. I2C Fast-mode (Fm)1
Symbol
Test Condition
Min
Typ
Max
Unit
SCL clock frequency2
SCL clock low time
SCL clock high time
SDA set-up time
fSCL
0
—
400
kHz
tLOW
1.3
0.6
—
—
—
—
—
—
—
μs
μs
ns
ns
μs
tHIGH
tSU,DAT
tHD,DAT
100
100
0.6
—
SDA hold time3
900
—
Repeated START condition tSU,STA
set-up time
(Repeated) START condition tHD,STA
hold time
0.6
—
—
μs
STOP condition set-up time tSU,STO
0.6
1.3
—
—
—
—
μs
μs
Bus free time between a
tBUF
STOP and START condition
Note:
1. For CLHR set to 1 in the I2Cn_CTRL register
2. For the minimum HFPERCLK frequency required in Fast-mode, refer to the I2C chapter in the reference manual
3. The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW
)
I2C Fast-mode Plus (Fm+)
Table 4.32. I2C Fast-mode Plus (Fm+)1
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SCL clock frequency2
SCL clock low time
SCL clock high time
SDA set-up time
fSCL
0
—
1000
kHz
tLOW
0.5
0.26
50
—
—
—
—
—
—
—
—
—
—
μs
μs
ns
ns
μs
tHIGH
tSU,DAT
tHD,DAT
SDA hold time
100
0.26
Repeated START condition tSU,STA
set-up time
(Repeated) START condition tHD,STA
hold time
0.26
—
—
μs
STOP condition set-up time tSU,STO
0.26
0.5
—
—
—
—
μs
μs
Bus free time between a
tBUF
STOP and START condition
Note:
1. For CLHR set to 0 or 1 in the I2Cn_CTRL register
2. For the minimum HFPERCLK frequency required in Fast-mode Plus, refer to the I2C chapter in the reference manual
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Electrical Specifications
4.1.19 USART SPI
SPI Master Timing
Table 4.33. SPI Master Timing
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SCLK period 1 2
tSCLK
2 *
tHFPERCLK
—
—
ns
CS to MOSI 1 2
tCS_MO
tSCLK_MO
tSU_MI
0
3
—
—
8
ns
ns
SCLK to MOSI 1 2
MISO setup time 1 2
20
IOVDD = 1.98 V
IOVDD = 3.0 V
56
37
6
—
—
—
—
—
—
ns
ns
ns
MISO hold time 1 2
tH_MI
Note:
1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0)
2. Measurement done with 8 pF output loading at 10% and 90% of VDD (figure shows 50% of VDD
)
tCS_MO
CS
tSCKL_MO
SCLK
CLKPOL = 0
tSCLK
SCLK
CLKPOL = 1
MOSI
MISO
tSU_MI
tH_MI
Figure 4.1. SPI Master Timing Diagram
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Electrical Specifications
SPI Slave Timing
Table 4.34. SPI Slave Timing
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SCKL period 1 2
tSCLK_sl
2 *
tHFPERCLK
—
—
ns
SCLK high period1 2
SCLK low period 1 2
tSCLK_hi
3 *
tHFPERCLK
—
—
—
—
ns
ns
tSCLK_lo
3 *
tHFPERCLK
CS active to MISO 1 2
CS disable to MISO 1 2
MOSI setup time 1 2
MOSI hold time 1 2
tCS_ACT_MI
tCS_DIS_MI
tSU_MO
4
4
4
—
—
—
—
50
50
—
—
ns
ns
ns
ns
tH_MO
3 + 2 *
tHFPERCLK
SCLK to MISO 1 2
tSCLK_MI
16 +
tHFPERCLK
—
66 + 2 *
tHFPERCLK
ns
Note:
1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0)
2. Measurement done with 8 pF output loading at 10% and 90% of VDD (figure shows 50% of VDD
)
tCS_ACT_MI
CS
tCS_DIS_MI
SCLK
CLKPOL = 0
tSCLK_HI
tSCLK_LO
SCLK
tSU_MO
CLKPOL = 1
tSCLK
tH_MO
MOSI
MISO
tSCLK_MI
Figure 4.2. SPI Slave Timing Diagram
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Electrical Specifications
4.2 Typical Performance Curves
Default test conditions: CCM mode, LDCDC = 4.7 μH, CDCDC = 1.0 μF, VDCDC_I = 3.3 V, VDCDC_O = 1.8 V, FDCDC_LN = 8 MHz
Efficiency VS Load Current, LN mode
Efficiency VS Load current, LP mode
100
90
80
70
60
50
40
100
90
80
70
60
50
40
LP _ CMP _ BIAS 3
Heavy Drive
Medium Drive
Light Drive
LP _ CMP _ BIAS 2
LP _ CMP _ BIAS 1
LP _ CMP _ BIAS 0
100
101
Load,mA
102
10-3
10-2
10-1
Load,mA
100
101
Relative output droop VS Load current, LP mode
Ron VS supply voltage in bypass mode
10
5
2
1.5
1
SW _ PFET _ EN 0
SW _ PFET _ EN 1
0
-5
-10
-15
-20
-25
-30
LP _ CMP _ BIAS 3
LP _ CMP _ BIAS 2
LP _ CMP _ BIAS 1
LP _ CMP _ BIAS 0
0.5
10-3
10-2
10-1
Load,mA
100
101
2
2.5
3
3.5
4
VDD,V
LN (CCM) and LP mode transition (load: 5mA)
Load Step Response in LN (CCM) mode (Heavy Drive)
DVDD
60mV/div
offset:1.8V
DVDD
50mV/div
offset:1.8V
100mA
V
2V/div
I
LOAD
1mA
SW
offset:1.8V
10μs/div
100μs/div
Figure 4.3. DC-DC Converter Typical Performance Characteristics
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Typical Connection Diagrams
5. Typical Connection Diagrams
5.1 Power
Typical power supply connections for direct supply, without using the internal DC-DC converter, are shown in the following figure.
VDD
C2
C3
C4
C5
C6
C7
C8
RFVDD
AVDD
C0
C1
C9
C10
C9
PAVDD
X1
HFXTAL_N
HFXTAL_P
LFXTAL_P
LFXTAL_N
X0
Figure 5.1. EFR32FG1 Typical Application Circuit: Direct Supply Configuration without DC-DC converter
Typical power supply circuits using the internal DC-DC converter are shown below. The MCU operates from the DC-DC converter sup-
ply. For low RF transmit power applications less than 13dBm, the RF PA may be supplied by the DC-DC converter. For OPNs support-
ing high power RF transmission, the RF PA must be directly supplied by VDD for RF transmit power greater than 13 dBm.
VDD
C2
C3
C4
C5
C6
C7
C8
L0
C9
FB2
FB1
C1
RFVDD
AVDD
C0
C10
C11
C9
PAVDD
HFXTAL_N
HFXTAL_P
LFXTAL_P
LFXTAL_N
X0
X1
Figure 5.2. EFR32FG1 Typical Application Circuit: Configuration with DC-DC Coverter (PAVDD from VDCDC)
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Typical Connection Diagrams
VDD
C2
C3
C4
C5
C6
C7
C8
L0
C9
FB1
C1
RFVDD
AVDD
C0
C10
C11
C9
PAVDD
X1
HFXTAL_N
HFXTAL_P
LFXTAL_P
LFXTAL_N
X0
Figure 5.3. EFR32FG1 Typical Application Circuit: Configuration with DC-DC Coverter (PAVDD from VDD)
5.2 RF Matching Networks
Typical RF matching network circuit diagrams are shown in Figure 5.4 Typical 2.4 GHz RF impedance-matching network circuits on
page 49 for applications in the 2.4GHz band. Application-specific component values can be found in the EFR32 Reference Manual.
For low RF transmit power applications less than 13dBm, the two-element match is recommended. For OPNs supporting high power
RF transmission, the four-element match is recommended for high RF transmit power (> 13dBm).
4-Element Match for 2.4GHz Band
2-Element Match for 2.4GHz Band
PAVDD
PAVDD
PAVDD
PAVDD
2G4RF_IOP
2G4RF_ION
L0
L0
L1
2G4RF_IOP
2G4RF_ION
50Ω
50Ω
C0
C0
C1
Figure 5.4. Typical 2.4 GHz RF impedance-matching network circuits
5.3 Other Connections
Other components or connections may be required to meet the system-level requirements. Application Note AN0002: "Hardware De-
sign Considerations" contains detailed information on these connections. Application Notes can be accessed on the Silicon Labs web-
site (www.silabs.com/32bit-appnotes).
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Pin Definitions
6. Pin Definitions
6.1 EFR32FG1 QFN48 2.4 GHz Definition
Figure 6.1. EFR32FG1 QFN48 2.4 GHz Pinout
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Pin Definitions
Table 6.1. Device Pinout
QFN48 Pin# and
Name
Pin Alternate Functionality / Description
Pin
#
Pin Name
Analog
Ground
Timers
Communication
Radio
Other
0
VSS
US0_TX #24
US0_RX #23
US0_CLK #22
US0_CS #21
US0_CTS #20
US0_RTS #19
US1_TX #24
US1_RX #23
US1_CLK #22
US1_CS #21
US1_CTS #20
US1_RTS #19
LEU0_TX #24
LEU0_RX #23
I2C0_SDA #24
I2C0_SCL #23
TIM0_CC0 #24
TIM0_CC1 #23
TIM0_CC2 #22
TIM0_CDTI0 #21
TIM0_CDTI1 #20
TIM0_CDTI2 #19
TIM1_CC0 #24
BUSAX [ADC0:
APORT1XCH16
ACMP0:
APORT1XCH16
ACMP1:
FRC_DCLK #24
FRC_DOUT #23
FRC_DFRAME #22
MODEM_DCLK #24
MODEM_DIN #23
MODEM_DOUT #22
PRS_CH0 #0
PRS_CH1 #7
PRS_CH2 #6
PRS_CH3 #5
ACMP0_O #24
ACMP1_O #24
APORT1XCH16]
1
PF0
PF1
PF2
TIM1_CC1 #23
TIM1_CC2 #22
BUSBY [ADC0:
APORT2YCH16
ACMP0:
APORT2YCH16
ACMP1:
TIM1_CC3 #21 LE-
TIM0_OUT0 #24
LETIM0_OUT1 #23
PCNT0_S0IN #24
PCNT0_S1IN #23
MODEM_ANT0 #21 DBG_SWCLKTCK
MODEM_ANT1 #20
#0
APORT2YCH16]
US0_TX #25
US0_RX #24
US0_CLK #23
US0_CS #22
US0_CTS #21
US0_RTS #20
US1_TX #25
US1_RX #24
US1_CLK #23
US1_CS #22
US1_CTS #21
US1_RTS #20
LEU0_TX #25
LEU0_RX #24
I2C0_SDA #25
I2C0_SCL #24
TIM0_CC0 #25
TIM0_CC1 #24
TIM0_CC2 #23
TIM0_CDTI0 #22
TIM0_CDTI1 #21
TIM0_CDTI2 #20
TIM1_CC0 #25
BUSAY [ADC0:
APORT1YCH17
ACMP0:
APORT1YCH17
ACMP1:
FRC_DCLK #25
FRC_DOUT #24
FRC_DFRAME #23
MODEM_DCLK #25
MODEM_DIN #24
MODEM_DOUT #23
PRS_CH0 #1
PRS_CH1 #0
PRS_CH2 #7
PRS_CH3 #6
ACMP0_O #25
ACMP1_O #25
APORT1YCH17]
2
TIM1_CC1 #24
TIM1_CC2 #23
BUSBX [ADC0:
APORT2XCH17
ACMP0:
APORT2XCH17
ACMP1:
TIM1_CC3 #22 LE-
TIM0_OUT0 #25
LETIM0_OUT1 #24
PCNT0_S0IN #25
PCNT0_S1IN #24
MODEM_ANT0 #22 DBG_SWDIOTMS
MODEM_ANT1 #21
#0
APORT2XCH17]
US0_TX #26
US0_RX #25
US0_CLK #24
US0_CS #23
US0_CTS #22
US0_RTS #21
US1_TX #26
US1_RX #25
US1_CLK #24
US1_CS #23
US1_CTS #22
US1_RTS #21
LEU0_TX #26
LEU0_RX #25
I2C0_SDA #26
I2C0_SCL #25
TIM0_CC0 #26
TIM0_CC1 #25
TIM0_CC2 #24
TIM0_CDTI0 #23
TIM0_CDTI1 #22
TIM0_CDTI2 #21
TIM1_CC0 #26
BUSAX [ADC0:
APORT1XCH18
ACMP0:
APORT1XCH18
ACMP1:
CMU_CLK0 #6
PRS_CH0 #2
PRS_CH1 #1
PRS_CH2 #0
PRS_CH3 #7
ACMP0_O #26
ACMP1_O #26
DBG_TDO #0
DBG_SWO #0
GPIO_EM4WU0
FRC_DCLK #26
FRC_DOUT #25
FRC_DFRAME #24
MODEM_DCLK #26
MODEM_DIN #25
MODEM_DOUT #24
MODEM_ANT0 #23
MODEM_ANT1 #22
APORT1XCH18]
3
TIM1_CC1 #25
TIM1_CC2 #24
BUSBY [ADC0:
APORT2YCH18
ACMP0:
APORT2YCH18
ACMP1:
TIM1_CC3 #23 LE-
TIM0_OUT0 #26
LETIM0_OUT1 #25
PCNT0_S0IN #26
PCNT0_S1IN #25
APORT2YCH18]
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Pin Definitions
QFN48 Pin# and
Name
Pin Alternate Functionality / Description
Pin
#
Pin Name
Analog
Timers
Communication
Radio
Other
US0_TX #27
US0_RX #26
US0_CLK #25
US0_CS #24
US0_CTS #23
US0_RTS #22
US1_TX #27
US1_RX #26
US1_CLK #25
US1_CS #24
US1_CTS #23
US1_RTS #22
LEU0_TX #27
LEU0_RX #26
I2C0_SDA #27
I2C0_SCL #26
TIM0_CC0 #27
TIM0_CC1 #26
TIM0_CC2 #25
TIM0_CDTI0 #24
TIM0_CDTI1 #23
TIM0_CDTI2 #22
TIM1_CC0 #27
BUSAY [ADC0:
APORT1YCH19
ACMP0:
APORT1YCH19
ACMP1:
FRC_DCLK #27
FRC_DOUT #26
CMU_CLK1 #6
PRS_CH0 #3
PRS_CH1 #2
PRS_CH2 #1
PRS_CH3 #0
ACMP0_O #27
ACMP1_O #27
DBG_TDI #0
FRC_DFRAME #25
MODEM_DCLK #27
MODEM_DIN #26
MODEM_DOUT #25
MODEM_ANT0 #24
MODEM_ANT1 #23
APORT1YCH19]
4
5
6
PF3
TIM1_CC1 #26
TIM1_CC2 #25
BUSBX [ADC0:
APORT2XCH19
ACMP0:
APORT2XCH19
ACMP1:
TIM1_CC3 #24 LE-
TIM0_OUT0 #27
LETIM0_OUT1 #26
PCNT0_S0IN #27
PCNT0_S1IN #26
APORT2XCH19]
US0_TX #28
US0_RX #27
US0_CLK #26
US0_CS #25
US0_CTS #24
US0_RTS #23
US1_TX #28
US1_RX #27
US1_CLK #26
US1_CS #25
US1_CTS #24
US1_RTS #23
LEU0_TX #28
LEU0_RX #27
I2C0_SDA #28
I2C0_SCL #27
TIM0_CC0 #28
TIM0_CC1 #27
TIM0_CC2 #26
TIM0_CDTI0 #25
TIM0_CDTI1 #24
TIM0_CDTI2 #23
TIM1_CC0 #28
BUSAX [ADC0:
APORT1XCH20
ACMP0:
APORT1XCH20
ACMP1:
FRC_DCLK #28
FRC_DOUT #27
PRS_CH0 #4
PRS_CH1 #3
PRS_CH2 #2
PRS_CH3 #1
ACMP0_O #28
ACMP1_O #28
FRC_DFRAME #26
MODEM_DCLK #28
MODEM_DIN #27
MODEM_DOUT #26
MODEM_ANT0 #25
MODEM_ANT1 #24
APORT1XCH20]
PF4
TIM1_CC1 #27
TIM1_CC2 #26
BUSBY [ADC0:
APORT2YCH20
ACMP0:
APORT2YCH20
ACMP1:
TIM1_CC3 #25 LE-
TIM0_OUT0 #28
LETIM0_OUT1 #27
PCNT0_S0IN #28
PCNT0_S1IN #27
APORT2YCH20]
US0_TX #29
US0_RX #28
US0_CLK #27
US0_CS #26
US0_CTS #25
US0_RTS #24
US1_TX #29
US1_RX #28
US1_CLK #27
US1_CS #26
US1_CTS #25
US1_RTS #24
LEU0_TX #29
LEU0_RX #28
I2C0_SDA #29
I2C0_SCL #28
TIM0_CC0 #29
TIM0_CC1 #28
TIM0_CC2 #27
TIM0_CDTI0 #26
TIM0_CDTI1 #25
TIM0_CDTI2 #24
TIM1_CC0 #29
BUSAY [ADC0:
APORT1YCH21
ACMP0:
APORT1YCH21
ACMP1:
FRC_DCLK #29
FRC_DOUT #28
PRS_CH0 #5
PRS_CH1 #4
PRS_CH2 #3
PRS_CH3 #2
ACMP0_O #29
ACMP1_O #29
FRC_DFRAME #27
MODEM_DCLK #29
MODEM_DIN #28
MODEM_DOUT #27
MODEM_ANT0 #26
MODEM_ANT1 #25
APORT1YCH21]
PF5
TIM1_CC1 #28
TIM1_CC2 #27
BUSBX [ADC0:
APORT2XCH21
ACMP0:
APORT2XCH21
ACMP1:
TIM1_CC3 #26 LE-
TIM0_OUT0 #29
LETIM0_OUT1 #28
PCNT0_S0IN #29
PCNT0_S1IN #28
APORT2XCH21]
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Pin Definitions
QFN48 Pin# and
Name
Pin Alternate Functionality / Description
Pin
#
Pin Name
Analog
Timers
Communication
Radio
Other
US0_TX #30
US0_RX #29
US0_CLK #28
US0_CS #27
US0_CTS #26
US0_RTS #25
US1_TX #30
US1_RX #29
US1_CLK #28
US1_CS #27
US1_CTS #26
US1_RTS #25
LEU0_TX #30
LEU0_RX #29
I2C0_SDA #30
I2C0_SCL #29
TIM0_CC0 #30
TIM0_CC1 #29
TIM0_CC2 #28
TIM0_CDTI0 #27
TIM0_CDTI1 #26
TIM0_CDTI2 #25
TIM1_CC0 #30
BUSAX [ADC0:
APORT1XCH22
ACMP0:
APORT1XCH22
ACMP1:
FRC_DCLK #30
FRC_DOUT #29
CMU_CLK1 #7
PRS_CH0 #6
PRS_CH1 #5
PRS_CH2 #4
PRS_CH3 #3
ACMP0_O #30
ACMP1_O #30
FRC_DFRAME #28
MODEM_DCLK #30
MODEM_DIN #29
MODEM_DOUT #28
MODEM_ANT0 #27
MODEM_ANT1 #26
APORT1XCH22]
7
PF6
TIM1_CC1 #29
TIM1_CC2 #28
BUSBY [ADC0:
APORT2YCH22
ACMP0:
APORT2YCH22
ACMP1:
TIM1_CC3 #27 LE-
TIM0_OUT0 #30
LETIM0_OUT1 #29
PCNT0_S0IN #30
PCNT0_S1IN #29
APORT2YCH22]
US0_TX #31
US0_RX #30
US0_CLK #29
US0_CS #28
US0_CTS #27
US0_RTS #26
US1_TX #31
US1_RX #30
US1_CLK #29
US1_CS #28
US1_CTS #27
US1_RTS #26
LEU0_TX #31
LEU0_RX #30
I2C0_SDA #31
I2C0_SCL #30
TIM0_CC0 #31
TIM0_CC1 #30
TIM0_CC2 #29
TIM0_CDTI0 #28
TIM0_CDTI1 #27
TIM0_CDTI2 #26
TIM1_CC0 #31
BUSAY [ADC0:
APORT1YCH23
ACMP0:
APORT1YCH23
ACMP1:
FRC_DCLK #31
FRC_DOUT #30
CMU_CLK0 #7
PRS_CH0 #7
PRS_CH1 #6
PRS_CH2 #5
PRS_CH3 #4
ACMP0_O #31
ACMP1_O #31
GPIO_EM4WU1
FRC_DFRAME #29
MODEM_DCLK #31
MODEM_DIN #30
MODEM_DOUT #29
MODEM_ANT0 #28
MODEM_ANT1 #27
APORT1YCH23]
8
PF7
TIM1_CC1 #30
TIM1_CC2 #29
BUSBX [ADC0:
APORT2XCH23
ACMP0:
APORT2XCH23
ACMP1:
TIM1_CC3 #28 LE-
TIM0_OUT0 #31
LETIM0_OUT1 #30
PCNT0_S0IN #31
PCNT0_S1IN #30
APORT2XCH23]
9
RFVDD
Radio power supply
10
11
HFXTAL_N
HFXTAL_P
High Frequency Crystal input pin.
High Frequency Crystal output pin.
Reset input, active low.To apply an external reset source to this pin, it is required to only drive this pin low
during reset, and let the internal pull-up ensure that reset is released.
12
RESETn
13
14
15
16
17
18
NC
No Connect.
RFVSS
Radio Ground
PAVSS
Power Amplifier (PA) voltage regulator VSS
2.4 GHz Differential RF input/output, negative path.
2.4 GHz Differential RF input/output, positive path.
Power Amplifier (PA) voltage regulator VDD input
2G4RF_ION
2G4RF_IOP
PAVDD
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Pin Definitions
QFN48 Pin# and
Name
Pin Alternate Functionality / Description
Pin
#
Pin Name
Analog
Timers
Communication
Radio
Other
US0_TX #18
US0_RX #17
US0_CLK #16
US0_CS #15
US0_CTS #14
US0_RTS #13
US1_TX #18
US1_RX #17
US1_CLK #16
US1_CS #15
US1_CTS #14
US1_RTS #13
LEU0_TX #18
LEU0_RX #17
I2C0_SDA #18
I2C0_SCL #17
BUSCX [ADC0:
APORT3XCH2
ACMP0:
APORT3XCH2
ACMP1:
APORT3XCH2
IDAC0:
APORT1XCH2]
TIM0_CC0 #18
TIM0_CC1 #17
TIM0_CC2 #16
TIM0_CDTI0 #15
TIM0_CDTI1 #14
TIM0_CDTI2 #13
TIM1_CC0 #18
FRC_DCLK #18
FRC_DOUT #17
CMU_CLK1 #4
PRS_CH3 #9
PRS_CH4 #1
PRS_CH5 #0
PRS_CH6 #12
ACMP0_O #18
ACMP1_O #18
FRC_DFRAME #16
MODEM_DCLK #18
MODEM_DIN #17
MODEM_DOUT #16
MODEM_ANT0 #15
MODEM_ANT1 #14
19
PD10
TIM1_CC1 #17
TIM1_CC2 #16
BUSDY [ADC0:
APORT4YCH2
ACMP0:
APORT4YCH2
ACMP1:
TIM1_CC3 #15 LE-
TIM0_OUT0 #18
LETIM0_OUT1 #17
PCNT0_S0IN #18
PCNT0_S1IN #17
APORT4YCH2]
US0_TX #19
US0_RX #18
US0_CLK #17
US0_CS #16
US0_CTS #15
US0_RTS #14
US1_TX #19
US1_RX #18
US1_CLK #17
US1_CS #16
US1_CTS #15
US1_RTS #14
LEU0_TX #19
LEU0_RX #18
I2C0_SDA #19
I2C0_SCL #18
BUSCY [ADC0:
APORT3YCH3
ACMP0:
APORT3YCH3
ACMP1:
APORT3YCH3
IDAC0:
APORT1YCH3]
TIM0_CC0 #19
TIM0_CC1 #18
TIM0_CC2 #17
TIM0_CDTI0 #16
TIM0_CDTI1 #15
TIM0_CDTI2 #14
TIM1_CC0 #19
FRC_DCLK #19
FRC_DOUT #18
PRS_CH3 #10
PRS_CH4 #2
PRS_CH5 #1
PRS_CH6 #13
ACMP0_O #19
ACMP1_O #19
FRC_DFRAME #17
MODEM_DCLK #19
MODEM_DIN #18
MODEM_DOUT #17
MODEM_ANT0 #16
MODEM_ANT1 #15
20
PD11
TIM1_CC1 #18
TIM1_CC2 #17
BUSDX [ADC0:
APORT4XCH3
ACMP0:
APORT4XCH3
ACMP1:
TIM1_CC3 #16 LE-
TIM0_OUT0 #19
LETIM0_OUT1 #18
PCNT0_S0IN #19
PCNT0_S1IN #18
APORT4XCH3]
US0_TX #20
US0_RX #19
US0_CLK #18
US0_CS #17
US0_CTS #16
US0_RTS #15
US1_TX #20
US1_RX #19
US1_CLK #18
US1_CS #17
US1_CTS #16
US1_RTS #15
LEU0_TX #20
LEU0_RX #19
I2C0_SDA #20
I2C0_SCL #19
BUSCX [ADC0:
APORT3XCH4
ACMP0:
APORT3XCH4
ACMP1:
APORT3XCH4
IDAC0:
APORT1XCH4]
TIM0_CC0 #20
TIM0_CC1 #19
TIM0_CC2 #18
TIM0_CDTI0 #17
TIM0_CDTI1 #16
TIM0_CDTI2 #15
TIM1_CC0 #20
FRC_DCLK #20
FRC_DOUT #19
PRS_CH3 #11
PRS_CH4 #3
PRS_CH5 #2
PRS_CH6 #14
ACMP0_O #20
ACMP1_O #20
FRC_DFRAME #18
MODEM_DCLK #20
MODEM_DIN #19
MODEM_DOUT #18
MODEM_ANT0 #17
MODEM_ANT1 #16
21
PD12
TIM1_CC1 #19
TIM1_CC2 #18
BUSDY [ADC0:
APORT4YCH4
ACMP0:
APORT4YCH4
ACMP1:
TIM1_CC3 #17 LE-
TIM0_OUT0 #20
LETIM0_OUT1 #19
PCNT0_S0IN #20
PCNT0_S1IN #19
APORT4YCH4]
silabs.com | Smart. Connected. Energy-friendly.
Preliminary Rev. 0.9 | 54
EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Pin Definitions
QFN48 Pin# and
Name
Pin Alternate Functionality / Description
Pin
#
Pin Name
Analog
Timers
Communication
Radio
Other
US0_TX #21
US0_RX #20
US0_CLK #19
US0_CS #18
US0_CTS #17
US0_RTS #16
US1_TX #21
US1_RX #20
US1_CLK #19
US1_CS #18
US1_CTS #17
US1_RTS #16
LEU0_TX #21
LEU0_RX #20
I2C0_SDA #21
I2C0_SCL #20
BUSCY [ADC0:
APORT3YCH5
ACMP0:
APORT3YCH5
ACMP1:
APORT3YCH5
IDAC0:
APORT1YCH5]
TIM0_CC0 #21
TIM0_CC1 #20
TIM0_CC2 #19
TIM0_CDTI0 #18
TIM0_CDTI1 #17
TIM0_CDTI2 #16
TIM1_CC0 #21
FRC_DCLK #21
FRC_DOUT #20
PRS_CH3 #12
PRS_CH4 #4
PRS_CH5 #3
PRS_CH6 #15
ACMP0_O #21
ACMP1_O #21
FRC_DFRAME #19
MODEM_DCLK #21
MODEM_DIN #20
MODEM_DOUT #19
MODEM_ANT0 #18
MODEM_ANT1 #17
22
PD13
TIM1_CC1 #20
TIM1_CC2 #19
BUSDX [ADC0:
APORT4XCH5
ACMP0:
APORT4XCH5
ACMP1:
TIM1_CC3 #18 LE-
TIM0_OUT0 #21
LETIM0_OUT1 #20
PCNT0_S0IN #21
PCNT0_S1IN #20
APORT4XCH5]
US0_TX #22
US0_RX #21
US0_CLK #20
US0_CS #19
US0_CTS #18
US0_RTS #17
US1_TX #22
US1_RX #21
US1_CLK #20
US1_CS #19
US1_CTS #18
US1_RTS #17
LEU0_TX #22
LEU0_RX #21
I2C0_SDA #22
I2C0_SCL #21
BUSCX [ADC0:
APORT3XCH6
ACMP0:
APORT3XCH6
ACMP1:
APORT3XCH6
IDAC0:
APORT1XCH6]
TIM0_CC0 #22
TIM0_CC1 #21
TIM0_CC2 #20
TIM0_CDTI0 #19
TIM0_CDTI1 #18
TIM0_CDTI2 #17
TIM1_CC0 #22
FRC_DCLK #22
FRC_DOUT #21
CMU_CLK0 #5
PRS_CH3 #13
PRS_CH4 #5
FRC_DFRAME #20
MODEM_DCLK #22
MODEM_DIN #21
MODEM_DOUT #20
MODEM_ANT0 #19
MODEM_ANT1 #18
PRS_CH5 #4
23
PD14
TIM1_CC1 #21
TIM1_CC2 #20
PRS_CH6 #16
ACMP0_O #22
ACMP1_O #22
GPIO_EM4WU4
BUSDY [ADC0:
APORT4YCH6
ACMP0:
APORT4YCH6
ACMP1:
TIM1_CC3 #19 LE-
TIM0_OUT0 #22
LETIM0_OUT1 #21
PCNT0_S0IN #22
PCNT0_S1IN #21
APORT4YCH6]
US0_TX #23
US0_RX #22
US0_CLK #21
US0_CS #20
US0_CTS #19
US0_RTS #18
US1_TX #23
US1_RX #22
US1_CLK #21
US1_CS #20
US1_CTS #19
US1_RTS #18
LEU0_TX #23
LEU0_RX #22
I2C0_SDA #23
I2C0_SCL #22
BUSCY [ADC0:
APORT3YCH7
ACMP0:
APORT3YCH7
ACMP1:
APORT3YCH7
IDAC0:
APORT1YCH7]
TIM0_CC0 #23
TIM0_CC1 #22
TIM0_CC2 #21
TIM0_CDTI0 #20
TIM0_CDTI1 #19
TIM0_CDTI2 #18
TIM1_CC0 #23
FRC_DCLK #23
FRC_DOUT #22
CMU_CLK1 #5
PRS_CH3 #14
PRS_CH4 #6
PRS_CH5 #5
PRS_CH6 #17
ACMP0_O #23
ACMP1_O #23
DBG_SWO #2
FRC_DFRAME #21
MODEM_DCLK #23
MODEM_DIN #22
MODEM_DOUT #21
MODEM_ANT0 #20
MODEM_ANT1 #19
24
PD15
TIM1_CC1 #22
TIM1_CC2 #21
BUSDX [ADC0:
APORT4XCH7
ACMP0:
APORT4XCH7
ACMP1:
TIM1_CC3 #20 LE-
TIM0_OUT0 #23
LETIM0_OUT1 #22
PCNT0_S0IN #23
PCNT0_S1IN #22
APORT4XCH7]
silabs.com | Smart. Connected. Energy-friendly.
Preliminary Rev. 0.9 | 55
EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Pin Definitions
QFN48 Pin# and
Name
Pin Alternate Functionality / Description
Pin
#
Pin Name
Analog
Timers
Communication
Radio
Other
ADC0_EXTN
US0_TX #0
US0_RX #31
US0_CLK #30
US0_CS #29
US0_CTS #28
US0_RTS #27
US1_TX #0
US1_RX #31
US1_CLK #30
US1_CS #29
US1_CTS #28
US1_RTS #27
LEU0_TX #0
LEU0_RX #31
I2C0_SDA #0
I2C0_SCL #31
TIM0_CC0 #0
TIM0_CC1 #31
TIM0_CC2 #30
TIM0_CDTI0 #29
TIM0_CDTI1 #28
TIM0_CDTI2 #27
TIM1_CC0 #0
TIM1_CC1 #31
TIM1_CC2 #30
TIM1_CC3 #29 LE-
TIM0_OUT0 #0 LE-
TIM0_OUT1 #31
PCNT0_S0IN #0
PCNT0_S1IN #31
BUSCX [ADC0:
APORT3XCH8
ACMP0:
APORT3XCH8
ACMP1:
APORT3XCH8
IDAC0:
APORT1XCH8]
FRC_DCLK #0
FRC_DOUT #31
CMU_CLK1 #0
PRS_CH6 #0
PRS_CH7 #10
PRS_CH8 #9
PRS_CH9 #8
ACMP0_O #0
ACMP1_O #0
FRC_DFRAME #30
MODEM_DCLK #0
MODEM_DIN #31
MODEM_DOUT #30
MODEM_ANT0 #29
MODEM_ANT1 #28
25
PA0
BUSDY [ADC0:
APORT4YCH8
ACMP0:
APORT4YCH8
ACMP1:
APORT4YCH8]
ADC0_EXTP
US0_TX #1
US0_RX #0
TIM0_CC0 #1
TIM0_CC1 #0
BUSCY [ADC0:
APORT3YCH9
ACMP0:
APORT3YCH9
ACMP1:
APORT3YCH9
IDAC0:
APORT1YCH9]
US0_CLK #31
US0_CS #30
US0_CTS #29
US0_RTS #28
US1_TX #1
TIM0_CC2 #31
TIM0_CDTI0 #30
TIM0_CDTI1 #29
TIM0_CDTI2 #28
TIM1_CC0 #1
FRC_DCLK #1
FRC_DOUT #0
FRC_DFRAME #31
MODEM_DCLK #1
MODEM_DIN #0
MODEM_DOUT #31
MODEM_ANT0 #30
MODEM_ANT1 #29
CMU_CLK0 #0
PRS_CH6 #1
PRS_CH7 #0
PRS_CH8 #10
PRS_CH9 #9
ACMP0_O #1
ACMP1_O #1
US1_RX #0
26
PA1
TIM1_CC1 #0
US1_CLK #31
US1_CS #30
US1_CTS #29
US1_RTS #28
LEU0_TX #1
LEU0_RX #0
I2C0_SDA #1
I2C0_SCL #0
TIM1_CC2 #31
TIM1_CC3 #30 LE-
TIM0_OUT0 #1 LE-
TIM0_OUT1 #0
PCNT0_S0IN #1
PCNT0_S1IN #0
BUSDX [ADC0:
APORT4XCH9
ACMP0:
APORT4XCH9
ACMP1:
APORT4XCH9]
US0_TX #2
US0_RX #1
BUSCX [ADC0:
APORT3XCH10
ACMP0:
APORT3XCH10
ACMP1:
APORT3XCH10
IDAC0:
APORT1XCH10]
TIM0_CC0 #2
TIM0_CC1 #1
TIM0_CC2 #0
TIM0_CDTI0 #31
TIM0_CDTI1 #30
TIM0_CDTI2 #29
TIM1_CC0 #2
US0_CLK #0
US0_CS #31
US0_CTS #30
US0_RTS #29
US1_TX #2
FRC_DCLK #2
FRC_DOUT #1
PRS_CH6 #2
PRS_CH7 #1
PRS_CH8 #0
PRS_CH9 #10
ACMP0_O #2
ACMP1_O #2
FRC_DFRAME #0
MODEM_DCLK #2
MODEM_DIN #1
MODEM_DOUT #0
MODEM_ANT0 #31
MODEM_ANT1 #30
US1_RX #1
27
PA2
TIM1_CC1 #1
TIM1_CC2 #0
US1_CLK #0
US1_CS #31
US1_CTS #30
US1_RTS #29
LEU0_TX #2
LEU0_RX #1
I2C0_SDA #2
I2C0_SCL #1
BUSDY [ADC0:
APORT4YCH10
ACMP0:
APORT4YCH10
ACMP1:
TIM1_CC3 #31 LE-
TIM0_OUT0 #2 LE-
TIM0_OUT1 #1
PCNT0_S0IN #2
PCNT0_S1IN #1
APORT4YCH10]
silabs.com | Smart. Connected. Energy-friendly.
Preliminary Rev. 0.9 | 56
EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Pin Definitions
QFN48 Pin# and
Name
Pin Alternate Functionality / Description
Pin
#
Pin Name
Analog
Timers
Communication
Radio
Other
US0_TX #3
US0_RX #2
US0_CLK #1
US0_CS #0
US0_CTS #31
US0_RTS #30
US1_TX #3
US1_RX #2
US1_CLK #1
US1_CS #0
US1_CTS #31
US1_RTS #30
LEU0_TX #3
LEU0_RX #2
I2C0_SDA #3
I2C0_SCL #2
BUSCY [ADC0:
APORT3YCH11
ACMP0:
APORT3YCH11
ACMP1:
APORT3YCH11
IDAC0:
APORT1YCH11]
TIM0_CC0 #3
TIM0_CC1 #2
TIM0_CC2 #1
TIM0_CDTI0 #0
TIM0_CDTI1 #31
TIM0_CDTI2 #30
TIM1_CC0 #3
FRC_DCLK #3
FRC_DOUT #2
PRS_CH6 #3
PRS_CH7 #2
PRS_CH8 #1
PRS_CH9 #0
ACMP0_O #3
ACMP1_O #3
GPIO_EM4WU8
FRC_DFRAME #1
MODEM_DCLK #3
MODEM_DIN #2
MODEM_DOUT #1
MODEM_ANT0 #0
MODEM_ANT1 #31
28
PA3
TIM1_CC1 #2
TIM1_CC2 #1
BUSDX [ADC0:
APORT4XCH11
ACMP0:
APORT4XCH11
ACMP1:
TIM1_CC3 #0 LE-
TIM0_OUT0 #3 LE-
TIM0_OUT1 #2
PCNT0_S0IN #3
PCNT0_S1IN #2
APORT4XCH11]
US0_TX #4
US0_RX #3
US0_CLK #2
US0_CS #1
US0_CTS #0
US0_RTS #31
US1_TX #4
US1_RX #3
US1_CLK #2
US1_CS #1
US1_CTS #0
US1_RTS #31
LEU0_TX #4
LEU0_RX #3
I2C0_SDA #4
I2C0_SCL #3
BUSCX [ADC0:
APORT3XCH12
ACMP0:
APORT3XCH12
ACMP1:
APORT3XCH12
IDAC0:
APORT1XCH12]
TIM0_CC0 #4
TIM0_CC1 #3
TIM0_CC2 #2
TIM0_CDTI0 #1
TIM0_CDTI1 #0
TIM0_CDTI2 #31
TIM1_CC0 #4
FRC_DCLK #4
FRC_DOUT #3
PRS_CH6 #4
PRS_CH7 #3
PRS_CH8 #2
PRS_CH9 #1
ACMP0_O #4
ACMP1_O #4
FRC_DFRAME #2
MODEM_DCLK #4
MODEM_DIN #3
MODEM_DOUT #2
MODEM_ANT0 #1
MODEM_ANT1 #0
29
PA4
TIM1_CC1 #3
TIM1_CC2 #2
BUSDY [ADC0:
APORT4YCH12
ACMP0:
APORT4YCH12
ACMP1:
TIM1_CC3 #1 LE-
TIM0_OUT0 #4 LE-
TIM0_OUT1 #3
PCNT0_S0IN #4
PCNT0_S1IN #3
APORT4YCH12]
US0_TX #5
US0_RX #4
US0_CLK #3
US0_CS #2
US0_CTS #1
US0_RTS #0
US1_TX #5
US1_RX #4
US1_CLK #3
US1_CS #2
US1_CTS #1
US1_RTS #0
LEU0_TX #5
LEU0_RX #4
I2C0_SDA #5
I2C0_SCL #4
BUSCY [ADC0:
APORT3YCH13
ACMP0:
APORT3YCH13
ACMP1:
APORT3YCH13
IDAC0:
APORT1YCH13]
TIM0_CC0 #5
TIM0_CC1 #4
TIM0_CC2 #3
TIM0_CDTI0 #2
TIM0_CDTI1 #1
TIM0_CDTI2 #0
TIM1_CC0 #5
FRC_DCLK #5
FRC_DOUT #4
PRS_CH6 #5
PRS_CH7 #4
PRS_CH8 #3
PRS_CH9 #2
ACMP0_O #5
ACMP1_O #5
FRC_DFRAME #3
MODEM_DCLK #5
MODEM_DIN #4
MODEM_DOUT #3
MODEM_ANT0 #2
MODEM_ANT1 #1
30
PA5
TIM1_CC1 #4
TIM1_CC2 #3
BUSDX [ADC0:
APORT4XCH13
ACMP0:
APORT4XCH13
ACMP1:
TIM1_CC3 #2 LE-
TIM0_OUT0 #5 LE-
TIM0_OUT1 #4
PCNT0_S0IN #5
PCNT0_S1IN #4
APORT4XCH13]
silabs.com | Smart. Connected. Energy-friendly.
Preliminary Rev. 0.9 | 57
EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Pin Definitions
QFN48 Pin# and
Name
Pin Alternate Functionality / Description
Pin
#
Pin Name
Analog
Timers
Communication
Radio
Other
US0_TX #6
US0_RX #5
US0_CLK #4
US0_CS #3
US0_CTS #2
US0_RTS #1
US1_TX #6
US1_RX #5
US1_CLK #4
US1_CS #3
US1_CTS #2
US1_RTS #1
LEU0_TX #6
LEU0_RX #5
I2C0_SDA #6
I2C0_SCL #5
BUSCY [ADC0:
APORT3YCH27
ACMP0:
APORT3YCH27
ACMP1:
APORT3YCH27
IDAC0:
APORT1YCH27]
TIM0_CC0 #6
TIM0_CC1 #5
TIM0_CC2 #4
TIM0_CDTI0 #3
TIM0_CDTI1 #2
TIM0_CDTI2 #1
TIM1_CC0 #6
FRC_DCLK #6
FRC_DOUT #5
PRS_CH6 #6
PRS_CH7 #5
PRS_CH8 #4
PRS_CH9 #3
ACMP0_O #6
ACMP1_O #6
FRC_DFRAME #4
MODEM_DCLK #6
MODEM_DIN #5
MODEM_DOUT #4
MODEM_ANT0 #3
MODEM_ANT1 #2
31
PB11
TIM1_CC1 #5
TIM1_CC2 #4
BUSDX [ADC0:
APORT4XCH27
ACMP0:
APORT4XCH27
ACMP1:
TIM1_CC3 #3 LE-
TIM0_OUT0 #6 LE-
TIM0_OUT1 #5
PCNT0_S0IN #6
PCNT0_S1IN #5
APORT4XCH27]
US0_TX #7
US0_RX #6
US0_CLK #5
US0_CS #4
US0_CTS #3
US0_RTS #2
US1_TX #7
US1_RX #6
US1_CLK #5
US1_CS #4
US1_CTS #3
US1_RTS #2
LEU0_TX #7
LEU0_RX #6
I2C0_SDA #7
I2C0_SCL #6
BUSCX [ADC0:
APORT3XCH28
ACMP0:
APORT3XCH28
ACMP1:
APORT3XCH28
IDAC0:
APORT1XCH28]
TIM0_CC0 #7
TIM0_CC1 #6
TIM0_CC2 #5
TIM0_CDTI0 #4
TIM0_CDTI1 #3
TIM0_CDTI2 #2
TIM1_CC0 #7
FRC_DCLK #7
FRC_DOUT #6
PRS_CH6 #7
PRS_CH7 #6
PRS_CH8 #5
PRS_CH9 #4
ACMP0_O #7
ACMP1_O #7
FRC_DFRAME #5
MODEM_DCLK #7
MODEM_DIN #6
MODEM_DOUT #5
MODEM_ANT0 #4
MODEM_ANT1 #3
32
PB12
TIM1_CC1 #6
TIM1_CC2 #5
BUSDY [ADC0:
APORT4YCH28
ACMP0:
APORT4YCH28
ACMP1:
TIM1_CC3 #4 LE-
TIM0_OUT0 #7 LE-
TIM0_OUT1 #6
PCNT0_S0IN #7
PCNT0_S1IN #6
APORT4YCH28]
US0_TX #8
US0_RX #7
US0_CLK #6
US0_CS #5
US0_CTS #4
US0_RTS #3
US1_TX #8
US1_RX #7
US1_CLK #6
US1_CS #5
US1_CTS #4
US1_RTS #3
LEU0_TX #8
LEU0_RX #7
I2C0_SDA #8
I2C0_SCL #7
BUSCY [ADC0:
APORT3YCH29
ACMP0:
APORT3YCH29
ACMP1:
APORT3YCH29
IDAC0:
APORT1YCH29]
TIM0_CC0 #8
TIM0_CC1 #7
TIM0_CC2 #6
TIM0_CDTI0 #5
TIM0_CDTI1 #4
TIM0_CDTI2 #3
TIM1_CC0 #8
FRC_DCLK #8
FRC_DOUT #7
PRS_CH6 #8
PRS_CH7 #7
PRS_CH8 #6
PRS_CH9 #5
ACMP0_O #8
ACMP1_O #8
DBG_SWO #1
GPIO_EM4WU9
FRC_DFRAME #6
MODEM_DCLK #8
MODEM_DIN #7
MODEM_DOUT #6
MODEM_ANT0 #5
MODEM_ANT1 #4
33
PB13
TIM1_CC1 #7
TIM1_CC2 #6
BUSDX [ADC0:
APORT4XCH29
ACMP0:
APORT4XCH29
ACMP1:
TIM1_CC3 #5 LE-
TIM0_OUT0 #8 LE-
TIM0_OUT1 #7
PCNT0_S0IN #8
PCNT0_S1IN #7
APORT4XCH29]
34
AVDD
Analog power supply.
silabs.com | Smart. Connected. Energy-friendly.
Preliminary Rev. 0.9 | 58
EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Pin Definitions
QFN48 Pin# and
Name
Pin Alternate Functionality / Description
Pin
#
Pin Name
Analog
Timers
Communication
Radio
Other
LFXTAL_N
US0_TX #9
US0_RX #8
US0_CLK #7
US0_CS #6
US0_CTS #5
US0_RTS #4
US1_TX #9
US1_RX #8
US1_CLK #7
US1_CS #6
US1_CTS #5
US1_RTS #4
LEU0_TX #9
LEU0_RX #8
I2C0_SDA #9
I2C0_SCL #8
TIM0_CC0 #9
TIM0_CC1 #8
TIM0_CC2 #7
TIM0_CDTI0 #6
TIM0_CDTI1 #5
TIM0_CDTI2 #4
TIM1_CC0 #9
BUSCX [ADC0:
APORT3XCH30
ACMP0:
APORT3XCH30
ACMP1:
APORT3XCH30
IDAC0:
APORT1XCH30]
FRC_DCLK #9
FRC_DOUT #8
CMU_CLK1 #1
PRS_CH6 #9
PRS_CH7 #8
PRS_CH8 #7
PRS_CH9 #6
ACMP0_O #9
ACMP1_O #9
FRC_DFRAME #7
MODEM_DCLK #9
MODEM_DIN #8
MODEM_DOUT #7
MODEM_ANT0 #6
MODEM_ANT1 #5
35
PB14
TIM1_CC1 #8
TIM1_CC2 #7
TIM1_CC3 #6 LE-
TIM0_OUT0 #9 LE-
TIM0_OUT1 #8
PCNT0_S0IN #9
PCNT0_S1IN #8
BUSDY [ADC0:
APORT4YCH30
ACMP0:
APORT4YCH30
ACMP1:
APORT4YCH30]
LFXTAL_P
US0_TX #10
US0_RX #9
US0_CLK #8
US0_CS #7
US0_CTS #6
US0_RTS #5
US1_TX #10
US1_RX #9
US1_CLK #8
US1_CS #7
TIM0_CC0 #10
TIM0_CC1 #9
TIM0_CC2 #8
TIM0_CDTI0 #7
TIM0_CDTI1 #6
TIM0_CDTI2 #5
TIM1_CC0 #10
TIM1_CC1 #9
BUSCY [ADC0:
APORT3YCH31
ACMP0:
APORT3YCH31
ACMP1:
APORT3YCH31
IDAC0:
APORT1YCH31]
FRC_DCLK #10
FRC_DOUT #9
CMU_CLK0 #1
PRS_CH6 #10
PRS_CH7 #9
PRS_CH8 #8
PRS_CH9 #7
ACMP0_O #10
ACMP1_O #10
FRC_DFRAME #8
MODEM_DCLK #10
MODEM_DIN #9
MODEM_DOUT #8
MODEM_ANT0 #7
MODEM_ANT1 #6
36
PB15
TIM1_CC2 #8
TIM1_CC3 #7 LE-
TIM0_OUT0 #10
LETIM0_OUT1 #9
PCNT0_S0IN #10
PCNT0_S1IN #9
US1_CTS #6
US1_RTS #5
LEU0_TX #10
LEU0_RX #9
I2C0_SDA #10
I2C0_SCL #9
BUSDX [ADC0:
APORT4XCH31
ACMP0:
APORT4XCH31
ACMP1:
APORT4XCH31]
37
38
39
40
VREGVSS
VREGSW
VREGVDD
DVDD
Voltage regulator VSS
DCDC regulator switching node
Voltage regulator VDD input
Digital power supply.
Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this
pin.
41
42
DECOUPLE
IOVDD
Digital IO power supply.
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Pin Definitions
QFN48 Pin# and
Name
Pin Alternate Functionality / Description
Pin
#
Pin Name
Analog
Timers
Communication
Radio
Other
US0_TX #11
US0_RX #10
US0_CLK #9
US0_CS #8
US0_CTS #7
US0_RTS #6
US1_TX #11
US1_RX #10
US1_CLK #9
US1_CS #8
US1_CTS #7
US1_RTS #6
LEU0_TX #11
LEU0_RX #10
I2C0_SDA #11
I2C0_SCL #10
TIM0_CC0 #11
TIM0_CC1 #10
TIM0_CC2 #9
TIM0_CDTI0 #8
TIM0_CDTI1 #7
TIM0_CDTI2 #6
TIM1_CC0 #11
TIM1_CC1 #10
TIM1_CC2 #9
TIM1_CC3 #8 LE-
TIM0_OUT0 #11
LETIM0_OUT1 #10
PCNT0_S0IN #11
PCNT0_S1IN #10
BUSAX [ADC0:
APORT1XCH6
ACMP0:
APORT1XCH6
ACMP1:
FRC_DCLK #11
FRC_DOUT #10
CMU_CLK0 #2
PRS_CH0 #8
PRS_CH9 #11
PRS_CH10 #0
PRS_CH11 #5
ACMP0_O #11
ACMP1_O #11
FRC_DFRAME #9
MODEM_DCLK #11
MODEM_DIN #10
MODEM_DOUT #9
MODEM_ANT0 #8
MODEM_ANT1 #7
APORT1XCH6]
43
PC6
BUSBY [ADC0:
APORT2YCH6
ACMP0:
APORT2YCH6
ACMP1:
APORT2YCH6]
US0_TX #12
US0_RX #11
US0_CLK #10
US0_CS #9
US0_CTS #8
US0_RTS #7
US1_TX #12
US1_RX #11
US1_CLK #10
US1_CS #9
US1_CTS #8
US1_RTS #7
LEU0_TX #12
LEU0_RX #11
I2C0_SDA #12
I2C0_SCL #11
TIM0_CC0 #12
TIM0_CC1 #11
TIM0_CC2 #10
TIM0_CDTI0 #9
TIM0_CDTI1 #8
TIM0_CDTI2 #7
TIM1_CC0 #12
TIM1_CC1 #11
TIM1_CC2 #10
TIM1_CC3 #9 LE-
TIM0_OUT0 #12
LETIM0_OUT1 #11
PCNT0_S0IN #12
PCNT0_S1IN #11
BUSAY [ADC0:
APORT1YCH7
ACMP0:
APORT1YCH7
ACMP1:
FRC_DCLK #12
FRC_DOUT #11
CMU_CLK1 #2
PRS_CH0 #9
PRS_CH9 #12
PRS_CH10 #1
PRS_CH11 #0
ACMP0_O #12
ACMP1_O #12
FRC_DFRAME #10
MODEM_DCLK #12
MODEM_DIN #11
MODEM_DOUT #10
MODEM_ANT0 #9
MODEM_ANT1 #8
APORT1YCH7]
44
PC7
BUSBX [ADC0:
APORT2XCH7
ACMP0:
APORT2XCH7
ACMP1:
APORT2XCH7]
US0_TX #13
US0_RX #12
US0_CLK #11
US0_CS #10
US0_CTS #9
US0_RTS #8
US1_TX #13
US1_RX #12
US1_CLK #11
US1_CS #10
US1_CTS #9
US1_RTS #8
LEU0_TX #13
LEU0_RX #12
I2C0_SDA #13
I2C0_SCL #12
TIM0_CC0 #13
TIM0_CC1 #12
TIM0_CC2 #11
TIM0_CDTI0 #10
TIM0_CDTI1 #9
TIM0_CDTI2 #8
TIM1_CC0 #13
TIM1_CC1 #12
TIM1_CC2 #11
TIM1_CC3 #10 LE-
TIM0_OUT0 #13
LETIM0_OUT1 #12
PCNT0_S0IN #13
PCNT0_S1IN #12
BUSAX [ADC0:
APORT1XCH8
ACMP0:
APORT1XCH8
ACMP1:
FRC_DCLK #13
FRC_DOUT #12
PRS_CH0 #10
PRS_CH9 #13
PRS_CH10 #2
PRS_CH11 #1
ACMP0_O #13
ACMP1_O #13
FRC_DFRAME #11
MODEM_DCLK #13
MODEM_DIN #12
MODEM_DOUT #11
MODEM_ANT0 #10
MODEM_ANT1 #9
APORT1XCH8]
45
PC8
BUSBY [ADC0:
APORT2YCH8
ACMP0:
APORT2YCH8
ACMP1:
APORT2YCH8]
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Pin Definitions
QFN48 Pin# and
Name
Pin Alternate Functionality / Description
Pin
#
Pin Name
Analog
Timers
Communication
Radio
Other
US0_TX #14
US0_RX #13
US0_CLK #12
US0_CS #11
US0_CTS #10
US0_RTS #9
US1_TX #14
US1_RX #13
US1_CLK #12
US1_CS #11
US1_CTS #10
US1_RTS #9
LEU0_TX #14
LEU0_RX #13
I2C0_SDA #14
I2C0_SCL #13
TIM0_CC0 #14
TIM0_CC1 #13
TIM0_CC2 #12
TIM0_CDTI0 #11
TIM0_CDTI1 #10
TIM0_CDTI2 #9
TIM1_CC0 #14
BUSAY [ADC0:
APORT1YCH9
ACMP0:
APORT1YCH9
ACMP1:
FRC_DCLK #14
FRC_DOUT #13
PRS_CH0 #11
PRS_CH9 #14
PRS_CH10 #3
PRS_CH11 #2
ACMP0_O #14
ACMP1_O #14
FRC_DFRAME #12
MODEM_DCLK #14
MODEM_DIN #13
MODEM_DOUT #12
MODEM_ANT0 #11
MODEM_ANT1 #10
APORT1YCH9]
46
PC9
TIM1_CC1 #13
TIM1_CC2 #12
BUSBX [ADC0:
APORT2XCH9
ACMP0:
APORT2XCH9
ACMP1:
TIM1_CC3 #11 LE-
TIM0_OUT0 #14
LETIM0_OUT1 #13
PCNT0_S0IN #14
PCNT0_S1IN #13
APORT2XCH9]
US0_TX #15
US0_RX #14
US0_CLK #13
US0_CS #12
US0_CTS #11
US0_RTS #10
US1_TX #15
US1_RX #14
US1_CLK #13
US1_CS #12
US1_CTS #11
US1_RTS #10
LEU0_TX #15
LEU0_RX #14
I2C0_SDA #15
I2C0_SCL #14
TIM0_CC0 #15
TIM0_CC1 #14
TIM0_CC2 #13
TIM0_CDTI0 #12
TIM0_CDTI1 #11
TIM0_CDTI2 #10
TIM1_CC0 #15
BUSAX [ADC0:
APORT1XCH10
ACMP0:
APORT1XCH10
ACMP1:
FRC_DCLK #15
FRC_DOUT #14
CMU_CLK1 #3
PRS_CH0 #12
PRS_CH9 #15
PRS_CH10 #4
PRS_CH11 #3
ACMP0_O #15
ACMP1_O #15
GPIO_EM4WU12
FRC_DFRAME #13
MODEM_DCLK #15
MODEM_DIN #14
MODEM_DOUT #13
MODEM_ANT0 #12
MODEM_ANT1 #11
APORT1XCH10]
47
PC10
TIM1_CC1 #14
TIM1_CC2 #13
BUSBY [ADC0:
APORT2YCH10
ACMP0:
APORT2YCH10
ACMP1:
TIM1_CC3 #12 LE-
TIM0_OUT0 #15
LETIM0_OUT1 #14
PCNT0_S0IN #15
PCNT0_S1IN #14
APORT2YCH10]
US0_TX #16
US0_RX #15
US0_CLK #14
US0_CS #13
US0_CTS #12
US0_RTS #11
US1_TX #16
US1_RX #15
US1_CLK #14
US1_CS #13
US1_CTS #12
US1_RTS #11
LEU0_TX #16
LEU0_RX #15
I2C0_SDA #16
I2C0_SCL #15
TIM0_CC0 #16
TIM0_CC1 #15
TIM0_CC2 #14
TIM0_CDTI0 #13
TIM0_CDTI1 #12
TIM0_CDTI2 #11
TIM1_CC0 #16
BUSAY [ADC0:
APORT1YCH11
ACMP0:
APORT1YCH11
ACMP1:
FRC_DCLK #16
FRC_DOUT #15
CMU_CLK0 #3
PRS_CH0 #13
PRS_CH9 #16
PRS_CH10 #5
PRS_CH11 #4
ACMP0_O #16
ACMP1_O #16
DBG_SWO #3
FRC_DFRAME #14
MODEM_DCLK #16
MODEM_DIN #15
MODEM_DOUT #14
MODEM_ANT0 #13
MODEM_ANT1 #12
APORT1YCH11]
48
PC11
TIM1_CC1 #15
TIM1_CC2 #14
BUSBX [ADC0:
APORT2XCH11
ACMP0:
APORT2XCH11
ACMP1:
TIM1_CC3 #13 LE-
TIM0_OUT0 #16
LETIM0_OUT1 #15
PCNT0_S0IN #16
PCNT0_S1IN #15
APORT2XCH11]
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Pin Definitions
6.1.1 EFR32FG1 QFN48 2.4 GHz GPIO Overview
The GPIO pins are organized as 16-bit ports indicated by letters A through F, and the individual pins on each port are indicated by a
number from 15 down to 0.
Table 6.2. GPIO Pinout
Port
Pin
15
Pin
14
Pin
13
Pin
12
Pin
11
Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0
10
PA5 PA4 PA3 PA2
(5V) (5V) (5V) (5V)
Port A
Port B
Port C
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PA1 PA0
PB13 PB12 PB11
(5V) (5V) (5V)
PB15 PB14
-
-
-
-
-
-
-
-
-
-
-
-
PC11 PC10 PC9 PC8 PC7 PC6
(5V) (5V) (5V) (5V) (5V) (5V)
-
-
-
-
PD15 PD14 PD13 PD12 PD11 PD10
(5V) (5V) (5V) (5V) (5V) (5V)
Port D
Port E
Port F
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0
(5V) (5V) (5V) (5V) (5V) (5V) (5V) (5V)
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Pin Definitions
6.2 EFR32FG1 QFN32 2.4 GHz Definition
Figure 6.2. EFR32FG1 QFN32 2.4 GHz Pinout
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Preliminary Rev. 0.9 | 63
EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Pin Definitions
Table 6.3. Device Pinout
QFN32 Pin# and
Name
Pin Alternate Functionality / Description
Pin
#
Pin Name
Analog
Ground
Timers
Communication
Radio
Other
0
VSS
US0_TX #24
US0_RX #23
US0_CLK #22
US0_CS #21
US0_CTS #20
US0_RTS #19
US1_TX #24
US1_RX #23
US1_CLK #22
US1_CS #21
US1_CTS #20
US1_RTS #19
LEU0_TX #24
LEU0_RX #23
I2C0_SDA #24
I2C0_SCL #23
TIM0_CC0 #24
TIM0_CC1 #23
TIM0_CC2 #22
TIM0_CDTI0 #21
TIM0_CDTI1 #20
TIM0_CDTI2 #19
TIM1_CC0 #24
BUSAX [ADC0:
APORT1XCH16
ACMP0:
APORT1XCH16
ACMP1:
FRC_DCLK #24
FRC_DOUT #23
FRC_DFRAME #22
MODEM_DCLK #24
MODEM_DIN #23
MODEM_DOUT #22
PRS_CH0 #0
PRS_CH1 #7
PRS_CH2 #6
PRS_CH3 #5
ACMP0_O #24
ACMP1_O #24
APORT1XCH16]
1
PF0
PF1
PF2
TIM1_CC1 #23
TIM1_CC2 #22
BUSBY [ADC0:
APORT2YCH16
ACMP0:
APORT2YCH16
ACMP1:
TIM1_CC3 #21 LE-
TIM0_OUT0 #24
LETIM0_OUT1 #23
PCNT0_S0IN #24
PCNT0_S1IN #23
MODEM_ANT0 #21 DBG_SWCLKTCK
MODEM_ANT1 #20
#0
APORT2YCH16]
US0_TX #25
US0_RX #24
US0_CLK #23
US0_CS #22
US0_CTS #21
US0_RTS #20
US1_TX #25
US1_RX #24
US1_CLK #23
US1_CS #22
US1_CTS #21
US1_RTS #20
LEU0_TX #25
LEU0_RX #24
I2C0_SDA #25
I2C0_SCL #24
TIM0_CC0 #25
TIM0_CC1 #24
TIM0_CC2 #23
TIM0_CDTI0 #22
TIM0_CDTI1 #21
TIM0_CDTI2 #20
TIM1_CC0 #25
BUSAY [ADC0:
APORT1YCH17
ACMP0:
APORT1YCH17
ACMP1:
FRC_DCLK #25
FRC_DOUT #24
FRC_DFRAME #23
MODEM_DCLK #25
MODEM_DIN #24
MODEM_DOUT #23
PRS_CH0 #1
PRS_CH1 #0
PRS_CH2 #7
PRS_CH3 #6
ACMP0_O #25
ACMP1_O #25
APORT1YCH17]
2
TIM1_CC1 #24
TIM1_CC2 #23
BUSBX [ADC0:
APORT2XCH17
ACMP0:
APORT2XCH17
ACMP1:
TIM1_CC3 #22 LE-
TIM0_OUT0 #25
LETIM0_OUT1 #24
PCNT0_S0IN #25
PCNT0_S1IN #24
MODEM_ANT0 #22 DBG_SWDIOTMS
MODEM_ANT1 #21
#0
APORT2XCH17]
US0_TX #26
US0_RX #25
US0_CLK #24
US0_CS #23
US0_CTS #22
US0_RTS #21
US1_TX #26
US1_RX #25
US1_CLK #24
US1_CS #23
US1_CTS #22
US1_RTS #21
LEU0_TX #26
LEU0_RX #25
I2C0_SDA #26
I2C0_SCL #25
TIM0_CC0 #26
TIM0_CC1 #25
TIM0_CC2 #24
TIM0_CDTI0 #23
TIM0_CDTI1 #22
TIM0_CDTI2 #21
TIM1_CC0 #26
BUSAX [ADC0:
APORT1XCH18
ACMP0:
APORT1XCH18
ACMP1:
CMU_CLK0 #6
PRS_CH0 #2
PRS_CH1 #1
PRS_CH2 #0
PRS_CH3 #7
ACMP0_O #26
ACMP1_O #26
DBG_TDO #0
DBG_SWO #0
GPIO_EM4WU0
FRC_DCLK #26
FRC_DOUT #25
FRC_DFRAME #24
MODEM_DCLK #26
MODEM_DIN #25
MODEM_DOUT #24
MODEM_ANT0 #23
MODEM_ANT1 #22
APORT1XCH18]
3
TIM1_CC1 #25
TIM1_CC2 #24
BUSBY [ADC0:
APORT2YCH18
ACMP0:
APORT2YCH18
ACMP1:
TIM1_CC3 #23 LE-
TIM0_OUT0 #26
LETIM0_OUT1 #25
PCNT0_S0IN #26
PCNT0_S1IN #25
APORT2YCH18]
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Preliminary Rev. 0.9 | 64
EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Pin Definitions
QFN32 Pin# and
Name
Pin Alternate Functionality / Description
Pin
#
Pin Name
Analog
Timers
Communication
Radio
Other
US0_TX #27
US0_RX #26
US0_CLK #25
US0_CS #24
US0_CTS #23
US0_RTS #22
US1_TX #27
US1_RX #26
US1_CLK #25
US1_CS #24
US1_CTS #23
US1_RTS #22
LEU0_TX #27
LEU0_RX #26
I2C0_SDA #27
I2C0_SCL #26
TIM0_CC0 #27
TIM0_CC1 #26
TIM0_CC2 #25
TIM0_CDTI0 #24
TIM0_CDTI1 #23
TIM0_CDTI2 #22
TIM1_CC0 #27
BUSAY [ADC0:
APORT1YCH19
ACMP0:
APORT1YCH19
ACMP1:
FRC_DCLK #27
FRC_DOUT #26
CMU_CLK1 #6
PRS_CH0 #3
PRS_CH1 #2
PRS_CH2 #1
PRS_CH3 #0
ACMP0_O #27
ACMP1_O #27
DBG_TDI #0
FRC_DFRAME #25
MODEM_DCLK #27
MODEM_DIN #26
MODEM_DOUT #25
MODEM_ANT0 #24
MODEM_ANT1 #23
APORT1YCH19]
4
PF3
TIM1_CC1 #26
TIM1_CC2 #25
BUSBX [ADC0:
APORT2XCH19
ACMP0:
APORT2XCH19
ACMP1:
TIM1_CC3 #24 LE-
TIM0_OUT0 #27
LETIM0_OUT1 #26
PCNT0_S0IN #27
PCNT0_S1IN #26
APORT2XCH19]
5
6
7
RFVDD
Radio power supply
HFXTAL_N
HFXTAL_P
High Frequency Crystal input pin.
High Frequency Crystal output pin.
Reset input, active low.To apply an external reset source to this pin, it is required to only drive this pin low
during reset, and let the internal pull-up ensure that reset is released.
8
9
RESETn
RFVSS
PAVSS
Radio Ground
10
11
12
13
Power Amplifier (PA) voltage regulator VSS
2.4 GHz Differential RF input/output, negative path.
2.4 GHz Differential RF input/output, positive path.
Power Amplifier (PA) voltage regulator VDD input
2G4RF_ION
2G4RF_IOP
PAVDD
US0_TX #21
BUSCY [ADC0:
APORT3YCH5
ACMP0:
APORT3YCH5
ACMP1:
APORT3YCH5
IDAC0:
TIM0_CC0 #21
TIM0_CC1 #20
TIM0_CC2 #19
TIM0_CDTI0 #18
TIM0_CDTI1 #17
TIM0_CDTI2 #16
TIM1_CC0 #21
US0_RX #20
US0_CLK #19
US0_CS #18
US0_CTS #17
US0_RTS #16
US1_TX #21
US1_RX #20
US1_CLK #19
US1_CS #18
US1_CTS #17
US1_RTS #16
LEU0_TX #21
LEU0_RX #20
I2C0_SDA #21
I2C0_SCL #20
FRC_DCLK #21
FRC_DOUT #20
PRS_CH3 #12
PRS_CH4 #4
PRS_CH5 #3
PRS_CH6 #15
ACMP0_O #21
ACMP1_O #21
FRC_DFRAME #19
MODEM_DCLK #21
MODEM_DIN #20
MODEM_DOUT #19
MODEM_ANT0 #18
MODEM_ANT1 #17
14
PD13
APORT1YCH5]
TIM1_CC1 #20
TIM1_CC2 #19
BUSDX [ADC0:
APORT4XCH5
ACMP0:
APORT4XCH5
ACMP1:
TIM1_CC3 #18 LE-
TIM0_OUT0 #21
LETIM0_OUT1 #20
PCNT0_S0IN #21
PCNT0_S1IN #20
APORT4XCH5]
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Preliminary Rev. 0.9 | 65
EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Pin Definitions
QFN32 Pin# and
Name
Pin Alternate Functionality / Description
Pin
#
Pin Name
Analog
Timers
Communication
Radio
Other
US0_TX #22
US0_RX #21
US0_CLK #20
US0_CS #19
US0_CTS #18
US0_RTS #17
US1_TX #22
US1_RX #21
US1_CLK #20
US1_CS #19
US1_CTS #18
US1_RTS #17
LEU0_TX #22
LEU0_RX #21
I2C0_SDA #22
I2C0_SCL #21
BUSCX [ADC0:
APORT3XCH6
ACMP0:
APORT3XCH6
ACMP1:
APORT3XCH6
IDAC0:
APORT1XCH6]
TIM0_CC0 #22
TIM0_CC1 #21
TIM0_CC2 #20
TIM0_CDTI0 #19
TIM0_CDTI1 #18
TIM0_CDTI2 #17
TIM1_CC0 #22
FRC_DCLK #22
FRC_DOUT #21
CMU_CLK0 #5
PRS_CH3 #13
PRS_CH4 #5
FRC_DFRAME #20
MODEM_DCLK #22
MODEM_DIN #21
MODEM_DOUT #20
MODEM_ANT0 #19
MODEM_ANT1 #18
PRS_CH5 #4
15
PD14
TIM1_CC1 #21
TIM1_CC2 #20
PRS_CH6 #16
ACMP0_O #22
ACMP1_O #22
GPIO_EM4WU4
BUSDY [ADC0:
APORT4YCH6
ACMP0:
APORT4YCH6
ACMP1:
TIM1_CC3 #19 LE-
TIM0_OUT0 #22
LETIM0_OUT1 #21
PCNT0_S0IN #22
PCNT0_S1IN #21
APORT4YCH6]
US0_TX #23
US0_RX #22
US0_CLK #21
US0_CS #20
US0_CTS #19
US0_RTS #18
US1_TX #23
US1_RX #22
US1_CLK #21
US1_CS #20
US1_CTS #19
US1_RTS #18
LEU0_TX #23
LEU0_RX #22
I2C0_SDA #23
I2C0_SCL #22
BUSCY [ADC0:
APORT3YCH7
ACMP0:
APORT3YCH7
ACMP1:
APORT3YCH7
IDAC0:
APORT1YCH7]
TIM0_CC0 #23
TIM0_CC1 #22
TIM0_CC2 #21
TIM0_CDTI0 #20
TIM0_CDTI1 #19
TIM0_CDTI2 #18
TIM1_CC0 #23
FRC_DCLK #23
FRC_DOUT #22
CMU_CLK1 #5
PRS_CH3 #14
PRS_CH4 #6
PRS_CH5 #5
PRS_CH6 #17
ACMP0_O #23
ACMP1_O #23
DBG_SWO #2
FRC_DFRAME #21
MODEM_DCLK #23
MODEM_DIN #22
MODEM_DOUT #21
MODEM_ANT0 #20
MODEM_ANT1 #19
16
PD15
TIM1_CC1 #22
TIM1_CC2 #21
BUSDX [ADC0:
APORT4XCH7
ACMP0:
APORT4XCH7
ACMP1:
TIM1_CC3 #20 LE-
TIM0_OUT0 #23
LETIM0_OUT1 #22
PCNT0_S0IN #23
PCNT0_S1IN #22
APORT4XCH7]
ADC0_EXTN
US0_TX #0
US0_RX #31
US0_CLK #30
US0_CS #29
US0_CTS #28
US0_RTS #27
US1_TX #0
US1_RX #31
US1_CLK #30
US1_CS #29
US1_CTS #28
US1_RTS #27
LEU0_TX #0
LEU0_RX #31
I2C0_SDA #0
I2C0_SCL #31
TIM0_CC0 #0
TIM0_CC1 #31
TIM0_CC2 #30
TIM0_CDTI0 #29
TIM0_CDTI1 #28
TIM0_CDTI2 #27
TIM1_CC0 #0
TIM1_CC1 #31
TIM1_CC2 #30
TIM1_CC3 #29 LE-
TIM0_OUT0 #0 LE-
TIM0_OUT1 #31
PCNT0_S0IN #0
PCNT0_S1IN #31
BUSCX [ADC0:
APORT3XCH8
ACMP0:
APORT3XCH8
ACMP1:
APORT3XCH8
IDAC0:
APORT1XCH8]
FRC_DCLK #0
FRC_DOUT #31
CMU_CLK1 #0
PRS_CH6 #0
PRS_CH7 #10
PRS_CH8 #9
PRS_CH9 #8
ACMP0_O #0
ACMP1_O #0
FRC_DFRAME #30
MODEM_DCLK #0
MODEM_DIN #31
MODEM_DOUT #30
MODEM_ANT0 #29
MODEM_ANT1 #28
17
PA0
BUSDY [ADC0:
APORT4YCH8
ACMP0:
APORT4YCH8
ACMP1:
APORT4YCH8]
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Pin Definitions
QFN32 Pin# and
Name
Pin Alternate Functionality / Description
Pin
#
Pin Name
Analog
Timers
Communication
Radio
Other
ADC0_EXTP
US0_TX #1
US0_RX #0
TIM0_CC0 #1
TIM0_CC1 #0
BUSCY [ADC0:
APORT3YCH9
ACMP0:
APORT3YCH9
ACMP1:
APORT3YCH9
IDAC0:
APORT1YCH9]
US0_CLK #31
US0_CS #30
US0_CTS #29
US0_RTS #28
US1_TX #1
TIM0_CC2 #31
TIM0_CDTI0 #30
TIM0_CDTI1 #29
TIM0_CDTI2 #28
TIM1_CC0 #1
FRC_DCLK #1
FRC_DOUT #0
FRC_DFRAME #31
MODEM_DCLK #1
MODEM_DIN #0
MODEM_DOUT #31
MODEM_ANT0 #30
MODEM_ANT1 #29
CMU_CLK0 #0
PRS_CH6 #1
PRS_CH7 #0
PRS_CH8 #10
PRS_CH9 #9
ACMP0_O #1
ACMP1_O #1
US1_RX #0
18
PA1
TIM1_CC1 #0
US1_CLK #31
US1_CS #30
US1_CTS #29
US1_RTS #28
LEU0_TX #1
LEU0_RX #0
I2C0_SDA #1
I2C0_SCL #0
TIM1_CC2 #31
TIM1_CC3 #30 LE-
TIM0_OUT0 #1 LE-
TIM0_OUT1 #0
PCNT0_S0IN #1
PCNT0_S1IN #0
BUSDX [ADC0:
APORT4XCH9
ACMP0:
APORT4XCH9
ACMP1:
APORT4XCH9]
US0_TX #6
US0_RX #5
US0_CLK #4
US0_CS #3
US0_CTS #2
US0_RTS #1
US1_TX #6
US1_RX #5
US1_CLK #4
US1_CS #3
US1_CTS #2
US1_RTS #1
LEU0_TX #6
LEU0_RX #5
I2C0_SDA #6
I2C0_SCL #5
BUSCY [ADC0:
APORT3YCH27
ACMP0:
APORT3YCH27
ACMP1:
APORT3YCH27
IDAC0:
APORT1YCH27]
TIM0_CC0 #6
TIM0_CC1 #5
TIM0_CC2 #4
TIM0_CDTI0 #3
TIM0_CDTI1 #2
TIM0_CDTI2 #1
TIM1_CC0 #6
FRC_DCLK #6
FRC_DOUT #5
PRS_CH6 #6
PRS_CH7 #5
PRS_CH8 #4
PRS_CH9 #3
ACMP0_O #6
ACMP1_O #6
FRC_DFRAME #4
MODEM_DCLK #6
MODEM_DIN #5
MODEM_DOUT #4
MODEM_ANT0 #3
MODEM_ANT1 #2
19
PB11
TIM1_CC1 #5
TIM1_CC2 #4
BUSDX [ADC0:
APORT4XCH27
ACMP0:
APORT4XCH27
ACMP1:
TIM1_CC3 #3 LE-
TIM0_OUT0 #6 LE-
TIM0_OUT1 #5
PCNT0_S0IN #6
PCNT0_S1IN #5
APORT4XCH27]
US0_TX #7
US0_RX #6
US0_CLK #5
US0_CS #4
US0_CTS #3
US0_RTS #2
US1_TX #7
US1_RX #6
US1_CLK #5
US1_CS #4
US1_CTS #3
US1_RTS #2
LEU0_TX #7
LEU0_RX #6
I2C0_SDA #7
I2C0_SCL #6
BUSCX [ADC0:
APORT3XCH28
ACMP0:
APORT3XCH28
ACMP1:
APORT3XCH28
IDAC0:
APORT1XCH28]
TIM0_CC0 #7
TIM0_CC1 #6
TIM0_CC2 #5
TIM0_CDTI0 #4
TIM0_CDTI1 #3
TIM0_CDTI2 #2
TIM1_CC0 #7
FRC_DCLK #7
FRC_DOUT #6
PRS_CH6 #7
PRS_CH7 #6
PRS_CH8 #5
PRS_CH9 #4
ACMP0_O #7
ACMP1_O #7
FRC_DFRAME #5
MODEM_DCLK #7
MODEM_DIN #6
MODEM_DOUT #5
MODEM_ANT0 #4
MODEM_ANT1 #3
20
PB12
TIM1_CC1 #6
TIM1_CC2 #5
BUSDY [ADC0:
APORT4YCH28
ACMP0:
APORT4YCH28
ACMP1:
TIM1_CC3 #4 LE-
TIM0_OUT0 #7 LE-
TIM0_OUT1 #6
PCNT0_S0IN #7
PCNT0_S1IN #6
APORT4YCH28]
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Pin Definitions
QFN32 Pin# and
Name
Pin Alternate Functionality / Description
Pin
#
Pin Name
Analog
Timers
Communication
Radio
Other
US0_TX #8
US0_RX #7
US0_CLK #6
US0_CS #5
US0_CTS #4
US0_RTS #3
US1_TX #8
US1_RX #7
US1_CLK #6
US1_CS #5
US1_CTS #4
US1_RTS #3
LEU0_TX #8
LEU0_RX #7
I2C0_SDA #8
I2C0_SCL #7
BUSCY [ADC0:
APORT3YCH29
ACMP0:
APORT3YCH29
ACMP1:
APORT3YCH29
IDAC0:
APORT1YCH29]
TIM0_CC0 #8
TIM0_CC1 #7
TIM0_CC2 #6
TIM0_CDTI0 #5
TIM0_CDTI1 #4
TIM0_CDTI2 #3
TIM1_CC0 #8
FRC_DCLK #8
FRC_DOUT #7
PRS_CH6 #8
PRS_CH7 #7
PRS_CH8 #6
PRS_CH9 #5
ACMP0_O #8
ACMP1_O #8
DBG_SWO #1
GPIO_EM4WU9
FRC_DFRAME #6
MODEM_DCLK #8
MODEM_DIN #7
MODEM_DOUT #6
MODEM_ANT0 #5
MODEM_ANT1 #4
21
PB13
TIM1_CC1 #7
TIM1_CC2 #6
BUSDX [ADC0:
APORT4XCH29
ACMP0:
APORT4XCH29
ACMP1:
TIM1_CC3 #5 LE-
TIM0_OUT0 #8 LE-
TIM0_OUT1 #7
PCNT0_S0IN #8
PCNT0_S1IN #7
APORT4XCH29]
22
AVDD
Analog power supply.
LFXTAL_N
US0_TX #9
US0_RX #8
US0_CLK #7
US0_CS #6
US0_CTS #5
US0_RTS #4
US1_TX #9
US1_RX #8
US1_CLK #7
US1_CS #6
US1_CTS #5
US1_RTS #4
LEU0_TX #9
LEU0_RX #8
I2C0_SDA #9
I2C0_SCL #8
TIM0_CC0 #9
TIM0_CC1 #8
TIM0_CC2 #7
TIM0_CDTI0 #6
TIM0_CDTI1 #5
TIM0_CDTI2 #4
TIM1_CC0 #9
BUSCX [ADC0:
APORT3XCH30
ACMP0:
APORT3XCH30
ACMP1:
APORT3XCH30
IDAC0:
APORT1XCH30]
FRC_DCLK #9
FRC_DOUT #8
CMU_CLK1 #1
PRS_CH6 #9
PRS_CH7 #8
PRS_CH8 #7
PRS_CH9 #6
ACMP0_O #9
ACMP1_O #9
FRC_DFRAME #7
MODEM_DCLK #9
MODEM_DIN #8
MODEM_DOUT #7
MODEM_ANT0 #6
MODEM_ANT1 #5
23
PB14
TIM1_CC1 #8
TIM1_CC2 #7
TIM1_CC3 #6 LE-
TIM0_OUT0 #9 LE-
TIM0_OUT1 #8
PCNT0_S0IN #9
PCNT0_S1IN #8
BUSDY [ADC0:
APORT4YCH30
ACMP0:
APORT4YCH30
ACMP1:
APORT4YCH30]
LFXTAL_P
US0_TX #10
US0_RX #9
US0_CLK #8
US0_CS #7
US0_CTS #6
US0_RTS #5
US1_TX #10
US1_RX #9
US1_CLK #8
US1_CS #7
TIM0_CC0 #10
TIM0_CC1 #9
TIM0_CC2 #8
TIM0_CDTI0 #7
TIM0_CDTI1 #6
TIM0_CDTI2 #5
TIM1_CC0 #10
TIM1_CC1 #9
BUSCY [ADC0:
APORT3YCH31
ACMP0:
APORT3YCH31
ACMP1:
APORT3YCH31
IDAC0:
APORT1YCH31]
FRC_DCLK #10
FRC_DOUT #9
CMU_CLK0 #1
PRS_CH6 #10
PRS_CH7 #9
PRS_CH8 #8
PRS_CH9 #7
ACMP0_O #10
ACMP1_O #10
FRC_DFRAME #8
MODEM_DCLK #10
MODEM_DIN #9
MODEM_DOUT #8
MODEM_ANT0 #7
MODEM_ANT1 #6
24
PB15
TIM1_CC2 #8
TIM1_CC3 #7 LE-
TIM0_OUT0 #10
LETIM0_OUT1 #9
PCNT0_S0IN #10
PCNT0_S1IN #9
US1_CTS #6
US1_RTS #5
LEU0_TX #10
LEU0_RX #9
I2C0_SDA #10
I2C0_SCL #9
BUSDX [ADC0:
APORT4XCH31
ACMP0:
APORT4XCH31
ACMP1:
APORT4XCH31]
25
26
27
28
VREGVSS
VREGSW
VREGVDD
DVDD
Voltage regulator VSS
DCDC regulator switching node
Voltage regulator VDD input
Digital power supply.
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Pin Definitions
QFN32 Pin# and
Name
Pin Alternate Functionality / Description
Pin
#
Pin Name
Analog
Timers
Communication
Radio
Other
Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this
pin.
29
30
DECOUPLE
IOVDD
Digital IO power supply.
US0_TX #15
TIM0_CC0 #15
TIM0_CC1 #14
TIM0_CC2 #13
TIM0_CDTI0 #12
TIM0_CDTI1 #11
TIM0_CDTI2 #10
TIM1_CC0 #15
US0_RX #14
US0_CLK #13
US0_CS #12
US0_CTS #11
US0_RTS #10
US1_TX #15
US1_RX #14
US1_CLK #13
US1_CS #12
US1_CTS #11
US1_RTS #10
LEU0_TX #15
LEU0_RX #14
I2C0_SDA #15
I2C0_SCL #14
BUSAX [ADC0:
APORT1XCH10
ACMP0:
APORT1XCH10
ACMP1:
FRC_DCLK #15
FRC_DOUT #14
CMU_CLK1 #3
PRS_CH0 #12
PRS_CH9 #15
PRS_CH10 #4
PRS_CH11 #3
ACMP0_O #15
ACMP1_O #15
GPIO_EM4WU12
FRC_DFRAME #13
MODEM_DCLK #15
MODEM_DIN #14
MODEM_DOUT #13
MODEM_ANT0 #12
MODEM_ANT1 #11
APORT1XCH10]
31
PC10
TIM1_CC1 #14
TIM1_CC2 #13
BUSBY [ADC0:
APORT2YCH10
ACMP0:
APORT2YCH10
ACMP1:
TIM1_CC3 #12 LE-
TIM0_OUT0 #15
LETIM0_OUT1 #14
PCNT0_S0IN #15
PCNT0_S1IN #14
APORT2YCH10]
US0_TX #16
US0_RX #15
US0_CLK #14
US0_CS #13
US0_CTS #12
US0_RTS #11
US1_TX #16
US1_RX #15
US1_CLK #14
US1_CS #13
US1_CTS #12
US1_RTS #11
LEU0_TX #16
LEU0_RX #15
I2C0_SDA #16
I2C0_SCL #15
TIM0_CC0 #16
TIM0_CC1 #15
TIM0_CC2 #14
TIM0_CDTI0 #13
TIM0_CDTI1 #12
TIM0_CDTI2 #11
TIM1_CC0 #16
BUSAY [ADC0:
APORT1YCH11
ACMP0:
APORT1YCH11
ACMP1:
FRC_DCLK #16
FRC_DOUT #15
CMU_CLK0 #3
PRS_CH0 #13
PRS_CH9 #16
PRS_CH10 #5
PRS_CH11 #4
ACMP0_O #16
ACMP1_O #16
DBG_SWO #3
FRC_DFRAME #14
MODEM_DCLK #16
MODEM_DIN #15
MODEM_DOUT #14
MODEM_ANT0 #13
MODEM_ANT1 #12
APORT1YCH11]
32
PC11
TIM1_CC1 #15
TIM1_CC2 #14
BUSBX [ADC0:
APORT2XCH11
ACMP0:
APORT2XCH11
ACMP1:
TIM1_CC3 #13 LE-
TIM0_OUT0 #16
LETIM0_OUT1 #15
PCNT0_S0IN #16
PCNT0_S1IN #15
APORT2XCH11]
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Pin Definitions
6.2.1 EFR32FG1 QFN32 2.4 GHz GPIO Overview
The GPIO pins are organized as 16-bit ports indicated by letters A through F, and the individual pins on each port are indicated by a
number from 15 down to 0.
Table 6.4. GPIO Pinout
Port
Pin
15
Pin
14
Pin
13
Pin
12
Pin
11
Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0
10
Port A
Port B
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PA1 PA0
PB13 PB12 PB11
(5V) (5V) (5V)
PB15 PB14
-
-
-
-
PC11 PC10
(5V) (5V)
Port C
-
-
-
-
-
-
-
-
-
-
-
-
PD15 PD14 PD13
(5V) (5V) (5V)
Port D
Port E
Port F
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PF3 PF2 PF1 PF0
(5V) (5V) (5V) (5V)
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Pin Definitions
6.3 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. The following table shows the name of the alter-
nate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.
Table 6.5. Alternate functionality overview
Alternate
LOCATION
12 - 15 16 - 19
Functionality
0 - 3
4 - 7
8 - 11
20 - 23
24 - 27
28 - 31
Description
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15 14: PC9
12: PC7
13: PC8
16: PC11 20: PD12 24: PF0
21: PD13 25: PF1
18: PD10 22: PD14 26: PF2
28: PF4
29: PF5
30: PF6
31: PF7
Analog comparator
ACMP0, digital out-
put.
ACMP0_O
11: PC6
15: PC10 19: PD11 23: PD15 27: PF3
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15 14: PC9
11: PC6
12: PC7
13: PC8
16: PC11 20: PD12 24: PF0
21: PD13 25: PF1
18: PD10 22: PD14 26: PF2
28: PF4
29: PF5
30: PF6
31: PF7
Analog comparator
ACMP1, digital out-
put.
ACMP1_O
15: PC10 19: PD11 23: PD15 27: PF3
0: PA0
Analog to digital
converter ADC0 ex-
ternal reference in-
put negative pin
ADC0_EXTN
ADC0_EXTP
CMU_CLK0
CMU_CLK1
0: PA1
Analog to digital
converter ADC0 ex-
ternal reference in-
put positive pin
0: PA1
Clock Management
Unit, clock output
number 0.
1: PB15
2: PC6
3: PC11
5: PD14
6: PF2
7: PF7
0: PA0
4: PD10
5: PD15
6: PF3
Clock Management
Unit, clock output
number 1.
1: PB14
2: PC7
3: PC10
7: PF6
Debug-interface
Serial Wire clock
input and JTAG
Test Clock.
0: PF0
DBG_SWCLKTCK
Note that this func-
tion is enabled to
the pin out of reset,
and has a built-in
pull down.
Debug-interface
Serial Wire data in-
put / output and
JTAG Test Mode
Select.
0: PF1
DBG_SWDIOTMS
Note that this func-
tion is enabled to
the pin out of reset,
and has a built-in
pull up.
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Pin Definitions
Alternate
LOCATION
12 - 15 16 - 19
Functionality
0 - 3
4 - 7
8 - 11
20 - 23
24 - 27
28 - 31
Description
Debug-interface
Serial Wire viewer
Output.
0: PF2
Note that this func-
tion is not enabled
after reset, and
must be enabled by
software to be
used.
1: PB13
2: PD15
3: PC11
DBG_SWO
Debug-interface
JTAG Test Data In.
0: PF3
Note that this func-
tion is enabled to
pin out of reset,
and has a built-in
pull up.
DBG_TDI
Debug-interface
JTAG Test Data
Out.
0: PF2
DBG_TDO
Note that this func-
tion is enabled to
pin out of reset.
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15 14: PC9
12: PC7
13: PC8
16: PC11 20: PD12 24: PF0
21: PD13 25: PF1
18: PD10 22: PD14 26: PF2
28: PF4
29: PF5
30: PF6
31: PF7
Frame Controller,
Data Sniffer Clock.
FRC_DCLK
11: PC6
15: PC10 19: PD11 23: PD15 27: PF3
0: PA2
1: PA3
2: PA4
3: PA5
4: PB11
5: PB12
6: PB13
7: PB14
8: PB15
9: PC6
10: PC7
11: PC8
12: PC9 16: PD10 20: PD14 24: PF2
13: PC10 17: PD11 21: PD15 25: PF3
28: PF6
29: PF7
30: PA0
31: PA1
Frame Controller,
Data Sniffer Frame
active
FRC_DFRAME
FRC_DOUT
14: PC11 18: PD12 22: PF0
19: PD13 23: PF1
26: PF4
27: PF5
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
20: PD13 24: PF1
17: PD10 21: PD14 25: PF2
28: PF5
29: PF6
30: PF7
31: PA0
Frame Controller,
Data Sniffer Out-
put.
5: PB11
6: PB12
7: PB13
14: PC10 18: PD11 22: PD15 26: PF3
15: PC11 19: PD12 23: PF0 27: PF4
0: PF2
0: PF7
0: PD14
0: PA3
Pin can be used to
wake the system
up from EM4
GPIO_EM4WU0
GPIO_EM4WU1
GPIO_EM4WU4
GPIO_EM4WU8
Pin can be used to
wake the system
up from EM4
Pin can be used to
wake the system
up from EM4
Pin can be used to
wake the system
up from EM4
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Pin Definitions
Alternate
LOCATION
12 - 15 16 - 19
Functionality
0 - 3
4 - 7
8 - 11
20 - 23
24 - 27
28 - 31
Description
0: PB13
Pin can be used to
wake the system
up from EM4
GPIO_EM4WU9
GPIO_EM4WU12
I2C0_SCL
0: PC10
Pin can be used to
wake the system
up from EM4
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
20: PD13 24: PF1
17: PD10 21: PD14 25: PF2
28: PF5
29: PF6
30: PF7
31: PA0
5: PB11
6: PB12
7: PB13
I2C0 Serial Clock
Line input / output.
14: PC10 18: PD11 22: PD15 26: PF3
15: PC11 19: PD12 23: PF0 27: PF4
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15 14: PC9
12: PC7
13: PC8
16: PC11 20: PD12 24: PF0
21: PD13 25: PF1
18: PD10 22: PD14 26: PF2
28: PF4
29: PF5
30: PF6
31: PF7
I2C0 Serial Data in-
put / output.
I2C0_SDA
11: PC6
15: PC10 19: PD11 23: PD15 27: PF3
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15 14: PC9
12: PC7
13: PC8
16: PC11 20: PD12 24: PF0
21: PD13 25: PF1
18: PD10 22: PD14 26: PF2
28: PF4
29: PF5
30: PF6
31: PF7
Low Energy Timer
LETIM0, output
channel 0.
LETIM0_OUT0
LETIM0_OUT1
LEU0_RX
11: PC6
15: PC10 19: PD11 23: PD15 27: PF3
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
20: PD13 24: PF1
17: PD10 21: PD14 25: PF2
28: PF5
29: PF6
30: PF7
31: PA0
Low Energy Timer
LETIM0, output
channel 1.
5: PB11
6: PB12
7: PB13
14: PC10 18: PD11 22: PD15 26: PF3
15: PC11 19: PD12 23: PF0 27: PF4
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
20: PD13 24: PF1
17: PD10 21: PD14 25: PF2
28: PF5
29: PF6
30: PF7
31: PA0
5: PB11
6: PB12
7: PB13
LEUART0 Receive
input.
14: PC10 18: PD11 22: PD15 26: PF3
15: PC11 19: PD12 23: PF0 27: PF4
LEUART0 Transmit
output. Also used
as receive input in
half duplex commu-
nication.
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15 14: PC9
12: PC7
13: PC8
16: PC11 20: PD12 24: PF0
21: PD13 25: PF1
18: PD10 22: PD14 26: PF2
28: PF4
29: PF5
30: PF6
31: PF7
LEU0_TX
11: PC6
15: PC10 19: PD11 23: PD15 27: PF3
Low Frequency
Crystal (typically
32.768 kHz) nega-
tive pin. Also used
as an optional ex-
ternal clock input
pin.
0: PB14
0: PB15
LFXTAL_N
Low Frequency
Crystal (typically
32.768 kHz) posi-
tive pin.
LFXTAL_P
0: PA3
1: PA4
2: PA5
3: PB11
4: PB12
5: PB13
6: PB14
7: PB15
8: PC6
9: PC7
10: PC8
11: PC9
12: PC10 16: PD11 20: PD15 24: PF3
28: PF7
29: PA0
30: PA1
31: PA2
MODEM antenna
control output 0,
used for antenna
diversity.
13: PC11 17: PD12 21: PF0
18: PD13 22: PF1
15: PD10 19: PD14 23: PF2
25: PF4
26: PF5
27: PF6
MODEM_ANT0
MODEM_ANT1
0: PA4
1: PA5
2: PB11
3: PB12
4: PB13
5: PB14
6: PB15
7: PC6
8: PC7
9: PC8
10: PC9
12: PC11 16: PD12 20: PF0
17: PD13 21: PF1
14: PD10 18: PD14 22: PF2
24: PF4
25: PF5
26: PF6
27: PF7
28: PA0
29: PA1
30: PA2
31: PA3
MODEM antenna
control output 1,
used for antenna
diversity.
11: PC10 15: PD11 19: PD15 23: PF3
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Preliminary Rev. 0.9 | 73
EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Pin Definitions
Alternate
LOCATION
12 - 15 16 - 19
Functionality
0 - 3
4 - 7
8 - 11
20 - 23
24 - 27
28 - 31
Description
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15 14: PC9
12: PC7
13: PC8
16: PC11 20: PD12 24: PF0
21: PD13 25: PF1
18: PD10 22: PD14 26: PF2
28: PF4
29: PF5
30: PF6
31: PF7
MODEM data clock
out.
MODEM_DCLK
MODEM_DIN
MODEM_DOUT
PCNT0_S0IN
PCNT0_S1IN
PRS_CH0
11: PC6
15: PC10 19: PD11 23: PD15 27: PF3
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
20: PD13 24: PF1
17: PD10 21: PD14 25: PF2
28: PF5
29: PF6
30: PF7
31: PA0
5: PB11
6: PB12
7: PB13
MODEM data in.
MODEM data out.
14: PC10 18: PD11 22: PD15 26: PF3
15: PC11 19: PD12 23: PF0 27: PF4
0: PA2
1: PA3
2: PA4
3: PA5
4: PB11
5: PB12
6: PB13
7: PB14
8: PB15
9: PC6
10: PC7
11: PC8
12: PC9 16: PD10 20: PD14 24: PF2
13: PC10 17: PD11 21: PD15 25: PF3
14: PC11 18: PD12 22: PF0
19: PD13 23: PF1
28: PF6
29: PF7
30: PA0
31: PA1
26: PF4
27: PF5
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15 14: PC9
12: PC7
13: PC8
16: PC11 20: PD12 24: PF0
21: PD13 25: PF1
18: PD10 22: PD14 26: PF2
28: PF4
29: PF5
30: PF6
31: PF7
Pulse Counter
PCNT0 input num-
ber 0.
11: PC6
15: PC10 19: PD11 23: PD15 27: PF3
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
20: PD13 24: PF1
17: PD10 21: PD14 25: PF2
28: PF5
29: PF6
30: PF7
31: PA0
Pulse Counter
PCNT0 input num-
ber 1.
5: PB11
6: PB12
7: PB13
14: PC10 18: PD11 22: PD15 26: PF3
15: PC11 19: PD12 23: PF0
27: PF4
0: PF0
1: PF1
2: PF2
3: PF3
4: PF4
5: PF5
6: PF6
7: PF7
8: PC6
9: PC7
10: PC8
11: PC9
12: PC10
13: PC11
Peripheral Reflex
System PRS, chan-
nel 0.
0: PF1
1: PF2
2: PF3
3: PF4
4: PF5
5: PF6
6: PF7
7: PF0
Peripheral Reflex
System PRS, chan-
nel 1.
PRS_CH1
0: PF2
1: PF3
2: PF4
3: PF5
4: PF6
5: PF7
6: PF0
7: PF1
Peripheral Reflex
System PRS, chan-
nel 2.
PRS_CH2
0: PF3
1: PF4
2: PF5
3: PF6
4: PF7
5: PF0
6: PF1
7: PF2
12: PD13
13: PD14
10: PD11 14: PD15
11: PD12
Peripheral Reflex
System PRS, chan-
nel 3.
9: PD10
PRS_CH3
4: PD13
5: PD14
6: PD15
Peripheral Reflex
System PRS, chan-
nel 4.
1: PD10
2: PD11
3: PD12
PRS_CH4
0: PD10
1: PD11
2: PD12
3: PD13
4: PD14
5: PD15
Peripheral Reflex
System PRS, chan-
nel 5.
PRS_CH5
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15 14: PD12
15: PD13
12: PD10 16: PD14
13: PD11 17: PD15
Peripheral Reflex
System PRS, chan-
nel 6.
PRS_CH6
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
8: PB14
9: PB15
10: PA0
Peripheral Reflex
System PRS, chan-
nel 7.
5: PB11
6: PB12
7: PB13
PRS_CH7
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Preliminary Rev. 0.9 | 74
EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0 - 3
4 - 7
8 - 11
12 - 15
16 - 19
20 - 23
24 - 27
28 - 31
Description
0: PA2
1: PA3
2: PA4
3: PA5
4: PB11
5: PB12
6: PB13
7: PB14
8: PB15
9: PA0
10: PA1
Peripheral Reflex
System PRS, chan-
nel 8.
PRS_CH8
PRS_CH9
PRS_CH10
PRS_CH11
TIM0_CC0
TIM0_CC1
TIM0_CC2
TIM0_CDTI0
TIM0_CDTI1
TIM0_CDTI2
TIM1_CC0
TIM1_CC1
TIM1_CC2
0: PA3
1: PA4
2: PA5
3: PB11
4: PB12
5: PB13
6: PB14
7: PB15
8: PA0
9: PA1
10: PA2
11: PC6
12: PC7
13: PC8
14: PC9
15: PC10
16: PC11
Peripheral Reflex
System PRS, chan-
nel 9.
0: PC6
1: PC7
2: PC8
3: PC9
4: PC10
5: PC11
Peripheral Reflex
System PRS, chan-
nel 10.
0: PC7
1: PC8
2: PC9
3: PC10
4: PC11
5: PC6
Peripheral Reflex
System PRS, chan-
nel 11.
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15 14: PC9
12: PC7
13: PC8
16: PC11 20: PD12 24: PF0
21: PD13 25: PF1
18: PD10 22: PD14 26: PF2
28: PF4
29: PF5
30: PF6
31: PF7
Timer 0 Capture
Compare input /
output channel 0.
11: PC6
15: PC10 19: PD11 23: PD15 27: PF3
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
20: PD13 24: PF1
28: PF5
29: PF6
30: PF7
31: PA0
Timer 0 Capture
Compare input /
output channel 1.
5: PB11
6: PB12
7: PB13
17: PD10 21: PD14 25: PF2
14: PC10 18: PD11 22: PD15 26: PF3
15: PC11 19: PD12 23: PF0 27: PF4
0: PA2
1: PA3
2: PA4
3: PA5
4: PB11
5: PB12
6: PB13
7: PB14
8: PB15
9: PC6
10: PC7
11: PC8
12: PC9 16: PD10 20: PD14 24: PF2
13: PC10 17: PD11 21: PD15 25: PF3
14: PC11 18: PD12 22: PF0
19: PD13 23: PF1
28: PF6
29: PF7
30: PA0
31: PA1
Timer 0 Capture
Compare input /
output channel 2.
26: PF4
27: PF5
0: PA3
1: PA4
2: PA5
3: PB11
4: PB12
5: PB13
6: PB14
7: PB15
8: PC6
9: PC7
10: PC8
11: PC9
12: PC10 16: PD11 20: PD15 24: PF3
13: PC11 17: PD12 21: PF0
18: PD13 22: PF1
28: PF7
29: PA0
30: PA1
31: PA2
Timer 0 Compli-
mentary Dead Time
Insertion channel 0.
25: PF4
26: PF5
27: PF6
15: PD10 19: PD14 23: PF2
0: PA4
1: PA5
2: PB11
3: PB12
4: PB13
5: PB14
6: PB15
7: PC6
8: PC7
9: PC8
10: PC9
12: PC11 16: PD12 20: PF0
17: PD13 21: PF1
14: PD10 18: PD14 22: PF2
24: PF4
25: PF5
26: PF6
27: PF7
28: PA0
29: PA1
30: PA2
31: PA3
Timer 0 Compli-
mentary Dead Time
Insertion channel 1.
11: PC10 15: PD11 19: PD15 23: PF3
0: PA5
4: PB14
5: PB15
6: PC6
7: PC7
8: PC8
9: PC9
16: PD13 20: PF1
24: PF5
25: PF6
26: PF7
27: PA0
28: PA1
29: PA2
30: PA3
31: PA4
Timer 0 Compli-
mentary Dead Time
Insertion channel 2.
1: PB11
2: PB12
3: PB13
13: PD10 17: PD14 21: PF2
10: PC10 14: PD11 18: PD15 22: PF3
11: PC11 15: PD12 19: PF0 23: PF4
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15 14: PC9
12: PC7
13: PC8
16: PC11 20: PD12 24: PF0
21: PD13 25: PF1
18: PD10 22: PD14 26: PF2
28: PF4
29: PF5
30: PF6
31: PF7
Timer 1 Capture
Compare input /
output channel 0.
11: PC6
15: PC10 19: PD11 23: PD15 27: PF3
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
20: PD13 24: PF1
28: PF5
29: PF6
30: PF7
31: PA0
Timer 1 Capture
Compare input /
output channel 1.
5: PB11
6: PB12
7: PB13
17: PD10 21: PD14 25: PF2
14: PC10 18: PD11 22: PD15 26: PF3
15: PC11 19: PD12 23: PF0 27: PF4
0: PA2
1: PA3
2: PA4
3: PA5
4: PB11
5: PB12
6: PB13
7: PB14
8: PB15
9: PC6
10: PC7
11: PC8
12: PC9 16: PD10 20: PD14 24: PF2
13: PC10 17: PD11 21: PD15 25: PF3
14: PC11 18: PD12 22: PF0
19: PD13 23: PF1
28: PF6
29: PF7
30: PA0
31: PA1
Timer 1 Capture
Compare input /
output channel 2.
26: PF4
27: PF5
silabs.com | Smart. Connected. Energy-friendly.
Preliminary Rev. 0.9 | 75
EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Pin Definitions
Alternate
LOCATION
12 - 15 16 - 19
12: PC10 16: PD11 20: PD15 24: PF3
Functionality
0 - 3
4 - 7
8 - 11
20 - 23
24 - 27
28 - 31
Description
0: PA3
1: PA4
2: PA5
3: PB11
4: PB12
5: PB13
6: PB14
7: PB15
8: PC6
9: PC7
10: PC8
11: PC9
28: PF7
29: PA0
30: PA1
31: PA2
Timer 1 Capture
Compare input /
output channel 3.
13: PC11 17: PD12 21: PF0
18: PD13 22: PF1
15: PD10 19: PD14 23: PF2
25: PF4
26: PF5
27: PF6
TIM1_CC3
US0_CLK
US0_CS
0: PA2
1: PA3
2: PA4
3: PA5
4: PB11
5: PB12
6: PB13
7: PB14
8: PB15
9: PC6
10: PC7
11: PC8
12: PC9
16: PD10 20: PD14 24: PF2
28: PF6
29: PF7
30: PA0
31: PA1
13: PC10 17: PD11 21: PD15 25: PF3
USART0 clock in-
put / output.
14: PC11 18: PD12 22: PF0
19: PD13 23: PF1
26: PF4
27: PF5
0: PA3
1: PA4
2: PA5
3: PB11
4: PB12
5: PB13
6: PB14
7: PB15
8: PC6
9: PC7
10: PC8
11: PC9
12: PC10 16: PD11 20: PD15 24: PF3
28: PF7
29: PA0
30: PA1
31: PA2
13: PC11 17: PD12 21: PF0
18: PD13 22: PF1
15: PD10 19: PD14 23: PF2
25: PF4
26: PF5
27: PF6
USART0 chip se-
lect input / output.
0: PA4
1: PA5
2: PB11
3: PB12
4: PB13
5: PB14
6: PB15
7: PC6
8: PC7
9: PC8
10: PC9
12: PC11 16: PD12 20: PF0
17: PD13 21: PF1
14: PD10 18: PD14 22: PF2
24: PF4
25: PF5
26: PF6
27: PF7
28: PA0
29: PA1
30: PA2
31: PA3
USART0 Clear To
Send hardware
flow control input.
US0_CTS
US0_RTS
11: PC10 15: PD11 19: PD15 23: PF3
0: PA5
4: PB14
5: PB15
6: PC6
7: PC7
8: PC8
9: PC9
16: PD13 20: PF1
13: PD10 17: PD14 21: PF2
24: PF5
25: PF6
26: PF7
27: PA0
28: PA1
29: PA2
30: PA3
31: PA4
USART0 Request
To Send hardware
flow control output.
1: PB11
2: PB12
3: PB13
10: PC10 14: PD11 18: PD15 22: PF3
11: PC11 15: PD12 19: PF0 23: PF4
USART0 Asynchro-
nous Receive.
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
20: PD13 24: PF1
17: PD10 21: PD14 25: PF2
28: PF5
29: PF6
30: PF7
31: PA0
5: PB11
6: PB12
7: PB13
USART0 Synchro-
nous mode Master
Input / Slave Out-
put (MISO).
US0_RX
14: PC10 18: PD11 22: PD15 26: PF3
15: PC11 19: PD12 23: PF0 27: PF4
USART0 Asynchro-
nous Transmit. Al-
so used as receive
input in half duplex
communication.
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15 14: PC9
12: PC7
13: PC8
16: PC11 20: PD12 24: PF0
21: PD13 25: PF1
18: PD10 22: PD14 26: PF2
28: PF4
29: PF5
30: PF6
31: PF7
US0_TX
USART0 Synchro-
nous mode Master
Output / Slave In-
put (MOSI).
11: PC6
15: PC10 19: PD11 23: PD15 27: PF3
0: PA2
1: PA3
2: PA4
3: PA5
4: PB11
5: PB12
6: PB13
7: PB14
8: PB15
9: PC6
10: PC7
11: PC8
12: PC9
16: PD10 20: PD14 24: PF2
28: PF6
29: PF7
30: PA0
31: PA1
13: PC10 17: PD11 21: PD15 25: PF3
14: PC11 18: PD12 22: PF0
19: PD13 23: PF1
USART1 clock in-
put / output.
US1_CLK
US1_CS
26: PF4
27: PF5
0: PA3
1: PA4
2: PA5
3: PB11
4: PB12
5: PB13
6: PB14
7: PB15
8: PC6
9: PC7
10: PC8
11: PC9
12: PC10 16: PD11 20: PD15 24: PF3
13: PC11 17: PD12 21: PF0
18: PD13 22: PF1
28: PF7
29: PA0
30: PA1
31: PA2
25: PF4
26: PF5
27: PF6
USART1 chip se-
lect input / output.
15: PD10 19: PD14 23: PF2
0: PA4
1: PA5
2: PB11
3: PB12
4: PB13
5: PB14
6: PB15
7: PC6
8: PC7
9: PC8
10: PC9
12: PC11 16: PD12 20: PF0
17: PD13 21: PF1
14: PD10 18: PD14 22: PF2
24: PF4
25: PF5
26: PF6
27: PF7
28: PA0
29: PA1
30: PA2
31: PA3
USART1 Clear To
Send hardware
flow control input.
US1_CTS
US1_RTS
11: PC10 15: PD11 19: PD15 23: PF3
0: PA5
4: PB14
5: PB15
6: PC6
7: PC7
8: PC8
9: PC9
16: PD13 20: PF1
13: PD10 17: PD14 21: PF2
24: PF5
25: PF6
26: PF7
27: PA0
28: PA1
29: PA2
30: PA3
31: PA4
USART1 Request
To Send hardware
flow control output.
1: PB11
2: PB12
3: PB13
10: PC10 14: PD11 18: PD15 22: PF3
11: PC11 15: PD12 19: PF0 23: PF4
silabs.com | Smart. Connected. Energy-friendly.
Preliminary Rev. 0.9 | 76
EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Pin Definitions
Alternate
LOCATION
12 - 15 16 - 19
Functionality
0 - 3
4 - 7
8 - 11
20 - 23
24 - 27
28 - 31
Description
USART1 Asynchro-
nous Receive.
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
20: PD13 24: PF1
17: PD10 21: PD14 25: PF2
28: PF5
29: PF6
30: PF7
31: PA0
5: PB11
6: PB12
7: PB13
USART1 Synchro-
nous mode Master
Input / Slave Out-
put (MISO).
US1_RX
14: PC10 18: PD11 22: PD15 26: PF3
15: PC11 19: PD12 23: PF0 27: PF4
USART1 Asynchro-
nous Transmit. Al-
so used as receive
input in half duplex
communication.
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15 14: PC9
11: PC6
12: PC7
13: PC8
16: PC11 20: PD12 24: PF0
21: PD13 25: PF1
18: PD10 22: PD14 26: PF2
28: PF4
29: PF5
30: PF6
31: PF7
US1_TX
USART1 Synchro-
nous mode Master
Output / Slave In-
put (MOSI).
15: PC10 19: PD11 23: PD15 27: PF3
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Pin Definitions
6.4 Analog Port (APORT)
The Analog Port (APORT) is an infrastructure used to connect chip pins with on-chip analog clients such as analog comparators, ADCs,
and DACs. The APORT consists of wires, switches, and control needed to configurably implement the routes. Please see the device
Reference Manual for a complete description.
PC6
PC8
BUSAX
PC10
PF0
PF2
PF4
PF6
BUSBY
PC7
PC9
BUSAY
PC11
PF1
PF3
PF5
PF7
BUSBX
PD10
PD12
BUSCX
PD14
PA0
PA2
PA4
PB12
PB14
BUSDY
PD11
PD13
BUSCY
PD15
PA1
PA3
PA5
PB11
PB13
PB15
BUSDX
1X1Y2X2Y3X3Y4X4Y
ACMP0
1X1Y2X2Y3X3Y4X4Y
ACMP1
1X1Y2X2Y3X3Y4X4Y
ADC0
1X1Y
IDAC0
Figure 6.3. EFR32FG1 APORT
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Pin Definitions
Table 6.6. APORT Client Map
Analog Module
Analog Module Channel
Shared Bus
Pin
ACMP0
ACMP0
ACMP0
ACMP0
APORT1XCH6
APORT1XCH8
APORT1XCH10
APORT1XCH16
APORT1XCH18
APORT1XCH20
APORT1XCH22
APORT1YCH7
APORT1YCH9
APORT1YCH11
APORT1YCH17
APORT1YCH19
APORT1YCH21
APORT1YCH23
APORT2XCH7
APORT2XCH9
APORT2XCH11
APORT2XCH17
APORT2XCH19
APORT2XCH21
APORT2XCH23
APORT2YCH6
APORT2YCH8
APORT2YCH10
APORT2YCH16
APORT2YCH18
APORT2YCH20
APORT2YCH22
BUSAX
BUSAY
BUSBX
BUSBY
PC6
PC8
PC10
PF0
PF2
PF4
PF6
PC7
PC9
PC11
PF1
PF3
PF5
PF7
PC7
PC9
PC11
PF1
PF3
PF5
PF7
PC6
PC8
PC10
PF0
PF2
PF4
PF6
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Pin Definitions
Analog Module
Analog Module Channel
APORT3XCH2
APORT3XCH4
APORT3XCH6
APORT3XCH8
APORT3XCH10
APORT3XCH12
APORT3XCH28
APORT3XCH30
APORT3YCH3
APORT3YCH5
APORT3YCH7
APORT3YCH9
APORT3YCH11
APORT3YCH13
APORT3YCH27
APORT3YCH29
APORT3YCH31
APORT4XCH3
APORT4XCH5
APORT4XCH7
APORT4XCH9
APORT4XCH11
APORT4XCH13
APORT4XCH27
APORT4XCH29
APORT4XCH31
APORT4YCH2
APORT4YCH4
APORT4YCH6
APORT4YCH8
APORT4YCH10
APORT4YCH12
APORT4YCH28
APORT4YCH30
Shared Bus
Pin
ACMP0
BUSCX
PD10
PD12
PD14
PA0
PA2
PA4
PB12
PB14
PD11
PD13
PD15
PA1
ACMP0
BUSCY
PA3
PA5
PB11
PB13
PB15
PD11
PD13
PD15
PA1
ACMP0
BUSDX
PA3
PA5
PB11
PB13
PB15
PD10
PD12
PD14
PA0
ACMP0
BUSDY
PA2
PA4
PB12
PB14
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Pin Definitions
Analog Module
Analog Module Channel
APORT1XCH6
APORT1XCH8
APORT1XCH10
APORT1XCH16
APORT1XCH18
APORT1XCH20
APORT1XCH22
APORT1YCH7
APORT1YCH9
APORT1YCH11
APORT1YCH17
APORT1YCH19
APORT1YCH21
APORT1YCH23
APORT2XCH7
APORT2XCH9
APORT2XCH11
APORT2XCH17
APORT2XCH19
APORT2XCH21
APORT2XCH23
APORT2YCH6
APORT2YCH8
APORT2YCH10
APORT2YCH16
APORT2YCH18
APORT2YCH20
APORT2YCH22
APORT3XCH2
APORT3XCH4
APORT3XCH6
APORT3XCH8
APORT3XCH10
APORT3XCH12
APORT3XCH28
APORT3XCH30
Shared Bus
Pin
ACMP1
ACMP1
ACMP1
ACMP1
ACMP1
BUSAX
BUSAY
BUSBX
BUSBY
BUSCX
PC6
PC8
PC10
PF0
PF2
PF4
PF6
PC7
PC9
PC11
PF1
PF3
PF5
PF7
PC7
PC9
PC11
PF1
PF3
PF5
PF7
PC6
PC8
PC10
PF0
PF2
PF4
PF6
PD10
PD12
PD14
PA0
PA2
PA4
PB12
PB14
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Pin Definitions
Analog Module
Analog Module Channel
APORT3YCH3
APORT3YCH5
APORT3YCH7
APORT3YCH9
APORT3YCH11
APORT3YCH13
APORT3YCH27
APORT3YCH29
APORT3YCH31
APORT4XCH3
APORT4XCH5
APORT4XCH7
APORT4XCH9
APORT4XCH11
APORT4XCH13
APORT4XCH27
APORT4XCH29
APORT4XCH31
APORT4YCH2
APORT4YCH4
APORT4YCH6
APORT4YCH8
APORT4YCH10
APORT4YCH12
APORT4YCH28
APORT4YCH30
APORT1XCH6
APORT1XCH8
APORT1XCH10
APORT1XCH16
APORT1XCH18
APORT1XCH20
APORT1XCH22
Shared Bus
Pin
ACMP1
BUSCY
PD11
PD13
PD15
PA1
PA3
PA5
PB11
PB13
PB15
PD11
PD13
PD15
PA1
ACMP1
BUSDX
PA3
PA5
PB11
PB13
PB15
PD10
PD12
PD14
PA0
ACMP1
BUSDY
PA2
PA4
PB12
PB14
PC6
ADC0
BUSAX
PC8
PC10
PF0
PF2
PF4
PF6
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Pin Definitions
Analog Module
Analog Module Channel
APORT1YCH7
APORT1YCH9
APORT1YCH11
APORT1YCH17
APORT1YCH19
APORT1YCH21
APORT1YCH23
APORT2XCH7
APORT2XCH9
APORT2XCH11
APORT2XCH17
APORT2XCH19
APORT2XCH21
APORT2XCH23
APORT2YCH6
APORT2YCH8
APORT2YCH10
APORT2YCH16
APORT2YCH18
APORT2YCH20
APORT2YCH22
APORT3XCH2
APORT3XCH4
APORT3XCH6
APORT3XCH8
APORT3XCH10
APORT3XCH12
APORT3XCH28
APORT3XCH30
Shared Bus
Pin
ADC0
ADC0
ADC0
ADC0
BUSAY
BUSBX
BUSBY
BUSCX
PC7
PC9
PC11
PF1
PF3
PF5
PF7
PC7
PC9
PC11
PF1
PF3
PF5
PF7
PC6
PC8
PC10
PF0
PF2
PF4
PF6
PD10
PD12
PD14
PA0
PA2
PA4
PB12
PB14
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Pin Definitions
Analog Module
Analog Module Channel
APORT3YCH3
APORT3YCH5
APORT3YCH7
APORT3YCH9
APORT3YCH11
APORT3YCH13
APORT3YCH27
APORT3YCH29
APORT3YCH31
APORT4XCH3
APORT4XCH5
APORT4XCH7
APORT4XCH9
APORT4XCH11
APORT4XCH13
APORT4XCH27
APORT4XCH29
APORT4XCH31
APORT4YCH2
APORT4YCH4
APORT4YCH6
APORT4YCH8
APORT4YCH10
APORT4YCH12
APORT4YCH28
APORT4YCH30
APORT1XCH2
APORT1XCH4
APORT1XCH6
APORT1XCH8
APORT1XCH10
APORT1XCH12
APORT1XCH28
APORT1XCH30
Shared Bus
Pin
ADC0
BUSCY
PD11
PD13
PD15
PA1
PA3
PA5
PB11
PB13
PB15
PD11
PD13
PD15
PA1
ADC0
BUSDX
PA3
PA5
PB11
PB13
PB15
PD10
PD12
PD14
PA0
ADC0
BUSDY
PA2
PA4
PB12
PB14
PD10
PD12
PD14
PA0
IDAC0
BUSCX
PA2
PA4
PB12
PB14
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Pin Definitions
Analog Module
Analog Module Channel
APORT1YCH3
Shared Bus
Pin
IDAC0
BUSCY
PD11
PD13
PD15
PA1
APORT1YCH5
APORT1YCH7
APORT1YCH9
APORT1YCH11
APORT1YCH13
APORT1YCH27
APORT1YCH29
APORT1YCH31
PA3
PA5
PB11
PB13
PB15
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
QFN48 Package Specifications
7. QFN48 Package Specifications
7.1 QFN48 Package Dimensions
Figure 7.1. QFN48 Package Drawing
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
QFN48 Package Specifications
Table 7.1. QFN48 Package Dimensions
Dimension
Min
0.80
0.00
Typ
0.85
Max
0.90
0.05
A
A1
A3
b
0.02
0.20 REF
0.25
0.18
6.90
6.90
4.60
4.60
0.30
7.10
7.10
4.80
4.80
D
7.00
E
7.00
D2
E2
e
4.70
4.70
0.50 BSC
0.40
L
0.30
0.20
0.09
0.50
—
K
—
R
—
0.14
aaa
bbb
ccc
ddd
eee
fff
0.15
0.10
0.10
0.05
0.08
0.10
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220, Variation VKKD-4.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
QFN48 Package Specifications
7.2 QFN48 PCB Land Pattern
Figure 7.2. QFN48 PCB Land Pattern Drawing
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
QFN48 Package Specifications
Table 7.2. QFN48 PCB Land Pattern Dimensions
Dimension
Typ
6.01
6.01
4.70
4.70
0.50
0.26
0.86
S1
S
L1
W1
e
W
L
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size can be 1:1 for all perimeter pads.
7. A 4x4 array of 0.75 mm square openings on a 1.00 mm pitch can be used for the center ground pad.
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
QFN48 Package Specifications
7.3 QFN48 Package Marking
EFR32
PPPPPPPPP
YYWWTTTTTT #
Figure 7.3. QFN48 Package Marking
The package marking consists of:
• PPPPPPPPP – The part number designation.
1. Family Code (B | M | F)
2. G (Gecko)
3. Generation (1)
4. Feature Code (3 | 2 | 1)
5. TRX Code (3 = TXRX | 2= RX | 1 = TX)
6. Band (1 = Sub-GHz | 2 = 2.4 GHz | 3 = Dual-band)
7. Flash (G = 256K | F = 128K | E = 64K | D = 32K)
8. Temperature Grade (G = -40 to 85 | I = -40 to 125)
• YY – The last 2 digits of the assembly year.
• WW – The 2-digit workweek when the device was assembled.
• TTTTTT – A trace or manufacturing code. The first letter is the device revision.
• # – Bootloader revision number.
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
QFN32 Package Specifications
8. QFN32 Package Specifications
8.1 QFN32 Package Dimensions
Figure 8.1. QFN32 Package Drawing
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
QFN32 Package Specifications
Table 8.1. QFN32 Package Dimensions
Dimension
Min
0.80
0.00
Typ
0.85
Max
0.90
0.05
A
A1
A3
b
0.02
0.20 REF
0.25
0.18
4.90
3.40
0.30
5.10
3.60
D/E
D2/E2
E
5.00
3.50
0.50 BSC
0.40
L
0.30
0.20
0.09
0.50
—
K
—
R
—
0.14
aaa
bbb
ccc
ddd
eee
fff
0.15
0.10
0.10
0.05
0.08
0.10
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220, Variation VKKD-4.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
QFN32 Package Specifications
8.2 QFN32 PCB Land Pattern
Figure 8.2. QFN32 PCB Land Pattern Drawing
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
QFN32 Package Specifications
Table 8.2. QFN32 PCB Land Pattern Dimensions
Dimension
Typ
4.01
4.01
3.50
3.50
0.50
0.26
0.86
S1
S
L1
W1
e
W
L
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size can be 1:1 for all perimeter pads.
7. A 3x3 array of 0.85 mm square openings on a 1.00 mm pitch can be used for the center ground pad.
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
QFN32 Package Specifications
8.3 QFN32 Package Marking
EFR32
PPPPPPPPP
YYWWTTTTTT
Figure 8.3. QFN32 Package Marking
The package marking consists of:
• PPPPPPPPP – The part number designation.
1. Family Code (B | M | F)
2. G (Gecko)
3. Generation (1)
4. Feature Code (3 | 2 | 1)
5. TRX Code (3 = TXRX | 2= RX | 1 = TX)
6. Band (1 = Sub-GHz | 2 = 2.4 GHz | 3 = Dual-band)
7. Flash (G = 256K | F = 128K | E = 64K | D = 32K)
8. Temperature Grade (G = -40 to 85 | I = -40 to 125)
• YY – The last 2 digits of the assembly year.
• WW – The 2-digit workweek when the device was assembled.
• TTTTTT – A trace or manufacturing code. The first letter is the device revision.
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EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Revision History
9. Revision History
9.1 Revision 0.9
2016-01-12
• Updated electrical specifications with latest characterization data.
• Added thermal characteristics table.
• Updated OPN decoder figure to include extended family options.
9.2 Revision 0.81
2015-12-01
• Engineering samples note added to ordering information table.
9.3 Revision 0.8
2015-11-14
• Initial external release.
• Consolidated individual device datasheets into single-family document.
• Re-formatted ordering information table and OPN decoder.
• Updated block diagrams for front page and system overview.
• Removed extraneous sections from DC-DC and wake-on-radio from system overview.
• Updated table formatting for electrical specifications to tech pubs standards.
• Updated electrcal specifications with latest available data.
• Added I2C and USART SPI timing tables.
• Moved DC-DC graph to typical performance curves.
• Updated APORT tables and APORT references to correct nomenclature.
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Preliminary Rev. 0.9 | 96
Table of Contents
1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.2 Radio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.2.1 Antenna Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.2.2 Fractional-N Frequency Synthesizer. . . . . . . . . . . . . . . . . . . . . . 4
3.2.3 Receiver Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2.4 Transmitter Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2.5 Wake on Radio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2.6 RFSENSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2.7 Flexible Frame Handling. . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2.8 Packet and State Trace . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2.9 Data Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2.10 Radio Controller (RAC). . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2.11 Random Number Generator . . . . . . . . . . . . . . . . . . . . . . . . 5
3.3 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.3.1 Energy Management Unit (EMU) . . . . . . . . . . . . . . . . . . . . . . . 6
3.3.2 DC-DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.4 General Purpose Input/Output (GPIO). . . . . . . . . . . . . . . . . . . . . . 6
3.5 Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.5.1 Clock Management Unit (CMU) . . . . . . . . . . . . . . . . . . . . . . . 6
3.5.2 Internal and External Oscillators . . . . . . . . . . . . . . . . . . . . . . . 6
3.6 Counters/Timers and PWM . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.6.1 Timer/Counter (TIMER) . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.6.2 Real Time Counter and Calendar (RTCC) . . . . . . . . . . . . . . . . . . . . 7
3.6.3 Low Energy Timer (LETIMER). . . . . . . . . . . . . . . . . . . . . . . . 7
3.6.4 Ultra Low Power Wake-up Timer (CRYOTIMER) . . . . . . . . . . . . . . . . . 7
3.6.5 Pulse Counter (PCNT) . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.6.6 Watchdog Timer (WDOG) . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.7 Communications and Other Digital Peripherals . . . . . . . . . . . . . . . . . . . 7
3.7.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) . . . . . . . . . . 7
3.7.2 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART) . . . . . . . . . . 8
2
3.7.3 Inter-Integrated Circuit Interface (I C) . . . . . . . . . . . . . . . . . . . . . 8
3.7.4 Peripheral Reflex System (PRS) . . . . . . . . . . . . . . . . . . . . . . . 8
3.8 Security Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.8.1 GPCRC (General Purpose Cyclic Redundancy Check) . . . . . . . . . . . . . . . 8
3.8.2 Crypto Accelerator (CRYPTO). . . . . . . . . . . . . . . . . . . . . . . . 8
3.9 Analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.9.1 Analog Port (APORT) . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.9.2 Analog Comparator (ACMP) . . . . . . . . . . . . . . . . . . . . . . . . 8
3.9.3 Analog to Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . 9
3.9.4 Digital to Analog Current Converter (IDAC) . . . . . . . . . . . . . . . . . . . 9
Table of Contents 97
3.10 Reset Management Unit (RMU) . . . . . . . . . . . . . . . . . . . . . . . 9
3.11 Core and Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.11.1 Processor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.11.2 Memory System Controller (MSC) . . . . . . . . . . . . . . . . . . . . . . 9
3.11.3 Linked Direct Memory Access Controller (LDMA) . . . . . . . . . . . . . . . . . 9
3.12 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.13 Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . .11
4. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .12
4.1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . .13
4.1.2 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . .14
4.1.2.1 General Operating Conditions . . . . . . . . . . . . . . . . . . . . . . .14
4.1.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .15
4.1.4 DC-DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.1.5 Current Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.1.5.1 Current Consumption 1.85 V without DC-DC Converter . . . . . . . . . . . . . .18
4.1.5.2 Current Consumption 3.3 V without DC-DC Converter . . . . . . . . . . . . . . .19
4.1.5.3 Current Consumption 3.3 V using DC-DC Converter . . . . . . . . . . . . . . .20
4.1.5.4 Current Consumption Using Radio . . . . . . . . . . . . . . . . . . . . .21
4.1.6 Wake up times . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.1.7 Brown Out Detector . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4.1.8 Frequency Synthesizer Characteristics . . . . . . . . . . . . . . . . . . . . .22
4.1.9 2.4 GHz RF Transceiver Characteristics . . . . . . . . . . . . . . . . . . . .23
4.1.9.1 RF Transmitter General Characteristics for the 2.4 GHz Band . . . . . . . . . . . .23
4.1.9.2 RF Receiver General Characteristics for the 2.4 GHz Band . . . . . . . . . . . . .24
4.1.9.3 RF Transmitter Characteristics for 1Mbps 2GFSK in the 2.4 GHz Band . . . . . . . . .25
4.1.9.4 RF Receiver Characteristics for 1Mbps 2GFSK in the 2.4 GHz Band . . . . . . . . . .26
4.1.9.5 RF Transmitter Characteristics for 802.15.4 O-QPSK DSSS in the 2.4 GHz Band . . . . . .28
4.1.9.6 RF Receiver Characteristics for 802.15.4 O-QPSK DSSS in the 2.4 GHz Band. . . . . . .29
4.1.10 Modem Features . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
4.1.11 Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
4.1.11.1 LFXO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
4.1.11.2 HFXO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
4.1.11.3 LFRCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
4.1.11.4 HFRCO and AUXHFRCO . . . . . . . . . . . . . . . . . . . . . . . .33
4.1.11.5 ULFRCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
4.1.12 Flash Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . .34
4.1.13 GPIO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
4.1.14 VMON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
4.1.15 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
4.1.16 IDAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
4.1.17 Analog Comparator (ACMP) . . . . . . . . . . . . . . . . . . . . . . . .41
4.1.18 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
4.1.19 USART SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
4.2 Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . .47
5. Typical Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . 48
5.1 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Table of Contents 98
5.2 RF Matching Networks . . . . . . . . . . . . . . . . . . . . . . . . . . .49
5.3 Other Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
6. Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.1 EFR32FG1 QFN48 2.4 GHz Definition . . . . . . . . . . . . . . . . . . . . .50
6.1.1 EFR32FG1 QFN48 2.4 GHz GPIO Overview . . . . . . . . . . . . . . . . . . .62
6.2 EFR32FG1 QFN32 2.4 GHz Definition . . . . . . . . . . . . . . . . . . . . .63
6.2.1 EFR32FG1 QFN32 2.4 GHz GPIO Overview . . . . . . . . . . . . . . . . . . .70
6.3 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . . . .71
6.4 Analog Port (APORT) . . . . . . . . . . . . . . . . . . . . . . . . . . .78
7. QFN48 Package Specifications. . . . . . . . . . . . . . . . . . . . . . . . 86
7.1 QFN48 Package Dimensions. . . . . . . . . . . . . . . . . . . . . . . . .86
7.2 QFN48 PCB Land Pattern. . . . . . . . . . . . . . . . . . . . . . . . . .88
7.3 QFN48 Package Marking . . . . . . . . . . . . . . . . . . . . . . . . . .90
8. QFN32 Package Specifications. . . . . . . . . . . . . . . . . . . . . . . . 91
8.1 QFN32 Package Dimensions. . . . . . . . . . . . . . . . . . . . . . . . .91
8.2 QFN32 PCB Land Pattern. . . . . . . . . . . . . . . . . . . . . . . . . .93
8.3 QFN32 Package Marking . . . . . . . . . . . . . . . . . . . . . . . . . .95
9. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
9.1 Revision 0.9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
9.2 Revision 0.81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
9.3 Revision 0.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table of Contents 99
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device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories
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相关型号:
EFR32FG1P132F64GM48-C0
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