MGM12P02F1024GA-V2_技术文档

MGM12P Mighty Gecko Multi-Protocol

Wireless Mesh Module Data Sheet

The Silicon Labs Mighty Gecko Module (MGM12P) is a fully-inte-

grated, certified module, enabling rapid development of wireless

KEY FEATURES

mesh networking solutions.

®

•

32-bit ARM Cortex -M4 core with 40

MHz maximum operating frequency

Based on the Silicon Labs EFR32MG12 Mighty Gecko SoC, the MGM12P combines an

energy- efficient, multi-protocol wireless SoC with a proven RF/antenna design and in-

dustry leading wireless software stacks. This integration accelerates time-to-market and

saves months of engineering effort and development costs.

• 1 MB of flash and 256 kB of RAM

• ZigBee, Thread, BLE, and multi-protocol

support

• Pin-compatible with MGM111 module

In addition, common software and development tools enable seamless migration from a

module to discrete SoC-based design when the time is right.

• 12-channel Peripheral Reflex System,

Low-Energy Sensor Interface & Multi-

channel Capacitive Sense Interface

MGM12P can be used in a wide variety of applications:

• Integrated PA with up to +17 dBm transmit

power

• IoT Multi-Protocol Devices

• Connected Home

• Lighting

• Robust peripheral set and up to 25 GPIO

• Health and Wellness

• Metering

• Building Automation and Security

Core / Memory

Clock Management

Energy Management

Other

CRYPTO

CRC

High Frequency

Crystal

Oscillator

High Frequency

RC Oscillator

Voltage

Voltage Monitor

Regulator

ARM Cortex^TMM4 processor

Memory

with DSP extensions and FPU

Protection Unit

Auxiliary High

Frequency RC

Oscillator

Low Frequency

RC Oscillator

DC-DC

Power-On Reset

Converter

True Random

Number Generator

Low Frequency

Crystal

Oscillator

Ultra Low

Frequency RC

Oscillator

Flash Program

RAM Memory

Memory

Debug Interface

with ETM

LDMA

Controller

Brown-Out

Detector

SMU

32-bit bus

Peripheral Reflex System

Antenna

Radio Transceiver

Serial

I/O Ports

Timers and Triggers

Analog I/F

Interfaces

Integrated Chip

Antenna

ADC

External

Interrupts

DEMOD

USART

Timer/Counter

Protocol Timer

Analog

Comparator

Low Energy

UART^TM

General

Purpose I/O

Low Energy

Timer

IFADC

AGC

PGA

I

Watchdog Timer

LNA

External Antenna

U.FL Connector

IDAC

RF Frontend

Real Time

Counter and

Calendar

Capacitive Sense

I²C

Pin Reset

Pulse Counter

PA

Frequency

Synthesizer

Q

VDAC

Matching

Low Energy

Sensor Interface

MOD

Pin Wakeup

Cryotimer

Op-Amp

Lowest power mode with peripheral operational:

EM0—Active EM1—Sleep

EM2—Deep Sleep

EM3—Stop

EM4—Hibernate

EM4—Shutoff

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Rev. 1.0

MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Feature List

1. Feature List

The MGM12P highlighted features are listed below.

• Low Power Wireless System-on-Chip.

• Wide selection of MCU peripherals

• 12-bit 1 Msps SAR Analog to Digital Converter (ADC)

• 2×Analog Comparator (ACMP)

High Performance 32-bit 40 MHz ARM Cortex^®-M4 with

DSP instruction and floating-point unit for efficient signal

processing

•

• 2×Digital to Analog Converter (VDAC)

• 3×Operational Amplifier (Opamp)

• 1024 kB flash program memory

• 256 kB RAM data memory

• Digital to Analog Current Converter (IDAC)

• Low-Energy Sensor Interface (LESENSE)

• Multi-channel Capacitive Sense Interface (CSEN)

• 2.4 GHz radio operation

• TX power up to +17 dBm

• Low Energy Consumption

• Up to 25 pins connected to analog channels (APORT)

shared between analog peripherals

• 10.3 mA RX current at 2.4 GHz (1 Mbps GFSK)

• 10.8 mA RX current at 2.4 GHz (250 kbps O-QPSK DSSS)

• 10 mA TX current @ 0 dBm output power at 2.4 GHz

• 70 μA/MHz in Active Mode (EM0)

• Up to 25 General Purpose I/O pins with output state reten-

tion and asynchronous interrupts

• 8 Channel DMA Controller

• 12 Channel Peripheral Reflex System (PRS)

• 2×16-bit Timer/Counter

• 2.1 μA EM2 DeepSleep current (256 kB RAM retention and

RTCC running from LFXO)

• High Receiver Performance

• 3 + 4 Compare/Capture/PWM channels

• 2×32-bit Timer/Counter

• -101 dBm sensitivity @ 250 kbps O-QPSK DSSS

• -105 dBm sensitivity @ 250 kbps O-QPSK DSSS (modules

with LNA)

• 3 + 4 Compare/Capture/PWM channels

• 32-bit Real Time Counter and Calendar

• 16-bit Low Energy Timer for waveform generation

• -95 dBm sensitivity @ 1Mbps 2GFSK

• -101.6 dBm sensitivity @ 1Mbps 2GFSK (modules with

LNA)

• 32-bit Ultra Low Energy Timer/Counter for periodic wake-up

from any Energy Mode

• Supported Modulation Format

• Shaped OQPSK

• 3×16-bit Pulse Counter with asynchronous operation

• 2×Watchdog Timer with dedicated RC oscillator

• 4×Universal Synchronous/Asynchronous Receiver/Trans-

mitter (UART/SPI/SmartCard (ISO 7816)/IrDA/I²S)

• 2-FSK / 4-FSK with fully configurable shaping

• Supported Protocols:

Bluetooth^®Low Energy (Bluetooth 5)

•

Low Energy UART (LEUART^™)

2×I²C interface with SMBus support and address recogni-

tion in EM3 Stop

•

• zigbee

• Thread

• Support for Internet Security

• General Purpose CRC

• True Random Number Generator

• Wide Operating Range

• 1.8 V to 3.8 V single power supply

• -40 °C to 85 °C

• Hardware Cryptographic Acceleration for AES 128/256,

SHA-1, SHA-2 (SHA-224 and SHA-256) and ECC

• WxLxH: 12.9 x 17.8 x 2.3 mm

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Ordering Information

2. Ordering Information

Ordering Code

Description

Max TX

Power

Sensitivity Antenna

(O-QPSK)

Packaging Production Status

MGM12P32F1024GA-V2 Multi-protocol Module +17 dBm -105 dBm

MGM12P32F1024GA-V2R Multi-protocol Module +17 dBm -105 dBm

MGM12P32F1024GE-V2 Multi-protocol Module +17 dBm -105 dBm

MGM12P32F1024GE-V2R Multi-protocol Module +17 dBm -105 dBm

MGM12P22F1024GA-V2 Multi-protocol Module +10 dBm -105 dBm

MGM12P22F1024GA-V2R Multi-protocol Module +10 dBm -105 dBm

MGM12P22F1024GE-V2 Multi-protocol Module +10 dBm -105 dBm

MGM12P22F1024GE-V2R Multi-protocol Module +10 dBm -105 dBm

MGM12P02F1024GA-V2 Multi-protocol Module +10 dBm -101 dBm

MGM12P02F1024GA-V2R Multi-protocol Module +10 dBm -101 dBm

MGM12P02F1024GE-V2 Multi-protocol Module +10 dBm -101 dBm

MGM12P02F1024GE-V2R Multi-protocol Module +10 dBm -101 dBm

Integrated chip an- Cut Reel

tenna

Full Production (certi-

fied)

(100 pcs)

Integrated chip an- Reel

tenna

Full Production (certi-

fied)

(1000 pcs)

External (U.FL)

Cut Reel

(100 pcs)

Reel

Full Production (certi-

fied)

Full Production (certi-

fied)

(1000 pcs)

Integrated chip an- Cut Reel

Full Production (certi-

fied)

tenna

(100 pcs)

Integrated chip an- Reel

Full Production (certi-

fied)

tenna

(1000 pcs)

External (U.FL)

Cut Reel

(100 pcs)

Reel

Full Production (certi-

fied)

Full Production (certi-

fied)

(1000 pcs)

Integrated chip an- Cut Reel

Full Production (certi-

fied)

tenna

(100 pcs)

Integrated chip an- Reel

Full Production (certi-

fied)

tenna

(1000 pcs)

External (U.FL)

Cut Reel

(100 pcs)

Reel

Full Production (certi-

fied)

Full Production (certi-

fied)

(1000 pcs)

SLWRB4304A

MGM12P Radio

Board³

+17 dBm -105 dBm

Integrated chip an- Single Unit Development Board

tenna

Note:

1. IAR license required for zigbee and Thread software development.

2. Bluetooth^®Low Energy regulatory certification pending. Contact sales for availability and certification time lines.

3. Requires Mesh Networking kit SLWSTK6000A or SLWSTK6000B

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Table of Contents

1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

3. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.2 Radio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.2.1 Antenna Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.2.2 Packet and State Trace . . . . . . . . . . . . . . . . . . . . . . . . 8

3.2.3 Random Number Generator . . . . . . . . . . . . . . . . . . . . . . . 8

3.3 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.3.1 Energy Management Unit (EMU) . . . . . . . . . . . . . . . . . . . . .10

3.3.2 DC-DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . .10

3.3.3 Power Domains . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.4 General Purpose Input/Output (GPIO). . . . . . . . . . . . . . . . . . . . . .11

3.5 Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.5.1 Clock Management Unit (CMU) . . . . . . . . . . . . . . . . . . . . . .11

3.5.2 Internal Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.6 Counters/Timers and PWM . . . . . . . . . . . . . . . . . . . . . . . . .12

3.6.1 Timer/Counter (TIMER) . . . . . . . . . . . . . . . . . . . . . . . .12

3.6.2 Wide Timer/Counter (WTIMER) . . . . . . . . . . . . . . . . . . . . . .12

3.6.3 Real Time Counter and Calendar (RTCC) . . . . . . . . . . . . . . . . . .12

3.6.4 Low Energy Timer (LETIMER) . . . . . . . . . . . . . . . . . . . . . .12

3.6.5 Ultra Low Power Wake-up Timer (CRYOTIMER) . . . . . . . . . . . . . . . .12

3.6.6 Pulse Counter (PCNT) . . . . . . . . . . . . . . . . . . . . . . . . .12

3.6.7 Watchdog Timer (WDOG). . . . . . . . . . . . . . . . . . . . . . . .12

3.7 Communications and Other Digital Peripherals . . . . . . . . . . . . . . . . . . .13

3.7.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) . . . . . . . . .13

3.7.2 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART) . . . . . . . . .13

2

3.7.3 Inter-Integrated Circuit Interface (I C) . . . . . . . . . . . . . . . . . . . .13

3.7.4 Peripheral Reflex System (PRS) . . . . . . . . . . . . . . . . . . . . .13

3.7.5 Low Energy Sensor Interface (LESENSE) . . . . . . . . . . . . . . . . . .13

3.8 Security Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

3.8.1 GPCRC (General Purpose Cyclic Redundancy Check) . . . . . . . . . . . . . .13

3.8.2 Crypto Accelerator (CRYPTO) . . . . . . . . . . . . . . . . . . . . . .14

3.8.3 True Random Number Generator (TRNG) . . . . . . . . . . . . . . . . . .14

3.8.4 Security Management Unit (SMU) . . . . . . . . . . . . . . . . . . . . .14

3.9 Analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

3.9.1 Analog Port (APORT) . . . . . . . . . . . . . . . . . . . . . . . . .14

3.9.2 Analog Comparator (ACMP) . . . . . . . . . . . . . . . . . . . . . . .14

3.9.3 Analog to Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . .14

3.9.4 Capacitive Sense (CSEN). . . . . . . . . . . . . . . . . . . . . . . .14

3.9.5 Digital to Analog Current Converter (IDAC) . . . . . . . . . . . . . . . . . .15

3.9.6 Digital to Analog Converter (VDAC) . . . . . . . . . . . . . . . . . . . .15

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3.9.7 Operational Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . .15

3.10 Reset Management Unit (RMU) . . . . . . . . . . . . . . . . . . . . . . .15

3.11 Core and Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

3.11.1 Processor Core . . . . . . . . . . . . . . . . . . . . . . . . . . .15

3.11.2 Memory System Controller (MSC) . . . . . . . . . . . . . . . . . . . .15

3.11.3 Linked Direct Memory Access Controller (LDMA) . . . . . . . . . . . . . . .15

3.12 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

3.13 Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . .18

4. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.1 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .19

4.1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . .19

4.1.2 General Operating Conditions . . . . . . . . . . . . . . . . . . . . . .20

4.1.3 DC-DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . .20

4.1.4 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . .21

4.1.5 Wake Up Times . . . . . . . . . . . . . . . . . . . . . . . . . . .24

4.1.6 Brown Out Detector (BOD) . . . . . . . . . . . . . . . . . . . . . . .25

4.1.7 Frequency Synthesizer. . . . . . . . . . . . . . . . . . . . . . . . .25

4.1.8 2.4 GHz RF Transceiver Characteristics . . . . . . . . . . . . . . . . . . .25

4.1.9 Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

4.1.10 Flash Memory Characteristics . . . . . . . . . . . . . . . . . . . . . .32

4.1.11 General-Purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . .33

4.1.12 Voltage Monitor (VMON). . . . . . . . . . . . . . . . . . . . . . . .34

4.1.13 Analog to Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . .35

4.1.14 Analog Comparator (ACMP) . . . . . . . . . . . . . . . . . . . . . .37

4.1.15 Digital to Analog Converter (VDAC) . . . . . . . . . . . . . . . . . . . .40

4.1.16 Current Digital to Analog Converter (IDAC) . . . . . . . . . . . . . . . . .43

4.1.17 Capacitive Sense (CSEN) . . . . . . . . . . . . . . . . . . . . . . .45

4.1.18 Operational Amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . .47

4.1.19 Pulse Counter (PCNT) . . . . . . . . . . . . . . . . . . . . . . . .50

4.1.20 Analog Port (APORT) . . . . . . . . . . . . . . . . . . . . . . . . .50

4.1.21 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

4.1.22 USART SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

5. Typical Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . 56

5.1 Network Co-Processor (NCP) Application with UART Host . . . . . . . . . . . . . . .56

5.2 Network Co-Processor (NCP) Application with SPI Host. . . . . . . . . . . . . . . .56

5.3 SoC Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

6. Layout Guidelines

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

6.1 Module Placement and Application PCB Layout Guidelines . . . . . . . . . . . . . .58

6.2 Effect of Plastic and Metal Materials . . . . . . . . . . . . . . . . . . . . . .59

6.3 Locating the Module Close to Human Body . . . . . . . . . . . . . . . . . . . .59

6.4 2D Radiation Pattern Plots . . . . . . . . . . . . . . . . . . . . . . . . .60

7. Hardware Design Guidelines

. . . . . . . . . . . . . . . . . . . . . . . .62

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7.1 Power Supply Requirements . . . . . . . . . . . . . . . . . . . . . . . . .62

7.2 Reset Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

7.3 Debug and Firmware Updates . . . . . . . . . . . . . . . . . . . . . . . .62

7.3.1 Programming and Debug Connections . . . . . . . . . . . . . . . . . . .62

7.3.2 Packet Trace Interface (PTI) . . . . . . . . . . . . . . . . . . . . . . .62

8. Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

8.1 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

8.1.1 GPIO Overview . . . . . . . . . . . . . . . . . . . . . . . . . . .65

8.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . . . .66

8.3 Analog Port (APORT) Client Maps . . . . . . . . . . . . . . . . . . . . . . .77

9. Package Specifications

. . . . . . . . . . . . . . . . . . . . . . . . . .86

9.1 MGM12P Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . .86

9.2 MGM12P Module Footprint . . . . . . . . . . . . . . . . . . . . . . . . .87

9.3 MGM12P Recommended PCB Land Pattern . . . . . . . . . . . . . . . . . . .88

9.4 MGM12P Package Marking . . . . . . . . . . . . . . . . . . . . . . . . .89

10. Tape and Reel Specifications . . . . . . . . . . . . . . . . . . . . . . . . 90

10.1 Tape and Reel Specification . . . . . . . . . . . . . . . . . . . . . . . .90

10.2 Reel Material and Dimensions . . . . . . . . . . . . . . . . . . . . . . . .90

10.3 Module Orientation and Tap. . . . . . . . . . . . . . . . . . . . . . . . .91

10.4 Carrier Tape and Cover Tape Information . . . . . . . . . . . . . . . . . . . .92

11. Certifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

11.1 CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

11.2 FCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

11.3 ISEDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

12. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

12.1 Revision 1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

12.2 Revision 0.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

System Overview

3. System Overview

3.1 Introduction

This section provides a brief overview of the MGM12P module architecture including both MCU and RF sub-systems. A detailed func-

tional description of the EFR32MG12 SoC used inside the module is available in the EFR32MG12 Mighty Gecko Datasheet and

EFR32xG12 Wireless Gecko Reference Manual. A block diagram of the EFR32MG12 SoC is shown in the figure below.

Radio Transceiver

Port I/O Configuration

Digital Peripherals

IOVDD

DEMOD

IFADC

AGC

RFSENSE

BALUN

2.4 GHz RF

LETIMER

I

Port A

Drivers

PGA

LNA

PAn

TIMER

CRYOTIMER

PCNT

2G4RF_IOP

2G4RF_ION

PA

Frequency

Synthesizer

Q

Port B

Drivers

PBn

PCn

PDn

PFn

To RF

Frontend

Circuits

MOD

RTC / RTCC

USART

Port

Mapper

Port C

Drivers

LEUART

I2C

Reset

Management

Unit

ARM Cortex-M4 Core

RESETn

Port D

Serial Wire

and ETM

Debug /

1024 KB ISP Flash

Program Memory

CRYPTO

CRC

Drivers

Debug Signals

(shared w/GPIO)

Brown Out /

Power-On

Reset

A

H

B

A

P

B

256 KB RAM

Memory Protection Unit

Floating Point Unit

LDMA Controller

Programming

Port F

Drivers

LESENSE

Energy Management

Analog Peripherals

Port I

Drivers

PAVDD

RFVDD

IOVDD

AVDD

IDAC

Voltage

Monitor

Port J

Drivers

-

+

Watchdog

Timer

PJn

VDAC

DVDD

bypass

Op-Amp

VDD

Internal

Reference

Port K

Drivers

Clock Management

PKn

VREGVDD

VREGSW

DC-DC

Converter

Voltage

Regulator

ULFRCO

AUXHFRCO

LFRCO

12-bit ADC

DECOUPLE

Temp

Sense

LFXTAL_P

LFXTAL_N

HFXTAL_P

HFXTAL_N

LFXO

HFRCO

HFXO

Capacitive

Sense

+

-

Analog Comparator

Figure 3.1. Detailed EFR32MG12 Block Diagram

3.2 Radio

The MGM12P modules feature a highly configurable radio transceiver that supports a wide range of wireless protocols including zigbee,

Thread, and Bluetooth Low Energy.

3.2.1 Antenna Interface

The MGM12P module family includes options for either a high-performance, integrated chip-antenna (MGM12P-GA) or external anten-

na (MGM12P-GE) via a U.FL connector. The table below includes performance specifications for the integrated chip antenna.

Table 3.1. Antenna Efficiency and Peak Gain (MGM12P)

Parameter

Efficiency

Peak gain

With optimal layout Note

-4 dB to -5 dB

1.0 dBi

Antenna efficiency, gain and radiation pattern are highly depend-

ent on the application PCB layout and mechanical design. Refer

to Chapter for PCB layout and antenna integration guidelines for

optimal performance.

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

System Overview

3.2.2 Packet and State Trace

The MGM12P Frame Controller has a packet and state trace unit that provides valuable information during the development phase. It

features:

• Non-intrusive trace of transmit data, receive data and state information

• Data observability on a single-pin UART data output, or on a two-pin SPI data output

• Configurable data output bitrate / baudrate

• Multiplexed transmitted data, received data and state / meta information in a single serial data stream

3.2.3 Random Number Generator

The Frame Controller (FRC) implements a random number generator that uses entropy gathered from noise in the RF receive chain.

The data is suitable for use in cryptographic applications.

Output from the random number generator can be used either directly or as a seed or entropy source for software-based random num-

ber generator algorithms such as Fortuna.

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

System Overview

3.3 Power

The MGM12P has an Energy Management Unit (EMU) and efficient integrated regulators to generate internal supply voltages. Only a

single external supply voltage is required, from which all internal voltages are created. An integrated DC-DC buck regulator is utilized to

further reduce the current consumption.

Figure 3.2. MGM12P Power Block for Modules (+10 dBm)

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

System Overview

Figure 3.3. MGM12P Power Block for Modules (+17 dBm)

3.3.1 Energy Management Unit (EMU)

The Energy Management Unit manages transitions of energy modes in the device. Each energy mode defines which peripherals and

features are available and the amount of current the device consumes. The EMU can also be used to turn off the power to unused RAM

blocks, and it contains control registers for the DC-DC regulator and the Voltage Monitor (VMON). The VMON is used to monitor multi-

ple supply voltages. It has multiple channels which can be programmed individually by the user to determine if a sensed supply has

fallen below a chosen threshold.

3.3.2 DC-DC Converter

The DC-DC buck converter covers a wide range of load currents and provides up to 90% efficiency in energy modes EM0, EM1, EM2,

and EM3. Patented RF noise mitigation allows operation of the DC-DC converter without degrading sensitivity of radio components.

Protection features include programmable current limiting, short-circuit protection, and dead-time protection. The DC-DC converter may

also enter bypass mode when the input voltage is too low for efficient operation. In bypass mode, the DC-DC input supply is internally

connected directly to its output through a low resistance switch. Bypass mode also supports in-rush current limiting to prevent input

supply voltage droops due to excessive output current transients.

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

System Overview

3.3.3 Power Domains

The MGM12P has two peripheral power domains for operation in EM2 and lower. If all of the peripherals in a peripheral power domain

are configured as unused, the power domain for that group will be powered off in the low-power mode, reducing the overall current

consumption of the device.

Table 3.2. Peripheral Power Subdomains

Peripheral Power Domain 1

Peripheral Power Domain 2

ACMP0

ACMP1

PCNT1

PCNT2

CSEN

DAC0

PCNT0

ADC0

LETIMER0

LESENSE

APORT

LEUART0

I2C0

-

I2C1

IDAC

3.4 General Purpose Input/Output (GPIO)

MGM12P has 25 General Purpose Input/Output pins. Each GPIO pin can be individually configured as either an output or input. More

advanced configurations including open-drain, open-source, and glitch-filtering can be configured for each individual GPIO pin. The

GPIO pins can be overridden by peripheral connections, like SPI communication. Each peripheral connection can be routed to several

GPIO pins on the device. The input value of a GPIO pin can be routed through the Peripheral Reflex System to other peripherals. The

GPIO subsystem supports asynchronous external pin interrupts.

3.5 Clocking

3.5.1 Clock Management Unit (CMU)

The Clock Management Unit controls oscillators and clocks in the MGM12P. Individual enabling and disabling of clocks to all peripheral

modules is perfomed by the CMU. The CMU also controls enabling and configuration of the oscillators. A high degree of flexibility al-

lows software to optimize energy consumption in any specific application by minimizing power dissipation in unused peripherals and

oscillators.

3.5.2 Internal Oscillators

The MGM12P fully integrates two crystal oscillators and four RC oscillators, listed below.

• A 38.4MHz high frequency crystal oscillator (HFXO) provides a precise timing reference for the MCU and radio.

• A 32.768 kHz crystal oscillator (LFXO) provides an accurate timing reference for low energy modes.

• An integrated high frequency RC oscillator (HFRCO) is available for the MCU system, when crystal accuracy is not required. The

HFRCO employs fast startup at minimal energy consumption combined with a wide frequency range.

• An integrated auxilliary high frequency RC oscillator (AUXHFRCO) is available for timing the general-purpose ADC and the Serial

Wire debug port with a wide frequency range.

• An integrated low frequency 32.768 kHz RC oscillator (LFRCO) can be used as a timing reference in low energy modes, when crys-

tal accuracy is not required.

• An integrated ultra-low frequency 1 kHz RC oscillator (ULFRCO) is available to provide a timing reference at the lowest energy con-

sumption in low energy modes.

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

System Overview

3.6 Counters/Timers and PWM

3.6.1 Timer/Counter (TIMER)

TIMER peripherals keep track of timing, count events, generate PWM outputs and trigger timed actions in other peripherals through the

PRS system. The core of each TIMER is a 16-bit counter with up to 4 compare/capture channels. Each channel is configurable in one

of three modes. In capture mode, the counter state is stored in a buffer at a selected input event. In compare mode, the channel output

reflects the comparison of the counter to a programmed threshold value. In PWM mode, the TIMER supports generation of pulse-width

modulation (PWM) outputs of arbitrary waveforms defined by the sequence of values written to the compare registers, with optional

dead-time insertion available in timer unit TIMER_0 only.

3.6.2 Wide Timer/Counter (WTIMER)

WTIMER peripherals function just as TIMER peripherals, but are 32 bits wide. They keep track of timing, count events, generate PWM

outputs and trigger timed actions in other peripherals through the PRS system. The core of each WTIMER is a 32-bit counter with up to

4 compare/capture channels. Each channel is configurable in one of three modes. In capture mode, the counter state is stored in a

buffer at a selected input event. In compare mode, the channel output reflects the comparison of the counter to a programmed thresh-

old value. In PWM mode, the WTIMER supports generation of pulse-width modulation (PWM) outputs of arbitrary waveforms defined by

the sequence of values written to the compare registers, with optional dead-time insertion available in timer unit WTIMER_0 only.

3.6.3 Real Time Counter and Calendar (RTCC)

The Real Time Counter and Calendar (RTCC) is a 32-bit counter providing timekeeping in all energy modes. The RTCC includes a

Binary Coded Decimal (BCD) calendar mode for easy time and date keeping. The RTCC can be clocked by any of the on-board oscilla-

tors with the exception of the AUXHFRCO, and it is capable of providing system wake-up at user defined instances. When receiving

frames, the RTCC value can be used for timestamping. The RTCC includes 128 bytes of general purpose data retention, allowing easy

and convenient data storage in all energy modes.

3.6.4 Low Energy Timer (LETIMER)

The unique LETIMER is a 16-bit timer that is available in energy mode EM2 Deep Sleep in addition to EM1 Sleep and EM0 Active. This

allows it to be used for timing and output generation when most of the device is powered down, allowing simple tasks to be performed

while the power consumption of the system is kept at an absolute minimum. The LETIMER can be used to output a variety of wave-

forms with minimal software intervention. The LETIMER is connected to the Real Time Counter and Calendar (RTCC), and can be con-

figured to start counting on compare matches from the RTCC.

3.6.5 Ultra Low Power Wake-up Timer (CRYOTIMER)

The CRYOTIMER is a 32-bit counter that is capable of running in all energy modes. It can be clocked by either the 32.768 kHz crystal

oscillator (LFXO), the 32.768 kHz RC oscillator (LFRCO), or the 1 kHz RC oscillator (ULFRCO). It can provide periodic Wakeup events

and PRS signals which can be used to wake up peripherals from any energy mode. The CRYOTIMER provides a wide range of inter-

rupt periods, facilitating flexible ultra-low energy operation.

3.6.6 Pulse Counter (PCNT)

The Pulse Counter (PCNT) peripheral can be used for counting pulses on a single input or to decode quadrature encoded inputs. The

clock for PCNT is selectable from either an external source on pin PCTNn_S0IN or from an internal timing reference, selectable from

among any of the internal oscillators, except the AUXHFRCO. The module may operate in energy mode EM0 Active, EM1 Sleep, EM2

Deep Sleep, and EM3 Stop.

3.6.7 Watchdog Timer (WDOG)

The watchdog timer can act both as an independent watchdog or as a watchdog synchronous with the CPU clock. It has windowed

monitoring capabilities, and can generate a reset or different interrupts depending on the failure mode of the system. The watchdog can

also monitor autonomous systems driven by PRS.

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System Overview

3.7 Communications and Other Digital Peripherals

3.7.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART)

The Universal Synchronous/Asynchronous Receiver/Transmitter is a flexible serial I/O module. It supports full duplex asynchronous

UART communication with hardware flow control as well as RS-485, SPI, MicroWire and 3-wire. It can also interface with devices

supporting:

• ISO7816 SmartCards

• IrDA

I²S

•

3.7.2 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART)

The unique LEUART^TMprovides two-way UART communication on a strict power budget. Only a 32.768 kHz clock is needed to allow

UART communication up to 9600 baud. The LEUART includes all necessary hardware to make asynchronous serial communication

possible with a minimum of software intervention and energy consumption.

3.7.3 Inter-Integrated Circuit Interface (I²C)

The I²C module provides an interface between the MCU and a serial I²C bus. It is capable of acting as both a master and a slave and

supports multi-master buses. Standard-mode, fast-mode and fast-mode plus speeds are supported, allowing transmission rates from 10

kbit/s up to 1 Mbit/s. Slave arbitration and timeouts are also available, allowing implementation of an SMBus-compliant system. The

interface provided to software by the I²C module allows precise timing control of the transmission process and highly automated trans-

fers. Automatic recognition of slave addresses is provided in active and low energy modes.

3.7.4 Peripheral Reflex System (PRS)

The Peripheral Reflex System provides a communication network between different peripheral modules without software involvement.

Peripheral modules producing Reflex signals are called producers. The PRS routes Reflex signals from producers to consumer periph-

erals which in turn perform actions in response. Edge triggers and other functionality such as simple logic operations (AND, OR, NOT)

can be applied by the PRS to the signals. The PRS allows peripheral to act autonomously without waking the MCU core, saving power.

3.7.5 Low Energy Sensor Interface (LESENSE)

The Low Energy Sensor Interface LESENSE^TMis a highly configurable sensor interface with support for up to 16 individually configura-

ble sensors. By controlling the analog comparators, ADC, and DAC, LESENSE is capable of supporting a wide range of sensors and

measurement schemes, and can for instance measure LC sensors, resistive sensors and capacitive sensors. LESENSE also includes a

programmable finite state machine which enables simple processing of measurement results without CPU intervention. LESENSE is

available in energy mode EM2, in addition to EM0 and EM1, making it ideal for sensor monitoring in applications with a strict energy

budget.

3.8 Security Features

3.8.1 GPCRC (General Purpose Cyclic Redundancy Check)

The GPCRC module implements a Cyclic Redundancy Check (CRC) function. It supports both 32-bit and 16-bit polynomials. The sup-

ported 32-bit polynomial is 0x04C11DB7 (IEEE 802.3), while the 16-bit polynomial can be programmed to any value, depending on the

needs of the application.

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3.8.2 Crypto Accelerator (CRYPTO)

The Crypto Accelerator is a fast and energy-efficient autonomous hardware encryption and decryption accelerator. EFR32 devices sup-

port AES encryption and decryption with 128- or 256-bit keys, ECC over both GF(P) and GF(2m), SHA-1 and SHA-2 (SHA-224 and

SHA-256).

Supported block cipher modes of operation for AES include: ECB, CTR, CBC, PCBC, CFB, OFB, GCM, CBC-MAC, GMAC and CCM.

Supported ECC NIST recommended curves include P-192, P-224, P-256, K-163, K-233, B-163 and B-233.

The CRYPTO is tightly linked to the Radio Buffer Controller (BUFC) enabling fast and efficient autonomous cipher operations on data

buffer content. It allows fast processing of GCM (AES), ECC and SHA with little CPU intervention. CRYPTO also provides trigger

signals for DMA read and write operations.

3.8.3 True Random Number Generator (TRNG)

The TRNG module is a non-deterministic random number generator based on a full hardware solution. The TRNG is validated with

NIST800-22 and AIS-31 test suites as well as being suitable for FIPS 140-2 certification (for the purposes of cryptographic key genera-

tion).

3.8.4 Security Management Unit (SMU)

The Security Management Unit (SMU) allows software to set up fine-grained security for peripheral access, which is not possible in the

Memory Protection Unit (MPU). Peripherals may be secured by hardware on an individual basis, such that only priveleged accesses to

the peripheral's register interface will be allowed. When an access fault occurs, the SMU reports the specific peripheral involved and

can optionally generate an interrupt.

3.9 Analog

3.9.1 Analog Port (APORT)

The Analog Port (APORT) is an analog interconnect matrix allowing access to analog modules on a flexible selection of pins. Each

APORT bus consists of analog switches connected to a common wire. Since many clients can operate differentially, buses are grouped

by X/Y pairs.

3.9.2 Analog Comparator (ACMP)

The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is high-

er. Inputs are selected from among internal references and external pins. The tradeoff between response time and current consumption

is configurable by software. Two 6-bit reference dividers allow for a wide range of internally-programmable reference sources. The

ACMP can also be used to monitor the supply voltage. An interrupt can be generated when the supply falls below or rises above the

programmable threshold.

3.9.3 Analog to Digital Converter (ADC)

The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits at up to 1 Msps. The output

sample resolution is configurable and additional resolution is possible using integrated hardware for averaging over multiple samples.

The ADC includes integrated voltage references and an integrated temperature sensor. Inputs are selectable from a wide range of

sources, including pins configurable as either single-ended or differential.

3.9.4 Capacitive Sense (CSEN)

The CSEN module is a dedicated Capacitive Sensing block for implementing touch-sensitive user interface elements such a switches

and sliders. The CSEN module uses a charge ramping measurement technique, which provides robust sensing even in adverse condi-

tions including radiated noise and moisture. The module can be configured to take measurements on a single port pin or scan through

multiple pins and store results to memory through DMA. Several channels can also be shorted together to measure the combined ca-

pacitance or implement wake-on-touch from very low energy modes. Hardware includes a digital accumulator and an averaging filter,

as well as digital threshold comparators to reduce software overhead.

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3.9.5 Digital to Analog Current Converter (IDAC)

The Digital to Analog Current Converter can source or sink a configurable constant current. This current can be driven on an output pin

or routed to the selected ADC input pin for capacitive sensing. The full-scale current is programmable between 0.05 μA and 64 μA with

several ranges consisting of various step sizes.

3.9.6 Digital to Analog Converter (VDAC)

The Digital to Analog Converter (VDAC) can convert a digital value to an analog output voltage. The VDAC is a fully differential, 500

ksps, 12-bit converter. The opamps are used in conjunction with the VDAC, to provide output buffering. One opamp is used per single-

ended channel, or two opamps are used to provide differential outputs. The VDAC may be used for a number of different applications

such as sensor interfaces or sound output. The VDAC can generate high-resolution analog signals while the MCU is operating at low

frequencies and with low total power consumption. Using DMA and a timer, the VDAC can be used to generate waveforms without any

CPU intervention. The VDAC is available in all energy modes down to and including EM3.

3.9.7 Operational Amplifiers

The opamps are low power amplifiers with a high degree of flexibility targeting a wide variety of standard opamp application areas. With

flexible built-in programming for gain and interconnection they can be configured to support multiple common opamp functions. All pins

are also available externally for filter configurations. Each opamp has a rail to rail input and a rail to rail output. They can be used in

conjunction with the VDAC module or in stand-alone configurations. The opamps save energy, PCB space, and cost as compared with

standalone opamps because they are integrated on-chip.

3.10 Reset Management Unit (RMU)

The RMU is responsible for handling reset of the MGM12P. A wide range of reset sources are available, including several power supply

monitors, pin reset, software controlled reset, core lockup reset and watchdog reset.

3.11 Core and Memory

3.11.1 Processor Core

The ARM Cortex-M4F processor includes a 32-bit RISC processor integrating the following features and tasks in the system:

• ARM Cortex-M4F RISC processor achieving 1.25 Dhrystone MIPS/MHz

• Memory Protection Unit (MPU) supporting up to 8 memory segments

• 1024 KB flash program memory

• 256 KB RAM data memory

• Configuration and event handling of all modules

• 2-pin Serial-Wire debug interface

3.11.2 Memory System Controller (MSC)

The Memory System Controller (MSC) is the program memory unit of the microcontroller. The flash memory is readable and writable

from both the Cortex-M and DMA. The flash memory is divided into two blocks; the main block and the information block. Program code

is normally written to the main block, whereas the information block is available for special user data and flash lock bits. There is also a

read-only page in the information block containing system and device calibration data. Read and write operations are supported in en-

ergy modes EM0 Active and EM1 Sleep.

3.11.3 Linked Direct Memory Access Controller (LDMA)

The Linked Direct Memory Access (LDMA) controller allows the system to perform memory operations independently of software. This

reduces both energy consumption and software workload. The LDMA allows operations to be linked together and staged, enabling so-

phisticated operations to be implemented.

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

System Overview

3.12 Memory Map

The MGM12P memory map is shown in the figures below.

Figure 3.4. MGM12P Memory Map — Core Peripherals and Code Space

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System Overview

Figure 3.5. MGM12P Memory Map — Peripherals

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System Overview

3.13 Configuration Summary

The features of the MGM12P are a subset of the feature set described in the device reference manual. The table below describes de-

vice specific implementation of the features. Remaining modules support full configuration.

Table 3.3. Configuration Summary

Module

USART0

USART1

Configuration

Pin Connections

IrDA SmartCard

US0_TX, US0_RX, US0_CLK, US0_CS

US1_TX, US1_RX, US1_CLK, US1_CS

IrDA I²S SmartCard

IrDA SmartCard

USART2

USART3

US2_TX, US2_RX, US2_CLK, US2_CS

US3_TX, US3_RX, US3_CLK, US3_CS

IrDA I²S SmartCard

TIMER0

with DTI

TIM0_CC[2:0], TIM0_CDTI[2:0]

TIM1_CC[3:0]

TIMER1

-

WTIMER0

WTIMER1

with DTI

-

WTIM0_CC[2:0], WTIM0_CDTI[2:0]

WTIM1_CC[3:0]

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Electrical Specifications

4. Electrical Specifications

4.1 Electrical Characteristics

All electrical parameters in all tables are specified under the following conditions, unless stated otherwise:

• Typical values are based on T_AMB=25 °C and V_DD= 3.3 V, by production test and/or technology characterization.

• Radio performance numbers are measured in conducted mode, based on Silicon Laboratories reference designs using output pow-

er-specific external RF impedance-matching networks for interfacing to a 50 Ω antenna.

• Minimum and maximum values represent the worst conditions across supply voltage, process variation, and operating temperature,

unless stated otherwise.

Refer to Figure 3.2 MGM12P Power Block for Modules (+10 dBm) on page 9 and Figure 3.3 MGM12P Power Block for Modules (+17

dBm) on page 10 to see the relation between the modules external VDD pin and internal voltage supplies. The module has only one

external power supply input (VDD).

Refer to 4.1.2 General Operating Conditions for more details about operational supply and temperature limits.

4.1.1 Absolute Maximum Ratings

Stresses above those listed below may cause permanent damage to the device. This is a stress rating only and functional operation of

the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure

to maximum rating conditions for extended periods may affect device reliability. For more information on the available quality and relia-

bility data, see the Quality and Reliability Monitor Report at http://www.silabs.com/support/quality/pages/default.aspx.

Table 4.1. Absolute Maximum Ratings

Parameter

Symbol

T_STG

Test Condition

Min

-40

-0.3

—

Typ

—

Max

85

Unit

°C

Storage temperature range

Voltage on any supply pin

V_DDMAX

V_DDRAMPMAX

—

3.8

1

V

Voltage ramp rate on any

supply pin

—

V / μs

DC Voltage on any over-volt- V_DIGPIN

age tolerant GPIO pin¹

-0.3

—

Min of 5.25

and IOVDD

+2

V

-0.3

—

IOVDD+0.3

V

Input RF level

P_RFMAX2G4

10

50

dBm

mA

Current per I/O pin

I_IOMAX

Sink

—

Source

Sink

—

50

Current for all I/O pins

I_IOALLMAX

—

200

Source

—

Note:

1. When a GPIO pin is routed to the analog module through the APORT, the maximum voltage = IOVDD.

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Electrical Specifications

4.1.2 General Operating Conditions

Table 4.2. General Operating Conditions

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Operating Ambient tempera- T_A

ture range

-G temperature grade

-40

25

85

°C

VDD supply voltage ¹

V_VDD

DCDC in regulation

2.4

1.8

—

3.3

—

3.8

40

V

DCDC in bypass 50mA load

FWAIT = 1, VSCALE2

FWAIT = 0, VSCALE0

V

Core Clock Frequency

f_CORE

MHz

—

20

Note:

1. The minimum voltage required in bypass mode is calculated using R_BYPfrom the DCDC specification table. Requirements for

other loads can be calculated as V_{DVDD_min}+I_LOAD* R_{BYP_max}

.

4.1.3 DC-DC Converter

Table 4.3. DC-DC Converter

Test Condition

Parameter

Symbol

Min

Typ

Max

Unit

Input voltage range

V_{DCDC_I}

Bypass mode, I_{DCDC_LOAD}= 50

mA

1.8

—

V_{VREGVDD_}

V

MAX

Low noise (LN) mode, 1.8 V out-

put, I_{DCDC_LOAD}= 100 mA, or

Low power (LP) mode, 1.8 V out-

put, I_{DCDC_LOAD}= 10 mA

2.4

—

V_{VREGVDD_}

V

MAX

Low noise (LN) mode, 1.8 V out-

put, I_{DCDC_LOAD}= 200 mA

2.6

1.8

—

V_{VREGVDD_}

V

MAX

Output voltage programma- V_{DCDC_O}

ble range¹

V_VREGVDD

V

Max load current

I_{LOAD_MAX}

Low noise (LN) mode, Medium

Drive²

100

50

mA

μA

mA

Low noise (LN) mode, Light

Drive²

—

Low power (LP) mode,

LPCMPBIASEMxx³= 0

—

75

Low power (LP) mode,

LPCMPBIASEMxx³= 3

—

10

Note:

1. Due to internal dropout, the DC-DC output will never be able to reach its input voltage, V_VDD

2. Drive levels are defined by configuration of the PFETCNT and NFETCNT registers. Light Drive: PFETCNT=NFETCNT=3; Medi-

um Drive: PFETCNT=NFETCNT=7; Heavy Drive: PFETCNT=NFETCNT=15.

3. In EMU_DCDCMISCCTRL register

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Electrical Specifications

4.1.4 Current Consumption

4.1.4.1 Current Consumption 3.3 V using DC-DC Converter

Unless otherwise indicated, typical conditions are: VDD = 3.3 V, DC-DC enabled. T_OP= 25 °C. Minimum and maximum values in this

table represent the worst conditions across supply voltage and process variation at T_OP= 25 °C.

Table 4.4. Current Consumption 3.3 V using DC-DC Converter

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Current consumption in EM0 I_{ACTIVE_DCM}

mode with all peripherals dis-

abled, DCDC in Low Noise

DCM mode².

38.4 MHz crystal, CPU running

while loop from flash⁴

—

88

—

μA/MHz

38 MHz HFRCO, CPU running

Prime from flash

—

70

—

μA/MHz

38 MHz HFRCO, CPU running

while loop from flash

38 MHz HFRCO, CPU running

CoreMark from flash

85

26 MHz HFRCO, CPU running

while loop from flash

77

1 MHz HFRCO, CPU running

while loop from flash

636

98

Current consumption in EM0 I_{ACTIVE_CCM}

mode with all peripherals dis-

abled, DCDC in Low Noise

CCM mode¹.

38.4 MHz crystal, CPU running

while loop from flash⁴

38 MHz HFRCO, CPU running

Prime from flash

—

81

82

—

μA/MHz

38 MHz HFRCO, CPU running

while loop from flash

38 MHz HFRCO, CPU running

CoreMark from flash

95

26 MHz HFRCO, CPU running

while loop from flash

95

1 MHz HFRCO, CPU running

while loop from flash

1155

101

1155

Current consumption in EM0 I_{ACTIVE_CCM_VS}19 MHz HFRCO, CPU running

mode with all peripherals dis-

abled and voltage scaling

enabled, DCDC in Low

Noise CCM mode¹.

while loop from flash

1 MHz HFRCO, CPU running

while loop from flash

38.4 MHz crystal⁴

38 MHz HFRCO

26 MHz HFRCO

1 MHz HFRCO

19 MHz HFRCO

1 MHz HFRCO

Current consumption in EM1 I_{EM1_DCM}

mode with all peripherals dis-

abled, DCDC in Low Noise

—

59

—

μA/MHz

—

41

48

—

μA/MHz

DCM mode².

610

52

Current consumption in EM1 I_{EM1_DCM_VS}

mode with all peripherals dis-

abled and voltage scaling

587

enabled, DCDC in Low

Noise DCM mode².

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Current consumption in EM2 I_{EM2_VS}

mode, with votage scaling

Full 256 kB RAM retention and

RTCC running from LFXO

—

2.62

—

μA

enabled, DCDC in LP mode.

3

Full 256 kB RAM retention and

RTCC running from LFRCO

—

2.72

2.02

—

μA

16 kB (1 bank) RAM retention and

RTCC running from LFRCO⁵

Current consumption in EM3 I_{EM3_VS}

mode, with voltage scaling

enabled.

Full 256 kB RAM retention and

CRYOTIMER running from ULFR-

CO

—

2.33

—

μA

Current consumption in

EM4H mode, with voltage

scaling enabled.

I_{EM4H_VS}

128 byte RAM retention, RTCC

running from LFXO

—

1.21

0.91

—

μA

128 byte RAM retention, CRYO-

TIMER running from ULFRCO

128 byte RAM retention, no RTCC

No RAM retention, no RTCC

—

0.91

0.58

—

μA

Current consumption in

EM4S mode

I_EM4S

Note:

1. DCDC Low Noise CCM Mode = Light Drive (PFETCNT=NFETCNT=3), F=6.4 MHz (RCOBAND=4), ANASW=DVDD.

2. DCDC Low Noise DCM Mode = Light Drive (PFETCNT=NFETCNT=3), F=3.0 MHz (RCOBAND=0), ANASW=DVDD.

3. DCDC Low Power Mode = Medium Drive (PFETCNT=NFETCNT=7), LPOSCDIV=1, LPCMPBIASEM234H=0, LPCLIMILIM-

SEL=1, ANASW=DVDD.

4. CMU_HFXOCTRL_LOWPOWER=0.

5. CMU_LFRCOCTRL_ENVREF = 1, CMU_LFRCOCTRL_VREFUPDATE = 1

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Electrical Specifications

4.1.4.2 Current Consumption Using Radio 3.3 V with DC-DC

Unless otherwise indicated, typical conditions are: VDD = 3.3 V, DC-DC enabled. T_OP= 25 °C. Minimum and maximum values in this

table represent the worst conditions across supply voltage and process variation at T_OP= 25 °C.

Table 4.5. Current Consumption Using Radio 3.3 V with DC-DC

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Current consumption in re-

ceive mode, active packet

reception (MCU in EM1 @

38.4 MHz, peripheral clocks

disabled).

I_{RX_ACTIVE}

1 Mbit/s, 2GFSK, F = 2.4 GHz,

Radio clock prescaled by 4

—

10.3

—

mA

2 Mbit/s, 2GFSK, F = 2.4 GHz,

Radio clock prescaled by 4

—

11.5

10.8

11.6

12.6

12.3

10

—

mA

802.15.4 receiving frame, F = 2.4

GHz, Radio clock prescaled by 3

LNA in bypass.

Current consumption in re-

ceive mode, listening for

packet (MCU in EM1 @ 38.4

MHz, peripheral clocks disa-

bled)

I_{RX_LISTEN}

1 Mbit/s, 2GFSK, F = 2.4 GHz, No

radio clock prescaling

2 Mbit/s, 2GFSK, F = 2.4 GHz, No

radio clock prescaling

802.15.4, F = 2.4 GHz, No radio

clock prescaling

LNA in bypass.

Current consumption in

transmit mode (MCU in EM1

@ 38.4 MHz, peripheral

clocks disabled)

I_TX

F = 2.4 GHz, CW, 0 dBm output

power, Radio clock prescaled by 1

F = 2.4 GHz, CW, 8 dBm output

power

28

LNA in bypass.

F = 2.4 GHz, CW, 10.5 dBm out-

put power

37.4

86

F = 2.4 GHz, CW, 16.5 dBm out-

put power, PAVDD connected di-

rectly to VDD

F = 2.4 GHz, CW, 19.5 dBm out-

put power, PAVDD connected di-

rectly to VDD

—

131

—

mA

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Electrical Specifications

4.1.5 Wake Up Times

Table 4.6. Wake Up Times

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Wakeup time from EM1

t_{EM1_WU}

—

3

—

AHB

Clocks

Wake up from EM2

Wake up from EM3

t_{EM2_WU}

Code execution from flash

Code execution from RAM

Code execution from flash

Code execution from RAM

Executing from flash

—

10.1

3.2

—

μs

t_{EM3_WU}

10.1

3.2

Wake up from EM4H¹

Wake up from EM4S¹

t_{EM4H_WU}

t_{EM4S_WU}

t_RESET

80

Executing from flash

—

291

—

μs

Time from release of reset

source to first instruction ex-

ectution.

Soft Pin Reset released

Any other reset released

—

43

—

μs

350

Power Mode Scaling time

t_SCALE

VSCALE0 to VSCALE2, HFCLK =

19 MHz^{2, 4}

—

31.8

4.3

—

μs

VSCALE2 to VSCALE0, HFCLK =

19 MHz^{2, 3}

Note:

1. Time from wakeup request until first instruction is executed. Wakeup results in device reset.

2. VSCALE0 to VSCALE2 voltage change transitions occur at a rate of 10 mV/μs for approximately 20 μs. During this transition,

peak currents will be dependent on the value of the DECOUPLE output capacitor, from 35 mA (with a 1 μF capacitor) to 70 mA

(with a 2.7 μF capacitor).

3. Scaling down from VSCALE2 to VSCALE0 requires approximately 2.8 μs + 29 HFCLKs.

4. Scaling up from VSCALE0 to VSCALE2 requires approximately 30.3 μs + 28 HFCLKs.

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Electrical Specifications

4.1.6 Brown Out Detector (BOD)

Table 4.7. Brown Out Detector (BOD)

Parameter

Symbol

Test Condition

Min

—

Typ

—

Max

1.62

—

Unit

V

DVDD BOD threshold

V_DVDDBOD

DVDD rising

DVDD falling (EM0/EM1)

DVDD falling (EM2/EM3)

1.35

1.3

—

V

—

V

DVDD BOD hysteresis

DVDD BOD response time

AVDD BOD threshold

V_{DVDDBOD_HYST}

18

2.4

—

mV

μs

V

t_{DVDDBOD_DELAY}Supply drops at 0.1V/μs rate

—

V_AVDDBOD

AVDD rising

—

1.8

—

AVDD falling (EM0/EM1)

AVDD falling (EM2/EM3)

1.62

1.53

—

V

—

V

AVDD BOD hysteresis

AVDD BOD response time

EM4 BOD threshold

V_{AVDDBOD_HYST}

20

2.4

—

mV

μs

V

t_{AVDDBOD_DELAY}Supply drops at 0.1V/μs rate

—

V_EM4DBOD

AVDD rising

AVDD falling

—

1.7

—

1.45

—

V

EM4 BOD hysteresis

V_{EM4BOD_HYST}

25

300

—

mV

μs

EM4 BOD response time

t_{EM4BOD_DELAY}Supply drops at 0.1V/μs rate

—

4.1.7 Frequency Synthesizer

Table 4.8. Frequency Synthesizer

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

RF Synthesizer Frequency

range

f_RANGE

2400 - 2483.5 MHz

2400

—

2483.5

MHz

LO tuning frequency resolu- f_RES

tion with 38.4 MHz crystal

2400 - 2483.5 MHz

—

73

Hz

Frequency deviation resolu- df_RES

tion with 38.4 MHz crystal

Maximum frequency devia-

tion with 38.4 MHz crystal

df_MAX

1677

kHz

4.1.8 2.4 GHz RF Transceiver Characteristics

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Electrical Specifications

4.1.8.1 RF Transmitter General Characteristics for 2.4 GHz Band

Unless otherwise indicated, typical conditions are: T_OP= 25 °C, VDD = 3.3 V, DVDD = RFVDD = PAVDD. RFVDD and PAVDD path is

filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 2.45 GHz.

Table 4.9. RF Transmitter General Characteristics for 2.4 GHz Band

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Maximum TX power¹

POUT_MAX

17 dBm-rated part numbers.

PAVDD connected directly to

VDD²

—

17

—

dBm

10 dBm-rated part numbers

CW

—

10

-30

1

—

dBm

dB

Minimum active TX Power

Output power step size

POUT_MIN

POUT_STEP

-5 dBm< Output power < 0 dBm

—

0 dBm < output power <

POUT_MAX

0.5

dB

Output power variation vs

supply at POUT_MAX

POUT_{VAR_V}

1.8 V < V_VREGVDD< 3.8 V,

PAVDD connected directly to

VDD, for output power > 10 dBm.

—

5.7

—

dB

1.8 V < V_VREGVDD< 3.8 V using

DC-DC converter

—

3.4

1.5

0.4

—

dB

Output power variation vs

temperature at POUT_MAX

POUT_{VAR_T}

From -40 to +85 °C, PAVDD con-

nected to DC-DC output

From -40 to +85 °C, PAVDD con-

nected to VDD

—

dB

Output power variation vs RF POUT_{VAR_F}

frequency at POUT_MAX

Over RF tuning frequency range

—

dB

RF tuning frequency range

F_RANGE

2400

2483.5

MHz

Note:

1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices cov-

ered in this datasheet can be found in the Max TX Power column of the Ordering Information Table.

2. For Bluetooth, the Maximum TX power on Channel 2456 is limited to +15 dBm to comply with In-band Spurious emissions.

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Electrical Specifications

4.1.8.2 RF Receiver General Characteristics for 2.4 GHz Band

Unless otherwise indicated, typical conditions are: T_OP= 25 °C, VDD = 3.3 V, DC-DC enabled. Crystal frequency=38.4 MHz. RF center

frequency 2.45 GHz.

Table 4.10. RF Receiver General Characteristics for 2.4 GHz Band

Parameter

Symbol

F_RANGE

SPUR_RX

Test Condition

Min

2400

—

Typ

—

Max

2483.5

—

Unit

MHz

dBm

RF tuning frequency range

Receive mode maximum

spurious emission

30 MHz to 1 GHz

1 GHz to 12 GHz

-57

—

-47

—

Max spurious emissions dur- SPUR_{RX_FCC}

ing active receive mode, per

FCC Part 15.109(a)

216 MHz to 960 MHz, Conducted

Measurement

—

-55.2

—

Above 960 MHz, Conducted

Measurement

—

-47.2

—

dBm

4.1.8.3 RF Receiver Characteristics for Bluetooth Low Energy in the 2.4GHz Band, 1 Mbps Data Rate

Unless otherwise indicated, typical conditions are: T = 25 °C, VDD = 3.3 V, DC-DC enabled. Crystal frequency=38.4MHz. RF center

frequency 2.45 GHz.

Table 4.11. RF Receiver Characteristics for Bluetooth Low Energy in the 2.4GHz Band, 1 Mbps Data Rate

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Signal is reference signal¹. Using

DC-DC converter.

Sensitivity, 0.1% BER

SENS

—

-95

—

dBm

Signal is reference signal.¹Using

DC-DC converter.

—

-101.6

—

dBm

Modules with LNA.

Note:

1. Reference signal is defined 2GFSK at -67 dBm, Modulation index = 0.5, BT = 0.5, Bit rate = 1 Mbps, desired data = PRBS9;

interferer data = PRBS15; frequency accuracy better than 1 ppm.

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Electrical Specifications

4.1.8.4 RF Receiver Characteristics for Bluetooth Low Energy in the 2.4GHz Band, 2 Mbps Data Rate

Unless otherwise indicated, typical conditions are: T = 25 °C, VDD = 3.3 V, DC-DC enabled. Crystal frequency=38.4MHz. RF center

frequency 2.45 GHz.1

Table 4.12. RF Receiver Characteristics for Bluetooth Low Energy in the 2.4GHz Band, 2 Mbps Data Rate

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Signal is reference signal¹. Using

DC-DC converter.

Sensitivity, 0.1% BER

SENS

—

-91

—

dBm

Signal is reference signal.¹Using

DC-DC converter.

—

-97

—

dBm

Modules with LNA.

Note:

1. Reference signal is defined 2GFSK at -67 dBm, Modulation index = 0.5, BT = 0.5, Bit rate = 2 Mbps, desired data = PRBS9;

interferer data = PRBS15; frequency accuracy better than 1 ppm.

4.1.8.5 RF Receiver Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band

Unless otherwise indicated, typical conditions are: T_OP= 25 °C, VDD = 3.3 V, DC-DC enabled. Crystal frequency=38.4 MHz. RF center

frequency 2.45 GHz.

Table 4.13. RF Receiver Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Sensitivity, 1% PER

SENS

Signal is reference signal. Packet

length is 20 octets. Using DC-DC

converter.

—

-101

—

dBm

Signal is reference signal. Packet

length is 20 octets. Using DC-DC

converter.

—

-105

—

dBm

Modules with LNA.

Note:

1. Reference signal is defined as O-QPSK DSSS per 802.15.4, Frequency range = 2400-2483.5 MHz, Symbol rate = 62.5 ksym-

bols/s.

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Electrical Specifications

4.1.9 Current Consumption

4.1.9.1 Low-Frequency Crystal Oscillator (LFXO)

Table 4.14. Low-Frequency Crystal Oscillator (LFXO)

Parameter

Symbol

Test Condition

Min

—

Typ

Max

—

Unit

kHz

ppm

Crystal Frequency

Crystal Frequency Tolerance

f_LFXO

32.768

-100

+100

4.1.9.2 High-Frequency Crystal Oscillator (HFXO)

Table 4.15. High-Frequency Crystal Oscillator (HFXO)

Parameter

Symbol

Test Condition

Min

Typ

38.4

—

Max

Unit

MHz

ppm

Crystal Frequency

f_HFXO

Frequency Tolerance for the FT_HFXO

crystal

-40

40

4.1.9.3 Low-Frequency RC Oscillator (LFRCO)

Table 4.16. Low-Frequency RC Oscillator (LFRCO)

Parameter

Symbol

Test Condition

ENVREF²= 1

ENVREF²= 0

Min

Typ

Max

Unit

Oscillation frequency

f_LFRCO

31.7

32.768

33.3

kHz

31.8

—

32.768

500

33.2

—

kHz

μs

Startup time

t_LFRCO

I_LFRCO

Current consumption ¹

ENVREF = 1 in

CMU_LFRCOCTRL

—

370

—

nA

ENVREF = 0 in

—

520

—

nA

CMU_LFRCOCTRL

Note:

1. Block is supplied by AVDD if ANASW = 0, or DVDD if ANASW=1 in EMU_PWRCTRL register.

2. in CMU_LFRCOCTRL register.

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Electrical Specifications

4.1.9.4 High-Freqency RC Oscillator (HFRCO)

Table 4.17. High-Freqency RC Oscillator (HFRCO)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Frequency Accuracy

f_{HFRCO_ACC}

At production calibrated frequen-

cies, across supply voltage and

temperature

-2.5

—

2.5

%

Start-up time

t_HFRCO

f_HFRCO≥ 19 MHz

4 < f_HFRCO< 19 MHz

f_HFRCO≤ 4 MHz

f_HFRCO= 38 MHz

f_HFRCO= 32 MHz

f_HFRCO= 26 MHz

f_HFRCO= 19 MHz

f_HFRCO= 16 MHz

f_HFRCO= 13 MHz

f_HFRCO= 7 MHz

f_HFRCO= 4 MHz

f_HFRCO= 2 MHz

f_HFRCO= 1 MHz

—

300

1

—

ns

μs

2.5

244

204

173

143

123

110

85

—

μs

Current consumption on all

supplies

I_HFRCO

265

222

188

156

136

124

94

μA

%

32

37

28

34

26

31

Coarse trim step size (% of

period)

SS_{HFRCO_COARS}

0.8

—

E

Fine trim step size (% of pe- SS_{HFRCO_FINE}

riod)

—

0.1

0.2

—

%

Period jitter

PJ_HFRCO

% RMS

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Electrical Specifications

4.1.9.5 Auxiliary High-Freqency RC Oscillator (AUXHFRCO)

Table 4.18. Auxiliary High-Freqency RC Oscillator (AUXHFRCO)

Parameter

Symbol

Test Condition

Min

-3

Typ

Max

Unit

Frequency Accuracy

f_{AUXHFRCO_ACC}At production calibrated frequen-

—

3

%

cies, across supply voltage and

temperature

Start-up time

t_AUXHFRCO

f_AUXHFRCO≥ 19 MHz

4 < f_AUXHFRCO< 19 MHz

f_AUXHFRCO≤ 4 MHz

f_AUXHFRCO= 38 MHz

f_AUXHFRCO= 32 MHz

f_AUXHFRCO= 26 MHz

f_AUXHFRCO= 19 MHz

f_AUXHFRCO= 16 MHz

f_AUXHFRCO= 13 MHz

f_AUXHFRCO= 7 MHz

f_AUXHFRCO= 4 MHz

f_AUXHFRCO= 2 MHz

f_AUXHFRCO= 1 MHz

—

400

1.4

2.5

193

157

135

108

100

77

—

ns

μs

—

μs

Current consumption on all

supplies

I_AUXHFRCO

213

175

151

122

113

88

μA

%

53

63

29

36

28

34

27

31

Coarse trim step size (% of

period)

SS_AUXHFR-

0.8

—

CO_COARSE

Fine trim step size (% of pe- SS_AUXHFR-

—

0.1

0.2

—

%

riod)

CO_FINE

Period jitter

PJ_AUXHFRCO

% RMS

4.1.9.6 Ultra-low Frequency RC Oscillator (ULFRCO)

Table 4.19. Ultra-low Frequency RC Oscillator (ULFRCO)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Oscillation frequency

f_ULFRCO

0.95

1

1.07

kHz

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Electrical Specifications

4.1.10 Flash Memory Characteristics³

Table 4.20. Flash Memory Characteristics³

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Flash erase cycles before

failure

EC_FLASH

10000

—

cycles

Flash data retention

RET_FLASH

t_{W_PROG}

10

20

—

years

μs

Word (32-bit) programming

time

Burst write, 128 words, average

time per word

24.4

30

Single word

60

20

68.4

26.4

26.5

80

35

Page erase time

Mass erase time¹

Device erase time²

Page erase current⁴

Write current⁴

t_PERASE

t_MERASE

t_DERASE

I_ERASE

ms

mA

V

—

69

—

100

1.6

3.8

3.6

I_WRITE

—

Supply voltage during flash

erase and write

V_FLASH

1.62

Note:

1. Mass erase is issued by the CPU and erases all flash

2. Device erase is issued over the AAP interface and erases all flash, SRAM, the Lock Bit (LB) page, and the User data page Lock

Word (ULW)

3. Flash data retention information is published in the Quarterly Quality and Reliability Report.

4. Measured at 25 °C

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Electrical Specifications

4.1.11 General-Purpose I/O (GPIO)

Table 4.21. General-Purpose I/O (GPIO)

Parameter

Symbol

Test Condition

GPIO pins

Min

—

Typ

—

Max

IOVDD*0.3

—

Unit

V

Input low voltage

Input high voltage

V_IL

V_IH

GPIO pins

IOVDD*0.7

IOVDD*0.8

—

V

Output high voltage relative V_OH

to IOVDD

Sourcing 3 mA, IOVDD ≥ 3 V,

—

V

DRIVESTRENGTH¹= WEAK

Sourcing 1.2 mA, IOVDD ≥ 1.62

V,

IOVDD*0.6

—

V

DRIVESTRENGTH¹= WEAK

Sourcing 20 mA, IOVDD ≥ 3 V,

IOVDD*0.8

—

0.1

—

V

DRIVESTRENGTH¹= STRONG

Sourcing 8 mA, IOVDD ≥ 1.62 V,

IOVDD*0.6

—

DRIVESTRENGTH¹= STRONG

Sinking 3 mA, IOVDD ≥ 3 V,

Output low voltage relative to V_OL

IOVDD

—

IOVDD*0.2

IOVDD*0.4

IOVDD*0.2

IOVDD*0.4

30

V

DRIVESTRENGTH¹= WEAK

Sinking 1.2 mA, IOVDD ≥ 1.62 V,

V

DRIVESTRENGTH¹= WEAK

Sinking 20 mA, IOVDD ≥ 3 V,

V

DRIVESTRENGTH¹= STRONG

Sinking 8 mA, IOVDD ≥ 1.62 V,

V

DRIVESTRENGTH¹= STRONG

Input leakage current

I_IOLEAK

All GPIO except LFXO pins, GPIO

≤ IOVDD

nA

LFXO Pins, GPIO ≤ IOVDD

—

0.1

3.3

50

15

nA

μA

Input leakage current on

I_5VTOLLEAK

IOVDD < GPIO ≤ IOVDD + 2 V

5VTOL pads above IOVDD

I/O pin pull-up/pull-down re- R_PUD

sistor

30

15

40

25

65

45

kΩ

ns

Pulse width of pulses re-

moved by the glitch suppres-

sion filter

t_IOGLITCH

Output fall time, From 70%

to 30% of V_IO

t_IOOF

C_L= 50 pF,

—

1.8

4.5

—

ns

DRIVESTRENGTH¹= STRONG,

SLEWRATE¹= 0x6

C_L= 50 pF,

DRIVESTRENGTH¹= WEAK,

SLEWRATE¹= 0x6

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Output rise time, From 30% t_IOOR

to 70% of V_IO

C_L= 50 pF,

—

2.2

—

ns

DRIVESTRENGTH¹= STRONG,

SLEWRATE = 0x6¹

C_L= 50 pF,

—

7.4

—

ns

DRIVESTRENGTH¹= WEAK,

SLEWRATE¹= 0x6

Note:

1. In GPIO_Pn_CTRL register

4.1.12 Voltage Monitor (VMON)

Table 4.22. Voltage Monitor (VMON)

Test Condition

Parameter

Symbol

I_VMON

Min

Typ

Max

Unit

Supply Current (including

I_SENSE)

In EM0 or EM1, 1 supply moni-

tored

—

6.3

10

μA

In EM0 or EM1, 4 supplies moni-

tored

—

12.5

62

17

—

μA

nA

In EM2, EM3 or EM4, 1 supply

monitored and above threshol

In EM2, EM3 or EM4, 1 supply

monitored and below threshold

62

In EM2, EM3 or EM4, 4 supplies

monitored and all above threshold

99

In EM2, EM3 or EM4, 4 supplies

monitored and all below threshold

99

Loading of Monitored Supply I_SENSE

In EM0 or EM1

—

2

—

3.4

—

μA

nA

V

In EM2, EM3 or EM4

Threshold range

V_{VMON_RANGE}

1.62

—

Threshold step size

N_{VMON_STESP}

Coarse

200

20

460

26

mV

ns

Fine

—

Response time

Hysteresis

t_{VMON_RES}

Supply drops at 1V/μs rate

—

V_{VMON_HYST}

—

mV

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Electrical Specifications

4.1.13 Analog to Digital Converter (ADC)

Table 4.23. Analog to Digital Converter (ADC)

Parameter

Symbol

Test Condition

Min

Typ

—

Max

12

Unit

Bits

V

Resolution

V_RESOLUTION

V_ADCIN

6

—

Input voltage range

Single ended

Differential

—

V_FS

-V_FS/2

1

—

V_FS/2

V_AVDD

V

Input range of external refer- V_{ADCREFIN_P}

ence voltage, single ended

and differential

—

V

Power supply rejection²

PSRR_ADC

At DC

—

80

—

dB

Analog input common mode CMRR_ADC

rejection ratio

Current from all supplies, us- I_{ADC_CONTI-}

1 Msps / 16 MHz ADCCLK, BIA-

SPROG = 0, GPBIASACC = 1 ³

—

270

125

80

315

—

μA

ing internal reference buffer.

NOUS_LP

Continous operation. WAR-

MUPMODE⁴= KEEPADC-

WARM

250 ksps / 4 MHz ADCCLK, BIA-

SPROG = 6, GPBIASACC = 1 ³

62.5 ksps / 1 MHz ADCCLK, BIA-

SPROG = 15, GPBIASACC = 1 ³

Current from all supplies, us- I_{ADC_NORMAL_LP}35 ksps / 16 MHz ADCCLK, BIA-

45

SPROG = 0, GPBIASACC = 1 ³

ing internal reference buffer.

Duty-cycled operation. WAR-

MUPMODE⁴= NORMAL

5 ksps / 16 MHz ADCCLK BIA-

SPROG = 0, GPBIASACC = 1 ³

8

Current from all supplies, us- I_{ADC_STAND-}

125 ksps / 16 MHz ADCCLK, BIA-

SPROG = 0, GPBIASACC = 1 ³

105

70

ing internal reference buffer.

BY_LP

Duty-cycled operation.

35 ksps / 16 MHz ADCCLK, BIA-

SPROG = 0, GPBIASACC = 1 ³

AWARMUPMODE⁴= KEEP-

INSTANDBY or KEEPIN-

SLOWACC

Current from all supplies, us- I_{ADC_CONTI-}

1 Msps / 16 MHz ADCCLK, BIA-

SPROG = 0, GPBIASACC = 0 ³

—

325

175

125

85

—

μA

ing internal reference buffer.

NOUS_HP

Continous operation. WAR-

MUPMODE⁴= KEEPADC-

WARM

250 ksps / 4 MHz ADCCLK, BIA-

SPROG = 6, GPBIASACC = 0 ³

62.5 ksps / 1 MHz ADCCLK, BIA-

SPROG = 15, GPBIASACC = 0 ³

Current from all supplies, us- I_{ADC_NORMAL_HP}35 ksps / 16 MHz ADCCLK, BIA-

SPROG = 0, GPBIASACC = 0 ³

ing internal reference buffer.

Duty-cycled operation. WAR-

MUPMODE⁴= NORMAL

5 ksps / 16 MHz ADCCLK BIA-

SPROG = 0, GPBIASACC = 0 ³

16

Current from all supplies, us- I_{ADC_STAND-}

125 ksps / 16 MHz ADCCLK, BIA-

SPROG = 0, GPBIASACC = 0 ³

160

125

ing internal reference buffer.

BY_HP

Duty-cycled operation.

35 ksps / 16 MHz ADCCLK, BIA-

SPROG = 0, GPBIASACC = 0 ³

AWARMUPMODE⁴= KEEP-

INSTANDBY or KEEPIN-

SLOWACC

Current from HFPERCLK

I_{ADC_CLK}

HFPERCLK = 16 MHz

—

160

—

μA

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Electrical Specifications

Parameter

Symbol

f_ADCCLK

Test Condition

Min

—

Typ

—

7

Max

16

1

Unit

MHz

ADC clock frequency

Throughput rate

f_ADCRATE

t_ADCCONV

—

Msps

cycles

μs

Conversion time¹

6 bit

8 bit

12 bit

—

5

—

9

—

13

—

WARMUPMODE⁴= NORMAL

Startup time of reference

generator and ADC core

t_ADCSTART

—

WARMUPMODE⁴= KEEPIN-

STANDBY

—

58

—

67

2

μs

dB

WARMUPMODE⁴= KEEPINSLO-

WACC

1

Internal reference⁶, differential

measurement

SNDR at 1Msps and f_IN

10kHz

=

SNDR_ADC

—

External reference⁵, differential

measurement

—

68

—

dB

Spurious-free dynamic range SFDR_ADC

(SFDR)

1 MSamples/s, 10 kHz full-scale

sine wave

—

-1

-6

75

—

2

dB

Differential non-linearity

(DNL)

DNL_ADC

12 bit resolution, no missing co-

des

LSB

Integral non-linearity (INL),

End point method

INL_ADC

12 bit resolution

6

Offset error

V_ADCOFFSETERR

V_ADCGAIN

-3

—

0

3

LSB

%

Gain error in ADC

Using internal reference

Using external reference

-0.2

-1

3.5

—

%

Temperature sensor slope

V_{TS_SLOPE}

-1.84

mV/°C

Note:

1. Derived from ADCCLK

2. PSRR is referenced to AVDD when ANASW=0 and to DVDD when ANASW=1 in EMU_PWRCTRL

3. In ADCn_BIASPROG register

4. In ADCn_CNTL register

5. External reference is 1.25 V applied externally to ADCnEXTREFP, with the selection CONF in the SINGLECTRL_REF or

SCANCTRL_REF register field and VREFP in the SINGLECTRLX_VREFSEL or SCANCTRLX_VREFSEL field. The differential

input range with this configuration is ±1.25 V.

6. Internal reference option used corresponds to selection 2V5 in the SINGLECTRL_REF or SCANCTRL_REF register field. The

differential input range with this configuration is ±1.25 V. Typical value is characterized using full-scale sine wave input. Minimum

value is production-tested using sine wave input at 1.5 dB lower than full scale.

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Electrical Specifications

4.1.14 Analog Comparator (ACMP)

Table 4.24. Analog Comparator (ACMP)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Input voltage range

V_ACMPIN

ACMPVDD =

ACMPn_CTRL_PWRSEL ¹

—

V_ACMPVDD

V

BIASPROG⁴≤ 0x10 or FULL-

BIAS⁴= 0

Supply voltage

V_ACMPVDD

1.8

2.1

—

V_{VREGVDD_}

V

MAX

0x10 < BIASPROG⁴≤ 0x20 and

FULLBIAS⁴= 1

V_{VREGVDD_}

MAX

BIASPROG⁴= 1, FULLBIAS⁴= 0

Active current not including

voltage reference²

I_ACMP

—

50

—

nA

BIASPROG⁴= 0x10, FULLBIAS⁴

= 0

306

BIASPROG⁴= 0x02, FULLBIAS⁴

= 1

—

6.5

75

50

—

92

—

μA

nA

BIASPROG⁴= 0x20, FULLBIAS⁴

= 1

Current consumption of inter- I_ACMPREF

nal voltage reference²

VLP selected as input using 2.5 V

Reference / 4 (0.625 V)

VLP selected as input using VDD

—

20

—

nA

μA

VBDIV selected as input using

1.25 V reference / 1

4.1

VADIV selected as input using

VDD/1

—

2.4

—

μA

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

HYSTSEL⁵= HYST0

HYSTSEL⁵= HYST1

HYSTSEL⁵= HYST2

HYSTSEL⁵= HYST3

HYSTSEL⁵= HYST4

HYSTSEL⁵= HYST5

HYSTSEL⁵= HYST6

HYSTSEL⁵= HYST7

HYSTSEL⁵= HYST8

HYSTSEL⁵= HYST9

HYSTSEL⁵= HYST10

HYSTSEL⁵= HYST11

HYSTSEL⁵= HYST12

HYSTSEL⁵= HYST13

HYSTSEL⁵= HYST14

HYSTSEL⁵= HYST15

BIASPROG⁴= 1, FULLBIAS⁴= 0

Hysteresis (V_CM= 1.25 V,

BIASPROG⁴= 0x10, FULL-

BIAS⁴= 1)

V_ACMPHYST

-3

—

3

mV

5

12

18

33

27

50

mV

μs

17

46

65

23

57

82

26

68

98

30

79

130

150

3

34

90

-3

0

-27

-50

-65

-82

-98

-130

-150

—

-18

-33

-45

-57

-67

-78

-88

30

-5

-12

-17

-23

-26

-30

-34

—

Comparator delay³

t_ACMPDELAY

BIASPROG⁴= 0x10, FULLBIAS⁴

= 0

—

3.7

—

μs

BIASPROG⁴= 0x02, FULLBIAS⁴

= 1

—

360

35

—

35

ns

BIASPROG⁴= 0x20, FULLBIAS⁴

= 1

BIASPROG⁴=0x10, FULLBIAS⁴

= 1

Offset voltage

V_ACMPOFFSET

-35

—

mV

Reference Voltage

V_ACMPREF

Internal 1.25 V reference

Internal 2.5 V reference

1

2

1.25

2.5

inf

1.47

2.8

—

V

CSRESSEL⁶= 0

CSRESSEL⁶= 1

CSRESSEL⁶= 2

CSRESSEL⁶= 3

CSRESSEL⁶= 4

CSRESSEL⁶= 5

CSRESSEL⁶= 6

CSRESSEL⁶= 7

Capacitive sense internal re- R_CSRES

sistance

—

kΩ

—

15

27

—

kΩ

39

51

100

162

235

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Electrical Specifications

Parameter

Note:

Symbol

Test Condition

Min

Typ

Max

Unit

1. ACMPVDD is a supply chosen by the setting in ACMPn_CTRL_PWRSEL and may be IOVDD, AVDD or DVDD

2. The total ACMP current is the sum of the contributions from the ACMP and its internal voltage reference. I_ACMPTOTAL= I_ACMP

I_ACMPREF

+

3. ± 100 mV differential drive

4. In ACMPn_CTRL register

5. In ACMPn_HYSTERESIS register

6. In ACMPn_INPUTSEL register

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Electrical Specifications

4.1.15 Digital to Analog Converter (VDAC)

DRIVESTRENGTH = 2 unless otherwise specified.

Table 4.25. Digital to Analog Converter (VDAC)

Parameter

Symbol

Test Condition

Min

0

Typ

—

Max

Unit

V

Output voltage

V_DACOUT

Single-Ended

V_VREF

Differential²

-V_VREF

—

V

Current consumption includ- I_DAC

ing references (2 channels)¹

500 ksps, 12-bit,

DRIVESTRENGTH = 2,

REFSEL = 4

—

396

—

μA

44.1 ksps, 12-bit,

DRIVESTRENGTH = 1,

REFSEL = 4

72

200 Hz refresh rate, 12-bit Sam-

ple- Off mode in EM2, DRIVES-

TRENGTH = 2, BGRREQTIME =

1, EM2REFENTIME = 9, REFSEL

= 4, SETTLETIME = 0x0A, WAR-

MUPTIME = 0x02

1.2

Current from HFPERCLK⁴

Sample rate

I_{DAC_CLK}

—

2

5.8

—

500

1

μA/MHz

ksps

MHz

μs

SR_DAC

DAC clock frequency

Conversion time

Settling time

f_DAC

—

t_DACCONV

t_DACSETTLE

t_DACSTARTUP

f_DAC= 1MHz

—

50% fs step settling to 2 LSB

—

2.5

—

μs

Startup time

Enable to 90% fs output, settling

to 10 LSB

12

μs

Output impedance

R_OUT

DRIVESTRENGTH = 2, 0.4 V ≤

V_OUT≤ V_OPA- 0.4 V, -8 mA <

I_OUT< 8 mA, Full supply range

—

2

—

Ω

DRIVESTRENGTH = 0 or 1, 0.4 V

≤ V_OUT≤ V_OPA- 0.4 V, -400 μA <

I_OUT< 400 μA, Full supply range

DRIVESTRENGTH = 2, 0.1 V ≤

V_OUT≤ V_OPA- 0.1 V, -2 mA <

I_OUT< 2 mA, Full supply range

2

Ω

DRIVESTRENGTH = 0 or 1, 0.1 V

≤ V_OUT≤ V_OPA- 0.1 V, -100 μA <

I_OUT< 100 μA

2

Ω

Power supply rejection ratio⁶

PSRR

Vout = 50% fs. DC

65.5

dB

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Signal to noise and distortion SNDR_DAC

ratio (1 kHz sine wave),

Noise band limited to 250

kHz

500 ksps, single-ended, internal

1.25V reference

—

60.4

—

dB

500 ksps, single-ended, internal

2.5V reference

—

61.6

64.0

63.3

64.4

65.8

65.3

66.7

70.0

67.8

69.0

68.5

—

dB

500 ksps, single-ended, 3.3V

VDD reference

500 ksps, differential, internal

1.25V reference

500 ksps, differential, internal

2.5V reference

500 ksps, differential, 3.3V VDD

reference

Signal to noise and distortion SNDR_{DAC_BAND}500 ksps, single-ended, internal

ratio (1 kHz sine wave).

Noise band limited to 22

kHz.

1.25V reference

500 ksps, single-ended, internal

2.5V reference

500 ksps, single-ended, 3.3V

VDD reference

500 ksps, differential, internal

1.25V reference

500 ksps, differential, internal

2.5V reference

500 ksps, differential, 3.3VDD ref-

erence

Total harmonic distortion

THD

—

70.2

—

1

dB

Differential non-linearity³

Intergral non-linearity

DNL_DAC

-0.99

LSB

INL_DAC

-4

-8

—

4

8

LSB

mV

Offset error⁵

V_OFFSET

T = 25 °C

Across operating temperature

range

-25

25

Gain error⁵

V_GAIN

T= 25 °C, Low-noise internal ref-

erence (REFSEL = 1V25LN or

2V5LN)

-1.5

—

1.5

%

T = 25 °C, Internal reference (RE-

FSEL = 1V25 or 2V5)

-5

—

5

%

T = 25 °C, External reference

(REFSEL = VDD or EXT)

-1.5

-3.5

1.5

3.5

Across operating temperature

range, Low-noise internal refer-

ence (REFSEL = 1V25LN or

2V5LN)

Across operating temperature

range, Internal reference (RE-

FSEL = 1V25 or 2V5)

-7.5

-1.5

—

7.5

1.5

%

Across operating temperature

range, External reference (RE-

FSEL = VDD or EXT)

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

External Load Capactiance, C_LOAD

OUTSCALE=0

—

75

pF

Note:

1. Supply current specifications are for VDAC circuitry operating with static output only and do not include current required to drive

the load.

2. In differential mode, the output is defined as the difference between two single-ended outputs. Absolute voltage on each output is

limited to the single-ended range.

3. Entire range is monotonic and has no missing codes.

4. Current from HFPERCLK is dependent on HFPERCLK frequency. This current contributes to the total supply current used when

the clock to the DAC module is enabled in the CMU.

5. Gain is calculated by measuring the slope from 10% to 90% of full scale. Offset is calculated by comparing actual VDAC output at

10% of full scale to ideal VDAC output at 10% of full scale with the measured gain.

6. PSRR calculated as 20 * log10(ΔVDD / ΔVOUT), VDAC output at 90% of full scale.

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Electrical Specifications

4.1.16 Current Digital to Analog Converter (IDAC)

Table 4.26. Current Digital to Analog Converter (IDAC)

Parameter

Symbol

Test Condition

Min

—

Typ

4

Max

—

Unit

-

Number of ranges

Output current

N_{IDAC_RANGES}

I_{IDAC_OUT}

RANGSEL¹= RANGE0

RANGSEL¹= RANGE1

RANGSEL¹= RANGE2

RANGSEL¹= RANGE3

0.05

—

1.6

μA

1.6

0.5

2

—

32

4.7

16

64

—

μA

Linear steps within each

range

N_{IDAC_STEPS}

—

RANGSEL¹= RANGE0

RANGSEL¹= RANGE1

RANGSEL¹= RANGE2

RANGSEL¹= RANGE3

Step size

SS_IDAC

—

-3

50

100

500

2

—

3

nA

μA

%

Total accuracy, STEPSEL¹=

0x80

ACC_IDAC

EM0 or EM1, AVDD=3.3 V, T = 25

°C

—

EM0 or EM1, Across operating

temperature range

-18

—

-2

22

—

%

EM2 or EM3, Source mode,

RANGSEL¹= RANGE0,

AVDD=3.3 V, T = 25 °C

EM2 or EM3, Source mode,

RANGSEL¹= RANGE1,

AVDD=3.3 V, T = 25 °C

—

-1.7

-0.8

-0.5

-0.7

-0.6

-0.5

5

—

%

EM2 or EM3, Source mode,

RANGSEL¹= RANGE2,

AVDD=3.3 V, T = 25 °C

%

EM2 or EM3, Source mode,

RANGSEL¹= RANGE3,

AVDD=3.3 V, T = 25 °C

%

EM2 or EM3, Sink mode, RANG-

SEL¹= RANGE0, AVDD=3.3 V, T

= 25 °C

%

EM2 or EM3, Sink mode, RANG-

SEL¹= RANGE1, AVDD=3.3 V, T

= 25 °C

%

EM2 or EM3, Sink mode, RANG-

SEL¹= RANGE2, AVDD=3.3 V, T

= 25 °C

%

EM2 or EM3, Sink mode, RANG-

SEL¹= RANGE3, AVDD=3.3 V, T

= 25 °C

%

μs

Start up time

t_{IDAC_SU}

Output within 1% of steady state

value

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

—

Typ

5

Max

—

Unit

μs

Settling time, (output settled t_{IDAC_SETTLE}

within 1% of steady state val-

ue),

Range setting is changed

Step value is changed

—

1

—

μs

Current consumption²

I_IDAC

EM0 or EM1 Source mode, ex-

cluding output current, Across op-

erating temperature range

—

11

13

18

21

μA

EM0 or EM1 Sink mode, exclud-

ing output current, Across operat-

ing temperature range

EM2 or EM3 Source mode, ex-

cluding output current, T = 25 °C

—

0.023

0.041

11

—

μA

%

EM2 or EM3 Sink mode, exclud-

ing output current, T = 25 °C

EM2 or EM3 Source mode, ex-

cluding output current, T ≥ 85 °C

EM2 or EM3 Sink mode, exclud-

ing output current, T ≥ 85 d °C

13

Output voltage compliance in I_{COMP_SRC}

source mode, source current

change relative to current

sourced at 0 V

RANGESEL1=0, output voltage =

min(V_IOVDD, V_AVDD²-100 mv)

0.11

RANGESEL1=1, output voltage =

min(V_IOVDD, V_AVDD²-100 mV)

—

0.06

0.04

0.03

—

%

RANGESEL1=2, output voltage =

min(V_IOVDD, V_AVDD²-150 mV)

RANGESEL1=3, output voltage =

min(V_IOVDD, V_AVDD²-250 mV)

Output voltage compliance in I_{COMP_SINK}

sink mode, sink current

change relative to current

sunk at IOVDD

RANGESEL1=0, output voltage =

100 mV

—

0.12

0.05

0.04

0.03

—

%

RANGESEL1=1, output voltage =

100 mV

RANGESEL1=2, output voltage =

150 mV

RANGESEL1=3, output voltage =

250 mV

Note:

1. In IDAC_CURPROG register.

2. The IDAC is supplied by either AVDD, DVDD, or IOVDD based on the setting of ANASW in the EMU_PWRCTRL register and

PWRSEL in the IDAC_CTRL register. Setting PWRSEL to 1 selects IOVDD. With PWRSEL cleared to 0, ANASW selects be-

tween AVDD (0) and DVDD (1).

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Electrical Specifications

4.1.17 Capacitive Sense (CSEN)

Table 4.27. Capacitive Sense (CSEN)

Parameter

Symbol

t_CNV

Test Condition

Min

—

Typ

20.2

26.4

1.55

Max

—

Unit

μs

Single conversion time (1x

accumulation)

12-bit SAR Conversions

16-bit SAR Conversions

—

μs

Delta Modulation Conversion (sin-

gle comparison)

—

μs

Maximum external capactive C_EXTMAX

load

CS0CG=7 (Gain = 1x), including

routing parasitics

—

68

680

1

—

pF

kΩ

nA

CS0CG=0 (Gain = 10x), including

routing parasitics

Maximum external series im- R_EXTMAX

pedance

Supply current, EM2 bonded I_{CSEN_BOND}

conversions, WARMUP-

MODE=NORMAL, WAR-

MUPCNT=0

12-bit SAR conversions, 20 ms

conversion rate, CS0CG=7 (Gain

= 1x), 10 channels bonded (total

capacitance of 330 pF)¹

326

Delta Modulation conversions, 20

ms conversion rate, CS0CG=7

(Gain = 1x), 10 channels bonded

—

226

33

—

nA

(total capacitance of 330 pF)¹

12-bit SAR conversions, 200 ms

conversion rate, CS0CG=7 (Gain

= 1x), 10 channels bonded (total

capacitance of 330 pF)¹

Delta Modulation conversions,

200 ms conversion rate,

25

CS0CG=7 (Gain = 1x), 10 chan-

nels bonded (total capacitance of

330 pF)¹

Supply current, EM2 scan

conversions, WARMUP-

MODE=NORMAL, WAR-

MUPCNT=0

I_{CSEN_EM2}

12-bit SAR conversions, 20 ms

scan rate, CS0CG=0 (Gain =

—

690

515

—

nA

10x), 8 samples per scan¹

Delta Modulation conversions, 20

ms scan rate, 8 comparisons per

sample (DMCR = 1, DMR = 2),

CS0CG=0 (Gain = 10x), 8 sam-

ples per scan¹

12-bit SAR conversions, 200 ms

scan rate, CS0CG=0 (Gain =

—

79

57

—

nA

10x), 8 samples per scan¹

Delta Modulation conversions,

200 ms scan rate, 8 comparisons

per sample (DMCR = 1, DMR =

2), CS0CG=0 (Gain = 10x), 8

samples per scan¹

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Supply current, continuous

conversions, WARMUP-

MODE= KEEPCSENWARM

I_{CSEN_ACTIVE}

SAR or Delta Modulation conver-

sions of 33 pF capacitor,

CS0CG=0 (Gain = 10x), always

on

—

90.5

—

μA

HFPERCLK supply current

I_{CSEN_HFPERCLK}Current contribution from

HFPERCLK when clock to CSEN

block is enabled.

—

2.25

—

μA/MHz

Note:

1. Current is specified with a total external capacitance of 33 pF per channel. Average current is dependent on how long the module

is actively sampling channels within the scan period, and scales with the number of samples acquired. Supply current for a specif-

ic application can be estimated by multiplying the current per sample by the total number of samples per period (total_current =

single_sample_current * (number_of_channels * accumulation)).

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Electrical Specifications

4.1.18 Operational Amplifier (OPAMP)

Unless otherwise indicated, specified conditions are: Non-inverting input configuration, VDD = 3.3 V, DRIVESTRENGTH = 2, MAIN-

OUTEN = 1, C_LOAD= 75 pF with OUTSCALE = 0, or C_LOAD= 37.5 pF with OUTSCALE = 1. Unit gain buffer and 3X-gain connection as

specified in table footnotes^{8 1}

.

Table 4.28. Operational Amplifier (OPAMP)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Supply voltage

V_OPA

HCMDIS = 0, Rail-to-rail input

range

2

—

3.8

V

HCMDIS = 1

1.62

—

3.8

V

Input voltage

V_IN

HCMDIS = 0, Rail-to-rail input

range

V_VSS

V_OPA

HCMDIS = 1

V_VSS

100

V_VSS

—

V_OPA-1.2

—

V

MΩ

V

Input impedance

Output voltage

R_IN

V_OUT

C_LOAD

—

V_OPA

75

Load capacitance²

OUTSCALE = 0

OUTSCALE = 1

—

pF

Ω

—

37.5

—

Output impedance

R_OUT

DRIVESTRENGTH = 2 or 3, 0.4 V

≤ V_OUT≤ V_OPA- 0.4 V, -8 mA <

I_OUT< 8 mA, Buffer connection,

Full supply range

—

0.25

DRIVESTRENGTH = 0 or 1, 0.4 V

≤ V_OUT≤ V_OPA- 0.4 V, -400 μA <

I_OUT< 400 μA, Buffer connection,

Full supply range

—

0.6

0.4

1

—

Ω

DRIVESTRENGTH = 2 or 3, 0.1 V

≤ V_OUT≤ V_OPA- 0.1 V, -2 mA <

I_OUT< 2 mA, Buffer connection,

Full supply range

DRIVESTRENGTH = 0 or 1, 0.1 V

≤ V_OUT≤ V_OPA- 0.1 V, -100 μA <

I_OUT< 100 μA, Buffer connection,

Full supply range

Internal closed-loop gain

Active current⁴

G_CL

Buffer connection

3x Gain connection

16x Gain connection

0.99

2.93

15.07

—

1

1.01

3.05

16.33

—

-

2.99

15.7

580

-

I_OPA

DRIVESTRENGTH = 3, OUT-

SCALE = 0

μA

DRIVESTRENGTH = 2, OUT-

SCALE = 0

—

176

13

—

μA

DRIVESTRENGTH = 1, OUT-

SCALE = 0

DRIVESTRENGTH = 0, OUT-

SCALE = 0

4.7

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

—

Typ

135

137

121

109

3.38

Max

—

Unit

dB

Open-loop gain

G_OL

DRIVESTRENGTH = 3

DRIVESTRENGTH = 2

DRIVESTRENGTH = 1

DRIVESTRENGTH = 0

—

dB

—

dB

—

dB

Loop unit-gain frequency⁷

UGF

DRIVESTRENGTH = 3, Buffer

connection

—

MHz

DRIVESTRENGTH = 2, Buffer

connection

—

0.9

132

34

—

MHz

kHz

DRIVESTRENGTH = 1, Buffer

connection

DRIVESTRENGTH = 0, Buffer

connection

kHz

DRIVESTRENGTH = 3, 3x Gain

connection

2.57

0.71

113

28

MHz

kHz

DRIVESTRENGTH = 2, 3x Gain

connection

DRIVESTRENGTH = 1, 3x Gain

connection

DRIVESTRENGTH = 0, 3x Gain

connection

kHz

Phase Margin

PM

DRIVESTRENGTH = 3, Buffer

connection

67

°

DRIVESTRENGTH = 2, Buffer

connection

69

°

DRIVESTRENGTH = 1, Buffer

connection

63

°

DRIVESTRENGTH = 0, Buffer

connection

68

°

Output voltage noise

N_OUT

DRIVESTRENGTH = 3, Buffer

connection, 10 Hz - 10 MHz

146

163

170

176

313

271

247

245

μVrms

DRIVESTRENGTH = 2, Buffer

connection, 10 Hz - 10 MHz

DRIVESTRENGTH = 1, Buffer

connection, 10 Hz - 10 MHz

DRIVESTRENGTH = 0, Buffer

connection, 10 Hz - 10 MHz

DRIVESTRENGTH = 3, 3x Gain

connection

DRIVESTRENGTH = 2, 3x Gain

connection, 10 Hz - 10 MHz

DRIVESTRENGTH = 1, 3x Gain

connection, 10 Hz - 10 MHz

DRIVESTRENGTH = 0, 3x Gain

connection, 10 Hz - 10 MHz

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Slew rate⁵

SR

DRIVESTRENGTH = 3,

INCBW=1³

—

4.7

—

V/μs

DRIVESTRENGTH = 3,

INCBW=0

—

1.5

—

V/μs

DRIVESTRENGTH = 2,

INCBW=1³

1.27

DRIVESTRENGTH = 2,

INCBW=0

—

0.42

0.17

—

V/μs

DRIVESTRENGTH = 1,

INCBW=1³

DRIVESTRENGTH = 1,

INCBW=0

—

0.058

0.044

—

V/μs

DRIVESTRENGTH = 0,

INCBW=1³

DRIVESTRENGTH = 0,

INCBW=0

—

0.015

—

V/μs

Startup time⁶

T_START

V_OSI

DRIVESTRENGTH = 2

—

-2

—

12

2

μs

Input offset voltage

DRIVESTRENGTH = 2 or 3, T_J=

25 °C

mV

DRIVESTRENGTH = 1 or 0, T_J=

25 °C

-2

—

2

mV

DRIVESTRENGTH = 2 or 3,

across operating temperature

range

-12

12

DRIVESTRENGTH = 1 or 0,

across operating temperature

range

-30

—

30

mV

DC power supply rejection

ratio₉

PSRR_DC

Input referred

—

70

90

—

dB

DC common-mode rejection CMRR_DC

ratio₉

Input referred

Total harmonic distortion

THD_OPA

DRIVESTRENGTH = 2, 3x Gain

connection, 1 kHz, V_OUT= 0.1 V

to V_OPA- 0.1 V

DRIVESTRENGTH = 0, 3x Gain

connection, 0.01 kHz, V_OUT= 0.1

V to V_OPA- 0.1 V

—

90

—

dB

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Electrical Specifications

Parameter

Note:

Symbol

Test Condition

Min

Typ

Max

Unit

1. Specified configuration for 3X-Gain configuration is: INCBW = 1, HCMDIS = 1, RESINSEL = VSS, V_INPUT= 0.5 V, V_OUTPUT= 1.5

V. Nominal voltage gain is 3.

2. If the maximum C_LOADis exceeded, an isolation resistor is required for stability. See AN0038 for more information.

3. When INCBW is set to 1 the OPAMP bandwidth is increased. This is allowed only when the non-inverting close-loop gain is ≥ 3,

or the OPAMP may not be stable.

4. Current into the load resistor is excluded. When the OPAMP is connected with closed-loop gain > 1, there will be extra current to

drive the resistor feedback network. The internal resistor feedback network has total resistance of 143.5 kOhm, which will cause

another ~10 μA current when the OPAMP drives 1.5 V between output and ground.

5. Step between 0.2V and V_OPA-0.2V, 10%-90% rising/falling range.

6. From enable to output settled. In sample-and-off mode, RC network after OPAMP will contribute extra delay. Settling error < 1mV.

7. In unit gain connection, UGF is the gain-bandwidth product of the OPAMP. In 3x Gain connection, UGF is the gain-bandwidth

product of the OPAMP and 1/3 attenuation of the feedback network.

8. Specified configuration for Unit gain buffer configuration is: INCBW = 0, HCMDIS = 0, RESINSEL = DISABLE. VINPUT = 0.5 V,

VOUTPUT = 0.5 V.

9. When HCMDIS=1 and input common mode transitions the region from VOPA-1.4V to VOPA-1V, input offset will change. PSRR

and CMRR specifications do not apply to this transition region.

4.1.19 Pulse Counter (PCNT)

Table 4.29. Pulse Counter (PCNT)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Input frequency

F_IN

Asynchronous Single and Quad-

rature Modes

—

20

MHz

Sampled Modes with Debounce

filter set to 0.

—

8

kHz

4.1.20 Analog Port (APORT)

Table 4.30. Analog Port (APORT)

Parameter

Symbol

Test Condition

Min

—

Typ

7

Max

—

Unit

μA

Supply current^{1, 2}

I_APORT

Operation in EM0/EM1

Operation in EM2/EM3

—

915

—

nA

Note:

1. Specified current is for continuous APORT operation. In applications where the APORT is not requested continuously (e.g. peri-

odic ACMP requests from LESENSE in EM2), the average current requirements can be estimated by mutiplying the duty cycle of

the requests by the specified continuous current number.

2. Supply current increase that occurs when an analog peripheral requests access to APORT. This current is not included in repor-

ted module currents. Additional peripherals requesting access to APORT do not incur further current.

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Electrical Specifications

4.1.21 I2C

4.1.21.1 I2C Standard-mode (Sm)¹

Table 4.31. I2C Standard-mode (Sm)¹

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

SCL clock frequency²

SCL clock low time

SCL clock high time

SDA set-up time

f_SCL

0

—

100

kHz

t_LOW

4.7

4

—

μs

ns

μs

t_HIGH

t_{SU_DAT}

t_{HD_DAT}

250

100

4.7

—

SDA hold time³

3450

—

Repeated START condition t_{SU_STA}

set-up time

(Repeated) START condition t_{HD_STA}

hold time

4

—

μs

STOP condition set-up time t_{SU_STO}

4

—

μs

Bus free time between a

t_BUF

4.7

STOP and START condition

Note:

1. For CLHR set to 0 in the I2Cn_CTRL register

2. For the minimum HFPERCLK frequency required in Standard-mode, refer to the I2C chapter in the reference manual

3. The maximum SDA hold time (t_{HD_DAT}) needs to be met only when the device does not stretch the low time of SCL (t_LOW

)

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Electrical Specifications

4.1.21.2 I2C Fast-mode (Fm)¹

Table 4.32. I2C Fast-mode (Fm)¹

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

SCL clock frequency²

SCL clock low time

SCL clock high time

SDA set-up time

f_SCL

0

—

400

kHz

t_LOW

1.3

0.6

—

μs

ns

μs

t_HIGH

t_{SU_DAT}

t_{HD_DAT}

100

0.6

—

SDA hold time³

900

—

Repeated START condition t_{SU_STA}

set-up time

(Repeated) START condition t_{HD_STA}

hold time

0.6

—

μs

STOP condition set-up time t_{SU_STO}

0.6

1.3

—

μs

Bus free time between a

t_BUF

STOP and START condition

Note:

1. For CLHR set to 1 in the I2Cn_CTRL register

2. For the minimum HFPERCLK frequency required in Fast-mode, refer to the I2C chapter in the reference manual

3. The maximum SDA hold time (t_HD,DAT) needs to be met only when the device does not stretch the low time of SCL (t_LOW

)

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Electrical Specifications

4.1.21.3 I2C Fast-mode Plus (Fm+)¹

Table 4.33. I2C Fast-mode Plus (Fm+)¹

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

SCL clock frequency²

SCL clock low time

SCL clock high time

SDA set-up time

f_SCL

0

—

1000

kHz

t_LOW

0.5

0.26

50

—

μs

ns

μs

t_HIGH

t_{SU_DAT}

t_{HD_DAT}

SDA hold time

100

0.26

Repeated START condition t_{SU_STA}

set-up time

(Repeated) START condition t_{HD_STA}

hold time

0.26

—

μs

STOP condition set-up time t_{SU_STO}

0.26

0.5

—

μs

Bus free time between a

t_BUF

STOP and START condition

Note:

1. For CLHR set to 0 or 1 in the I2Cn_CTRL register

2. For the minimum HFPERCLK frequency required in Fast-mode Plus, refer to the I2C chapter in the reference manual

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Electrical Specifications

4.1.22 USART SPI

SPI Master Timing

Table 4.34. SPI Master Timing

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

SCLK period ^{1 3 2}

t_SCLK

2 *

t_HFPERCLK

—

ns

CS to MOSI ^{1 3}

t_{CS_MO}

t_{SCLK_MO}

t_{SU_MI}

-14.5

-8.5

—

13.5

8

ns

SCLK to MOSI ^{1 3}

MISO setup time ^{1 3}

IOVDD = 1.62 V

IOVDD = 3.0 V

92

42

—

ns

MISO hold time ^{1 3}

t_{H_MI}

-10

Note:

1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0).

2. t_HFPERCLKis one period of the selected HFPERCLK.

3. Measurement done with 8 pF output loading at 10% and 90% of V_DD(figure shows 50% of V_DD).

t_{CS_MO}

CS

t_{SCKL_MO}

SCLK

CLKPOL = 0

t_SCLK

SCLK

CLKPOL = 1

MOSI

MISO

t_{SU_MI}

t_{H_MI}

Figure 4.1. SPI Master Timing Diagram

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Electrical Specifications

SPI Slave Timing

Table 4.35. SPI Slave Timing

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

SCLK period ^{1 3 2}

t_SCLK

6 *

t_HFPERCLK

—

ns

SCLK high time^{1 3 2}

SCLK low time^{1 3 2}

t_{SCLK_HI}

2.5 *

t_HFPERCLK

—

ns

t_{SCLK_LO}

2.5 *

t_HFPERCLK

CS active to MISO ^{1 3}

CS disable to MISO ^{1 3}

MOSI setup time ^{1 3}

MOSI hold time ^{1 3 2}

SCLK to MISO ^{1 3 2}

t_{CS_ACT_MI}

t_{CS_DIS_MI}

t_{SU_MO}

4

8

7

—

70

50

—

ns

t_{H_MO}

t_{SCLK_MI}

10 + 1.5*

t_HFPERCLK

65 + 2.5 *

t_HFPERCLK

Note:

1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0)

2. t_HFPERCLKis one period of the selected HFPERCLK

3. Measurement done with 8 pF output loading at 10% and 90% of V_DD(figure shows 50% of V_DD

)

t_{CS_ACT_MI}

CS

t_{CS_DIS_MI}

SCLK

CLKPOL = 0

t_{SCLK_HI}

t_{SCLK_LO}

SCLK

t_{SU_MO}

CLKPOL = 1

t_SCLK

t_{H_MO}

MOSI

MISO

t_{SCLK_MI}

Figure 4.2. SPI Slave Timing Diagram

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Typical Connection Diagrams

5. Typical Connection Diagrams

5.1 Network Co-Processor (NCP) Application with UART Host

The MGM12P can be controlled over the UART interface as a peripheral to an external host processor. Typical power supply, program-

ming/debug, and host interface connections are shown in the figure below. Refer to AN958: Debugging and Programming Interfaces for

Custom Designs for more details.

Figure 5.1. Connection Diagram: UART NCP Configuration

5.2 Network Co-Processor (NCP) Application with SPI Host

The MGM12P can be controlled over the SPI interface as a peripheral to an external host processor. Typical power supply, program-

ming/debug and host interface connections are shown in the figure below. Refer to AN958: Debugging and Programming Interfaces for

Custom Designs for more details.

Figure 5.2. Connection Diagram: SPI NCP Configuration

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Typical Connection Diagrams

5.3 SoC Application

The MGM12P can be used in a standalone SoC configuration with no external host processor. Typical power supply and programming/

debug connections are shown in the figure below. Refer to AN958: Debugging and Programming Interfaces for Custom Designs for

more details.

Figure 5.3. Connection Diagram: SoC Configuration

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Layout Guidelines

6. Layout Guidelines

For optimal performance of the MGM12P (with integrated antenna), please follow the PCB layout guidelines and ground plane recom-

mendations indicated in this section.

6.1 Module Placement and Application PCB Layout Guidelines

• Place the module at the edge of the PCB, as shown in the figure below.

• Do not place any metal (traces, components, battery, etc.) within the clearance area of the antenna (shown in the figure below).

• Connect all ground pads directly to a solid ground plane.

• Place the ground vias as close to the ground pads as possible.

• Do not place plastic or any other dielectric material in touch with the antenna.

Figure 6.1. Recommended Application PCB Layout for MGM12P with Integrated Antenna

The layouts in the next figure will result in severely degraded RF-performance.

Figure 6.2. Non-optimal Module Placements for MGM12P with Integrated Antenna

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Layout Guidelines

Figure 6.3. Impact of GND Plane Size vs. Range for MGM12P

6.2 Effect of Plastic and Metal Materials

Do not place plastic or any other dielectric material in closs proximity to the antenna.

Any metallic objects in close proximity to the antenna will prevent the antenna from radiating freely. The minimum recommended dis-

tance of metallic and/or conductive objects is 10 mm in any direction from the antenna except in the directions of the application PCB

ground planes.

6.3 Locating the Module Close to Human Body

Placing the module in touch or very close to the human body will negatively impact antenna efficiency and reduce range.

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Layout Guidelines

6.4 2D Radiation Pattern Plots

Figure 6.4. Typical 2D Radiation Pattern – Front View

Figure 6.5. Typical 2D Radiation Pattern – Side View

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Layout Guidelines

Figure 6.6. Typical 2D Radiation Pattern – Top View

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Hardware Design Guidelines

7. Hardware Design Guidelines

The MGM12P is an easy-to-use module with regard to hardware application design but certain design guidelines must be followed to

guarantee optimal performance. These guidelines are listed in the next sub-sections.

7.1 Power Supply Requirements

Coin cell batteries cannot withstand high peak currents (e.g. higher than 15 mA). If the peak current exceeds 15 mA it’s recommended

to place 47 - 100 µF capacitor in parallel with the coin cell battery to improve the battery life time. Notice that the total current consump-

tion of your application is a combination of the radio, peripherals and MCU current consumption so you must take all of these into ac-

count. MGM12P should be powered by a unipolar supply voltage with nominal value of 3.3 V.

7.2 Reset Functions

The MGM12P can be reset by three different methods: by pulling the RESET line low, by the internal watchdog timer or software com-

mand. The reset state in MGM12P does not provide any power saving functionality and thus is not recommended as a means to con-

serve power. MGM12P has an internal system power-up reset function. The RESET pin includes an on-chip pull-up resistor and can

therefore be left unconnected if no external reset switch or source is needed.

7.3 Debug and Firmware Updates

This section contains information on debug and firmware update methods. For additional information, refer to the following application

note: AN958: Debugging and Programming Interfaces for Custom Designs.

7.3.1 Programming and Debug Connections

It is recommended to expose the debug pins in your own hardware design for firmware update and debug purposes. The following table

lists the required pins for JTAG connection and SWD connections.

The debug pins have pull-down and pull-up enabled by default, so leaving them enabled may increase current consumption if left con-

nected to supply or ground. If enabling the JTAG pins the module must be power cycled to enable a SWD debug session.

Table 7.1. JTAG Pads

PAD NAME

PAD NUMBER

JTAG SIGNAL NAME

SWD SIGNAL NAME

COMMENTS

PF3

24

TDI

N/A

This pin is disabled after

reset. Once enabled the

pin has a built-in pull-up.

PF2

PF1

PF0

23

22

21

TDO

TMS

TCK

N/A

This pin is disabled after

reset

SWDIO

SWCLK

Pin is enabled after reset

and has a built-in pull-up

Pin is enabled after reset

and has a built-in pull-

down

7.3.2 Packet Trace Interface (PTI)

The MGM12P integrates a true PHY-level PTI with the MAC, allowing complete, non-intrusive capture of all packets to and from the

EFR32 Wireless STK development tools.

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Pin Definitions

8. Pin Definitions

8.1 Pin Definitions

GND

PD13

PD14

PD15

PA0

GND

RESETn

VDD

PF7

1

2

31

30

29

28

27

26

25

24

23

22

21

20

MGM12P

TOP VIEW

3

4

PF6

5

PA1

PF5

6

PA2

PF4

7

PA3

PF3

8

PA4

PF2

9

PA5

PF1

10

11

12

PB11

GND

PF0

GND

19

17 18

13 14 15 16

Figure 8.1. MGM12P Pinout

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Pin Definitions

Table 8.1. MGM12P Device Pinout

Pin Name

Pin(s) Description

Pin Name

Pin(s) Description

1

12

GND

Ground

20

PD13

2

GPIO

31

PD14

PA0

PA2

PA4

PB11

PC6

PC8

PC10

PF0

3

GPIO

PD15

PA1

PA3

PA5

PB13

PC7

PC9

PC11

PF1

4

GPIO

5

GPIO

6

GPIO

7

GPIO

8

GPIO

9

GPIO

10

13

15

17

19

22

24

26

28

GPIO (5V)

GPIO

11

14

16

18

21

23

25

27

GPIO

GPIO (5V)

PF2

PF3

PF4

PF5

PF6

PF7

Reset input, active low. To apply an ex-

ternal reset source to this pin, it is re-

quired to only drive this pin low during

reset, and let the internal pull-up ensure

that reset is released.

VDD

29

Module Power Supply

RESETn

30

Note:

1. GPIO with 5V tolerance are indicated by (5V).

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Pin Definitions

8.1.1 GPIO Overview

The GPIO pins are organized as 16-bit ports indicated by letters A through F, and the individual pins on each port are indicated by a

number from 15 down to 0.

Table 8.2. GPIO Pinout

Port

15

14

13

12

11

Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0

10

PA5

(5V)

Port A

Port B

Port C

-

PB13

-

PA4 PA3 PA2 PA1 PA0

PB11

-

PC11 PC10 PC9 PC8 PC7 PC6

(5V) (5V) (5V) (5V) (5V) (5V)

-

Port D

Port E

PD15 PD14 PD13

-

PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0

(5V) (5V) (5V) (5V) (5V) (5V) (5V) (5V)

Port F

-

Note:

1. GPIO with 5V tolerance are indicated by (5V).

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Pin Definitions

8.2 Alternate Functionality Pinout

A wide selection of alternate functionality is available for multiplexing to various pins. The following table shows the name of the alter-

nate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.

Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout

is shown in the column corresponding to LOCATION 0.

Table 8.3. Alternate Functionality Overview

Alternate

LOCATION

Functionality

0 - 3

4 - 7

8 - 11

12 - 15

16 - 19

20 - 23

24 - 27

28 - 31

Description

0: PA0

1: PA1

2: PA2

3: PA3

4: PA4

5: PA5

6: PB11

8: PB13

12: PC7

13: PC8

14: PC9

15: PC10

16: PC11

24: PF0

28: PF4

29: PF5

30: PF6

31: PF7

Analog comparator

ACMP0, digital out-

put.

21: PD13 25: PF1

22: PD14 26: PF2

23: PD15 27: PF3

ACMP0_O

ACMP1_O

ADC0_EXTN

ADC0_EXTP

BOOT_RX

BOOT_TX

11: PC6

8: PB13

0: PA0

1: PA1

2: PA2

3: PA3

4: PA4

5: PA5

6: PB11

12: PC7

13: PC8

14: PC9

15: PC10

16: PC11

24: PF0

21: PD13 25: PF1

22: PD14 26: PF2

23: PD15 27: PF3

28: PF4

29: PF5

30: PF6

31: PF7

Analog comparator

ACMP1, digital out-

put.

11: PC6

0: PA0

0: PA1

0: PF1

0: PF0

0: PA1

Analog to digital

converter ADC0 ex-

ternal reference in-

put negative pin.

Analog to digital

converter ADC0 ex-

ternal reference in-

put positive pin.

Bootloader RX.

Bootloader TX.

Clock Management

Unit, clock output

number 0.

5: PD14

6: PF2

7: PF7

CMU_CLK0

CMU_CLK1

CMU_CLKI0

2: PC6

3: PC11

0: PA0

Clock Management

Unit, clock output

number 1.

5: PD15

6: PF3

7: PF6

2: PC7

3: PC10

0: PB13

1: PF7

2: PC6

4: PA5

Clock Management

Unit, clock output

number I0.

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Pin Definitions

Alternate

LOCATION

12 - 15 16 - 19

Functionality

0 - 3

4 - 7

8 - 11

20 - 23

24 - 27

28 - 31

Description

0: PF0

Debug-interface

Serial Wire clock

input and JTAG

Test Clock.

DBG_SWCLKTCK

DBG_SWDIOTMS

DBG_SWO

Note that this func-

tion is enabled to

the pin out of reset,

and has a built-in

pull down.

0: PF1

Debug-interface

Serial Wire data in-

put / output and

JTAG Test Mode

Select.

Note that this func-

tion is enabled to

the pin out of reset,

and has a built-in

pull up.

0: PF2

Debug-interface

Serial Wire viewer

Output.

1: PB13

2: PD15

3: PC11

Note that this func-

tion is not enabled

after reset, and

must be enabled by

software to be

used.

0: PF3

Debug-interface

JTAG Test Data In.

Note that this func-

tion becomes avail-

able after the first

valid JTAG com-

mand is received,

and has a built-in

pull up when JTAG

is active.

DBG_TDI

0: PF2

Debug-interface

JTAG Test Data

Out.

Note that this func-

tion becomes avail-

able after the first

valid JTAG com-

mand is received.

DBG_TDO

ETM_TCLK

1: PA5

3: PC6

Embedded Trace

Module ETM clock .

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Pin Definitions

Alternate

LOCATION

Functionality

0 - 3

3: PC7

3: PC8

3: PC9

3: PC10

4 - 7

8 - 11

12 - 15

16 - 19

20 - 23

24 - 27

28 - 31

Description

Embedded Trace

Module ETM data

0.

ETM_TD0

Embedded Trace

Module ETM data

1.

ETM_TD1

Embedded Trace

Module ETM data

2.

ETM_TD2

Embedded Trace

Module ETM data

3.

ETM_TD3

0: PA0

1: PA1

2: PA2

3: PA3

4: PA4

5: PA5

6: PB11

8: PB13

11: PC6

12: PC7

13: PC8

14: PC9

15: PC10

16: PC11

24: PF0

28: PF4

29: PF5

30: PF6

31: PF7

21: PD13 25: PF1

22: PD14 26: PF2

23: PD15 27: PF3

Frame Controller,

Data Sniffer Clock.

FRC_DCLK

0: PA2

1: PA3

2: PA4

3: PA5

4: PB11

6: PB13

12: PC9

13: PC10

14: PC11

20: PD14 24: PF2

21: PD15 25: PF3

28: PF6

29: PF7

30: PA0

31: PA1

Frame Controller,

Data Sniffer Frame

active

9: PC6

10: PC7

11: PC8

FRC_DFRAME

FRC_DOUT

22: PF0

19: PD13 23: PF1

26: PF4

27: PF5

0: PA1

1: PA2

2: PA3

3: PA4

4: PA5

5: PB11

12: PC8

13: PC9

14: PC10

15: PC11

20: PD13 24: PF1

21: PD14 25: PF2

22: PD15 26: PF3

28: PF5

29: PF6

30: PF7

31: PA0

Frame Controller,

Data Sniffer Out-

put.

10: PC6

11: PC7

7: PB13

23: PF0

27: PF4

0: PF2

Pin can be used to

wake the system

up from EM4

GPIO_EM4WU0

GPIO_EM4WU1

GPIO_EM4WU4

GPIO_EM4WU8

GPIO_EM4WU9

GPIO_EM4WU12

0: PF7

Pin can be used to

wake the system

up from EM4

0: PD14

0: PA3

0: PB13

0: PC10

Pin can be used to

wake the system

up from EM4

Pin can be used to

wake the system

up from EM4

Pin can be used to

wake the system

up from EM4

Pin can be used to

wake the system

up from EM4

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Rev. 1.0 | 68

MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Pin Definitions

Alternate

LOCATION

Functionality

0 - 3

4 - 7

8 - 11

12 - 15

16 - 19

20 - 23

24 - 27

28 - 31

Description

0: PA1

1: PA2

2: PA3

3: PA4

4: PA5

5: PB11

12: PC8

13: PC9

14: PC10

15: PC11

20: PD13 24: PF1

21: PD14 25: PF2

22: PD15 26: PF3

28: PF5

29: PF6

30: PF7

31: PA0

I2C0 Serial Clock

Line input / output.

I2C0_SCL

I2C0_SDA

I2C1_SCL

I2C1_SDA

LES_CH5

LES_CH6

LES_CH7

LES_CH8

LES_CH9

LES_CH10

LES_CH11

LES_CH12

LES_CH13

10: PC6

11: PC7

7: PB13

23: PF0

27: PF4

0: PA0

1: PA1

2: PA2

3: PA3

4: PA4

5: PA5

6: PB11

8: PB13

12: PC7

13: PC8

14: PC9

15: PC10

16: PC11

24: PF0

28: PF4

29: PF5

30: PF6

31: PF7

21: PD13 25: PF1

22: PD14 26: PF2

23: PD15 27: PF3

I2C0 Serial Data in-

put / output.

11: PC6

I2C1 Serial Clock

Line input / output.

18: PC10

19: PC11

20: PC11

I2C1 Serial Data in-

put / output.

19: PC10

0: PD13

0: PD14

0: PD15

0: PA0

0: PA1

0: PA2

0: PA3

0: PA4

0: PA5

LESENSE channel

5.

LESENSE channel

6.

LESENSE channel

7.

LESENSE channel

8.

LESENSE channel

9.

LESENSE channel

10.

LESENSE channel

11.

LESENSE channel

12.

LESENSE channel

13.

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Pin Definitions

Alternate

LOCATION

Functionality

0 - 3

4 - 7

8 - 11

12 - 15

16 - 19

20 - 23

24 - 27

28 - 31

Description

0: PA0

1: PA1

2: PA2

3: PA3

4: PA4

5: PA5

6: PB11

8: PB13

12: PC7

13: PC8

14: PC9

15: PC10

16: PC11

24: PF0

28: PF4

29: PF5

30: PF6

31: PF7

Low Energy Timer

LETIM0, output

channel 0.

21: PD13 25: PF1

22: PD14 26: PF2

23: PD15 27: PF3

LETIM0_OUT0

LETIM0_OUT1

LEU0_RX

11: PC6

0: PA1

1: PA2

2: PA3

3: PA4

4: PA5

5: PB11

12: PC8

13: PC9

14: PC10

15: PC11

20: PD13 24: PF1

21: PD14 25: PF2

22: PD15 26: PF3

28: PF5

29: PF6

30: PF7

31: PA0

Low Energy Timer

LETIM0, output

channel 1.

10: PC6

11: PC7

7: PB13

23: PF0

27: PF4

0: PA1

1: PA2

2: PA3

3: PA4

4: PA5

5: PB11

12: PC8

13: PC9

14: PC10

15: PC11

20: PD13 24: PF1

21: PD14 25: PF2

22: PD15 26: PF3

28: PF5

29: PF6

30: PF7

31: PA0

LEUART0 Receive

input.

10: PC6

11: PC7

7: PB13

23: PF0

27: PF4

0: PA0

1: PA1

2: PA2

3: PA3

4: PA4

5: PA5

6: PB11

8: PB13

12: PC7

13: PC8

14: PC9

15: PC10

16: PC11

24: PF0

28: PF4

29: PF5

30: PF6

31: PF7

LEUART0 Transmit

output. Also used

as receive input in

half duplex commu-

nication.

21: PD13 25: PF1

22: PD14 26: PF2

23: PD15 27: PF3

LEU0_TX

11: PC6

0: PA3

1: PA4

2: PA5

3: PB11

8: PC6

9: PC7

10: PC8

11: PC9

12: PC10

13: PC11

20: PD15 24: PF3

28: PF7

29: PA0

30: PA1

31: PA2

MODEM antenna

control output 0,

used for antenna

diversity.

5: PB13

21: PF0

18: PD13 22: PF1

19: PD14 23: PF2

25: PF4

26: PF5

27: PF6

MODEM_ANT0

MODEM_ANT1

MODEM_DCLK

MODEM_DIN

MODEM_DOUT

OPA0_N

0: PA4

1: PA5

2: PB11

4: PB13

7: PC6

8: PC7

9: PC8

10: PC9

11: PC10

12: PC11

20: PF0

17: PD13 21: PF1

18: PD14 22: PF2

19: PD15 23: PF3

24: PF4

25: PF5

26: PF6

27: PF7

28: PA0

29: PA1

30: PA2

31: PA3

MODEM antenna

control output 1,

used for antenna

diversity.

0: PA0

1: PA1

2: PA2

3: PA3

4: PA4

5: PA5

6: PB11

8: PB13

12: PC7

13: PC8

14: PC9

15: PC10

16: PC11

24: PF0

28: PF4

29: PF5

30: PF6

31: PF7

21: PD13 25: PF1

22: PD14 26: PF2

23: PD15 27: PF3

MODEM data clock

out.

11: PC6

0: PA1

1: PA2

2: PA3

3: PA4

4: PA5

5: PB11

12: PC8

13: PC9

14: PC10

15: PC11

20: PD13 24: PF1

21: PD14 25: PF2

22: PD15 26: PF3

28: PF5

29: PF6

30: PF7

31: PA0

MODEM data in.

MODEM data out.

10: PC6

11: PC7

7: PB13

4: PB11

23: PF0

27: PF4

0: PA2

1: PA3

2: PA4

3: PA5

12: PC9

13: PC10

14: PC11

20: PD14 24: PF2

21: PD15 25: PF3

28: PF6

29: PF7

30: PA0

31: PA1

9: PC6

10: PC7

11: PC8

6: PB13

22: PF0

19: PD13 23: PF1

26: PF4

27: PF5

0: PA4

Operational Amplifi-

er 0 external nega-

tive input.

0: PA2

Operational Amplifi-

er 0 external posi-

tive input.

OPA0_P

0: PD15

0: PD13

Operational Amplifi-

er 1 external nega-

tive input.

OPA1_N

Operational Amplifi-

er 1 external posi-

tive input.

OPA1_P

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Pin Definitions

Alternate

LOCATION

Functionality

0 - 3

4 - 7

8 - 11

12 - 15

16 - 19

20 - 23

24 - 27

28 - 31

Description

0: PB13

Operational Amplifi-

er 2 external nega-

tive input.

OPA2_N

0: PB11

Operational Amplifi-

er 2 external posi-

tive input.

OPA2_P

0: PA0

1: PA1

2: PA2

3: PA3

4: PA4

5: PA5

6: PB11

8: PB13

11: PC6

12: PC7

13: PC8

14: PC9

15: PC10

16: PC11

24: PF0

28: PF4

29: PF5

30: PF6

31: PF7

Pulse Counter

PCNT0 input num-

ber 0.

21: PD13 25: PF1

22: PD14 26: PF2

23: PD15 27: PF3

PCNT0_S0IN

PCNT0_S1IN

PCNT1_S0IN

PCNT1_S1IN

PCNT2_S0IN

PCNT2_S1IN

PRS_CH0

0: PA1

1: PA2

2: PA3

3: PA4

4: PA5

5: PB11

12: PC8

13: PC9

14: PC10

15: PC11

20: PD13 24: PF1

21: PD14 25: PF2

22: PD15 26: PF3

28: PF5

29: PF6

30: PF7

31: PA0

Pulse Counter

PCNT0 input num-

ber 1.

10: PC6

11: PC7

7: PB13

23: PF0

27: PF4

20: PF7

Pulse Counter

PCNT1 input num-

ber 0.

19: PF6

Pulse Counter

PCNT1 input num-

ber 1.

18: PF6

19: PF7

20: PC11

Pulse Counter

PCNT2 input num-

ber 0.

19: PC10

Pulse Counter

PCNT2 input num-

ber 1.

18: PC10

19: PC11

0: PF0

1: PF1

2: PF2

3: PF3

4: PF4

5: PF5

6: PF6

7: PF7

8: PC6

9: PC7

10: PC8

11: PC9

12: PC10

13: PC11

Peripheral Reflex

System PRS, chan-

nel 0.

0: PF1

1: PF2

2: PF3

3: PF4

4: PF5

5: PF6

6: PF7

7: PF0

Peripheral Reflex

System PRS, chan-

nel 1.

PRS_CH1

0: PF2

1: PF3

2: PF4

3: PF5

4: PF6

5: PF7

6: PF0

7: PF1

Peripheral Reflex

System PRS, chan-

nel 2.

PRS_CH2

0: PF3

1: PF4

2: PF5

3: PF6

4: PF7

5: PF0

6: PF1

7: PF2

12: PD13

13: PD14

14: PD15

Peripheral Reflex

System PRS, chan-

nel 3.

PRS_CH3

4: PD13

5: PD14

6: PD15

Peripheral Reflex

System PRS, chan-

nel 4.

PRS_CH4

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Pin Definitions

Alternate

LOCATION

Functionality

0 - 3

4 - 7

8 - 11

12 - 15

16 - 19

20 - 23

24 - 27

28 - 31

Description

4: PD14

5: PD15

Peripheral Reflex

System PRS, chan-

nel 5.

PRS_CH5

PRS_CH6

PRS_CH7

PRS_CH8

PRS_CH9

PRS_CH10

PRS_CH11

TIM0_CC0

TIM0_CC1

TIM0_CC2

TIM0_CDTI0

TIM0_CDTI1

TIM0_CDTI2

3: PD13

0: PA0

1: PA1

2: PA2

3: PA3

4: PA4

5: PA5

6: PB11

8: PB13

16: PD14

17: PD15

Peripheral Reflex

System PRS, chan-

nel 6.

15: PD13

0: PA1

1: PA2

2: PA3

3: PA4

4: PA5

5: PB11

Peripheral Reflex

System PRS, chan-

nel 7.

10: PA0

7: PB13

4: PB11

0: PA2

1: PA3

2: PA4

3: PA5

Peripheral Reflex

System PRS, chan-

nel 8.

9: PA0

10: PA1

6: PB13

0: PA3

1: PA4

2: PA5

3: PB11

8: PA0

9: PA1

10: PA2

11: PC6

12: PC7

13: PC8

14: PC9

15: PC10

16: PC11

Peripheral Reflex

System PRS, chan-

nel 9.

5: PB13

0: PC6

1: PC7

2: PC8

3: PC9

4: PC10

5: PC11

Peripheral Reflex

System PRS, chan-

nel 10.

0: PC7

1: PC8

2: PC9

3: PC10

4: PC11

5: PC6

Peripheral Reflex

System PRS, chan-

nel 11.

0: PA0

1: PA1

2: PA2

3: PA3

4: PA4

5: PA5

6: PB11

8: PB13

11: PC6

12: PC7

13: PC8

14: PC9

15: PC10

16: PC11

24: PF0

28: PF4

29: PF5

30: PF6

31: PF7

Timer 0 Capture

Compare input /

output channel 0.

21: PD13 25: PF1

22: PD14 26: PF2

23: PD15 27: PF3

0: PA1

1: PA2

2: PA3

3: PA4

4: PA5

5: PB11

12: PC8

13: PC9

14: PC10

15: PC11

20: PD13 24: PF1

21: PD14 25: PF2

22: PD15 26: PF3

28: PF5

29: PF6

30: PF7

31: PA0

Timer 0 Capture

Compare input /

output channel 1.

10: PC6

11: PC7

7: PB13

4: PB11

23: PF0

27: PF4

0: PA2

1: PA3

2: PA4

3: PA5

12: PC9

13: PC10

14: PC11

20: PD14 24: PF2

21: PD15 25: PF3

28: PF6

29: PF7

30: PA0

31: PA1

Timer 0 Capture

Compare input /

output channel 2.

9: PC6

10: PC7

11: PC8

6: PB13

22: PF0

19: PD13 23: PF1

26: PF4

27: PF5

0: PA3

1: PA4

2: PA5

3: PB11

8: PC6

9: PC7

10: PC8

11: PC9

12: PC10

13: PC11

20: PD15 24: PF3

28: PF7

29: PA0

30: PA1

31: PA2

Timer 0 Compli-

mentary Dead Time

Insertion channel 0.

5: PB13

21: PF0

18: PD13 22: PF1

19: PD14 23: PF2

25: PF4

26: PF5

27: PF6

0: PA4

1: PA5

2: PB11

4: PB13

7: PC6

8: PC7

9: PC8

10: PC9

11: PC10

12: PC11

20: PF0

17: PD13 21: PF1

18: PD14 22: PF2

19: PD15 23: PF3

24: PF4

25: PF5

26: PF6

27: PF7

28: PA0

29: PA1

30: PA2

31: PA3

Timer 0 Compli-

mentary Dead Time

Insertion channel 1.

0: PA5

1: PB11

8: PC8

9: PC9

10: PC10

11: PC11

16: PD13 20: PF1

17: PD14 21: PF2

18: PD15 22: PF3

24: PF5

25: PF6

26: PF7

27: PA0

28: PA1

29: PA2

30: PA3

31: PA4

Timer 0 Compli-

mentary Dead Time

Insertion channel 2.

6: PC6

7: PC7

3: PB13

19: PF0

23: PF4

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Pin Definitions

Alternate

LOCATION

Functionality

0 - 3

4 - 7

8 - 11

12 - 15

16 - 19

20 - 23

24 - 27

28 - 31

Description

0: PA0

1: PA1

2: PA2

3: PA3

4: PA4

5: PA5

6: PB11

8: PB13

12: PC7

13: PC8

14: PC9

15: PC10

16: PC11

24: PF0

28: PF4

29: PF5

30: PF6

31: PF7

Timer 1 Capture

Compare input /

output channel 0.

21: PD13 25: PF1

22: PD14 26: PF2

23: PD15 27: PF3

TIM1_CC0

TIM1_CC1

TIM1_CC2

TIM1_CC3

US0_CLK

US0_CS

11: PC6

0: PA1

1: PA2

2: PA3

3: PA4

4: PA5

5: PB11

12: PC8

13: PC9

14: PC10

15: PC11

20: PD13 24: PF1

21: PD14 25: PF2

22: PD15 26: PF3

28: PF5

29: PF6

30: PF7

31: PA0

Timer 1 Capture

Compare input /

output channel 1.

10: PC6

11: PC7

7: PB13

4: PB11

23: PF0

27: PF4

0: PA2

1: PA3

2: PA4

3: PA5

12: PC9

13: PC10

14: PC11

20: PD14 24: PF2

21: PD15 25: PF3

28: PF6

29: PF7

30: PA0

31: PA1

Timer 1 Capture

Compare input /

output channel 2.

9: PC6

10: PC7

11: PC8

6: PB13

22: PF0

19: PD13 23: PF1

26: PF4

27: PF5

0: PA3

1: PA4

2: PA5

3: PB11

8: PC6

9: PC7

10: PC8

11: PC9

12: PC10

13: PC11

20: PD15 24: PF3

28: PF7

29: PA0

30: PA1

31: PA2

Timer 1 Capture

Compare input /

output channel 3.

5: PB13

21: PF0

18: PD13 22: PF1

19: PD14 23: PF2

25: PF4

26: PF5

27: PF6

0: PA2

1: PA3

2: PA4

3: PA5

4: PB11

6: PB13

12: PC9

13: PC10

14: PC11

20: PD14 24: PF2

21: PD15 25: PF3

28: PF6

29: PF7

30: PA0

31: PA1

9: PC6

10: PC7

11: PC8

USART0 clock in-

put / output.

22: PF0

26: PF4

27: PF5

19: PD13 23: PF1

0: PA3

1: PA4

2: PA5

3: PB11

8: PC6

9: PC7

10: PC8

11: PC9

12: PC10

13: PC11

20: PD15 24: PF3

28: PF7

29: PA0

30: PA1

31: PA2

5: PB13

21: PF0

18: PD13 22: PF1

19: PD14 23: PF2

25: PF4

26: PF5

27: PF6

USART0 chip se-

lect input / output.

0: PA4

1: PA5

2: PB11

4: PB13

7: PC6

8: PC7

9: PC8

10: PC9

11: PC10

12: PC11

20: PF0

17: PD13 21: PF1

18: PD14 22: PF2

19: PD15 23: PF3

24: PF4

25: PF5

26: PF6

27: PF7

28: PA0

29: PA1

30: PA2

31: PA3

USART0 Clear To

Send hardware

flow control input.

US0_CTS

US0_RTS

0: PA5

1: PB11

8: PC8

9: PC9

10: PC10

11: PC11

16: PD13 20: PF1

17: PD14 21: PF2

18: PD15 22: PF3

24: PF5

25: PF6

26: PF7

27: PA0

28: PA1

29: PA2

30: PA3

31: PA4

USART0 Request

To Send hardware

flow control output.

6: PC6

7: PC7

3: PB13

19: PF0

23: PF4

0: PA1

1: PA2

2: PA3

3: PA4

4: PA5

5: PB11

12: PC8

13: PC9

14: PC10

15: PC11

20: PD13 24: PF1

21: PD14 25: PF2

22: PD15 26: PF3

28: PF5

29: PF6

30: PF7

31: PA0

USART0 Asynchro-

nous Receive.

10: PC6

11: PC7

USART0 Synchro-

nous mode Master

Input / Slave Out-

put (MISO).

US0_RX

7: PB13

23: PF0

27: PF4

0: PA0

1: PA1

2: PA2

3: PA3

4: PA4

5: PA5

6: PB11

8: PB13

11: PC6

12: PC7

13: PC8

14: PC9

15: PC10

16: PC11

24: PF0

28: PF4

29: PF5

30: PF6

31: PF7

USART0 Asynchro-

nous Transmit. Al-

so used as receive

input in half duplex

communication.

21: PD13 25: PF1

22: PD14 26: PF2

23: PD15 27: PF3

US0_TX

USART0 Synchro-

nous mode Master

Output / Slave In-

put (MOSI).

0: PA2

1: PA3

2: PA4

3: PA5

4: PB11

6: PB13

12: PC9

13: PC10

14: PC11

20: PD14 24: PF2

21: PD15 25: PF3

28: PF6

29: PF7

30: PA0

31: PA1

9: PC6

10: PC7

11: PC8

USART1 clock in-

put / output.

US1_CLK

22: PF0

19: PD13 23: PF1

26: PF4

27: PF5

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Pin Definitions

Alternate

LOCATION

12 - 15 16 - 19

Functionality

0 - 3

4 - 7

8 - 11

20 - 23

24 - 27

28 - 31

Description

0: PA3

1: PA4

2: PA5

3: PB11

8: PC6

9: PC7

10: PC8

11: PC9

12: PC10

13: PC11

20: PD15 24: PF3

28: PF7

29: PA0

30: PA1

31: PA2

5: PB13

21: PF0

25: PF4

26: PF5

27: PF6

USART1 chip se-

lect input / output.

US1_CS

18: PD13 22: PF1

19: PD14 23: PF2

0: PA4

1: PA5

2: PB11

4: PB13

7: PC6

8: PC7

9: PC8

10: PC9

11: PC10

12: PC11

20: PF0

17: PD13 21: PF1

18: PD14 22: PF2

19: PD15 23: PF3

24: PF4

25: PF5

26: PF6

27: PF7

28: PA0

29: PA1

30: PA2

31: PA3

USART1 Clear To

Send hardware

flow control input.

US1_CTS

US1_RTS

0: PA5

1: PB11

8: PC8

9: PC9

10: PC10

11: PC11

16: PD13 20: PF1

17: PD14 21: PF2

18: PD15 22: PF3

24: PF5

25: PF6

26: PF7

27: PA0

28: PA1

29: PA2

30: PA3

31: PA4

USART1 Request

To Send hardware

flow control output.

6: PC6

7: PC7

3: PB13

19: PF0

23: PF4

0: PA1

1: PA2

2: PA3

3: PA4

4: PA5

5: PB11

12: PC8

13: PC9

14: PC10

15: PC11

20: PD13 24: PF1

21: PD14 25: PF2

22: PD15 26: PF3

28: PF5

29: PF6

30: PF7

31: PA0

USART1 Asynchro-

nous Receive.

10: PC6

11: PC7

USART1 Synchro-

nous mode Master

Input / Slave Out-

put (MISO).

US1_RX

7: PB13

23: PF0

27: PF4

0: PA0

1: PA1

2: PA2

3: PA3

4: PA4

5: PA5

6: PB11

8: PB13

11: PC6

12: PC7

13: PC8

14: PC9

15: PC10

16: PC11

24: PF0

28: PF4

29: PF5

30: PF6

31: PF7

USART1 Asynchro-

nous Transmit. Al-

so used as receive

input in half duplex

communication.

21: PD13 25: PF1

22: PD14 26: PF2

23: PD15 27: PF3

US1_TX

USART1 Synchro-

nous mode Master

Output / Slave In-

put (MOSI).

12: PF0

13: PF1

14: PF3

15: PF4

16: PF5

17: PF6

18: PF7

USART2 clock in-

put / output.

US2_CLK

US2_CS

30: PA5

29: PA5

28: PA5

12: PF1

13: PF3

14: PF4

15: PF5

16: PF6

17: PF7

USART2 chip se-

lect input / output.

11: PF0

12: PF3

13: PF4

14: PF5

15: PF6

16: PF7

USART2 Clear To

Send hardware

flow control input.

US2_CTS

US2_RTS

10: PF0

11: PF1

12: PF4

13: PF5

14: PF6

15: PF7

USART2 Request

To Send hardware

flow control output.

9: PF0

10: PF1

11: PF3

27: PA5

16: PF4

17: PF5

18: PF6

19: PF7

USART2 Asynchro-

nous Receive.

13: PF0

14: PF1

15: PF3

USART2 Synchro-

nous mode Master

Input / Slave Out-

put (MISO).

US2_RX

31: PA5

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Pin Definitions

Alternate

LOCATION

Functionality

0 - 3

4 - 7

8 - 11

12 - 15

16 - 19

20 - 23

24 - 27

28 - 31

Description

0: PA5

16: PF3

17: PF4

18: PF5

19: PF6

20: PF7

USART2 Asynchro-

nous Transmit. Al-

so used as receive

input in half duplex

communication.

14: PF0

15: PF1

US2_TX

USART2 Synchro-

nous mode Master

Output / Slave In-

put (MOSI).

4: PD14

5: PD15

13: PB11

12: PB11

USART3 clock in-

put / output.

US3_CLK

US3_CS

3: PD13

4: PD15

USART3 chip se-

lect input / output.

2: PD13

3: PD14

USART3 Clear To

Send hardware

flow control input.

1: PD13

2: PD14

3: PD15

US3_CTS

US3_RTS

11: PB11

10: PB11

0: PD13

1: PD14

2: PD15

USART3 Request

To Send hardware

flow control output.

4: PD13

5: PD14

6: PD15

USART3 Asynchro-

nous Receive.

14: PB11

USART3 Synchro-

nous mode Master

Input / Slave Out-

put (MISO).

US3_RX

USART3 Asynchro-

nous Transmit. Al-

so used as receive

input in half duplex

communication.

5: PD13

6: PD14

7: PD15

15: PB11

US3_TX

USART3 Synchro-

nous mode Master

Output / Slave In-

put (MOSI).

0: PA1

0: PA3

Digital to analog

converter VDAC0

external reference

input pin.

VDAC0_EXT

Digital to Analog

Converter DAC0

output channel

number 0.

VDAC0_OUT0 /

OPA0_OUT

0: PA5

1: PD13

2: PD15

Digital to Analog

Converter DAC0 al-

ternative output for

channel 0.

VDAC0_OUT0AL

T / OPA0_OUT-

ALT

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Pin Definitions

Alternate

LOCATION

Functionality

0 - 3

4 - 7

8 - 11

12 - 15

16 - 19

20 - 23

24 - 27

28 - 31

Description

0: PD14

Digital to Analog

Converter DAC0

output channel

number 1.

VDAC0_OUT1 /

OPA1_OUT

Digital to Analog

Converter DAC0 al-

ternative output for

channel 1.

VDAC0_OUT1AL

T / OPA1_OUT-

ALT

1: PA2

2: PA4

0: PA0

1: PA1

2: PA2

3: PA3

4: PA4

5: PA5

28: PC8

29: PC9

30: PC10 put / output channel

31: PC11 0.

Wide timer 0 Cap-

ture Compare in-

17: PB13

WTIM0_CC0

WTIM0_CC1

WTIM0_CC2

WTIM0_CDTI0

WTIM0_CDTI1

WTIM0_CDTI2

WTIM1_CC0

WTIM1_CC1

WTIM1_CC2

WTIM1_CC3

26: PC6

27: PC7

15: PB11

0: PA2

1: PA3

2: PA4

3: PA5

24: PC6

25: PC7

26: PC8

27: PC9

28: PC10 Wide timer 0 Cap-

29: PC11 ture Compare in-

put / output channel

1.

13: PB11

15: PB13

0: PA4

1: PA5

24: PC8

25: PC9

26: PC10

27: PC11

Wide timer 0 Cap-

ture Compare in-

put / output channel

2.

13: PB13

22: PC6

23: PC7

11: PB11

9: PB13

20: PC8

21: PC9

22: PC10

23: PC11

Wide timer 0 Com-

29: PD13 plimentary Dead

30: PD14 Time Insertion

31: PD15 channel 0.

18: PC6

19: PC7

7: PB11

16: PC6

17: PC7

18: PC8

19: PC9

20: PC10

21: PC11

28: PD14 Wide timer 0 Com-

29: PD15 plimentary Dead

30: PF0

5: PB11

7: PB13

Time Insertion

channel 1.

27: PD13 31: PF1

16: PC8

17: PC9

18: PC10

19: PC11

28: PF0

25: PD13 29: PF1

26: PD14 30: PF2

27: PD15 31: PF3

Wide timer 0 Com-

plimentary Dead

Time Insertion

channel 2.

5: PB13

14: PC6

15: PC7

3: PB11

1: PB13

12: PC8

13: PC9

14: PC10

15: PC11

24: PF0

28: PF4

29: PF5

30: PF6

31: PF7

Wide timer 1 Cap-

ture Compare in-

put / output channel

0.

21: PD13 25: PF1

22: PD14 26: PF2

23: PD15 27: PF3

10: PC6

11: PC7

8: PC6

9: PC7

10: PC8

11: PC9

12: PC10

13: PC11

20: PD14 24: PF2

21: PD15 25: PF3

28: PF6

29: PF7

Wide timer 1 Cap-

ture Compare in-

put / output channel

1.

22: PF0

26: PF4

27: PF5

19: PD13 23: PF1

8: PC8

9: PC9

10: PC10

11: PC11

20: PF0

17: PD13 21: PF1

18: PD14 22: PF2

19: PD15 23: PF3

24: PF4

25: PF5

26: PF6

27: PF7

Wide timer 1 Cap-

ture Compare in-

put / output channel

2.

6: PC6

7: PC7

4: PC6

5: PC7

6: PC8

7: PC9

8: PC10

9: PC11

16: PD14 20: PF2

17: PD15 21: PF3

18: PF0

15: PD13 19: PF1

24: PF6

25: PF7

Wide timer 1 Cap-

ture Compare in-

put / output channel

3.

22: PF4

23: PF5

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Pin Definitions

8.3 Analog Port (APORT) Client Maps

The Analog Port (APORT) is an infrastructure used to connect chip pins with on-chip analog clients such as analog comparators, ADCs,

DACs, etc. The APORT consists of a set of shared buses, switches, and control logic needed to configurably implement the signal

routing. Figure 8.2 APORT Connection Diagram on page 77 Shows the APORT routing for this device family. A complete description

of APORT functionality can be found in the Reference Manual. The APORT information in this section is reflective of the IC used in the

modules. Not all ports are available on the modules. The module pins available correspond with the pin names in this section.

1X

IDAC0

1Y

ACMP1X

ACMP1Y

PB15

0X

1X

2X

3X

4X

NEXT1

NEXT0

PB14

0X

1X

2X

3X

4X

NEXT1

NEXT0

POS

NEG

PF0

PF1

PB13

POS

NEG

OPA2_N

0Y

1Y

2Y

3Y

4Y

PF2

ACMP0

PB12

PB11

0Y

1Y

2Y

3Y

PF3

ACMP1

OUT2

PF8

NEXT1

4Y

NEXT1

NEXT0

OPA2_P

PF9

PF10

PF11

PF12

PF13

PF14

PF15

PK0

PK1

PK2

PF4

PB10

PB9

VDAC0_OPA2ALT

0X

1X

2X

3X

4X

NEXT0

NEXT2

OUT2ALT

POS

NEG

PB8

PB7

0Y

1Y

2Y

3Y

4Y

NEXT1

ADC0

PB6

PI3

PI2

EXTP

EXTN

PI1

OPA1_P

1X

2X

3X

4X

PI0

POS

OPA0_P

1X

2X

3X

4X

PF5

PA9

POS

NEG

PF6

PA8

OPA1_N

1Y

2Y

3Y

4Y

PF7

PA7 LESENSE

PA6 LESENSE

NEG

OUT

OPA0_N

1Y

2Y

3Y

4Y

OPA1

OPA0

PA5 LESENSE

PA4 LESENSE

PA3 LESENSE

PA2 LESENSE

OUT1

OUT1ALT

OUT1

OUT2

OUT3

VDAC0_OUT0ALT

VDAC0_OUT1ALT

OUT0ALT

OUT1ALT

OUT0

OUT0ALT

OUT1

OUT2

OUT3

OPA0_INN0

OUT

OPA0_N

OUT4

NEXT1

OUT4

NEXT0

OPA0_OUT

OUT0

VDAC0_OUT1ALT

OUT1ALT

OPA2_P

1X

POS

NEG

OPA0_INP0

ADC0_EXTP

2X

3X

4X

OPA0_P

PA1 LESENSE

PA0 LESENSE

ADC_EXTP

OPA2_N

1Y

2Y

3Y

4Y

ADC0_EXTN

OPA0ALT

ADC_EXTN

OUT0ALT

OPA2

PD15 LESENSE

OPA1_INN0

OUT2

OUT2ALT

OUT1

OPA1N

OUT

OUT2

OUT3

OUT4

NEXT2

1X

1Y

3X

3Y

CEXT

CSEN

2X

2Y

nX, nY

APORTnX, APORTnY

CEXT_SENSE

4X

4Y

AX, BY, …

BUSAX, BUSBY, ...

ADC0X,

ADC0Y

BUSADC0X,

BUSADC0Y

ACMP0X,

BUSACMP0X,

ACMP1Y, … BUSACMP1Y, ...

Figure 8.2. APORT Connection Diagram

Client maps for each analog circuit using the APORT are shown in the following tables. The maps are organized by bus, and show the

peripheral's port connection, the shared bus, and the connection from specific bus channel numbers to GPIO pins.

In general, enumerations for the pin selection field in an analog peripheral's register can be determined by finding the desired pin con-

nection in the table and then combining the value in the Port column (APORT__), and the channel identifier (CH__). For example, if pin

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Rev. 1.0 | 77

MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Pin Definitions

PF7 is available on port APORT2X as CH23, the register field enumeration to connect to PF7 would be APORT2XCH23. The shared

bus used by this connection is indicated in the Bus column.

Table 8.4. ACMP0 Bus and Pin Mapping

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Pin Definitions

Table 8.5. ACMP1 Bus and Pin Mapping

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Rev. 1.0 | 79

MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Pin Definitions

Table 8.6. ADC0 Bus and Pin Mapping

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Pin Definitions

Table 8.7. CSEN Bus and Pin Mapping

CEXT

CEXT_SENSE

Table 8.8. IDAC0 Bus and Pin Mapping

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Rev. 1.0 | 81

MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Pin Definitions

Table 8.9. VDAC0 / OPA Bus and Pin Mapping

OPA0_N

OPA0_P

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Pin Definitions

OPA1_N

OPA1_P

OPA2_N

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Rev. 1.0 | 83

MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Pin Definitions

OPA2_OUT

OPA2_P

VDAC0_OUT0 / OPA0_OUT

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Rev. 1.0 | 84

MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Pin Definitions

VDAC0_OUT1 / OPA1_OUT

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Rev. 1.0 | 85

MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Package Specifications

9. Package Specifications

9.1 MGM12P Dimensions

Figure 9.1. MGM12P Package Dimensions

Figure 9.2. MGM12P with U.FL Package Dimensions

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Package Specifications

9.2 MGM12P Module Footprint

The figure below shows the Module footprint and PCB dimensions.

Figure 9.3. MGM12P Footprint

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Package Specifications

9.3 MGM12P Recommended PCB Land Pattern

The figure below shows the recommended land pattern. The antenna clearance section is not required for the MGM12P module version

with the U.FL connector.

Figure 9.4. MGM12P Recommended PCB Land Pattern

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Rev. 1.0 | 88

MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Package Specifications

9.4 MGM12P Package Marking

The figure below shows the Module markings printed on the RF-shield.

Figure 9.5. MGM12P Package Marking

The module marking consists of:

MGM12Pxxxxxx - Part number designation

Model: MGM12Pxxxx – Model number designation

FCC ID: QOQMGM12Px – FCC

• QOQMGM12P0 for model MGM12P02GA and MGM12P02GE

• QOQMGM12P2 for model MGM12P22GA and MGM12P22GE

• QOQMGM12P3 for model MGM12P32GA and MGM12P32GE

IC: 5123A-MGM12Px – IC

• 5123A-MGM12P0 for model MGM12P02GA and MGM12P02GE

• 5123A-MGM12P2 for model MGM12P22GA and MGM12P22GE

• 5123A-MGM12P3 for model MGM12P32GA and MGM12P32GE

YYWWXXXX

• YY – The last 2 digits of the assembly year

• WW – The 2 digit work week when the device was assembled

• XXXX – A trace or manufacturing code. The first letter is the device revision.

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Rev. 1.0 | 89

MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Tape and Reel Specifications

10. Tape and Reel Specifications

10.1 Tape and Reel Specification

This section contains information regarding the tape and reel packaging for the MGM12P Mighty Gecko Module.

10.2 Reel Material and Dimensions

• Reel material: Polystyrene (PS)

• Reel diameter: 13 inches (330 mm)

• Number of modules per reel: 1000 pcs

• Disk deformation, folding whitening and mold imperfections: Not allowed

• Disk set: consists of two 13 inch (330 mm) rotary round disks and one central axis (100 mm)

• Antistatic treatment: Required

• Surface resistivity: 104 - 109 Ω/sq.

Figure 10.1. Reel Dimension — Side View

Symbol

W0

Dimensions [mm]

44.0 +0.5/-.0.0

48.0

W1

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Tape and Reel Specifications

10.3 Module Orientation and Tap

The user direction of feed, start and end of tape on reel and orientation of the Modules on the tape are shown in the figures below.

Figure 10.2. Module Orientation and Feed Direction

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Tape and Reel Specifications

10.4 Carrier Tape and Cover Tape Information

Figure 10.3. Carrier Tape Information

Figure 10.4. Cover Tape Information

Symbol

Thickness (T)

Width (W)

Dimensions [mm]

0.055 +0.005/-0.003

37.50 +0.30/-0.10

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Rev. 1.0 | 92

MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Certifications

11. Certifications

11.1 CE

The MGM12P02 and MGM12P22 modules are in conformity with the essential requirements and other relevant requirements of the

Radio Equipment Directive(RED). Please note that every application using the MGM12P will need to perform the radio EMC tests on

the end product according toEN 301 489-17. Separate RF testing is not required provided that the customer follows the module manu-

facturer's recommendations and instructions and does not make modifications, e.g. to the provided antenna solutions or requirements.

A formal DoC is available via www.silabs.com

MGM12P32 module is inconformity with the essential requirements and other relevant requirements of the Radio Equipment Direc-

tive(RED) at nominal 10 dBm transmit power.

The transmit power of the module is not limited and when an end product is using MGM12P32, the end product manufacturer is respon-

sible that the end product is in inconformity of all relevant requirements of the RED.

11.2 FCC

This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:

1. This device may not cause harmful interference, and

2. This device must accept any interference received, including interference that may cause undesirable operation.

Any changes or modifications not expressly approved by Silicon Labs could void the user’s authority to operate the equipment.

FCC RF Radiation Exposure Statement:

This equipment complies with FCC radiation exposure limits set forth for an uncontrolled environment. End users must follow the specif-

ic operating instructions for satisfying RF exposure compliance. This transmitter meets both portable and mobile limits as demonstrated

in the RF Exposure Analysis. This transmitter must not be co-located or operating in conjunction with any other antenna or transmitter

except in accordance with FCC multi-transmitter product procedures.

OEM Responsibilities to comply with FCC Regulations

OEM integrator is responsible for testing their end-product for any additional compliance requirements required with this module instal-

led (for example, digital device emissions, PC peripheral requirements, etc.).

• With MGM12P22GA, MGM12P22GE, MGM12P02GA and MGM12P02GE the antenna(s) must be installed such that a minimum

separation distance of 6.7mm is maintained between the radiator (antenna) and all persons at all times.

• With MGM12P32GA and MGM12P32GE the antenna(s) must be installed such that a minimum separation distance of 39mm is

maintained between the radiator (antenna) and all persons at all times.

• The transmitter module must not be co-located or operating in conjunction with any other antenna or transmitter except in accord-

ance with FCC multi-transmitter product procedures.

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MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Certifications

IMPORTANT NOTE: In the event that the above conditions cannot be met (for certain configurations or co-location with another trans-

mitter), then the FCC authorization is no longer considered valid and the FCC ID cannot be used on the final product. In these circum-

stances, the OEM integrator will be responsible for re-evaluating the end product (including the transmitter) and obtaining a separate

FCC authorization.

End Product Labeling

The variants of MGM12P Modules are labeled with their own FCC IDs. If the FCC ID is not visible when the module is installed inside

another device, then the outside of the device into which the module is installed must also display a label referring to the enclosed

module. In that case, the final product must be labeled in a visible area with the following

MODELS MGM12P02GE and MGM12P02GA:

“Contains Transmitter Module FCC ID: QOQMGM12P0”

or

“Contains FCC ID: QOQMGM12P0

MODELS MGM12P22GE and MGM12P22GA:

“Contains Transmitter Module FCC ID: QOQMGM12P2”

or

“Contains FCC ID: QOQMGM12P2

MODELS MGM12P32GE and MGM12P32GA:

“Contains Transmitter Module FCC ID: QOQMGM12P3”

or

“Contains FCC ID: QOQMGM12P3

The OEM integrator has to be aware not to provide information to the end user regarding how to install or remove this RF module or

change RF related parameters in the user manual of the end product.

silabs.com | Building a more connected world.

Rev. 1.0 | 94

MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Certifications

11.3 ISEDC

This radio transmitter (IC: 5123A-MGM12P) has been approved by Industry Canada to operate with the embedded chip antenna and a

standard 2.14 dBi dipole antenna. Other antenna types are strictly prohibited for use with this device.

This device complies with Industry Canada’s license-exempt RSS standards. Operation is subject to the following two conditions:

1. This device may not cause interference; and

2. This device must accept any interference, including interference that may cause undesired operation of the device

RF Exposure Statemment

Exception from routine SAR evaluation limits are given in RSS-102 Issue 5.

MGM12P22GA, MGM12P22GE, MGM12P02GA and MGM12P02GE modules meets the given requirements when the minimum sepa-

ration distance to human body is 20 mm.

MGM12P32GA and MGM12P32GA modules meets the given requirements when the minimum separation distance to human body is

35 mm.

RF exposure or SAR evaluation is not required when the separation distance is same or more than stated above. If the separation dis-

tance is less than stated above the OEM integrator is responsible for evaluating the SAR.

OEM Responsibilities to comply with IC Regulations

The MGM12P module has been certified for integration into products only by OEM integrators under the following conditions:

• The antenna(s) must be installed such that a minimum separation distance as stated above is maintained between the radiator (an-

tenna) and all persons at all times.

• The transmitter module must not be co-located or operating in conjunction with any other antenna or transmitter.

As long as the two conditions above are met, further transmitter testing will not be required. However, the OEM integrator is still respon-

sible for testing their end-product for any additional compliance requirements required with this module installed (for example, digital

device emissions, PC peripheral requirements, etc.).

IMPORTANT NOTE: In the event that these conditions cannot be met (for certain configurations or co-location with another transmit-

ter), then the ISEDC authorization is no longer considered valid and the IC ID cannot be used on the final product. In these circumstan-

ces, the OEM integrator will be responsible for re-evaluating the end product (including the transmitter) and obtaining a separate ISEDC

authorization.

End Product Labeling

The MGM12P modules are labeled with their own IC ID. If the IC ID is not visible when the module is installed inside another device,

then the outside of the device into which the module is installed must also display a label referring to the enclosed module. In that case,

the final end product must be labeled in a visible area with the following:

MODELS MGM12P02GE and MGM12P02GA:

“Contains Transmitter Module IC: 5123A-MGM12P0”

or

“Contains IC: 5123A-MGM12P0

MODELS MGM12P22GE and MGM12P22GA:

“Contains Transmitter Module IC: 5123A-MGM12P2”

or

“Contains IC: 5123A-MGM12P2

MODELS MGM12P32GE and MGM12P32GA:

“Contains Transmitter Module IC: 5123A-MGM12P3”

or

“Contains IC: 5123A-MGM12P3”

The OEM integrator has to be aware not to provide information to the end user regarding how to install or remove this RF module or

change RF related parameters in the user manual of the end product

silabs.com | Building a more connected world.

Rev. 1.0 | 95

MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Certifications

ISEDC (Français)

Industrie Canada a approuvé l’utilisation de cet émetteur radio (IC: 5123A-MGM12P) en conjonction avec des antennes de type dipo-

laire à 2.14dBi ou des antennes embarquées, intégrée au produit.

L’utilisation de tout autre type d’antenne avec ce composant est proscrite.

Ce composant est conforme aux normes RSS, exonérées de licence d'Industrie Canada. Son mode de fonctionnement est soumis aux

deux conditions suivantes :

1. Ce composant ne doit pas générer d’interférences

2. Ce composant doit pouvoir est soumis à tout type de perturbation y compris celle pouvant nuire à son bon fonctionnement.

Déclaration d'exposition RF

L'exception tirée des limites courantes d'évaluation SAR est donnée dans le document RSS-102 Issue 5.

Les modules MGM12P22GA, MGM12P22GE, MGM12P02GA et MGM12P02GE répondent aux exigences requises lorsque la distance

minimale de séparation avec le corps humain est de 20 mm.

Les modules MGM12P32GA et MGM12P32GA répondent aux exigences requises lorsque la distance minimale de séparation avec le

corps humain est de 35 mm.

La déclaration d’exposition RF ou l'évaluation SAR n'est pas nécessaire lorsque la distance de séparation est identique ou supérieure à

celle indiquée ci-dessus.

Si la distance de séparation est inférieure à celle mentionnées plus haut, il incombe à l'intégrateur OEM de procédé à une évaluation

SAR.

Responsabilités des OEM pour une mise en conformité avec le Règlement du Circuit Intégré

Le module MGM12P a été approuvé pour l'intégration dans des produits finaux exclusivement réalisés par des OEM sous les condi-

tions suivantes:

• L'antenne (s) doit être installée de sorte qu'une distance de séparation minimale indiquée ci-dessus soit maintenue entre le radiateur

(antenne) et toutes les personnes avoisinante, ce à tout moment.

• Le module émetteur ne doit pas être localisé ou fonctionner avec une autre antenne ou un autre transmetteur que celle indiquée

plus haut.

Tant que les deux conditions ci-dessus sont respectées, il n’est pas nécessaire de tester ce transmetteur de façon plus poussée. Ce-

pendant, il incombe à l’intégrateur OEM de s’assurer de la bonne conformité du produit fini avec les autres normes auxquelles il pour-

rait être soumis de fait de l’utilisation de ce module (par exemple, les émissions des périphériques numériques, les exigences de pé-

riphériques PC, etc.).

REMARQUE IMPORTANTE: dans le cas où ces conditions ne peuvent être satisfaites (pour certaines configurations ou co-implanta-

tion avec un autre émetteur), l'autorisation ISEDC n'est plus considérée comme valide et le numéro d’identification ID IC ne peut pas

être apposé sur le produit final. Dans ces circonstances, l'intégrateur OEM sera responsable de la réévaluation du produit final (y comp-

ris le transmetteur) et de l'obtention d'une autorisation ISEDC distincte.

Étiquetage des produits finis

Les modules MGM12P sont étiquetés avec leur propre ID IC. Si l'ID IC n'est pas visible lorsque le module est intégré au sein d'un autre

produit, cet autre produit dans lequel le module est installé devra porter une étiquette faisant apparaitre les référence du module inté-

gré. Dans un tel cas, sur le produit final doit se trouver une étiquette aisément lisible sur laquelle figurent les informations suivantes :

MODÈLES MGM12P02GE et MGM12P02GA:

"Contient le module transmetteur : 5123A-MGM12P0"

ou

"Contient le circuit: 5123A-MGM12P0

MODÈLES MGM12P22GE et MGM12P22GA:

"Contient le module transmetteur: 5123A-MGM12P2"

ou

"Contient IC: 5123A-MGM12P2

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Rev. 1.0 | 96

MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Certifications

MODÈLES MGM12P32GE et MGM12P32GA:

"Contient le module émetteur IC: 5123A-MGM12P3"

ou

"Contient IC: 5123A-MGM12P3"

L'intégrateur OEM doit être conscient qu’il ne doit pas fournir, dans le manuel d’utilisation, d'informations relatives à la façon d'installer

ou de d’enlever ce module RF ainsi que sur la procédure à suivre pour modifier les paramètres liés à la radio.

silabs.com | Building a more connected world.

Rev. 1.0 | 97

MGM12P Mighty Gecko Multi-Protocol Wireless Mesh Module Data Sheet

Revision History

12. Revision History

12.1 Revision 1.0

• Minor Updates

12.2 Revision 0.2

• Initial Publication

silabs.com | Building a more connected world.

Rev. 1.0 | 98

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Disclaimer

Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or

intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical"

parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes

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型号：	MGM12P02F1024GA-V2
厂家：	SILICON
描述：	Telecom IC, 电信电信集成电路
文件：	总99页 (文件大小：3155K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MGM12P02F1024GA-V2 [SILICON]

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