SI1001-C-GM [SILICON]
Ultra Low Power, 64/32 kB, 10-Bit ADC MCU with Integrated 240-960 MHz EZRadioPRO Transceiver; 超低功耗， 64/32 KB ， 10位ADC， MCU ，集成了240-960兆赫的EZRadioPRO收发器
| 型号： | SI1001-C-GM |
| 厂家： | 
SILICON |
| 描述： | Ultra Low Power, 64/32 kB, 10-Bit ADC MCU with Integrated 240-960 MHz EZRadioPRO Transceiver |
| 文件： | 总376页 (文件大小：2369K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si1000/1/2/3/4/5
Ultra Low Power, 64/32 kB, 10-Bit ADC
®
MCU with Integrated 240–960 MHz EZRadioPRO Transceiver
EZRadioPRO® Transceiver
Ultra Low Power: 0.9 to 3.6 V Operation
-
Typical sleep mode current < 0.1 µA; retains state and
RAM contents over full supply range; fast wakeup of < 2 µs
Less than 600 nA with RTC running
Less than 1 µA with RTC running and radio state retained
On-chip dc-dc converter allows operation down to 0.9 V.
-
-
-
-
Frequency range = 240–960 MHz
Sensitivity = –121 dBm
FSK, GFSK, and OOK modulation
Max output power = +20 dBm (Si1000/1), +13 dBm
(Si1002/3/4/5)
-
-
-
-
Two built-in brown-out detectors cover sleep and active
modes
-
RF power consumption
- 18.5 mA receive
10-Bit Analog to Digital Converter
- 18 mA @ +1 dBm transmit
- 30 mA @ +13 dBm transmit
- 85 mA @ +20 dBm transmit
Data rate = 0.123 to 256 kbps
Auto-frequency calibration (AFC)
Antenna diversity and transmit/receive switch control
Programmable packet handler
TX and RX 64 byte FIFOs
-
-
-
Up to 300 ksps
Up to 18 external inputs
External pin or internal VREF (no external capacitor
required)
-
-
-
-
-
-
-
-
-
-
Built-in temperature sensor
External conversion start input option
Autonomous burst mode with 16-bit automatic averaging
accumulator
Frequency hopping capability
On-chip crystal tuning
Dual Comparators
-
-
-
Programmable hysteresis and response time
Configurable as interrupt or reset source
Low current (< 0.5 µA)
Digital Peripherals
-
19 or 16 port I/O plus 3 GPIO pins; Hardware enhanced
UART, SPI, and I2C serial ports available concurrently
Low power 32-bit SmaRTClock
On-Chip Debug
-
-
-
On-chip debug circuitry facilitates full-speed, non-intrusive
in-system debug (No emulator required)
Four general purpose 16-bit counter/timers; six channel
programmable counter array (PCA)
-
-
-
Provides breakpoints, single stepping
Inspect/modify memory and registers
Complete development kit
Clock Sources
-
Precision internal oscillators: 24.5 MHz with ±2% accuracy
supports UART operation; spread-spectrum mode for
reduced EMI; Low power 20 MHz internal oscillator
High-Speed 8051 µC Core
-
Pipelined instruction architecture; executes 70% of instruc-
tions in 1 or 2 system clocks
-
-
-
External oscillator: Crystal, RC, C, CMOS clock
SmaRTClock oscillator: 32.768 kHz crystal or self-oscillate
Can switch between clock sources on-the-fly; useful in
implementing various power saving modes
-
-
Up to 25 MIPS throughput with 25 MHz clock
Expanded interrupt handler
Memory
Package
-
-
4352 bytes internal data RAM (256 + 4096)
64 kB (Si1000/2/4) or 32 kB (Si1001/3/5) Flash; In-system
programmable in 1024-byte sectors—1024 bytes are
reserved in the 64 kB devices
-
42-pin QFN (5 x 7 mm)
Temperature Range: –40 to +85 °C
ANALOG
PERIPHERALS
DIGITAL I/O
EZRadioPRO
(240–960 MHz)
UART
SMBus
SPI
Port 0
EZRadio
PRO
Serial
LNA
A
M
U
X
10-bit
IREF
PCA
300 ksps
ADC
Timer 0
Timer 1
Timer 2
Timer 3
CRC
Interface
Port 1
PA
+
–
+
VREF
TEMP
SENSOR
–
Mixer
PGA
ADC
Port 2
VREG
VOLTAGE
COMPARATORS
24.5 MHz PRECISION
20 MHz LOW POWER
INTERNAL OSCILLATOR
INTERNAL OSCILLATOR
Digital
Modem
External Oscillator
HARDWARE smaRTClock
PLL
Delta
Sigma
HIGH-SPEED CONTROLLER CORE
Modulator
64/32 kB
ISP FLASH
FLEXIBLE
INTERRUPTS
8051 CPU
(25 MIPS)
DEBUG
4352 B
SRAM
OSC
Digital
Logic
POR WDT
CIRCUITRY
Rev. 1.0 9/10
Copyright © 2010 by Silicon Laboratories
Si1000/1/2/3/4/5
Si1000/1/2/3/4/5
2
Rev. 1.0
Si1000/1/2/3/4/5
Table of Contents
1. System Overview ..................................................................................................... 16
1.1. Typical Connection Diagram ............................................................................. 20
1.2. CIP-51™ Microcontroller Core .......................................................................... 21
1.3. Port Input/Output ............................................................................................... 22
1.4. Serial Ports........................................................................................................ 23
1.5. Programmable Counter Array............................................................................ 23
1.6. 10-bit SAR ADC with 16-bit Auto-Averaging Accumulator and
Autonomous Low Power Burst Mode................................................................ 24
1.7. Programmable Current Reference (IREF0)....................................................... 25
1.8. Comparators...................................................................................................... 25
2. Ordering Information............................................................................................... 27
3. Pinout and Package Definitions ............................................................................. 28
4. Electrical Characteristics........................................................................................ 40
4.1. Absolute Maximum Specifications..................................................................... 40
4.2. MCU Electrical Characteristics.......................................................................... 41
®
4.3. EZRadioPRO Electrical Characteristics .......................................................... 66
4.4. Definition of Test Conditions for the EZRadioPRO Peripheral .......................... 73
5. 10-Bit SAR ADC with 16-bit Auto-Averaging Accumulator and
Autonomous Low Power Burst Mode ................................................................... 74
5.1. Output Code Formatting.................................................................................... 74
5.2. Modes of Operation........................................................................................... 76
5.3. 8-Bit Mode ......................................................................................................... 80
5.4. Programmable Window Detector....................................................................... 87
5.5. ADC0 Analog Multiplexer .................................................................................. 90
5.6. Temperature Sensor.......................................................................................... 92
5.7. Voltage and Ground Reference Options ........................................................... 95
5.8. External Voltage References............................................................................. 95
5.9. Internal Voltage References.............................................................................. 96
5.10. Analog Ground Reference............................................................................... 96
5.11. Temperature Sensor Enable ........................................................................... 96
5.12. Voltage Reference Electrical Specifications.................................................... 97
6. Programmable Current Reference (IREF0)............................................................ 98
6.1. IREF0 Specifications ......................................................................................... 98
7. Comparators............................................................................................................. 99
7.1. Comparator Inputs............................................................................................. 99
7.2. Comparator Outputs........................................................................................ 100
7.3. Comparator Response Time ........................................................................... 101
7.4. Comparator Hysteresis.................................................................................... 101
7.5. Comparator Register Descriptions .................................................................. 102
7.6. Comparator0 and Comparator1 Analog Multiplexers ...................................... 106
8. CIP-51 Microcontroller........................................................................................... 109
8.1. Performance.................................................................................................... 109
8.2. Programming and Debugging Support............................................................ 110
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3
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8.3. Instruction Set.................................................................................................. 110
8.4. CIP-51 Register Descriptions .......................................................................... 115
9. Memory Organization ............................................................................................ 118
9.1. Program Memory............................................................................................. 119
9.2. Data Memory................................................................................................... 119
10. On-Chip XRAM ..................................................................................................... 121
10.1. Accessing XRAM........................................................................................... 121
10.2. Special Function Registers............................................................................ 122
11. Special Function Registers................................................................................. 123
11.1. SFR Paging ................................................................................................... 124
12. Interrupt Handler.................................................................................................. 129
12.1. Enabling Interrupt Sources............................................................................ 129
12.2. MCU Interrupt Sources and Vectors.............................................................. 129
12.3. Interrupt Priorities .......................................................................................... 130
12.4. Interrupt Latency............................................................................................ 130
12.5. Interrupt Register Descriptions...................................................................... 132
12.6. External Interrupts INT0 and INT1................................................................. 139
13. Flash Memory....................................................................................................... 141
13.1. Programming The Flash Memory.................................................................. 141
13.2. Non-volatile Data Storage ............................................................................. 143
13.3. Security Options ............................................................................................ 143
13.4. Determining the Device Part Number at Run Time ....................................... 145
13.5. Flash Write and Erase Guidelines................................................................. 145
13.6. Minimizing Flash Read Current ..................................................................... 147
14. Power Management ............................................................................................. 151
14.1. Normal Mode................................................................................................. 152
14.2. Idle Mode....................................................................................................... 153
14.3. Stop Mode ..................................................................................................... 153
14.4. Suspend Mode .............................................................................................. 154
14.5. Sleep Mode ................................................................................................... 154
14.6. Configuring Wakeup Sources........................................................................ 155
14.7. Determining the Event that Caused the Last Wakeup................................... 155
14.8. Power Management Specifications ............................................................... 157
15. Cyclic Redundancy Check Unit (CRC0)............................................................. 158
15.1. CRC Algorithm............................................................................................... 158
15.2. Preparing for a CRC Calculation ................................................................... 160
15.3. Performing a CRC Calculation ...................................................................... 160
15.4. Accessing the CRC0 Result .......................................................................... 160
15.5. CRC0 Bit Reverse Feature............................................................................ 164
16. On-Chip DC-DC Converter (DC0)........................................................................ 165
16.1. Startup Behavior............................................................................................ 166
16.2. High Power Applications ............................................................................ 167
16.3. Pulse Skipping Mode..................................................................................... 167
16.4. Enabling the DC-DC Converter ..................................................................... 167
16.5. Minimizing Power Supply Noise .................................................................... 168
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16.6. Selecting the Optimum Switch Size............................................................... 169
16.7. DC-DC Converter Clocking Options.............................................................. 169
16.8. DC-DC Converter Behavior in Sleep Mode................................................... 169
16.9. DC-DC Converter Register Descriptions....................................................... 171
16.10. DC-DC Converter Specifications................................................................. 173
17. Voltage Regulator (VREG0)................................................................................. 174
17.1. Voltage Regulator Electrical Specifications................................................... 174
18. Reset Sources...................................................................................................... 175
18.1. Power-On (VBAT Supply Monitor) Reset ...................................................... 176
18.2. Power-Fail (VDD_MCU Supply Monitor) Reset............................................. 177
18.3. External Reset............................................................................................... 179
18.4. Missing Clock Detector Reset ....................................................................... 179
18.5. Comparator0 Reset ....................................................................................... 180
18.6. PCA Watchdog Timer Reset ......................................................................... 180
18.7. Flash Error Reset .......................................................................................... 180
18.8. SmaRTClock (Real Time Clock) Reset ......................................................... 180
18.9. Software Reset.............................................................................................. 180
19. Clocking Sources................................................................................................. 182
19.1. Programmable Precision Internal Oscillator .................................................. 183
19.2. Low Power Internal Oscillator........................................................................ 183
19.3. External Oscillator Drive Circuit..................................................................... 183
19.4. Special Function Registers for Selecting and Configuring the System Clock 187
20. SmaRTClock (Real Time Clock).......................................................................... 190
20.1. SmaRTClock Interface .................................................................................. 190
20.2. SmaRTClock Clocking Sources .................................................................... 197
20.3. SmaRTClock Timer and Alarm Function....................................................... 201
21. Port Input/Output ................................................................................................. 207
21.1. Port I/O Modes of Operation.......................................................................... 208
21.2. Assigning Port I/O Pins to Analog and Digital Functions............................... 209
21.3. Priority Crossbar Decoder ............................................................................. 211
21.4. Port Match ..................................................................................................... 216
21.5. Special Function Registers for Accessing and Configuring Port I/O ............. 219
®
22. EZRadioPRO Serial Interface (SPI1) ................................................................ 228
22.1. Signal Descriptions........................................................................................ 229
22.2. SPI Master Operation on the MCU Core Side.............................................. 229
22.3. SPI Slave Operation on the EZRadioPRO Peripheral Side........................... 229
22.4. EZRadioPRO Serial Interface Interrupt Sources........................................... 232
22.5. Serial Clock Phase and Polarity .................................................................... 232
22.6. SPI Special Function Registers..................................................................... 233
®
23. EZRadioPRO 240–960 MHz Transceiver.......................................................... 239
23.1. EZRadioPRO Operating Modes .................................................................... 240
23.2. Interrupts ...................................................................................................... 243
23.3. System Timing............................................................................................... 244
23.4. Modulation Options........................................................................................ 251
23.5. Internal Functional Blocks ............................................................................. 256
Rev. 1.0
5
Si1000/1/2/3/4/5
23.6. Data Handling and Packet Handler ............................................................... 261
23.7. RX Modem Configuration .............................................................................. 269
23.8. Auxiliary Functions ........................................................................................ 269
23.9. Reference Design.......................................................................................... 280
23.10. Application Notes and Reference Designs.................................................. 283
23.11. Customer Support ....................................................................................... 283
23.12. Register Table and Descriptions ................................................................. 284
23.13. Required Changes to Default Register Values............................................ 286
24. SMBus................................................................................................................... 287
24.1. Supporting Documents.................................................................................. 288
24.2. SMBus Configuration..................................................................................... 288
24.3. SMBus Operation .......................................................................................... 288
24.4. Using the SMBus........................................................................................... 290
24.5. SMBus Transfer Modes................................................................................. 302
24.6. SMBus Status Decoding................................................................................ 305
25. UART0................................................................................................................... 310
25.1. Enhanced Baud Rate Generation.................................................................. 311
25.2. Operational Modes ........................................................................................ 311
25.3. Multiprocessor Communications ................................................................... 313
26. Enhanced Serial Peripheral Interface (SPI0) ..................................................... 317
26.1. Signal Descriptions........................................................................................ 318
26.2. SPI0 Master Mode Operation........................................................................ 318
26.3. SPI0 Slave Mode Operation.......................................................................... 320
26.4. SPI0 Interrupt Sources .................................................................................. 321
26.5. Serial Clock Phase and Polarity .................................................................... 322
26.6. SPI Special Function Registers..................................................................... 323
27. Timers ................................................................................................................... 330
27.1. Timer 0 and Timer 1 ...................................................................................... 332
27.2. Timer 2 .......................................................................................................... 340
27.3. Timer 3 .......................................................................................................... 346
28. Programmable Counter Array............................................................................. 352
28.1. PCA Counter/Timer ....................................................................................... 353
28.2. PCA0 Interrupt Sources................................................................................. 354
28.3. Capture/Compare Modules ........................................................................... 355
28.4. Watchdog Timer Mode .................................................................................. 363
28.5. Register Descriptions for PCA0..................................................................... 365
29. C2 Interface .......................................................................................................... 371
29.1. C2 Interface Registers................................................................................... 371
29.2. C2 Pin Sharing .............................................................................................. 374
Document Change List.............................................................................................. 375
Contact Information................................................................................................... 376
6
Rev. 1.0
Si1000/1/2/3/4/5
List of Registers
SFR Definition 5.1. ADC0CN: ADC0 Control ................................................................ 81
SFR Definition 5.2. ADC0CF: ADC0 Configuration ...................................................... 82
SFR Definition 5.3. ADC0AC: ADC0 Accumulator Configuration ................................. 83
SFR Definition 5.4. ADC0PWR: ADC0 Burst Mode Power-Up Time ............................ 84
SFR Definition 5.5. ADC0TK: ADC0 Burst Mode Track Time ....................................... 85
SFR Definition 5.6. ADC0H: ADC0 Data Word High Byte ............................................ 86
SFR Definition 5.7. ADC0L: ADC0 Data Word Low Byte .............................................. 86
SFR Definition 5.8. ADC0GTH: ADC0 Greater-Than High Byte ................................... 87
SFR Definition 5.9. ADC0GTL: ADC0 Greater-Than Low Byte .................................... 87
SFR Definition 5.10. ADC0LTH: ADC0 Less-Than High Byte ...................................... 88
SFR Definition 5.11. ADC0LTL: ADC0 Less-Than Low Byte ........................................ 88
SFR Definition 5.12. ADC0MX: ADC0 Input Channel Select ........................................ 91
SFR Definition 5.13. TOFFH: ADC0 Data Word High Byte .......................................... 94
SFR Definition 5.14. TOFFL: ADC0 Data Word Low Byte ............................................ 94
SFR Definition 5.15. REF0CN: Voltage Reference Control .......................................... 97
SFR Definition 6.1. IREF0CN: Current Reference Control ........................................... 98
SFR Definition 7.1. CPT0CN: Comparator 0 Control .................................................. 102
SFR Definition 7.2. CPT0MD: Comparator 0 Mode Selection .................................... 103
SFR Definition 7.3. CPT1CN: Comparator 1 Control .................................................. 104
SFR Definition 7.4. CPT1MD: Comparator 1 Mode Selection .................................... 105
SFR Definition 7.5. CPT0MX: Comparator0 Input Channel Select ............................. 107
SFR Definition 7.6. CPT1MX: Comparator1 Input Channel Select ............................. 108
SFR Definition 8.1. DPL: Data Pointer Low Byte ........................................................ 115
SFR Definition 8.2. DPH: Data Pointer High Byte ....................................................... 115
SFR Definition 8.3. SP: Stack Pointer ......................................................................... 116
SFR Definition 8.4. ACC: Accumulator ....................................................................... 116
SFR Definition 8.5. B: B Register ................................................................................ 116
SFR Definition 8.6. PSW: Program Status Word ........................................................ 117
SFR Definition 10.1. EMI0CN: External Memory Interface Control ............................ 122
SFR Definition 11.1. SFRPage: SFR Page ................................................................. 125
SFR Definition 12.1. IE: Interrupt Enable .................................................................... 133
SFR Definition 12.2. IP: Interrupt Priority .................................................................... 134
SFR Definition 12.3. EIE1: Extended Interrupt Enable 1 ............................................ 135
SFR Definition 12.4. EIP1: Extended Interrupt Priority 1 ............................................ 136
SFR Definition 12.5. EIE2: Extended Interrupt Enable 2 ............................................ 137
SFR Definition 12.6. EIP2: Extended Interrupt Priority 2 ............................................ 138
SFR Definition 12.7. IT01CF: INT0/INT1 Configuration .............................................. 140
SFR Definition 13.1. PSCTL: Program Store R/W Control ......................................... 148
SFR Definition 13.2. FLKEY: Flash Lock and Key ...................................................... 149
SFR Definition 13.3. FLSCL: Flash Scale ................................................................... 150
SFR Definition 13.4. FLWR: Flash Write Only ............................................................ 150
1,2
SFR Definition 14.1. PMU0CF: Power Management Unit Configuration
................ 156
SFR Definition 14.2. PCON: Power Management Control Register ........................... 157
SFR Definition 15.1. CRC0CN: CRC0 Control ........................................................... 161
Rev. 1.0
7
Si1000/1/2/3/4/5
SFR Definition 15.2. CRC0IN: CRC0 Data Input ........................................................ 162
SFR Definition 15.3. CRC0DAT: CRC0 Data Output .................................................. 162
SFR Definition 15.4. CRC0AUTO: CRC0 Automatic Control ...................................... 163
SFR Definition 15.5. CRC0CNT: CRC0 Automatic Flash Sector Count ..................... 163
SFR Definition 15.6. CRC0FLIP: CRC0 Bit Flip .......................................................... 164
SFR Definition 16.1. DC0CN: DC-DC Converter Control ........................................... 171
SFR Definition 16.2. DC0CF: DC-DC Converter Configuration .................................. 172
SFR Definition 17.1. REG0CN: Voltage Regulator Control ........................................ 174
SFR Definition 18.1. VDM0CN: VDD_MCU Supply Monitor Control .......................... 179
SFR Definition 18.2. RSTSRC: Reset Source ............................................................ 181
SFR Definition 19.1. CLKSEL: Clock Select ............................................................... 187
SFR Definition 19.2. OSCICN: Internal Oscillator Control .......................................... 188
SFR Definition 19.3. OSCICL: Internal Oscillator Calibration ..................................... 188
SFR Definition 19.4. OSCXCN: External Oscillator Control ........................................ 189
SFR Definition 20.1. RTC0KEY: SmaRTClock Lock and Key .................................... 194
SFR Definition 20.2. RTC0ADR: SmaRTClock Address ............................................ 195
SFR Definition 20.3. RTC0DAT: SmaRTClock Data .................................................. 196
Internal Register Definition 20.4. RTC0CN: SmaRTClock Control . . . . . . . . . . . . . . . 203
Internal Register Definition 20.5. RTC0XCN: SmaRTClock Oscillator Control . . . . . . 204
Internal Register Definition 20.6. RTC0XCF: SmaRTClock Oscillator Configuration . 205
Internal Register Definition 20.7. RTC0PIN: SmaRTClock Pin Configuration . . . . . . 205
Internal Register Definition 20.8. CAPTUREn: SmaRTClock Timer Capture . . . . . . . 206
Internal Register Definition 20.9. ALARMn: SmaRTClock Alarm Programmed Value 206
SFR Definition 21.1. XBR0: Port I/O Crossbar Register 0 .......................................... 214
SFR Definition 21.2. XBR1: Port I/O Crossbar Register 1 .......................................... 215
SFR Definition 21.3. XBR2: Port I/O Crossbar Register 2 .......................................... 216
SFR Definition 21.4. P0MASK: Port0 Mask Register .................................................. 217
SFR Definition 21.5. P0MAT: Port0 Match Register ................................................... 217
SFR Definition 21.6. P1MASK: Port1 Mask Register .................................................. 218
SFR Definition 21.7. P1MAT: Port1 Match Register ................................................... 218
SFR Definition 21.8. P0: Port0 .................................................................................... 220
SFR Definition 21.9. P0SKIP: Port0 Skip .................................................................... 220
SFR Definition 21.10. P0MDIN: Port0 Input Mode ...................................................... 221
SFR Definition 21.11. P0MDOUT: Port0 Output Mode ............................................... 221
SFR Definition 21.12. P0DRV: Port0 Drive Strength .................................................. 222
SFR Definition 21.13. P1: Port1 .................................................................................. 223
SFR Definition 21.14. P1SKIP: Port1 Skip .................................................................. 223
SFR Definition 21.15. P1MDIN: Port1 Input Mode ...................................................... 224
SFR Definition 21.16. P1MDOUT: Port1 Output Mode ............................................... 224
SFR Definition 21.17. P1DRV: Port1 Drive Strength .................................................. 225
SFR Definition 21.18. P2: Port2 .................................................................................. 225
SFR Definition 21.19. P2SKIP: Port2 Skip .................................................................. 226
SFR Definition 21.20. P2MDIN: Port2 Input Mode ...................................................... 226
SFR Definition 21.21. P2MDOUT: Port2 Output Mode ............................................... 227
SFR Definition 21.22. P2DRV: Port2 Drive Strength .................................................. 227
8
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Si1000/1/2/3/4/5
SFR Definition 22.1. SPI1CFG: SPI Configuration ..................................................... 234
SFR Definition 22.2. SPI1CN: SPI Control ................................................................. 235
SFR Definition 22.3. SPI1CKR: SPI Clock Rate ......................................................... 236
SFR Definition 22.4. SPI1DAT: SPI Data ................................................................... 237
SFR Definition 24.1. SMB0CF: SMBus Clock/Configuration ...................................... 293
SFR Definition 24.2. SMB0CN: SMBus Control .......................................................... 295
SFR Definition 24.3. SMB0ADR: SMBus Slave Address ............................................ 298
SFR Definition 24.4. SMB0ADM: SMBus Slave Address Mask .................................. 298
SFR Definition 24.5. SMB0DAT: SMBus Data ............................................................ 301
SFR Definition 25.1. SCON0: Serial Port 0 Control .................................................... 314
SFR Definition 25.2. SBUF0: Serial (UART0) Port Data Buffer .................................. 315
SFR Definition 26.7. SPI0CFG: SPI0 Configuration ................................................... 324
SFR Definition 26.8. SPI0CN: SPI0 Control ............................................................... 325
SFR Definition 26.9. SPI0CKR: SPI0 Clock Rate ....................................................... 326
SFR Definition 26.10. SPI0DAT: SPI0 Data ............................................................... 326
SFR Definition 27.1. CKCON: Clock Control .............................................................. 331
SFR Definition 27.2. TCON: Timer Control ................................................................. 336
SFR Definition 27.3. TMOD: Timer Mode ................................................................... 337
SFR Definition 27.4. TL0: Timer 0 Low Byte ............................................................... 338
SFR Definition 27.5. TL1: Timer 1 Low Byte ............................................................... 338
SFR Definition 27.6. TH0: Timer 0 High Byte ............................................................. 339
SFR Definition 27.7. TH1: Timer 1 High Byte ............................................................. 339
SFR Definition 27.8. TMR2CN: Timer 2 Control ......................................................... 343
SFR Definition 27.9. TMR2RLL: Timer 2 Reload Register Low Byte .......................... 344
SFR Definition 27.10. TMR2RLH: Timer 2 Reload Register High Byte ...................... 344
SFR Definition 27.11. TMR2L: Timer 2 Low Byte ....................................................... 345
SFR Definition 27.12. TMR2H Timer 2 High Byte ....................................................... 345
SFR Definition 27.13. TMR3CN: Timer 3 Control ....................................................... 349
SFR Definition 27.14. TMR3RLL: Timer 3 Reload Register Low Byte ........................ 350
SFR Definition 27.15. TMR3RLH: Timer 3 Reload Register High Byte ...................... 350
SFR Definition 27.16. TMR3L: Timer 3 Low Byte ....................................................... 351
SFR Definition 27.17. TMR3H Timer 3 High Byte ....................................................... 351
SFR Definition 28.1. PCA0CN: PCA Control .............................................................. 365
SFR Definition 28.2. PCA0MD: PCA Mode ................................................................ 366
SFR Definition 28.3. PCA0PWM: PCA PWM Configuration ....................................... 367
SFR Definition 28.4. PCA0CPMn: PCA Capture/Compare Mode .............................. 368
SFR Definition 28.5. PCA0L: PCA Counter/Timer Low Byte ...................................... 369
SFR Definition 28.6. PCA0H: PCA Counter/Timer High Byte ..................................... 369
SFR Definition 28.7. PCA0CPLn: PCA Capture Module Low Byte ............................. 370
SFR Definition 28.8. PCA0CPHn: PCA Capture Module High Byte ........................... 370
C2 Register Definition 29.1. C2ADD: C2 Address ...................................................... 371
C2 Register Definition 29.2. DEVICEID: C2 Device ID ............................................... 372
C2 Register Definition 29.3. REVID: C2 Revision ID .................................................. 372
C2 Register Definition 29.4. FPCTL: C2 Flash Programming Control ........................ 373
C2 Register Definition 29.5. FPDAT: C2 Flash Programming Data ............................ 373
Rev. 1.0
9
Si1000/1/2/3/4/5
List of Figures
Figure 1.1. Si1000 Block Diagram ........................................................................... 17
Figure 1.2. Si1001 Block Diagram ........................................................................... 17
Figure 1.3. Si1002 Block Diagram ........................................................................... 18
Figure 1.4. Si1003 Block Diagram ........................................................................... 18
Figure 1.5. Si1004 Block Diagram ........................................................................... 19
Figure 1.6. Si1005 Block Diagram ........................................................................... 19
Figure 1.7. Si1002/3 RX/TX Direct-tie Application Example .................................... 20
Figure 1.8. Si1000/1 Antenna Diversity Application Example ................................. 20
Figure 1.9. Port I/O Functional Block Diagram ........................................................ 22
Figure 1.10. PCA Block Diagram ............................................................................. 23
Figure 1.11. ADC0 Functional Block Diagram ......................................................... 24
Figure 1.12. ADC0 Multiplexer Block Diagram ........................................................ 25
Figure 1.13. Comparator 0 Functional Block Diagram ............................................ 26
Figure 1.14. Comparator 1 Functional Block Diagram ............................................ 26
Figure 3.1. Si1000/1/2/3 Pinout Diagram (Top View) .............................................. 32
Figure 3.2. Si1004/5 Pinout Diagram (Top View) .................................................... 33
Figure 3.3. QFN-42 Package Drawing .................................................................... 34
Figure 3.4. Typical QFN-42 Landing Diagram ......................................................... 36
Figure 3.5. VIA Placement and Keepout Region ..................................................... 37
Figure 3.6. Typical PCB Stencil Diagram ................................................................ 38
Figure 4.1. Active Mode Current (External CMOS Clock) ....................................... 45
Figure 4.2. Idle Mode Current (External CMOS Clock) ........................................... 46
Figure 4.3. Typical DC-DC Converter Efficiency (High Current, VDD/DC+ = 2 V ... 47
Figure 4.4. Typical DC-DC Converter Efficiency (High Current, VDD/DC+ = 3 V) .. 48
Figure 4.5. Typical DC-DC Converter Efficiency (Low Current, VDD/DC+ = 2 V) ... 49
Figure 4.6. Typical One-Cell Suspend Mode Current .............................................. 50
Figure 4.7. Typical VOH Curves, 1.8–3.6 V ............................................................ 52
Figure 4.8. Typical VOH Curves, 0.9–1.8 V ............................................................ 53
Figure 4.9. Typical VOL Curves, 1.8–3.6 V ............................................................. 54
Figure 4.10. Typical VOL Curves, 1.8–3.6 V ........................................................... 55
Figure 4.11. Typical VOL Curves, 0.9–1.8 V ........................................................... 56
Figure 5.1. ADC0 Functional Block Diagram ........................................................... 74
Figure 5.2. 10-Bit ADC Track and Conversion Example Timing (BURSTEN = 0) ... 77
Figure 5.3. Burst Mode Tracking Example with Repeat Count Set to 4 .................. 78
Figure 5.4. ADC0 Equivalent Input Circuits ............................................................. 79
Figure 5.5. ADC Window Compare Example: Right-Justified Single-Ended Data .. 89
Figure 5.6. ADC Window Compare Example: Left-Justified Single-Ended Data ..... 89
Figure 5.7. ADC0 Multiplexer Block Diagram .......................................................... 90
Figure 5.8. Temperature Sensor Transfer Function ................................................ 92
Figure 5.9. Temperature Sensor Error with 1-Point Calibration (V
= 1.68 V) .... 93
REF
Figure 5.10. Voltage Reference Functional Block Diagram ..................................... 95
Figure 7.1. Comparator 0 Functional Block Diagram .............................................. 99
Figure 7.2. Comparator 1 Functional Block Diagram ............................................ 100
10
Rev. 1.0
Si1000/1/2/3/4/5
Figure 7.3. Comparator Hysteresis Plot ................................................................ 101
Figure 7.4. CPn Multiplexer Block Diagram ........................................................... 106
Figure 8.1. CIP-51 Block Diagram ......................................................................... 109
Figure 9.1. Si1000/1/2/3/4/5 Memory Map ............................................................ 118
Figure 9.2. Flash Program Memory Map ............................................................... 119
Figure 13.1. Flash Program Memory Map ............................................................. 143
Figure 14.1. Si1000/1/2/3/4/5 Power Distribution .................................................. 152
Figure 15.1. CRC0 Block Diagram ........................................................................ 158
Figure 15.2. Bit Reverse Register ......................................................................... 164
Figure 16.1. DC-DC Converter Block Diagram ...................................................... 165
Figure 16.2. DC-DC Converter Configuration Options .......................................... 168
Figure 18.1. Reset Sources ................................................................................... 175
Figure 18.2. Power-Fail Reset Timing Diagram .................................................... 176
Figure 18.3. Power-Fail Reset Timing Diagram .................................................... 177
Figure 19.1. Clocking Sources Block Diagram ...................................................... 182
Figure 19.2. 25 MHz External Crystal Example ..................................................... 184
Figure 20.1. SmaRTClock Block Diagram ............................................................. 190
Figure 20.2. Interpreting Oscillation Robustness (Duty Cycle) Test Results ......... 199
Figure 21.1. Port I/O Functional Block Diagram .................................................... 207
Figure 21.2. Port I/O Cell Block Diagram .............................................................. 208
Figure 21.3. Crossbar Priority Decoder with No Pins Skipped .............................. 212
Figure 21.4. Crossbar Priority Decoder with Crystal Pins Skipped ....................... 213
Figure 22.1. EZRadioPRO Serial Interface Block Diagram ................................... 228
Figure 22.2. SPI Timing ......................................................................................... 230
Figure 22.3. SPI Timing—READ Mode ................................................................. 230
Figure 22.4. SPI Timing—Burst Write Mode ......................................................... 231
Figure 22.5. SPI Timing—Burst Read Mode ......................................................... 231
Figure 22.6. Master Mode Data/Clock Timing ....................................................... 232
Figure 22.7. SPI Master Timing ............................................................................. 238
Figure 23.1. State Machine Diagram ..................................................................... 241
Figure 23.2. TX Timing .......................................................................................... 244
Figure 23.3. RX Timing .......................................................................................... 245
Figure 23.4. Frequency Deviation ......................................................................... 248
Figure 23.5. Sensitivity at 1% PER vs. Carrier Frequency Offset ......................... 250
Figure 23.6. FSK vs. GFSK Spectrums ................................................................. 252
Figure 23.7. Direct Synchronous Mode Example .................................................. 255
Figure 23.8. Direct Asynchronous Mode Example ................................................ 255
Figure 23.9. Microcontroller Connections .............................................................. 256
Figure 23.10. PLL Synthesizer Block Diagram ...................................................... 258
Figure 23.11. FIFO Thresholds ............................................................................. 261
Figure 23.12. Packet Structure .............................................................................. 262
Figure 23.13. Multiple Packets in TX Packet Handler ........................................... 263
Figure 23.14. Required RX Packet Structure with Packet Handler Disabled ........ 263
Figure 23.15. Multiple Packets in RX Packet Handler ........................................... 264
Figure 23.16. Multiple Packets in RX with CRC or Header Error .......................... 264
Rev. 1.0
11
Si1000/1/2/3/4/5
Figure 23.17. Operation of Data Whitening, Manchester Encoding, and CRC ..... 266
Figure 23.18. Manchester Coding Example .......................................................... 266
Figure 23.19. Header ............................................................................................. 268
Figure 23.20. POR Glitch Parameters ................................................................... 269
Figure 23.21. General Purpose ADC Architecture ................................................ 272
Figure 23.22. Temperature Ranges using ADC8 .................................................. 274
Figure 23.23. WUT Interrupt and WUT Operation ................................................. 277
Figure 23.24. Low Duty Cycle Mode ..................................................................... 278
Figure 23.25. RSSI Value vs. Input Power ............................................................ 280
Figure 23.26. Si1002 Split RF TX/RX Direct-Tie Reference Design—Schematic . 281
Figure 23.27. Si1000 Switch Matching Reference Design—Schematic ................ 282
Figure 24.1. SMBus Block Diagram ...................................................................... 287
Figure 24.2. Typical SMBus Configuration ............................................................ 288
Figure 24.3. SMBus Transaction ........................................................................... 289
Figure 24.4. Typical SMBus SCL Generation ........................................................ 291
Figure 24.5. Typical Master Write Sequence ........................................................ 302
Figure 24.6. Typical Master Read Sequence ........................................................ 303
Figure 24.7. Typical Slave Write Sequence .......................................................... 304
Figure 24.8. Typical Slave Read Sequence .......................................................... 305
Figure 25.1. UART0 Block Diagram ...................................................................... 310
Figure 25.2. UART0 Baud Rate Logic ................................................................... 311
Figure 25.3. UART Interconnect Diagram ............................................................. 312
Figure 25.4. 8-Bit UART Timing Diagram .............................................................. 312
Figure 25.5. 9-Bit UART Timing Diagram .............................................................. 313
Figure 25.6. UART Multi-Processor Mode Interconnect Diagram ......................... 313
Figure 26.1. SPI Block Diagram ............................................................................ 317
Figure 26.2. Multiple-Master Mode Connection Diagram ...................................... 319
Figure 26.3. 3-Wire Single Master and 3-Wire Single Slave Mode
Connection Diagram .......................................................................... 319
Figure 26.4. 4-Wire Single Master Mode and 4-Wire Slave Mode
Connection Diagram .......................................................................... 320
Figure 26.5. Master Mode Data/Clock Timing ....................................................... 322
Figure 26.6. Slave Mode Data/Clock Timing (CKPHA = 0) ................................... 323
Figure 26.7. Slave Mode Data/Clock Timing (CKPHA = 1) ................................... 323
Figure 26.8. SPI Master Timing (CKPHA = 0) ....................................................... 327
Figure 26.9. SPI Master Timing (CKPHA = 1) ....................................................... 327
Figure 26.10. SPI Slave Timing (CKPHA = 0) ....................................................... 328
Figure 26.11. SPI Slave Timing (CKPHA = 1) ....................................................... 328
Figure 27.1. T0 Mode 0 Block Diagram ................................................................. 333
Figure 27.2. T0 Mode 2 Block Diagram ................................................................. 334
Figure 27.3. T0 Mode 3 Block Diagram ................................................................. 335
Figure 27.4. Timer 2 16-Bit Mode Block Diagram ................................................. 340
Figure 27.5. Timer 2 8-Bit Mode Block Diagram ................................................... 341
Figure 27.6. Timer 2 Capture Mode Block Diagram .............................................. 342
Figure 27.7. Timer 3 16-Bit Mode Block Diagram ................................................. 346
12
Rev. 1.0
Si1000/1/2/3/4/5
Figure 27.8. Timer 3 8-Bit Mode Block Diagram. .................................................. 347
Figure 27.9. Timer 3 Capture Mode Block Diagram .............................................. 348
Figure 28.1. PCA Block Diagram ........................................................................... 352
Figure 28.2. PCA Counter/Timer Block Diagram ................................................... 353
Figure 28.3. PCA Interrupt Block Diagram ............................................................ 354
Figure 28.4. PCA Capture Mode Diagram ............................................................. 356
Figure 28.5. PCA Software Timer Mode Diagram ................................................. 357
Figure 28.6. PCA High-Speed Output Mode Diagram ........................................... 358
Figure 28.7. PCA Frequency Output Mode ........................................................... 359
Figure 28.8. PCA 8-Bit PWM Mode Diagram ........................................................ 360
Figure 28.9. PCA 9, 10 and 11-Bit PWM Mode Diagram ...................................... 361
Figure 28.10. PCA 16-Bit PWM Mode ................................................................... 362
Figure 28.11. PCA Module 5 with Watchdog Timer Enabled ................................ 363
Figure 29.1. Typical C2 Pin Sharing ...................................................................... 374
Rev. 1.0
13
Si1000/1/2/3/4/5
List of Tables
Table 2.1. Product Selection Guide ......................................................................... 27
Table 3.1. Pin Definitions for the Si1000/1/2/3/4/5 .................................................. 28
Table 3.2. QFN-42 Package Dimensions ................................................................ 35
Table 3.3. PCB Land Pattern ................................................................................... 39
Table 4.1. Absolute Maximum Ratings .................................................................... 40
Table 4.2. Global Electrical Characteristics ............................................................. 41
Table 4.3. Port I/O DC Electrical Characteristics ..................................................... 51
Table 4.4. Reset Electrical Characteristics .............................................................. 57
Table 4.5. Power Management Electrical Specifications ......................................... 58
Table 4.6. Flash Electrical Characteristics .............................................................. 58
Table 4.7. Internal Precision Oscillator Electrical Characteristics ........................... 59
Table 4.8. Internal Low-Power Oscillator Electrical Characteristics ........................ 59
Table 4.9. ADC0 Electrical Characteristics .............................................................. 60
Table 4.10. Temperature Sensor Electrical Characteristics .................................... 61
Table 4.11. Voltage Reference Electrical Characteristics ....................................... 61
Table 4.12. IREF0 Electrical Characteristics ........................................................... 62
Table 4.13. Comparator Electrical Characteristics .................................................. 63
Table 4.14. DC-DC Converter (DC0) Electrical Characteristics .............................. 65
Table 4.15. VREG0 Electrical Characteristics ......................................................... 65
1
Table 4.16. DC Characteristics .............................................................................. 66
1
Table 4.17. Synthesizer AC Electrical Characteristics ........................................... 67
1
Table 4.18. Receiver AC Electrical Characteristics ............................................... 68
1
Table 4.19. Transmitter AC Electrical Characteristics ............................................ 69
1
Table 4.20. Auxiliary Block Specifications .............................................................. 70
Table 4.21. Digital IO Specifications (nIRQ) ............................................................ 71
Table 4.22. GPIO Specifications (GPIO_0, GPIO_1, and GPIO_2) ........................ 71
Table 4.23. Absolute Maximum Ratings .................................................................. 72
Table 8.1. CIP-51 Instruction Set Summary .......................................................... 111
Table 11.1. Special Function Register (SFR) Memory Map (Page 0x0) ............... 123
Table 11.2. Special Function Register (SFR) Memory Map (Page 0xF) ............... 124
Table 11.3. Special Function Registers ................................................................. 125
Table 12.1. Interrupt Summary .............................................................................. 131
Table 13.1. Flash Security Summary .................................................................... 144
Table 14.1. Power Modes ...................................................................................... 151
Table 15.1. Example 16-bit CRC Outputs ............................................................. 159
Table 16.1. IPeak Inductor Current Limit Settings ................................................. 166
Table 19.1. Recommended XFCN Settings for Crystal Mode ............................... 184
Table 19.2. Recommended XFCN Settings for RC and C modes ......................... 185
Table 20.1. SmaRTClock Internal Registers ......................................................... 191
Table 20.2. SmaRTClock Load Capacitance Settings .......................................... 198
Table 20.3. SmaRTClock Bias Settings ................................................................ 200
Table 21.1. Port I/O Assignment for Analog Functions ......................................... 210
Table 21.2. Port I/O Assignment for Digital Functions ........................................... 210
14
Rev. 1.0
Si1000/1/2/3/4/5
Table 21.3. Port I/O Assignment for External Digital Event Capture Functions .... 211
Table 22.1. Serial Interface Timing Parameters .................................................... 230
Table 22.2. SPI Timing Parameters ...................................................................... 238
Table 23.1. EZRadioPRO Operating Modes ......................................................... 240
Table 23.2. EZRadioPRO Operating Modes Response Time ............................... 241
Table 23.3. Frequency Band Selection ................................................................. 246
Table 23.4. Packet Handler Registers ................................................................... 265
Table 23.5. Minimum Receiver Settling Time ........................................................ 267
Table 23.6. POR Parameters ................................................................................ 270
Table 23.7. Temperature Sensor Range ............................................................... 273
Table 23.8. Antenna Diversity Control ................................................................... 279
Table 23.9. EZRadioPRO Internal Register Descriptions ...................................... 284
Table 24.1. SMBus Clock Source Selection .......................................................... 291
Table 24.2. Minimum SDA Setup and Hold Times ................................................ 292
Table 24.3. Sources for Hardware Changes to SMB0CN ..................................... 296
Table 24.4. Hardware Address Recognition Examples (EHACK = 1) ................... 297
Table 24.5. SMBus Status Decoding With Hardware ACK Generation Disabled
(EHACK = 0) ....................................................................................... 306
Table 24.6. SMBus Status Decoding With Hardware ACK Generation Enabled
(EHACK = 1) ....................................................................................... 308
Table 25.1. Timer Settings for Standard Baud Rates
Using The Internal 24.5 MHz Oscillator .............................................. 316
Table 25.2. Timer Settings for Standard Baud Rates
Using an External 22.1184 MHz Oscillator ......................................... 316
Table 26.1. SPI Slave Timing Parameters ............................................................ 329
Table 27.1. Timer 0 Running Modes ..................................................................... 332
Table 28.1. PCA Timebase Input Options ............................................................. 353
Table 28.2. PCA0CPM and PCA0PWM Bit Settings for PCA
Capture/Compare Modules ................................................................ 355
Table 28.3. Watchdog Timer Timeout Intervals1 ................................................... 364
Rev. 1.0
15
Si1000/1/2/3/4/5
1. System Overview
Si1000/1/2/3/4/5 devices are fully integrated mixed-signal system-on-a-chip MCUs. Highlighted features
are listed below. Refer to Table 2.1 for specific product feature selection and part ordering numbers.
®
240–960 MHz EZRadioPRO transceiver
Single/Dual battery operation with on-chip dc-dc boost converter
High-speed pipelined 8051-compatible microcontroller core (up to 25 MIPS)
In-system, full-speed, non-intrusive debug interface (on-chip)
True 10-bit 300 ksps 23-channel single-ended ADC with analog multiplexer
6-bit programmable current reference
Precision programmable 24.5 MHz internal oscillator with spread spectrum technology
64 kB or 32 kB of on-chip flash memory
4352 bytes of on-chip RAM
2
SMBus/I C, Enhanced UART, and two Enhanced SPI serial interfaces implemented in hardware
(SPI1 is dedicated for communication with the EZRadioPRO peripheral)
Four general-purpose 16-bit timers
Programmable counter/timer array (PCA) with six capture/compare modules and watchdog timer
(WDT) function
On-chip power-on reset, V monitor, and temperature sensor
DD
Two on-chip voltage comparators with 18 touch sense inputs
19 or 22 port I/O (5 V tolerant except for GPIO_0, GPIO_1, and GPIO_2)
With on-chip power-on reset, V
monitor, watchdog timer, and clock oscillator, the Si1000/1/2/3/4/5
DD
devices are truly standalone system-on-a-chip solutions. The Flash memory can be reprogrammed even
in-circuit, providing non-volatile data storage, and also allowing field upgrades of the 8051 firmware. User
software has complete control of all peripherals, and may individually shut down any or all peripherals for
power savings.
The on-chip Silicon Labs 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip
resources), full speed, in-circuit debugging using the production MCU installed in the final application. This
debug logic supports inspection and modification of memory and registers, setting breakpoints, single
stepping, and run and halt commands. All analog and digital peripherals are fully functional while debug-
ging using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging
without occupying package pins.
Each device is specified for 1.8 to 3.6 V operation over the industrial temperature range (–40 to +85 °C).
The Port I/O and RST pins are tolerant of input signals up to 5 V. The Si1000/1/2/3/4/5 are available in a
42-pin QFN package (lead-free and RoHS compliant). See Table 2.1 for ordering information. Block dia-
grams are included in Figure 1.1 through Figure 1.6.
The transceiver's extremely low receive sensitivity (–121 dBm) coupled with industry leading +20 dBm out-
put power ensures extended range and improved link performance. Built-in antenna diversity and support
for frequency hopping can be used to further extend range and enhance performance. The advanced radio
features including continuous frequency coverage from 240–960 MHz in 156 Hz or 312 Hz steps allow pre-
cise tuning control. Additional system features such as an automatic wake-up timer, low battery detector,
64 byte TX/RX FIFOs, automatic packet handling, and preamble detection reduce overall current con-
sumption. The transceivers digital receive architecture features a high-performance ADC and DSP-based
modem which performs demodulation, filtering, and packet handling for increased flexibility and perfor-
mance. The direct digital transmit modulation and automatic PA power ramping ensure precise transmit
modulation and reduced spectral spreading, ensuring compliance with global regulations including FCC,
ETSI, ARIB, and 802.15.4d regulations.
An easy-to-use calculator is provided to quickly configure the radio settings, simplifying customer's system
design and reducing time to market.
16
Rev. 1.0
Si1000/1/2/3/4/5
CIP-51 8051
Controller Core
Analog Peripherals
RF XCVR
(240-960 MHz,
+20 dBm)
Power On
Reset/PMU
6-bit
Wake
Reset
64k Byte ISP Flash
Program Memory
IREF0
IREF
PA
TX
External
VREF
Internal
VREF
256 Byte SRAM
4096 Byte XRAM
Debug /
C2CK/RST
AGC
VDD
VREF
Programming
Hardware
RXp
A
M
U
X
10-bit
RXn
Temp
Sensor
LNA
300ksps
ADC
C2D
Mixer
PGA
ADC
CRC
Engine
GND
VDD
GND
VREG
CP0, CP0A
CP1, CP1A
+
SYSCLK
-
+
-
Comparators
Digital Peripherals
Transceiver Control Interface
SFR
Bus
Digital
Modem
Precision
24.5 MHz
Oscillator
Delta
Sigma
Modulator
Low Power
20 MHz
Oscillator
Digital
Logic
UART
External
Oscillator
Circuit
P0.2/XTAL1
P0.3/XTAL2
XIN
XOUT
Timers 0,
1, 2, 3
OSC
Priority
Crossbar
Decoder
WDT
PCA/
XTAL3
XTAL4
SmaRTClock
Oscillator
SMBus
SPI 0
22
ANALOG &
DIGITAL I/O
System Clock
Configuration
Port I/O
Config
Figure 1.1. Si1000 Block Diagram
CIP-51 8051
Controller Core
Analog Peripherals
RF XCVR
Power On
Reset/PMU
(240-960 MHz,
+20 dBm)
6-bit
Wake
Reset
32k Byte ISP Flash
Program Memory
IREF0
IREF
PA
TX
External
VREF
Internal
VREF
256 Byte SRAM
4096 Byte XRAM
Debug /
C2CK/RST
AGC
LNA
VDD
VREF
Programming
Hardware
RXp
RXn
A
M
U
X
10-bit
Temp
Sensor
300ksps
ADC
C2D
Mixer
PGA
ADC
CRC
Engine
GND
VDD
GND
VREG
CP0, CP0A
CP1, CP1A
+
SYSCLK
-
+
-
Comparators
Digital Peripherals
Transceiver Control Interface
SFR
Bus
Digital
Modem
Precision
24.5 MHz
Oscillator
Delta
Sigma
Modulator
Low Power
20 MHz
Oscillator
Digital
Logic
UART
External
Oscillator
Circuit
P0.2/XTAL1
P0.3/XTAL2
XIN
XOUT
Timers 0,
1, 2, 3
OSC
Priority
Crossbar
Decoder
WDT
PCA/
XTAL3
XTAL4
SmaRTClock
Oscillator
SMBus
SPI 0
22
ANALOG &
DIGITAL I/O
System Clock
Configuration
Port I/O
Config
Figure 1.2. Si1001 Block Diagram
Rev. 1.0
17
Si1000/1/2/3/4/5
CIP-51 8051
Controller Core
Analog Peripherals
RF XCVR
(240-960 MHz,
+13 dBm)
Power On
Reset/PMU
6-bit
Wake
Reset
64k Byte ISP Flash
Program Memory
IREF0
IREF
PA
TX
External
VREF
Internal
VREF
256 Byte SRAM
4096 Byte XRAM
Debug /
Programming
Hardware
C2CK/RST
AGC
LNA
VDD
VREF
RXp
RXn
A
M
U
X
10-bit
Temp
Sensor
300ksps
ADC
C2D
Mixer
PGA
ADC
CRC
Engine
GND
VDD
GND
VREG
CP0, CP0A
CP1, CP1A
+
SYSCLK
-
+
-
Comparators
Digital Peripherals
Transceiver Control Interface
SFR
Bus
Digital
Modem
Precision
24.5 MHz
Oscillator
Delta
Sigma
Modulator
Low Power
20 MHz
Oscillator
Digital
Logic
UART
External
Oscillator
Circuit
P0.2/XTAL1
P0.3/XTAL2
XIN
XOUT
Timers 0,
1, 2, 3
OSC
Priority
Crossbar
Decoder
WDT
PCA/
XTAL3
XTAL4
SmaRTClock
Oscillator
SMBus
SPI 0
22
ANALOG &
DIGITAL I/O
System Clock
Configuration
Port I/O
Config
Figure 1.3. Si1002 Block Diagram
CIP-51 8051
Controller Core
Analog Peripherals
RF XCVR
(240-960 MHz,
+13 dBm)
Power On
Reset/PMU
6-bit
Wake
Reset
32k Byte ISP Flash
Program Memory
IREF0
IREF
PA
TX
External
VREF
Internal
VREF
256 Byte SRAM
4096 Byte XRAM
Debug /
C2CK/RST
AGC
LNA
VDD
VREF
Programming
Hardware
RXp
RXn
A
M
U
X
10-bit
Temp
Sensor
300ksps
ADC
C2D
Mixer
PGA
ADC
CRC
Engine
GND
VDD
GND
VREG
CP0, CP0A
CP1, CP1A
+
SYSCLK
-
+
-
Comparators
Digital Peripherals
Transceiver Control Interface
SFR
Bus
Digital
Modem
Precision
24.5 MHz
Oscillator
Delta
Sigma
Modulator
Low Power
20 MHz
Oscillator
Digital
Logic
UART
External
Oscillator
Circuit
P0.2/XTAL1
P0.3/XTAL2
XIN
XOUT
Timers 0,
1, 2, 3
OSC
Priority
Crossbar
Decoder
WDT
PCA/
XTAL3
XTAL4
SmaRTClock
Oscillator
SMBus
SPI 0
22
ANALOG &
DIGITAL I/O
System Clock
Configuration
Port I/O
Config
Figure 1.4. Si1003 Block Diagram
18
Rev. 1.0
Si1000/1/2/3/4/5
CIP-51 8051
Controller Core
Analog Peripherals
RF XCVR
(240-960 MHz)
Power On
Reset/PMU
6-bit
Wake
Reset
64k Byte ISP Flash
Program Memory
IREF0
IREF
PA
TX
External
VREF
Internal
VREF
256 Byte SRAM
4096 Byte XRAM
Debug /
C2CK/RST
AGC
VDD
VREF
Programming
Hardware
RXp
A
M
U
X
10-bit
RXn
Temp
Sensor
LNA
300ksps
ADC
C2D
Mixer
PGA
ADC
CRC
Engine
GND
Power Net
VDD/DC+
GND/DC-
VREG
CP0, CP0A
CP1, CP1A
+
Analog
Power
Digital
Power
SYSCLK
-
+
-
Comparators
Digital Peripherals
Transceiver Control Interface
SFR
Bus
Digital
Modem
Precision
24.5 MHz
Oscillator
Delta
Sigma
Modulator
DC/DC
Converter
VBAT
GND
Low Power
20 MHz
Oscillator
Digital
Logic
UART
External
Oscillator
Circuit
XTAL1
XIN
XOUT
Timers 0,
1, 2, 3
OSC
XTAL2
Priority
Crossbar
Decoder
WDT
PCA/
XTAL3
XTAL4
SmaRTClock
Oscillator
SMBus
SPI 0
19
ANALOG &
DIGITAL I/O
System Clock
Configuration
Port I/O
Config
Figure 1.5. Si1004 Block Diagram
CIP-51 8051
Controller Core
Analog Peripherals
RF XCVR
(240-960 MHz)
Power On
Reset/PMU
6-bit
Wake
Reset
32k Byte ISP Flash
Program Memory
IREF0
IREF
PA
TX
External
VREF
Internal
VREF
256 Byte SRAM
4096 Byte XRAM
Debug /
C2CK/RST
AGC
LNA
VDD
VREF
Programming
Hardware
RXp
RXn
A
M
U
X
10-bit
Temp
Sensor
300ksps
ADC
C2D
Mixer
PGA
ADC
CRC
Engine
GND
Power Net
VDD/DC+
GND/DC-
VREG
CP0, CP0A
CP1, CP1A
+
Analog
Power
Digital
Power
SYSCLK
-
+
-
Comparators
Digital Peripherals
Transceiver Control Interface
SFR
Bus
Digital
Modem
Precision
24.5 MHz
Oscillator
Delta
Sigma
Modulator
DC/DC
Converter
VBAT
GND
Low Power
20 MHz
Oscillator
Digital
Logic
UART
External
Oscillator
Circuit
XTAL1
XTAL2
XIN
XOUT
Timers 0,
1, 2, 3
OSC
Priority
Crossbar
Decoder
WDT
PCA/
XTAL3
XTAL4
SmaRTClock
Oscillator
SMBus
SPI 0
19
ANALOG &
DIGITAL I/O
System Clock
Configuration
Port I/O
Config
Figure 1.6. Si1005 Block Diagram
Rev. 1.0
19
Si1000/1/2/3/4/5
1.1. Typical Connection Diagram
The application shown in Figure 1.7 is designed for a system with a TX/RX direct-tie configuration without
the use of a TX/RX switch. Most lower power applications will use this configuration. A complete direct-tie
reference design is available from Silicon Laboratories applications support.
For applications seeking improved performance in the presence of multipath fading, antenna diversity can
be used. Antenna diversity support is integrated into the EZRadioPRO transceiver and can improve the
system link budget by 8–10 dB in the presence of these fading conditions, resulting in substantial range
increases. A complete Antenna Diversity reference design is available from Silicon Laboratories applica-
tions support.
supply voltage
X1
30MHz
C6
C7
C8
1u
100p
100n
L1
VDD_RF
VDD_MCU
VDD_DIG
L2
TX
Px.x
L4
C3
L3
C2
C1
RFp
Si100x
RXn
C4
0.1 uF
0.1 uF
L6
L5
C9
1u
C5
Programmable load capacitors for X1 are integrated.
L1-L6 and C1-C5 values depend on frequency band, antenna
impedance, output power and supply voltage range.
Figure 1.7. Si1002/3 RX/TX Direct-tie Application Example
Supply Voltage
X1
30 MHz
C6
C7
C8
1 u
100 p
100 n
L1
VDD_RF
VDD_MCU
VDD_DIG
TR & ANT-DIV
Switch
L3
L2
TX
Px.x
C1
C3
C2
RXp
1
6
5
4
Si100x
RXn
2
3
C4
0.1 uF
0.1 uF
L4
C9
1u
C5
Programmable load capacitors for X1 are
integrated.
L1–L4 and C1–C5 values depend on frequency
band, antenna impedance, output power, and
supply voltage range.
Figure 1.8. Si1000/1 Antenna Diversity Application Example
20
Rev. 1.0
Si1000/1/2/3/4/5
1.2. CIP-51™ Microcontroller Core
1.2.1. Fully 8051 Compatible
The Si1000/1/2/3/4/5 family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-51 is
fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be
used to develop software. The CIP-51 core offers all the peripherals included with a standard 8052.
1.2.2. Improved Throughput
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan-
dard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute with a maximum system clock of 12-to-24 MHz. By contrast, the CIP-51 core exe-
cutes 70% of its instructions in one or two system clock cycles, with only four instructions taking more than
four system clock cycles.
The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that
require each execution time.
Clocks to Execute
1
2
2/3
5
3
3/4
7
4
3
4/5
1
5
2
8
1
Number of Instructions
26
50
14
With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS.
1.2.3. Additional Features
The Si1000/1/2/3/4/5 SoC family includes several key enhancements to the CIP-51 core and peripherals to
improve performance and ease of use in end applications.
The extended interrupt handler provides multiple interrupt sources into the CIP-51, allowing numerous
analog and digital peripherals to interrupt the controller. An interrupt driven system requires less interven-
tion by the MCU, giving it more effective throughput. The extra interrupt sources are very useful when
building multi-tasking, real-time systems.
Eight reset sources are available: power-on reset circuitry (POR), an on-chip V
monitor (forces reset
DD
when power supply voltage drops below safe levels), a watchdog timer, a Missing Clock Detector, SmaRT-
Clock oscillator fail or alarm, a voltage level detection from Comparator0, a forced software reset, an exter-
nal reset pin, and an illegal Flash access protection circuit. Each reset source except for the POR, Reset
Input Pin, or Flash error may be disabled by the user in software. The WDT may be permanently disabled
in software after a power-on reset during MCU initialization.
The internal oscillator factory is calibrated to 24.5 MHz and is accurate to ±2% over the full temperature
and supply range. The internal oscillator period can also be adjusted by user firmware. An additional
20 MHz low power oscillator is also available which facilitates low-power operation. An external oscillator
drive circuit is included, allowing an external crystal, ceramic resonator, capacitor, RC, or CMOS clock
source to generate the system clock. If desired, the system clock source may be switched between both
internal and external oscillator circuits. An external oscillator can also be extremely useful in low power
applications, allowing the MCU to run from a slow (power saving) source, while periodically switching to
the fast (up to 25 MHz) internal oscillator as needed.
Rev. 1.0
21
Si1000/1/2/3/4/5
1.3. Port Input/Output
Digital and analog resources are available through 19 (Si1000/1/2/3) or 16 (Si1004/5) I/O pins. Three addi-
tional GPIO pins are available through the EZRadioPRO peripheral. Port pins are organized as three byte-
wide ports. Port pins P0.0–P2.6 can be defined as digital or analog I/O. Digital I/O pins can be assigned to
one of the internal digital resources or used as general purpose I/O (GPIO). Analog I/O pins are used by
the internal analog resources. P1.0, P1.1, P1.2, and P1.4 are dedicated for communication with the EZRa-
dioPRO peripheral. P1.3 is not available. P2.7 can be used as GPIO and is shared with the C2 Interface
Data signal (C2D). See Section “29. C2 Interface” on page 371 for more details.
The designer has complete control over which digital and analog functions are assigned to individual port
pins and is limited only by the number of physical I/O pins. This resource assignment flexibility is achieved
through the use of a Priority Crossbar Decoder. See Section “21.3. Priority Crossbar Decoder” on
page 211 for more information on the crossbar.
All Px.x Port I/Os are 5 V tolerant when used as digital inputs or open-drain outputs. For Port I/Os config-
ured as push-pull outputs, current is sourced from the VDD_MCU supply. Port I/Os used for analog func-
tions can operate up to the VDD_MCU supply voltage. See Section “21.1. Port I/O Modes of Operation” on
page 208 for more information on Port I/O operating modes and the electrical specifications chapter for
detailed electrical specifications.
XBR0, XBR1,
XBR2, PnSKIP
Registers
Port Match
P0MASK, P0MAT
P1MASK, P1MAT
External Interrupts
EX0 and EX1
Priority
Decoder
PnMDOUT,
PnMDIN Registers
2
UART
Highest
Priority
4
2
SPI0
SPI1
P0.0
P0.7
SMBus
P0
I/O
Cells
Digital
Crossbar
8
8
CP0
CP1
Outputs
4
P1.5
P1.6
P1.7
SYSCLK
PCA
P1
I/O
Cells
7
2
Lowest
Priority
T0, T1
8
P2.0
8
P0
P1
P2
(P0.0-P0.7)
P2
I/O
Cell
P2.6
P2.7
8
(P1.0-P1.7)
To Analog Peripherals
(ADC0, CP0, and CP1 inputs,
VREF, IREF0, AGND)
No analog functionality
available on P2.7
8
(P2.0-P2.7)
Note: P1.0, P1.1, P1.2, and P1.4 are internally connected to the
EZRadioPRO peripheral. P1.3 is not internally or externally connected.
P2.4, P2.5, and P2.6 are only available on Si1000/1/2/3
Figure 1.9. Port I/O Functional Block Diagram
22
Rev. 1.0
Si1000/1/2/3/4/5
1.4. Serial Ports
2
The Si1000/1/2/3/4/5 family includes an SMBus/I C interface, a full-duplex UART with enhanced baud rate
configuration, and an Enhanced SPI interface. Each of the serial buses is fully implemented in hardware
and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention. There is
also a dedicated EZRadioPRO Serial Interface (SPI1) to allow communication with the EZRadioPRO
peripheral.
1.5. Programmable Counter Array
An on-chip Programmable Counter/Timer Array (PCA) is included in addition to the four 16-bit general pur-
pose counter/timers. The PCA consists of a dedicated 16-bit counter/timer time base with six programma-
ble capture/compare modules. The PCA clock is derived from one of six sources: the system clock divided
by 12, the system clock divided by 4, Timer 0 overflows, an External Clock Input (ECI), the system clock, or
the external oscillator clock source divided by 8.
Each capture/compare module can be configured to operate in a variety of modes: edge-triggered capture,
software timer, high-speed output, pulse width modulator (8, 9, 10, 11, or 16-bit), or frequency output. Addi-
tionally, Capture/Compare Module 5 offers watchdog timer capabilities. Following a system reset, Module 5
is configured and enabled in WDT mode. The PCA Capture/Compare Module I/O and External Clock Input
may be routed to Port I/O via the Digital Crossbar.
SYSCLK/12
SYSCLK/4
PCA
CLOCK
MUX
Timer0 Overflow
ECI
16 -Bit Counter/Timer
SYSCLK
External Clock 8
/
Capture/ Compare
Module0
Capture/ Compare
Module1
Capture/ Compare
Module2
Capture/ Compare
Module3
Capture/ Compare
Module4
Capture/ Compare
Module5 / WDT
Crossbar
Port I/O
Figure 1.10. PCA Block Diagram
Rev. 1.0
23
Si1000/1/2/3/4/5
1.6. 10-bit SAR ADC with 16-bit Auto-Averaging Accumulator and Autonomous
Low Power Burst Mode
Si1000/1/2/3/4/5 devices have a 300 ksps, 10-bit successive-approximation-register (SAR) ADC with inte-
grated track-and-hold and programmable window detector. ADC0 also has an autonomous low power
Burst Mode which can automatically enable ADC0, capture and accumulate samples, then place ADC0 in
a low power shutdown mode without CPU intervention. It also has a 16-bit accumulator that can automati-
cally average the ADC results, providing an effective 11, 12, or 13-bit ADC result without any additional
CPU intervention.
The ADC can sample the voltage at any of the GPIO pins (with the exception of P2.7) and has an on-chip
attenuator that allows it to measure voltages up to twice the voltage reference. Additional ADC inputs
include an on-chip temperature sensor, the VDD_MCU supply voltage, the VBAT supply voltage, and the
internal digital supply voltage.
ADC0CN
VDD
000
001
010
011
100
AD0BUSY (W)
Timer 0 Overflow
Timer 2 Overflow
Timer 3 Overflow
CNVSTR Input
Start
Conversion
ADC0TK
Burst Mode Logic
ADC0PWR
10-bit
SAR
AIN+
From
AMUX0
16-Bit Accumulator
ADC
AD0WINT
Window
Compare
Logic
32
ADC0LTH ADC0LTL
ADC0GTH ADC0GTL
ADC0CF
Figure 1.11. ADC0 Functional Block Diagram
24
Rev. 1.0
Si1000/1/2/3/4/5
ADC0MX
P0.0
Programmable
Attenuator
AIN+
ADC0
AMUX
P2.6*
Temp
Sensor
Gain=0. 5 or1
Digital Supply
VDD_MCU
*P1.0 – P1.4 are not
available as device pins
Figure 1.12. ADC0 Multiplexer Block Diagram
1.7. Programmable Current Reference (IREF0)
Si1000/1/2/3/4/5 devices include an on-chip programmable current reference (source or sink) with two out-
put current settings: low power mode and high current mode. The maximum current output in low power
mode is 63 µA (1 µA steps) and the maximum current output in high current mode is 504 µA (8 µA steps).
1.8. Comparators
Si1000/1/2/3/4/5 devices include two on-chip programmable voltage comparators: Comparator 0 (CPT0),
which is shown in Figure 1.13, and Comparator 1 (CPT1), which is shown in Figure 1.14. The two compar-
ators operate identically but may differ in their ability to be used as reset or wake-up sources. See Section
“18. Reset Sources” on page 175 and Section “14. Power Management” on page 151 for details on reset
sources and low power mode wake-up sources, respectively.
The comparators offer programmable response time and hysteresis, an analog input multiplexer, and two
outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0, CP1), or an
asynchronous “raw” output (CP0A, CP1A). The asynchronous CP0A signal is available even when the
system clock is not active. This allows the comparator to operate and generate an output when the device
is in some low power modes.
The comparator inputs may be connected to Port I/O pins or to other internal signals. Port pins may also be
used to directly sense capacitive touch switches. See Application Note “AN338: Capacitive Touch Sense
Solution” for details on Capacitive Touch Switch sensing.
Rev. 1.0
25
Si1000/1/2/3/4/5
CP0EN
CP0OUT
CP0RIF
VDD
CP0FIF
CP0HYP1
CP0HYP0
CP0HYN1
CP0HYN0
CP0
Interrupt
CPT0MD
Analog Input Multiplexer
CP0
Rising-edge
CP0
Falling-edge
Px.x
CP0 +
Interrupt
Logic
Px.x
Px.x
CP0
+
-
SET
SET
CLR
D
Q
Q
D
Q
Q
CLR
Crossbar
(SYNCHRONIZER)
(ASYNCHRONOUS)
GND
CP0 -
CP0A
Reset
Decision
Tree
Px.x
Figure 1.13. Comparator 0 Functional Block Diagram
CP1EN
CP1OUT
CP1RIF
CP1FIF
VDD
CP1HYP1
CP1HYP0
CP1HYN1
CP1HYN0
CP1
Interrupt
CPT0MD
Analog Input Multiplexer
CP1
Rising-edge
CP1
Falling-edge
Px.x
CP1 +
Interrupt
Logic
Px.x
Px.x
CP1
+
-
SET
SET
CLR
D
Q
Q
D
Q
Q
CLR
Crossbar
(SYNCHRONIZER)
(ASYNCHRONOUS)
GND
CP1 -
CP1A
Reset
Decision
Tree
Px.x
Figure 1.14. Comparator 1 Functional Block Diagram
26
Rev. 1.0
Si1000/1/2/3/4/5
2. Ordering Information
Table 2.1. Product Selection Guide
Si1000-C-GM 25 64 4352
Si1001-C-GM 25 32 4352
Si1002-C-GM 25 64 4352
Si1003-C-GM 25 32 4352
Si1004-C-GM 25 64 4352
Si1005-C-GM 25 32 4352
P
P
P
P
P
P
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4
4
4
4
4
4
P
P
P
P
P
P
22 P
22 P
22 P
22 P
19 P
19 P
P
P
P
P
P
P
P
P
P
P
P
P
+20 dBm 1.8 P QFN-42
+20 dBm 1.8 P QFN-42
+13 dBm 1.8 P QFN-42
+13 dBm 1.8 P QFN-42
+13 dBm 0.9 P QFN-42
+13 dBm 0.9 P QFN-42
Rev. 1.0
27
Si1000/1/2/3/4/5
3. Pinout and Package Definitions
Table 3.1. Pin Definitions for the Si1000/1/2/3/4/5
Name
Pin Number
Type
Description
Si1000/1
Si1002/3
Si1004/5
VDD_MCU
GND_MCU
VBAT
38
—
P In
G
Power Supply Voltage for the entire MCU except for the
EZRadioPRO peripheral. Must be 1.8 to 3.6 V.
37
—
—
41
38
Required Ground for the entire MCU except for the
EZRadioPRO peripheral.
P In
Battery Supply Voltage. Must be 0.9 to 1.8 V in single-cell
battery mode and 1.8 to 3.6 V in dual-cell battery mode.
GND
—
P In
G
In dual-cell battery mode, this pin must be connected
directly to ground.
In one-cell applications, this pin should be connected
directly to the negative battery terminal, which is not
connected to the ground plane.
VBAT-
DCEN
—
—
40
39
P In
G
DC-DC Enable Pin. In single-cell battery mode, this pin
must be connected to VBAT through a 0.68 µH inductor.
In dual-cell battery mode, this pin must be connected
directly to ground.
VDD_MCU /
DC+
P In
Power Supply Voltage for the entire MCU except for the
EZRadioPRO peripheral. Must be 1.8 to 3.6 V. This supply
voltage is not required in low power sleep mode. This
voltage must always be > VBAT.
P Out Positive output of the dc-dc converter. In single-cell battery
mode, a 1uF ceramic capacitor is required between dc+ and
dc–. This pin can supply power to external devices when
operating in single-cell battery mode.
GND_MCU
DC–
—
37
G
G
In dual-cell battery mode, this pin must be connected
directly to ground.
DC-DC converter return current path. In one-cell mode, this
pin must be connected to the ground plane.
VDD_RF
VDD_DIG
VR_DIG
16
28
27
16
28
27
P In
P In
Power Supply Voltage for the analog portion of the
EZRadioPRO peripheral. Must be 1.8 to 3.6 V.
Power Supply Voltage for the digital portion of the
EZRadioPRO peripheral. Must be 1.8 to 3.6 V.
P Out Regulated Output Voltage of the digital 1.7 V regulator for
the EZRadioPRO peripheral. A 1 µF decoupling capacitor is
required.
GND_RF
23
23
G
Required Ground for the digital and analog portions of the
EZRadioPRO peripheral.
28
Rev. 1.0
Si1000/1/2/3/4/5
Table 3.1. Pin Definitions for the Si1000/1/2/3/4/5 (Continued)
Name
Pin Number
Type
Description
Si1000/1
Si1002/3
Si1004/5
RST/
39
42
D I/O Device Reset. Open-drain output of internal POR or V
DD
monitor. An external source can initiate a system reset by
driving this pin low for at least 15 µs. A 1–5 k pullup to
VDD_MCU is recommended. See Reset Sources section
for a complete description.
C2CK
P2.7/
D I/O
Clock signal for the C2 Debug Interface.
40
1
D I/O Port 2.7. This pin can only be used as GPIO. The Crossbar
cannot route signals to this pin and it cannot be configured
as an analog input. See Port I/O section for a complete
description.
C2D
D I/O Bi-directional data signal for the C2 Debug Interface.
XTAL3
1
3
2
A In
SmaRTClock Oscillator Crystal Input.
See Section 20 for a complete description.
XTAL4
P0.0
42
36
A Out SmaRTClock Oscillator Crystal Output.
See Section 20 for a complete description.
36
D I/O or Port 0.0. See Port I/O section for a complete description.
A In
A In
V
External V
Input.
REF
REF
A Out
Internal V
Output. External V
decoupling capacitors
REF
REF
are recommended. See Voltage Reference section.
P0.1
35
34
35
34
D I/O or Port 0.1. See Port I/O Section for a complete description.
A In
G
AGND
P0.2
Optional Analog Ground. See VREF chapter.
D I/O or Port 0.2. See Port I/O Section for a complete description.
A In
A In
XTAL1
P0.3
External Clock Input. This pin is the external oscillator
return for a crystal or resonator. See Oscillator section.
33
33
D I/O or Port 0.3. See Port I/O Section for a complete description.
A In
A Out
D In
XTAL2
External Clock Output. This pin is the excitation driver for an
external crystal or resonator.
External Clock Input. This pin is the external clock input in
external CMOS clock mode.
External Clock Input. This pin is the external clock input in
capacitor or RC oscillator configurations.
A In
See Oscillator section for complete details.
Rev. 1.0
29
Si1000/1/2/3/4/5
Table 3.1. Pin Definitions for the Si1000/1/2/3/4/5 (Continued)
Name
Pin Number
Type
Description
Si1000/1
Si1002/3
Si1004/5
P0.4
32
32
D I/O or Port 0.4. See Port I/O section for a complete description.
A In
D Out
TX
UART TX Pin. See Port I/O section.
P0.5
31
30
31
30
D I/O or Port 0.5. See Port I/O section for a complete description.
A In
D In
RX
UART RX Pin. See Port I/O section.
P0.6
D I/O or Port 0.6. See Port I/O section for a complete description.
A In
D In
CNVSTR
P0.7
External Convert Start Input for ADC0. See ADC0 section
for a complete description.
29
29
D I/O or Port 0.7. See Port I/O section for a complete description.
A In
A Out
IREF0
P1.5
IREF0 Output. See IREF section for complete description.
10
9
10
9
D I/O or Port 1.5. See Port I/O section for a complete description.
A In
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
D I/O or Port 1.6. See Port I/O section for a complete description.
A In
8
8
D I/O or Port 1.7. See Port I/O section for a complete description.
A In
7
7
D I/O or Port 2.0. See Port I/O section for a complete description.
A In
6
6
D I/O or Port 2.1. See Port I/O section for a complete description.
A In
5
5
D I/O or Port 2.2. See Port I/O section for a complete description.
A In
4
4
D I/O or Port 2.3. See Port I/O section for a complete description.
A In
3
—
—
—
D I/O or Port 2.4. See Port I/O section for a complete description.
A In
2
D I/O or Port 2.5. See Port I/O section for a complete description.
A In
41
D I/O or Port 2.6. See Port I/O section for a complete description.
A In
30
Rev. 1.0
Si1000/1/2/3/4/5
Table 3.1. Pin Definitions for the Si1000/1/2/3/4/5 (Continued)
Name
Pin Number
Type
Description
Si1000/1
Si1002/3
Si1004/5
GPIO_0
GPIO_1
GPIO_2
nIRQ
24
24
D I/O or General Purpose I/O controlled by the EZRadioPRO periph-
eral. May be configured through the EZRadioPRO registers
to perform various functions including: Clock Output, FIFO
status, POR, Wake-Up Timer, Low Battery Detect, TRSW,
AntDiversity control, etc. See the EZRadioPRO GPIO Con-
figuration Registers for more information.
A I/O
25
26
11
25
26
11
D I/O or
A I/O
D I/O or
A I/O
D O
EZRadioPRO peripheral interrupt status pin. Will be set low
to indicate a pending EZRadioPRO interrupt event. See the
EZRadioPRO Control Logic Registers for more details. This
pin is an open-drain output with a 220 k internal pullup
resistor. An external pull-up resistor is recommended.
XOUT
XIN
12
13
12
13
A O
A I
EZRadioPRO peripheral crystal oscillator output. Connect
to an external 30 MHz crystal or leave floating if driving the
XIN pin with an external signal source.
EZRadioPRO peripheral crystal oscillator input. Connect to
an external 30 MHz crystal or to an external source. If using
an external clock source with no crystal, dc coupling with a
nominal 0.8 VDC level is recommended with a minimum
ac amplitude of 700 mVpp.
NC
14, 20, 14, 20,
No Connect. May be left floating or tied to power or ground.
22
22
SDN
15
15
D I
EZRadioPRO peripheral shutdown pin. When driven to
logic HIGH, the EZRadioPRO peripheral will be completely
shut down and the contents of the EZRadioPRO registers
will be lost. This pin should be driven to logic LOW during all
other times; this pin should never be left floating.
TX
17
17
A O
EZRadioPRO peripheral transmit RF output pin. The PA
output is an open-drain connection so the L-C match must
supply (1.8 to 3.6 VDC) to this pin.
RXp
RXn
18
19
18
19
A I
A I
EZRadioPRO peripheral differential RF input pins of the
LNA. See application schematic for example matching net-
work.
ANT_A
21
21
D O
EZRadioPRO peripheral TR switch control signal.
Rev. 1.0
31
Si1000/1/2/3/4/5
XTAL3
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
P1.7
P1.6
1
2
3
4
5
6
7
8
9
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P0.1/AGND
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7/IREF0
VDD_DIG
VR_DIG
GND_MCU
Si1000/1/2/3
Top View
P1.5 10
nIRQ 11
XOUT 12
XIN 13
GPIO_2
GPIO_1
GPIO_0
GND_RF
N.C.
GND_RF
N.C. 14
Figure 3.1. Si1000/1/2/3 Pinout Diagram (Top View)
32
Rev. 1.0
Si1000/1/2/3/4/5
P2.7/C2D
XTAL4
XTAL3
P2.3
1
2
3
4
5
6
7
8
9
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P0.1/AGND
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P2.2
P0.5/RX
P2.1
P0.6/CNVSTR
P0.7/IREF0
VDD_DIG
VR_DIG
GND_MCU
P2.0
Si1004/5
Top View
P1.7
P1.6
P1.5 10
nIRQ 11
XOUT 12
XIN 13
GPIO_2
GPIO_1
GPIO_0
GND_RF
N.C.
GND_RF
N.C. 14
Figure 3.2. Si1004/5 Pinout Diagram (Top View)
Rev. 1.0
33
Si1000/1/2/3/4/5
Figure 3.3. QFN-42 Package Drawing
34
Rev. 1.0
Si1000/1/2/3/4/5
Table 3.2. QFN-42 Package Dimensions
Dimension
Min
Typ
Max
Dimension
Min
Typ
Max
A
b
0.60
0.20
0.65
0.25
0.70
0.30
F
G
0.07 REF
1.42 BSC
0.30
D
5.00 BSC
3.00 BSC
4.25 BSC
3.16
L
0.25
0.50
0.35
0.60
D1
D2
D3
D4
L1
L2
L3
0.55
0.10 REF
0.125 REF
0.525 BSC
3.11
2.68
3.21
2.78
4
2.73
P1
4
e
0.50 BSC
0.475 BSC
P2
E
E1
7.00 BSC
6.50 BSC
3.00 BSC
2.97
aaa
bbb
ccc
ddd
fff
—
—
—
—
—
—
—
—
—
—
0.15
0.10
0.10
0.05
0.10
E2
E3
2.92
2.58
3.02
2.68
E4
2.63
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small
Body Components.
4. All pitches other than P1, P2 are represented by e.
Rev. 1.0
35
Si1000/1/2/3/4/5
Figure 3.4. Typical QFN-42 Landing Diagram
36
Rev. 1.0
Si1000/1/2/3/4/5
Figure 3.5. VIA Placement and Keepout Region
Rev. 1.0
37
Si1000/1/2/3/4/5
Figure 3.6. Typical PCB Stencil Diagram
38
Rev. 1.0
Si1000/1/2/3/4/5
Table 3.3. PCB Land Pattern
Dimension
Value
C1
4.75
X1 (27x)
Y1 (27x)
C2
0.95
0.30
7.00
0.30
0.70
0.50
>1.00
0.125
2.73
2.63
1.59
3.16
2.97
0.07
1.42
X2 (15x)
Y2 (15x)
E
K
X3
X4
Y4
Y5
X6
Y6
X7
Y7
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This land pattern design is based on the IPC-7351 guidelines.
PCB Design
1. High-Tg PCB materials (Glass Transition Temperature > 170° C are recommended for Pb-free reflow profiles per standard industry practice.
2. PCB design must ensure sufficient thermal relief for operation of the device.
3. Via placement must minimize mechanical stress due to CTE mismatch between PCB material and the package while maintaining electrical or
thermal performance as required for the particular application.
a. A minimum of four vias are required under each E-pad; eight or more vias are recommended for designs that require increased thermal
conductivity.
b. Via diameters should be between 0.20 and 0.31 mm (8 to 12 mil).
c. Metal-to-metal distance between outer edge of via diameter and closest edge of device perimeter pad must be > 1.00 mm (dimension "K").
d. Vias may be placed as desired within the non-hatched area of the E-pads. Final via size and quantity is dependent on choice of PCB
materials and total thermal relief provided by internal Cu plane in the PCB.
e. Vias should either be filled or tented on the top-side of the board to prevent solder from migrating away from the E-pads during reflow.
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad should be 60 µm minimum
around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
4. A 3x3 array of 0.7 mm square openings on 0.9 mm pitch should be used for the upper center ground pad.
5. A 3x3 array of 0.8 mm square openings on 1.0 mm pitch should be used for the lower center ground pad.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
Rev. 1.0
39
Si1000/1/2/3/4/5
4. Electrical Characteristics
In sections 4.1 and 4.2, , “V ” refers to the VDD_MCU supply voltage on Si1000/1/2/3 devices and to the
DD
VDD_MCU/DC+ supply voltage on Si1004/5 devices. The ADC, Comparator, and Port I/O specifications in
these two sections do not apply to the EZRadioPRO peripheral.
In sections 4.3 and 4.4, “V ” refers to the VDD_RF and VDD_DIG Supply Voltage. All specifications in
DD
these sections pertain to the EZRadioPRO peripheral.
4.1. Absolute Maximum Specifications
Table 4.1. Absolute Maximum Ratings
Parameter
Conditions
Min
Typ
Max
Units
Ambient Temperature under Bias
Storage Temperature
–55
–65
—
—
125
150
5.8
°C
°C
V
Voltage on any Px.x I/O Pin or
RST with Respect to GND
V
V
> 2.2 V
< 2.2 V
–0.3
–0.3
—
—
DD
DD
V
+ 3.6
DD
Voltage on VBAT with respect to One-Cell Mode
–0.3
–0.3
—
—
2.0
4.0
V
V
GND
Two-Cell Mode
Voltage on VDD_MCU or
VDD_MCU/DC+ with respect to
GND
–0.3
—
4.0
Maximum Total Current through
VBAT, DCEN, VDD_MCU/DC+ or
GND
—
—
500
mA
Maximum Output Current Sunk
by RST or any Px.x Pin
—
—
—
—
100
200
mA
mA
Maximum Total Current through
all Px.x Pins
DC-DC Converter Output Power
ESD (Human Body Model)
—
—
—
—
110
2
mW
kV
All pins except TX, RXp,
and RXn
TX, RXp, and RXn
—
—
—
—
1
kV
V
ESD (Machine Model)
All pins except TX, RXp,
and RXn
150
TX, RXp, and RXn
—
—
45
V
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the devices at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
40
Rev. 1.0
Si1000/1/2/3/4/5
4.2. MCU Electrical Characteristics
Table 4.2. Global Electrical Characteristics
–40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the
‘F9xx" for details on how to achieve the supply current specifications listed in this table.
Parameter
Conditions
Min
Typ
Max
Units
Battery Supply Voltage (VBAT) One-Cell Mode
Two-Cell Mode
0.9
1.8
1.2
2.4
1.8
3.6
V
Supply Voltage
(VDD_MCU/DC+)
One-Cell Mode
Two-Cell Mode
1.8
1.8
1.9
2.4
3.6
3.6
V
V
Minimum RAM Data
VDD (not in Sleep Mode)
VBAT (in Sleep Mode)
—
—
1.4
0.3
—
0.5
1
Retention Voltage
2
SYSCLK (System Clock)
0
—
—
—
—
25
—
MHz
ns
T
T
(SYSCLK High Time)
18
SYSH
SYSL
(SYSCLK Low Time)
18
—
ns
Specified Operating
–40
+85
°C
Temperature Range
Rev. 1.0
41
Si1000/1/2/3/4/5
Table 4.2. Global Electrical Characteristics (Continued)
–40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the
‘F9xx" for details on how to achieve the supply current specifications listed in this table.
Parameter
Conditions
Min
Typ
Max
Units
Digital Supply Current—CPU Active (Normal Mode, fetching instructions from Flash)
3, 4, 5, 6, 7, 8
—
4.1
5.0
mA
mA
I
V
= 1.8–3.6 V, F = 24.5 MHz
DD
DD
(includes precision oscillator current)
—
3.5
—
V
= 1.8–3.6 V, F = 20 MHz
DD
(includes low power oscillator current)
—
—
295
365
—
—
µA
µA
V
V
= 1.8 V, F = 1 MHz
= 3.6 V, F = 1 MHz
DD
DD
(includes external oscillator/GPIO cur-
rent)
—
—
—
90
—
—
—
µA
V
= 1.8–3.6 V, F = 32.768 kHz
DD
(includes SmaRTClock oscillator cur-
rent)
3, 5, 6,
226
120
µA/MHz
µA/MHz
I
Frequency Sensitivity
V
= 1.8–3.6 V, T = 25 °C,
DD
DD
7. 8
F < 10 MHz (Flash oneshot active, see
13.6)
V
= 1.8–3.6 V, T = 25 °C,
DD
F > 10 MHz (Flash oneshot bypassed,
see 13.6)
Digital Supply Current—CPU Inactive (Idle Mode, not fetching instructions from Flash)
4, 6,7,8
—
2.5
3.0
mA
mA
I
V
= 1.8–3.6 V, F = 24.5 MHz
DD
DD
(includes precision oscillator current)
—
1.8
—
V
= 1.8–3.6 V, F = 20 MHz
DD
(includes low power oscillator current)
—
—
165
235
—
—
µA
µA
V
V
= 1.8 V, F = 1 MHz
= 3.6 V, F = 1 MHz
DD
DD
(includes external oscillator/GPIO cur-
rent)
—
—
84
95
—
—
µA
V
= 1.8–3.6 V, F = 32.768 kHz
DD
(includes SmaRTClock oscillator
current)
1,6,8
µA/MHz
I
Frequency Sensitivity
V
= 1.8–3.6 V, T = 25 °C
DD
DD
42
Rev. 1.0
Si1000/1/2/3/4/5
Table 4.2. Global Electrical Characteristics (Continued)
–40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the
‘F9xx" for details on how to achieve the supply current specifications listed in this table.
Parameter
Conditions
Min
Typ
Max
Units
Digital Supply Current—Suspend and Sleep Mode
6,7,8
—
77
—
µA
µA
Digital Supply Current
(Suspend Mode)
V
= 1.8–3.6 V, two-cell mode
DD
8
1.8 V, T = 25 °C
3.0 V, T = 25 °C
3.6 V, T = 25 °C
1.8 V, T = 85 °C
3.0 V, T = 85 °C
3.6 V, T = 85 °C
(includes SmaRTClock oscillator and
brownout detector)
—
—
—
—
—
—
0.61
0.76
0.87
1.32
1.62
1.93
—
—
—
—
—
—
Digital Supply Current
(Sleep Mode, SmaRTClock
running)
8
1.8 V, T = 25 °C
3.0 V, T = 25 °C
3.6 V, T = 25 °C
1.8 V, T = 85 °C
3.0 V, T = 85 °C
3.6 V, T = 85 °C
(includes brownout detector)
—
—
—
—
—
—
0.06
0.09
0.14
0.77
0.92
1.23
—
—
—
—
—
—
µA
Digital Supply Current
(Sleep Mode)
Rev. 1.0
43
Si1000/1/2/3/4/5
Table 4.2. Global Electrical Characteristics (Continued)
–40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the
‘F9xx" for details on how to achieve the supply current specifications listed in this table.
Parameter
Conditions
Min
Typ
Max
Units
Notes:
1. Based on device characterization data; Not production tested.
2. SYSCLK must be at least 32 kHz to enable debugging.
3. Digital Supply Current depends upon the particular code being executed. The values in this table are obtained
with the CPU executing an “sjmp $” loop, which is the compiled form of a while(1) loop in C. One iteration
requires 3 CPU clock cycles, and the Flash memory is read on each cycle. The supply current will vary
slightly based on the physical location of the sjmp instruction and the number of Flash address lines that
toggle as a result. In the worst case, current can increase by up to 30% if the sjmp loop straddles a 128-byte
Flash address boundary (e.g., 0x007F to 0x0080). Real-world code with larger loops and longer linear
sequences will have few transitions across the 128-byte address boundaries.
4. Includes oscillator and regulator supply current.
5. IDD can be estimated for frequencies <10 MHz by simply multiplying the frequency of interest by the
frequency sensitivity number for that range, then adding an offset of 90 µA. When using these numbers to
estimate IDD for >10 MHz, the estimate should be the current at 25 MHz minus the difference in current
indicated by the frequency sensitivity number. For example: VDD = 3.0 V; F = 20 MHz, IDD = 4.1 mA –
(25 MHz – 20 MHz) x 0.120 mA/MHz = 3.5 mA.
6. The Supply Voltage is the voltage at the VDD_MCU pin, typically 1.8 to 3.6 V (default = 1.9 V).
Idle IDD can be estimated by taking the current at 25 MHz minus the difference in current indicated by the
frequency sensitivity number. For example: VDD = 3.0 V; F = 5 MHz, Idle IDD = 2.5 mA – (25 MHz –
5 MHz) x 0.095 mA/MHz = 0.6 mA.
7. The supply current specifications in Table 4.2 are for two cell mode. The VBAT current in one-cell mode can
be estimated using the following equation:
Supply Voltage Supply Current (two-cell mode)
DC-DC Converter Efficiency VBAT Voltage
----------------------------------------------------------------------------------------------------------------------------------
VBAT Current (one-cell mode) =
The VBAT Voltage is the voltage at the VBAT pin, typically 0.9 to 1.8 V.
The Supply Current (two-cell mode) is the data sheet specification for supply current.
The Supply Voltage is the voltage at the VDD/DC+ pin, typically 1.8 to 3.3 V (default = 1.9 V).
The DC-DC Converter Efficiency can be estimated using Figure 4.3–Figure 4.5.
8. The EZRadioPRO peripheral is placed in Shutdown mode.
44
Rev. 1.0
Si1000/1/2/3/4/5
4200
4100
4000
3900
3800
3700
3600
3500
3400
3300
3200
3100
3000
2900
2800
2700
2600
2500
2400
2300
2200
2100
2000
1900
1800
1700
1600
1500
1400
1300
1200
1100
1000
900
F < 10 MHz
F > 10 MHz
Oneshot Bypassed
Oneshot Enabled
< 170 µA/MHz
200 µA/MHz
215 µA/MHz
240 µA/MHz
800
250 µA/MHz
700
600
500
400
300
200
300 µA/MHz
100
0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Frequency (MHz)
Figure 4.1. Active Mode Current (External CMOS Clock)
Rev. 1.0
45
Si1000/1/2/3/4/5
Supply Current vs. Frequency
4200
4100
4000
3900
3800
3700
3600
3500
3400
3300
3200
3100
3000
2900
2800
2700
2600
2500
2400
2300
2200
2100
2000
1900
1800
1700
1600
1500
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Frequency (MHz)
Figure 4.2. Idle Mode Current (External CMOS Clock)
46
Rev. 1.0
Si1000/1/2/3/4/5
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Load Current (mA)
Figure 4.3. Typical DC-DC Converter Efficiency (High Current, VDD/DC+ = 2 V
Rev. 1.0
47
Si1000/1/2/3/4/5
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Load current (mA)
Figure 4.4. Typical DC-DC Converter Efficiency (High Current, VDD/DC+ = 3 V)
48
Rev. 1.0
Si1000/1/2/3/4/5
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ꢋꢌꢍꢎꢏꢐꢏꢃꢂꢇꢏꢋ
ꢋꢌꢍꢎꢏꢐꢏꢃꢂꢆꢏꢋ
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ꢋꢌꢍꢎꢏꢐꢏꢃꢂꢄꢏꢋ
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ꢋꢌꢍꢎꢏꢐꢏꢁꢂꢊꢏꢋ
ꢁꢂꢀꢉꢏꢕꢖꢏꢗꢘꢙꢕꢚꢛꢜꢝ ꢏꢃꢄꢃꢁꢏ!"ꢚ#"$% ꢏꢓꢑ&ꢏꢐꢏꢁꢂꢃꢏ'()*
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ꢃꢂꢁꢁ
ꢃꢂꢄꢇ
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ꢄꢂꢄꢇ
ꢄꢂꢇꢁ
ꢄꢂꢈꢇ
ꢅꢂꢁꢁ
Load current (mA)
Figure 4.5. Typical DC-DC Converter Efficiency (Low Current, VDD/DC+ = 2 V)
Rev. 1.0
49
Si1000/1/2/3/4/5
ꢃꢁꢇꢁ
ꢁꢂꢀꢉꢏꢕꢖꢏꢗꢘꢙꢕꢚꢛꢜꢝ ꢏꢃꢄꢃꢁꢏ!"ꢚ#"$% ꢏꢓꢑ&ꢏꢐꢏꢁꢂꢃꢏ'()*
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ꢀꢁꢁ
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ꢄꢁꢁ
ꢑꢒꢑꢓꢔꢏꢐꢏꢃ ꢏꢏꢋ++,+-.ꢏꢐꢏꢃꢂꢊꢏꢋ ꢏꢔꢜ"ꢙꢏ-ꢕꢝꢝ%ꢘꢛꢏꢐꢏꢉꢁꢏꢕꢍ
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/0ꢘꢏ1ꢕ2*%ꢏꢒ0ꢙꢛ(7ꢏꢆꢁꢏꢘ*
/0ꢘꢏ1ꢕ2*%ꢏꢒ0ꢙꢛ(7ꢏꢉꢁꢏꢘ*
ꢁꢂꢊ
ꢃꢂꢁ
ꢃꢂꢃ
ꢃꢂꢄ
ꢃꢂꢅ
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ꢃꢂꢀ
ꢃꢂꢈ
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ꢋꢌꢍꢎꢏ3ꢋ5
Figure 4.6. Typical One-Cell Suspend Mode Current
50
Rev. 1.0
Si1000/1/2/3/4/5
Table 4.3. Port I/O DC Electrical Characteristics
VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified.
Parameters
Conditions
Min
Typ
Max
Units
Output High Voltage High Drive Strength, PnDRV.n = 1
IOH = –3 mA, Port I/O push-pull
V
V
V
– 0.7
– 0.1
—
—
—
—
DD
DD
IOH = –10 µA, Port I/O push-pull
IOH = –10 mA, Port I/O push-pull
See Chart
Low Drive Strength, PnDRV.n = 0
IOH = –1 mA, Port I/O push-pull
IOH = –10 µA, Port I/O push-pull
IOH = –3 mA, Port I/O push-pull
V
V
– 0.7
– 0.1
—
—
—
—
—
—
DD
DD
See Chart
Output Low Voltage High Drive Strength, PnDRV.n = 1
V
I
I
I
= 8.5 mA
= 10 µA
= 25 mA
—
—
—
—
—
0.6
0.1
—
OL
OL
OL
See Chart
Low Drive Strength, PnDRV.n = 0
I
I
I
= 1.4 mA
= 10 µA
= 4 mA
—
—
—
—
—
0.6
0.1
—
OL
OL
OL
See Chart
Input High Voltage
Input Low Voltage
V
V
V
V
= 2.0 to 3.6 V
= 0.9 to 2.0 V
= 2.0 to 3.6 V
= 0.9 to 2.0 V
V
– 0.6
DD
—
—
—
—
—
—
V
V
DD
DD
DD
DD
0.7 x VDD
—
—
0.6
V
0.3 x VDD
V
Input Leakage
Current
Weak Pullup On, V = 0 V, V = 1.8 V
—
—
4
20
—
30
µA
IN
DD
Weak Pullup On, Vin = 0 V, V = 3.6 V
DD
Rev. 1.0
51
Si1000/1/2/3/4/5
Typical VOH (High Drive Mode)
3.6
3.3
3
VDD = 3.6V
VDD = 3.0V
VDD = 2.4V
VDD = 1.8V
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0
5
10
15
20
25
30
35
40
45
50
Load Current (mA)
Typical VOH (Low Drive Mode)
3.6
3.3
3
VDD = 3.6V
VDD = 3.0V
VDD = 2.4V
VDD = 1.8V
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
Load Current (mA)
Figure 4.7. Typical VOH Curves, 1.8–3.6 V
52
Rev. 1.0
Si1000/1/2/3/4/5
Typical VOH (High Drive Mode)
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
VDD = 1.8V
VDD = 1.5V
VDD = 1.2V
VDD = 0.9V
0.9
0.8
0.7
0.6
0.5
0
1
2
3
4
5
6
7
8
9
10 11 12
Load Current (mA)
Typical VOH (Low Drive Mode)
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
VDD = 1.8V
VDD = 1.5V
VDD = 1.2V
VDD = 0.9V
0.9
0.8
0.7
0.6
0.5
0
1
2
3
Load Current (mA)
Figure 4.8. Typical VOH Curves, 0.9–1.8 V
Rev. 1.0
53
Si1000/1/2/3/4/5
Typical VOL (High Drive Mode)
1.8
1.5
1.2
0.9
0.6
0.3
0
VDD = 3.6V
VDD = 3.0V
VDD = 2.4V
VDD = 1.8V
-80
-70
-60
-50
-40
-30
-20
-10
0
Load Current (mA)
Typical VOL (Low Drive Mode)
1.8
1.5
1.2
0.9
0.6
0.3
0
VDD = 3.6V
VDD = 3.0V
VDD = 2.4V
VDD = 1.8V
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
Load Current (mA)
Figure 4.9. Typical VOL Curves, 1.8–3.6 V
54
Rev. 1.0
Si1000/1/2/3/4/5
Typical VOL (High Drive Mode)
1.8
1.5
1.2
0.9
0.6
0.3
0
VDD = 3.6V
VDD = 3.0V
VDD = 2.4V
VDD = 1.8V
-80
-70
-60
-50
-40
-30
-20
-10
0
Load Current (mA)
Typical VOL (Low Drive Mode)
1.8
1.5
1.2
0.9
0.6
0.3
0
VDD = 3.6V
VDD = 3.0V
VDD = 2.4V
VDD = 1.8V
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
Load Current (mA)
Figure 4.10. Typical VOL Curves, 1.8–3.6 V
Rev. 1.0
55
Si1000/1/2/3/4/5
Typical VOL (High Drive Mode)
0.5
0.4
0.3
0.2
0.1
VDD = 1.8V
VDD = 1.5V
VDD = 1.2V
VDD = 0.9V
0
-5
-4
-3
-2
-1
0
Load Current (mA)
Typical VOL (Low Drive Mode)
0.5
0.4
0.3
0.2
0.1
VDD = 1.8V
VDD = 1.5V
VDD = 1.2V
VDD = 0.9V
0
-3
-2
-1
0
Load Current (mA)
Figure 4.11. Typical VOL Curves, 0.9–1.8 V
56
Rev. 1.0
Si1000/1/2/3/4/5
Table 4.4. Reset Electrical Characteristics
VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified.
Parameter
Conditions
= 1.4 mA,
Min
Typ
—
Max
0.6
Units
V
RST Output Low Voltage
RST Input High Voltage
I
—
OL
V
V
V
V
= 2.0 to 3.6 V
= 0.9 to 2.0 V
= 2.0 to 3.6 V
= 0.9 to 2.0 V
V
– 0.6
—
—
V
DD
DD
DD
DD
DD
0.7 x V
—
—
—
V
DD
RST Input Low Voltage
—
0.6
V
—
—
0.3 x V
V
DD
RST Input Pullup Current
VDD_MCU Monitor
RST = 0.0 V, VDD = 1.8 V
RST = 0.0 V, VDD = 3.6 V
—
—
4
20
—
30
µA
Early Warning
Reset Trigger
1.8
1.7
1.85
1.75
1.9
1.8
V
Threshold (V
)
RST
(all power modes except Sleep)
V
On
Ramp Time for Power
V
Ramp from 0–0.9 V
DD
—
—
3
ms
V
DD
VDD Monitor Threshold
(V
Initial Power-On (V Rising)
Brownout Condition (V Falling)
Recovery from Brownout (V Rising)
—
0.7
—
0.75
0.8
0.95
—
0.9
—
DD
)
POR
DD
DD
Missing Clock Detector
Timeout
Time from last system clock rising edge
to reset initiation
100
650
1000
µs
Minimum System Clock w/ System clock frequency which triggers
—
7
10
kHz
Missing Clock Detector
Enabled
a missing clock detector timeout
Reset Time Delay
Delay between release of any reset
source and code
—
10
—
—
—
µs
µs
execution at location 0x0000
Minimum RST Low Time to
Generate a System Reset
15
V
V
Monitor Turn-on Time
—
—
300
7
—
—
ns
DD
Monitor Supply
µA
DD
Current
Rev. 1.0
57
Si1000/1/2/3/4/5
Table 4.5. Power Management Electrical Specifications
VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified.
Parameter
Conditions
Min
2
Typ
—
Max
3
Units
SYSCLKs
ns
Idle Mode Wake-up Time
Suspend Mode Wake-up Time
Low power oscillator
Precision oscillator
—
400
—
—
—
—
1.3
2
—
—
—
µs
µs
µs
Two-cell mode
One-cell mode
Sleep Mode Wake-up Time
10
Table 4.6. Flash Electrical Characteristics
VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified.
Parameter
Flash Size
Conditions
Si1000/2/4
Si1001/3/5
Min
Typ
Max
Units
bytes
bytes
bytes
65536*
32768
1024
1k
—
—
—
—
Scratchpad Size
Endurance
—
1024
—
30k
Erase/Write
Cycles
Erase Cycle Time
Write Cycle Time
28
57
32
64
36
71
ms
µs
Note: 1024 bytes at addresses 0xFC00 to 0xFFFF are reserved.
58
Rev. 1.0
Si1000/1/2/3/4/5
Table 4.7. Internal Precision Oscillator Electrical Characteristics
VDD = 1.8 to 3.6 V; TA = –40 to +85 °C unless otherwise specified; Using factory-calibrated settings.
Parameter
Conditions
Min
Typ
Max
Units
–40 to +85 °C,
Oscillator Frequency
24
24.5
25
MHz
V
= 1.8–3.6 V
DD
Oscillator Supply Current
25 °C; includes bias current
of 90–100 µA
—
300*
—
µA
(from V
)
DD
*Note: Does not include clock divider or clock tree supply current.
Table 4.8. Internal Low-Power Oscillator Electrical Characteristics
VDD = 1.8 to 3.6 V; TA = –40 to +85 °C unless otherwise specified; Using factory-calibrated settings.
Parameter
Conditions
Min
Typ
Max
Units
–40 to +85 °C,
Oscillator Frequency
18
20
22
MHz
V
= 1.8–3.6 V
DD
25 °C
Oscillator Supply Current
—
100*
—
µA
No separate bias current
required.
(from V
)
DD
*Note: Does not include clock divider or clock tree supply current.
Rev. 1.0
59
Si1000/1/2/3/4/5
Table 4.9. ADC0 Electrical Characteristics
V
= 1.8 to 3.6V V, VREF = 1.65 V (REFSL[1:0] = 11), –40 to +85 °C unless otherwise specified.
DD
Parameter
Conditions
Min
Typ
Max
Units
DC Accuracy
Resolution
10
bits
LSB
LSB
LSB
LSB
Integral Nonlinearity
Differential Nonlinearity
Offset Error
—
—
—
—
±0.5
±0.5
±<1
±1
±1
±1
Guaranteed Monotonic
±2
Full Scale Error
±2.5
Dynamic performance (10 kHz sine-wave single-ended input, 1 dB below Full Scale, 300 ksps)
Signal-to-Noise Plus Distortion
Signal-to-Distortion
54
—
—
58
73
75
—
—
—
dB
dB
dB
Spurious-Free Dynamic Range
Conversion Rate
SAR Conversion Clock
—
—
7.33
MHz
Conversion Time in SAR Clocks
10-bit Mode
8-bit Mode
13
11
—
—
—
—
clocks
Track/Hold Acquisition Time
Throughput Rate
1.5
—
—
—
—
us
300
ksps
Analog Inputs
ADC Input Voltage Range
Single Ended (AIN+ – GND)
Single Ended
0
0
—
—
VREF
V
V
Absolute Pin Voltage with respect
to GND
V
DD
Sampling Capacitance
1x Gain
0.5x Gain
—
—
30
28
—
pF
Input Multiplexer Impedance
Power Specifications
Power Supply Current
5
—
k
Conversion Mode (300 ksps)
Tracking Mode (0 ksps)
—
—
800
680
—
—
µA
dB
(V supplied to ADC0)
DD
Power Supply Rejection
Internal High Speed VREF
External VREF
—
—
67
74
—
—
60
Rev. 1.0
Si1000/1/2/3/4/5
Table 4.10. Temperature Sensor Electrical Characteristics
V
= 1.8 to 3.6V V, –40 to +85 °C unless otherwise specified.
DD
Parameter
Conditions
Min
Typ
Max
Units
Linearity
Slope
—
—
—
—
—
—
±1
3.40
40
—
—
—
—
—
°C
mV/°C
µV/°C
mV
1
1
Slope Error
Offset
Temp = 25 °C
Temp = 25 °C
1025
18
Offset Error
mV
Temperature Sensor Settling
Initial Voltage=0 V
Initial Voltage=3.6 V
—
3.0
6.5
µs
2
Time
Supply Current
—
35
—
µA
Notes:
1. Represents one standard deviation from the mean.
2. The temperature sensor settling time, resulting from an ADC mux change or enabling of the temperature
sensor, varies with the voltage of the previously sampled channel and can be up to 6.5 µs if the previously
sampled channel voltage was greater than 3 V. To minimize the temperature sensor settling time, the ADC
mux can be momentarily set to ground before being set to the temperature sensor output. This ensures that
the temperature sensor output will settle in 3 µs or less.
Table 4.11. Voltage Reference Electrical Characteristics
V
= 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified.
DD
Parameter
Conditions
Min
Typ
Max
Units
Internal High-Speed Reference (REFSL[1:0] = 11)
–40 to +85 °C,
= 1.8–3.6 V
Output Voltage
1.60
1.65
1.70
V
V
DD
VREF Turn-on Time
Supply Current
—
—
—
1.7
—
µs
200
µA
Internal Precision Reference (REFSL[1:0] = 00, REFOE = 1)
–40 to +85 °C,
= 1.8–3.6 V
Output Voltage
1.645
1.680
1.715
V
V
DD
VREF Short-Circuit Current
Load Regulation
—
—
—
3.5
400
15
—
—
—
mA
µV/µA
ms
Load = 0 to 200 µA to AGND
4.7 µF tantalum, 0.1 µF ceramic
bypass, settling to 0.5 LSB
0.1 µF ceramic bypass, settling to
0.5 LSB
VREF Turn-on Time 1
VREF Turn-on Time 2
—
300
—
µs
no bypass cap, settling to 0.5 LSB
VREF Turn-on Time 3
Supply Current
—
—
25
15
—
—
µs
µA
External Reference (REFSL[1:0] = 00, REFOE = 0)
Input Voltage Range
0
—
V
V
DD
Sample Rate = 300 ksps; VREF =
3.0 V
Input Current
—
5.25
—
µA
Rev. 1.0
61
Si1000/1/2/3/4/5
Table 4.12. IREF0 Electrical Characteristics
V
= 1.8 to 3.6 V, –40 to +85 °C, unless otherwise specified.
DD
Parameter
Conditions
Min
Typ
Max
Units
Static Performance
Resolution
6
—
bits
V
Output Compliance Range
Low Power Mode, Source
High Current Mode, Source
Low Power Mode, Sink
0
0
V
– 0.4
DD
—
V
– 0.8
V
DD
0.3
0.8
—
—
—
—
—
—
—
—
—
V
V
DD
DD
High Current Mode, Sink
—
V
V
Integral Nonlinearity
Differential Nonlinearity
Offset Error
<±0.2
<±0.2
<±0.1
—
±1.0
LSB
LSB
LSB
%
±1.0
±0.5
±5
Full Scale Error*
Low Power Mode, Source
High Current Mode, Source
Low Power Mode, Sink
—
±6
%
—
±8
%
High Current Mode, Sink
—
±8
%
Absolute Current Error
Low Power Mode
Sourcing 20 µA
<±1
±3
%
Dynamic Performance
Output Settling Time to 1/2 LSB
Startup Time
—
—
300
1
—
—
ns
µs
Power Consumption
Net Power Supply Current
Low Power Mode, Source
IREF0DAT = 000001
IREF0DAT = 111111
(V supplied to IREF0 minus
DD
—
—
10
10
—
—
µA
µA
any output source current)
High Current Mode, Source
IREF0DAT = 000001
IREF0DAT = 111111
—
—
10
10
—
—
µA
µA
Low Power Mode, Sink
IREF0DAT = 000001
IREF0DAT = 111111
—
—
1
—
—
µA
µA
11
High Current Mode, Sink
IREF0DAT = 000001
IREF0DAT = 111111
—
—
12
81
—
—
µA
µA
*Note: Full scale is 63 µA in low power mode and 504 µA in high power mode.
62
Rev. 1.0
Si1000/1/2/3/4/5
Table 4.13. Comparator Electrical Characteristics
VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise noted.
Parameter
Response Time:
Conditions
Min
—
Typ
130
200
210
410
420
1200
1750
6200
1.5
Max
—
—
—
—
—
—
—
—
4
Units
ns
CP0+ – CP0– = 100 mV
CP0+ – CP0– = –100 mV
CP0+ – CP0– = 100 mV
CP0+ – CP0– = –100 mV
CP0+ – CP0– = 100 mV
CP0+ – CP0– = –100 mV
CP0+ – CP0– = 100 mV
CP0+ – CP0– = –100 mV
*
*
*
*
Mode 0, V = 2.4 V, V
= 1.2 V
= 1.2 V
= 1.2 V
= 1.2 V
DD
CM
CM
CM
CM
—
ns
Response Time:
—
ns
Mode 1, V = 2.4 V, V
DD
—
ns
Response Time:
—
ns
Mode 2, V = 2.4 V, V
DD
—
ns
Response Time:
—
ns
Mode 3, V = 2.4 V, V
DD
—
ns
Common-Mode Rejection Ratio
—
mV/V
V
Inverting or Non-Inverting Input
Voltage Range
–0.25
—
V
+ 0.25
DD
Input Capacitance
Input Bias Current
Input Offset Voltage
Power Supply
—
—
–7
12
1
—
—
+7
pF
nA
—
mV
Power Supply Rejection
Power-up Time
—
—
—
—
—
—
—
—
—
0.1
0.6
1.0
1.8
10
—
—
—
—
—
—
—
—
—
mV/V
µs
VDD = 3.6 V
VDD = 3.0 V
VDD = 2.4 V
VDD = 1.8 V
Mode 0
µs
µs
µs
Supply Current at DC
23
µA
µA
µA
µA
Mode 1
8.8
2.6
0.4
Mode 2
Mode 3
Note: Vcm is the common-mode voltage on CP0+ and CP0–.
Rev. 1.0
63
Si1000/1/2/3/4/5
Table 4.13. Comparator Electrical Characteristics
VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise noted.
Parameter
Conditions
Min
Typ
Max
Units
Hysteresis
Mode 0
Hysteresis 1
Hysteresis 2
Hysteresis 3
Hysteresis 4
Mode 1
(CPnHYP/N1–0 = 00)
(CPnHYP/N1–0 = 01)
(CPnHYP/N1–0 = 10)
(CPnHYP/N1–0 = 11)
—
—
—
—
0
—
—
—
—
mV
mV
mV
mV
8.5
17
34
Hysteresis 1
Hysteresis 2
Hysteresis 3
Hysteresis 4
Mode 2
(CPnHYP/N1–0 = 00)
(CPnHYP/N1–0 = 01)
(CPnHYP/N1–0 = 10)
(CPnHYP/N1–0 = 11)
—
—
—
—
0
—
—
—
—
mV
mV
mV
mV
6.5
13
26
Hysteresis 1
Hysteresis 2
Hysteresis 3
Hysteresis 4
Mode 3
(CPnHYP/N1–0 = 00)
(CPnHYP/N1–0 = 01)
(CPnHYP/N1–0 = 10)
(CPnHYP/N1–0 = 11)
—
2
0
5
1
mV
mV
mV
mV
10
20
30
5
10
20
12
Hysteresis 1
Hysteresis 2
Hysteresis 3
Hysteresis 4
(CPnHYP/N1–0 = 00)
(CPnHYP/N1–0 = 01)
(CPnHYP/N1–0 = 10)
(CPnHYP/N1–0 = 11)
—
—
—
—
0
4.5
9
—
—
—
—
mV
mV
mV
mV
17
Note: Vcm is the common-mode voltage on CP0+ and CP0–.
64
Rev. 1.0
Si1000/1/2/3/4/5
Table 4.14. DC-DC Converter (DC0) Electrical Characteristics
VBAT = 0.9 to 1.8 V, –40 to +85 °C unless otherwise specified.
Parameter
Input Voltage Range
Input Inductor Value
Conditions
Min
0.9
Typ
—
Max
1.8
Units
V
500
680
900
nH
Input Inductor Current
Rating
250
—
—
—
—
mA
Inductor DC Resistance
Input Capacitor Value
Output Voltage Range
0.5
—
—
4.7
1.0
—
—
µF
Source Impedance < 2
Target Output = 1.8 V
Target Output = 1.9 V
Target Output = 2.0 V
Target Output = 2.1 V
Target Output = 2.1 V
Target Output = 2.7 V
Target Output = 3.0 V
Target Output = 3.3 V
Target Output = 2.0 V, 1 to 30 mA
Target Output = 3.0 V, 1 to 20 mA
Target Output = 1.8 V
Target Output = 1.9 V
Target Output = 2.0 V
Target Output = 2.1 V
Target Output = 2.4 V
Target Output = 2.7 V
Target Output = 3.0 V
Target Output = 3.3 V
1.73
1.83
1.93
2.03
2.30
2.60
2.90
3.18
—
1.80
1.90
2.00
2.10
2.40
2.70
3.00
3.30
±0.3
±1
1.87
1.97
2.07
2.17
2.50
2.80
3.10
3.42
—
V
V
V
V
V
V
V
V
Output Load Regulation
%
—
—
%
Output Current
(based on output power
spec)
—
—
36
mA
mA
mA
mA
mA
mA
mA
mA
mW
—
—
34
—
—
32
—
—
30
—
—
27
—
—
24
—
—
21
—
—
19
Output Power
—
—
65
from VBAT supply
from VDD/DC+ supply
—
—
80
100
—
—
Bias Current
µA
MHz
mA
Clocking Frequency
1.6
2.4
3.2
Maximum DC Load Current
During Startup
—
—
1
Capacitance Connected to
Output
0.8
1.0
2.0
µF
Table 4.15. VREG0 Electrical Characteristics
VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
Input Voltage Range
Bias Current
1.8
—
—
3.6
—
V
Normal, Idle, Suspend, or Stop Mode
20
µA
Rev. 1.0
65
Si1000/1/2/3/4/5
®
4.3. EZRadioPRO Electrical Characteristics
Table 4.16. DC Characteristics1
Parameter
Symbol
Conditions
Min Typ Max Units
Supply Voltage
Range
V
1.8 3.0
3.6
V
DD
Power Saving Modes I
RC Oscillator, Main Digital Regulator,
and Low Power Digital Regulator OFF
—
—
15
50
nA
nA
Shutdown
I
Low Power Digital Regulator ON (Register
values retained) and Main Digital
450 800
Standby
Regulator, and RC Oscillator OFF
I
RC Oscillator and Low Power Digital
Regulator ON
(Register values retained) and Main Digital
Regulator OFF
—
—
—
—
1
1
—
—
—
—
µA
µA
µA
µA
Sleep
I
Main Digital Regulator and Low Battery
Detector ON,
Sensor-
LBD
Crystal Oscillator and all other blocks
2
OFF
I
Main Digital Regulator and Temperature
Sensor ON,
1
Sensor-TS
Crystal Oscillator and all other blocks
2
OFF
I
Crystal Oscillator and Main Digital
Regulator ON,
800
Ready
all other blocks OFF. Crystal Oscillator
buffer disabled
TUNE Mode Current
RX Mode Current
I
Synthesizer and regulators enabled
—
—
—
8.5
18.5
85
—
—
—
mA
mA
mA
Tune
I
RX
TX Mode Current
—Si1000/1
I
I
txpow[2:0] = 111 (+20 dBm)
Using Silicon Labs’ Reference Design.
TX current consumption is dependent on
match and board layout.
TX_+20
TX Mode Current
—Si1002/3
txpow[2:0] = 110 (+13 dBm)
Using Silicon Labs’ Reference Design.
TX current consumption is dependent on
match and board layout.
—
—
30
17
—
—
mA
mA
TX_+13
I
txpow[2:0] = 010 (+1 dBm)
Using Silicon Labs’ Reference Design.
TX current consumption is dependent on
match and board layout.
TX_+1
Notes:
1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max
limits are listed in the "Production Test Conditions" section on page 73.
2. Guaranteed by qualification. Qualification test conditions are listed in the "Production Test Conditions"
section on page 73.
66
Rev. 1.0
Si1000/1/2/3/4/5
Table 4.17. Synthesizer AC Electrical Characteristics1
Parameter
Symbol
Conditions
Min
Typ
Max Units
Synthesizer Frequency
F
240
—
960
MHz
SYN
Range
Synthesizer Frequency
Resolution
F
Low Band, 240–480 MHz
High Band, 480–960 MHz
—
—
156.25
312.5
—
—
—
Hz
Hz
V
RES-LB
2
F
RES-HB
REF_LV
Reference Frequency
f
When using external reference
signal driving XOUT pin, instead
of using crystal. Measured peak-
0.7
1.6
2
Input Level
to-peak (V
)
PP
2
Synthesizer Settling Time
t
Measured from exiting Ready
mode with XOSC running to any
frequency.
—
—
200
2
—
4
µs
LOCK
Including VCO Calibration.
2
Residual FM
F
Integrated over 250 kHz band-
width (500 Hz lower bound of
integration)
kHz
RMS
RMS
2
Phase Noise
L(f )
F = 10 kHz
F = 100 kHz
F = 1 MHz
F = 10 MHz
—
—
—
—
–80
–90
—
—
—
—
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
M
–115
–130
Notes:
1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max
limits are listed in the "Production Test Conditions" section on page 73.
2. Guaranteed by qualification. Qualification test conditions are listed in the "Production Test Conditions" section
on page 73.
Rev. 1.0
67
Si1000/1/2/3/4/5
Table 4.18. Receiver AC Electrical Characteristics1
Parameter
Symbol
Conditions
Min
240
—
Typ
—
Max Units
RX Frequence Range
960
—
MHz
dBm
F
RX
2
(BER < 0.1%)
(2 kbps, GFSK, BT = 0.5,
f = 5 kHz)3
RX Sensitivity
–121
P
RX_2
(BER < 0.1%)
(40 kbps, GFSK, BT = 0.5,
f = 20 kHz)3
(BER < 0.1%)
(100 kbps, GFSK, BT = 0.5,
f = 50 kHz)3
(BER < 0.1%)
(125 kbps, GFSK, BT = 0.5,
f = 62.5 kHz)
—
—
—
–108
–104
–101
—
—
—
dBm
dBm
dBm
P
RX_40
P
P
RX_100
RX_125
(BER < 0.1%)
—
—
–110
–102
—
—
dBm
dBm
P
RX_OOK
(4.8 kbps, 350 kHz BW, OOK)3
(BER < 0.1%)
(40 kbps, 400 kHz BW, OOK)3
3
RX Channel Bandwidth
2.6
—
—
0
620
0.1
kHz
BW
Up to +5 dBm Input Level
BER Variation vs Power
ppm
P
RX_RES
3
Level
3
915 MHz
868 MHz
433 MHz
315 MHz
LNA Input Impedance
—
—
—
—
—
—
—
—
51–60j
54–63j
89–110j
107–137j
±0.5
—
—
—
—
—
—
—
—
R
IN-RX
(Unmatched—measured
differentially across RX
input pins)
RSSI Resolution
dB
dB
dB
dB
RES
RSSI
1-CH
2-CH
3-CH
3
Desired Ref Signal 3 dB above
sensitivity, BER < 0.1%. Interferer
and desired modulated with
40 kbps F = 20 kHz GFSK with BT
= 0.5, channel spacing = 150 kHz
1-Ch Offset Selectivity
–31
C/I
C/I
C/I
3
2-Ch Offset Selectivity
–35
3
3-Ch Offset Selectivity
–40
3
Desired Ref Signal 3 dB above
sensitivity. Interferer and desired
modulated with 40 kbps F =
20 kHz GFSK with BT = 0.5
Blocking at 1 MHz Offset
Blocking at 4 MHz Offset
Blocking at 8 MHz Offset
—
—
—
—
–52
–56
–63
–30
—
—
—
—
dB
dB
dB
dB
1M
4M
8M
BLOCK
BLOCK
BLOCK
3
3
3
Rejection at the image frequency.
IF=937 kHz
Image Rejection
Im
REJ
3
Measured at RX pins
Spurious Emissions
—
—
–54
dBm
P
OB_RX1
Notes:
1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max
limits are listed in the "Production Test Conditions" section on page 73.
2. Receive sensitivity at multiples of 30 MHz may be degraded. If channels with a multiple of 30 MHz are required
it is recommended to shift the crystal frequency. Contact Silicon Labs Applications Support for
recommendations.
3. Guaranteed by qualification. Qualification test conditions are listed in the "Production Test Conditions" section
on page 73.
68
Rev. 1.0
Si1000/1/2/3/4/5
Table 4.19. Transmitter AC Electrical Characteristics1
Parameter
Symbol
Conditions
Min
240
Typ
—
Max Units
TX Frequency Range
F
960
256
40
MHz
kbps
kbps
kHz
TX
2
FSK Data Rate
DR
0.123
0.123
±0.625
±0.625
—
—
FSK
2
OOK Data Rate
DR
—
OOK
Modulation Deviation
Δf1
Δf2
Δf
860–960 MHz
240–860 MHz
±320
±160
—
kHz
Modulation Deviation
0.625
—
kHz
RES
2
Resolution
Output Power Range—
P
P
+1
–4
+20
+13
dBm
dBm
TX
TX
3
Si1000/1
Output Power Range—
—
3
Si1002/3
2
TX RF Output Steps
P
P
controlled by txpow[2:0]
—
—
3
2
—
—
dB
dB
RF_OUT
2
TX RF Output Level
–40 to +85 C
RF_TEMP
Variation vs. Temperature
TX RF Output Level
Variation vs. Frequency
P
Measured across any one
frequency band
—
—
1
—
—
dB
RF_FREQ
2
Transmit Modulation
B*T
Gaussian Filtering Bandwith
0.5
2
Filtering
Time
Product
2
Spurious Emissions
P
P
P
= 11 dBm,
OUT
Frequencies <1 GHz
—
—
—
—
–54
–54
dBm
dBm
OB-TX1
OB-TX2
1–12.75 GHz, excluding
harmonics
2
Harmonics
P
P
Using reference design TX
matching network and filter
with max output power. Har-
monics reduce linearly with
output power.
—
—
—
—
–42
–42
dBm
dBm
2HARM
3HARM
Notes:
1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max
limits are listed in the "Production Test Conditions" section on page 73.
2. Guaranteed by qualification. Qualification test conditions are listed in the "Production Test Conditions" section
on page 73.
3. Output power is dependent on matching components, board layout, and is measured at the pin.
Rev. 1.0
69
Si1000/1/2/3/4/5
Table 4.20. Auxiliary Block Specifications1
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Temperature Sensor
Accuracy
TS
After calibrated via sen-
sor offset register
tvoffs[7:0]
—
0.5
—
°C
A
2
Temperature Sensor
Sensitivity
TS
—
—
5
50
250
—
—
—
mV/°C
mV
S
2
Low Battery Detector
LBD
RES
2
Resolution
Low Battery Detector
LBD
—
—
µs
CT
2
Conversion Time
Microcontroller Clock
Output Frequency
F
Configurable to
30 MHz, 15 MHz,
10 MHz, 4 MHz, 3 MHz,
2 MHz, 1 MHz, or
32.768 kHz
32.768K
30M
Hz
MC
General Purpose ADC
Resolution
ADC
ADC
—
—
—
8
4
—
—
—
bit
mV/bit
µs
ENB
RES
2
General Purpose ADC Bit
2
Resolution
Temp Sensor & General
Purpose ADC Conversion
ADC
305
CT
2
Time
30 MHz XTAL Start-Up time
t
Using XTAL and board
layout in reference
design. Start-up time
will vary with XTAL type
and board layout.
—
—
600
97
—
—
µs
fF
30M
30 MHz XTAL Cap
30M
See “Crystal Oscillator”
on page 260 for total
load capacitance
calculation
RES
2
Resolution
2
32 kHz XTAL Start-Up Time
t
—
—
6
—
—
sec
32k
32 kHz Accuracy using
32KRC
1000
ppm
RES
2
Internal RC Oscillator
32 kHz RC Oscillator Start-
Up
t
—
500
—
µs
32kRC
POR Reset Time
t
—
—
16
—
—
ms
µs
POR
2
Software Reset Time
t
250
soft
Notes:
1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max
limits are listed in the "Production Test Conditions" section on page 73.
2. Guaranteed by qualification. Qualification test conditions are listed in the "Production Test Conditions" section
on page 73.
70
Rev. 1.0
Si1000/1/2/3/4/5
Table 4.21. Digital IO Specifications (nIRQ)
Parameter
Rise Time
Symbol
Conditions
Min
—
Typ
—
Max Units
T
T
0.1 x V to 0.9 x V , C = 5 pF
8
8
ns
ns
pF
V
RISE
FALL
DD
DD
L
Fall Time
0.9 x V to 0.1 x V
C = 5 pF
—
—
DD
DD,
L
Input Capacitance
C
V
—
—
1
IN
Logic High Level Input
Voltage
V
V
– 0.6
—
—
IH
DD
Logic Low Level Input
Voltage
V
—
0.6
V
IL
Input Current
I
0<V < V
–100
– 0.6
DD
—
—
100
—
nA
V
IN
IN
DD
Logic High Level
V
I
<1 mA source, V =1.8 V
OH
OH
DD
Output Voltage
Logic Low Level
V
I
<1 mA sink, V =1.8 V
—
—
0.6
V
OL
OL
DD
Output Voltage
Note: All specifications guaranteed by qualification. Qualification test conditions are listed in the "Production Test
Conditions" section on page 73.
Table 4.22. GPIO Specifications (GPIO_0, GPIO_1, and GPIO_2)
Parameter
Rise Time
Symbol
Conditions
0.1 x V to 0.9 x V ,
DD
Min
Typ
Max
Units
T
—
—
8
ns
RISE
DD
C = 10 pF, DRV<1:0>=HH
L
Fall Time
T
0.9 x V to 0.1 x V
—
—
—
8
1
ns
FALL
DD
DD,
C = 10 pF, DRV<1:0>=HH
L
Input Capacitance
C
V
—
—
pF
V
IN
Logic High Level Input
Voltage
V
– 0.6
DD
IH
Logic Low Level Input
Voltage
V
—
—
0.6
V
IL
Input Current
I
0<V < V
DD
–100
5
—
—
100
25
nA
µA
IN
IN
Input Current If Pullup is
Activated
I
V =0 V
INP
IL
Maximum Output Current
I
DRV<1:0>=LL
DRV<1:0>=LH
DRV<1:0>=HL
DRV<1:0>=HH
0.1
0.9
1.5
1.8
0.5
2.3
3.1
3.6
—
0.8
3.5
4.8
5.4
—
mA
mA
mA
mA
V
OmaxLL
OmaxLH
OmaxHL
OmaxHH
I
I
I
Logic High Level Output
Voltage
V
I
< I
source,
V
– 0.6
DD
OH
OH Omax
V
=1.8 V
DD
Logic Low Level Output
Voltage
V
I
< I sink,
—
—
0.6
V
OL
OL Omax
V
=1.8 V
DD
Note: All specifications guaranteed by qualification. Qualification test conditions are listed in the "Production Test
Conditions" section on page 73.
Rev. 1.0
71
Si1000/1/2/3/4/5
Table 4.23. Absolute Maximum Ratings
Parameter
Value
Unit
V
V
to GND
–0.3, +3.6
–0.3, +8.0
–0.3, +6.5
DD
Instantaneous V
to GND on TX Output Pin
V
RF-peak
Sustained V
to GND on TX Output Pin
V
RF-peak
Voltage on Digital Control Inputs
Voltage on Analog Inputs
–0.3, V + 0.3
V
DD
–0.3, V + 0.3
V
DD
RX Input Power
+10
–40 to +85
30
dBm
C
C/W
C
C
Operating Ambient Temperature Range T
A
Thermal Impedance
JA
Junction Temperature T
+125
J
Storage Temperature Range T
–55 to +125
STG
Note: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. These are stress ratings only and functional operation of the device at or beyond these ratings in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Power Amplifier may be damaged if switched on without proper
load or termination connected. TX matching network design will influence TX VRF-peak on TX output pin.
Caution: ESD sensitive device.
72
Rev. 1.0
Si1000/1/2/3/4/5
4.4. Definition of Test Conditions for the EZRadioPRO Peripheral
Production Test Conditions:
T = +25 °C
A
V
= +3.3 VDC
DD
Sensitivity measured at 919 MHz
TX output power measured at 915 MHz
External reference signal (XOUT) = 1.0 V at 30 MHz, centered around 0.8 VDC
PP
Production test schematic (unless noted otherwise)
All RF input and output levels referred to the pins of the Si100x (not the RF module)
Qualification Test Conditions:
T = –40 to +85 °C
A
V
= +1.8 to +3.6 VDC
DD
Using 4432, 4431, or 4430 DKDB1 reference design or production test schematic
All RF input and output levels referred to the pins of the Si100x (not the RF module)
Rev. 1.0
73
Si1000/1/2/3/4/5
5. 10-Bit SAR ADC with 16-bit Auto-Averaging Accumulator and
Autonomous Low Power Burst Mode
The ADC0 on the Si1000/1/2/3/4/5 is a 300 ksps, 10-bit successive-approximation-register (SAR) ADC
with integrated track-and-hold and programmable window detector. ADC0 also has an autonomous low
power Burst Mode which can automatically enable ADC0, capture and accumulate samples, then place
ADC0 in a low power shutdown mode without CPU intervention. It also has a 16-bit accumulator that can
automatically oversample and average the ADC results.
The ADC is fully configurable under software control via Special Function Registers. The ADC0 operates in
Single-ended mode and may be configured to measure various different signals using the analog multi-
plexer described in “5.5. ADC0 Analog Multiplexer” on page 90. The voltage reference for the ADC is
selected as described in “5.7. Voltage and Ground Reference Options” on page 95.
ADC0CN
VDD
000
001
010
011
100
AD0BUSY (W)
Timer 0 Overflow
Timer 2 Overflow
Timer 3 Overflow
CNVSTR Input
Start
Conversion
ADC0TK
Burst Mode Logic
ADC0PWR
10-bit
SAR
AIN+
From
AMUX0
16-Bit Accumulator
ADC
AD0WINT
Window
Compare
Logic
32
ADC0LTH ADC0LTL
ADC0GTH ADC0GTL
ADC0CF
Figure 5.1. ADC0 Functional Block Diagram
5.1. Output Code Formatting
The registers ADC0H and ADC0L contain the high and low bytes of the output conversion code from the
ADC at the completion of each conversion. Data can be right-justified or left-justified, depending on the
setting of the AD0SJST[2:0]. When the repeat count is set to 1, conversion codes are represented as 10-
bit unsigned integers. Inputs are measured from 0 to VREF x 1023/1024. Example codes are shown below
for both right-justified and left-justified data. Unused bits in the ADC0H and ADC0L registers are set to 0.
74
Rev. 1.0
Si1000/1/2/3/4/5
Input Voltage
Right-Justified ADC0H:ADC0L
(AD0SJST = 000)
Left-Justified ADC0H:ADC0L
(AD0SJST = 100)
VREF x 1023/1024
VREF x 512/1024
VREF x 256/1024
0
0x03FF
0x0200
0x0100
0x0000
0xFFC0
0x8000
0x4000
0x0000
When the repeat count is greater than 1, the output conversion code represents the accumulated result of
the conversions performed and is updated after the last conversion in the series is finished. Sets of 4, 8,
16, 32, or 64 consecutive samples can be accumulated and represented in unsigned integer format. The
repeat count can be selected using the AD0RPT bits in the ADC0AC register. When a repeat count higher
than 1, the ADC output must be right-justified (AD0SJST = 0xx); unused bits in the ADC0H and ADC0L
registers are set to 0. The example below shows the right-justified result for various input voltages and
n
repeat counts. Notice that accumulating 2 samples is equivalent to left-shifting by n bit positions when all
samples returned from the ADC have the same value.
Input Voltage
Repeat Count = 4
Repeat Count = 16
Repeat Count = 64
V
V
V
0
x 1023/1024 0x0FFC
0x3FF0
0x2000
0x1FF0
0x0000
0xFFC0
0x8000
0x7FC0
0x0000
REF
REF
REF
x 512/1024
x 511/1024
0x0800
0x07FC
0x0000
The AD0SJST bits can be used to format the contents of the 16-bit accumulator. The accumulated result
can be shifted right by 1, 2, or 3 bit positions. Based on the principles of oversampling and averaging, the
effective ADC resolution increases by 1 bit each time the oversampling rate is increased by a factor of 4.
The example below shows how to increase the effective ADC resolution by 1, 2, and 3 bits to obtain an
effective ADC resolution of 11-bit, 12-bit, or 13-bit respectively without CPU intervention.
Input Voltage
Repeat Count = 4
Shift Right = 1
11-Bit Result
Repeat Count = 16
Shift Right = 2
12-Bit Result
Repeat Count = 64
Shift Right = 3
13-Bit Result
V
V
V
0
x 1023/1024 0x07F7
0x0FFC
0x0800
0x04FC
0x0000
0x1FF8
0x1000
0x0FF8
0x0000
REF
REF
REF
x 512/1024
x 511/1024
0x0400
0x03FE
0x0000
Rev. 1.0
75
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5.2. Modes of Operation
ADC0 has a maximum conversion speed of 300 ksps. The ADC0 conversion clock (SARCLK) is a divided
version of the system clock when Burst Mode is disabled (BURSTEN = 0), or a divided version of the low
power oscillator when Burst Mode is enabled (BURSEN = 1). The clock divide value is determined by the
AD0SC bits in the ADC0CF register.
5.2.1. Starting a Conversion
A conversion can be initiated in one of five ways, depending on the programmed states of the ADC0 Start
of Conversion Mode bits (AD0CM2–0) in register ADC0CN. Conversions may be initiated by one of the fol-
lowing:
1. Writing a 1 to the AD0BUSY bit of register ADC0CN
2. A Timer 0 overflow (i.e., timed continuous conversions)
3. A Timer 2 overflow
4. A Timer 3 overflow
5. A rising edge on the CNVSTR input signal (pin P0.6)
Writing a 1 to AD0BUSY provides software control of ADC0 whereby conversions are performed "on-
demand". During conversion, the AD0BUSY bit is set to logic 1 and reset to logic 0 when the conversion is
complete. The falling edge of AD0BUSY triggers an interrupt (when enabled) and sets the ADC0 interrupt
flag (AD0INT). Note: When polling for ADC conversion completions, the ADC0 interrupt flag (AD0INT)
should be used. Converted data is available in the ADC0 data registers, ADC0H:ADC0L, when bit AD0INT
is logic 1. Note that when Timer 2 or Timer 3 overflows are used as the conversion source, Low Byte over-
flows are used if Timer 2/3 is in 8-bit mode; High byte overflows are used if Timer 2/3 is in 16-bit mode.
See “27. Timers” on page 330 for timer configuration.
Important Note About Using CNVSTR: The CNVSTR input pin also functions as Port pin P0.6. When the
CNVSTR input is used as the ADC0 conversion source, Port pin P0.6 should be skipped by the Digital
Crossbar. To configure the Crossbar to skip P0.6, set to 1 Bit 6 in register P0SKIP. See “21. Port Input/Out-
put” on page 207 for details on Port I/O configuration.
Important Note: When operating the device in one-cell mode, there is an option available to automatically
synchronize the start of conversion with the quietest portion of the dc-dc converter switching cycle. Activat-
ing this option may help to reduce interference from internal or external power supply noise generated by
the dc-dc converter. Asserting this bit will hold off the start of an ADC conversion initiated by any of the
methods described above until the ADC receives a synchronizing signal from the dc-dc converter. The
delay in initiation of the conversion can be as much as one cycle of the dc-dc converter clock, which is
625 ns at the minimum dc-dc clock frequency of 1.6 MHz. For rev C and later C8051F93x-92x devices, the
synchronization feature also causes the dc-dc converter clock to be used as the ADC0 conversion clock.
The maximum conversion rate will be limited to approximately 170 ksps at the maximum dc-dc converter
clock rate of 3.2 MHz. In this mode, the ADC0 SAR Conversion Clock Divider must be set to 1 by setting
AD0SC[4:0] = 00000b in SFR register ADC0CF. To provide additional flexibility in minimizing noise, the
ADC0 conversion clock provided by the dc-dc converter can be inverted by setting the AD0CKINV bit in the
DC0CF register. For additional information on the synchronization feature, see the description of the SYNC
bit in “SFR Definition 16.1. DC0CN: DC-DC Converter Control” on page 171 and the description of the
AD0CKINV bit in “SFR Definition 16.2. DC0CF: DC-DC Converter Configuration” on page 172. This bit
must be set to 0 in two-cell mode for the ADC to operate.
76
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5.2.2. Tracking Modes
Each ADC0 conversion must be preceded by a minimum tracking time in order for the converted result to
be accurate. The minimum tracking time is given in Table 4.9. The AD0TM bit in register ADC0CN controls
the ADC0 track-and-hold mode. In its default state when Burst Mode is disabled, the ADC0 input is contin-
uously tracked, except when a conversion is in progress. When the AD0TM bit is logic 1, ADC0 operates in
low-power track-and-hold mode. In this mode, each conversion is preceded by a tracking period of 3 SAR
clocks (after the start-of-conversion signal). When the CNVSTR signal is used to initiate conversions in
low-power tracking mode, ADC0 tracks only when CNVSTR is low; conversion begins on the rising edge of
CNVSTR (see Figure 5.2). Tracking can also be disabled (shutdown) when the device is in low power
standby or sleep modes. Low-power track-and-hold mode is also useful when AMUX settings are fre-
quently changed, due to the settling time requirements described in “5.2.4. Settling Time Requirements” on
page 79.
A. ADC0 Timing for External Trigger Source
CNVSTR
(AD0CM[2:0]=100)
1
2 3 4 5 6 7 8 9 10 11 12 13 14
SAR Clocks
AD0TM=1
Low Power
or Convert
Low Power
Mode
Track
Convert
Convert
AD0TM=0
Track or Convert
Track
B. ADC0 Timing for Internal Trigger Source
Write '1' to AD0BUSY,
Timer 0, Timer 2,
Timer 1, Timer 3 Overflow
(AD0CM[2:0]=000, 001,010
011, 101)
1
1
2
3
4
4
5
5
6
6
7
7
8
8
9 10 11 12 13 14 15 16 17
SAR
Clocks
Low Power
or Convert
Track
Convert
Low Power Mode
AD0TM=1
2
3
9 10 11 12 13 14
SAR
Clocks
Track or
Convert
Convert
Track
AD0TM=0
Figure 5.2. 10-Bit ADC Track and Conversion Example Timing (BURSTEN = 0)
Rev. 1.0
77
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5.2.3. Burst Mode
Burst Mode is a power saving feature that allows ADC0 to remain in a low power state between conver-
sions. When Burst Mode is enabled, ADC0 wakes from a low power state, accumulates 1, 4, 8, 16, 32, or
64 using an internal Burst Mode clock (approximately 20 MHz), then re-enters a low power state. Since the
Burst Mode clock is independent of the system clock, ADC0 can perform multiple conversions then enter a
low power state within a single system clock cycle, even if the system clock is slow (e.g. 32.768 kHz), or
suspended.
Burst Mode is enabled by setting BURSTEN to logic 1. When in Burst Mode, AD0EN controls the ADC0
idle power state (i.e., the state ADC0 enters when not tracking or performing conversions). If AD0EN is set
to logic 0, ADC0 is powered down after each burst. If AD0EN is set to logic 1, ADC0 remains enabled after
each burst. On each convert start signal, ADC0 is awakened from its Idle Power State. If ADC0 is powered
down, it will automatically power up and wait the programmable Power-Up Time controlled by the
AD0PWR bits. Otherwise, ADC0 will start tracking and converting immediately. Figure 5.3 shows an exam-
ple of Burst Mode Operation with a slow system clock and a repeat count of 4.
When Burst Mode is enabled, a single convert start will initiate a number of conversions equal to the repeat
count. When Burst Mode is disabled, a convert start is required to initiate each conversion. In both modes,
the ADC0 End of Conversion Interrupt Flag (AD0INT) will be set after “repeat count” conversions have
been accumulated. Similarly, the Window Comparator will not compare the result to the greater-than and
less-than registers until “repeat count” conversions have been accumulated.
In Burst Mode, tracking is determined by the settings in AD0PWR and AD0TK. The default settings for
these registers will work in most applications without modification; however, settling time requirements may
need adjustment in some applications. Refer to “5.2.4. Settling Time Requirements” on page 79 for more
details.
Notes:
Setting AD0TM to 1 will insert an additional 3 SAR clocks of tracking before each conversion,
regardless of the settings of AD0PWR and AD0TK.
When using Burst Mode, care must be taken to issue a convert start signal no faster than once every
four SYSCLK periods. This includes external convert start signals.
System Clock
Convert Start
AD0TM = 1
AD0EN = 0
Powered
Down
Power-Up
and Track
T
3
T
3
T
3
T
3
Powered
Down
Power-Up
and Track
C
T
C
T
C
T
C
T
T
C..
C..
AD0TM = 0
AD0EN = 0
Powered
Down
Power-Up
and Track
Powered
Down
Power-Up
and Track
C
T
C
T
C
T
C
AD0PW R
AD0TK
T = Tracking set by AD0TK
T3 = Tracking set by AD0TM (3 SAR clocks)
C = Converting
Figure 5.3. Burst Mode Tracking Example with Repeat Count Set to 4
78
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5.2.4. Settling Time Requirements
A minimum amount of tracking time is required before each conversion can be performed, to allow the
sampling capacitor voltage to settle. This tracking time is determined by the AMUX0 resistance, the ADC0
sampling capacitance, any external source resistance, and the accuracy required for the conversion. Note
that in low-power tracking mode, three SAR clocks are used for tracking at the start of every conversion.
For many applications, these three SAR clocks will meet the minimum tracking time requirements, and
higher values for the external source impedance will increase the required tracking time.
Figure 5.4 shows the equivalent ADC0 input circuit. The required ADC0 settling time for a given settling
accuracy (SA) may be approximated by Equation 5.1. When measuring the Temperature Sensor output or
V
with respect to GND, R
reduces to R
. See Table 4.9 for ADC0 minimum settling time require-
DD
TOTAL
MUX
ments as well as the mux impedance and sampling capacitor values.
2n
SA
------
t = ln
RTOTALCSAMPLE
Equation 5.1. ADC0 Settling Time Requirements
Where:
SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB)
t is the required settling time in seconds
R
is the sum of the AMUX0 resistance and any external source resistance.
TOTAL
n is the ADC resolution in bits (10).
MUX Select
P0.x
RMUX
CSAMPLE
RCInput= RMUX * CSAMPLE
Note: The value of CSAMPLE depends on the PGA Gain. See Table 4.9 for details.
Figure 5.4. ADC0 Equivalent Input Circuits
Rev. 1.0
79
Si1000/1/2/3/4/5
5.2.5. Gain Setting
The ADC has gain settings of 1x and 0.5x. In 1x mode, the full scale reading of the ADC is determined
directly by V . In 0.5x mode, the full-scale reading of the ADC occurs when the input voltage is V
x 2.
REF
REF
The 0.5x gain setting can be useful to obtain a higher input Voltage range when using a small V
volt-
REF
age, or to measure input voltages that are between V
trolled by the AMP0GN bit in register ADC0CF.
and V . Gain settings for the ADC are con-
DD
REF
5.3. 8-Bit Mode
Setting the ADC08BE bit in register ADC0CF to 1 will put the ADC in 8-bit mode.In 8-bit mode, only the
8 MSBs of data are converted, allowing the conversion to be completed in two fewer SAR clock cycles
than a 10-bit conversion. This can result in an overall lower power consumption since the system can
spend more time in a low power mode. The two LSBs of a conversion are always 00 in this mode, and the
ADC0L register will always read back 0x00.
80
Rev. 1.0
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SFR Definition 5.1. ADC0CN: ADC0 Control
Bit
7
6
5
4
3
2
1
0
AD0EN BURSTEN AD0INT AD0BUSY AD0WINT
ADC0CM
Name
Type
Reset
R/W
0
R/W
0
R/W
0
W
0
R/W
0
R/W
0
0
0
SFR Page = 0x0; SFR Address = 0xE8; bit-addressable;
Bit
Name
Function
7
AD0EN
ADC0 Enable.
0: ADC0 Disabled (low-power shutdown).
1: ADC0 Enabled (active and ready for data conversions).
6
5
BURSTEN ADC0 Burst Mode Enable.
0: ADC0 Burst Mode Disabled.
1: ADC0 Burst Mode Enabled.
AD0INT
ADC0 Conversion Complete Interrupt Flag.
Set by hardware upon completion of a data conversion (BURSTEN=0), or a burst
of conversions (BURSTEN=1). Can trigger an interrupt. Must be cleared by soft-
ware.
4
3
AD0BUSY
AD0WINT
ADC0 Busy.
Writing 1 to this bit initiates an ADC conversion when ADC0CM[2:0] = 000.
ADC0 Window Compare Interrupt Flag.
Set by hardware when the contents of ADC0H:ADC0L fall within the window speci-
fied by ADC0GTH:ADC0GTL and ADC0LTH:ADC0LTL. Can trigger an interrupt.
Must be cleared by software.
2:0 ADC0CM[2:0] ADC0 Start of Conversion Mode Select.
Specifies the ADC0 start of conversion source.
000: ADC0 conversion initiated on write of 1 to AD0BUSY.
001: ADC0 conversion initiated on overflow of Timer 0.
010: ADC0 conversion initiated on overflow of Timer 2.
011: ADC0 conversion initiated on overflow of Timer 3.
1xx: ADC0 conversion initiated on rising edge of CNVSTR.
Rev. 1.0
81
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SFR Definition 5.2. ADC0CF: ADC0 Configuration
Bit
7
6
5
4
3
2
1
0
AD0SC[4:0]
AD08BE
AD0TM
AMP0GN
Name
Type
Reset
R/W
1
R/W
0
R/W
0
R/W
0
1
1
1
1
SFR Page = 0x0; SFR Address = 0xBC
Bit Name
Function
7:3 AD0SC[4:0] ADC0 SAR Conversion Clock Divider.
SAR Conversion clock is derived from FCLK by the following equation, where
AD0SC refers to the 5-bit value held in bits AD0SC[4:0]. SAR Conversion clock
requirements are given in Table 4.9.
BURSTEN = 0: FCLK is the current system clock.
BURSTEN = 1: FCLK is the 20 MHz low power oscillator, independent of the system
clock.
FCLK
AD0SC = ------------------- – 1 *
CLKSAR
*Round the result up.
or
FCLK
CLKSAR = ----------------------------
AD0SC + 1
2
1
AD08BE
AD0TM
ADC0 8-Bit Mode Enable.
0: ADC0 operates in 10-bit mode (normal operation).
1: ADC0 operates in 8-bit mode.
ADC0 Track Mode.
Selects between Normal or Delayed Tracking Modes.
0: Normal Track Mode: When ADC0 is enabled, conversion begins immediately fol-
lowing the start-of-conversion signal.
1: Delayed Track Mode: When ADC0 is enabled, conversion begins 3 SAR clock
cycles following the start-of-conversion signal. The ADC is allowed to track during
this time.
0
AMP0GN ADC0 Gain Control.
0: The on-chip PGA gain is 0.5.
1: The on-chip PGA gain is 1.
82
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SFR Definition 5.3. ADC0AC: ADC0 Accumulator Configuration
Bit
7
6
5
4
3
2
1
0
Reserved
AD0AE
AD0SJST
AD0RPT
Name
Type
Reset
R/W
0
W
0
R/W
0
R/W
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xBA
Bit
Name
Function
7
6
Reserved
AD0AE
Read = 0b.
ADC0 Accumulate Enable.
Enables multiple conversions to be accumulated when burst mode is disabled.
0: ADC0H:ADC0L contain the result of the latest conversion when Burst Mode is
disabled.
1: ADC0H:ADC0L contain the accumulated conversion results when Burst Mode
is disabled. Software must write 0x0000 to ADC0H:ADC0L to clear the accumu-
lated result.
This bit is write-only. Always reads 0b.
5:3
AD0SJST[2:0]
ADC0 Accumulator Shift and Justify.
Specifies the format of data read from ADC0H:ADC0L.
000: Right justified. No shifting applied.
001: Right justified. Shifted right by 1 bit.
010: Right justified. Shifted right by 2 bits.
011: Right justified. Shifted right by 3 bits.
100: Left justified. No shifting applied.
All remaining bit combinations are reserved.
2:0
AD0RPT[2:0]
ADC0 Repeat Count.
Selects the number of conversions to perform and accumulate in Burst Mode.
This bit field must be set to 000 if Burst Mode is disabled.
000: Perform and Accumulate 1 conversion.
001: Perform and Accumulate 4 conversions.
010: Perform and Accumulate 8 conversions.
011: Perform and Accumulate 16 conversions.
100: Perform and Accumulate 32 conversions.
101: Perform and Accumulate 64 conversions.
All remaining bit combinations are reserved.
Rev. 1.0
83
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SFR Definition 5.4. ADC0PWR: ADC0 Burst Mode Power-Up Time
Bit
7
6
5
4
3
2
1
0
Reserved
AD0PWR[3:0]
R/W
Name
Type
Reset
R
0
R
0
R
0
R
0
1
1
1
1
SFR Page = 0xF; SFR Address = 0xBA
Bit
Name
Function
7
Reserved
Unused
Read = 0b; Must write 0b.
Read = 0000b; Write = Don’t Care.
6:4
3:0 AD0PWR[3:0]
ADC0 Burst Mode Power-Up Time.
Sets the time delay required for ADC0 to power up from a low power state.
For BURSTEN = 0:
ADC0 power state controlled by AD0EN.
For BURSTEN = 1 and AD0EN = 1:
ADC0 remains enabled and does not enter a low power state after all conver-
sions are complete.
Conversions can begin immediately following the start-of-conversion signal.
For BURSTEN = 1 and AD0EN = 0:
ADC0 enters a low power state (as specified in Table 5.1) after all conversions
are complete.
Conversions can begin a programmed delay after the start-of-conversion sig-
nal.
The ADC0 Burst Mode Power-Up time is programmed according to the follow-
ing equation:
Tstartup
AD0PWR = ---------------------- – 1
400ns
or
Tstartup = AD0PWR + 1400ns
84
Rev. 1.0
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SFR Definition 5.5. ADC0TK: ADC0 Burst Mode Track Time
Bit
7
6
5
4
3
2
1
0
AD0TK[5:0]
R/W
Name
Type
Reset
R
0
R
0
0
1
0
1
1
0
SFR Page = 0xF; SFR Address = 0xBD
Bit
Name
Function
7:6
Unused
Read = 00b; Write = Don’t Care.
5:0 AD0TK[5:0]
ADC0 Burst Mode Track Time.
Sets the time delay between consecutive conversions performed in Burst Mode.
The ADC0 Burst Mode Track time is programmed according to the following equa-
tion:
Ttrack
50ns
AD0TK = 63 – ---------------- – 1
or
Ttrack = 64 – AD0TK50ns
Notes:
1. If AD0TM is set to 1, an additional 3 SAR clock cycles of Track time will be inserted prior to starting the
conversion.
2. The Burst Mode Track delay is not inserted prior to the first conversion. The required tracking time for the first
conversion should be met by the Burst Mode Power-Up Time.
Rev. 1.0
85
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SFR Definition 5.6. ADC0H: ADC0 Data Word High Byte
Bit
7
6
5
4
3
2
1
0
ADC0[15:8]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xBE
Bit
Name
Description
Read
Write
7:0 ADC0[15:8]
Most Significant Byte of the Set the most significant
16-bit ADC0 Accumulator byte of the 16-bit ADC0
formatted according to the Accumulator to the value
settings in AD0SJST[2:0]. written.
ADC0 Data Word High
Byte.
Note: If Accumulator shifting is enabled, the most significant bits of the value read will be zeros. This register
should not be written when the SYNC bit is set to 1.
SFR Definition 5.7. ADC0L: ADC0 Data Word Low Byte
Bit
7
6
5
4
3
2
1
0
ADC0[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xBD;
Bit
Name
Description
Read
Write
7:0
ADC0[7:0]
Least Significant Byte of the Set the least significant
ADC0 Data Word Low Byte.
16-bit ADC0 Accumulator
formatted according to the
settings in AD0SJST[2:0].
byte of the 16-bit ADC0
Accumulator to the value
written.
Note: If Accumulator shifting is enabled, the most significant bits of the value read will be the least significant bits of
the accumulator high byte. This register should not be written when the SYNC bit is set to 1.
86
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5.4. Programmable Window Detector
The ADC Programmable Window Detector continuously compares the ADC0 output registers to user-pro-
grammed limits, and notifies the system when a desired condition is detected. This is especially effective in
an interrupt-driven system, saving code space and CPU bandwidth while delivering faster system
response times. The window detector interrupt flag (AD0WINT in register ADC0CN) can also be used in
polled mode. The ADC0 Greater-Than (ADC0GTH, ADC0GTL) and Less-Than (ADC0LTH, ADC0LTL)
registers hold the comparison values. The window detector flag can be programmed to indicate when mea-
sured data is inside or outside of the user-programmed limits, depending on the contents of the ADC0
Less-Than and ADC0 Greater-Than registers.
SFR Definition 5.8. ADC0GTH: ADC0 Greater-Than High Byte
Bit
7
6
5
4
3
2
1
0
AD0GT[15:8]
R/W
Name
Type
Reset
1
1
1
1
1
1
1
1
SFR Page = 0x0; SFR Address = 0xC4
Bit Name
7:0 AD0GT[15:8]
Function
ADC0 Greater-Than High Byte.
Most Significant Byte of the 16-bit Greater-Than window compare register.
SFR Definition 5.9. ADC0GTL: ADC0 Greater-Than Low Byte
Bit
7
6
5
4
3
2
1
0
AD0GT[7:0]
R/W
Name
Type
Reset
1
1
1
1
1
1
1
1
SFR Page = 0x0; SFR Address = 0xC3
Bit Name
7:0 AD0GT[7:0]
Function
ADC0 Greater-Than Low Byte.
Least Significant Byte of the 16-bit Greater-Than window compare register.
Note: In 8-bit mode, this register should be set to 0x00.
Rev. 1.0
87
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SFR Definition 5.10. ADC0LTH: ADC0 Less-Than High Byte
Bit
7
6
5
4
3
2
1
0
AD0LT[15:8]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xC6
Bit Name
7:0 AD0LT[15:8] ADC0 Less-Than High Byte.
Most Significant Byte of the 16-bit Less-Than window compare register.
Function
SFR Definition 5.11. ADC0LTL: ADC0 Less-Than Low Byte
Bit
7
6
5
4
3
2
1
0
AD0LT[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xC5
Bit
Name
AD0LT[7:0] ADC0 Less-Than Low Byte.
Least Significant Byte of the 16-bit Less-Than window compare register.
Function
7:0
Note: In 8-bit mode, this register should be set to 0x00.
5.4.1. Window Detector In Single-Ended Mode
Figure 5.5
shows
two
example
window
comparisons
for
right-justified
data,
with
ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). The input voltage can
range from 0 to VREF x (1023/1024) with respect to GND, and is represented by a 10-bit unsigned integer
value. In the left example, an AD0WINT interrupt will be generated if the ADC0 conversion word
(ADC0H:ADC0L) is within the range defined by ADC0GTH:ADC0GTL and ADC0LTH:ADC0LTL
(if 0x0040 < ADC0H:ADC0L < 0x0080). In the right example, and AD0WINT interrupt will be generated if
the ADC0 conversion word is outside of the range defined by the ADC0GT and ADC0LT registers
(if ADC0H:ADC0L < 0x0040 or ADC0H:ADC0L > 0x0080). Figure 5.6 shows an example using left-justi-
fied data with the same comparison values.
88
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ADC0H:ADC0L
0x03FF
ADC0H:ADC0L
Input Voltage
(Px.x - GND)
Input Voltage
(Px.x - GND)
VREF x (1023/1024)
VREF x (1023/1024)
0x03FF
AD0WINT
not affected
AD0WINT=1
0x0081
0x0081
VREF x (128/1024)
VREF x (64/1024)
0x0080
0x007F
ADC0LTH:ADC0LTL
VREF x (128/1024)
VREF x (64/1024)
0x0080
0x007F
ADC0GTH:ADC0GTL
AD0WINT
not affected
AD0WINT=1
0x0041
0x0040
0x0041
0x0040
ADC0GTH:ADC0GTL
ADC0LTH:ADC0LTL
0x003F
0x003F
AD0WINT=1
AD0WINT
not affected
0x0000
0x0000
0
0
Figure 5.5. ADC Window Compare Example: Right-Justified Single-Ended Data
ADC0H:ADC0L
0xFFC0
ADC0H:ADC0L
0xFFC0
Input Voltage
(Px.x - GND)
Input Voltage
(Px.x - GND)
VREF x (1023/1024)
VREF x (1023/1024)
AD0WINT
not affected
AD0WINT=1
0x2040
0x2040
VREF x (128/1024)
VREF x (64/1024)
0x2000
0x1FC0
ADC0LTH:ADC0LTL
VREF x (128/1024)
VREF x (64/1024)
0x2000
0x1FC0
ADC0GTH:ADC0GTL
AD0WINT
not affected
AD0WINT=1
0x1040
0x1000
0x1040
0x1000
ADC0GTH:ADC0GTL
ADC0LTH:ADC0LTL
0x0FC0
0x0FC0
AD0WINT=1
AD0WINT
not affected
0x0000
0x0000
0
0
Figure 5.6. ADC Window Compare Example: Left-Justified Single-Ended Data
5.4.2. ADC0 Specifications
See “4. Electrical Characteristics” on page 40 for a detailed listing of ADC0 specifications.
Rev. 1.0
89
Si1000/1/2/3/4/5
5.5. ADC0 Analog Multiplexer
ADC0 on Si1000/1/2/3/4/5 has an analog multiplexer, referred to as AMUX0.
AMUX0 selects the positive inputs to the single-ended ADC0. Any of the following may be selected as the
positive input: Port I/O pins, the on-chip temperature sensor, Regulated Digital Supply Voltage (Output of
VREG0), VDD_MCU Supply, or the positive input may be connected to GND. The ADC0 input channels
are selected in the ADC0MX register described in SFR Definition 5.12.
ADC0MX
P0.0
Programmable
Attenuator
AIN+
ADC0
AMUX
P2.6*
Temp
Sensor
Gain=0. 5 or1
Digital Supply
VDD_MCU
*P1.0 – P1.4 are not available as device pins.
P2.4 – P2.6 are only available on Si1000/1/2/3 devices
Figure 5.7. ADC0 Multiplexer Block Diagram
Important Note About ADC0 Input Configuration: Port pins selected as ADC0 inputs should be config-
ured as analog inputs, and should be skipped by the Digital Crossbar. To configure a Port pin for analog
input, set to 0 the corresponding bit in register PnMDIN and disable the digital driver (PnMDOUT = 0 and
Port Latch = 1). To force the Crossbar to skip a Port pin, set to 1 the corresponding bit in register PnSKIP.
See Section “21. Port Input/Output” on page 207 for more Port I/O configuration details.
90
Rev. 1.0
Si1000/1/2/3/4/5
SFR Definition 5.12. ADC0MX: ADC0 Input Channel Select
Bit
7
6
5
4
3
2
1
0
AD0MX
Name
Type
Reset
R
0
R
0
R
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
SFR Page = 0x0; SFR Address = 0xBB
Bit
Name
Unused Read = 000b; Write = Don’t Care.
AD0MX
Function
7:5
4:0
AMUX0 Positive Input Selection.
Selects the positive input channel for ADC0.
00000:
00001:
00010:
00011:
00100:
00101:
00110:
00111:
01000:
01001:
01010:
01011:
01100:
01101:
01110:
01111:
P0.0
10000:
10001:
10010:
10011:
10100:
10101:
10110:
10111:
11000:
11001:
11010:
11011:
11100:
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
P1.5
Reserved.
Reserved.
Reserved.
Temperature Sensor
VDD_MCU Supply Voltage
(1.8–3.6 V)
P1.6
11101:
11110:
11111:
Digital Supply Voltage
(VREG0 Output, 1.7 V Typical)
P1.7
VDD_MCU Supply Voltage
(1.8–3.6 V)
Ground
Rev. 1.0
91
Si1000/1/2/3/4/5
5.6. Temperature Sensor
An on-chip temperature sensor is included on the Si1000/1/2/3/4/5 which can be directly accessed via the
ADC multiplexer in single-ended configuration. To use the ADC to measure the temperature sensor, the
ADC mux channel should select the temperature sensor. The temperature sensor transfer function is
shown in Figure 5.8. The output voltage (V
) is the positive ADC input when the ADC multiplexer is set
TEMP
correctly. The TEMPE bit in register REF0CN enables/disables the temperature sensor, as described in
SFR Definition 5.15. While disabled, the temperature sensor defaults to a high impedance state and any
ADC measurements performed on the sensor will result in meaningless data. Refer to Table 4.9 for the
slope and offset parameters of the temperature sensor.
VTEMP = (Slope x TempC - 25) +Offset
TempC = 25 + (VTEMP - Offset) / Slope
Slope( V / deg C)
Offset( V at 25 Celsius)
Temperature
Figure 5.8. Temperature Sensor Transfer Function
5.6.1. Calibration
The uncalibrated temperature sensor output is extremely linear and suitable for relative temperature mea-
surements (see Table 4.10 for linearity specifications). For absolute temperature measurements, offset
and/or gain calibration is recommended. Typically a 1-point (offset) calibration includes the following steps:
1. Control/measure the ambient temperature (this temperature must be known).
2. Power the device, and delay for a few seconds to allow for self-heating.
3. Perform an ADC conversion with the temperature sensor selected as the positive input and GND
selected as the negative input.
4. Calculate the offset characteristics, and store this value in non-volatile memory for use with subsequent
temperature sensor measurements.
92
Rev. 1.0
Si1000/1/2/3/4/5
Figure 5.9 shows the typical temperature sensor error assuming a 1-point calibration at 25 °C. Parame-
ters that affect ADC measurement, in particular the voltage reference value, will also affect temper-
ature measurement.
A single-point offset measurement of the temperature sensor is performed on each device during produc-
tion test. The measurement is performed at 25 °C ±5 °C, using the ADC with the internal high speed refer-
ence buffer selected as the Voltage Reference. The direct ADC result of the measurement is stored in the
SFR registers TOFFH and TOFFL, shown in SFR Definition 5.13 and SFR Definition 5.14.
5.00
4.00
3.00
2.00
1.00
0.00
5.00
4.00
3.00
2.00
1.00
0.00
-1.00
-2.00
-3.00
-4.00
-5.00
40.00
-40.00
-20.00
0.00
60.00
80.00
20.00
-1.00
-2.00
-3.00
-4.00
-5.00
Temperature (degrees C)
Figure 5.9. Temperature Sensor Error with 1-Point Calibration (VREF = 1.68 V)
Rev. 1.0
93
Si1000/1/2/3/4/5
SFR Definition 5.13. TOFFH: ADC0 Data Word High Byte
Bit
7
6
5
4
3
2
1
0
TOFF[9:2]
Name
Type
Reset
R
R
R
R
R
R
R
R
Varies
Varies
Varies
Varies
Varies
Varies
Varies
Varies
SFR Page = 0xF; SFR Address = 0x86
Bit
Name
Function
7:0
TOFF[9:2]
Temperature Sensor Offset High Bits.
Most Significant Bits of the 10-bit temperature sensor offset measurement.
SFR Definition 5.14. TOFFL: ADC0 Data Word Low Byte
Bit
7
6
5
4
3
2
1
0
TOFF[1:0]
Name
Type
Reset
R
R
Varies
Varies
0
0
0
0
0
0
SFR Page = 0xF; SFR Address = 0x85
Bit
Name
Function
7:6
TOFF[1:0] Temperature Sensor Offset Low Bits.
Least Significant Bits of the 10-bit temperature sensor offset measurement.
Read = 0; Write = Don't Care.
5:0
Unused
94
Rev. 1.0
Si1000/1/2/3/4/5
5.7. Voltage and Ground Reference Options
The voltage reference MUX is configurable to use an externally connected voltage reference, one of two
internal voltage references, or one of two power supply voltages (see Figure 5.10). The ground reference
MUX allows the ground reference for ADC0 to be selected between the ground pin (GND) or a port pin
dedicated to analog ground (P0.1/AGND).
The voltage and ground reference options are configured using the REF0CN SFR described on page 97.
Electrical specifications are can be found in the Electrical Specifications Chapter.
Important Note About the V
and AGND Inputs: Port pins are used as the external V
and AGND
REF
REF
inputs. When using an external voltage reference or the internal precision reference, P0.0/VREF should be
configured as an analog input and skipped by the Digital Crossbar. When using AGND as the ground refer-
ence to ADC0, P0.1/AGND should be configured as an analog input and skipped by the Digital Crossbar.
Refer to Section “21. Port Input/Output” on page 207 for complete Port I/O configuration details. The exter-
nal reference voltage must be within the range 0 V
VDD_MCU and the external ground reference
REF
must be at the same DC voltage potential as GND.
REF0CN
ADC
Input
Mux
Temp Sensor
EN
REFOE
EN
Internal 1.68V
Reference
VDD
External
Voltage
Reference
Circuit
R1
P0.0/VREF
VDD/DC+
00
01
10
11
VREF
(to ADC)
Internal 1.8V
Regulated Digital Supply
GND
Internal 1.65V
High Speed Reference
+
4.7F
0.1F
GND
0
1
Ground
(to ADC)
Recommended
Bypass Capacitors
P0.1/AGND
REFGND
Figure 5.10. Voltage Reference Functional Block Diagram
5.8. External Voltage References
To use an external voltage reference, REFSL[1:0] should be set to 00 and the internal 1.68 V precision ref-
erence should be disabled by setting REFOE to 0. Bypass capacitors should be added as recommended
by the manufacturer of the external voltage reference.
Rev. 1.0
95
Si1000/1/2/3/4/5
5.9. Internal Voltage References
For applications requiring the maximum number of port I/O pins, or very short VREF turn-on time, the
1.65 V high-speed reference will be the best internal reference option to choose. The high speed internal
reference is selected by setting REFSL[1:0] to 11. When selected, the high speed internal reference will be
automatically enabled/disabled on an as-needed basis by ADC0.
For applications requiring the highest absolute accuracy, the 1.68 V precision voltage reference will be the
best internal reference option to choose. The 1.68 V precision reference may be enabled and selected by
setting REFOE to 1 and REFSL[1:0] to 00. An external capacitor of at least 0.1 µF is recommended when
using the precision voltage reference.
In applications that leave the precision internal oscillator always running, there is no additional power
required to use the precision voltage reference. In all other applications, using the high speed reference
will result in lower overall power consumption due to its minimal startup time and the fact that it remains in
a low power state when an ADC conversion is not taking place.
Note: When using the precision internal oscillator as the system clock source, the precision voltage refer-
ence should not be enabled from a disabled state. To use the precision oscillator and the precision voltage
reference simultaneously, the precision voltage reference should be enabled first and allowed to settle to
its final value (charging the external capacitor) before the precision oscillator is started and selected as the
system clock.
For applications with a non-varying power supply voltage, using the power supply as the voltage reference
can provide ADC0 with added dynamic range at the cost of reduced power supply noise rejection. To use
the 1.8 to 3.6 V power supply voltage (VDD_MCU) or the 1.8 V regulated digital supply voltage as the ref-
erence source, REFSL[1:0] should be set to 01 or 10, respectively.
5.10. Analog Ground Reference
To prevent ground noise generated by switching digital logic from affecting sensitive analog measure-
ments, a separate analog ground reference option is available. When enabled, the ground reference for
ADC0 during both the tracking/sampling and the conversion periods is taken from the P0.1/AGND pin. Any
external sensors sampled by ADC0 should be referenced to the P0.1/AGND pin. This pin should be con-
nected to the ground terminal of any external sensors sampled by ADC0. If an external voltage reference is
used, the P0.1/AGND pin should be connected to the ground of the external reference and its associated
decoupling capacitor. If the 1.68 V precision internal reference is used, then P0.1/AGND should be con-
nected to the ground terminal of its external decoupling capacitor. The separate analog ground reference
option is enabled by setting REFGND to 1. Note that when sampling the internal temperature sensor, the
internal chip ground is always used for the sampling operation, regardless of the setting of the REFGND
bit. Similarly, whenever the internal 1.65 V high-speed reference is selected, the internal chip ground is
always used during the conversion period, regardless of the setting of the REFGND bit.
5.11. Temperature Sensor Enable
The TEMPE bit in register REF0CN enables/disables the temperature sensor. While disabled, the temper-
ature sensor defaults to a high impedance state and any ADC0 measurements performed on the sensor
result in meaningless data. See Section “5.6. Temperature Sensor” on page 92 for details on temperature
sensor characteristics when it is enabled.
96
Rev. 1.0
Si1000/1/2/3/4/5
SFR Definition 5.15. REF0CN: Voltage Reference Control
Bit
7
6
5
4
3
2
1
0
REFGND
REFSL
TEMPE
REFOE
Name
Type
Reset
R
0
R
0
R/W
0
R/W
1
R/W
1
R/W
0
R
0
R/W
0
SFR Page = 0x0; SFR Address = 0xD1
Bit
7:6
5
Name
Function
Unused Read = 00b; Write = Don’t Care.
REFGND Analog Ground Reference.
Selects the ADC0 ground reference.
0: The ADC0 ground reference is the GND pin.
1: The ADC0 ground reference is the P0.1/AGND pin.
4:3
REFSL Voltage Reference Select.
Selects the ADC0 voltage reference.
00: The ADC0 voltage reference is the P0.0/VREF pin.
01: The ADC0 voltage reference is the VDD_MCU pin.
10: The ADC0 voltage reference is the internal 1.8 V digital supply voltage.
11: The ADC0 voltage reference is the internal 1.65 V high speed voltage reference.
2
TEMPE Temperature Sensor Enable.
Enables/Disables the internal temperature sensor.
0: Temperature Sensor Disabled.
1: Temperature Sensor Enabled.
1
0
Unused Read = 0b; Write = Don’t Care.
REFOE Internal Voltage Reference Output Enable.
Connects/Disconnects the internal voltage reference to the P0.0/VREF pin.
0: Internal 1.68 V Precision Voltage Reference disabled and not connected to
P0.0/VREF.
1: Internal 1.68 V Precision Voltage Reference enabled and connected to
P0.0/VREF.
5.12. Voltage Reference Electrical Specifications
See Table 4.11 on page 61 for detailed Voltage Reference Electrical Specifications.
Rev. 1.0
97
Si1000/1/2/3/4/5
6. Programmable Current Reference (IREF0)
Si1000/1/2/3/4/5 devices include an on-chip programmable current reference (source or sink) with two out-
put current settings: Low Power Mode and High Current Mode. The maximum current output in Low Power
Mode is 63 µA (1 µA steps) and the maximum current output in High Current Mode is 504 µA (8 µA steps).
The current source/sink is controlled though the IREF0CN special function register. It is enabled by setting
the desired output current to a non-zero value. It is disabled by writing 0x00 to IREF0CN. The port I/O pin
associated with ISRC0 should be configured as an analog input and skipped in the Crossbar. See Section
“21. Port Input/Output” on page 207 for more details.
SFR Definition 6.1. IREF0CN: Current Reference Control
Bit
7
6
5
4
3
2
1
0
SINK
MODE
IREF0DAT
R/W
Name
Type
Reset
R/W
0
R/W
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xB9
Bit
Name
Function
7
SINK
IREF0 Current Sink Enable.
Selects if IREF0 is a current source or a current sink.
0: IREF0 is a current source.
1: IREF0 is a current sink.
6
MDSEL
IREF0 Output Mode Select.
Selects Low Power or High Current Mode.
0: Low Power Mode is selected (step size = 1 µA).
1: High Current Mode is selected (step size = 8 µA).
5:0 IREF0DAT[5:0] IREF0 Data Word.
Specifies the number of steps required to achieve the desired output current.
Output current = direction x step size x IREF0DAT.
IREF0 is in a low power state when IREF0DAT is set to 0x00.
6.1. IREF0 Specifications
See Table 4.12 on page 62 for a detailed listing of IREF0 specifications.
98
Rev. 1.0
Si1000/1/2/3/4/5
7. Comparators
Si1000/1/2/3/4/5 devices include two on-chip programmable voltage comparators: Comparator 0 (CPT0) is
shown in Figure 7.1; Comparator 1 (CPT1) is shown in Figure 7.2. The two comparators operate identi-
cally, but may differ in their ability to be used as reset or wake-up sources. See the Reset Sources chapter
and the Power Management chapter for details on reset sources and low power mode wake-up sources,
respectively.
The Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two
outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0, CP1), or an
asynchronous “raw” output (CP0A, CP1A). The asynchronous CP0A signal is available even when the
system clock is not active. This allows the Comparator to operate and generate an output when the device
is in some low power modes.
7.1. Comparator Inputs
Each Comparator performs an analog comparison of the voltage levels at its positive (CP0+ or CP1+) and
negative (CP0- or CP1-) input. Both comparators support multiple port pin inputs multiplexed to their posi-
tive and negative comparator inputs using analog input multiplexers. The analog input multiplexers are
completely under software control and configured using SFR registers. See Section “7.6. Comparator0 and
Comparator1 Analog Multiplexers” on page 106 for details on how to select and configure Comparator
inputs.
Important Note About Comparator Inputs: The Port pins selected as Comparator inputs should be con-
figured as analog inputs and skipped by the Crossbar. See the Port I/O chapter for more details on how to
configure Port I/O pins as Analog Inputs. The Comparator may also be used to compare the logic level of
digital signals, however, Port I/O pins configured as digital inputs must be driven to a valid logic state
(HIGH or LOW) to avoid increased power consumption.
CP0EN
CP0OUT
CP0RIF
CP0FIF
VDD
CP0HYP1
CP0HYP0
CP0HYN1
CP0HYN0
CP0
Interrupt
CPT0MD
Analog Input Multiplexer
CP0
Rising-edge
CP0
Falling-edge
Px.x
CP0 +
Interrupt
Logic
Px.x
Px.x
CP0
+
-
SET
SET
CLR
D
Q
Q
D
Q
Q
CLR
Crossbar
(SYNCHRONIZER)
(ASYNCHRONOUS)
GND
CP0 -
CP0A
Reset
Decision
Tree
Px.x
Figure 7.1. Comparator 0 Functional Block Diagram
Rev. 1.0
99
Si1000/1/2/3/4/5
7.2. Comparator Outputs
When a comparator is enabled, its output is a logic 1 if the voltage at the positive input is higher than the
voltage at the negative input. When disabled, the comparator output is a logic 0. The comparator output is
synchronized with the system clock as shown in Figure 7.2. The synchronous “latched” output (CP0, CP1)
can be polled in software (CPnOUT bit), used as an interrupt source, or routed to a Port pin through the
Crossbar.
The asynchronous “raw” comparator output (CP0A, CP1A) is used by the low power mode wakeup logic
and reset decision logic. See the Power Options chapter and the Reset Sources chapter for more details
on how the asynchronous comparator outputs are used to make wake-up and reset decisions. The asyn-
chronous comparator output can also be routed directly to a Port pin through the Crossbar, and is available
for use outside the device even if the system clock is stopped.
When using a Comparator as an interrupt source, Comparator interrupts can be generated on rising-edge
and/or falling-edge comparator output transitions. Two independent interrupt flags (CPnRIF and CPnFIF)
allow software to determine which edge caused the Comparator interrupt. The comparator rising-edge and
falling-edge interrupt flags are set by hardware when a corresponding edge is detected regardless of the
interrupt enable state. Once set, these bits remain set until cleared by software.
The rising-edge and falling-edge interrupts can be individually enabled using the CPnRIE and CPnFIE
interrupt enable bits in the CPTnMD register. In order for the CPnRIF and/or CPnFIF interrupt flags to gen-
erate an interrupt request to the CPU, the Comparator must be enabled as an interrupt source and global
interrupts must be enabled. See the Interrupt Handler chapter for additional information.
CP1EN
CP1OUT
CP1RIF
CP1FIF
VDD
CP1HYP1
CP1HYP0
CP1HYN1
CP1HYN0
CP1
Interrupt
CPT0MD
Analog Input Multiplexer
CP1
Rising-edge
CP1
Falling-edge
Px.x
CP1 +
Interrupt
Logic
Px.x
Px.x
CP1
+
-
SET
SET
CLR
D
Q
Q
D
Q
Q
CLR
Crossbar
(SYNCHRONIZER)
(ASYNCHRONOUS)
GND
CP1 -
CP1A
Reset
Decision
Tree
Px.x
Figure 7.2. Comparator 1 Functional Block Diagram
100
Rev. 1.0
Si1000/1/2/3/4/5
7.3. Comparator Response Time
Comparator response time may be configured in software via the CPTnMD registers described on
“CPT0MD: Comparator 0 Mode Selection” on page 103 and “CPT1MD: Comparator 1 Mode Selection” on
page 105. Four response time settings are available: Mode 0 (Fastest Response Time), Mode 1, Mode 2,
and Mode 3 (Lowest Power). Selecting a longer response time reduces the Comparator active supply cur-
rent. The Comparators also have low power shutdown state, which is entered any time the comparator is
disabled. Comparator rising edge and falling edge response times are typically not equal. See Table 4.13
on page 63 for complete comparator timing and supply current specifications.
7.4. Comparator Hysteresis
The Comparators feature software-programmable hysteresis that can be used to stabilize the comparator
output while a transition is occurring on the input. Using the CPTnCN registers, the user can program both
the amount of hysteresis voltage (referred to the input voltage) and the positive and negative-going sym-
metry of this hysteresis around the threshold voltage (i.e., the comparator negative input).
Figure 7.3 shows that when positive hysteresis is enabled, the comparator output does not transition from
logic 0 to logic 1 until the comparator positive input voltage has exceeded the threshold voltage by an
amount equal to the programmed hysteresis. It also shows that when negative hysteresis is enabled, the
comparator output does not transition from logic 1 to logic 0 until the comparator positive input voltage has
fallen below the threshold voltage by an amount equal to the programmed hysteresis.
The amount of positive hysteresis is determined by the settings of the CPnHYP bits in the CPTnCN regis-
ter and the amount of negative hysteresis voltage is determined by the settings of the CPnHYN bits in the
same register. Settings of 20, 10, 5, or 0 mV can be programmed for both positive and negative hysteresis.
See Section “Table 4.13. Comparator Electrical Characteristics” on page 63 for complete comparator hys-
teresis specifications.
CPn+
VIN+
VIN-
+
CPn
_
OUT
CPn-
CIRCUIT CONFIGURATION
Positive Hysteresis Voltage
(Programmed with CP0HYP Bits)
VIN-
Negative Hysteresis Voltage
(Programmed by CP0HYN Bits)
INPUTS
VIN+
VOH
OUTPUT
VOL
Negative Hysteresis
Disabled
Maximum
Negative Hysteresis
Positive Hysteresis
Disabled
Maximum
Positive Hysteresis
Figure 7.3. Comparator Hysteresis Plot
Rev. 1.0
101
Si1000/1/2/3/4/5
7.5. Comparator Register Descriptions
The SFRs used to enable and configure the comparators are described in the following register descrip-
tions. A Comparator must be enabled by setting the CPnEN bit to logic 1 before it can be used. From an
enabled state, a comparator can be disabled and placed in a low power state by clearing the CPnEN bit to
logic 0.
Important Note About Comparator Settings: False rising and falling edges can be detected by the Com-
parator while powering on or if changes are made to the hysteresis or response time control bits. There-
fore, it is recommended that the rising-edge and falling-edge flags be explicitly cleared to logic 0 a short
time after the comparator is enabled or its mode bits have been changed. The Comparator Power Up Time
is specified in Section “Table 4.13. Comparator Electrical Characteristics” on page 63.
SFR Definition 7.1. CPT0CN: Comparator 0 Control
Bit
7
6
5
4
3
2
1
0
CP0EN
CP0OUT
CP0RIF
CP0FIF
CP0HYP[1:0]
R/W
CP0HYN[1:0]
R/W
Name
Type
Reset
R/W
0
R
0
R/W
0
R/W
0
0
0
0
0
SFR Page= 0x0; SFR Address = 0x9B
Bit
Name
Function
7
CP0EN
Comparator0 Enable Bit.
0: Comparator0 Disabled.
1: Comparator0 Enabled.
6
5
CP0OUT
CP0RIF
CP0FIF
Comparator0 Output State Flag.
0: Voltage on CP0+ < CP0–.
1: Voltage on CP0+ > CP0–.
Comparator0 Rising-Edge Flag. Must be cleared by software.
0: No Comparator0 Rising Edge has occurred since this flag was last cleared.
1: Comparator0 Rising Edge has occurred.
4
Comparator0 Falling-Edge Flag. Must be cleared by software.
0: No Comparator0 Falling-Edge has occurred since this flag was last cleared.
1: Comparator0 Falling-Edge has occurred.
3:2
CP0HYP[1:0] Comparator0 Positive Hysteresis Control Bits.
00: Positive Hysteresis Disabled.
01: Positive Hysteresis = 5 mV.
10: Positive Hysteresis = 10 mV.
11: Positive Hysteresis = 20 mV.
1:0
CP0HYN[1:0] Comparator0 Negative Hysteresis Control Bits.
00: Negative Hysteresis Disabled.
01: Negative Hysteresis = 5 mV.
10: Negative Hysteresis = 10 mV.
11: Negative Hysteresis = 20 mV.
102
Rev. 1.0
Si1000/1/2/3/4/5
SFR Definition 7.2. CPT0MD: Comparator 0 Mode Selection
Bit
7
6
5
4
3
2
1
0
CP0RIE
CP0FIE
CP0MD[1:0]
R/W
Name
Type
Reset
R/W
1
R
0
R/W
0
R/W
0
R
0
R
0
1
0
SFR Page = All Pages; SFR Address = 0x9D
Bit
Name
Function
7
Reserved Read = 1b, Must Write 1b.
6
Unused
CP0RIE
Read = 0b, Write = don’t care.
5
Comparator0 Rising-Edge Interrupt Enable.
0: Comparator0 Rising-edge interrupt disabled.
1: Comparator0 Rising-edge interrupt enabled.
4
CP0FIE
Comparator0 Falling-Edge Interrupt Enable.
0: Comparator0 Falling-edge interrupt disabled.
1: Comparator0 Falling-edge interrupt enabled.
3:2
1:0
Unused
Read = 00b, Write = don’t care.
CP0MD[1:0] Comparator0 Mode Select.
These bits affect the response time and power consumption for Comparator0.
00: Mode 0 (Fastest Response Time, Highest Power Consumption)
01: Mode 1
10: Mode 2
11: Mode 3 (Slowest Response Time, Lowest Power Consumption)
Rev. 1.0
103
Si1000/1/2/3/4/5
SFR Definition 7.3. CPT1CN: Comparator 1 Control
Bit
7
6
5
4
3
2
1
0
CP1EN
CP1OUT
CP1RIF
CP1FIF
CP1HYP[1:0]
R/W
CP1HYN[1:0]
R/W
Name
Type
Reset
R/W
0
R
0
R/W
0
R/W
0
0
0
0
0
SFR Page= 0x0; SFR Address = 0x9A
Bit
Name
Function
7
CP1EN
Comparator1 Enable Bit.
0: Comparator1 Disabled.
1: Comparator1 Enabled.
6
5
CP1OUT
CP1RIF
CP1FIF
Comparator1 Output State Flag.
0: Voltage on CP1+ < CP1–.
1: Voltage on CP1+ > CP1–.
Comparator1 Rising-Edge Flag. Must be cleared by software.
0: No Comparator1 Rising Edge has occurred since this flag was last cleared.
1: Comparator1 Rising Edge has occurred.
4
Comparator1 Falling-Edge Flag. Must be cleared by software.
0: No Comparator1 Falling-Edge has occurred since this flag was last cleared.
1: Comparator1 Falling-Edge has occurred.
3:2
CP1HYP[1:0] Comparator1 Positive Hysteresis Control Bits.
00: Positive Hysteresis Disabled.
01: Positive Hysteresis = 5 mV.
10: Positive Hysteresis = 10 mV.
11: Positive Hysteresis = 20 mV.
1:0
CP1HYN[1:0] Comparator1 Negative Hysteresis Control Bits.
00: Negative Hysteresis Disabled.
01: Negative Hysteresis = 5 mV.
10: Negative Hysteresis = 10 mV.
11: Negative Hysteresis = 20 mV.
104
Rev. 1.0
Si1000/1/2/3/4/5
SFR Definition 7.4. CPT1MD: Comparator 1 Mode Selection
Bit
7
6
5
4
3
2
1
0
CP1RIE
CP1FIE
CP1MD[1:0]
R/W
Name
Type
Reset
R/W
1
R
0
R/W
0
R/W
0
R
0
R
0
1
0
SFR Page = 0x0; SFR Address = 0x9C
Bit
Name
Function
7
Reserved Read = 1b, Must Write 1b.
6
Unused
CP1RIE
Read = 00b, Write = don’t care.
5
Comparator1 Rising-Edge Interrupt Enable.
0: Comparator1 Rising-edge interrupt disabled.
1: Comparator1 Rising-edge interrupt enabled.
4
CP1FIE
Comparator1 Falling-Edge Interrupt Enable.
0: Comparator1 Falling-edge interrupt disabled.
1: Comparator1 Falling-edge interrupt enabled.
3:2
1:0
Unused
Read = 00b, Write = don’t care.
CP1MD[1:0] Comparator1 Mode Select
These bits affect the response time and power consumption for Comparator1.
00: Mode 0 (Fastest Response Time, Highest Power Consumption)
01: Mode 1
10: Mode 2
11: Mode 3 (Slowest Response Time, Lowest Power Consumption)
Rev. 1.0
105
Si1000/1/2/3/4/5
7.6. Comparator0 and Comparator1 Analog Multiplexers
Comparator0 and Comparator1 on Si1000/1/2/3/4/5 devices have analog input multiplexers to connect
Port I/O pins and internal signals the comparator inputs; CP0+/CP0- are the positive and negative input
multiplexers for Comparator0 and CP1+/CP1- are the positive and negative input multiplexers for
Comparator1.
The comparator input multiplexers directly support capacitive touch switches. When the Capacitive Touch
Sense Compare input is selected on the positive or negative multiplexer, any Port I/O pin connected to the
other multiplexer can be directly connected to a capacitive touch switch with no additional external compo-
nents. The Capacitive Touch Sense Compare provides the appropriate reference level for detecting when
the capacitive touch switches have charged or discharged through the on-chip Rsense resistor. The Com-
parator outputs can be routed to Timer2 or Timer3 for capturing sense capacitor’s charge and discharge
time. See Section “27. Timers” on page 330 for details. See Application Note AN338 for details on Capaci-
tive Touch Switch sensing.
Any of the following may be selected as comparator inputs: Port I/O pins, Capacitive Touch Sense Com-
pare, VDD_MCU Supply Voltage, Regulated Digital Supply Voltage (Output of VREG0) or ground. The
Comparator’s supply voltage divided by 2 is also available as an input; the resistors used to divide the volt-
age only draw current when this setting is selected. The Comparator input multiplexers are configured
using the CPT0MX and CPT1MX registers described in SFR Definition 7.5 and SFR Definition 7.6.
CPTnMX
P0.1
P0.3
P0.5
P0.7
P0.0
P0.2
P0.4
P0.6
CPnOUT
Rsense
CPnOUT
Rsense
P1.5
P1.7
P2.1
P2.3
P2.5
P1.6
P2.0
P2.2
P2.4
P2.6
Only enabled when
Capacitive Touch
Sense Compare is
selected on CPn+
Input MUX.
Only enabled when
Capacitive Touch
Sense Compare is
selected on CPn-
Input MUX.
Capacitive
Capacitive
CPn-
Input
MUX
CPn+
Input
MUX
VDD_MCU
VDD_MCU
R
CPnOUT
R
VDD_MCU CPnOUT
Touch
Sense
Touch
Sense
R
R
Compare
Compare
+
-
(1/3 or 2/3) x VDD_MCU
(1/3 or 2/3) x VDD_MCU
R
R
VDD_MCU
R
VDD_MCU
R
GND
½ x VDD_MCU
Digital Supply
½ x VDD_MCU
VBAT
R
R
VDD_MCU
GND
Figure 7.4. CPn Multiplexer Block Diagram
Important Note About Comparator Input Configuration: Port pins selected as comparator inputs should
be configured as analog inputs, and should be skipped by the Digital Crossbar. To configure a Port pin for
analog input, set to 0 the corresponding bit in register PnMDIN and disable the digital driver (PnMDOUT =
0 and Port Latch = 1). To force the Crossbar to skip a Port pin, set to 1 the corresponding bit in register
PnSKIP. See Section “21. Port Input/Output” on page 207 for more Port I/O configuration details.
106
Rev. 1.0
Si1000/1/2/3/4/5
SFR Definition 7.5. CPT0MX: Comparator0 Input Channel Select
Bit
7
6
5
4
3
2
1
0
CMX0N[3:0]
CMX0P[3:0]
Name
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
SFR Page = 0x0; SFR Address = 0x9F
Bit
Name
Function
7:4
CMX0N Comparator0 Negative Input Selection.
Selects the negative input channel for Comparator0.
0000:
0001:
0010:
0011:
0100:
P0.1
1000:
1001:
1010:
1011:
1100:
P2.1
P0.3
P2.3
P0.5
P2.5
P0.7
Reserved
Reserved
Capacitive Touch Sense
Compare
0101:
0110:
0111:
Reserved
P1.5
1101:
1110:
1111:
VDD_MCU divided by 2
Digital Supply Voltage
Ground
P1.7
3:0
CMX0P Comparator0 Positive Input Selection.
Selects the positive input channel for Comparator0.
0000:
0001:
0010:
0011:
0100:
P0.0
1000:
1001:
1010:
1011:
1100:
P2.0
P2.2
P2.4
P2.6
P0.2
P0.4
P0.6
Reserved
Capacitive Touch Sense
Compare
0101:
0110:
0111:
Reserved
Reserved
P1.6
1101:
1110:
1111:
VDD_MCU divided by 2
VBAT Supply Voltage
VDD_MCU Supply Voltage
Rev. 1.0
107
Si1000/1/2/3/4/5
SFR Definition 7.6. CPT1MX: Comparator1 Input Channel Select
Bit
7
6
5
4
3
2
1
0
CMX1N[3:0]
CMX1P[3:0]
Name
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
SFR Page = 0x0; SFR Address = 0x9E
Bit
Name
Function
7:4
CMX1N Comparator1 Negative Input Selection.
Selects the negative input channel for Comparator1.
0000:
0001:
0010:
0011:
0100:
P0.1
1000:
1001:
1010:
1011:
1100:
P2.1
P0.3
P2.3
P0.5
P2.5
P0.7
Reserved
Reserved
Capacitive Touch Sense
Compare
0101:
0110:
0111:
Reserved
P1.5
1101:
1110:
1111:
VDD_MCU divided by 2
Digital Supply Voltage
Ground
P1.7
3:0
CMX1P Comparator1 Positive Input Selection.
Selects the positive input channel for Comparator1.
0000:
0001:
0010:
0011:
0100:
P0.0
1000:
1001:
1010:
1011:
1100:
P2.0
P2.2
P2.4
P2.6
P0.2
P0.4
P0.6
Reserved
Capacitive Touch Sense
Compare
0101:
0110:
0111:
Reserved
Reserved
P1.6
1101:
1110:
1111:
VDD_MCU divided by 2
VBAT Supply Voltage
VDD_MCU Supply Voltage
108
Rev. 1.0
Si1000/1/2/3/4/5
8. CIP-51 Microcontroller
The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the
MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft-
ware. The MCU family has a superset of all the peripherals included with a standard 8051. The CIP-51
also includes on-chip debug hardware (see description in Section 29), and interfaces directly with the ana-
log and digital subsystems providing a complete data acquisition or control-system solution in a single inte-
grated circuit.
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as
additional custom peripherals and functions to extend its capability (see Figure 8.1 for a block diagram).
The CIP-51 includes the following features:
Fully Compatible with MCS-51 Instruction Set
25 MIPS Peak Throughput with 25 MHz Clock
0 to 25 MHz Clock Frequency
Reset Input
Power Management Modes
On-chip Debug Logic
Extended Interrupt Handler
Program and Data Memory Security
8.1. Performance
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan-
dard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51
core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more
than eight system clock cycles.
DATA BUS
ACCUMULATOR
B
REGISTER
STACK POINTER
TMP1
TMP2
SRAM
ADDRESS
REGISTER
PSW
SRAM
ALU
DATA BUS
SFR_ADDRESS
SFR_CONTROL
BUFFER
D8
SFR
BUS
INTERFACE
D8
SFR_WRITE_DATA
SFR_READ_DATA
D8
DATA POINTER
PC INCREMENTER
D8
MEM_ADDRESS
MEM_CONTROL
PROGRAM COUNTER (PC)
PRGM. ADDRESS REG.
PIPELINE
MEMORY
INTERFACE
A16
D8
MEM_WRITE_DATA
MEM_READ_DATA
CONTROL
LOGIC
RESET
CLOCK
SYSTEM_IRQs
INTERRUPT
INTERFACE
EMULATION_IRQ
D8
STOP
IDLE
POWER CONTROL
REGISTER
D8
Figure 8.1. CIP-51 Block Diagram
Rev. 1.0
109
Si1000/1/2/3/4/5
With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. The CIP-51 has
a total of 109 instructions. The table below shows the total number of instructions that require each execu-
tion time.
Clocks to Execute
1
2
2/3
5
3
3/4
7
4
3
4/5
1
5
2
8
1
Number of Instructions
26
50
14
8.2. Programming and Debugging Support
In-system programming of the Flash program memory and communication with on-chip debug support
logic is accomplished via the Silicon Labs 2-Wire Development Interface (C2).
The on-chip debug support logic facilitates full speed in-circuit debugging, allowing the setting of hardware
breakpoints, starting, stopping and single stepping through program execution (including interrupt service
routines), examination of the program's call stack, and reading/writing the contents of registers and mem-
ory. This method of on-chip debugging is completely non-intrusive, requiring no RAM, Stack, timers, or
other on-chip resources. C2 details can be found in Section “29. C2 Interface” on page 371.
The CIP-51 is supported by development tools from Silicon Labs and third party vendors. Silicon Labs pro-
vides an integrated development environment (IDE) including editor, debugger and programmer. The IDE's
debugger and programmer interface to the CIP-51 via the C2 interface to provide fast and efficient in-sys-
tem device programming and debugging. Third party macro assemblers and C compilers are also avail-
able.
8.3. Instruction Set
The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ instruc-
tion set. Standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51
instructions are the binary and functional equivalent of their MCS-51™ counterparts, including opcodes,
addressing modes and effect on PSW flags. However, instruction timing is different than that of the stan-
dard 8051.
8.3.1. Instruction and CPU Timing
In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with
machine cycles varying from 2 to 12 clock cycles in length. However, the CIP-51 implementation is based
solely on clock cycle timing. All instruction timings are specified in terms of clock cycles.
Due to the pipelined architecture of the CIP-51, most instructions execute in the same number of clock
cycles as there are program bytes in the instruction. Conditional branch instructions take one less clock
cycle to complete when the branch is not taken as opposed to when the branch is taken. Table 8.1 is the
CIP-51 Instruction Set Summary, which includes the mnemonic, number of bytes, and number of clock
cycles for each instruction.
110
Rev. 1.0
Si1000/1/2/3/4/5
Table 8.1. CIP-51 Instruction Set Summary
Mnemonic
Description
Bytes
Clock
Cycles
Arithmetic Operations
ADD A, Rn
ADD A, direct
ADD A, @Ri
ADD A, #data
ADDC A, Rn
ADDC A, direct
ADDC A, @Ri
ADDC A, #data
SUBB A, Rn
SUBB A, direct
SUBB A, @Ri
SUBB A, #data
INC A
INC Rn
INC direct
INC @Ri
DEC A
DEC Rn
DEC direct
DEC @Ri
INC DPTR
MUL AB
DIV AB
Add register to A
Add direct byte to A
Add indirect RAM to A
Add immediate to A
Add register to A with carry
Add direct byte to A with carry
Add indirect RAM to A with carry
Add immediate to A with carry
Subtract register from A with borrow
Subtract direct byte from A with borrow
Subtract indirect RAM from A with borrow
Subtract immediate from A with borrow
Increment A
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
1
1
2
1
1
1
1
1
1
2
2
2
1
2
2
2
1
2
2
2
1
1
2
2
1
1
2
2
1
4
8
1
Increment register
Increment direct byte
Increment indirect RAM
Decrement A
Decrement register
Decrement direct byte
Decrement indirect RAM
Increment Data Pointer
Multiply A and B
Divide A by B
Decimal adjust A
DA A
Logical Operations
ANL A, Rn
AND Register to A
AND direct byte to A
AND indirect RAM to A
AND immediate to A
AND A to direct byte
AND immediate to direct byte
OR Register to A
OR direct byte to A
OR indirect RAM to A
OR immediate to A
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
2
1
2
2
2
2
3
1
2
2
2
2
3
1
2
2
2
2
ANL A, direct
ANL A, @Ri
ANL A, #data
ANL direct, A
ANL direct, #data
ORL A, Rn
ORL A, direct
ORL A, @Ri
ORL A, #data
ORL direct, A
ORL direct, #data
XRL A, Rn
OR A to direct byte
OR immediate to direct byte
Exclusive-OR Register to A
Exclusive-OR direct byte to A
Exclusive-OR indirect RAM to A
Exclusive-OR immediate to A
Exclusive-OR A to direct byte
XRL A, direct
XRL A, @Ri
XRL A, #data
XRL direct, A
Rev. 1.0
111
Si1000/1/2/3/4/5
Table 8.1. CIP-51 Instruction Set Summary (Continued)
Mnemonic
Description
Bytes
Clock
Cycles
XRL direct, #data
CLR A
CPL A
RL A
RLC A
RR A
RRC A
SWAP A
Exclusive-OR immediate to direct byte
Clear A
Complement A
Rotate A left
Rotate A left through Carry
Rotate A right
3
1
1
1
1
1
1
1
3
1
1
1
1
1
1
1
Rotate A right through Carry
Swap nibbles of A
Data Transfer
MOV A, Rn
MOV A, direct
MOV A, @Ri
MOV A, #data
MOV Rn, A
Move Register to A
Move direct byte to A
Move indirect RAM to A
Move immediate to A
1
2
1
2
1
2
2
2
2
3
2
3
1
2
2
3
1
1
1
1
1
1
2
2
1
2
1
1
1
2
2
2
1
2
2
2
2
3
2
3
2
2
2
3
3
3
3
3
3
3
2
2
1
2
2
2
Move A to Register
MOV Rn, direct
MOV Rn, #data
MOV direct, A
MOV direct, Rn
MOV direct, direct
MOV direct, @Ri
MOV direct, #data
MOV @Ri, A
MOV @Ri, direct
MOV @Ri, #data
MOV DPTR, #data16
MOVC A, @A+DPTR
MOVC A, @A+PC
MOVX A, @Ri
MOVX @Ri, A
MOVX A, @DPTR
MOVX @DPTR, A
PUSH direct
Move direct byte to Register
Move immediate to Register
Move A to direct byte
Move Register to direct byte
Move direct byte to direct byte
Move indirect RAM to direct byte
Move immediate to direct byte
Move A to indirect RAM
Move direct byte to indirect RAM
Move immediate to indirect RAM
Load DPTR with 16-bit constant
Move code byte relative DPTR to A
Move code byte relative PC to A
Move external data (8-bit address) to A
Move A to external data (8-bit address)
Move external data (16-bit address) to A
Move A to external data (16-bit address)
Push direct byte onto stack
Pop direct byte from stack
POP direct
XCH A, Rn
XCH A, direct
XCH A, @Ri
Exchange Register with A
Exchange direct byte with A
Exchange indirect RAM with A
Exchange low nibble of indirect RAM with A
XCHD A, @Ri
Boolean Manipulation
CLR C
Clear Carry
Clear direct bit
Set Carry
Set direct bit
Complement Carry
Complement direct bit
1
2
1
2
1
2
1
2
1
2
1
2
CLR bit
SETB C
SETB bit
CPL C
CPL bit
112
Rev. 1.0
Si1000/1/2/3/4/5
Table 8.1. CIP-51 Instruction Set Summary (Continued)
Mnemonic
ANL C, bit
ANL C, /bit
ORL C, bit
ORL C, /bit
MOV C, bit
MOV bit, C
JC rel
Description
Bytes
Clock
Cycles
AND direct bit to Carry
AND complement of direct bit to Carry
OR direct bit to carry
OR complement of direct bit to Carry
Move direct bit to Carry
Move Carry to direct bit
2
2
2
2
2
2
2
2
3
3
3
2
2
2
2
2
2
Jump if Carry is set
2/3
2/3
3/4
3/4
3/4
JNC rel
Jump if Carry is not set
Jump if direct bit is set
Jump if direct bit is not set
Jump if direct bit is set and clear bit
JB bit, rel
JNB bit, rel
JBC bit, rel
Program Branching
ACALL addr11
LCALL addr16
RET
Absolute subroutine call
Long subroutine call
Return from subroutine
Return from interrupt
Absolute jump
Long jump
Short jump (relative address)
Jump indirect relative to DPTR
Jump if A equals zero
Jump if A does not equal zero
Compare direct byte to A and jump if not equal
Compare immediate to A and jump if not equal
Compare immediate to Register and jump if not
equal
2
3
1
1
2
3
2
1
2
2
3
3
3
3
4
5
5
3
4
3
3
2/3
2/3
3/4
3/4
3/4
RETI
AJMP addr11
LJMP addr16
SJMP rel
JMP @A+DPTR
JZ rel
JNZ rel
CJNE A, direct, rel
CJNE A, #data, rel
CJNE Rn, #data, rel
CJNE @Ri, #data, rel
Compare immediate to indirect and jump if not
equal
3
4/5
DJNZ Rn, rel
DJNZ direct, rel
NOP
Decrement Register and jump if not zero
Decrement direct byte and jump if not zero
No operation
2
3
1
2/3
3/4
1
Rev. 1.0
113
Si1000/1/2/3/4/5
Notes on Registers, Operands and Addressing Modes:
Rn - Register R0–R7 of the currently selected register bank.
@Ri - Data RAM location addressed indirectly through R0 or R1.
rel - 8-bit, signed (twos complement) offset relative to the first byte of the following instruction. Used by
SJMP and all conditional jumps.
direct - 8-bit internal data location’s address. This could be a direct-access Data RAM location (0x00–
0x7F) or an SFR (0x80–0xFF).
#data - 8-bit constant
#data16 - 16-bit constant
bit - Direct-accessed bit in Data RAM or SFR
addr11 - 11-bit destination address used by ACALL and AJMP. The destination must be within the same
2 kB page of program memory as the first byte of the following instruction.
addr16 - 16-bit destination address used by LCALL and LJMP. The destination may be anywhere within
the 8 kB program memory space.
There is one unused opcode (0xA5) that performs the same function as NOP.
All mnemonics copyrighted © Intel Corporation 1980.
114
Rev. 1.0
Si1000/1/2/3/4/5
8.4. CIP-51 Register Descriptions
Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits
should not be set to logic l. Future product versions may use these bits to implement new features in which
case the reset value of the bit will be logic 0, selecting the feature's default state. Detailed descriptions of
the remaining SFRs are included in the sections of the data sheet associated with their corresponding sys-
tem function.
SFR Definition 8.1. DPL: Data Pointer Low Byte
Bit
7
6
5
4
3
2
1
0
DPL[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Page = All Pages; SFR Address = 0x82
Bit
Name
Function
7:0
DPL[7:0] Data Pointer Low.
The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indi-
rectly addressed Flash memory or XRAM.
SFR Definition 8.2. DPH: Data Pointer High Byte
Bit
7
6
5
4
3
2
1
0
DPH[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Page = All Pages; SFR Address = 0x83
Bit
Name
Function
7:0
DPH[7:0] Data Pointer High.
The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indi-
rectly addressed Flash memory or XRAM.
Rev. 1.0
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Si1000/1/2/3/4/5
SFR Definition 8.3. SP: Stack Pointer
Bit
7
6
5
4
3
2
1
0
SP[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
1
1
1
SFR Page = All Pages; SFR Address = 0x81
Bit
Name
Function
7:0
SP[7:0]
Stack Pointer.
The Stack Pointer holds the location of the top of the stack. The stack pointer is incre-
mented before every PUSH operation. The SP register defaults to 0x07 after reset.
SFR Definition 8.4. ACC: Accumulator
Bit
7
6
5
4
3
2
1
0
ACC[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Page = All Pages; SFR Address = 0xE0; Bit-Addressable
Bit
Name
Function
7:0
ACC[7:0] Accumulator.
This register is the accumulator for arithmetic operations.
SFR Definition 8.5. B: B Register
Bit
7
6
5
4
3
2
1
0
B[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Page = All Pages; SFR Address = 0xF0; Bit-Addressable
Bit
Name
Function
7:0
B[7:0]
B Register.
This register serves as a second accumulator for certain arithmetic operations.
116
Rev. 1.0
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SFR Definition 8.6. PSW: Program Status Word
Bit
7
6
5
4
3
2
1
0
CY
AC
F0
RS[1:0]
R/W
OV
F1
PARITY
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
0
0
SFR Page = All Pages; SFR Address = 0xD0; Bit-Addressable
Bit
Name
Function
7
CY
Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry (addition) or a bor-
row (subtraction). It is cleared to logic 0 by all other arithmetic operations.
6
AC
Auxiliary Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry into (addition) or a
borrow from (subtraction) the high order nibble. It is cleared to logic 0 by all other arith-
metic operations.
5
F0
User Flag 0.
This is a bit-addressable, general purpose flag for use under software control.
4:3
RS[1:0] Register Bank Select.
These bits select which register bank is used during register accesses.
00: Bank 0, Addresses 0x00-0x07
01: Bank 1, Addresses 0x08-0x0F
10: Bank 2, Addresses 0x10-0x17
11: Bank 3, Addresses 0x18-0x1F
2
OV
Overflow Flag.
This bit is set to 1 under the following circumstances:
An ADD, ADDC, or SUBB instruction causes a sign-change overflow.
A MUL instruction results in an overflow (result is greater than 255).
A DIV instruction causes a divide-by-zero condition.
The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all
other cases.
1
0
F1
User Flag 1.
This is a bit-addressable, general purpose flag for use under software control.
PARITY Parity Flag.
This bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared
if the sum is even.
Rev. 1.0
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Si1000/1/2/3/4/5
9. Memory Organization
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are
two separate memory spaces: program memory and data memory. Program and data memory share the
same address space but are accessed via different instruction types. The memory organization of the
Si1000/1/2/3/4/5 device family is shown in Figure 9.1
PROGRAM/DATA MEMORY
(FLASH)
DATA MEMORY
(RAM)
INTERNAL DATA ADDRESS SPACE
Si1000/2
Upper 128 RAM
Special Function
Registers
0x03FF
0x0000
0xFFFF
Scrachpad Memory
(DATA only)
(Indirect Addressing Only) (Direct Addressing Only)
0
F
RESERVED
(Direct and Indirect
Addressing)
0xFC00
0xFBFF
Lower 128 RAM
(Direct and Indirect
Addressing)
64KB FLASH
Bit Addressable
(In-System
Programmable in 1024
Byte Sectors)
General Purpose
Registers
0x0000
EXTERNAL DATA ADDRESS SPACE
0xFFFF
Si1001/3
0x03FF
0x0000
Scrachpad Memory
(DATA only)
Reserved
0x7FFF
0x1000
0x0FFF
32KB FLASH
(In-System
Programmable in 1024
Byte Sectors)
XRAM - 4096 Bytes
(accessable using MOVX
instruction)
0x0000
0x0000
Figure 9.1. Si1000/1/2/3/4/5 Memory Map
118
Rev. 1.0
Si1000/1/2/3/4/5
9.1. Program Memory
The CIP-51 core has a 64 kB program memory space. The Si1000/1/2/3/4/5 implements 64 kB (Si1000/2)
or 32 kB (Si1001/3) of this program memory space as in-system, re-programmable Flash memory, orga-
nized in a contiguous block from addresses 0x0000 to 0xFBFF (Si1000/2) or 0x7FFF (Si1001/3). The
address 0xFBFF (Si1000/2) or 0x7FFF (Si1001/3) serves as the security lock byte for the device. Any
addresses above the lock byte are reserved.
Si1000/2
(SFLE=0)
Si1001/3
(SFLE=0)
0xFFFF
0xFFFF
Reserved Area
0xFC00
0xFBFF
Unpopulated
Address Space
(Reserved)
Lock Byte
0xFBFE
Lock Byte Page
0xF800
0xF7FF
0x8000
0x7FFF
Lock Byte
Si1000/2
Si1001/3
(SFLE=1)
0x7FFE
Lock Byte Page
Flash Memory Space
0x7C00
0x7BFF
0x03FF
0x0000
Flash Memory Space
Scratchpad
(Data Only)
0x0000
0x0000
Figure 9.2. Flash Program Memory Map
9.1.1. MOVX Instruction and Program Memory
The MOVX instruction in an 8051 device is typically used to access external data memory. On the
Si1000/1/2/3/4/5 devices, the MOVX instruction is normally used to read and write on-chip XRAM, but can
be re-configured to write and erase on-chip Flash memory space. MOVC instructions are always used to
read Flash memory, while MOVX write instructions are used to erase and write Flash. This Flash access
feature provides a mechanism for the Si1000/1/2/3/4/5 to update program code and use the program
memory space for non-volatile data storage. Refer to Section “13. Flash Memory” on page 141 for further
details.
9.2. Data Memory
The Si1000/1/2/3/4/5 device family includes 4352 bytes of RAM data memory. 256 bytes of this memory is
mapped into the internal RAM space of the 8051. 4096 bytes of this memory is on-chip “external” memory.
The data memory map is shown in Figure 9.1 for reference.
9.2.1. Internal RAM
There are 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The
lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either
direct or indirect addressing may be used to access the lower 128 bytes of data memory. Locations 0x00
through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight
byte-wide registers. The next 16 bytes, locations 0x20 through 0x2F, may either be addressed as bytes or
as 128 bit locations accessible with the direct addressing mode.
The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the
same address space as the Special Function Registers (SFR) but is physically separate from the SFR
space. The addressing mode used by an instruction when accessing locations above 0x7F determines
whether the CPU accesses the upper 128 bytes of data memory space or the SFRs. Instructions that use
Rev. 1.0
119
Si1000/1/2/3/4/5
direct addressing will access the SFR space. Instructions using indirect addressing above 0x7F access the
upper 128 bytes of data memory. Figure 9.1 illustrates the data memory organization of the
Si1000/1/2/3/4/5.
9.2.1.1. General Purpose Registers
The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of gen-
eral-purpose registers. Each bank consists of eight byte-wide registers designated R0 through R7. Only
one of these banks may be enabled at a time. Two bits in the program status word, RS0 (PSW.3) and RS1
(PSW.4), select the active register bank (see description of the PSW in SFR Definition 8.6). This allows
fast context switching when entering subroutines and interrupt service routines. Indirect addressing modes
use registers R0 and R1 as index registers.
9.2.1.2. Bit Addressable Locations
In addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20
through 0x2F are also accessible as 128 individually addressable bits. Each bit has a bit address from
0x00 to 0x7F. Bit 0 of the byte at 0x20 has bit address 0x00 while bit7 of the byte at 0x20 has bit address
0x07. Bit 7 of the byte at 0x2F has bit address 0x7F. A bit access is distinguished from a full byte access by
the type of instruction used (bit source or destination operands as opposed to a byte source or destina-
tion).
The MCS-51™ assembly language allows an alternate notation for bit addressing of the form XX.B where
XX is the byte address and B is the bit position within the byte. For example, the instruction:
MOV
C, 22.3h
moves the Boolean value at 0x13 (bit 3 of the byte at location 0x22) into the Carry flag.
9.2.1.3. Stack
A programmer's stack can be located anywhere in the 256-byte data memory. The stack area is desig-
nated using the Stack Pointer (SP) SFR. The SP will point to the last location used. The next value pushed
on the stack is placed at SP+1 and then SP is incremented. A reset initializes the stack pointer to location
0x07. Therefore, the first value pushed on the stack is placed at location 0x08, which is also the first regis-
ter (R0) of register bank 1. Thus, if more than one register bank is to be used, the SP should be initialized
to a location in the data memory not being used for data storage. The stack depth can extend up to
256 bytes.
9.2.2. External RAM
There are 4096 bytes of on-chip RAM mapped into the external data memory space. All of these address
locations may be accessed using the external move instruction (MOVX) and the data pointer (DPTR), or
using MOVX indirect addressing mode (such as @R1) in combination with the EMI0CN register.
120
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10. On-Chip XRAM
The Si1000/1/2/3/4/5 MCUs include on-chip RAM mapped into the external data memory space (XRAM).
The external memory space may be accessed using the external move instruction (MOVX) with the target
address specified in either the data pointer (DPTR), or with the target address low byte in R0 or R1 and the
target address high byte in the External Memory Interface Control Register (EMI0CN, shown in SFR Defi-
nition 10.1).
When using the MOVX instruction to access on-chip RAM, no additional initialization is required and the
MOVX instruction execution time is as specified in the CIP-51 chapter.
Important Note: MOVX write operations can be configured to target Flash memory, instead of XRAM. See
Section “13. Flash Memory” on page 141 for more details. The MOVX instruction accesses XRAM by
default.
10.1. Accessing XRAM
The XRAM memory space is accessed using the MOVX instruction. The MOVX instruction has two forms,
both of which use an indirect addressing method. The first method uses the Data Pointer, DPTR, a 16-bit
register which contains the effective address of the XRAM location to be read from or written to. The sec-
ond method uses R0 or R1 in combination with the EMI0CN register to generate the effective XRAM
address. Examples of both of these methods are given below.
10.1.1. 16-Bit MOVX Example
The 16-bit form of the MOVX instruction accesses the memory location pointed to by the contents of the
DPTR register. The following series of instructions reads the value of the byte at address 0x1234 into the
accumulator A:
MOV
MOVX
DPTR, #1234h
A, @DPTR
; load DPTR with 16-bit address to read (0x1234)
; load contents of 0x1234 into accumulator A
The above example uses the 16-bit immediate MOV instruction to set the contents of DPTR. Alternately,
the DPTR can be accessed through the SFR registers DPH, which contains the upper 8-bits of DPTR, and
DPL, which contains the lower 8-bits of DPTR.
10.1.2. 8-Bit MOVX Example
The 8-bit form of the MOVX instruction uses the contents of the EMI0CN SFR to determine the upper 8-bits
of the effective address to be accessed and the contents of R0 or R1 to determine the lower 8-bits of the
effective address to be accessed. The following series of instructions read the contents of the byte at
address 0x1234 into the accumulator A.
MOV
MOV
MOVX
EMI0CN, #12h
R0, #34h
a, @R0
; load high byte of address into EMI0CN
; load low byte of address into R0 (or R1)
; load contents of 0x1234 into accumulator A
Rev. 1.0
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Si1000/1/2/3/4/5
10.2. Special Function Registers
The special function register used for configuring XRAM access is EMI0CN.
SFR Definition 10.1. EMI0CN: External Memory Interface Control
Bit
7
6
5
4
3
2
1
0
PGSEL[3:0]
R/W
Name
Type
Reset
R
0
R
0
R
0
R
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xAA
Bit
7:4
3:0
Name
Unused
PGSEL
Function
Read = 0000b; Write = Don’t Care.
XRAM Page Select.
The EMI0CN register provides the high byte of the 16-bit external data memory
address when using an 8-bit MOVX command, effectively selecting a 256-byte page
of RAM. Since the upper (unused) bits of the register are always zero, EMI0CN deter-
mines which page of XRAM is accessed.
For Example:
If EMI0CN = 0x01, addresses 0x0100 through 0x01FF will be accessed.
If EMI0CN = 0x0F, addresses 0x0F00 through 0x0FFF will be accessed.
122
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11. Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFRs). The SFRs provide control and data exchange with the Si1000/1/2/3/4/5's resources and peripher-
als. The CIP-51 controller core duplicates the SFRs found in a typical 8051 implementation as well as
implementing additional SFRs used to configure and access the sub-systems unique to the
Si1000/1/2/3/4/5. This allows the addition of new functionality while retaining compatibility with the MCS-
51™ instruction set. Table 11.1 and Table 11.2 list the SFRs implemented in the Si1000/1/2/3/4/5 device
family.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations
from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, SCON0, IE, etc.) are bit-
addressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied
addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate
effect and should be avoided. Refer to the corresponding pages of the data sheet, as indicated in
Table 11.3, for a detailed description of each register.
Table 11.1. Special Function Register (SFR) Memory Map (Page 0x0)
F8 SPI0CN
F0
PCA0L
PCA0H PCA0CPL0 PCA0CPH0 PCA0CPL4 PCA0CPH4 VDM0CN
P1MDIN P2MDIN SMB0ADR SMB0ADM EIP1 EIP2
B
P0MDIN
E8 ADC0CN PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2 PCA0CPL3 PCA0CPH3 RSTSRC
E0 ACC XBR0 XBR1 XBR2 IT01CF EIE1 EIE2
D8 PCA0CN PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2 PCA0CPM3 PCA0CPM4 PCA0PWM
D0 PSW
C8 TMR2CN REG0CN TMR2RLL TMR2RLH
C0 SMB0CN SMB0CF SMB0DAT ADC0GTL ADC0GTH
B8 IP IREF0CN ADC0AC ADC0MX ADC0CF
B0 SPI1CN OSCXCN OSCICN OSCICL
REF0CN PCA0CPL5 PCA0CPH5 P0SKIP
P1SKIP
TMR2H
P2SKIP
PCA0CPM5
ADC0LTH
ADC0H
P0MAT
P1MAT
TMR2L
ADC0LTL
ADC0L
P0MASK
P1MASK
FLKEY
PMU0CF
FLSCL
A8
A0
IE
CLKSEL
EMI0CN
Reserved RTC0ADR RTC0DAT
RTC0KEY
Reserved
P2
SPI0CFG SPI0CKR SPI0DAT P0MDOUT P1MDOUT
P2MDOUT SFRPAGE
98 SCON0
90 P1
88 TCON
SBUF0
CPT1CN
CPT0CN
CPT1MD
TMR3L
TH0
CPT0MD
TMR3H
TH1
CPT1MX
DC0CF
CKCON
SPI1DAT
6(E)
CPT0MX
DC0CN
PSCTL
PCON
7(F)
TMR3CN TMR3RLL TMR3RLH
TMOD
SP
TL0
DPL
2(A)
TL1
DPH
3(B)
80
P0
SPI1CFG
4(C)
SPI1CKR
5(D)
0(8)
1(9)
(bit addressable)
Rev. 1.0
123
Si1000/1/2/3/4/5
11.1. SFR Paging
To accommodate more than 128 SFRs in the 0x80 to 0xFF address space, SFR paging has been imple-
mented. By default, all SFR accesses target SFR Page 0x0 to allow access to the registers listed in
Table 11.1. During device initialization, some SFRs located on SFR Page 0xF may need to be accessed.
Table 11.2 lists the SFRs accessible from SFR Page 0x0F. Some SFRs are accessible from both pages,
including the SFRPAGE register. SFRs accessible only from Page 0xF are in bold.
The following procedure should be used when accessing SFRs from Page 0xF:
1. Save the current interrupt state (EA_save = EA).
2. Disable Interrupts (EA = 0).
3. Set SFRPAGE = 0xF.
4. Access the SFRs located on SFR Page 0xF.
5. Set SFRPAGE = 0x0.
6. Restore interrupt state (EA = EA_save).
Table 11.2. Special Function Register (SFR) Memory Map (Page 0xF)
F8
F0
E8
B
EIP1
EIE1
EIP2
EIE2
E0 ACC
D8
D0 PSW
C8
C0
B8
B0
ADC0PWR
ADC0TK
P1DRV
A8
A0
98
90
88
80
IE
CLKSEL
P2
P0DRV
P2DRV
SFRPAGE
P1
CRC0DAT CRC0CN
CRC0IN
CRC0FLIP CRC0AUTO CRC0CNT
P0
SP
DPL
2(A)
DPH
3(B)
TOFFL
TOFFH
PCON
7(F)
0(8)
1(9)
4(C)
5(D)
6(E)
(bit addressable)
124
Rev. 1.0
Si1000/1/2/3/4/5
SFR Definition 11.1. SFRPage: SFR Page
Bit
7
6
5
4
3
2
1
0
SFRPAGE[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Page = All Pages; SFR Address = 0xA7
Bit Name
7:0 SFRPAGE[7:0] SFR Page.
Function
Specifies the SFR Page used when reading, writing, or modifying special function
registers.
Table 11.3. Special Function Registers
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
Address SFR Page
Description
Page
ACC
0xE0
0xBA
0xBC
0xE8
0xC4
0xC3
0xBE
0xBD
0xC6
0xC5
0xBB
0xBA
0xBD
0xF0
0x8E
0xA9
0x9B
0x9D
0x9F
0x9A
0x9C
0x9E
0x96
0x92
0x97
0x91
0x95
All
Accumulator
ADC0 Accumulator Configuration
ADC0 Configuration
116
83
82
81
87
87
86
86
88
88
91
84
85
116
331
187
103
103
107
104
105
108
163
161
163
162
164
ADC0AC
ADC0CF
ADC0CN
ADC0GTH
ADC0GTL
ADC0H
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0xF
0xF
All
ADC0 Control
ADC0 Greater-Than Compare High
ADC0 Greater-Than Compare Low
ADC0 High
ADC0L
ADC0 Low
ADC0LTH
ADC0LTL
ADC0MX
ADC0PWR
ADC0TK
B
ADC0 Less-Than Compare Word High
ADC0 Less-Than Compare Word Low
AMUX0 Channel Select
ADC0 Burst Mode Power-Up Time
ADC0 Tracking Control
B Register
Clock Control
Clock Select
Comparator0 Control
Comparator0 Mode Selection
Comparator0 Mux Selection
Comparator1 Control
Comparator1 Mode Selection
Comparator1 Mux Selection
CRC0 Automatic Control
CRC0 Control
CRC0 Automatic Flash Sector Count
CRC0 Data
CRC0 Flip
CKCON
0x0
All
CLKSEL
CPT0CN
CPT0MD
CPT0MX
CPT1CN
CPT1MD
CPT1MX
CRC0AUTO
CRC0CN
CRC0CNT
CRC0DAT
CRC0FLIP
0x0
0x0
0x0
0x0
0x0
0x0
0xF
0xF
0xF
0xF
0xF
Rev. 1.0
125
Si1000/1/2/3/4/5
Table 11.3. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
CRC0IN
DC0CF
Address SFR Page
Description
Page
162
0x93
0x96
0xF
0x0
CRC0 Input
DC0 (DC-DC Converter) Configuration
DC0 (DC-DC Converter) Control
172
DC0CN
0x97
0x0
171
DPH
DPL
EIE1
EIE2
EIP1
EIP2
EMI0CN
FLKEY
FLSCL
IE
0x83
0x82
0xE6
0xE7
0xF6
0xF7
0xAA
0xB7
0xB6
0xA8
0xB8
0xB9
0xE4
0xB3
0xB2
0xB1
0x80
0xA4
0xC7
0xD7
0xF1
0xA4
0xD4
0x90
0xA5
0xBF
0xCF
0xF2
0xA5
0xD5
0xA0
0xA6
0xF3
0xA6
0xD6
0xD8
0xFC
0xEA
0xEC
0xEE
0xFE
All
All
All
Data Pointer High
Data Pointer Low
115
115
135
137
136
138
122
149
149
133
134
98
140
188
188
189
220
222
217
217
221
221
220
223
225
218
218
224
224
223
225
227
226
227
226
365
370
370
370
370
370
Extended Interrupt Enable 1
Extended Interrupt Enable 2
Extended Interrupt Priority 1
Extended Interrupt Priority 2
EMIF Control
Flash Lock And Key
Flash Scale
Interrupt Enable
All
0x0
0x0
0x0
0x0
0x0
All
0x0
0x0
0x0
0x0
0x0
0x0
All
0xF
0x0
0x0
0x0
0x0
0x0
All
0xF
0x0
0x0
0x0
0x0
0x0
All
IP
Interrupt Priority
IREF0CN
IT01CF
OSCICL
OSCICN
OSCXCN
P0
P0DRV
P0MASK
P0MAT
P0MDIN
P0MDOUT
P0SKIP
P1
P1DRV
P1MASK
P1MAT
P1MDIN
P1MDOUT
P1SKIP
P2
P2DRV
P2MDIN
P2MDOUT
P2SKIP
PCA0CN
PCA0CPH0
PCA0CPH1
PCA0CPH2
PCA0CPH3
PCA0CPH4
Current Reference IREF Control
INT0/INT1 Configuration
Internal Oscillator Calibration
Internal Oscillator Control
External Oscillator Control
Port 0 Latch
Port 0 Drive Strength
Port 0 Mask
Port 0 Match
Port 0 Input Mode Configuration
Port 0 Output Mode Configuration
Port 0 Skip
Port 1 Latch
Port 1 Drive Strength
Port 1 Mask
Port 1 Match
Port 1 Input Mode Configuration
Port 1 Output Mode Configuration
Port 1 Skip
Port 2 Latch
0xF
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Port 2 Drive Strength
Port 2 Input Mode Configuration
Port 2 Output Mode Configuration
Port 2 Skip
PCA0 Control
PCA0 Capture 0 High
PCA0 Capture 1 High
PCA0 Capture 2 High
PCA0 Capture 3 High
PCA0 Capture 4 High
126
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Table 11.3. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
Address SFR Page
Description
Page
PCA0CPH5
PCA0CPL0
PCA0CPL1
PCA0CPL2
PCA0CPL3
PCA0CPL4
PCA0CPL5
PCA0CPM0
PCA0CPM1
PCA0CPM2
PCA0CPM3
PCA0CPM4
PCA0CPM5
PCA0H
0xD3
0xFB
0xE9
0xEB
0xED
0xFD
0xD2
0xDA
0xDB
0xDC
0xDD
0xDE
0xCE
0xFA
0xF9
0xD9
0xDF
0x87
0xB5
0x8F
0xD0
0xD1
0xC9
0xEF
0xAC
0xAD
0xAE
0x99
0x98
0xA7
0xF5
0xF4
0xC1
0xC0
0xC2
0x81
0xA1
0xA2
0xF8
0xA3
0x84
0x85
0xB0
0x86
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
All
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
All
0x0
0x0
0x0
0x0
0x0
All
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
PCA0 Capture 5 High
PCA0 Capture 0 Low
PCA0 Capture 1 Low
PCA0 Capture 2 Low
PCA0 Capture 3 Low
PCA0 Capture 4 Low
PCA0 Capture 5 Low
PCA0 Module 0 Mode Register
PCA0 Module 1 Mode Register
PCA0 Module 2 Mode Register
PCA0 Module 3 Mode Register
PCA0 Module 4 Mode Register
PCA0 Module 5 Mode Register
PCA0 Counter High
PCA0 Counter Low
PCA0 Mode
370
370
370
370
370
370
370
368
368
368
368
368
368
369
369
366
367
157
156
148
117
97
174
181
195
196
194
315
314
125
298
298
293
295
301
116
324
326
325
326
324
326
325
326
PCA0L
PCA0MD
PCA0PWM
PCON
PMU0CF
PSCTL
PCA0 PWM Configuration
Power Control
PMU0 Configuration
Program Store R/W Control
Program Status Word
Voltage Reference Control
Voltage Regulator (VREG0) Control
Reset Source Configuration/Status
RTC0 Address
RTC0 Data
RTC0 Key
UART0 Data Buffer
UART0 Control
SFR Page
SMBus Slave Address Mask
SMBus Slave Address
SMBus0 Configuration
SMBus0 Control
SMBus0 Data
Stack Pointer
SPI0 Configuration
SPI0 Clock Rate Control
SPI0 Control
SPI0 Data
SPI1 Configuration
PSW
REF0CN
REG0CN
RSTSRC
RTC0ADR
RTC0DAT
RTC0KEY
SBUF0
SCON0
SFRPAGE
SMB0ADM
SMB0ADR
SMB0CF
SMB0CN
SMB0DAT
SP
SPI0CFG
SPI0CKR
SPI0CN
SPI0DAT
SPI1CFG
SPI1CKR
SPI1CN
SPI1 Clock Rate Control
SPI1 Control
SPI1 Data
SPI1DAT
Rev. 1.0
127
Si1000/1/2/3/4/5
Table 11.3. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
Address SFR Page
Description
Page
TCON
TH0
TH1
TL0
TL1
TMOD
TMR2CN
TMR2H
TMR2L
TMR2RLH
TMR2RLL
TMR3CN
TMR3H
TMR3L
TMR3RLH
TMR3RLL
TOFFH
TOFFL
VDM0CN
XBR0
0x88
0x8C
0x8D
0x8A
0x8B
0x89
0xC8
0xCD
0xCC
0xCB
0xCA
0x91
0x95
0x94
0x93
0x92
0x86
0x85
0xFF
0xE1
0xE2
0xE3
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0xF
0xF
0x0
0x0
0x0
0x0
Timer/Counter Control
Timer/Counter 0 High
Timer/Counter 1 High
Timer/Counter 0 Low
Timer/Counter 1 Low
Timer/Counter Mode
Timer/Counter 2 Control
Timer/Counter 2 High
Timer/Counter 2 Low
Timer/Counter 2 Reload High
Timer/Counter 2 Reload Low
Timer/Counter 3 Control
Timer/Counter 3 High
336
339
339
338
338
337
343
345
345
344
344
349
351
351
350
350
94
Timer/Counter 3 Low
Timer/Counter 3 Reload High
Timer/Counter 3 Reload Low
Temperature Offset High
Temperature Offset Low
VDD Monitor Control
Port I/O Crossbar Control 0
Port I/O Crossbar Control 1
Port I/O Crossbar Control 2
94
179
214
215
216
XBR1
XBR2
128
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12. Interrupt Handler
The Si1000/1/2/3/4/5 microcontroller family includes an extended interrupt system supporting multiple
interrupt sources and two priority levels. The allocation of interrupt sources between on-chip peripherals
and external input pins varies according to the specific version of the device. Refer to Table 12.1, “Interrupt
Summary,” on page 131 for a detailed listing of all interrupt sources supported by the device. Refer to the
data sheet section associated with a particular on-chip peripheral for information regarding valid interrupt
conditions for the peripheral and the behavior of its interrupt-pending flag(s).
Each interrupt source has one or more associated interrupt-pending flag(s) located in an SFR or an indi-
rect register. When a peripheral or external source meets a valid interrupt condition, the associated inter-
rupt-pending flag is set to logic 1. If both global interrupts and the specific interrupt source is enabled, a
CPU interrupt request is generated when the interrupt-pending flag is set.
As soon as execution of the current instruction is complete, the CPU generates an LCALL to a predeter-
mined address to begin execution of an interrupt service routine (ISR). Each ISR must end with an RETI
instruction, which returns program execution to the next instruction that would have been executed if the
interrupt request had not occurred. If interrupts are not enabled, the interrupt-pending flag is ignored by the
hardware and program execution continues as normal. (The interrupt-pending flag is set to logic 1 regard-
less of the interrupt's enable/disable state.)
Some interrupt-pending flags are automatically cleared by hardware when the CPU vectors to the ISR.
However, most are not cleared by the hardware and must be cleared by software before returning from the
ISR. If an interrupt-pending flag remains set after the CPU completes the return-from-interrupt (RETI)
instruction, a new interrupt request will be generated immediately and the CPU will re-enter the ISR after
the completion of the next instruction.
12.1. Enabling Interrupt Sources
Each interrupt source can be individually enabled or disabled through the use of an associated interrupt
enable bit in the Interrupt Enable and Extended Interrupt Enable SFRs. However, interrupts must first be
globally enabled by setting the EA bit (IE.7) to logic 1 before the individual interrupt enables are recog-
nized. Setting the EA bit to logic 0 disables all interrupt sources regardless of the individual interrupt-
enable settings. Note that interrupts which occur when the EA bit is set to logic 0 will be held in a pending
state, and will not be serviced until the EA bit is set back to logic 1.
12.2. MCU Interrupt Sources and Vectors
The CPU services interrupts by generating an LCALL to a predetermined address (the interrupt vector
address) to begin execution of an interrupt service routine (ISR). The interrupt vector addresses associ-
ated with each interrupt source are listed in Table 12.1 on page 131. Software should ensure that the inter-
rupt vector for each enabled interrupt source contains a valid interrupt service routine.
Software can simulate an interrupt by setting any interrupt-pending flag to logic 1. If interrupts are enabled
for the flag, an interrupt request will be generated and the CPU will vector to the ISR address associated
with the interrupt-pending flag.
Rev. 1.0
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12.3. Interrupt Priorities
Each interrupt source can be individually programmed to one of two priority levels: low or high. A low prior-
ity interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be
preempted. If a high priority interrupt preempts a low priority interrupt, the low priority interrupt will finish
execution after the high priority interrupt completes. Each interrupt has an associated interrupt priority bit in
in the Interrupt Priority and Extended Interrupt Priority registers used to configure its priority level. Low pri-
ority is the default.
If two interrupts are recognized simultaneously, the interrupt with the higher priority is serviced first. If both
interrupts have the same priority level, a fixed priority order is used to arbitrate. See Table 12.1 on
page 131 to determine the fixed priority order used to arbitrate between simultaneously recognized inter-
rupts.
12.4. Interrupt Latency
Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are
sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is 7
system clock cycles: 1 clock cycle to detect the interrupt, 1 clock cycle to execute a single instruction, and
5 clock cycles to complete the LCALL to the ISR. If an interrupt is pending when a RETI is executed, a sin-
gle instruction is executed before an LCALL is made to service the pending interrupt. Therefore, the maxi-
mum response time for an interrupt (when no other interrupt is currently being serviced or the new interrupt
is of greater priority) occurs when the CPU is performing an RETI instruction followed by a DIV as the next
instruction. In this case, the response time is 19 system clock cycles: 1 clock cycle to detect the interrupt,
5 clock cycles to execute the RETI, 8 clock cycles to complete the DIV instruction and 5 clock cycles to
execute the LCALL to the ISR. If the CPU is executing an ISR for an interrupt with equal or higher priority,
the new interrupt will not be serviced until the current ISR completes, including the RETI and following
instruction.
130
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Table 12.1. Interrupt Summary
Pending Flag
Interrupt Source
Enable
Flag
Priority
Control
Reset
0x0000 Top
None
N/A N/A Always
Enabled
Always
Highest
External Interrupt 0 (INT0) 0x0003
0
1
2
3
4
IE0 (TCON.1)
TF0 (TCON.5)
IE1 (TCON.3)
TF1 (TCON.7)
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
EX0 (IE.0) PX0 (IP.0)
ET0 (IE.1) PT0 (IP.1)
EX1 (IE.2) PX1 (IP.2)
ET1 (IE.3) PT1 (IP.3)
ES0 (IE.4) PS0 (IP.4)
Timer 0 Overflow
0x000B
External Interrupt 1 (INT1) 0x0013
Timer 1 Overflow
UART0
0x001B
0x0023
RI0 (SCON0.0)
TI0 (SCON0.1)
Timer 2 Overflow
SPI0
0x002B
0x0033
5
6
TF2H (TMR2CN.7)
TF2L (TMR2CN.6)
Y
Y
N
N
ET2 (IE.5) PT2 (IP.5)
SPIF (SPI0CN.7)
WCOL (SPI0CN.6)
MODF (SPI0CN.5)
RXOVRN (SPI0CN.4)
ESPI0
(IE.6)
PSPI0
(IP.6)
SMB0
0x003B
0x0043
0x004B
7
8
9
SI (SMB0CN.0)
Y
N
Y
N
N
N
N
N
N
N
N
ESMB0
(EIE1.0)
PSMB0
(EIP1.0)
SmaRTClock Alarm
ALRM (RTC0CN.2)*
EARTC0
(EIE1.1)
PARTC0
(EIP1.1)
ADC0 Window
Comparator
AD0WINT
(ADC0CN.3)
EWADC0 PWADC0
(EIE1.2)
(EIP1.2)
ADC0 End of Conversion 0x0053 10
AD0INT (ADC0STA.5) Y
EADC0
(EIE1.3)
PADC0
(EIP1.3)
Programmable Counter
Array
0x005B 11
0x0063 12
0x006B 13
0x0073 14
0x007B 15
0x0083 16
CF (PCA0CN.7)
CCFn (PCA0CN.n)
Y
N
N
N
EPCA0
(EIE1.4)
PPCA0
(EIP1.4)
Comparator0
CP0FIF (CPT0CN.4)
CP0RIF (CPT0CN.5)
ECP0
(EIE1.5)
PCP0
(EIP1.5)
Comparator1
CP1FIF (CPT1CN.4)
CP1RIF (CPT1CN.5)
ECP1
(EIE1.6)
PCP1
(EIP1.6)
Timer 3 Overflow
TF3H (TMR3CN.7)
TF3L (TMR3CN.6)
ET3
(EIE1.7)
PT3
(EIP1.7)
VDD_MCU Supply
Monitor Early Warning
VDDOK
(VDM0CN.5)
EWARN
(EIE2.0)
PWARN
(EIP2.0)
1
Port Match
None
EMAT
PMAT
(EIE2.1)
(EIP2.1)
Rev. 1.0
131
Si1000/1/2/3/4/5
Table 12.1. Interrupt Summary (Continued)
Interrupt Source
Pending Flag
Enable
Flag
Priority
Control
SmaRTClock Oscillator
Fail
0x008B 17
0x0093 18
OSCFAIL
(RTC0CN.5)
N
N
N
N
ERTC0F
(EIE2.2)
PFRTC0F
(EIP2.2)
2
EZRadioPRO Serial
Interface (SPI1)
SPIF (SPI1CN.7)
WCOL (SPI1CN.6)
MODF (SPI1CN.5)
RXOVRN (SPI1CN.4)
ESPI1
(EIE2.3)
PSPI1
(EIP2.3)
Notes:
1. Indicates a read-only interrupt pending flag. The interrupt enable may be used to prevent software from
vectoring to the associated interrupt service routine.
2. Indicates a register located in an indirect memory space.
12.5. Interrupt Register Descriptions
The SFRs used to enable the interrupt sources and set their priority level are described in the following
register descriptions. Refer to the data sheet section associated with a particular on-chip peripheral for
information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending
flag(s).
132
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SFR Definition 12.1. IE: Interrupt Enable
Bit
7
6
5
4
3
2
1
0
EA
ESPI0
ET2
ES0
ET1
EX1
ET0
EX0
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Page = All Pages; SFR Address = 0xA8; Bit-Addressable
Bit
Name
Function
7
EA
Enable All Interrupts.
Globally enables/disables all interrupts. It overrides individual interrupt mask settings.
0: Disable all interrupt sources.
1: Enable each interrupt according to its individual mask setting.
6
5
4
3
2
1
0
ESPI0 Enable Serial Peripheral Interface (SPI0) Interrupt.
This bit sets the masking of the SPI0 interrupts.
0: Disable all SPI0 interrupts.
1: Enable interrupt requests generated by SPI0.
ET2
ES0
ET1
EX1
ET0
EX0
Enable Timer 2 Interrupt.
This bit sets the masking of the Timer 2 interrupt.
0: Disable Timer 2 interrupt.
1: Enable interrupt requests generated by the TF2L or TF2H flags.
Enable UART0 Interrupt.
This bit sets the masking of the UART0 interrupt.
0: Disable UART0 interrupt.
1: Enable UART0 interrupt.
Enable Timer 1 Interrupt.
This bit sets the masking of the Timer 1 interrupt.
0: Disable all Timer 1 interrupt.
1: Enable interrupt requests generated by the TF1 flag.
Enable External Interrupt 1.
This bit sets the masking of External Interrupt 1.
0: Disable external interrupt 1.
1: Enable interrupt requests generated by the INT1 input.
Enable Timer 0 Interrupt.
This bit sets the masking of the Timer 0 interrupt.
0: Disable all Timer 0 interrupt.
1: Enable interrupt requests generated by the TF0 flag.
Enable External Interrupt 0.
This bit sets the masking of External Interrupt 0.
0: Disable external interrupt 0.
1: Enable interrupt requests generated by the INT0 input.
Rev. 1.0
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SFR Definition 12.2. IP: Interrupt Priority
Bit
7
6
5
4
3
2
1
0
PSPI0
PT2
PS0
PT1
PX1
PT0
PX0
Name
Type
Reset
R
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Page = 0x0; SFR Address = 0xB8; Bit-Addressable
Bit
Name
Function
7
6
Unused Read = 1b, Write = don't care.
PSPI0
PT2
PS0
PT1
PX1
PT0
PX0
Serial Peripheral Interface (SPI0) Interrupt Priority Control.
This bit sets the priority of the SPI0 interrupt.
0: SPI0 interrupt set to low priority level.
1: SPI0 interrupt set to high priority level.
5
4
3
2
1
0
Timer 2 Interrupt Priority Control.
This bit sets the priority of the Timer 2 interrupt.
0: Timer 2 interrupt set to low priority level.
1: Timer 2 interrupt set to high priority level.
UART0 Interrupt Priority Control.
This bit sets the priority of the UART0 interrupt.
0: UART0 interrupt set to low priority level.
1: UART0 interrupt set to high priority level.
Timer 1 Interrupt Priority Control.
This bit sets the priority of the Timer 1 interrupt.
0: Timer 1 interrupt set to low priority level.
1: Timer 1 interrupt set to high priority level.
External Interrupt 1 Priority Control.
This bit sets the priority of the External Interrupt 1 interrupt.
0: External Interrupt 1 set to low priority level.
1: External Interrupt 1 set to high priority level.
Timer 0 Interrupt Priority Control.
This bit sets the priority of the Timer 0 interrupt.
0: Timer 0 interrupt set to low priority level.
1: Timer 0 interrupt set to high priority level.
External Interrupt 0 Priority Control.
This bit sets the priority of the External Interrupt 0 interrupt.
0: External Interrupt 0 set to low priority level.
1: External Interrupt 0 set to high priority level.
134
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SFR Definition 12.3. EIE1: Extended Interrupt Enable 1
Bit
7
6
5
4
3
2
1
0
ET3
ECP1
ECP0
EPCA0
EADC0
EWADC0 ERTC0A
ESMB0
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Page = All Pages; SFR Address = 0xE6
Bit
Name
Function
7
ET3
Enable Timer 3 Interrupt.
This bit sets the masking of the Timer 3 interrupt.
0: Disable Timer 3 interrupts.
1: Enable interrupt requests generated by the TF3L or TF3H flags.
6
5
4
3
2
1
0
ECP1
ECP0
Enable Comparator1 (CP1) Interrupt.
This bit sets the masking of the CP1 interrupt.
0: Disable CP1 interrupts.
1: Enable interrupt requests generated by the CP1RIF or CP1FIF flags.
Enable Comparator0 (CP0) Interrupt.
This bit sets the masking of the CP0 interrupt.
0: Disable CP0 interrupts.
1: Enable interrupt requests generated by the CP0RIF or CP0FIF flags.
EPCA0 Enable Programmable Counter Array (PCA0) Interrupt.
This bit sets the masking of the PCA0 interrupts.
0: Disable all PCA0 interrupts.
1: Enable interrupt requests generated by PCA0.
EADC0 Enable ADC0 Conversion Complete Interrupt.
This bit sets the masking of the ADC0 Conversion Complete interrupt.
0: Disable ADC0 Conversion Complete interrupt.
1: Enable interrupt requests generated by the AD0INT flag.
EWADC0 Enable Window Comparison ADC0 Interrupt.
This bit sets the masking of ADC0 Window Comparison interrupt.
0: Disable ADC0 Window Comparison interrupt.
1: Enable interrupt requests generated by ADC0 Window Compare flag (AD0WINT).
ERTC0A Enable SmaRTClock Alarm Interrupts.
This bit sets the masking of the SmaRTClock Alarm interrupt.
0: Disable SmaRTClock Alarm interrupts.
1: Enable interrupt requests generated by a SmaRTClock Alarm.
ESMB0 Enable SMBus (SMB0) Interrupt.
This bit sets the masking of the SMB0 interrupt.
0: Disable all SMB0 interrupts.
1: Enable interrupt requests generated by SMB0.
Rev. 1.0
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SFR Definition 12.4. EIP1: Extended Interrupt Priority 1
Bit
7
6
5
4
3
2
1
0
PT3
PCP1
PCP0
PPCA0
PADC0
PWADC0 PRTC0A
PSMB0
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Page = All Pages; SFR Address = 0xF6
Bit
Name
Function
7
PT3
Timer 3 Interrupt Priority Control.
This bit sets the priority of the Timer 3 interrupt.
0: Timer 3 interrupts set to low priority level.
1: Timer 3 interrupts set to high priority level.
6
5
4
3
2
1
0
PCP1
PCP0
Comparator1 (CP1) Interrupt Priority Control.
This bit sets the priority of the CP1 interrupt.
0: CP1 interrupt set to low priority level.
1: CP1 interrupt set to high priority level.
Comparator0 (CP0) Interrupt Priority Control.
This bit sets the priority of the CP0 interrupt.
0: CP0 interrupt set to low priority level.
1: CP0 interrupt set to high priority level.
PPCA0 Programmable Counter Array (PCA0) Interrupt Priority Control.
This bit sets the priority of the PCA0 interrupt.
0: PCA0 interrupt set to low priority level.
1: PCA0 interrupt set to high priority level.
PADC0 ADC0 Conversion Complete Interrupt Priority Control.
This bit sets the priority of the ADC0 Conversion Complete interrupt.
0: ADC0 Conversion Complete interrupt set to low priority level.
1: ADC0 Conversion Complete interrupt set to high priority level.
PWADC0 ADC0 Window Comparator Interrupt Priority Control.
This bit sets the priority of the ADC0 Window interrupt.
0: ADC0 Window interrupt set to low priority level.
1: ADC0 Window interrupt set to high priority level.
PRTC0A SmaRTClock Alarm Interrupt Priority Control.
This bit sets the priority of the SmaRTClock Alarm interrupt.
0: SmaRTClock Alarm interrupt set to low priority level.
1: SmaRTClock Alarm interrupt set to high priority level.
PSMB0 SMBus (SMB0) Interrupt Priority Control.
This bit sets the priority of the SMB0 interrupt.
0: SMB0 interrupt set to low priority level.
1: SMB0 interrupt set to high priority level.
136
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SFR Definition 12.5. EIE2: Extended Interrupt Enable 2
Bit
7
6
5
4
3
2
1
0
ESPI1
ERTC0F
EMAT
EWARN
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Page = All Pages;SFR Address = 0xE7
Bit
7:4
3
Name
Function
Read = 0000b. Write = Don’t care.
Unused
ESPI1 Enable Serial Peripheral Interface (SPI1) Interrupt.
This bit sets the masking of the SPI1 interrupts.
0: Disable all SPI1 interrupts.
1: Enable interrupt requests generated by SPI1.
2
1
0
ERTC0F Enable SmaRTClock Oscillator Fail Interrupt.
This bit sets the masking of the SmaRTClock Alarm interrupt.
0: Disable SmaRTClock Alarm interrupts.
1: Enable interrupt requests generated by SmaRTClock Alarm.
EMAT Enable Port Match Interrupts.
This bit sets the masking of the Port Match Event interrupt.
0: Disable all Port Match interrupts.
1: Enable interrupt requests generated by a Port Match.
EWARN Enable VDD_MCU Supply Monitor Early Warning Interrupt.
This bit sets the masking of the VDD_MCU Supply Monitor Early Warning interrupt.
0: Disable the VDD_MCU Supply Monitor Early Warning interrupt.
1: Enable interrupt requests generated by VDD_MCU Supply Monitor.
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SFR Definition 12.6. EIP2: Extended Interrupt Priority 2
Bit
7
6
5
4
3
2
1
0
PSPI1
PRTC0F
PMAT
PWARN
Name
Type
Reset
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Page = All Pages; SFR Address = 0xF7
Bit
7:4
3
Name
Function
Unused
Read = 0000b. Write = Don’t care.
PSPI1 Serial Peripheral Interface (SPI1) Interrupt Priority Control.
This bit sets the priority of the SPI1 interrupt.
0: SP1 interrupt set to low priority level.
1: SPI1 interrupt set to high priority level.
2
1
0
PRTC0F SmaRTClock Oscillator Fail Interrupt Priority Control.
This bit sets the priority of the SmaRTClock Alarm interrupt.
0: SmaRTClock Alarm interrupt set to low priority level.
1: SmaRTClock Alarm interrupt set to high priority level.
PMAT Port Match Interrupt Priority Control.
This bit sets the priority of the Port Match Event interrupt.
0: Port Match interrupt set to low priority level.
1: Port Match interrupt set to high priority level.
PWARN VDD_MCU Supply Monitor Early Warning Interrupt Priority Control.
This bit sets the priority of the VDD_MCU Supply Monitor Early Warning interrupt.
0: VDD_MCU Supply Monitor Early Warning interrupt set to low priority level.
1: VDD_MCU Supply Monitor Early Warning interrupt set to high priority level.
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12.6. External Interrupts INT0 and INT1
The INT0 and INT1 external interrupt sources are configurable as active high or low, edge or level sensi-
tive. The IN0PL (INT0 Polarity) and IN1PL (INT1 Polarity) bits in the IT01CF register select active high or
active low; the IT0 and IT1 bits in TCON (Section “27.1. Timer 0 and Timer 1” on page 332) select level or
edge sensitive. The table below lists the possible configurations.
IT0
IN0PL
INT0 Interrupt
IT1
IN1PL
INT1 Interrupt
1
1
0
0
0
1
0
1
Active low, edge sensitive
Active high, edge sensitive
Active low, level sensitive
Active high, level sensitive
1
1
0
0
0
1
0
1
Active low, edge sensitive
Active high, edge sensitive
Active low, level sensitive
Active high, level sensitive
INT0 and INT1 are assigned to Port pins as defined in the IT01CF register (see SFR Definition 12.7). Note
that INT0 and INT0 Port pin assignments are independent of any Crossbar assignments. INT0 and INT1
will monitor their assigned Port pins without disturbing the peripheral that was assigned the Port pin via the
Crossbar. To assign a Port pin only to INT0 and/or INT1, configure the Crossbar to skip the selected pin(s).
This is accomplished by setting the associated bit in register XBR0 (see Section “21.3. Priority Crossbar
Decoder” on page 211 for complete details on configuring the Crossbar).
IE0 (TCON.1) and IE1 (TCON.3) serve as the interrupt-pending flags for the INT0 and INT1 external inter-
rupts, respectively. If an INT0 or INT1 external interrupt is configured as edge-sensitive, the corresponding
interrupt-pending flag is automatically cleared by the hardware when the CPU vectors to the ISR. When
configured as level sensitive, the interrupt-pending flag remains logic 1 while the input is active as defined
by the corresponding polarity bit (IN0PL or IN1PL); the flag remains logic 0 while the input is inactive. The
external interrupt source must hold the input active until the interrupt request is recognized. It must then
deactivate the interrupt request before execution of the ISR completes or another interrupt request will be
generated.
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SFR Definition 12.7. IT01CF: INT0/INT1 Configuration
Bit
7
6
5
4
3
2
1
0
IN1PL
IN1SL[2:0]
IN0PL
IN0SL[2:0]
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
0
0
0
1
SFR Page = 0x0; SFR Address = 0xE4
Bit
Name
Function
7
IN1PL
INT1 Polarity.
0: INT1 input is active low.
1: INT1 input is active high.
6:4 IN1SL[2:0] INT1 Port Pin Selection Bits.
These bits select which Port pin is assigned to INT1. Note that this pin assignment is
independent of the Crossbar; INT1 will monitor the assigned Port pin without disturb-
ing the peripheral that has been assigned the Port pin via the Crossbar. The Crossbar
will not assign the Port pin to a peripheral if it is configured to skip the selected pin.
000: Select P0.0
001: Select P0.1
010: Select P0.2
011: Select P0.3
100: Select P0.4
101: Select P0.5
110: Select P0.6
111: Select P0.7
3
IN0PL
INT0 Polarity.
0: INT0 input is active low.
1: INT0 input is active high.
2:0 IN0SL[2:0] INT0 Port Pin Selection Bits.
These bits select which Port pin is assigned to INT0. Note that this pin assignment is
independent of the Crossbar; INT0 will monitor the assigned Port pin without disturb-
ing the peripheral that has been assigned the Port pin via the Crossbar. The Crossbar
will not assign the Port pin to a peripheral if it is configured to skip the selected pin.
000: Select P0.0
001: Select P0.1
010: Select P0.2
011: Select P0.3
100: Select P0.4
101: Select P0.5
110: Select P0.6
111: Select P0.7
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13. Flash Memory
On-chip, re-programmable Flash memory is included for program code and non-volatile data storage. The
Flash memory can be programmed in-system through the C2 interface or by software using the MOVX
write instruction. Once cleared to logic 0, a Flash bit must be erased to set it back to logic 1. Flash bytes
would typically be erased (set to 0xFF) before being reprogrammed. The write and erase operations are
automatically timed by hardware for proper execution; data polling to determine the end of the write/erase
operations is not required. Code execution is stalled during Flash write/erase operations. Refer to
Table 4.6 for complete Flash memory electrical characteristics.
13.1. Programming The Flash Memory
The simplest means of programming the Flash memory is through the C2 interface using programming
tools provided by Silicon Laboratories or a third party vendor. This is the only means for programming a
non-initialized device. For details on the C2 commands to program Flash memory, see Section “29. C2
Interface” on page 371.
The Flash memory can be programmed by software using the MOVX write instruction with the address and
data byte to be programmed provided as normal operands. Before programming Flash memory using
MOVX, Flash programming operations must be enabled by: (1) setting the PSWE Program Store Write
Enable bit (PSCTL.0) to logic 1 (this directs the MOVX writes to target Flash memory); and (2) Writing the
Flash key codes in sequence to the Flash Lock register (FLKEY). The PSWE bit remains set until cleared
by software. For detailed guidelines on programming Flash from firmware, please see Section “13.5. Flash
Write and Erase Guidelines” on page 145.
To ensure the integrity of the Flash contents, the on-chip VDD Monitor must be enabled and enabled as a
reset source in any system that includes code that writes and/or erases Flash memory from software. Fur-
thermore, there should be no delay between enabling the V Monitor and enabling the V Monitor as a
DD
DD
reset source. Any attempt to write or erase Flash memory while the V
Monitor is disabled, or not
DD
enabled as a reset source, will cause a Flash Error device reset.
13.1.1. Flash Lock and Key Functions
Flash writes and erases by user software are protected with a lock and key function. The Flash Lock and
Key Register (FLKEY) must be written with the correct key codes, in sequence, before Flash operations
may be performed. The key codes are: 0xA5, 0xF1. The timing does not matter, but the codes must be
written in order. If the key codes are written out of order, or the wrong codes are written, Flash writes and
erases will be disabled until the next system reset. Flash writes and erases will also be disabled if a Flash
write or erase is attempted before the key codes have been written properly. The Flash lock resets after
each write or erase; the key codes must be written again before a following Flash operation can be per-
formed. The FLKEY register is detailed in SFR Definition 13.2.
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13.1.2. Flash Erase Procedure
The Flash memory is organized in 1024-byte pages. The erase operation applies to an entire page (setting
all bytes in the page to 0xFF). To erase an entire 1024-byte page, perform the following steps:
1. Save current interrupt state and disable interrupts.
2. Set the PSEE bit (register PSCTL).
3. Set the PSWE bit (register PSCTL).
4. Write the first key code to FLKEY: 0xA5.
5. Write the second key code to FLKEY: 0xF1.
6. Using the MOVX instruction, write a data byte to any location within the 1024-byte page to be erased.
7. Clear the PSWE and PSEE bits.
8. Restore previous interrupt state.
Steps 4–6 must be repeated for each 1024-byte page to be erased.
Notes:
1. Future 16 and 8 kB derivatives in this product family will use a 512-byte page size. To maintain code
compatibility across the entire family, the erase procedure should be performed on each 512-byte section of
memory.
2. Flash security settings may prevent erasure of some Flash pages, such as the reserved area and the page
containing the lock bytes. For a summary of Flash security settings and restrictions affecting Flash erase
operations, please see Section “13.3. Security Options” on page 143.
3. 8-bit MOVX instructions cannot be used to erase or write to Flash memory at addresses higher than 0x00FF.
13.1.3. Flash Write Procedure
A write to Flash memory can clear bits to logic 0 but cannot set them; only an erase operation can set bits
to logic 1 in Flash. A byte location to be programmed should be erased before a new value is written.
The recommended procedure for writing a single byte in Flash is as follows:
1. Save current interrupt state and disable interrupts.
2. Ensure that the Flash byte has been erased (has a value of 0xFF).
3. Set the PSWE bit (register PSCTL).
4. Clear the PSEE bit (register PSCTL).
5. Write the first key code to FLKEY: 0xA5.
6. Write the second key code to FLKEY: 0xF1.
7. Using the MOVX instruction, write a single data byte to the desired location within the 1024-byte sector.
8. Clear the PSWE bit.
9. Restore previous interrupt state.
Steps 5–7 must be repeated for each byte to be written.
Notes:
1. Future 16 and 8 kB derivatives in this product family will use a 512-byte page size. To maintain code
compatibility across the entire family, the erase procedure should be performed on each 512-byte section of
memory.
2. Flash security settings may prevent writes to some areas of Flash, such as the reserved area. For a summary
of Flash security settings and restrictions affecting Flash write operations, please see Section “13.3. Security
Options” on page 143.
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13.2. Non-volatile Data Storage
The Flash memory can be used for non-volatile data storage as well as program code. This allows data
such as calibration coefficients to be calculated and stored at run time. Data is written using the MOVX
write instruction and read using the MOVC instruction. Note: MOVX read instructions always target XRAM.
An additional 1024-byte scratchpad is available for non-volatile data storage. It is accessible at addresses
0x0000 to 0x03FF when SFLE is set to 1. The scratchpad area cannot be used for code execution.
13.3. Security Options
The CIP-51 provides security options to protect the Flash memory from inadvertent modification by soft-
ware as well as to prevent the viewing of proprietary program code and constants. The Program Store
Write Enable (bit PSWE in register PSCTL) and the Program Store Erase Enable (bit PSEE in register
PSCTL) bits protect the Flash memory from accidental modification by software. PSWE must be explicitly
set to 1 before software can modify the Flash memory; both PSWE and PSEE must be set to 1 before soft-
ware can erase Flash memory. Additional security features prevent proprietary program code and data
constants from being read or altered across the C2 interface.
A Security Lock Byte located at the last byte of Flash user space offers protection of the Flash program
memory from access (reads, writes, or erases) by unprotected code or the C2 interface. The Flash security
mechanism allows the user to lock n 1024-byte Flash pages, starting at page 0 (addresses 0x0000 to
0x03FF), where n is the 1s complement number represented by the Security Lock Byte. Note that the
page containing the Flash Security Lock Byte is unlocked when no other Flash pages are locked
(all bits of the Lock Byte are 1) and locked when any other Flash pages are locked (any bit of the
Lock Byte is 0). See the Si1000 example below.
Security Lock Byte:
ones Complement:
Flash pages locked:
11111101b
00000010b
3 (First two Flash pages + Lock Byte Page)
Addresses locked:
0x0000 to 0x07FF (first two Flash pages) and
0xF800 to 0xFBFF (Lock Byte Page)
64KB Flash Device
(SFLE = 0)
32KB Flash Device
(SFLE = 0)
0xFFFF
0xFFFF
Reserved
0xFC00
Unpopulated
Address Space
(Reserved)
0xFBFF
Lock Byte
0xFBFE
Lock Byte Page
0xF800
Locked when
any other
Flash pages
0x8000
Flash
memory
organized in
1024-byte
pages
0x7FFF
Lock Byte
0x7FFE
are locked
Lock Byte Page
0x7C00
Unlocked Flash Pages
64/32KB Flash Device
Unlocked Flash Pages
(SFLE = 1)
Access limit
set according
to the Flash
security lock
byte
0x03FF
Scratchpad Area
(Data Only)
0x0000
0x0000
0x0000
Figure 13.1. Flash Program Memory Map
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The level of Flash security depends on the Flash access method. The three Flash access methods that
can be restricted are reads, writes, and erases from the C2 debug interface, user firmware executing on
unlocked pages, and user firmware executing on locked pages. Table 13.1 summarizes the Flash security
features of the Si1000/1/2/3/4/5 devices.
Table 13.1. Flash Security Summary
Action
C2 Debug
Interface
User Firmware executing from:
an unlocked page a locked page
Read, Write or Erase unlocked pages
(except page with Lock Byte)
Permitted
Permitted
Permitted
Permitted
Permitted
Permitted
Permitted
Permitted
FEDR
Read, Write or Erase locked pages
(except page with Lock Byte)
Not Permitted FEDR
Read or Write page containing Lock Byte
(if no pages are locked)
Permitted
Permitted
Read or Write page containing Lock Byte
(if any page is locked)
Not Permitted FEDR
Read contents of Lock Byte
(if no pages are locked)
Permitted
Permitted
Read contents of Lock Byte
(if any page is locked)
Not Permitted FEDR
Erase page containing Lock Byte
(if no pages are locked)
Permitted
FEDR
ErasepagecontainingLockByte-Unlockallpages Only by C2DE FEDR
(if any page is locked)
FEDR
Lock additional pages
(change 1s to 0s in the Lock Byte)
Not Permitted FEDR
Not Permitted FEDR
Not Permitted FEDR
FEDR
Unlock individual pages
(change 0s to 1s in the Lock Byte)
FEDR
Read, Write or Erase Reserved Area
FEDR
C2DE—C2 Device Erase (Erases all Flash pages including the page containing the Lock Byte)
FEDR—Not permitted; Causes Flash Error Device Reset (FERROR bit in RSTSRC is 1 after reset)
- All prohibited operations that are performed via the C2 interface are ignored (do not cause device reset).
- Locking any Flash page also locks the page containing the Lock Byte.
- Once written to, the Lock Byte cannot be modified except by performing a C2 Device Erase.
- If user code writes to the Lock Byte, the Lock does not take effect until the next device reset.
- The scratchpad is locked when all other Flash pages are locked.
- The scratchpad is erased when a Flash Device Erase command is performed.
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13.4. Determining the Device Part Number at Run Time
In many applications, user software may need to determine the MCU part number at run time in order to
determine the hardware capabilities. The part number can be determined by reading the value of the Flash
byte at address 0xFFFE.
The value of the Flash byte at address 0xFFFE can be decoded as follows:
0xD0—Si1000
0xD1—Si1001
0xD2—Si1002
0xD3—Si1003
13.5. Flash Write and Erase Guidelines
Any system which contains routines which write or erase Flash memory from software involves some risk
that the write or erase routines will execute unintentionally if the CPU is operating outside its specified
operating range of VDD, system clock frequency, or temperature. This accidental execution of Flash modi-
fying code can result in alteration of Flash memory contents causing a system failure that is only recover-
able by re-Flashing the code in the device.
To help prevent the accidental modification of Flash by firmware, the VDD Monitor must be enabled and
enabled as a reset source on C8051F92x-C8051F93x devices for the Flash to be successfully modified. If
either the VDD Monitor or the VDD Monitor reset source is not enabled, a Flash Error Device Reset
will be generated when the firmware attempts to modify the Flash.
The following guidelines are recommended for any system that contains routines which write or erase
Flash from code.
13.5.1. VDD Maintenance and the VDD Monitor
1. If the system power supply is subject to voltage or current "spikes," add sufficient transient protection
devices to the power supply to ensure that the supply voltages listed in the Absolute Maximum Ratings
table are not exceeded.
2. Make certain that the minimum V rise time specification of 1 ms is met. If the system cannot meet
DD
this rise time specification, then add an external VDD brownout circuit to the RST pin of the device that
holds the device in reset until V reaches the minimum device operating voltage and re-asserts RST if
DD
V
drops below the minimum device operating voltage.
DD
3. Keep the on-chip VDD Monitor enabled and enable the V Monitor as a reset source as early in code
DD
as possible. This should be the first set of instructions executed after the Reset Vector. For C-based
systems, this will involve modifying the startup code added by the C compiler. See your compiler
documentation for more details. Make certain that there are no delays in software between enabling the
V
Monitor and enabling the V Monitor as a reset source. Code examples showing this can be
DD
DD
found in “AN201: Writing to Flash from Firmware," available from the Silicon Laboratories website.
Notes: On Si1000/1/2/3/4/5 devices, both the VDD Monitor and the VDD Monitor reset source must be enabled to write
or erase Flash without generating a Flash Error Device Reset.
On Si1000/1/2/3/4/5 devices, both the VDD Monitor and the VDD Monitor reset source are enabled by hardware
after a power-on reset.
4. As an added precaution, explicitly enable the V Monitor and enable the V Monitor as a reset
DD
DD
source inside the functions that write and erase Flash memory. The V Monitor enable instructions
DD
should be placed just after the instruction to set PSWE to a 1, but before the Flash write or erase
operation instruction.
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5. Make certain that all writes to the RSTSRC (Reset Sources) register use direct assignment operators
and explicitly DO NOT use the bit-wise operators (such as AND or OR). For example, "RSTSRC =
0x02" is correct, but "RSTSRC |= 0x02" is incorrect.
6. Make certain that all writes to the RSTSRC register explicitly set the PORSF bit to a 1. Areas to check
are initialization code which enables other reset sources, such as the Missing Clock Detector or
Comparator, for example, and instructions which force a Software Reset. A global search on "RSTSRC"
can quickly verify this.
13.5.2. PSWE Maintenance
7. Reduce the number of places in code where the PSWE bit (b0 in PSCTL) is set to a 1. There should be
exactly one routine in code that sets PSWE to a 1 to write Flash bytes and one routine in code that sets
both PSWE and PSEE both to a 1 to erase Flash pages.
8. Minimize the number of variable accesses while PSWE is set to a 1. Handle pointer address updates
and loop maintenance outside the "PSWE = 1;... PSWE = 0;" area. Code examples showing this can be
found in “AN201: Writing to Flash from Firmware," available from the Silicon Laboratories website.
9. Disable interrupts prior to setting PSWE to a 1 and leave them disabled until after PSWE has been
reset to 0. Any interrupts posted during the Flash write or erase operation will be serviced in priority
order after the Flash operation has been completed and interrupts have been re-enabled by software.
10.Make certain that the Flash write and erase pointer variables are not located in XRAM. See your
compiler documentation for instructions regarding how to explicitly locate variables in different memory
areas.
11.Add address bounds checking to the routines that write or erase Flash memory to ensure that a routine
called with an illegal address does not result in modification of the Flash.
13.5.3. System Clock
12.If operating from an external crystal, be advised that crystal performance is susceptible to electrical
interference and is sensitive to layout and to changes in temperature. If the system is operating in an
electrically noisy environment, use the internal oscillator or use an external CMOS clock.
13.If operating from the external oscillator, switch to the internal oscillator during Flash write or erase
operations. The external oscillator can continue to run, and the CPU can switch back to the external
oscillator after the Flash operation has completed.
Additional Flash recommendations and example code can be found in “AN201: Writing to Flash from Firm-
ware," available from the Silicon Laboratories website.
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13.6. Minimizing Flash Read Current
The Flash memory in the Si1000/1/2/3/4/5 devices is responsible for a substantial portion of the total digital
supply current when the device is executing code. Below are suggestions to minimize Flash read current.
1. Use Idle, Suspend, or Sleep Modes while waiting for an interrupt, rather than polling the interrupt flag.
Idle Mode is particularly well-suited for use in implementing short pauses, since the wake-up time is no
more than three system clock cycles. See the Power Management chapter for details on the various
low-power operating modes.
2. Si1000/1/2/3/4/5 devices have a one-shot timer that saves power when operating at system clock
frequencies of 10 MHz or less. The one-shot timer generates a minimum-duration enable signal for the
Flash sense amps on each clock cycle in which the Flash memory is accessed. This allows the Flash to
remain in a low power state for the remainder of the long clock cycle.
At clock frequencies above 10 MHz, the system clock cycle becomes short enough that the one-shot
timer no longer provides a power benefit. Disabling the one-shot timer at higher frequencies reduces
power consumption. The one-shot is enabled by default, and it can be disabled (bypassed) by setting
the BYPASS bit (FLSCL.6) to logic 1. To re-enable the one-shot, clear the BYPASS bit to logic 0. See
the note in SFR Definition 13.3. FLSCL: Flash Scale for more information on how to properly clear the
BYPASS bit.
3. Flash read current depends on the number of address lines that toggle between sequential Flash read
operations. In most cases, the difference in power is relatively small (on the order of 5%).
4. The Flash memory is organized in rows. Each row in the Si1000/1/2/3/4/5 Flash contains 128 bytes. A
substantial current increase can be detected when the read address jumps from one row in the Flash
memory to another. Consider a 3-cycle loop (e.g., SJMP $, or while(1);) which straddles a 128-byte
Flash row boundary. The Flash address jumps from one row to another on two of every three clock
cycles. This can result in a current increase of up 30% when compared to the same 3-cycle loop
contained entirely within a single row.
5. To minimize the power consumption of small loops, it is best to locate them within a single row, if
possible. To check if a loop is contained within a Flash row, divide the starting address of the first
instruction in the loop by 128. If the remainder (result of modulo operation) plus the length of the loop is
less than 127, then the loop fits inside a single Flash row. Otherwise, the loop will be straddling two
adjacent Flash rows. If a loop executes in 20 or more clock cycles, then the transitions from one row to
another will occur on relatively few clock cycles, and any resulting increase in operating current will be
negligible.
Note: Future 16 and 8 kB derivatives in this product family will use a Flash memory that is organized in rows of 64
bytes each. To maintain code compatibility across the entire family, it is best to locate small loops within a single
64-byte segment.
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SFR Definition 13.1. PSCTL: Program Store R/W Control
Bit
7
6
5
4
3
2
1
0
SFLE
PSEE
PSWE
Name
Type
Reset
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
SFR Page =0x0; SFR Address = 0x8F
Bit
7:3
2
Name
Function
Unused Read = 00000b, Write = don’t care.
SFLE
PSEE
Scratchpad Flash Memory Access Enable.
When this bit is set, Flash MOVC reads and MOVX writes from user software are
directed to the Scratchpad Flash sector. Flash accesses outside the address range
0x0000-0x03FF should not be attempted and may yield undefined results when SFLE
is set to 1.
0: Flash access from user software directed to the Program/Data Flash sector.
1: Flash access from user software directed to the Scratchpad Sector.
1
Program Store Erase Enable.
Setting this bit (in combination with PSWE) allows an entire page of Flash program
memory to be erased. If this bit is logic 1 and Flash writes are enabled (PSWE is logic
1), a write to Flash memory using the MOVX instruction will erase the entire page that
contains the location addressed by the MOVX instruction. The value of the data byte
written does not matter.
0: Flash program memory erasure disabled.
1: Flash program memory erasure enabled.
0
PSWE Program Store Write Enable.
Setting this bit allows writing a byte of data to the Flash program memory using the
MOVX write instruction. The Flash location should be erased before writing data.
0: Writes to Flash program memory disabled.
1: Writes to Flash program memory enabled; the MOVX write instruction targets Flash
memory.
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SFR Definition 13.2. FLKEY: Flash Lock and Key
Bit
7
6
5
4
3
2
1
0
FLKEY[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xB6
Bit Name
Function
7:0 FLKEY[7:0] Flash Lock and Key Register.
Write:
This register provides a lock and key function for Flash erasures and writes. Flash
writes and erases are enabled by writing 0xA5 followed by 0xF1 to the FLKEY regis-
ter. Flash writes and erases are automatically disabled after the next write or erase is
complete. If any writes to FLKEY are performed incorrectly, or if a Flash write or erase
operation is attempted while these operations are disabled, the Flash will be perma-
nently
locked from writes or erasures until the next device reset. If an application never
writes to Flash, it can intentionally lock the Flash by writing a non-0xA5 value to
FLKEY from software.
Read:
When read, bits 1–0 indicate the current Flash lock state.
00: Flash is write/erase locked.
01: The first key code has been written (0xA5).
10: Flash is unlocked (writes/erases allowed).
11: Flash writes/erases disabled until the next reset.
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SFR Definition 13.3. FLSCL: Flash Scale
Bit
7
6
BYPASS
R/W
5
4
3
2
1
0
Name
Type
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
0
SFR Page = 0x0; SFR Address = 0xB6
Bit
Name
Function
7
Reserved Always Write to 0.
6
BYPASS Flash Read Timing One-Shot Bypass.
0: The one-shot determines the Flash read time. This setting should be used for oper-
ating frequencies less than 10 MHz.
1: The system clock determines the Flash read time. This setting should be used for
frequencies greater than 10 MHz.
5:0 Reserved Always Write to 000000.
Note: When changing the BYPASS bit from 1 to 0, the third opcode byte fetched from program memory is
indeterminate. Therefore, the operation which clears the BYPASS bit should be immediately followed by a
benign 3-byte instruction whose third byte is a don’t care. An example of such an instruction is a 3-byte MOV
that targets the FLWR register. When programming in C, the dummy value written to FLWR should be a non-
zero value to prevent the compiler from generating a 2-byte MOV instruction.
SFR Definition 13.4. FLWR: Flash Write Only
Bit
7
6
5
4
3
2
1
0
FLWR[7:0]
Name
Type
Reset
W
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xE5
Bit Name
7:0 FLWR[7:0] Flash Write Only.
Function
All writes to this register have no effect on system operation.
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14. Power Management
Si1000/1/2/3/4/5 devices support 5 power modes: Normal, Idle, Stop, Suspend, and Sleep. The power
management unit (PMU0) allows the device to enter and wake-up from the available power modes. A brief
description of each power mode is provided in Table 14.1. Detailed descriptions of each mode can be
found in the following sections.
Table 14.1. Power Modes
Power Mode
Description
Wake-Up
Sources
Power Savings
Normal
Idle
Device fully functional
N/A
Excellent MIPS/mW
All peripherals fully functional.
Very easy to wake up.
Any Interrupt
Good
No Code Execution
Stop
Legacy 8051 low power mode.
A reset is required to wake up.
Any Reset
Good
No Code Execution
Precision Oscillator Disabled
Suspend
Similar to Stop Mode, but very fast SmaRTClock,
Very Good
wake-up time and code resumes
execution at the next instruction.
Port Match,
Comparator0,
RST pin
No Code Execution
All Internal Oscillators Disabled
System Clock Gated
Sleep
Ultra Low Power and flexible
wake-up sources. Code resumes
execution at the next instruction.
Comparator0 only functional in
two-cell mode.
SmaRTClock,
Port Match,
Comparator0,
RST pin
Excellent
Power Supply Gated
All Oscillators except SmaRT-
Clock Disabled
In battery powered systems, the system should spend as much time as possible in Sleep mode in order to
preserve battery life. When a task with a fixed number of clock cycles needs to be performed, the device
should switch to Normal mode, finish the task as quickly as possible, and return to Sleep mode. Idle Mode
and Suspend modes provide a very fast wake-up time; however, the power savings in these modes will not
be as much as in Sleep Mode. Stop Mode is included for legacy reasons; the system will be more power
efficient and easier to wake up when Idle, Suspend, or Sleep Mode are used.
Although switching power modes is an integral part of power management, enabling/disabling individual
peripherals as needed will help lower power consumption in all power modes. Each analog peripheral can
be disabled when not in use or placed in a low power mode. Digital peripherals such as timers or serial
busses draw little power whenever they are not in use. Digital peripherals draw no power in Sleep Mode.
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Si1000/1/2/3/4/5
14.1. Normal Mode
The MCU is fully functional in Normal Mode. Figure 14.1 shows the on-chip power distribution to various
peripherals. There are three supply voltages powering various sections of the chip: VBAT, VDD/DC+, and
the 1.8 V internal core supply. VREG0, PMU0 and the SmaRTClock are always powered directly from the
VBAT pin. All analog peripherals are directly powered from the VDD/DC+ pin, which is an output in one-cell
mode and an input in two-cell mode. All digital peripherals and the CIP-51 core are powered from the 1.8 V
internal core supply. The RAM is also powered from the core supply in Normal mode.
One-cell: 0.9 to 1.8 V
Two-cell: 1.8 to 3.6 V
VBAT
VDD/DC+
One-cell or Two-cell: 1.8 to 3.6 V
Note: VDD/DC+ must be > VBAT
1.9 V
typical
GPIO
DC0
Analog Peripherals
One-Cell Active/
Idle/Stop/Suspend
One-Cell Sleep
VREF
IREF0
A
10-bit
300 ksps
ADC
M
U
X
+
-
+
-
VREG0
TEMP
SENSOR
VOLTAGE
COMPARATORS
Active/Idle/
Stop/Suspend
Sleep
Digital Peripherals
1.8 V
UART
Flash
PMU0
SmaRTClock
CIP-51
Core
SPI
RAM
Timers
SMBus
Figure 14.1. Si1000/1/2/3/4/5 Power Distribution
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14.2. Idle Mode
Setting the Idle Mode Select bit (PCON.0) causes the CIP-51 to halt the CPU and enter Idle mode as soon
as the instruction that sets the bit completes execution. All internal registers and memory maintain their
original data. All analog and digital peripherals can remain active during Idle mode.
Note: To ensure the MCU enters a low power state upon entry into Idle Mode, the one-shot circuit should be
enabled by clearing the BYPASS bit (FLSCL.6) to logic 0. See the note in SFR Definition 13.3. FLSCL:
Flash Scale for more information on how to properly clear the BYPASS bit.
Idle mode is terminated when an enabled interrupt is asserted or a reset occurs. The assertion of an
enabled interrupt will cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU to resume
operation. The pending interrupt will be serviced and the next instruction to be executed after the return
from interrupt (RETI) will be the instruction immediately following the one that set the Idle Mode Select bit.
If Idle mode is terminated by an internal or external reset, the CIP-51 performs a normal reset sequence
and begins program execution at address 0x0000.
If enabled, the Watchdog Timer (WDT) will eventually cause an internal watchdog reset and thereby termi-
nate the Idle mode. This feature protects the system from an unintended permanent shutdown in the event
of an inadvertent write to the PCON register. If this behavior is not desired, the WDT may be disabled by
software prior to entering the Idle mode if the WDT was initially configured to allow this operation. This pro-
vides the opportunity for additional power savings, allowing the system to remain in the Idle mode indefi-
nitely, waiting for an external stimulus to wake up the system. Refer to Section “18.6. PCA Watchdog Timer
Reset” on page 180 for more information on the use and configuration of the WDT.
14.3. Stop Mode
Setting the Stop Mode Select bit (PCON.1) causes the CIP-51 to enter Stop mode as soon as the instruc-
tion that sets the bit completes execution. In Stop mode the precision internal oscillator and CPU are
stopped; the state of the low power oscillator and the external oscillator circuit is not affected. Each analog
peripheral (including the external oscillator circuit) may be shut down individually prior to entering Stop
Mode. Stop mode can only be terminated by an internal or external reset. On reset, the CIP-51 performs
the normal reset sequence and begins program execution at address 0x0000.
If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode.
The Missing Clock Detector should be disabled if the CPU is to be put to in STOP mode for longer than the
MCD timeout of 100 µs.
Stop Mode is a legacy 8051 power mode; it will not result in optimal power savings. Sleep or Suspend
mode will provide more power savings if the MCU needs to be inactive for a long period of time.
On Si1000/1/2/3/4/5 devices, the Precision Oscillator Bias is not automatically disabled and should be dis-
abled by software to achieve the lowest possible Stop mode current.
To ensure the MCU enters a low power state upon entry into Stop Mode, the one-shot circuit should be
enabled by clearing the BYPASS bit (FLSCL.6) to logic 0. See the note in SFR Definition 13.3. FLSCL: Flash
Scale for more information on how to properly clear the BYPASS bit.
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14.4. Suspend Mode
Setting the Suspend Mode Select bit (PMU0CF.6) causes the system clock to be gated off and all internal
oscillators disabled. All digital logic (timers, communication peripherals, interrupts, CPU, etc.) stops
functioning until one of the enabled wake-up sources occurs.
Important Notes:
When entering Suspend Mode, the global clock divider must be set to "divide by 1" by setting
CLKDIV[2:0] = 000b in the CLKSEL register.
The one-shot circuit should be enabled by clearing the BYPASS bit (FLSCL.6) to logic 0. See the
note in SFR Definition 13.3. FLSCL: Flash Scale for more information on how to properly clear
the BYPASS bit.
Upon wake-up from suspend mode, PMU0 requires two system clocks in order to update the PMU0CF
wake-up flags. All flags will read back a value of 0 during the first two system clocks following a wake-
up from suspend mode.
The system clock source must be set to the low power internal oscillator or the precision oscillator prior
to entering suspend mode.
The following wake-up sources can be configured to wake the device from suspend mode:
SmaRTClock Oscillator Fail
SmaRTClock Alarm
Port Match Event
Comparator0 Rising Edge
In addition, a noise glitch on RST that is not long enough to reset the device will cause the device to exit
suspend. In order for the MCU to respond to the pin reset event, software must not place the device back
into suspend mode for a period of 15 µs. The PMU0CF register may be checked to determine if the wake-
up was due to a falling edge on the /RST pin. If the wake-up source is not due to a falling edge on RST,
there is no time restriction on how soon software may place the device back into suspend mode. A 4.7 k
pullup resistor to VDD_MCU/DC+ is recommend for RST to prevent noise glitches from waking the device.
14.5. Sleep Mode
Setting the Sleep Mode Select bit (PMU0CF.6) turns off the internal 1.8 V regulator (VREG0) and switches
the power supply of all on-chip RAM to the VDD_MCU pin (see Figure 14.1). Power to most digital logic on
the chip is disconnected; only PMU0 and the SmaRTClock remain powered. Analog peripherals remain
powered. The Comparators remain functional when the device enters sleep mode. All other analog periph-
erals (ADC0, IREF0, External Oscillator, etc.) should be disabled prior to entering sleep mode. The system
clock source must be set to the low power internal oscillator or the precision oscillator prior to entering
sleep mode.
Important Notes:
When entering Sleep Mode, the global clock divider must be set to "divide by 1" by setting
CLKDIV[2:0] = 000b in the CLKSEL register.
Any write to PMU0CF which places the device in sleep mode should be immediately followed by two
NOP instructions. Software that does not place two NOP instructions immediately following the write to
PMU0CF should continue to behave the same way as during software development.
GPIO pins configured as digital outputs will retain their output state during sleep mode. In two-cell mode,
they will maintain the same current drive capability in sleep mode as they have in normal mode. In one-cell
mode, the VDD_MCU/DC+ supply will drop to the level of VBAT, which will reduce the output high-voltage
level and the source and sink current drive capability.
GPIO pins configured as digital inputs can be used during sleep mode as wakeup sources using the port
match feature. In two-cell mode, they will maintain the same input level specifications in sleep mode as
they have in normal mode. In one-cell mode, the VDD supply will drop to the level of VBAT, which will lower
the switching threshold and increase the propagation delay.
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Note: By default, the VDD/DC+ supply is connected to VBAT upon entry into Sleep Mode (one-cell mode). If the
VDDSLP bit (DC0CF.1) is set to logic 1, the VDD/DC+ supply will float in Sleep Mode. This allows the
decoupling capacitance on the VDD/DC+ supply to maintain the supply rail until the capacitors are discharged.
For relatively short sleep intervals, this can result in substantial power savings because the decoupling
capacitance is not continuously charged and discharged.
RAM and SFR register contents are preserved in sleep mode as long as the voltage on VBAT (or
VDD_MCU on Si1000/1/2/3 devices) does not fall below V
. The PC counter and all other volatile state
POR
information is preserved allowing the device to resume code execution upon waking up from sleep mode.
The following wake-up sources can be configured to wake the device from sleep mode:
SmaRTClock Oscillator Fail
SmaRTClock Alarm
Port Match Event
Comparator0 Rising Edge
The Comparator0 Rising Edge wakeup is only valid in two-cell mode. The comparator requires a supply
voltage of at least 1.8 V to operate properly.
In addition, any falling edge on RST (due to a pin reset or a noise glitch) will cause the device to exit sleep
mode. In order for the MCU to respond to the pin reset event, software must not place the device back into
sleep mode for a period of 15 µs. The PMU0CF register may be checked to determine if the wake-up was
due to a falling edge on the RST pin. If the wake-up source is not due to a falling edge on RST, there is no
time restriction on how soon software may place the device back into sleep mode. A 4.7 k pullup resistor
to VDD_MCU/DC+ is recommend for RST to prevent noise glitches from waking the device.
14.6. Configuring Wakeup Sources
Before placing the device in a low power mode, one or more wakeup sources should be enabled so that
the device does not remain in the low power mode indefinitely. For Idle Mode, this includes enabling any
interrupt. For stop mode, this includes enabling any reset source or relying on the RST pin to reset the
device.
Wake-up sources for suspend and sleep modes are configured through the PMU0CF register. Wake-up
sources are enabled by writing 1 to the corresponding wake-up source enable bit. Wake-up sources must
be re-enabled each time the device is placed in suspend or sleep mode, in the same write that places the
device in the low power mode.
The reset pin is always enabled as a wake-up source. On the falling edge of RST, the device will be
awaken from sleep mode. The device must remain awake for more than 15 µs in order for the reset to take
place.
14.7. Determining the Event that Caused the Last Wakeup
When waking from Idle Mode, the CPU will vector to the interrupt which caused it to wake up. When wak-
ing from Stop mode, the RSTSRC register may be read to determine the cause of the last reset.
Upon exit from Suspend or Sleep mode, the wake-up flags in the PMU0CF register can be read to deter-
mine the event which caused the device to wake up. After waking up, the wake-up flags will continue to be
updated if any of the wake-up events occur. Wake-up flags are always updated, even if they are not
enabled as wake-up sources.
All wake-up flags enabled as wake-up sources in PMU0CF must be cleared before the device can enter
suspend or sleep mode. After clearing the wake-up flags, each of the enabled wake-up events should be
checked in the individual peripherals to ensure that a wake-up event did not occur while the wake-up flags
were being cleared.
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Si1000/1/2/3/4/5
1,2
SFR Definition 14.1. PMU0CF: Power Management Unit Configuration
Bit
7
6
5
4
3
2
1
0
SLEEP SUSPEND
CLEAR
RSTWK RTCFWK RTCAWK PMATWK CPT0WK
Name
Type
Reset
W
0
W
0
W
0
R
R/W
R/W
R/W
R/W
Varies
Varies
Varies
Varies
Varies
SFR Page = 0x0; SFR Address = 0xB5
Bit
Name
Description
Write
Read
7
SLEEP
Sleep Mode Select
Writing 1 places the
device in Sleep Mode.
N/A
N/A
6
5
4
3
SUSPEND Suspend Mode Select
Writing 1 places the
device in Suspend Mode.
CLEAR
RSTWK
Wake-up Flag Clear
Writing 1 clears all wake- N/A
up flags.
Reset Pin Wake-up Flag N/A
Set to 1 if a falling edge has
been detected on RST.
RTCFWK SmaRTClock Oscillator
Fail Wake-up Source
0: Disable wake-up on
SmaRTClock Osc. Fail.
1: Enable wake-up on
SmaRTClock Osc. Fail.
Set to 1 if the SmaRTClock
Oscillator has failed.
Enable and Flag
2
RTCAWK SmaRTClock Alarm
0: Disable wake-up on
Set to 1 if a SmaRTClock
Alarm has occurred.
Wake-up Source Enable SmaRTClock Alarm.
and Flag
1: Enable wake-up on
SmaRTClock Alarm.
1
PMATWK Port Match Wake-up
0: Disable wake-up on
Set to 1 if a Port Match
Event has occurred.
Source Enable and Flag Port Match Event.
1: Enable wake-up on
Port Match Event.
0
CPT0WK Comparator0 Wake-up
0: Disable wake-up on
Set to 1 if Comparator0 ris-
Source Enable and Flag Comparator0 rising edge. ing edge has occurred.
1: Enable wake-up on
Comparator0 rising edge.
Notes:
1. Read-modify-write operations (ORL, ANL, etc.) should not be used on this register. Wake-up sources must be
re-enabled each time the SLEEP or SUSPEND bits are written to 1.
2. The Low Power Internal Oscillator cannot be disabled and the MCU cannot be placed in Suspend or Sleep
Mode if any wake-up flags are set to 1. Software should clear all wake-up sources after each reset and after
each wake-up from Suspend or Sleep Modes.
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SFR Definition 14.2. PCON: Power Management Control Register
Bit
7
6
5
4
3
2
1
0
GF[5:0]
R/W
STOP
IDLE
Name
Type
Reset
W
0
W
0
0
0
0
0
0
0
SFR Page = All Pages; SFR Address = 0x87
Bit
7:2
1
Name
GF[5:0]
STOP
Description
General Purpose Flags
Stop Mode Select
Write
Read
Sets the logic value.
Returns the logic value.
N/A
Writing 1 places the
device in Stop Mode.
0
IDLE
Idle Mode Select
Writing 1 places the
device in Idle Mode.
N/A
14.8. Power Management Specifications
See Table 4.5 on page 58 for detailed Power Management Specifications.
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Si1000/1/2/3/4/5
15. Cyclic Redundancy Check Unit (CRC0)
Si1000/1/2/3/4/5 devices include a cyclic redundancy check unit (CRC0) that can perform a CRC using a
16-bit or 32-bit polynomial. CRC0 accepts a stream of 8-bit data written to the CRC0IN register. CRC0
posts the 16-bit or 32-bit result to an internal register. The internal result register may be accessed indi-
rectly using the CRC0PNT bits and CRC0DAT register, as shown in Figure 15.1. CRC0 also has a bit
reverse register for quick data manipulation.
8
8
Automatic CRC
Controller
Flash
Memory
CRC0IN
CRC0AUTO
CRC0CNT
CRC0SEL
CRC0INIT
CRC0VAL
CRC0PNT1
CRC0PNT0
CRC Engine
32
RESULT
CRC0FLIP
Write
8
8
8
8
4 to 1 MUX
8
CRC0DAT
CRC0FLIP
Read
Figure 15.1. CRC0 Block Diagram
15.1. CRC Algorithm
The Si1000/1/2/3/4/5 CRC unit generates a CRC result equivalent to the following algorithm:
1. XOR the input with the most-significant bits of the current CRC result. If this is the first iteration of the
CRC unit, the current CRC result will be the set initial value
(0x00000000 or 0xFFFFFFFF).
2a. If the MSB of the CRC result is set, shift the CRC result and XOR the result with the selected
polynomial.
2b. If the MSB of the CRC result is not set, shift the CRC result.
Repeat Steps 2a/2b for the number of input bits (8). The algorithm is also described in the following exam-
ple.
The 16-bit Si1000/1/2/3/4/5 CRC algorithm can be described by the following code:
unsigned short UpdateCRC (unsigned short CRC_acc, unsigned char CRC_input)
{
unsigned char i;
// loop counter
#define POLY 0x1021
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// Create the CRC "dividend" for polynomial arithmetic (binary arithmetic
// with no carries)
CRC_acc = CRC_acc ^ (CRC_input << 8);
// "Divide" the poly into the dividend using CRC XOR subtraction
// CRC_acc holds the "remainder" of each divide
//
// Only complete this division for 8 bits since input is 1 byte
for (i = 0; i < 8; i++)
{
// Check if the MSB is set (if MSB is 1, then the POLY can "divide"
// into the "dividend")
if ((CRC_acc & 0x8000) == 0x8000)
{
// if so, shift the CRC value, and XOR "subtract" the poly
CRC_acc = CRC_acc << 1;
CRC_acc ^= POLY;
}
else
{
// if not, just shift the CRC value
CRC_acc = CRC_acc << 1;
}
}
// Return the final remainder (CRC value)
return CRC_acc;
}
The following table lists several input values and the associated outputs using the 16-bit Si1000/1/2/3/4/5
CRC algorithm:
Table 15.1. Example 16-bit CRC Outputs
Input
Output
0xBD35
0xB1F4
0x4ECA
0x6CF6
0xB166
0x63
0x8C
0x7D
0xAA, 0xBB, 0xCC
0x00, 0x00, 0xAA, 0xBB, 0xCC
Rev. 1.0
159
Si1000/1/2/3/4/5
15.2. Preparing for a CRC Calculation
To prepare CRC0 for a CRC calculation, software should select the desired polynomial and set the initial
value of the result. Two polynomials are available: 0x1021 (16-bit) and 0x04C11DB7 (32-bit). The CRC0
result may be initialized to one of two values: 0x00000000 or 0xFFFFFFFF. The following steps can be
used to initialize CRC0.
1. Select a polynomial (Set CRC0SEL to 0 for 32-bit or 1 for 16-bit).
2. Select the initial result value (Set CRC0VAL to 0 for 0x00000000 or 1 for 0xFFFFFFFF).
3. Set the result to its initial value (Write 1 to CRC0INIT).
15.3. Performing a CRC Calculation
Once CRC0 is initialized, the input data stream is sequentially written to CRC0IN, one byte at a time. The
CRC0 result is automatically updated after each byte is written. The CRC engine may also be configured to
automatically perform a CRC on one or more Flash sectors. The following steps can be used to automati-
cally perform a CRC on Flash memory.
1. Prepare CRC0 for a CRC calculation as shown above.
2. Write the index of the starting page to CRC0AUTO.
3. Set the AUTOEN bit in CRC0AUTO.
4. Write the number of Flash sectors to perform in the CRC calculation to CRC0CNT.
Note: Each Flash sector is 1024 bytes.
5. Write any value to CRC0CN (or OR its contents with 0x00) to initiate the CRC calculation. The CPU will
not execute code any additional code until the CRC operation completes.
See the note in SFR Definition 15.1. CRC0CN: CRC0 Control for more information on how to
properly initiate a CRC calculation.
6. Clear the AUTOEN bit in CRC0AUTO.
7. Read the CRC result using the procedure below.
15.4. Accessing the CRC0 Result
The internal CRC0 result is 32-bits (CRC0SEL = 0b) or 16-bits (CRC0SEL = 1b). The CRC0PNT bits
select the byte that is targeted by read and write operations on CRC0DAT and increment after each read or
write. The calculation result will remain in the internal CR0 result register until it is set, overwritten, or addi-
tional data is written to CRC0IN.
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SFR Definition 15.1. CRC0CN: CRC0 Control
Bit
7
6
5
4
3
2
1
0
CRC0SEL CRC0INIT CRC0VAL
CRC0PNT[1:0]
R/W
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
0
SFR Page = 0xF; SFR Address = 0x92
Bit
7:5
4
Name
Function
Unused
Read = 000b; Write = Don’t Care.
CRC0SEL
CRC0 Polynomial Select Bit.
This bit selects the CRC0 polynomial and result length (32-bit or 16-bit).
0: CRC0 uses the 32-bit polynomial 0x04C11DB7 for calculating the CRC result.
1: CRC0 uses the 16-bit polynomial 0x1021 for calculating the CRC result.
3
2
CRC0INIT
CRC0VAL
CRC0 Result Initialization Bit.
Writing a 1 to this bit initializes the entire CRC result based on CRC0VAL.
CRC0 Set Value Initialization Bit.
This bit selects the set value of the CRC result.
0: CRC result is set to 0x00000000 on write of 1 to CRC0INIT.
1: CRC result is set to 0xFFFFFFFF on write of 1 to CRC0INIT.
1:0 CRC0PNT[1:0] CRC0 Result Pointer.
Specifies the byte of the CRC result to be read/written on the next access to
CRC0DAT. The value of these bits will auto-increment upon each read or write.
For CRC0SEL = 0:
00: CRC0DAT accesses bits 7–0 of the 32-bit CRC result.
01: CRC0DAT accesses bits 15–8 of the 32-bit CRC result.
10: CRC0DAT accesses bits 23–16 of the 32-bit CRC result.
11: CRC0DAT accesses bits 31–24 of the 32-bit CRC result.
For CRC0SEL = 1:
00: CRC0DAT accesses bits 7–0 of the 16-bit CRC result.
01: CRC0DAT accesses bits 15–8 of the 16-bit CRC result.
10: CRC0DAT accesses bits 7–0 of the 16-bit CRC result.
11: CRC0DAT accesses bits 15–8 of the 16-bit CRC result.
Note: Upon initiation of an automatic CRC calculation, the third opcode byte fetched from program memory is
indeterminate. Therefore, writes to CRC0CN that initiate a CRC operation must be immediately followed by a
benign 3-byte instruction whose third byte is a don’t care. An example of such an instruction is a 3-byte MOV
that targets the CRC0FLIP register. When programming in ‘C’, the dummy value written to CRC0FLIP should
be a non-zero value to prevent the compiler from generating a 2-byte MOV instruction.
Rev. 1.0
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Si1000/1/2/3/4/5
SFR Definition 15.2. CRC0IN: CRC0 Data Input
Bit
7
6
5
4
3
2
1
0
CRC0IN[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Page = 0xF; SFR Address = 0x93
Bit Name
7:0 CRC0IN[7:0] CRC0 Data Input.
Function
Each write to CRC0IN results in the written data being computed into the existing
CRC result according to the CRC algorithm described in Section 15.1
SFR Definition 15.3. CRC0DAT: CRC0 Data Output
Bit
7
6
5
4
3
2
1
0
CRC0DAT[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Page = 0xF; SFR Address = 0x91
Bit Name
7:0 CRC0DAT[7:0] CRC0 Data Output.
Function
Each read or write performed on CRC0DAT targets the CRC result bits pointed to
by the CRC0 Result Pointer (CRC0PNT bits in CRC0CN).
162
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SFR Definition 15.4. CRC0AUTO: CRC0 Automatic Control
Bit
7
6
5
4
3
2
1
0
AUTOEN CRCDONE
CRC0ST[5:0]
Name
Type
Reset
R/W
0
R/W
0
0
1
0
0
0
0
SFR Page = 0xF; SFR Address = 0x96
Bit
Name
Function
7
AUTOEN
Automatic CRC Calculation Enable.
When AUTOEN is set to 1, any write to CRC0CN will initiate an automatic CRC
starting at Flash sector CRC0ST and continuing for CRC0CNT sectors.
6
CRCDONE
CRCDONE Automatic CRC Calculation Complete.
Set to '0' when a CRC calculation is in progress. Note that code execution is
stopped during a CRC calculation, therefore reads from firmware will always
return '1'.
5:0 CRC0ST[5:0] Automatic CRC Calculation Starting Flash Sector.
These bits specify the Flash sector to start the automatic CRC calculation. The
starting address of the first Flash sector included in the automatic CRC calculation
is CRC0ST x 1024.
SFR Definition 15.5. CRC0CNT: CRC0 Automatic Flash Sector Count
Bit
7
6
5
4
3
2
1
0
CRC0CNT[5:0]
Name
Type
Reset
R/W
0
R/W
0
0
0
0
0
0
0
SFR Page = 0xF; SFR Address = 0x97
Bit
Name
Function
7:6
Unused
Read = 00b; Write = Don’t Care.
5:0 CRC0CNT[5:0] Automatic CRC Calculation Flash Sector Count.
These bits specify the number of Flash sectors to include in an automatic CRC
calculation. The starting address of the last Flash sector included in the automatic
CRC calculation is (CRC0ST+CRC0CNT) x 1024.
Rev. 1.0
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Si1000/1/2/3/4/5
15.5. CRC0 Bit Reverse Feature
CRC0 includes hardware to reverse the bit order of each bit in a byte as shown in Figure 15.2. Each byte
of data written to CRC0FLIP is read back bit reversed. For example, if 0xC0 is written to CRC0FLIP, the
data read back is 0x03. Bit reversal is a useful mathematical function used in algorithms such as the FFT.
CRC0FLIP
Write
CRC0FLIP
Read
Figure 15.2. Bit Reverse Register
SFR Definition 15.6. CRC0FLIP: CRC0 Bit Flip
Bit
7
6
5
4
3
2
1
0
CRC0FLIP[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Page = 0xF; SFR Address = 0x95
Bit Name
7:0 CRC0FLIP[7:0] CRC0 Bit Flip.
Function
Any byte written to CRC0FLIP is read back in a bit-reversed order, i.e. the written
LSB becomes the MSB. For example:
If 0xC0 is written to CRC0FLIP, the data read back will be 0x03.
If 0x05 is written to CRC0FLIP, the data read back will be 0xA0.
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16. On-Chip DC-DC Converter (DC0)
Si1004/5 devices include an on-chip dc-dc converter to allow operation from a single cell battery with a
supply voltage as low as 0.9 V. The dc-dc converter is a switching boost converter with an input voltage
range of 0.9 to 1.8 V and a programmable output voltage range of 1.8 to 3.3 V. The default output voltage
is 1.9 V. The dc-dc converter can supply the system with up to 65 mW of regulated power (or up to
100 mW in some applications) and can be used for powering other devices in the system. This allows the
most flexibility when interfacing to sensors and other analog signals which typically require a higher supply
voltage than a single-cell battery can provide.
Figure 16.1 shows a block diagram of the dc-dc converter. During normal operation in the first half of the
switching cycle, the Duty Cycle Control switch is closed and the Diode Bypass switch is open. Since the
output voltage is higher than the voltage at the DCEN pin, no current flows through the diode and the load
is powered from the output capacitor. During this stage, the DCEN pin is connected to ground through the
Duty Cycle Control switch, generating a positive voltage across the inductor and forcing its current to ramp
up.
In the second half of the switching cycle, the Duty Cycle control switch is opened and the Diode Bypass
switch is closed. This connects DCEN directly to VDD_MCU/DC+ and forces the inductor current to charge
the output capacitor. Once the inductor transfers its stored energy to the output capacitor, the Duty Cycle
Control switch is closed, the Diode Bypass switch is opened, and the cycle repeats.
The dc-dc converter has a built in voltage reference and oscillator, and will automatically limit or turn off the
switching activity in case the peak inductor current rises beyond a safe limit or the output voltage rises
above the programmed target value. This allows the dc-dc converter output to be safely overdriven by a
secondary power source (when available) in order to preserve battery life. The dc-dc converter’s settings
can be modified using SFR registers which provide the ability to change the target output voltage, oscillator
frequency or source, Diode Bypass switch resistance, peak inductor current, and minimum duty cycle.
DC/DC Converter
VBAT
VDD_MCU/DC+
0.68 uH
DCEN
Diode
4.7 uF
Bypass
Duty
Cycle
Control
Control Logic
Voltage
Iload
Cload
1uF
DC0CN
Reference
DC/DC
Oscillator
DC0CF
Lparasitic
Lparasitic
GND/VBAT-
GND_MCU/DC-
Figure 16.1. DC-DC Converter Block Diagram
Rev. 1.0
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Si1000/1/2/3/4/5
16.1. Startup Behavior
On initial power-on, the dc-dc converter outputs a constant 50% duty cycle until there is sufficient voltage
on the output capacitor to maintain regulation. The size of the output capacitor and the amount of load cur-
rent present during startup will determine the length of time it takes to charge the output capacitor.
During initial power-on reset, the maximum peak inductor current threshold, which triggers the overcurrent
protection circuit, is set to approximately 125 mA. This generates a “soft-start” to limit the output voltage
slew rate and prevent excessive in-rush current at the output capacitor. In order to ensure reliable startup
of the dc-dc converter, the following restrictions have been imposed:
•
The maximum dc load current allowed during startup is given in Table 4.15 on page 65. If the dc-dc
converter is powering external sensors or devices through the VDD_MCU/DC+ pin or through GPIO
pins, then the current supplied to these sensors or devices is counted towards this limit. The in-rush
current into capacitors does not count towards this limit.
•
The maximum total output capacitance is given in Table 4.15 on page 65. This value includes the
required 1 µF ceramic output capacitor and any additional capacitance connected to the
VDD_MCU/DC+ pin.
Once initial power-on is complete, the peak inductor current limit can be increased by software as shown in
Table 16.1. Limiting the peak inductor current can allow the device to start up near the battery’s end of life.
.
Table 16.1. IPeak Inductor Current Limit Settings
SWSEL
ILIMIT
Peak Current (mA)
1
0
1
0
0
0
1
1
100
125
250
500
The peak inductor current is dependent on several factors including the dc load current and can be esti-
mated using following equation:
2 ILOADVDD/DC+ – VBAT
efficiency inductance frequency
IPK
=
-------------------------------------------------------------------------------------------
efficiency = 0.80
inductance = 0.68 µH
frequency = 2.4 MHz
166
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16.2. High Power Applications
The dc-dc converter is designed to provide the system with 65 mW of output power, however, it can safely
provide up to 100 mW of output power without any risk of damage to the device. For high power applica-
tions, the system should be carefully designed to prevent unwanted VBAT and VDD_MCU/DC+ Supply
Monitor resets, which are more likely to occur when the dc-dc converter output power exceeds 65mW. In
addition, output power above 65 mW causes the dc-dc converter to have relaxed output regulation, high
output ripple and more analog noise. At high output power, an inductor with low DC resistance should be
chosen in order to minimize power loss and maximize efficiency.
The combination of high output power and low input voltage will result in very high peak and average
inductor currents. If the power supply has a high internal resistance, the transient voltage on the VBAT ter-
minal could drop below 0.9 V and trigger a VBAT Supply Monitor Reset, even if the open-circuit voltage is
well above the 0.9 V threshold. While this problem is most often associated with operation from very small
batteries or batteries that are near the end of their useful life, it can also occur when using bench power
supplies that have a slow transient response; the supply’s display may indicate a voltage above 0.9 V, but
the minimum voltage on the VBAT pin may be lower. A similar problem can occur at the output of the dc-dc
converter: using the default low current limit setting (125 mA) can trigger V Supply Monitor resets if there
DD
is a high transient load current, particularly if the programmed output voltage is at or near 1.8 V.
16.3. Pulse Skipping Mode
The dc-dc converter allows the user to set the minimum pulse width such that if the duty cycle needs to
decrease below a certain width in order to maintain regulation, an entire "clock pulse" will be skipped.
Pulse skipping can provide substantial power savings, particularly at low values of load current. The con-
verter will continue to maintain a minimum output voltage at its programmed value when pulse skipping is
employed, though the output voltage ripple can be higher. Another consideration is that the dc-dc will oper-
ate with pulse-frequency modulation rather than pulse-width modulation, which makes the switching fre-
quency spectrum less predictable; this could be an issue if the dc-dc converter is used to power a radio.
Figure 4.5 and Figure 4.6 on page 49 and page 50 show the effect of pulse skipping on power consump-
tion.
16.4. Enabling the DC-DC Converter
On power-on reset, the state of the DCEN pin is sampled to determine if the device will power up in one-
cell or two-cell mode. In two-cell mode, the dc-dc converter always remains disabled. In one-cell mode, the
dc-dc converter remains disabled in Sleep Mode, and enabled in all other power modes. See Section
“14. Power Management” on page 151 for complete details on available power modes.
The dc-dc converter is enabled (one-cell mode) in hardware by placing a 0.68 µH inductor between DCEN
and VBAT. The dc-dc converter is disabled (two-cell mode) by shorting DCEN directly to GND. The DCEN
pin should never be left floating. Note that the device can only switch between one-cell and two-cell mode
during a power-on reset. See Section “18. Reset Sources” on page 175 for more information regarding
reset behavior.
Figure 16.2 shows the two dc-dc converter configuration options.
Rev. 1.0
167
Si1000/1/2/3/4/5
0.68 uH
1 uF
DC-DC Converter
Enabled
4.7 uF
0.9 to 1.8 V
Supply Voltage
GND_MCU/
VBAT GND/VBAT- DCEN
DC-
VDD_MCU/
DC+
(one-cell mode)
VBAT GND/VBAT- DCEN
GND_MCU/
DC-
DC-DC Converter
Disabled
VDD_MCU/
DC+
1.8 to 3.6 V
Supply Voltage
(two-cell mode)
Figure 16.2. DC-DC Converter Configuration Options
When the dc-dc converter “Enabled” configuration (one-cell mode) is chosen, the following guidelines
apply:
In most cases, the GND/VBAT– pin should not be externally connected to GND.
The 0.68 µH inductor should be placed as close as possible to the DCEN pin for maximum efficiency.
The 4.7 µF capacitor should be placed as close as possible to the inductor.
The current loop including GND/VBAT-, the 4.7 µF capacitor, the 0.68 µH inductor and the DCEN pin
should be made as short as possible to minimize capacitance.
The PCB traces connecting VDD_MCU/DC+ to the output capacitor and the output capacitor to
GND_MCU/DC– should be as short and as thick as possible in order to minimize parasitic inductance.
16.5. Minimizing Power Supply Noise
To minimize noise on the power supply lines, the GND/VBAT- and GND_MCU/DC- pins should be kept
separate, as shown in Figure 16.2; GND_MCU/DC- should be connected to the pc board ground plane.
The large decoupling capacitors in the input and output circuits ensure that each supply is relatively quiet
with respect to its own ground. However, connecting a circuit element "diagonally" (e.g., connecting an
external chip between VDD_MCU/DC+ and GND/VBAT-, or between VBAT and GND_MCU/DC-) can
result in high supply noise across that circuit element.
To accommodate situations in which ADC0 is sampling a signal that is referenced to one of the external
grounds, we recommend using the Analog Ground Reference (P0.1/AGND) option described in Section
5.12. This option prevents any voltage differences between the internal chip ground and the external
grounds from modulating the ADC input signal. If this option is enabled, the P0.1 pin should be tied to the
168
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Si1000/1/2/3/4/5
ground reference of the external analog input signal. When using the ADC with the dc-dc converter, we
also recommend enabling the SYNC bit in the DC0CN register to minimize interference.
These general guidelines provide the best performance in most applications, though some situations may
benefit from experimentation to eliminate any residual noise issues. Examples might include tying the
grounds together, using additional low-inductance decoupling caps in parallel with the recommended ones,
investigating the effects of different dc-dc converter settings, etc.
16.6. Selecting the Optimum Switch Size
The dc-dc converter has two built-in switches (the diode bypass switch and duty cycle control switch). To
maximize efficiency, one of two switch sizes may be selected. The large switches are ideal for carrying
high currents and the small switches are ideal for low current applications. The ideal switchover point to
switch from the small switches to the large switches varies with the programmed output voltage. At an out-
put voltage of 2 V, the ideal switchover point is at approximately 4 mA total output current. At an output
voltage of 3 V, the ideal switchover point is at approximately 8 mA total output current.
16.7. DC-DC Converter Clocking Options
The dc-dc converter may be clocked from its internal oscillator, or from any system clock source, select-
able by the CLKSEL bit (DC0CF.0). The dc-dc converter internal oscillator frequency is approximately
2.4 MHz. For a more accurate clock source, the system clock, or a divided version of the system clock may
be used as the dc-dc clock source. The dc-dc converter has a built in clock divider (configured using
DC0CF[6:5]) which allows any system clock frequency over 1.6 MHz to generate a valid clock in the range
of 1.6 to 3.2 MHz.
When the precision internal oscillator is selected as the system clock source, the OSCICL register may be
used to fine tune the oscillator frequency and the dc-dc converter clock. The oscillator frequency should
only be decreased since it is factory calibrated at its maximum frequency. The minimum frequency which
can be reached by the oscillator after taking into account process variations is approximately 16 MHz. The
system clock routed to the dc-dc converter clock divider also may be inverted by setting the CLKINV bit
(DC0CF.3) to logic 1. These options can be used to minimize interference in noise sensitive applications.
16.8. DC-DC Converter Behavior in Sleep Mode
When the Si1000/1/2/3/4/5 devices are placed in Sleep mode, the dc-dc converter is disabled, and the
VDD_MCU/DC+ output is internally connected to VBAT by default. This behavior ensures that the GPIO
pins are powered from a low-impedance source during sleep mode. If the GPIO pins are not used as
inputs or outputs during sleep mode, then the VDD_MCU/DC+ output can be made to float during Sleep
mode by setting the VDDSLP bit in the DC0CF register to 1.
Setting this bit can provide power savings in two ways. First, if the sleep interval is relatively short and the
VDD_MCU/DC+ load current (include leakage currents) is negligible, then the capacitor on
VDD_MCU/DC+ will maintain the output voltage near the programmed value, which means that the
VDD_MCU/DC+ capacitor will not need to be recharged upon every wake up event. The second power
advantage is that internal or external low-power circuits that require more than 1.8 V can continue to func-
tion during Sleep mode without operating the dc-dc converter, powered by the energy stored in the 1 µF
output decoupling capacitor. For example, the Si1004/5 comparators require about 0.4 µA when operating
in their lowest power mode. If the dc-dc converter output were increased to 3.3 V just before putting the
device into Sleep mode, then the comparator could be powered for more than 3 seconds before the output
voltage dropped to 1.8 V. In this example, the overall energy consumption would be much lower than if the
dc-dc converter were kept running to power the comparator.
If the load current on VDD_MCU/DC+ is high enough to discharge the VDD_MCU/DC+ capacitance to a
voltage lower than VBAT during the sleep interval, an internal diode will prevent VDD_MCU/DC+ from
dropping more than a few hundred millivolts below VBAT. There may be some additional leakage current
Rev. 1.0
169
Si1000/1/2/3/4/5
from VBAT to ground when the VDD_MCU/DC+ level falls below VBAT, but this leakage current should be
small compared to the current from VDD_MCU/DC+.
The amount of time that it takes for a device configured in one-cell mode to wake up from Sleep mode
depends on a number of factors, including the dc-dc converter clock speed, the settings of the SWSEL and
ILIMIT bits, the battery internal resistance, the load current, and the difference between the VBAT voltage
level and the programmed output voltage. The wake up time can be as short as 2 µs, though it is more
commonly in the range of 5 to 10 µs, and it can exceed 50 µs under extreme conditions.
See Section “14. Power Management” on page 151 for more information about sleep mode.
170
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16.9. DC-DC Converter Register Descriptions
The SFRs used to configure the dc-dc converter are described in the following register descriptions. The
reset values for these registers can be used as-is in most systems; therefore, no software intervention or
initialization is required.
SFR Definition 16.1. DC0CN: DC-DC Converter Control
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
MINPW
R/W
SWSEL
R/W
Reserved
R/W
SYNC
R/W
VSEL
R/W
0
0
1
0
0
0
0
1
SFR Page = 0x0; SFR Address = 0x97
Bit
Name
Function
7:6
MINPW[1:0]
DC-DC Converter Minimum Pulse Width.
Specifies the minimum pulse width.
00: No minimum duty cycle.
01: Minimum pulse width is 20 ns.
10: Minimum pulse width is 40 ns.
11: Minimum pulse width is 80 ns.
5
SWSEL
DC-DC Converter Switch Select.
Selects one of two possible converter switch sizes to maximize efficiency.
0: The large switches are selected (best efficiency for high output currents).
1: The small switches are selected (best efficiency for low output currents).
4
3
Reserved Always Write to 0.
SYNC
ADC0 Synchronization Enable.
When synchronization is enabled, the ADC0SC[4:0] bits in the ADC0CF register
must be set to 00000b. Behavior as described is valid in REVC and later devices.
0: The ADC is not synchronized to the dc-dc converter.
1: The ADC is synchronized to the dc-dc converter. ADC0 tracking is performed
during the longest quiet time of the dc-dc converter switching cycle and ADC0 SAR
clock is also synchronized to the dc-dc converter switching cycle.
2:0
VSEL[2:0]
DC-DC Converter Output Voltage Select.
Specifies the target output voltage.
000: Target output voltage is 1.8 V.
001: Target output voltage is 1.9 V.
010: Target output voltage is 2.0 V.
011: Target output voltage is 2.1 V.
100: Target output voltage is 2.4 V.
101: Target output voltage is 2.7 V.
110: Target output voltage is 3.0 V.
111: Target output voltage is 3.3 V.
Rev. 1.0
171
Si1000/1/2/3/4/5
SFR Definition 16.2. DC0CF: DC-DC Converter Configuration
Bit
7
6
5
4
3
2
ILIMIT
R/W
0
1
0
Name Reserved
CLKDIV[1:0]
AD0CKINV CLKINV
VDDSLP CLKSEL
Type
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
SFR Page = 0x0; SFR Address = 0x96
Bit
Name
Function
7
Reserved Read = 0b; Must write 0b.
6:5 CLKDIV[1:0]
DC-DC Clock Divider.
Divides the dc-dc converter clock when the system clock is selected as the clock
source for dc-dc converter. These bits are ignored when the dc-dc converter is
clocked from its local oscillator.
00: The dc-dc converter clock is system clock divided by 1.
01: The dc-dc converter clock is system clock divided by 2.
10: The dc-dc converter clock is system clock divided by 4.
11: The dc-dc converter clock is system clock divided by 8.
4
AD0CKINV ADC0 Clock Inversion (Clock Invert During Sync).
Inverts the ADC0 SAR clock derived from the dc-dc converter clock when the SYNC
bit (DC0CN.3) is enabled. This bit is ignored when the SYNC bit is set to zero.
0: ADC0 SAR clock is inverted.
1: ADC0 SAR clock is not inverted.
3
2
CLKINV
DC-DC Converter Clock Invert.
Inverts the system clock used as the input to the dc-dc clock divider.
0: The dc-dc converter clock is not inverted.
1: The dc-dc converter clock is inverted.
ILIMIT
Peak Current Limit Threshold.
Sets the threshold for the maximum allowed peak inductor current. See Table 16.1
for peak inductor current levels.
0: Peak inductor current is set at a lower level.
1: Peak inductor current is set at a higher level.
1
0
VDDSLP
VDD_MCU/DC+ Sleep Mode Connection.
Specifies the power source for VDD_MCU/DC+ in Sleep Mode when the dc-dc con-
verter is enabled.
0: VDD_MCU/DC+ connected to VBAT in Sleep Mode.
1: VDD_MCU/DC+ is floating in Sleep Mode.
CLKSEL
DC-DC Converter Clock Source Select.
Specifies the dc-dc converter clock source.
0: The dc-dc converter is clocked from its local oscillator.
1: The dc-dc converter is clocked from the system clock.
172
Rev. 1.0
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16.10. DC-DC Converter Specifications
See Table 4.14 on page 65 for a detailed listing of dc-dc converter specifications.
Rev. 1.0
173
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17. Voltage Regulator (VREG0)
Si1000/1/2/3/4/5 devices include an internal voltage regulator (VREG0) to regulate the internal core supply
to 1.8 V from a VDD_MCU supply of 1.8 to 3.6 V. Electrical characteristics for the on-chip regulator are
specified in the Electrical Specifications chapter.
The REG0CN register allows the Precision Oscillator Bias to be disabled, saving approximately 80 µA in
all non-Sleep power modes. This bias should only be disabled when the precision oscillator is not being
used.
The internal regulator (VREG0) is disabled when the device enters Sleep Mode and remains enabled
when the device enters Suspend Mode. See Section “14. Power Management” on page 151 for complete
details about low power modes.
SFR Definition 17.1. REG0CN: Voltage Regulator Control
Bit
7
6
5
4
3
2
1
0
Reserved Reserved OSCBIAS
Reserved
Name
Type
Reset
R
0
R/W
0
R/W
0
R/W
1
R
0
R
0
R
0
R/W
0
SFR Page = 0x0; SFR Address = 0xC9
Bit
Name
Function
7
Unused Read = 0b. Write = Don’t care.
Reserved Read = 0b. Must Write 0b.
OSCBIAS Precision Oscillator Bias.
6:5
4
When set to 1, the bias used by the precision oscillator is forced on. If the precision
oscillator is not being used, this bit may be cleared to 0 to save approximately 80 µA
of supply current in all non-Sleep power modes. If disabled then re-enabled, the pre-
cision oscillator bias requires 4 µs of settling time.
3:1
0
Unused Read = 000b. Write = Don’t care.
Reserved Read = 0b. Must Write 0b.
17.1. Voltage Regulator Electrical Specifications
See Table 4.15 on page 65 for detailed Voltage Regulator Electrical Specifications.
174
Rev. 1.0
Si1000/1/2/3/4/5
18. Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this
reset state, the following occur:
CIP-51 halts program execution
Special Function Registers (SFRs) are initialized to their defined reset values
External Port pins are forced to a known state
Interrupts and timers are disabled
All SFRs are reset to the predefined values noted in the SFR descriptions. The contents of RAM are unaf-
fected during a reset; any previously stored data is preserved as long as power is not lost. Since the stack
pointer SFR is reset, the stack is effectively lost, even though the data on the stack is not altered.
The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pullups are enabled dur-
ing and after the reset. For V
Monitor and power-on resets, the RST pin is driven low until the device
DD
exits the reset state.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to an internal
oscillator. Refer to Section “19. Clocking Sources” on page 182 for information on selecting and configur-
ing the system clock source. The Watchdog Timer is enabled with the system clock divided by 12 as its
clock source (Section “28.4. Watchdog Timer Mode” on page 363 details the use of the Watchdog Timer).
Program execution begins at location 0x0000.
VDD_MCU/DC+
VBAT
*On Si1000/1/2/3 devices,
VBAT is internally
connected to VDD_MCU.
Power On
Reset
Supply
Monitor
(wired-OR)
Comparator 0
Px.x
Px.x
+
-
0
RST
+
-
Enable
C0RSEF
SmaRTClock
RTC0RE
Reset
Funnel
Missing
Clock
Detector
(one-
shot)
EN
PCA
WDT
(Software Reset)
SWRSF
EN
Illegal Flash
Operation
System
Clock
CIP-51
System Reset
System Reset
Microcontroller
Core
Power Management
Block (PMU0)
Power-On Reset
Reset
Extended Interrupt
Handler
Figure 18.1. Reset Sources
Rev. 1.0
175
Si1000/1/2/3/4/5
18.1. Power-On (VBAT Supply Monitor) Reset
During power-up, the device is held in a reset state and the RST pin is driven low until V
settles above
BAT
V
V
. An additional delay occurs before the device is released from reset; the delay decreases as the
POR
ramp time increases (V
ramp time is defined as how fast V
ramps from 0 V to V
).
=
BAT
BAT
BAT
POR
Figure 18.3 plots the power-on and V
monitor reset timing. For valid ramp times (less than 3 ms), the
DD
power-on reset delay (T
3.6 V).
) is typically 3 ms (V
= 0.9 V), 7 ms (V
= 1.8 V), or 15 ms (V
BAT
PORDelay
BAT
BAT
Note: The maximum VDD ramp time is 3 ms; slower ramp times may cause the device to be released from reset
before VBAT reaches the VPOR level.
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000), software can
read the PORSF flag to determine if a power-up was the cause of reset. The contents of internal data
memory should be assumed to be undefined after a power-on reset.
Note: Si1000/1/2/3 have the VBAT signal internally connected to VDD_MCU.
VBAT
VPOR
~0.8
0.6
~0.5
See specification
table for min/max
voltages.
t
RST
Logic HIGH
Logic LOW
TPORDelay
TPORDelay
Power-On
Reset
Power-On
Reset
Figure 18.2. Power-Fail Reset Timing Diagram
176
Rev. 1.0
Si1000/1/2/3/4/5
18.2. Power-Fail (VDD_MCU Supply Monitor) Reset
Si1000/1/2/3/4/5 devices have a VDD_MCU Supply Monitor that is enabled and selected as a reset source
after each power-on or power-fail reset. When enabled and selected as a reset source, any power down
transition or power irregularity that causes VDD_MCU to drop below V
will cause the RST pin to be
RST
driven low and the CIP-51 will be held in a reset state (see Figure 18.3). When VDD_MCU returns to a
level above V , the CIP-51 will be released from the reset state.
RST
After a power-fail reset, the PORSF flag reads 1, the contents of RAM invalid, and theVDD_MCU supply
monitor is enabled and selected as a reset source. The enable state of the VDD_MCU supply monitor and
its selection as a reset source is only altered by power-on and power-fail resets. For example, if the
VDD_MCU supply monitor is de-selected as a reset source and disabled by software, then a software
reset is performed, the VDD_MCU supply monitor will remain disabled and de-selected after the reset.
In battery-operated systems, the contents of RAM can be preserved near the end of the battery’s usable
life if the device is placed in sleep mode prior to a power-fail reset occurring. When the device is in sleep
mode, the power-fail reset is automatically disabled and the contents of RAM are preserved as long as the
VBAT supply does not fall below V
. A large capacitor can be used to hold the power supply voltage
POR
above V
while the user is replacing the battery. Upon waking from sleep mode, the enable and reset
POR
source select state of the VDD_MCU supply monitor are restored to the value last set by the user.
To allow software early notification that a power failure is about to occur, the VDDOK bit is cleared when
the VDD_MCU supply falls below the V
threshold. The VDDOK bit can be configured to generate an
WARN
interrupt. See Section “12. Interrupt Handler” on page 129 for more details.
Important Note: To protect the integrity of Flash contents, the VDD_MCU supply monitor must be
enabled and selected as a reset source if software contains routines which erase or write Flash
memory. If the VDD_MCU supply monitor is not enabled, any erase or write performed on Flash memory
will cause a Flash Error device reset.
VDD_MCU/DC+
VWARN
VRST
VBAT
VPOR
t
VDDOK
SLEEP
RST
Note: Wakeup signal
required after new
battery insertion
Sleep Mode
RAM Retained - No Reset
Active Mode
Power-Fail Reset
Figure 18.3. Power-Fail Reset Timing Diagram
Rev. 1.0
177
Si1000/1/2/3/4/5
Important Notes:
The Power-on Reset (POR) delay is not incurred after a VDD_MCU supply monitor reset. See Section
“4. Electrical Characteristics” on page 40 for complete electrical characteristics of the VDD_MCU
monitor.
Software should take care not to inadvertently disable the V Monitor as a reset source when writing
DD
to RSTSRC to enable other reset sources or to trigger a software reset. All writes to RSTSRC should
explicitly set PORSF to '1' to keep the V Monitor enabled as a reset source.
DD
The VDD_MCU supply monitor must be enabled before selecting it as a reset source. Selecting the
VDD_MCU supply monitor as a reset source before it has stabilized may generate a system reset. In
systems where this reset would be undesirable, a delay should be introduced between enabling the
VDD_MCU supply monitor and selecting it as a reset source. See Section “4. Electrical Characteristics”
on page 40 for minimum VDD_MCU Supply Monitor turn-on time. No delay should be introduced in
systems where software contains routines that erase or write Flash memory. The procedure for
enabling the VDD_MCU supply monitor and selecting it as a reset source is shown below:
1. Enable the VDD_MCU Supply Monitor (VDMEN bit in VDM0CN = 1).
2. Wait for the VDD_MCU Supply Monitor to stabilize (optional).
3. Select the VDD_MCU Supply Monitor as a reset source (PORSF bit in RSTSRC = 1).
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SFR Definition 18.1. VDM0CN: VDD_MCU Supply Monitor Control
Bit
7
6
5
4
3
2
1
0
VDMEN VDDSTAT VDDOK Reserved Reserved Reserved
Name
Type
Reset
R/W
1
R
R
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Varies
Varies
SFR Page = 0x0; SFR Address = 0xFF
Bit
Name
Function
7
VDMEN
VDD_MCU Supply Monitor Enable.
This bit turns the VDD_MCU supply monitor circuit on/off. The VDD_MCU Supply
Monitor cannot generate system resets until it is also selected as a reset source in
register RSTSRC (SFR Definition 18.2).
0: VDD_MCU Supply Monitor Disabled.
1: VDD_MCU Supply Monitor Enabled.
6
5
VDDSTAT
VDDOK
VDD_MCU Supply Status.
This bit indicates the current power supply status.
0: VDD_MCU is at or below the V
1: VDD_MCU is above the V
threshold.
threshold.
RST
RST
VDD_MCU Supply Status (Early Warning).
This bit indicates the current power supply status.
0: VDD_MCU is at or below the V
threshold.
WARN
1: VDD_MCU is above the V
monitor threshold.
WARN
4:2
1:0
Reserved
Unused
Read = 000b. Must Write 000b.
Read = 00b. Write = Don’t Care.
18.3. External Reset
The external RST pin provides a means for external circuitry to force the device into a reset state. Assert-
ing an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST
pin may be necessary to avoid erroneous noise-induced resets. See Table 4.4 for complete RST pin spec-
ifications. The external reset remains functional even when the device is in the low power Suspend and
Sleep Modes. The PINRSF flag (RSTSRC.0) is set on exit from an external reset.
18.4. Missing Clock Detector Reset
The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system
clock remains high or low for more than 100 µs, the one-shot will time out and generate a reset. After a
MCD reset, the MCDRSF flag (RSTSRC.2) will read 1, signifying the MCD as the reset source; otherwise,
this bit reads 0. Writing a 1 to the MCDRSF bit enables the Missing Clock Detector; writing a 0 disables it.
The missing clock detector reset is automatically disabled when the device is in the low power Suspend or
Sleep mode. Upon exit from either low power state, the enabled/disabled state of this reset source is
restored to its previous value. The state of the RST pin is unaffected by this reset.
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18.5. Comparator0 Reset
Comparator0 can be configured as a reset source by writing a 1 to the C0RSEF flag (RSTSRC.5).
Comparator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on
chatter on the output from generating an unwanted reset. The Comparator0 reset is active-low: if the non-
inverting input voltage (on CP0+) is less than the inverting input voltage (on CP0-), the device is put into
the reset state. After a Comparator0 reset, the C0RSEF flag (RSTSRC.5) will read 1 signifying
Comparator0 as the reset source; otherwise, this bit reads 0. The Comparator0 reset source remains func-
tional even when the device is in the low power Suspend and Sleep states as long as Comparator0 is also
enabled as a wake-up source. The state of the RST pin is unaffected by this reset.
18.6. PCA Watchdog Timer Reset
The programmable Watchdog Timer (WDT) function of the Programmable Counter Array (PCA) can be
used to prevent software from running out of control during a system malfunction. The PCA WDT function
can be enabled or disabled by software as described in Section “28.4. Watchdog Timer Mode” on
page 363; the WDT is enabled and clocked by SYSCLK / 12 following any reset. If a system malfunction
prevents user software from updating the WDT, a reset is generated and the WDTRSF bit (RSTSRC.5) is
set to 1. The PCA Watchdog Timer reset source is automatically disabled when the device is in the low
power Suspend or Sleep mode. Upon exit from either low power state, the enabled/disabled state of this
reset source is restored to its previous value.The state of the RST pin is unaffected by this reset.
18.7. Flash Error Reset
If a Flash read/write/erase or program read targets an illegal address, a system reset is generated. This
may occur due to any of the following:
A Flash write or erase is attempted above user code space. This occurs when PSWE is set to 1 and a
MOVX write operation targets an address above the Lock Byte address.
A Flash read is attempted above user code space. This occurs when a MOVC operation targets an
address above the Lock Byte address.
A Program read is attempted above user code space. This occurs when user code attempts to branch
to an address above the Lock Byte address.
A Flash read, write or erase attempt is restricted due to a Flash security setting (see Section
“13.3. Security Options” on page 143).
A Flash write or erase is attempted while the V Monitor is disabled.
DD
The FERROR bit (RSTSRC.6) is set following a Flash error reset. The state of the RST pin is unaffected by
this reset.
18.8. SmaRTClock (Real Time Clock) Reset
The SmaRTClock can generate a system reset on two events: SmaRTClock Oscillator Fail or SmaRT-
Clock Alarm. The SmaRTClock Oscillator Fail event occurs when the SmaRTClock Missing Clock Detector
is enabled and the SmaRTClock clock is below approximately 20 kHz. A SmaRTClock alarm event occurs
when the SmaRTClock Alarm is enabled and the SmaRTClock timer value matches the ALARMn regis-
ters. The SmaRTClock can be configured as a reset source by writing a 1 to the RTC0RE flag (RST-
SRC.7). The SmaRTClock reset remains functional even when the device is in the low power Suspend or
Sleep mode. The state of the RST pin is unaffected by this reset.
18.9. Software Reset
Software may force a reset by writing a 1 to the SWRSF bit (RSTSRC.4). The SWRSF bit will read 1 fol-
lowing a software forced reset. The state of the RST pin is unaffected by this reset.
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SFR Definition 18.2. RSTSRC: Reset Source
Bit
7
6
5
4
3
2
1
0
RTC0RE FERROR C0RSEF
SWRSF WDTRSF MCDRSF
PORSF
PINRSF
Name
Type
Reset
R/W
R
R/W
R/W
R
R/W
R/W
R
Varies
Varies
Varies
Varies
Varies
Varies
Varies
Varies
SFR Page = 0x0; SFR Address = 0xEF.
Bit
Name
Description
Write
Read
7
RTC0RE SmaRTClock Reset Enable 0: Disable SmaRTClock
Set to 1 if SmaRTClock
alarm or oscillator fail
caused the last reset.
and Flag
as a reset source.
1: Enable SmaRTClock as
a reset source.
6
5
FERROR Flash Error Reset Flag.
N/A
Set to 1 if Flash
read/write/erase error
caused the last reset.
C0RSEF Comparator0 Reset Enable 0: Disable Comparator0 as Set to 1 if Comparator0
and Flag.
a reset source.
caused the last reset.
1: Enable Comparator0 as
a reset source.
4
3
2
SWRSF Software Reset Force and
Writing a 1 forces a sys-
tem reset.
Set to 1 if last reset was
caused by a write to
SWRSF.
Flag.
WDTRSF Watchdog Timer Reset Flag. N/A
Set to 1 if Watchdog Timer
overflow caused the last
reset.
MCDRSF Missing Clock Detector
0: Disable the MCD.
Set to 1 if Missing Clock
Detector timeout caused
the last reset.
(MCD) Enable and Flag.
1: Enable the MCD.
The MCD triggers a reset
if a missing clock condition
is detected.
1
PORSF Power-On / Power-Fail
0: Disable the VDD_MCU Set to 1 anytime a power-
Reset Flag, and Power-Fail Supply Monitor as a reset on or V monitor reset
DD
2
Reset Enable.
source.
occurs.
1: Enable the VDD_MCU
Supply Monitor as a reset
3
source.
0
PINRSF HW Pin Reset Flag.
N/A
Set to 1 if RST pin caused
the last reset.
Notes:
1. It is safe to use read-modify-write operations (ORL, ANL, etc.) to enable or disable specific interrupt sources.
2. If PORSF read back 1, the value read from all other bits in this register are indeterminate.
3. Writing a 1 to PORSF before the VDD_MCU Supply Monitor is stabilized may generate a system reset.
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19. Clocking Sources
Si1000/1/2/3/4/5 devices include a programmable precision internal oscillator, an external oscillator drive
circuit, a low power internal oscillator, and a SmaRTClock real time clock oscillator. The precision internal
oscillator can be enabled/disabled and calibrated using the OSCICN and OSCICL registers, as shown in
Figure 19.1. The external oscillator can be configured using the OSCXCN register. The low power internal
oscillator is automatically enabled and disabled when selected and deselected as a clock source. SmaRT-
Clock operation is described in the SmaRTClock oscillator chapter.
The system clock (SYSCLK) can be derived from the precision internal oscillator, external oscillator, low
power internal oscillator, or SmaRTClock oscillator. The global clock divider can generate a system clock
that is 1, 2, 4, 8, 16, 32, 64, or 128 times slower that the selected input clock source. Oscillator electrical
specifications can be found in the Electrical Specifications Chapter.
OSCICL
OSCICN
CLKSEL
Option 2
VDD
Option 3
XTAL2
XTAL2
EN
Precision
Internal Oscillator
Precision Internal Oscillator
External Oscillator
CLKRDY
Option 1
XTAL1
External
Oscillator
10M
Drive Circuit
n
SYSCLK
Low Power Internal Oscillator
smaRTClock Oscillator
XTAL2
Clock Divider
Option 4
XTAL2
smaRTClock
Oscillator
Low Power
Internal Oscillator
OSCXCN
Figure 19.1. Clocking Sources Block Diagram
The proper way of changing the system clock when both the clock source and the clock divide value are
being changed is as follows:
If switching from a fast “undivided” clock to a slower “undivided” clock:
1. Change the clock divide value.
2. Poll for CLKRDY > 1.
3. Change the clock source.
If switching from a slow “undivided” clock to a faster “undivided” clock:
1. Change the clock source.
2. Change the clock divide value.
3. Poll for CLKRDY > 1.
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19.1. Programmable Precision Internal Oscillator
All Si1000/1/2/3/4/5 devices include a programmable precision internal oscillator that may be selected as
the system clock. OSCICL is factory calibrated to obtain a 24.5 MHz frequency. See Section “4. Electrical
Characteristics” on page 40 for complete oscillator specifications.
The precision oscillator supports a spread spectrum mode which modulates the output frequency in order
to reduce the EMI generated by the system. When enabled (SSE = 1), the oscillator output frequency is
modulated by a stepped triangle wave whose frequency is equal to the oscillator frequency divided by 384
(63.8 kHz using the factory calibration). The deviation from the nominal oscillator frequency is +0%, –1.6%,
and the step size is typically 0.26% of the nominal frequency. When using this mode, the typical average
oscillator frequency is lowered from 24.5 MHz to 24.3 MHz.
19.2. Low Power Internal Oscillator
All Si1000/1/2/3/4/5 devices include a low power internal oscillator that defaults as the system clock after a
system reset. The low power internal oscillator frequency is 20 MHz ± 10% and is automatically enabled
when selected as the system clock and disabled when not in use. See Section “4. Electrical Characteris-
tics” on page 40 for complete oscillator specifications.
19.3. External Oscillator Drive Circuit
All Si1000/1/2/3/4/5 devices include an external oscillator circuit that may drive an external crystal, ceramic
resonator, capacitor, or RC network. A CMOS clock may also provide a clock input. Figure 19.1 shows a
block diagram of the four external oscillator options. The external oscillator is enabled and configured
using the OSCXCN register.
The external oscillator output may be selected as the system clock or used to clock some of the digital
peripherals (e.g., Timers, PCA, etc.). See the data sheet chapters for each digital peripheral for details.
See Section “4. Electrical Characteristics” on page 40 for complete oscillator specifications.
19.3.1. External Crystal Mode
If a crystal or ceramic resonator is used as the external oscillator, the crystal/resonator and a 10 Mresis-
tor must be wired across the XTAL1 and XTAL2 pins as shown in Figure 19.1, Option 1. Appropriate load-
ing capacitors should be added to XTAL1 and XTAL2, and both pins should be configured for analog I/O
with the digital output drivers disabled.
Figure 19.2 shows the external oscillator circuit for a 20 MHz quartz crystal with a manufacturer recom-
mended load capacitance of 12.5 pF. Loading capacitors are "in series" as seen by the crystal and "in par-
allel" with the stray capacitance of the XTAL1 and XTAL2 pins. The total value of the each loading
capacitor and the stray capacitance of each XTAL pin should equal 12.5pF x 2 = 25 pF. With a stray capac-
itance of 10 pF per pin, the 15 pF capacitors yield an equivalent series capacitance of 12.5 pF across the
crystal.
Note: The recommended load capacitance depends upon the crystal and the manufacturer. Please refer to the crystal
data sheet when completing these calculations.
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15 pF
XTAL1
XTAL2
10 M
25 MHz
15 pF
Figure 19.2. 25 MHz External Crystal Example
Important Note on External Crystals: Crystal oscillator circuits are quite sensitive to PCB layout. The
crystal should be placed as close as possible to the XTAL pins on the device. The traces should be as
short as possible and shielded with ground plane from any other traces which could introduce noise or
interference.
When using an external crystal, the external oscillator drive circuit must be configured by software for Crys-
tal Oscillator Mode or Crystal Oscillator Mode with divide by 2 stage. The divide by 2 stage ensures that the
clock derived from the external oscillator has a duty cycle of 50%. The External Oscillator Frequency Con-
trol value (XFCN) must also be specified based on the crystal frequency. The selection should be based on
Table 19.1. For example, a 25 MHz crystal requires an XFCN setting of 111b.
Table 19.1. Recommended XFCN Settings for Crystal Mode
XFCN
Crystal Frequency
Bias Current
Typical Supply Current
(VDD = 2.4 V)
000
001
010
011
100
101
110
111
f 20 kHz
0.5 µA
1.5 µA
4.8 µA
14 µA
3.0 µA, f = 32.768 kHz
4.8 µA, f = 32.768 kHz
9.6 µA, f = 32.768 kHz
28 µA, f = 400 kHz
71 µA, f = 400 kHz
193 µA, f = 400 kHz
940 µA, f = 8 MHz
20 kHz f 58 kHz
58 kHz f 155 kHz
155 kHz f 415 kHz
415 kHz f 1.1 MHz
1.1 MHz f 3.1 MHz
3.1 MHz f 8.2 MHz
8.2 MHz f 25 MHz
40 µA
120 µA
550 µA
2.6 mA
3.9 mA, f = 25 MHz
When the crystal oscillator is first enabled, the external oscillator valid detector allows software to deter-
mine when the external system clock has stabilized. Switching to the external oscillator before the crystal
oscillator has stabilized can result in unpredictable behavior. The recommended procedure for starting the
crystal is:
1. Configure XTAL1 and XTAL2 for analog I/O and disable the digital output drivers.
2. Configure and enable the external oscillator.
3. Poll for XTLVLD => 1.
4. Switch the system clock to the external oscillator.
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19.3.2. External RC Mode
If an RC network is used as the external oscillator, the circuit should be configured as shown in
Figure 19.1, Option 2. The RC network should be added to XTAL2, and XTAL2 should be configured for
analog I/O with the digital output drivers disabled. XTAL1 is not affected in RC mode.
The capacitor should be no greater than 100 pF; however for very small capacitors, the total capacitance
may be dominated by parasitic capacitance in the PCB layout. The resistor should be no smaller than
10k. The oscillation frequency can be determined by the following equation:
1.23 103
f = ------------------------
R C
where
f = frequency of clock in MHzR = pull-up resistor value in k
V
= power supply voltage in VoltsC = capacitor value on the XTAL2 pin in pF
DD
To determine the required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register,
first select the RC network value to produce the desired frequency of oscillation. For example, if the fre-
quency desired is 100 kHz, let R = 246 k and C = 50 pF:
1.23 103
R C 246 50
1.23 103
f = ------------------------ = ------------------------ = 100 kHz
where
f = frequency of clock in MHz; R = pull-up resistor value in k
= power supply voltage in Volts; C = capacitor value on the XTAL2 pin in pF
V
DD
Referencing Table 19.2, the recommended XFCN setting is 010.
Table 19.2. Recommended XFCN Settings for RC and C modes
XFCN
Approximate
K Factor (C Mode)
Typical Supply Current/ Actual
Frequency Range (RC
and C Mode)
Measured Frequency
(C Mode, VDD = 2.4 V)
000
001
010
011
100
101
110
111
f 25 kHz
K Factor = 0.87
K Factor = 2.6
K Factor = 7.7
K Factor = 22
K Factor = 65
K Factor = 180
K Factor = 664
K Factor = 1590
3.0 µA, f = 11 kHz, C = 33 pF
5.5 µA, f = 33 kHz, C = 33 pF
13 µA, f = 98 kHz, C = 33 pF
32 µA, f = 270 kHz, C = 33 pF
82 µA, f = 310 kHz, C = 46 pF
242 µA, f = 890 kHz, C = 46 pF
1.0 mA, f = 2.0 MHz, C = 46 pF
4.6 mA, f = 6.8 MHz, C = 46 pF
25 kHz f 50 kHz
50 kHz f 100 kHz
100 kHz f 200 kHz
200 kHz f 400 kHz
400 kHz f 800 kHz
800 kHz f 1.6 MHz
1.6 MHz f 3.2 MHz
When the RC oscillator is first enabled, the external oscillator valid detector allows software to determine
when oscillation has stabilized. The recommended procedure for starting the RC oscillator is:
1. Configure XTAL2 for analog I/O and disable the digital output drivers.
2. Configure and enable the external oscillator.
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3. Poll for XTLVLD > 1.
4. Switch the system clock to the external oscillator.
19.3.3. External Capacitor Mode
If a capacitor is used as the external oscillator, the circuit should be configured as shown in Figure 19.1,
Option 3. The capacitor should be added to XTAL2, and XTAL2 should be configured for analog I/O with
the digital output drivers disabled. XTAL1 is not affected in RC mode.
The capacitor should be no greater than 100 pF; however, for very small capacitors, the total capacitance
may be dominated by parasitic capacitance in the PCB layout. The oscillation frequency and the required
External Oscillator Frequency Control value (XFCN) in the OSCXCN Register can be determined by the
following equation:
KF
f = ---------------------
C VDD
where
f = frequency of clock in MHzR = pull-up resistor value in k
V
= power supply voltage in VoltsC = capacitor value on the XTAL2 pin in pF
DD
Below is an example of selecting the capacitor and finding the frequency of oscillation Assume V = 3.0 V
DD
and f = 150 kHz:
KF
f = ---------------------
C VDD
KF
0.150 MHz = -----------------
C 3.0
Since a frequency of roughly 150 kHz is desired, select the K Factor from Table 19.2 as KF = 22:
22
0.150 MHz = -----------------------
C 3.0 V
22
C = ----------------------------------------------
0.150 MHz 3.0 V
C = 48.8 pF
Therefore, the XFCN value to use in this example is 011 and C is approximately 50 pF.
The recommended startup procedure for C mode is the same as RC mode.
19.3.4. External CMOS Clock Mode
If an external CMOS clock is used as the external oscillator, the clock should be directly routed into XTAL2.
The XTAL2 pin should be configured as a digital input. XTAL1 is not used in external CMOS clock mode.
The external oscillator valid detector will always return zero when the external oscillator is configured to
External CMOS Clock mode.
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19.4. Special Function Registers for Selecting and Configuring the System Clock
The clocking sources on Si1000/1/2/3/4/5 devices are enabled and configured using the OSCICN,
OSCICL, OSCXCN and the SmaRTClock internal registers. See Section “20. SmaRTClock (Real Time
Clock)” on page 190 for SmaRTClock register descriptions. The system clock source for the MCU can be
selected using the CLKSEL register. To minimize active mode current, the oneshot timer which sets Flash
read time should by bypassed when the system clock is greater than 10 MHz. See the FLSCL register
description for details.
The clock selected as the system clock can be divided by 1, 2, 4, 8, 16, 32, 64, or 128. When switching
between two clock divide values, the transition may take up to 128 cycles of the undivided clock source.
The CLKRDY flag can be polled to determine when the new clock divide value has been applied. The clock
divider must be set to "divide by 1" when entering Suspend or Sleep Mode.
The system clock source may also be switched on-the-fly. The switchover takes effect after one clock
period of the slower oscillator.
SFR Definition 19.1. CLKSEL: Clock Select
Bit
7
6
5
4
3
2
1
0
CLKRDY
CLKDIV[2:0]
CLKSEL[2:0]
Name
Type
Reset
R
0
R/W
0
R/W
1
R/W
1
R/W
0
R/W
1
R/W
0
R/W
0
SFR Page = All Pages; SFR Address = 0xA9
Bit
Name
Function
7
CLKRDY
System Clock Divider Clock Ready Flag.
0: The selected clock divide setting has not been applied to the system clock.
1: The selected clock divide setting has been applied to the system clock.
6:4
CLKDIV[2:0] System Clock Divider Bits.
Selects the clock division to be applied to the undivided system clock source.
000: System clock is divided by 1.
001: System clock is divided by 2.
010: System clock is divided by 4.
011: System clock is divided by 8.
100: System clock is divided by 16.
101: System clock is divided by 32.
110: System clock is divided by 64.
111: System clock is divided by 128.
Read = 0b. Must Write 0b.
3
Unused
2:0
CLKSEL[2:0] System Clock Select.
Selects the oscillator to be used as the undivided system clock source.
000: Precision Internal Oscillator.
001: External Oscillator.
010: Reserved.
011: SmaRTClock Oscillator.
1xx: Low Power Oscillator.
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SFR Definition 19.2. OSCICN: Internal Oscillator Control
Bit
7
6
5
4
3
2
1
0
IOSCEN
IFRDY
Reserved[5:0]
R/W R/W
Name
Type
Reset
R/W
0
R
0
R/W
0
R/W
0
R/W
1
R/W
1
1
1
SFR Page = 0x0; SFR Address = 0xB2
Bit
Name
Function
7
IOSCEN Internal Oscillator Enable.
0: Internal oscillator disabled.
1: Internal oscillator enabled.
6
Internal Oscillator Frequency Ready Flag.
IFRDY
0: Internal oscillator is not running at its programmed frequency.
1: Internal oscillator is running at its programmed frequency.
5:0
Reserved Read = 001111b. Must Write 001111b.
Note: It is recommended to use read-modify-write operations such as ORL and ANL to set or clear the enable bit of
this register.
SFR Definition 19.3. OSCICL: Internal Oscillator Calibration
Bit
7
6
5
4
3
2
1
0
SSE
OSCICL[6:0]
Name
Type
Reset
R/W
0
R
R/W
R/W
R/W
R/W
R/W
R/W
Varies
Varies
Varies
Varies
Varies
Varies
Varies
SFR Page = 0x0; SFR Address = 0xB3
Bit
Name
Function
7
Spread Spectrum Enable.
SSE
0: Spread Spectrum clock dithering disabled.
1: Spread Spectrum clock dithering enabled.
6:0
Internal Oscillator Calibration.
OSCICL
Factory calibrated to obtain a frequency of 24.5 MHz. Incrementing this register decreases the
oscillator frequency and decrementing this register increases the oscillator frequency. The
step size is approximately 1% of the calibrated frequency. The recommended calibration fre-
quency range is between 16 and 24.5 MHz.
Note: If the Precision Internal Oscillator is selected as the system clock, the following procedure should be used when
changing the value of the internal oscillator calibration bits.
1. Switch to a different clock source.
2. Disable the oscillator by writing OSCICN.7 to 0.
3. Change OSCICL to the desired setting.
4. Enable the oscillator by writing OSCICN.7 to 1.
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SFR Definition 19.4. OSCXCN: External Oscillator Control
Bit
7
6
5
4
3
2
1
0
XCLKVLD
XOSCMD[2:0]
Reserved
XFCN[2:0]
Name
Type
Reset
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Page = 0x0; SFR Address = 0xB1
Bit
Name
XCLKVLD External Oscillator Valid Flag.
Function
7
Provides External Oscillator status and is valid at all times for all modes of operation
except External CMOS Clock Mode and External CMOS Clock Mode with divide by
2. In these modes, XCLKVLD always returns 0.
0: External Oscillator is unused or not yet stable.
1: External Oscillator is running and stable.
6:4
XOSCMD External Oscillator Mode Bits.
Configures the external oscillator circuit to the selected mode.
00x: External Oscillator circuit disabled.
010: External CMOS Clock Mode.
011: External CMOS Clock Mode with divide by 2 stage.
100: RC Oscillator Mode.
101: Capacitor Oscillator Mode.
110: Crystal Oscillator Mode.
111: Crystal Oscillator Mode with divide by 2 stage.
3
Reserved Read = 0b. Must Write 0b.
2:0
XFCN
External Oscillator Frequency Control Bits.
Controls the external oscillator bias current.
000-111: See Table 19.1 on page 184 (Crystal Mode) or Table 19.2 on page 185 (RC
or C Mode) for recommended settings.
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20. SmaRTClock (Real Time Clock)
Si1000/1/2/3/4/5 devices include an ultra low power 32-bit SmaRTClock Peripheral (Real Time Clock) with
alarm. The SmaRTClock has a dedicated 32 kHz oscillator that can be configured for use with or without a
crystal. No external resistor or loading capacitors are required. The on-chip loading capacitors are pro-
grammable to 16 discrete levels allowing compatibility with a wide range of crystals. The SmaRTClock can
operate directly from a 0.9–3.6 V battery voltage and remains operational even when the device goes into
its lowest power down mode.
The SmaRTClock allows a maximum of 36 hour 32-bit independent time-keeping when used with a
32.768 kHz Watch Crystal. The SmaRTClock provides an Alarm and Missing SmaRTClock events, which
could be used as reset or wakeup sources. See Section “18. Reset Sources” on page 175 and Section
“14. Power Management” on page 151 for details on reset sources and low power mode wake-up sources,
respectively.
XTAL3
XTAL4
SmaRTClock
Power/
Clock
Mgmt
Programmable Load Capacitors
SmaRTClock Oscillator
32-Bit
SmaRTClock
Timer
SmaRTClock State Machine
Wake-Up
Interrupt
Interface
Registers
CAPTUREn
RTC0CN
Internal
Registers
RTC0KEY
RTC0ADR
RTC0DAT
RTC0XCN
RTC0XCF
RTC0PIN
ALARMn
Figure 20.1. SmaRTClock Block Diagram
20.1. SmaRTClock Interface
The SmaRTClock Interface consists of three registers: RTC0KEY, RTC0ADR, and RTC0DAT. These inter-
face registers are located on the CIP-51’s SFR map and provide access to the SmaRTClock internal regis-
ters listed in Table 20.1. The SmaRTClock internal registers can only be accessed indirectly through the
SmaRTClock Interface.
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Table 20.1. SmaRTClock Internal Registers
SmaRTClock SmaRTClock
Register Name
Description
Address
Register
0x00–0x03
CAPTUREn SmaRTClock Capture
Registers
Four Registers used for setting the 32-bit
SmaRTClock timer or reading its current value.
0x04
0x05
0x06
RTC0CN
SmaRTClock Control
Register
Controls the operation of the SmaRTClock State
Machine.
RTC0XCN SmaRTClock Oscillator Controls the operation of the SmaRTClock
Control Register Oscillator.
RTC0XCF SmaRTClock Oscillator Controls the value of the progammable
Configuration Register
oscillator load capacitance and
enables/disables AutoStep.
0x07
RTC0PIN
ALARMn
SmaRTClock Pin
Configuration Register
Note: Forces XTAL3 and XTAL4 to be internally
shorted.
This register also contains other reserved bits
which should not be modified.
0x08–0x0B
SmaRTClock Alarm
Registers
Four registers used for setting or reading the
32-bit SmaRTClock alarm value.
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20.1.1. SmaRTClock Lock and Key Functions
The SmaRTClock Interface is protected with a lock and key function. The SmaRTClock Lock and Key Reg-
ister (RTC0KEY) must be written with the correct key codes, in sequence, before writes and reads to
RTC0ADR and RTC0DAT may be performed. The key codes are: 0xA5, 0xF1. There are no timing restric-
tions, but the key codes must be written in order. If the key codes are written out of order, the wrong codes
are written, or an indirect register read or write is attempted while the interface is locked, the SmaRTClock
interface will be disabled, and the RTC0ADR and RTC0DAT registers will become inaccessible until the
next system reset. Once the SmaRTClock interface is unlocked, software may perform any number of
accesses to the SmaRTClock registers until the interface is re-locked or the device is reset. Any write to
RTC0KEY while the SmaRTClock interface is unlocked will re-lock the interface.
Reading the RTC0KEY register at any time will provide the SmaRTClock Interface status and will not inter-
fere with the sequence that is being written. The RTC0KEY register description in SFR Definition 20.1 lists
the definition of each status code.
20.1.2. Using RTC0ADR and RTC0DAT to Access SmaRTClock Internal Registers
The SmaRTClock internal registers can be read and written using RTC0ADR and RTC0DAT. The
RTC0ADR register selects the SmaRTClock internal register that will be targeted by subsequent reads or
writes. Recommended instruction timing is provided in this section. If the recommended instruction timing
is not followed, then BUSY (RTC0ADR.7) should be checked prior to each read or write operation to make
sure the SmaRTClock Interface is not busy performing the previous read or write operation. A SmaRT-
Clock Write operation is initiated by writing to the RTC0DAT register. Below is an example of writing to a
SmaRTClock internal register.
1. Poll BUSY (RTC0ADR.7) until it returns 0 or follow recommended instruction timing.
2. Write 0x05 to RTC0ADR. This selects the internal RTC0CN register at SmaRTClock Address 0x05.
3. Write 0x00 to RTC0DAT. This operation writes 0x00 to the internal RTC0CN register.
A SmaRTClock Read operation is initiated by setting the SmaRTClock Interface Busy bit. This transfers
the contents of the internal register selected by RTC0ADR to RTC0DAT. The transferred data will remain in
RTC0DAT until the next read or write operation. Below is an example of reading a SmaRTClock internal
register.
1. Poll BUSY (RTC0ADR.7) until it returns 0 or follow recommended instruction timing.
2. Write 0x05 to RTC0ADR. This selects the internal RTC0CN register at SmaRTClock Address 0x05.
3. Write 1 to BUSY. This initiates the transfer of data from RTC0CN to RTC0DAT.
4. Poll BUSY (RTC0ADR.7) until it returns 0 or follow recommend instruction timing.
5. Read data from RTC0DAT. This data is a copy of the RTC0CN register.
Note: The RTC0ADR and RTC0DAT registers will retain their state upon a device reset.
20.1.3. RTC0ADR Short Strobe Feature
Reads and writes to indirect SmaRTClock registers normally take 7 system clock cycles. To minimize the
indirect register access time, the Short Strobe feature decreases the read and write access time to 6 sys-
tem clocks. The Short Strobe feature is automatically enabled on reset and can be manually enabled/dis-
abled using the SHORT (RTC0ADR.4) control bit.
Recommended Instruction Timing for a single register read with short strobe enabled:
mov RTC0ADR, #095h
nop
nop
nop
mov A, RTC0DAT
192
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Recommended Instruction Timing for a single register write with short strobe enabled:
mov RTC0ADR, #095h
mov RTC0DAT, #000h
nop
20.1.4. SmaRTClock Interface Autoread Feature
When Autoread is enabled, each read from RTC0DAT initiates the next indirect read operation on the
SmaRTClock internal register selected by RTC0ADR. Software should set the BUSY bit once at the begin-
ning of each series of consecutive reads. Software should follow recommended instruction timing or check
if the SmaRTClock Interface is busy prior to reading RTC0DAT. Autoread is enabled by setting AUTORD
(RTC0ADR.6) to logic 1.
20.1.5. RTC0ADR Autoincrement Feature
For ease of reading and writing the 32-bit CAPTURE and ALARM values, RTC0ADR automatically incre-
ments after each read or write to a CAPTUREn or ALARMn register. This speeds up the process of setting
an alarm or reading the current SmaRTClock timer value. Autoincrement is always enabled.
Recommended Instruction Timing for a multi-byte register read with short strobe and autoread enabled:
mov RTC0ADR, #0d0h
nop
nop
nop
mov A, RTC0DAT
nop
nop
mov A, RTC0DAT
nop
nop
mov A, RTC0DAT
nop
nop
mov A, RTC0DAT
Recommended Instruction Timing for a multi-byte register write with short strobe enabled:
mov RTC0ADR, #010h
mov RTC0DAT, #05h
nop
mov RTC0DAT, #06h
nop
mov RTC0DAT, #07h
nop
mov RTC0DAT, #08h
nop
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SFR Definition 20.1. RTC0KEY: SmaRTClock Lock and Key
Bit
7
6
5
4
3
2
1
0
RTC0ST[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xAE
Bit
Name
Function
7:0
RTC0ST SmaRTClock Interface Lock/Key and Status.
Locks/unlocks the SmaRTClock interface when written. Provides lock status when
read.
Read:
0x00: SmaRTClock Interface is locked.
0x01: SmaRTClock Interface is locked.
First key code (0xA5) has been written, waiting for second key code.
0x02: SmaRTClock Interface is unlocked.
First and second key codes (0xA5, 0xF1) have been written.
0x03: SmaRTClock Interface is disabled until the next system reset.
Write:
When RTC0ST = 0x00 (locked), writing 0xA5 followed by 0xF1 unlocks the
SmaRTClock Interface.
When RTC0ST = 0x01 (waiting for second key code), writing any value other
than the second key code (0xF1) will change RTC0STATE to 0x03 and disable
the SmaRTClock Interface until the next system reset.
When RTC0ST = 0x02 (unlocked), any write to RTC0KEY will lock the SmaRT-
Clock Interface.
When RTC0ST = 0x03 (disabled), writes to RTC0KEY have no effect.
194
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SFR Definition 20.2. RTC0ADR: SmaRTClock Address
Bit
7
6
5
4
3
2
1
0
BUSY
AUTORD
SHORT
ADDR[3:0]
R/W
Name
Type
Reset
R/W
0
R/W
0
R
0
R/W
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xAC
Bit
Name
Function
7
BUSY
SmaRTClock Interface Busy Indicator.
Indicates SmaRTClock interface status. Writing 1 to this bit initiates an indirect read.
6
AUTORD SmaRTClock Interface Autoread Enable.
Enables/disables Autoread.
0: Autoread Disabled.
1: Autoread Enabled.
5
4
Unused
SHORT Short Strobe Enable.
Enables/disables the Short Strobe Feature.
Read = 0b; Write = Don’t Care.
0: Short Strobe disabled.
1: Short Strobe enabled.
3:0 ADDR[3:0] SmaRTClock Indirect Register Address.
Sets the currently selected SmaRTClock register.
See Table 20.1 for a listing of all SmaRTClock indirect registers.
Note: The ADDR bits increment after each indirect read/write operation that targets a CAPTUREn or ALARMn
internal SmaRTClock register.
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SFR Definition 20.3. RTC0DAT: SmaRTClock Data
Bit
7
6
5
4
3
2
1
0
RTC0DAT[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Page= 0x0; SFR Address = 0xAD
Bit
Name
Function
7:0
RTC0DAT SmaRTClock Data Bits.
Holds data transferred to/from the internal SmaRTClock register selected by
RTC0ADR.
Note: Read-modify-write instructions (orl, anl, etc.) should not be used on this register.
196
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20.2. SmaRTClock Clocking Sources
The SmaRTClock peripheral is clocked from its own timebase, independent of the system clock. The
SmaRTClock timebase is derived from the SmaRTClock oscillator circuit, which has two modes of opera-
tion: Crystal Mode, and Self-Oscillate Mode. The oscillation frequency is 32.768 kHz in Crystal Mode and
can be programmed in the range of 10 kHz to 40 kHz in Self-Oscillate Mode. The frequency of the SmaRT-
Clock oscillator can be measured with respect to another oscillator using an on-chip timer. See Section
“27. Timers” on page 330 for more information on how this can be accomplished.
Note: The SmaRTClock timebase can be selected as the system clock and routed to a port pin. See Section
“19. Clocking Sources” on page 182 for information on selecting the system clock source and Section “21. Port
Input/Output” on page 207 for information on how to route the system clock to a port pin.
20.2.1. Using the SmaRTClock Oscillator with a Crystal or External CMOS Clock
When using Crystal Mode, a 32.768 kHz crystal should be connected between XTAL3 and XTAL4. No
other external components are required. The following steps show how to start the SmaRTClock crystal
oscillator in software:
1. Set SmaRTClock to Crystal Mode (XMODE = 1).
2. Disable Automatic Gain Control (AGCEN) and enable Bias Doubling (BIASX2) for fast crystal startup.
3. Set the desired loading capacitance (RTC0XCF).
4. Enable power to the SmaRTClock oscillator circuit (RTC0EN = 1).
5. Wait 20 ms.
6. Poll the SmaRTClock Clock Valid Bit (CLKVLD) until the crystal oscillator stabilizes.
7. Poll the SmaRTClock Load Capacitance Ready Bit (LOADRDY) until the load capacitance reaches its
programmed value.
8. Enable Automatic Gain Control (AGCEN) and disable Bias Doubling (BIASX2) for maximum power
savings.
9. Enable the SmaRTClock missing clock detector.
10.Wait 2 ms.
11.Clear the PMU0CF wake-up source flags.
In Crystal Mode, the SmaRTClock oscillator may be driven by an external CMOS clock. The CMOS clock
should be applied to XTAL3. XTAL4 should be left floating. The input low voltage (VIL) and input high volt-
age (VIH) for XTAL3 when used with an external CMOS clock are 0.1 and 0.8 V, respectively. The SmaRT-
Clock oscillator should be configured to its lowest bias setting with AGC disabled. The CLKVLD bit is
indeterminate when using a CMOS clock, however, the OSCFAIL bit may be checked 2 ms after SmaRT-
Clock oscillator is powered on to ensure that there is a valid clock on XTAL3.
20.2.2. Using the SmaRTClock Oscillator in Self-Oscillate Mode
When using Self-Oscillate Mode, the XTAL3 and XTAL4 pins should be shorted together. The RTC0PIN
register can be used to internally short XTAL3 and XTAL4. The following steps show how to configure
SmaRTClock for use in Self-Oscillate Mode:
1. Set SmaRTClock to Self-Oscillate Mode (XMODE = 0).
2. Set the desired oscillation frequency:
For oscillation at about 20 kHz, set BIASX2 = 0.
For oscillation at about 40 kHz, set BIASX2 = 1.
3. The oscillator starts oscillating instantaneously.
4. Fine tune the oscillation frequency by adjusting the load capacitance (RTC0XCF).
Rev. 1.0
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20.2.3. Programmable Load Capacitance
The programmable load capacitance has 16 values to support crystal oscillators with a wide range of rec-
ommended load capacitance. If Automatic Load Capacitance Stepping is enabled, the crystal load capaci-
tors start at the smallest setting to allow a fast startup time, then slowly increase the capacitance until the
final programmed value is reached. The final programmed loading capacitor value is specified using the
LOADCAP bits in the RTC0XCF register. The LOADCAP setting specifies the amount of on-chip load
capacitance and does not include any stray PCB capacitance. Once the final programmed loading capaci-
tor value is reached, the LOADRDY flag will be set by hardware to logic 1.
When using the SmaRTClock oscillator in Self-Oscillate mode, the programmable load capacitance can be
used to fine tune the oscillation frequency. In most cases, increasing the load capacitor value will result in
a decrease in oscillation frequency.Table 20.2 shows the crystal load capacitance for various settings of
LOADCAP.
.
Table 20.2. SmaRTClock Load Capacitance Settings
LOADCAP
Crystal Load Capacitance
Equivalent Capacitance seen on
XTAL3 and XTAL4
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
4.0 pF
4.5 pF
5.0 pF
5.5 pF
6.0 pF
6.5 pF
7.0 pF
7.5 pF
8.0 pF
8.5 pF
9.0 pF
9.5 pF
10.5 pF
11.5 pF
12.5 pF
13.5 pF
8.0 pF
9.0 pF
10.0 pF
11.0 pF
12.0 pF
13.0 pF
14.0 pF
15.0 pF
16.0 pF
17.0 pF
18.0 pF
19.0 pF
21.0 pF
23.0 pF
25.0 pF
27.0 pF
198
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20.2.4. Automatic Gain Control (Crystal Mode Only) and SmaRTClock Bias Doubling
Automatic Gain Control allows the SmaRTClock oscillator to trim the oscillation amplitude of a crystal in
order to achieve the lowest possible power consumption. Automatic Gain Control automatically detects
when the oscillation amplitude has reached a point where it safe to reduce the drive current, therefore, it
may be enabled during crystal startup. It is recommended to enable Automatic Gain Control in most sys-
tems which use the SmaRTClock oscillator in Crystal Mode. The following are recommended crystal spec-
ifications and operating conditions when Automatic Gain Control is enabled:
ESR < 50 k
Load Capacitance < 10 pF
Supply Voltage < 3.0 V
Temperature > –20 °C
When using Automatic Gain Control, it is recommended to perform an oscillation robustness test to ensure
that the chosen crystal will oscillate under the worst case condition to which the system will be exposed.
The worst case condition that should result in the least robust oscillation is at the following system condi-
tions: lowest temperature, highest supply voltage, highest ESR, highest load capacitance, and lowest bias
current (AGC enabled, Bias Double Disabled).
To perform the oscillation robustness test, the SmaRTClock oscillator should be enabled and selected as
the system clock source. Next, the SYSCLK signal should be routed to a port pin configured as a push-pull
digital output. The positive duty cycle of the output clock can be used as an indicator of oscillation robust-
ness. As shown in Figure 20.2, duty cycles less than 55% indicate a robust oscillation. As the duty cycle
approaches 60%, oscillation becomes less reliable and the risk of clock failure increases. Increasing the
bias current (by disabling AGC) will always improve oscillation robustness and will reduce the output
clock’s duty cycle. This test should be performed at the worst case system conditions, as results at very
low temperatures or high supply voltage will vary from results taken at room temperature or low supply
voltage.
Low Risk of Clock
Failure
High Risk of Clock
Failure
Safe Operating Zone
Duty Cycle
25%
55%
60%
Figure 20.2. Interpreting Oscillation Robustness (Duty Cycle) Test Results
As an alternative to performing the oscillation robustness test, Automatic Gain Control may be disabled at
the cost of increased power consumption (approximately 200 nA). Disabling Automatic Gain Control will
provide the crystal oscillator with higher immunity against external factors which may lead to clock failure.
Automatic Gain Control must be disabled if using the SmaRTClock oscillator in self-oscillate mode.
Table 20.3 shows a summary of the oscillator bias settings. The SmaRTClock Bias Doubling feature allows
the self-oscillation frequency to be increased (almost doubled) and allows a higher crystal drive strength in
crystal mode. High crystal drive strength is recommended when the crystal is exposed to poor environmen-
tal conditions such as excessive moisture. SmaRTClock Bias Doubling is enabled by setting BIASX2
(RTC0XCN.5) to 1.
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.
Table 20.3. SmaRTClock Bias Settings
Mode
Setting
Power
Consumption
Crystal
Bias Double Off, AGC On
Bias Double Off, AGC Off
Lowest
600 nA
Low
800 nA
Bias Double On, AGC On
Bias Double On, AGC Off
Bias Double Off
High
Highest
Low
Self-Oscillate
Bias Double On
High
20.2.5. Missing SmaRTClock Detector
The missing SmaRTClock detector is a one-shot circuit enabled by setting MCLKEN (RTC0CN.6) to 1.
When the SmaRTClock Missing Clock Detector is enabled, OSCFAIL (RTC0CN.5) is set by hardware if
SmaRTClock oscillator remains high or low for more than 100 µs.
A SmaRTClock Missing Clock detector timeout can trigger an interrupt, wake the device from a low power
mode, or reset the device. See Section “12. Interrupt Handler” on page 129, Section “14. Power Manage-
ment” on page 151, and Section “18. Reset Sources” on page 175 for more information.
Note: The SmaRTClock Missing Clock Detector should be disabled when making changes to the oscillator settings in
RTC0XCN.
20.2.6. SmaRTClock Oscillator Crystal Valid Detector
The SmaRTClock oscillator crystal valid detector is an oscillation amplitude detector circuit used during
crystal startup to determine when oscillation has started and is nearly stable. The output of this detector
can be read from the CLKVLD bit (RTX0XCN.4).
Notes:
The CLKVLD bit has a blanking interval of 2 ms. During the first 2 ms after turning on the crystal
oscillator, the output of CLKVLD is not valid.
This SmaRTClock crystal valid detector (CLKVLD) is not intended for detecting an oscillator failure. The
missing SmaRTClock detector (CLKFAIL) should be used for this purpose.
200
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20.3. SmaRTClock Timer and Alarm Function
The SmaRTClock timer is a 32-bit counter that, when running (RTC0TR = 1), is incremented every
SmaRTClock oscillator cycle. The timer has an alarm function that can be set to generate an interrupt,
wake the device from a low power mode, or reset the device at a specific time. See Section “12. Interrupt
Handler” on page 129, Section “14. Power Management” on page 151, and Section “18. Reset Sources”
on page 175 for more information.
The SmaRTClock timer includes an Auto Reset feature, which automatically resets the timer to zero one
SmaRTClock cycle after the alarm signal is deasserted. When using Auto Reset, the Alarm match value
should always be set to 2 counts less than the desired match value. Auto Reset can be enabled by writing
a 1 to ALRM (RTC0CN.2).
20.3.1. Setting and Reading the SmaRTClock Timer Value
The 32-bit SmaRTClock timer can be set or read using the six CAPTUREn internal registers. Note that the
timer does not need to be stopped before reading or setting its value. The following steps can be used to
set the timer value:
1. Write the desired 32-bit set value to the CAPTUREn registers.
2. Write 1 to RTC0SET. This will transfer the contents of the CAPTUREn registers to the SmaRTClock
timer.
3. Operation is complete when RTC0SET is cleared to 0 by hardware.
The following steps can be used to read the current timer value:
1. Write 1 to RTC0CAP. This will transfer the contents of the timer to the CAPTUREn registers.
2. Poll RTC0CAP until it is cleared to 0 by hardware.
3. A snapshot of the timer value can be read from the CAPTUREn registers
20.3.2. Setting a SmaRTClock Alarm
The SmaRTClock alarm function compares the 32-bit value of SmaRTClock Timer to the value of the
ALARMn registers. An alarm event is triggered if the SmaRTClock timer is equal to the ALARMn registers.
If Auto Reset is enabled, the 32-bit timer will be cleared to zero one SmaRTClock cycle after the alarm
event.
The SmaRTClock alarm event can be configured to reset the MCU, wake it up from a low power mode, or
generate an interrupt. See Section “12. Interrupt Handler” on page 129, Section “14. Power Management”
on page 151, and Section “18. Reset Sources” on page 175 for more information.
The following steps can be used to set up a SmaRTClock Alarm:
1. Disable SmaRTClock Alarm Events (RTC0AEN = 0).
2. Set the ALARMn registers to the desired value.
3. Enable SmaRTClock Alarm Events (RTC0AEN = 1).
Notes:
The ALRM bit, which is used as the SmaRTClock Alarm Event flag, is cleared by disabling
SmaRTClock Alarm Events (RTC0AEN = 0).
If AutoReset is disabled, disabling (RTC0AEN = 0) then Re-enabling Alarm Events (RTC0AEN = 1)
after a SmaRTClock Alarm without modifying ALARMn registers will automatically schedule the next
alarm after 2^32 SmaRTClock cycles (approximately 36 hours using a 32.768 kHz crystal).
The SmaRTClock Alarm Event flag will remain asserted for a maximum of one SmaRTClock cycle. See
Section “14. Power Management” on page 151 for information on how to capture a SmaRTClock Alarm
event using a flag which is not automatically cleared by hardware.
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20.3.3. Software Considerations for using the SmaRTClock Timer and Alarm
The SmaRTClock timer and alarm have two operating modes to suit varying applications. The two modes
are described below:
Mode 1:
The first mode uses the SmaRTClock timer as a perpetual timebase which is never reset to zero. Every 36
hours, the timer is allowed to overflow without being stopped or disrupted. The alarm interval is software
managed and is added to the ALRMn registers by software after each alarm. This allows the alarm match
value to always stay ahead of the timer by one software managed interval. If software uses 32-bit unsigned
addition to increment the alarm match value, then it does not need to handle overflows since both the timer
and the alarm match value will overflow in the same manner.
This mode is ideal for applications which have a long alarm interval (e.g. 24 or 36 hours) and/or have a
need for a perpetual timebase. An example of an application that needs a perpetual timebase is one
whose wake-up interval is constantly changing. For these applications, software can keep track of the
number of timer overflows in a 16-bit variable, extending the 32-bit (36 hour) timer to a 48-bit (272 year)
perpetual timebase.
Mode 2:
The second mode uses the SmaRTClock timer as a general purpose up counter which is auto reset to zero
by hardware after each alarm. The alarm interval is managed by hardware and stored in the ALRMn regis-
ters. Software only needs to set the alarm interval once during device initialization. After each alarm, soft-
ware should keep a count of the number of alarms that have occurred in order to keep track of time.
This mode is ideal for applications that require minimal software intervention and/or have a fixed alarm
interval. This mode is the most power efficient since it requires less CPU time per alarm.
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Internal Register Definition 20.4. RTC0CN: SmaRTClock Control
Bit
7
6
5
4
3
2
1
0
RTC0EN MCLKEN OSCFAIL RTC0TR RTC0AEN
ALRM
RTC0SET RTC0CAP
Name
Type
Reset
R/W
0
R/W
0
R/W
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Varies
SmaRTClock Address = 0x04
Bit
Name
Function
7
RTC0EN SmaRTClock Enable.
Enables/disables the SmaRTClock oscillator and associated bias currents.
0: SmaRTClock oscillator disabled.
1: SmaRTClock oscillator enabled.
6
MCLKEN Missing SmaRTClock Detector Enable.
Enables/disables the missing SmaRTClock detector.
0: Missing SmaRTClock detector disabled.
1: Missing SmaRTClock detector enabled.
5
4
OSCFAIL SmaRTClock Oscillator Fail Event Flag.
Set by hardware when a missing SmaRTClock detector timeout occurs. Must be
cleared by software. The value of this bit is not defined when the SmaRTClock
oscillator is disabled.
RTC0TR SmaRTClock Timer Run Control.
Controls if the SmaRTClock timer is running or stopped (holds current value).
0: SmaRTClock timer is stopped.
1: SmaRTClock timer is running.
3
2
RTC0AEN SmaRTClock Alarm Enable.
Enables/disables the SmaRTClock alarm function. Also clears the ALRM flag.
0: SmaRTClock alarm disabled.
1: SmaRTClock alarm enabled.
ALRM
SmaRTClock Alarm Event Read:
Write:
Flag and Auto Reset
Enable
0: SmaRTClock alarm
event flag is de-asserted.
1: SmaRTClock alarm
event flag is asserted.
0: Disable Auto Reset.
1: Enable Auto Reset.
Reads return the state of the
alarm event flag.
Writes enable/disable the
Auto Reset function.
1
0
RTC0SET SmaRTClock Timer Set.
Writing 1 initiates a SmaRTClock timer set operation. This bit is cleared to 0 by hard-
ware to indicate that the timer set operation is complete.
RTC0CAP SmaRTClock Timer Capture.
Writing 1 initiates a SmaRTClock timer capture operation. This bit is cleared to 0 by
hardware to indicate that the timer capture operation is complete.
Note: The ALRM flag will remain asserted for a maximum of one SmaRTClock cycle. See Section “Power
Management” on page 151 for information on how to capture a SmaRTClock Alarm event using a flag which is
not automatically cleared by hardware.
Rev. 1.0
203
Si1000/1/2/3/4/5
Internal Register Definition 20.5. RTC0XCN: SmaRTClock Oscillator Control
Bit
7
6
5
4
3
2
1
0
AGCEN
XMODE
BIASX2
CLKVLD
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R
0
R
0
R
0
R
0
R
0
SmaRTClock Address = 0x05
Bit
Name
Function
7
AGCEN SmaRTClock Oscillator Automatic Gain Control (AGC) Enable.
0: AGC disabled.
1: AGC enabled.
6
5
XMODE SmaRTClock Oscillator Mode.
Selects Crystal or Self Oscillate Mode.
0: Self-Oscillate Mode selected.
1: Crystal Mode selected.
BIASX2 SmaRTClock Oscillator Bias Double Enable.
Enables/disables the Bias Double feature.
0: Bias Double disabled.
1: Bias Double enabled.
4
CLKVLD SmaRTClock Oscillator Crystal Valid Indicator.
Indicates if oscillation amplitude is sufficient for maintaining oscillation.
0: Oscillation has not started or oscillation amplitude is too low to maintain oscillation.
1: Sufficient oscillation amplitude detected.
3:0
Unused Read = 0000b; Write = Don’t Care.
204
Rev. 1.0
Si1000/1/2/3/4/5
Internal Register Definition 20.6. RTC0XCF: SmaRTClock Oscillator Configuration
Bit
7
6
5
4
3
2
1
0
AUTOSTP LOADRDY
LOADCAP
R/W
Name
Type
Reset
R/W
0
R
0
R
0
R
0
Varies
Varies
Varies
Varies
SmaRTClock Address = 0x06
Bit
Name
Function
7
AUTOSTP Automatic Load Capacitance Stepping Enable.
Enables/disables automatic load capacitance stepping.
0: Load capacitance stepping disabled.
1: Load capacitance stepping enabled.
6
LOADRDY Load Capacitance Ready Indicator.
Set by hardware when the load capacitance matches the programmed value.
0: Load capacitance is currently stepping.
1: Load capacitance has reached it programmed value.
5:4
3:0
Unused
Read = 00b; Write = Don’t Care.
LOADCAP Load Capacitance Programmed Value.
Holds the user’s desired value of the load capacitance. See Table 20.2 on
page 198.
Internal Register Definition 20.7. RTC0PIN: SmaRTClock Pin Configuration
Bit
7
6
5
4
3
2
1
0
RTC0PIN
W
Name
Type
Reset
0
1
1
0
0
1
1
1
SmaRTClock Address = 0x07
Bit Name
7:0 RTC0PIN SmaRTClock Pin Configuration.
Function
Writing 0xE7 to this register forces XTAL3 and XTAL4 to be internally shorted for use
with Self Oscillate Mode.
Writing 0x67 returns XTAL3 and XTAL4 to their normal configuration.
Rev. 1.0
205
Si1000/1/2/3/4/5
Internal Register Definition 20.8. CAPTUREn: SmaRTClock Timer Capture
Bit
7
6
5
4
3
2
1
0
CAPTURE[31:0]
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SmaRTClock Addresses: CAPTURE0 = 0x00; CAPTURE1 = 0x01; CAPTURE2 =0x02; CAPTURE3: 0x03.
Bit Name Function
7:0 CAPTURE[31:0] SmaRTClock Timer Capture.
These 4 registers (CAPTURE3–CAPTURE0) are used to read or set the 32-bit
SmaRTClock timer. Data is transferred to or from the SmaRTClock timer when
the RTC0SET or RTC0CAP bits are set.
Note: The least significant bit of the timer capture value is in CAPTURE0.0.
Internal Register Definition 20.9. ALARMn: SmaRTClock Alarm Programmed Value
Bit
7
6
5
4
3
2
1
0
ALARM[31:0]
R/W R/W
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
0
SmaRTClock Addresses: ALARM0 = 0x08; ALARM1 = 0x09; ALARM2 = 0x0A; ALARM3 = 0x0B
Bit Name Function
7:0 ALARM[31:0] SmaRTClock Alarm Programmed Value.
These 4 registers (ALARM3–ALARM0) are used to set an alarm event for the
SmaRTClock timer. The SmaRTClock alarm should be disabled (RTC0AEN=0)
when updating these registers.
Note: The least significant bit of the alarm programmed value is in ALARM0.0.
206
Rev. 1.0
Si1000/1/2/3/4/5
21. Port Input/Output
Digital and analog resources are available through 19 or 16 I/O pins. The EZRadioPRO peripheral pro-
vides an additional 3 GPIO pins which are independent of the pins described in this chapter. Port pins are
organized as three byte-wide ports. Port pins P0.0–P2.6 can be defined as digital or analog I/O. Digital I/O
pins can be assigned to one of the internal digital resources or used as general purpose I/O (GPIO). Ana-
log I/O pins are used by the internal analog resources. P1.0, P1.1, P1.2, and P1.4 are dedicated for com-
munication with the EZRadioPRO peripheral. P1.3 is not available. P2.4, P2.5, and P2.6 are only available
on the Si1000/1/2/3. P2.7 can be used as GPIO and is shared with the C2 Interface Data signal (C2D).
See Section “29. C2 Interface” on page 371 for more details.
The designer has complete control over which digital and analog functions are assigned to individual Port
pins, limited only by the number of physical I/O pins. This resource assignment flexibility is achieved
through the use of a Priority Crossbar Decoder. See Section 21.3 for more information on the Crossbar.
All Px.x Port I/Os are 5V tolerant when used as digital inputs or open-drain outputs. For Port I/Os config-
ured as push-pull outputs, current is sourced from the VDD_MCU supply. Port I/Os used for analog func-
tions can operate up to the VDD_MCU supply voltage. See Section 21.1 for more information on Port I/O
operating modes and the electrical specifications chapter for detailed electrical specifications.
XBR0, XBR1,
XBR2, PnSKIP
Registers
Port Match
P0MASK, P0MAT
P1MASK, P1MAT
External Interrupts
EX0 and EX1
Priority
Decoder
PnMDOUT,
PnMDIN Registers
2
UART
Highest
Priority
4
2
SPI0
SPI1
P0.0
P0.7
SMBus
P0
I/O
Cells
Digital
Crossbar
8
8
CP0
CP1
Outputs
4
P1.5
P1.6
P1.7
SYSCLK
PCA
P1
I/O
Cells
7
2
Lowest
Priority
T0, T1
8
P2.0
8
P0
P1
P2
(P0.0-P0.7)
P2
I/O
Cell
P2.6
P2.7
8
(P1.0-P1.7)
To Analog Peripherals
(ADC0, CP0, and CP1 inputs,
VREF, IREF0, AGND)
No analog functionality
available on P2.7
8
(P2.0-P2.7)
Note: P1.0, P1.1, P1.2, and P1.4 are internally connected to the
EZRadioPRO peripheral. P1.3 is not internally or externally connected.
P2.4, P2.5, and P2.6 are only available on Si1000/1/2/3
Figure 21.1. Port I/O Functional Block Diagram
Rev. 1.0
207
Si1000/1/2/3/4/5
21.1. Port I/O Modes of Operation
Port pins P0.0–P2.6 use the Port I/O cell shown in Figure 21.2. Each Port I/O cell can be configured by
software for analog I/O or digital I/O using the PnMDIN registers. On reset, all Port I/O cells default to a dig-
ital high impedance state with weak pull-ups enabled.
21.1.1. Port Pins Configured for Analog I/O
Any pins to be used as Comparator or ADC input, external oscillator input/output, or AGND, VREF, or Cur-
rent Reference output should be configured for analog I/O (PnMDIN.n = 0). When a pin is configured for
analog I/O, its weak pullup and digital receiver are disabled. In most cases, software should also disable
the digital output drivers. Port pins configured for analog I/O will always read back a value of 0 regardless
of the actual voltage on the pin.
Configuring pins as analog I/O saves power and isolates the Port pin from digital interference. Port pins
configured as digital inputs may still be used by analog peripherals; however, this practice is not recom-
mended and may result in measurement errors.
21.1.2. Port Pins Configured For Digital I/O
Any pins to be used by digital peripherals (UART, SPI, SMBus, etc.), external digital event capture func-
tions, or as GPIO should be configured as digital I/O (PnMDIN.n = 1). For digital I/O pins, one of two output
modes (push-pull or open-drain) must be selected using the PnMDOUT registers.
Push-pull outputs (PnMDOUT.n = 1) drive the Port pad to the VDD_MCU or GND supply rails based on the
output logic value of the Port pin. Open-drain outputs have the high side driver disabled; therefore, they
only drive the Port pad to GND when the output logic value is 0 and become high impedance inputs (both
high and low drivers turned off) when the output logic value is 1.
When a digital I/O cell is placed in the high impedance state, a weak pull-up transistor pulls the Port pad to
the VDD_MCU supply voltage to ensure the digital input is at a defined logic state. Weak pull-ups are dis-
abled when the I/O cell is driven to GND to minimize power consumption and may be globally disabled by
setting WEAKPUD to 1. The user must ensure that digital I/O are always internally or externally pulled or
driven to a valid logic state. Port pins configured for digital I/O always read back the logic state of the Port
pad, regardless of the output logic value of the Port pin.
WEAKPUD
(Weak Pull-Up Disable)
PnMDOUT.x
(1 for push-pull)
(0 for open-drain)
VDD/DC+
VDD/DC+
XBARE
(Crossbar
Enable)
(WEAK)
PORT
PAD
Pn.x – Output
Logic Value
(Port Latch or
Crossbar)
PnMDIN.x
(1 for digital)
(0 for analog)
GND
To/From Analog
Peripheral
Pn.x – Input Logic Value
(Reads 0 when pin is configured as an analog I/O)
Figure 21.2. Port I/O Cell Block Diagram
208
Rev. 1.0
Si1000/1/2/3/4/5
21.1.3. Interfacing Port I/O to 5 V and 3.3 V Logic
All Port I/O configured for digital, open-drain operation are capable of interfacing to digital logic operating at
a supply voltage higher than 4.5 V and less than 5.25 V. When the supply voltage is in the range of 1.8 to
2.2 V, the I/O may also interface to digital logic operating between 3.0 to 3.6 V if the input signal frequency
is less than 12.5 MHz or less than 25 MHz if the signal rise time (10% to 90%) is less than 1.2 ns. When
operating at a supply voltage above 2.2 V, the device should not interface to 3.3 V logic; however, interfac-
ing to 5 V logic is permitted. An external pull-up resistor to the higher supply voltage is typically required for
most systems.
Important Notes:
When interfacing to a signal that is between 4.5 and 5.25 V, the maximum clock frequency that may be
input on a GPIO pin is 12.5 MHz. The exception to this rule is when routing an external CMOS clock to
P0.3, in which case, a signal up to 25 MHz is valid as long as the rise time (10% to 90%) is shorter than
1.8 ns.
When the supply voltage is less than 2.2 V and interfacing to a signal that is between 3.0 and 3.6 V, the
maximum clock frequency that may be input on a GPIO pin is 3.125 MHz. The exception to this rule is
when routing an external CMOS clock to P0.3, in which case, a signal up to 25 MHz is valued as long
as the rise time (10% to 90%) is shorter than 1.2 ns.
In a multi-voltage interface, the external pull-up resistor should be sized to allow a current of at least
150 µA to flow into the Port pin when the supply voltage is between (VDD_MCU/DC+ plus 0.4 V) and
(VDD_MCU/DC+ plus 1.0 V). Once the Port pad voltage increases beyond this range, the current
flowing into the Port pin is minimal.
These guidelines only apply to multi-voltage interfaces. Port I/Os may always interface to digital logic oper-
ating at the same supply voltage.
21.1.4. Increasing Port I/O Drive Strength
Port I/O output drivers support a high and low drive strength; the default is low drive strength. The drive
strength of a Port I/O can be configured using the PnDRV registers. See Section “4. Electrical Characteris-
tics” on page 40 for the difference in output drive strength between the two modes.
21.2. Assigning Port I/O Pins to Analog and Digital Functions
Port I/O pins P0.0–P2.6 can be assigned to various analog, digital, and external interrupt functions. The
Port pins assuaged to analog functions should be configured for analog I/O and Port pins assuaged to dig-
ital or external interrupt functions should be configured for digital I/O.
21.2.1. Assigning Port I/O Pins to Analog Functions
Table 21.1 shows all available analog functions that need Port I/O assignments. Port pins selected for
these analog functions should have their digital drivers disabled (PnMDOUT.n = 0 and Port Latch =
1) and their corresponding bit in PnSKIP set to 1. This reserves the pin for use by the analog function
and does not allow it to be claimed by the Crossbar. Table 21.1 shows the potential mapping of Port I/O to
each analog function.
Rev. 1.0
209
Si1000/1/2/3/4/5
Table 21.1. Port I/O Assignment for Analog Functions
Analog Function
Potentially
Assignable Port Pins
SFR(s) used for
Assignment
ADC Input
P0.0–P2.6
P0.0–P2.6
P0.0–P2.6
P0.0
ADC0MX, PnSKIP
CPT0MX, PnSKIP
CPT1MX, PnSKIP
REF0CN, PnSKIP
REF0CN, PnSKIP
IREF0CN, PnSKIP
OSCXCN, PnSKIP
OSCXCN, PnSKIP
Comparator0 Input
Comparator1 Input
Voltage Reference (VREF0)
Analog Ground Reference (AGND)
Current Reference (IREF0)
External Oscillator Input (XTAL1)
External Oscillator Output (XTAL2)
P0.1
P0.7
P0.2
P0.3
21.2.2. Assigning Port I/O Pins to Digital Functions
Any Port pins not assigned to analog functions may be assigned to digital functions or used as GPIO. Most
digital functions rely on the Crossbar for pin assignment; however, some digital functions bypass the
Crossbar in a manner similar to the analog functions listed above. Port pins used by these digital func-
tions and any Port pins selected for use as GPIO should have their corresponding bit in PnSKIP set
to 1. Table 21.2 shows all available digital functions and the potential mapping of Port I/O to each digital
function.
Table 21.2. Port I/O Assignment for Digital Functions
Digital Function
Potentially Assignable Port Pins
SFR(s) used for
Assignment
UART0, SPI1, SPI0, SMBus,
CP0 and CP1 Outputs, Sys-
tem Clock Output, PCA0,
Timer0 and Timer1 External
Inputs.
Any Port pin available for assignment by the
Crossbar. This includes P0.0–P2.6 pins which
have their PnSKIP bit set to 0.
Note: The Crossbar will always assign UART0
and SPI1 pins to fixed locations.
XBR0, XBR1, XBR2
Any pin used for GPIO
P0.0–P2.6
P0SKIP, P1SKIP,
P2SKIP
21.2.3. Assigning Port I/O Pins to External Digital Event Capture Functions
External digital event capture functions can be used to trigger an interrupt or wake the device from a low
power mode when a transition occurs on a digital I/O pin. The digital event capture functions do not require
dedicated pins and will function on both GPIO pins (PnSKIP = 1) and pins in use by the Crossbar (PnSKIP
= 0). External digital even capture functions cannot be used on pins configured for analog I/O. Table 21.3
shows all available external digital event capture functions.
210
Rev. 1.0
Si1000/1/2/3/4/5
Table 21.3. Port I/O Assignment for External Digital Event Capture Functions
Digital Function
Potentially Assignable Port Pins
SFR(s) used for
Assignment
External Interrupt 0
External Interrupt 1
Port Match
P0.0–P0.7
P0.0–P0.7
P0.0–P1.7
IT01CF
IT01CF
P0MASK, P0MAT
P1MASK, P1MAT
21.3. Priority Crossbar Decoder
The Priority Crossbar Decoder assigns a Port I/O pin to each software selected digital function using the
fixed peripheral priority order shown in Figure 21.3. The registers XBR0, XBR1, and XBR2 defined in SFR
Definition 21.1, SFR Definition 21.2, and SFR Definition 21.3 are used to select digital functions in the
Crossbar. The Port pins available for assignment by the Crossbar include all Port pins (P0.0–P2.6) which
have their corresponding bit in PnSKIP set to 0.
From Figure 21.3, the highest priority peripheral is UART0. If UART0 is selected in the Crossbar (using the
XBRn registers), then P0.4 and P0.5 will be assigned to UART0. The next highest priority peripheral is
SPI1. If SPI1 is selected in the Crossbar, then P1.0–P1.2 will be assigned to SPI1. P1.3 will be assigned if
SPI1 is configured for 4-wire mode. The user should ensure that the pins to be assigned by the Crossbar
have their PnSKIP bits set to 0.
For all remaining digital functions selected in the Crossbar, starting at the top of Figure 21.3 going down,
the least-significant unskipped, unassigned Port pin(s) are assigned to that function. If a Port pin is already
assigned (e.g., UART0 or SPI1 pins), or if its PnSKIP bit is set to 1, then the Crossbar will skip over the pin
and find next available unskipped, unassigned Port pin. All Port pins used for analog functions, GPIO, or
dedicated digital functions such as the EMIF should have their PnSKIP bit set to 1.
Figure 21.3 shows the Crossbar Decoder priority with no Port pins skipped (P0SKIP, P1SKIP, P2SKIP =
0x00); Figure 21.4 shows the Crossbar Decoder priority with the External Oscillator pins (XTAL1 and
XTAL2) skipped (P0SKIP = 0x0C).
Notes:
The Crossbar must be enabled (XBARE = 1) before any Port pin is used as a digital output. Port output
drivers are disabled while the Crossbar is disabled.
When SMBus is selected in the Crossbar, the pins associated with SDA and SCL will automatically be
forced into open-drain output mode regardless of the PnMDOUT setting.
SPI0 can be operated in either 3-wire or 4-wire modes, depending on the state of the NSSMD1-
NSSMD0 bits in register SPI0CN. The NSS signal is only routed to a Port pin when 4-wire mode is
selected. When SPI0 is selected in the Crossbar, the SPI0 mode (3-wire or 4-wire) will affect the pinout
of all digital functions lower in priority than SPI0.
For given XBRn, PnSKIP, and SPInCN register settings, one can determine the I/O pin-out of the
device using Figure 21.3 and Figure 21.4.
Rev. 1.0
211
Si1000/1/2/3/4/5
P0
P1
P2
EZRadioPRO
Serial
SF Signals
Interface
PIN I/O
TX0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4 5 6 7
RX0
SCK (SPI1)
MISO (SPI1)
MOSI (SPI1)
SCK (SPI0)
MISO (SPI0)
MOSI (SPI0)
NSS* (SPI0)
SDA
(*4-Wire SPI Only)
SCL
CP0
CP0A
CP1
CP1A
/SYSCLK
CEX0
CEX1
CEX2
CEX3
CEX4
CEX5
ECI
T0
T1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0 0 X
P0SKIP[0:7]
P1SKIP[0:7]
P2SKIP[0:7]
Figure 21.3. Crossbar Priority Decoder with No Pins Skipped
212
Rev. 1.0
Si1000/1/2/3/4/5
P0
P1
P2
EZRadioPRO
Serial
SF Signals
Interface
PIN I/O
TX0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0 1 2 3 4 5 6 7
RX0
SCK (SPI1)
MISO (SPI1)
MOSI (SPI1)
NSS* (SPI1)
SCK (SPI0)
MISO (SPI0)
MOSI (SPI0)
NSS* (SPI0)
SDA
(*4-Wire SPI Only)
SCL
CP0
CP0A
CP1
CP1A
/SYSCLK
CEX0
CEX1
CEX2
CEX3
CEX4
CEX5
ECI
T0
T1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0 0
0 0 0 0 X
P0SKIP[0:7]
P1SKIP[0:7]
P2SKIP[0:7]
Figure 21.4. Crossbar Priority Decoder with Crystal Pins Skipped
Rev. 1.0
213
Si1000/1/2/3/4/5
SFR Definition 21.1. XBR0: Port I/O Crossbar Register 0
Bit
7
CP1AE
R/W
0
6
CP1E
R/W
0
5
CP0AE
R/W
0
4
CP0E
R/W
0
3
SYSCKE
R/W
2
SMB0E
R/W
0
1
SPI0E
R/W
0
0
URT0E
R/W
0
Name
Type
Reset
0
SFR Page = 0x0; SFR Address = 0xE1
Bit
Name
Function
7
CP1AE Comparator1 Asynchronous Output Enable.
0: Asynchronous CP1 output unavailable at Port pin.
1: Asynchronous CP1 output routed to Port pin.
6
5
4
3
2
1
CP1E
Comparator1 Output Enable.
0: CP1 output unavailable at Port pin.
1: CP1 output routed to Port pin.
CP0AE Comparator0 Asynchronous Output Enable.
0: Asynchronous CP0 output unavailable at Port pin.
1: Asynchronous CP0 output routed to Port pin.
CP0E
Comparator0 Output Enable.
0: CP1 output unavailable at Port pin.
1: CP1 output routed to Port pin.
SYSCKE SYSCLK Output Enable.
0: SYSCLK output unavailable at Port pin.
1: SYSCLK output routed to Port pin.
SMB0E SMBus I/O Enable.
0: SMBus I/O unavailable at Port pin.
1: SDA and SCL routed to Port pins.
SPI0E
SPI0 I/O Enable
0: SPI0 I/O unavailable at Port pin.
1: SCK, MISO, and MOSI (for SPI0) routed to Port pins.
NSS (for SPI0) routed to Port pin only if SPI0 is configured to 4-wire mode.
0
URT0E Comparator1 Asynchronous Output Enable.
0: UART I/O unavailable at Port pin.
1: TX0 and RX0 routed to Port pins P0.4 and P0.5.
Note: SPI0 can be assigned either 3 or 4 Port I/O pins.
214
Rev. 1.0
Si1000/1/2/3/4/5
SFR Definition 21.2. XBR1: Port I/O Crossbar Register 1
Bit
7
6
SPI1E
R/W
0
5
4
3
ECIE
R/W
0
2
1
0
Name
Type
Reset
T1E
R/W
0
T0E
R/W
0
PCA0ME[2:0]
R/W
0
R/W
0
R/W
0
R/W
0
SFR Page = 0x0; SFR Address = 0xE2
Bit
Name
Function
7
Unused Read = 0b; Write = Don’t Care.
6
SPI1E
EZRadioPRO Serial Interface (SPI1) Enable.
0: EZRadioPRO peripheral unavailable.
1: SCK (for EZRadioPRO) routed to P1.0.
MISO (for EZRadioPRO) routed to P1.1.
MOSI (for EZRadioPRO) routed to P1.2.
NSS (for EZRadioPRO) routed to P1.3 only if SPI1 is configured to 4-wire mode.
Note: When communicating with EZRadioPRO, the SPI1 should be configured to 3-
wire mode and P1.4 should be used as a standard Port I/O pin to control NSS.
5
4
T1E
T0E
Timer1 Input Enable.
0: T1 input unavailable at Port pin.
1: T1 input routed to Port pin.
Timer0 Input Enable.
0: T0 input unavailable at Port pin.
1: T0 input routed to Port pin.
3
ECIE
PCA0 External Counter Input (ECI) Enable.
0: PCA0 external counter input unavailable at Port pin.
1: PCA0 external counter input routed to Port pin.
2:0
PCA0ME PCA0 Module I/O Enable.
000: All PCA0 I/O unavailable at Port pin.
001: CEX0 routed to Port pin.
010: CEX0, CEX1 routed to Port pins.
011: CEX0, CEX1, CEX2 routed to Port pins.
100: CEX0, CEX1, CEX2 CEX3 routed to Port pins.
101: CEX0, CEX1, CEX2, CEX3, CEX4 routed to Port pins.
110: CEX0, CEX1, CEX2, CEX3, CEX4, CEX5 routed to Port pins.
111: Reserved.
Note: SPI1 can be assigned either 3 or 4 Port I/O pins.
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SFR Definition 21.3. XBR2: Port I/O Crossbar Register 2
Bit
7
6
XBARE
R/W
0
5
4
3
2
1
0
Name WEAKPUD
Type
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
SFR Page = 0x0; SFR Address = 0xE3
Bit
Name
Function
7
WEAKPUD Port I/O Weak Pullup Disable
0: Weak Pullups enabled (except for Port I/O pins configured for analog mode).
6
XBARE
Unused
Crossbar Enable
0: Crossbar disabled.
1: Crossbar enabled.
5:0
Read = 000000b; Write = Don’t Care.
Note: The Crossbar must be enabled (XBARE = 1) to use any Port pin as a digital output.
21.4. Port Match
Port match functionality allows system events to be triggered by a logic value change on P0 or P1. A soft-
ware controlled value stored in the PnMAT registers specifies the expected or normal logic values of P0
and P1. A Port mismatch event occurs if the logic levels of the Port’s input pins no longer match the soft-
ware controlled value. This allows Software to be notified if a certain change or pattern occurs on P0 or P1
input pins regardless of the XBRn settings.
The PnMASK registers can be used to individually select which P0 and P1 pins should be compared
against the PnMAT registers. A Port mismatch event is generated if (P0 & P0MASK) does not equal
(PnMAT & P0MASK) or if (P1 & P1MASK) does not equal (PnMAT & P1MASK).
A Port mismatch event may be used to generate an interrupt or wake the device from a low power mode.
See Section “12. Interrupt Handler” on page 129 and Section “14. Power Management” on page 151 for
more details on interrupt and wake-up sources.
216
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SFR Definition 21.4. P0MASK: Port0 Mask Register
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P0MASK[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page= 0x0; SFR Address = 0xC7
Bit
Name
Function
7:0
P0MASK[7:0] Port0 Mask Value.
Selects the P0 pins to be compared with the corresponding bits in P0MAT.
0: P0.n pin pad logic value is ignored and cannot cause a Port Mismatch event.
1: P0.n pin pad logic value is compared to P0MAT.n.
SFR Definition 21.5. P0MAT: Port0 Match Register
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P0MAT[7:0]
R/W
1
1
1
1
1
1
1
1
SFR Page= 0x0; SFR Address = 0xD7
Bit
Name
Function
7:0
P0MAT[7:0] Port 0 Match Value.
Match comparison value used on Port 0 for bits in P0MASK which are set to 1.
0: P0.n pin logic value is compared with logic LOW.
1: P0.n pin logic value is compared with logic HIGH.
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SFR Definition 21.6. P1MASK: Port1 Mask Register
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P1MASK[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page= 0x0; SFR Address = 0xBF
Bit
Name
Function
7:0
P1MASK[7:0] Port 1 Mask Value.
Selects P1 pins to be compared to the corresponding bits in P1MAT.
0: P1.n pin logic value is ignored and cannot cause a Port Mismatch event.
1: P1.n pin logic value is compared to P1MAT.n.
Note: P1.0, P1.1, P1.2, and P1.4 are internally connected to the EZRadioPRO peripheral. P1.3 is not externally or
internally connected.
SFR Definition 21.7. P1MAT: Port1 Match Register
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P1MAT[7:0]
R/W
1
1
1
1
1
1
1
1
SFR Page = 0x0; SFR Address = 0xCF
Bit
Name
Function
7:0
P1MAT[7:0] Port 1 Match Value.
Match comparison value used on Port 1 for bits in P1MASK which are set to 1.
0: P1.n pin logic value is compared with logic LOW.
1: P1.n pin logic value is compared with logic HIGH.
Note: P1.0, P1.1, P1.2, and P1.4 are internally connected to the EZRadioPRO peripheral. P1.3 is not externally or
internally connected.
218
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21.5. Special Function Registers for Accessing and Configuring Port I/O
All Port I/O are accessed through corresponding special function registers (SFRs) that are both byte
addressable and bit addressable. When writing to a Port, the value written to the SFR is latched to main-
tain the output data value at each pin. When reading, the logic levels of the Port's input pins are returned
regardless of the XBRn settings (i.e., even when the pin is assigned to another signal by the Crossbar, the
Port register can always read its corresponding Port I/O pin). The exception to this is the execution of the
read-modify-write instructions that target a Port Latch register as the destination. The read-modify-write
instructions when operating on a Port SFR are the following: ANL, ORL, XRL, JBC, CPL, INC, DEC, DJNZ
and MOV, CLR or SETB, when the destination is an individual bit in a Port SFR. For these instructions, the
value of the latch register (not the pin) is read, modified, and written back to the SFR.
Each Port has a corresponding PnSKIP register which allows its individual Port pins to be assigned to dig-
ital functions or skipped by the Crossbar. All Port pins used for analog functions, GPIO, or dedicated digital
functions such as the EMIF should have their PnSKIP bit set to 1.
The Port input mode of the I/O pins is defined using the Port Input Mode registers (PnMDIN). Each Port
cell can be configured for analog or digital I/O. This selection is required even for the digital resources
selected in the XBRn registers, and is not automatic. The only exception to this is P2.7, which can only be
used for digital I/O.
The output driver characteristics of the I/O pins are defined using the Port Output Mode registers (PnMD-
OUT). Each Port Output driver can be configured as either open drain or push-pull. This selection is
required even for the digital resources selected in the XBRn registers, and is not automatic. The only
exception to this is the SMBus (SDA, SCL) pins, which are configured as open-drain regardless of the
PnMDOUT settings.
The drive strength of the output drivers are controlled by the Port Drive Strength (PnDRV) registers. The
default is low drive strength. See Section “4. Electrical Characteristics” on page 40 for the difference in out-
put drive strength between the two modes.
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SFR Definition 21.8. P0: Port0
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P0[7:0]
R/W
1
1
1
1
1
1
1
1
SFR Page = All Pages; SFR Address = 0x80; Bit-Addressable
Bit
Name
P0[7:0] Port 0 Data.
Sets the Port latch logic
Description
Write
0: Set output latch to logic 0: P0.n Port pin is logic
LOW. LOW.
1: Set output latch to logic 1: P0.n Port pin is logic
Read
7:0
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
HIGH.
HIGH.
SFR Definition 21.9. P0SKIP: Port0 Skip
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P0SKIP[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page= 0x0; SFR Address = 0xD4
Bit Name
7:0 P0SKIP[7:0] Port 0 Crossbar Skip Enable Bits.
Function
These bits select Port 0 pins to be skipped by the Crossbar Decoder. Port pins used
for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P0.n pin is not skipped by the Crossbar.
1: Corresponding P0.n pin is skipped by the Crossbar.
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SFR Definition 21.10. P0MDIN: Port0 Input Mode
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P0MDIN[7:0]
R/W
1
1
1
1
1
1
1
1
SFR Page= 0x0; SFR Address = 0xF1
Bit Name
Function
7:0 P0MDIN[7:0] Analog Configuration Bits for P0.7–P0.0 (respectively).
Port pins configured for analog mode have their weak pullup, and digital receiver
disabled. The digital driver is not explicitly disabled.
0: Corresponding P0.n pin is configured for analog mode.
1: Corresponding P0.n pin is not configured for analog mode.
SFR Definition 21.11. P0MDOUT: Port0 Output Mode
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P0MDOUT[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xA4
Bit Name
Function
7:0 P0MDOUT[7:0] Output Configuration Bits for P0.7–P0.0 (respectively).
These bits control the digital driver even when the corresponding bit in register
P0MDIN is logic 0.
0: Corresponding P0.n Output is open-drain.
1: Corresponding P0.n Output is push-pull.
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SFR Definition 21.12. P0DRV: Port0 Drive Strength
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P0DRV[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0xF; SFR Address = 0xA4
Bit Name
7:0 P0DRV[7:0] Drive Strength Configuration Bits for P0.7–P0.0 (respectively).
Function
Configures digital I/O Port cells to high or low output drive strength.
0: Corresponding P0.n Output has low output drive strength.
1: Corresponding P0.n Output has high output drive strength.
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SFR Definition 21.13. P1: Port1
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P1[7:0]
R/W
1
1
1
1
1
1
1
1
SFR Page = All Pages; SFR Address = 0x90; Bit-Addressable
Bit
Name
P1[7:0] Port 1 Data.
Sets the Port latch logic
Description
Write
0: Set output latch to logic 0: P1.n Port pin is logic
LOW. LOW.
1: Set output latch to logic 1: P1.n Port pin is logic
Read
7:0
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
HIGH.
HIGH.
Note: P1.0, P1.1, P1.2, and P1.4 are internally connected to the EZRadioPRO peripheral. P1.3 is not externally or
internally connected.
SFR Definition 21.14. P1SKIP: Port1 Skip
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P1SKIP[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xD5
Bit Name
7:0 P1SKIP[7:0] Port 1 Crossbar Skip Enable Bits.
Function
These bits select Port 1 pins to be skipped by the Crossbar Decoder. Port pins used
for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P1.n pin is not skipped by the Crossbar.
1: Corresponding P1.n pin is skipped by the Crossbar.
Note: P1.0, P1.1, P1.2, and P1.4 are internally connected to the EZRadioPRO peripheral. P1.3 is not externally or
internally connected. P1.3 and P1.4 should always be skipped in the crossbar.
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SFR Definition 21.15. P1MDIN: Port1 Input Mode
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P1MDIN[7:0]
R/W
1
1
1
1
1
1
1
1
SFR Page = 0x0; SFR Address = 0xF2
Bit Name
Function
7:0 P1MDIN[7:0] Analog Configuration Bits for P1.7–P1.0 (respectively).
Port pins configured for analog mode have their weak pullup and digital receiver
disabled. The digital driver is not explicitly disabled.
0: Corresponding P1.n pin is configured for analog mode.
1: Corresponding P1.n pin is not configured for analog mode.
Note: P1.0, P1.1, P1.2, and P1.4 are internally connected to the EZRadioPRO peripheral. P1.3 is not externally or
internally connected.
SFR Definition 21.16. P1MDOUT: Port1 Output Mode
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P1MDOUT[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xA5
Bit Name
Function
7:0 P1MDOUT[7:0] Output Configuration Bits for P1.7–P1.0 (respectively).
These bits control the digital driver even when the corresponding bit in register
P1MDIN is logic 0.
0: Corresponding P1.n Output is open-drain.
1: Corresponding P1.n Output is push-pull.
Note: P1.0, P1.1, P1.2, and P1.4 are internally connected to the EZRadioPRO peripheral. P1.3 is not externally or
internally connected.
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SFR Definition 21.17. P1DRV: Port1 Drive Strength
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P1DRV[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0xF; SFR Address = 0xA5
Bit Name
7:0 P1DRV[7:0] Drive Strength Configuration Bits for P1.7–P1.0 (respectively).
Function
Configures digital I/O Port cells to high or low output drive strength.
0: Corresponding P1.n Output has low output drive strength.
1: Corresponding P1.n Output has high output drive strength.
Note: P1.0, P1.1, P1.2, and P1.4 are internally connected to the EZRadioPRO peripheral. P1.3 is not externally or
internally connected.
SFR Definition 21.18. P2: Port2
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P2[7:0]
R/W
1
1
1
1
1
1
1
1
SFR Page = All Pages; SFR Address = 0xA0; Bit-Addressable
Bit
Name
P2[7:0] Port 2 Data.
Sets the Port latch logic
Description
Read
0: Set output latch to logic 0: P2.n Port pin is logic
LOW. LOW.
1: Set output latch to logic 1: P2.n Port pin is logic
Write
7:0
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
HIGH.
HIGH.
Rev. 1.0
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SFR Definition 21.19. P2SKIP: Port2 Skip
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P2SKIP[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xD6
Bit
Name
Description
Read
Write
7:0
P2SKIP[7:0] Port 1 Crossbar Skip Enable Bits.
These bits select Port 2 pins to be skipped by the Crossbar Decoder. Port pins
used for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P2.n pin is not skipped by the Crossbar.
1: Corresponding P2.n pin is skipped by the Crossbar.
SFR Definition 21.20. P2MDIN: Port2 Input Mode
Bit
7
6
5
4
3
2
1
0
Name Reserved
P2MDIN[6:0]
Type
R/W
Reset
1
1
1
1
1
1
1
1
SFR Page = 0x0; SFR Address = 0xF3
Bit
Name
Function
7
Reserved. Read = 1b; Must Write 1b.
P2MDIN[3:0] Analog Configuration Bits for P2.6–P2.0 (respectively).
6:0
Port pins configured for analog mode have their weak pullup and digital receiver
disabled. The digital driver is not explicitly disabled.
0: Corresponding P2.n pin is configured for analog mode.
1: Corresponding P2.n pin is not configured for analog mode.
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SFR Definition 21.21. P2MDOUT: Port2 Output Mode
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P2MDOUT[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xA6
Bit Name
Function
7:0 P2MDOUT[7:0] Output Configuration Bits for P2.7–P2.0 (respectively).
These bits control the digital driver even when the corresponding bit in register
P2MDIN is logic 0.
0: Corresponding P2.n Output is open-drain.
1: Corresponding P2.n Output is push-pull.
SFR Definition 21.22. P2DRV: Port2 Drive Strength
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P2DRV[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0x0F; SFR Address = 0xA6
Bit
Name
Function
7:0
P2DRV[7:0] Drive Strength Configuration Bits for P2.7–P2.0 (respectively).
Configures digital I/O Port cells to high or low output drive strength.
0: Corresponding P2.n Output has low output drive strength.
1: Corresponding P2.n Output has high output drive strength.
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22. EZRadioPRO® Serial Interface (SPI1)
The EZRadioPRO serial interface (SPI1) provides access to the EZRadioPRO peripheral registers from
software executing on the MCU core. The serial interface consists of two SPI peripherals -- a dedicated
SPI Master accessible from the MCU core and dedicated SPI Slave residing inside the EZRadioPRO
peripheral. The SPI1 peripheral on the MCU core side can only be used in master mode to communicate
with the EZRadioPRO slave device in three wire mode. NSS for the EZRadioPRO is provided using Port
1.4, which is internally routed to the EZRadioPRO peripheral. The EZRadioPRO Serial Interface provides
a system interrupt to regulate SPI traffic between the MCU core and the EZRadioPRO peripheral. This
interrupt is internally routed to the MCU core. The EZRadioPRO peripheral also has an nIRQ pin which
should be routed external to the package back into an external interrupt pin. The nIRQ interrupt pin is
independent of the EZRadioPRO Serial Interface.
SFR Bus
SPI1CKR
SPI1CFG
SPI1CN
Clock Divide
Logic
SYSCLK
SPI CONTROL LOGIC
EZRadioPRO Serial Interface (SPI1) IRQ
Data Path
Control
Pin Interface
Control
P1.0
SCK
SCK
Tx Data
C
R
O
S
S
B
A
R
SPI1DAT
P1.1
MISO
MOSI
NSS
MISO
Transmit Data Buffer
Pin
Control
Logic
EZRadioPRO
Peripheral
Shift Register
P1.2
P1.4
MOSI
NSS
Rx Data
7 6 5 4 3 2 1 0
Receive Data Buffer
Read
SPI0DAT
Write
SPI0DAT
SFR Bus
Figure 22.1. EZRadioPRO Serial Interface Block Diagram
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22.1. Signal Descriptions
The four signals used by SPI1 (MOSI, MISO, SCK, NSS) are described below.
22.1.1. Master Out, Slave In (MOSI)
The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices. It
is used to serially transfer data from the master to the slave. This signal is an output from the MCU core
and an input to the EZRadioPRO peripheral. Data is transferred most-significant bit first. MOSI is driven by
the MSB of the shift register.
22.1.2. Master In, Slave Out (MISO)
The master-in, slave-out (MISO) signal is an output from a slave device and an input to master devices. It
is used to serially transfer data from the EZRadioPRO to the MCU core. This signal is an input to the MCU
core and an output from the EZRadioPRO peripheral. Data is transferred most-significant bit first. The
MISO pin is placed in a high-impedance state when the SPI module is disabled.
22.1.3. Serial Clock (SCK)
The serial clock (SCK) signal is an output from the master device and an input to slave devices. It is used
to synchronize the transfer of data between the master and slave on the MOSI and MISO lines. SPI1 gen-
erates this signal.
22.1.4. Slave Select (NSS)
Since SPI1 operates in three wire mode, the NSS functionality built into the SPI state machine is not used.
Instead, a Port pin must be configured to control the chip select on the EZRadioPRO peripheral.
22.2. SPI Master Operation on the MCU Core Side
A SPI master device initiates all data transfers on a SPI bus. SPI1 is placed in master mode by setting the
Master Enable flag (MSTENn, SPI1CN.6). Writing a byte of data to the SPI1 data register (SPI1DAT) when
in master mode writes to the transmit buffer. If the SPI shift register is empty, the byte in the transmit buffer
is moved to the shift register, and a data transfer begins. The SPI1 master immediately shifts out the data
serially on the MOSI line while providing the serial clock on SCK. The SPIF1 (SPI1CN.7) flag is set to logic
1 at the end of the transfer. If interrupts are enabled, an interrupt request is generated when the SPIF flag
is set. While the SPI1 master transfers data to a slave on the MOSI line, the addressed SPI slave device
simultaneously transfers the contents of its shift register to the SPI master on the MISO line in a full-duplex
operation. Therefore, the SPIF flag serves as both a transmit-complete and receive-data-ready flag. The
data byte received from the slave is transferred MSB-first into the master's shift register. When a byte is
fully shifted into the register, it is moved to the receive buffer where it can be read by the processor by
reading SPI1DAT.
22.3. SPI Slave Operation on the EZRadioPRO Peripheral Side
The EZRadioPRO peripheral presents a standard 4-wire SPI interface: SCK, MISO, MOSI and NSS. The
SPI master can read data from the device on the MOSI output pin. A SPI transaction is a 16-bit sequence
which consists of a Read-Write (R/W) select bit, followed by a 7-bit address field (ADDR), and an 8-bit data
field (DATA) as demonstrated in Figure 22.2. The 7-bit address field is used to select one of the 128, 8-bit
control registers. The R/W select bit determines whether the SPI transaction is a read or write transaction.
If R/W = 1 it signifies a WRITE transaction, while R/W = 0 signifies a READ transaction. The contents
(ADDR or DATA) are latched into the transceiver every eight clock cycles. The timing parameters for the
SPI interface are shown in Table 22.1. The SCK rate is flexible with a maximum rate of 10 MHz.
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Data
Address
MSB
LSB
RW A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 xx xx RW A7
MOSI
SCL
NSS
Figure 22.2. SPI Timing
Table 22.1. Serial Interface Timing Parameters
Symbol
Parameter
Min
Diagram
(nsec)
t
Clock high time
Clock low time
Data setup time
Data hold time
40
40
20
20
20
CH
t
CL
DS
DH
DD
SCL
t
tSS
tCL tCH
tDS tDH tDD
tSH tDE
t
t
Output data delay
time
MOSI
MISO
t
t
Output enable time
Output disable time
Select setup time
Select hold time
20
50
20
50
80
EN
tEN
tSW
DE
NSS
t
SS
SH
t
t
Select high period
SW
To read back data from the transceiver, the R/W bit must be set to 0 followed by the 7-bit address of the
register from which to read. The 8 bit DATA field following the 7-bit ADDR field is ignored on the MOSI pin
when R/W = 0. The next eight negative edge transitions of the SCK signal will clock out the contents of the
selected register. The data read from the selected register will be available on the MISO output. The READ
function is shown in Figure 22.3. After the READ function is completed the MISO signal will remain at
either a logic 1 or logic 0 state depending on the last data bit clocked out (D0). When NSS goes high the
MISO output pin will be pulled high by internal pullup.
First Bit
Last Bit
RW
=0
D7 D6 D5 D4 D3 D2 D1 D0
=X =X =X =X =X =X =X =X
A6 A5 A4 A3 A2 A1 A0
MOSI
SCL
First Bit
Last Bit
MISO
D7 D6 D5 D4 D3 D2 D1 D0
NSS
Figure 22.3. SPI Timing—READ Mode
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The SPI interface contains a burst read/write mode which allows for reading/writing sequential registers
without having to re-send the SPI address. When the NSS bit is held low while continuing to send SCK
pulses, the SPI interface will automatically increment the ADDR and read from/write to the next address.
An example burst write transaction is illustrated in Figure 22.4 and a burst read in Figure 22.5. As long as
NSS is held low, input data will be latched into the transceiver every eight SCK cycles.
First Bit
Last Bit
RW
=1
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
=X =X =X =X =X =X =X =X =X =X =X =X =X =X =X =X
MOSI
A6 A5 A4 A3 A2 A1 A0
SCL
NSS
Figure 22.4. SPI Timing—Burst Write Mode
First Bit
Last Bit
RW
=0
D7 D6 D5 D4 D3 D2 D1 D0
=X =X =X =X =X =X =X =X
A6 A5 A4 A3 A2 A1 A0
MOSI
SCL
First Bit
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
S
MISO
NSS
Figure 22.5. SPI Timing—Burst Read Mode
Rev. 1.0
231
Si1000/1/2/3/4/5
22.4. EZRadioPRO Serial Interface Interrupt Sources
When SPI1 interrupts are enabled, the following flags will generate an interrupt when they are set to logic
1:
All of the following bits must be cleared by software.
1. The SPI Interrupt Flag, SPIFn (SPInCN.7) is set to logic 1 at the end of each byte transfer.
This flag can occur in all SPIn modes.
2. The Write Collision Flag, WCOLn (SPInCN.6) is set to logic 1 if a write to SPInDAT is
attempted when the transmit buffer has not been emptied to the SPI shift register. When this
occurs, the write to SPInDAT will be ignored, and the transmit buffer will not be written.This
flag can occur in all SPIn modes.
3. The Mode Fault Flag MODFn (SPInCN.5) is set to logic 1 when SPIn is configured as a
master, and for multi-master mode and the NSS pin is pulled low. When a Mode Fault occurs,
the MSTENn and SPIENn bits in SPI0CN are set to logic 0 to disable SPIn and allow another
master device to access the bus.
4. The Receive Overrun Flag RXOVRNn (SPInCN.4) is set to logic 1 when configured as a slave,
and a transfer is completed and the receive buffer still holds an unread byte from a previous
transfer. The new byte is not transferred to the receive buffer, allowing the previously received
data byte to be read. The data byte which caused the overrun is lost.
22.5. Serial Clock Phase and Polarity
Four combinations of serial clock phase and polarity can be selected using the clock control bits in the SPI
Configuration Register (SPI1CFG). The CKPHA bit (SPI1CFG.5) selects one of two clock phases (edge
used to latch the data). The CKPOL bit (SPI1CFG.4) selects between an active-high or active-low clock.
Both CKPOL and CKPHA must be set to zero in order to communicate with the EZRadioPRO peripheral.
The SPI1 Clock Rate Register (SPI1CKR) as shown in SFR Definition 22.3 controls the master mode
serial clock frequency. When the SPI is configured as a master, the maximum data transfer rate (bits/sec)
is one-half the system clock frequency or 12.5 MHz, whichever is slower.
SCK
(CKPOL=0, CKPHA=0)
SCK
(CKPOL=0, CKPHA=1)
SCK
(CKPOL=1, CKPHA=0)
SCK
(CKPOL=1, CKPHA=1)
MISO/MOSI
MSB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
NSS (Must Remain High
in Multi-Master Mode)
Figure 22.6. Master Mode Data/Clock Timing
232
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22.6. SPI Special Function Registers
SPI1 is accessed and controlled through four special function registers in the system controller: SPI1CN
Control Register, SPI1DAT Data Register, SPI1CFG Configuration Register, and SPI1CKR Clock Rate
Register. The special function registers related to the operation of the SPI1 Bus are described in the follow-
ing figures.
Rev. 1.0
233
Si1000/1/2/3/4/5
SFR Definition 22.1. SPI1CFG: SPI Configuration
Bit
7
6
MSTEN
R/W
0
5
CKPHA
R/W
0
4
CKPOL
R/W
0
3
2
1
0
Name SPIBSY
Type
R
0
R
0
R
1
R
1
R
1
Reset
SFR Page = 0x0; SFR Address = 0x84
Bit
Name
Function
7
SPIBSY
SPI Busy.
This bit is set to logic 1 when a SPI transfer is in progress.
6
5
MSTEN
CKPHA
CKPOL
Master Mode Enable.
When set to ‘1’, enables master mode. This bit must be set to 1 to communicate
with the EZRadioPRO peripheral.
SPI Clock Phase.
*
0: Data centered on first edge of SCK period.
1: Data centered on second edge of SCK period.
*
4
SPI Clock Polarity.
0: SCK line low in idle state.
1: SCK line high in idle state.
3:0
Reserved.
Read = 0000, Write = don’t care.
Note: In master mode, data on MISO is sampled one SYSCLK before the end of each data bit, to provide maximum
settling time for the slave device. See Table 22.2 for timing parameters.
234
Rev. 1.0
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SFR Definition 22.2. SPI1CN: SPI Control
Bit
7
6
5
4
3
2
1
0
SPI1EN
R/W
0
Name SPIF1 WCOL1 MODF1
NSS1MD1 NSS1MD0
TXBMT1
Type
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
R
1
Reset
SFR Page = 0x0; SFR Address = 0xB0; Bit-Addressable
Bit
Name
Function
7
SPIF1
SPI1 Interrupt Flag.
This bit is set to logic 1 by hardware at the end of a data transfer. If interrupts are
enabled, setting this bit causes the CPU to vector to the SPI1 interrupt service
routine. This bit is not automatically cleared by hardware. It must be cleared by
software.
6
5
4
WCOL1
MODF1
Write Collision Flag.
This bit is set to logic 1 by hardware (and generates a SPI1 interrupt) to indicate a
write to the SPI1 data register was attempted while a data transfer was in progress.
It must be cleared by software.
Mode Fault Flag.
This bit is set to logic 1 by hardware (and generates a SPI1 interrupt) when a mas-
ter mode collision is detected (NSS is low, MSTEN = 1, and NSSMD[1:0] = 01).
This bit is not automatically cleared by hardware. It must be cleared by software.
Reserved.
Read = varies; Write = must write zero.
3:2 NSS1MD[1:0] Slave Select Mode.
Must be set to 00b. SPI1 can only be used in 3-wire master mode.
Transmit Buffer Empty.
1
TXBMT1
This bit will be set to logic 0 when new data has been written to the transmit buffer.
When data in the transmit buffer is transferred to the SPI shift register, this bit will
be set to logic 1, indicating that it is safe to write a new byte to the transmit buffer.
0
SPI1EN
SPI1 Enable.
0: SPI1 disabled.
1: SPI1 enabled.
Rev. 1.0
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SFR Definition 22.3. SPI1CKR: SPI Clock Rate
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
SCR1[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0x85
Bit
Name
Function
7:0
SCR1
SPI Clock Rate.
These bits determine the frequency of the SCK output when the SPI module is
configured for master mode operation. The SCK clock frequency is a divided
version of the system clock, and is given in the following equation, where SYSCLK
is the system clock frequency and SPI1CKR is the 8-bit value held in the SPI1CKR
register.
SYSCLK
fSCK = ----------------------------------------------------------
2 SPI1CKR[7:0] + 1
for 0 <= SPI0CKR <= 255
Example: If SYSCLK = 2 MHz and SPI1CKR = 0x04,
2000000
fSCK = -------------------------
2 4 + 1
fSCK = 200kHz
236
Rev. 1.0
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SFR Definition 22.4. SPI1DAT: SPI Data
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
SPI1DAT[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0x86
Bit
Name
Function
7:0
SPI1DAT
SPI1 Transmit and Receive Data.
The SPI1DAT register is used to transmit and receive SPI1 data. Writing data to
SPI1DAT places the data into the transmit buffer and initiates a transfer when in
Master Mode. A read of SPI1DAT returns the contents of the receive buffer.
Rev. 1.0
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SCK*
T
T
MCKL
MCKH
T
T
MIS
MIH
MISO
MOSI
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
Figure 22.7. SPI Master Timing
Table 22.2. SPI Timing Parameters
Parameter
Description
Min
Max
Units
Master Mode Timing
T
T
T
T
SCK High Time
SCK Low Time
1 x T
1 x T
—
—
—
—
ns
ns
ns
ns
MCKH
MCKL
MIS
SYSCLK
SYSCLK
MISO Valid to SCK Shift Edge
1 x T
+ 20
SYSCLK
SCK Shift Edge to MISO Change
0
MIH
Note: TSYSCLK is equal to one period of the device system clock (SYSCLK).
238
Rev. 1.0
Si1000/1/2/3/4/5
23. EZRadioPRO® 240–960 MHz Transceiver
Si1000/1/2/3/4/5 devices include the EZRadioPRO family of ISM wireless transceivers with continuous fre-
quency tuning over 240–960 MHz. The wide operating voltage range of 1.8–3.6 V and low current con-
sumption makes the EZRadioPRO an ideal solution for battery powered applications.
The EZRadioPRO transceiver operates as a time division duplexing (TDD) transceiver where the device
alternately transmits and receives data packets. The device uses a single-conversion mixer to downcon-
vert the 2-level FSK/GFSK/OOK modulated receive signal to a low IF frequency. Following a programma-
ble gain amplifier (PGA) the signal is converted to the digital domain by a high performance ADC
allowing filtering, demodulation, slicing, and packet handling to be performed in the built-in DSP increasing
the receiver’s performance and flexibility versus analog based architectures. The demodulated signal is
then output to the system MCU through a programmable GPIO or via the standard SPI bus by reading the
64-byte RX FIFO.
A single high precision local oscillator (LO) is used for both transmit and receive modes since the transmit-
ter and receiver do not operate at the same time. The LO is generated by an integrated VCO and Frac-
tional-N PLL synthesizer. The synthesizer is designed to support configurable data rates, output frequency
and frequency deviation at any frequency between 240–960 MHz. The transmit FSK data is modulated
directly into the data stream and can be shaped by a Gaussian low-pass filter to reduce unwanted
spectral content.
The Si1000’s PA output power can be configured between –1 and +20 dBm in 3 dB steps, while the
Si1002/3/4/5's PA output power can be configured between –8 and +13 dBm in 3 dB steps. The PA is sin-
gle-ended to allow for easy antenna matching and low BOM cost. The PA incorporates automatic ramp-up
and rampdown control to reduce unwanted spectral spreading. The +20 dBm power amplifier of the
Si1000/1 can also be used to compensate for the reduced performance of a lower cost, lower performance
antenna or antenna with size constraints due to a small form-factor. Competing solutions require large and
expensive external PAs to achieve comparable performance. The EZRadioPRO transceivers support fre-
quency hopping, TX/RX switch control, and antenna diversity switch control to extend the link range and
improve performance.
The EZRadioPRO peripheral also controls three GPIO pins: GPIO_0, GPIO_1, and GPIO_2. See Applica-
tion Note “AN415: EZRadioPRO Programming Guide“ for details on initializing and using the EZRadioPRO
peripheral.
Rev. 1.0
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Si1000/1/2/3/4/5
23.1. EZRadioPRO Operating Modes
The EZRadioPRO transceivers provide several operating modes which can be used to optimize the power
consumption for a given application. Depending upon the system communication protocol, an optimal
trade-off between the radio wake time and power consumption can be achieved.
Table 23.1 summarizes the operating modes of the EZRadioPRO transceivers. In general, any given oper-
ating mode may be classified as an active mode or a power saving mode. The table indicates which
block(s) are enabled (active) in each corresponding mode. With the exception of the SHUTDOWN mode,
all can be dynamically selected by sending the appropriate commands over the SPI. An “X” in any cell
means that, in the given mode of operation, that block can be independently programmed to be either ON
or OFF, without noticeably impacting the current consumption. The SPI circuit block includes the SPI inter-
face hardware and the device register space. The 32 kHz OSC block includes the 32.768 kHz RC oscilla-
tor or 32.768 kHz crystal oscillator and wake-up timer. AUX (Auxiliary Blocks) includes the temperature
sensor, general purpose ADC, and low-battery detector.
Table 23.1. EZRadioPRO Operating Modes
Mode
Name
Circuit Blocks
32 kHz OSC AUX
Digital LDO
SPI
30 MHz
XTAL
PLL
PA
RX
I
VDD
SHUT-
DOWN
OFF (Regis-
ter contents
lost)
OFF
OFF
OFF
OFF
OFF
OFF OFF
15 nA
STANDBY ON (Register
ON
ON
ON
ON
ON
ON
OFF
ON
X
OFF
X
OFF
OFF
OFF
ON
OFF
OFF
OFF
OFF
ON
OFF OFF 450 nA
contents
retained)
SLEEP
OFF OFF
OFF OFF
1 µA
1 µA
SENSOR
READY
ON
X
X
OFF OFF 600 µA
OFF OFF 8.5 mA
TUNING
X
X
ON
TRANS-
MIT
X
X
ON
ON
ON
OFF 30 mA*
RECEIVE
ON
X
X
ON
ON
OFF
ON 18.5 mA
Note: Using Si1002/3 at +13 dBm using recommended reference design. These power modes are for the
EZRadioPRO peripheral only and are independent of the MCU power modes.
240
Rev. 1.0
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23.1.1. Operating Mode Control
There are four primary states in the EZRadioPRO transceiver radio state machine: SHUTDOWN, IDLE,
TX, and RX (see Figure 23.1). The SHUTDOWN state completely shuts down the radio to minimize current
consumption. There are five different configurations/options for the IDLE state which can be selected to
optimize the chip to the applications needs. "Register 07h. Operating Mode and Function Control 1" con-
trols which operating mode/state is selected with the exception of SHUTDOWN which is controlled by SDN
pin 20. The TX and RX state may be reached automatically from any of the IDLE states by setting the
txon/rxon bits in "Register 07h. Operating Mode and Function Control 1". Table 23.2 shows each of the
operating modes with the time required to reach either RX or TX mode as well as the current consumption
of each mode.
The transceivers include a low-power digital regulated supply (LPLDO) which is internally connected in
parallel to the output of the main digital regulator (and is available externally at the VR_DIG pin). This com-
mon digital supply voltage is connected to all digital circuit blocks including the digital modem, crystal oscil-
lator, SPI, and register space. The LPLDO has extremely low quiescent current consumption but limited
current supply capability; it is used only in the IDLE-STANDBY and IDLE-SLEEP modes. The main digital
regulator is automatically enabled in all other modes.
SHUTDOWN
IDLE*
TX
RX
*Five Different Options for IDLE
Figure 23.1. State Machine Diagram
Table 23.2. EZRadioPRO Operating Modes Response Time
State/Mode
Response Time to
Current in State /Mode
[µA]
TX
RX
Shut Down State
16.8 ms
16.8 ms
15 nA
Idle States:
Standby Mode
Sleep Mode
Sensor Mode
Ready Mode
Tune Mode
800 µs
800 µs
800 µs
200 µs
200 µs
800 µs
800 µs
800 µs
200 µs
200 µs
450 nA
1 µA
1 µA
800 µA
8.5 mA
TX State
RX State
NA
200 µs
NA
30 mA @ +13 dBm
18.5 mA
200 µs
Rev. 1.0
241
Si1000/1/2/3/4/5
23.1.1.1. SHUTDOWN State
The SHUTDOWN state is the lowest current consumption state of the device with nominally less than
15 nA of current consumption. The shutdown state may be entered by driving the SDN pin (Pin 20) high.
The SDN pin should be held low in all states except the SHUTDOWN state. In the SHUTDOWN state, the
contents of the registers are lost and there is no SPI access.
When the chip is connected to the power supply, a POR will be initiated after the falling edge of SDN. After
a POR, the device will be in READY mode with the buffers enabled.
23.1.1.1.1. IDLE State
There are five different modes in the IDLE state which may be selected by "Register 07h. Operating Mode
and Function Control 1". All modes have a tradeoff between current consumption and response time to
TX/RX mode. This tradeoff is shown in Table 23.2. After the POR event, SWRESET, or exiting from the
SHUTDOWN state the chip will default to the IDLE-READY mode. After a POR event the interrupt registers
must be read to properly enter the SLEEP, SENSOR, or STANDBY mode and to control the 32 kHz clock
correctly.
23.1.1.1.2. STANDBY Mode
STANDBY mode has the lowest current consumption of the five IDLE states with only the LPLDO enabled
to maintain the register values. In this mode the registers can be accessed in both read and write mode.
The STANDBY mode can be entered by writing 0h to "Register 07h. Operating Mode and Function Control
1". If an interrupt has occurred (i.e., the nIRQ pin = 0) the interrupt registers must be read to achieve the
minimum current consumption. Additionally, the ADC should not be selected as an input to the GPIO in this
mode as it will cause excess current consumption.
23.1.1.1.3. SLEEP Mode
In SLEEP mode the LPLDO is enabled along with the Wake-Up-Timer, which can be used to accurately
wake-up the radio at specified intervals. See “Wake-Up Timer and 32 kHz Clock Source” on page 275 for
more information on the Wake-Up-Timer. SLEEP mode is entered by setting enwt = 1 (40h) in "Register
07h. Operating Mode and Function Control 1". If an interrupt has occurred (i.e., the nIRQ pin = 0) the inter-
rupt registers must be read to achieve the minimum current consumption. Also, the ADC should not be
selected as an input to the GPIO in this mode as it will cause excess current consumption.
23.1.1.1.4. SENSOR Mode
In SENSOR mode either the Low Battery Detector, Temperature Sensor, or both may be enabled in addi-
tion to the LPLDO and Wake-Up-Timer. The Low Battery Detector can be enabled by setting enlbd = 1 in
"Register 07h. Operating Mode and Function Control 1". See “Temperature Sensor” on page 272 and “Low
Battery Detector” on page 274 for more information on these features. If an interrupt has occurred (i.e.,
the nIRQ pin = 0) the interrupt registers must be read to achieve the minimum current consumption.
23.1.1.1.5. READY Mode
READY Mode is designed to give a fast transition time to TX mode with reasonable current consumption.
In this mode the Crystal oscillator remains enabled reducing the time required to switch to TX or RX mode
by eliminating the crystal start-up time. READY mode is entered by setting xton = 1 in "Register 07h. Oper-
ating Mode and Function Control 1". To achieve the lowest current consumption state the crystal oscillator
buffer should be disabled in “Register 62h. Crystal Oscillator Control and Test.” To exit READY mode,
bufovr (bit 1) of this register must be set back to 0.
23.1.1.1.6. TUNE Mode
In TUNE mode the PLL remains enabled in addition to the other blocks enabled in the IDLE modes. This
will give the fastest response to TX mode as the PLL will remain locked but it results in the highest current
consumption. This mode of operation is designed for frequency hopping spread spectrum systems
(FHSS). TUNE mode is entered by setting pllon = 1 in "Register 07h. Operating Mode and Function Con-
trol 1". It is not necessary to set xton to 1 for this mode, the internal state machine automatically enables
the crystal oscillator.
242
Rev. 1.0
Si1000/1/2/3/4/5
23.1.1.2. TX State
The TX state may be entered from any of the IDLE modes when the txon bit is set to 1 in "Register 07h.
Operating Mode and Function Control 1". A built-in sequencer takes care of all the actions required to tran-
sition between states from enabling the crystal oscillator to ramping up the PA. The following sequence of
events will occur automatically when going from STANDBY mode to TX mode by setting the txon bit.
1. Enable the main digital LDO and the Analog LDOs.
2. Start up crystal oscillator and wait until ready (controlled by an internal timer).
3. Enable PLL.
4. Calibrate VCO (this action is skipped when the skipvco bit is 1, default value is 0).
5. Wait until PLL settles to required transmit frequency (controlled by an internal timer).
6. Activate power amplifier and wait until power ramping is completed (controlled by an internal timer).
7. Transmit packet.
Steps in this sequence may be eliminated depending on which IDLE mode the chip is configured to prior to
setting the txon bit. By default, the VCO and PLL are calibrated every time the PLL is enabled.
23.1.1.3. RX State
The RX state may be entered from any of the IDLE modes when the rxon bit is set to 1 in "Register 07h.
Operating Mode and Function Control 1". A built-in sequencer takes care of all the actions required to tran-
sition from one of the IDLE modes to the RX state. The following sequence of events will occur automati-
cally to get the chip into RX mode when going from STANDBY mode to RX mode by setting the rxon bit:
1. Enable the main digital LDO and the Analog LDOs.
2. Start up crystal oscillator and wait until ready (controlled by an internal timer).
3. Enable PLL.
4. Calibrate VCO (this action is skipped when the skipvco bit is 1, default value is 0).
5. Wait until PLL settles to required receive frequency (controlled by an internal timer).
6. Enable receive circuits: LNA, mixers, and ADC.
7. Enable receive mode in the digital modem.
Depending on the configuration of the radio all or some of the following functions will be performed auto-
matically by the digital modem: AGC, AFC (optional), update status registers, bit synchronization, packet
handling (optional) including sync word, header check, and CRC.
23.1.1.4. Device Status
D7
D6
D5
D4
D3
D2
D1
D0 POR Def.
Add R/W
Function/
Description
02
R
Device Status
ffovfl ffunfl
rxffem
headerr
freqerr
cps[1] cps[0]
—
The operational status of the EZRadioPRO peripheral can be read from "Register 02h. Device Status".
23.2. Interrupts
The EZRadioPRO peripheral is capable of generating an interrupt signal (nIRQ) when certain events
occur. The nIRQ pin is driven low to indicate a pending interrupt request. The EZRadioPRO interrupt
does not have an internal interrupt vector. To use the interrupt, the nIRQ pin must be looped back
to an external interrupt input. This interrupt signal will be generated when any one (or more) of the inter-
rupt events (corresponding to the Interrupt Status bits) shown below occur. The nIRQ pin will remain low
until the Interrupt Status Register(s) (Registers 03h–04h) containing the active Interrupt Status bit is read.
The nIRQ output signal will then be reset until the next change in status is detected. The interrupts must be
Rev. 1.0
243
Si1000/1/2/3/4/5
enabled by the corresponding enable bit in the Interrupt Enable Registers (Registers 05h–06h). All
enabled interrupt bits will be cleared when the corresponding interrupt status register is read. If the inter-
rupt is not enabled when the event occurs it will not trigger the nIRQ pin, but the status may still be read at
anytime in the Interrupt Status registers.
Important Note: The nIRQ line should not be monitored for POR after SDN or initial power up. The POR
signal is available by default on GPIO0 and GPIO1 and should be monitored as an alternative to nIRQ for
POR. As an alternative, software may wait 18 ms after SDN rising before polling the interrupt status regis-
ters in 03h and 04h to check for POR and chip ready (XTAL start-up/ready). This process may take up to
26 ms. After the initial interrupt is cleared, the operation of the nIRQ pin will be normal.
D7
D6
D5
D4
D3
D2
D1
D0
POR
Def.
Add R/W
Function/
Description
03
04
R
R
Interrupt Status 1
ifferr
itxffafull
itxffaem
irxffafull
irssi
iext ipksent ipkvalid icrcerror
iwut ilbd ichiprdy ipor
—
—
Interrupt Status 2 iswdet ipreaval ipreainval
05 R/W Interrupt Enable 1 enfferr entxffafull entxffaem enrxffafull enext enpksent enpkvalid encrcerror
06 R/W Interrupt Enable 2 enswdet enpreava enpreainval enrssi enwut enlbd enchiprdy enpor
00h
01h
See “AN440: EZRadioPRO Detailed Register Descriptions” for a complete list of interrupts.
23.3. System Timing
The system timing for TX and RX modes is shown in Figures 23.2 and 23.3. The figures demonstrate tran-
sitioning from STANDBY mode to TX or RX mode through the built-in sequencer of required steps. The
user only needs to program the desired mode, and the internal sequencer will properly transition the part
from its current mode.
The VCO will automatically calibrate at every frequency change or power up. The PLL T0 time is to allow
for bias settling of the VCO. The PLL TS time is for the settling time of the PLL, which has a default setting
of 100 µs. The total time for PLL T0, PLL CAL, and PLL TS under all conditions is 200 µs. Under certain
applications, the PLL T0 time and the PLL CAL may be skipped for faster turn-around time. Contact appli-
cations support if faster turnaround time is desired.
XTAL Settling
TX Packet
Time
600us
Figure 23.2. TX Timing
244
Rev. 1.0
Si1000/1/2/3/4/5
XTAL Settling
Time
RX Packet
600us
Figure 23.3. RX Timing
23.3.1. Frequency Control
For calculating the necessary frequency register settings it is recommended that customers use Silicon
Labs’ Wireless Design Suite (WDS) or the EZRadioPRO Register Calculator worksheet (in Microsoft
Excel) available on the product website. These methods offer a simple method to quickly determine the
correct settings based on the application requirements. The following information can be used to calcu-
lated these values manually.
23.3.2. Frequency Programming
In order to receive or transmit an RF signal, the desired channel frequency, f
, must be programmed
carrier
into the transceiver. Note that this frequency is the center frequency of the desired channel and not an LO
frequency. The carrier frequency is generated by a Fractional-N Synthesizer, using 10 MHz both as the ref-
rd
erence frequency and the clock of the (3 order) ΔΣ modulator. This modulator uses modulo 64000 accu-
mulators. This design was made to obtain the desired frequency resolution of the synthesizer. The overall
division ratio of the feedback loop consist of an integer part (N) and a fractional part (F).In a generic sense,
the output frequency of the synthesizer is as follows:
fOUT 10MHz(N F)
The fractional part (F) is determined by three different values, Carrier Frequency (fc[15:0]), Frequency Off-
set (fo[8:0]), and Frequency Deviation (fd[7:0]). Due to the fine resolution and high loop bandwidth of the
synthesizer, FSK modulation is applied inside the loop and is done by varying F according to the incoming
data; this is discussed further in “Frequency Deviation” on page 248. Also, a fixed offset can be added to
fine-tune the carrier frequency and counteract crystal tolerance errors. For simplicity assume that only the
fc[15:0] register will determine the fractional component. The equation for selection of the carrier frequency
is shown below:
Rev. 1.0
245
Si1000/1/2/3/4/5
fcarrier 10MHz(hbsel 1)(N F)
fc[15:0]
fTX 10MHz*(hbsel 1)*( fb[4:0] 24
)
64000
D7
D6
D5
D4
D3
D2
D1
D0 POR Def.
Add R/W
Function/
Description
73 R/W
74 R/W
Frequency
Offset 1
fo[7]
fo[6]
fo[5]
fo[4]
fo[3]
fo[2]
fo[1] fo[0]
fo[9] fo[8]
fb[1] fb[0]
fc[9] fc[8]
fc[1] fc[0]
00h
00h
35h
BBh
80h
Frequency
Offset 2
75 R/W Frequency Band
Select
sbsel
fc[14]
fc[6]
hbsel
fc[13]
fc[5]
fb[4]
fc[12]
fc[4]
fb[3]
fc[11]
fc[3]
fb[2]
fc[10]
fc[2]
76 R/W Nominal Carrier
Frequency 1
fc[15]
fc[7]
77 R/W Nominal Carrier
Frequency 0
The integer part (N) is determined by fb[4:0]. Additionally, the output frequency can be halved by connect-
ing a ÷2 divider to the output. This divider is not inside the loop and is controlled by the hbsel bit in "Regis-
ter 75h. Frequency Band Select". This effectively partitions the entire 240–960 MHz frequency range into
two separate bands: High Band (HB) for hbsel = 1, and Low Band (LB) for hbsel = 0. The valid range of
fb[4:0] is from 0 to 23. If a higher value is written into the register, it will default to a value of 23. The integer
part has a fixed offset of 24 added to it as shown in the formula above. Table 23.3 demonstrates the selec-
tion of fb[4:0] for the corresponding frequency band.
After selection of the fb (N) the fractional component may be solved with the following equation:
fTX
fc[15:0]
fb[4:0] 24 *64000
10MHz*(hbsel 1)
fb and fc are the actual numbers stored in the corresponding registers.
Table 23.3. Frequency Band Selection
fb[4:0] Value
N
Frequency Band
hbsel=0
hbsel=1
0
1
2
3
4
5
6
7
8
24
25
26
27
28
29
30
31
32
240–249.9 MHz
250–259.9 MHz
260–269.9 MHz
270–279.9 MHz
280–289.9 MHz
290–299.9 MHz
300–309.9 MHz
310–319.9 MHz
320–329.9 MHz
480–499.9 MHz
500–519.9 MHz
520–539.9 MHz
540–559.9 MHz
560–579.9 MHz
580–599.9 MHz
600–619.9 MHz
620–639.9 MHz
640–659.9 MHz
246
Rev. 1.0
Si1000/1/2/3/4/5
Table 23.3. Frequency Band Selection (Continued)
9
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
330–339.9 MHz
340–349.9 MHz
350–359.9 MHz
360–369.9 MHz
370–379.9 MHz
380–389.9 MHz
390–399.9 MHz
400–409.9 MHz
410–419.9 MHz
420–429.9 MHz
430–439.9 MHz
440–449.9 MHz
450–459.9 MHz
460–469.9 MHz
470–479.9 MHz
660–679.9 MHz
680–699.9 MHz
700–719.9 MHz
720–739.9 MHz
740–759.9 MHz
760–779.9 MHz
780–799.9 MHz
800–819.9 MHz
820–839.9 MHz
840–859.9 MHz
860–879.9 MHz
880–899.9 MHz
900–919.9 MHz
920–939.9 MHz
940–960 MHz
10
11
12
13
14
15
16
17
18
19
20
21
22
23
The chip will automatically shift the frequency of the Synthesizer down by 937.5 kHz (30 MHz ÷ 32) to
achieve the correct Intermediate Frequency (IF) when RX mode is entered. Low-side injection is used in
the RX Mixing architecture; therefore, no frequency reprogramming is required when using the same TX
frequency and switching between RX/TX modes.
23.3.3. Easy Frequency Programming for FHSS
While Registers 73h–77h may be used to program the carrier frequency of the transceiver, it is often easier
to think in terms of “channels” or “channel numbers” rather than an absolute frequency value in Hz. Also,
there may be some timing-critical applications (such as for Frequency Hopping Systems) in which it is
desirable to change frequency by programming a single register. Once the channel step size is set, the fre-
quency may be changed by a single register corresponding to the channel number. A nominal frequency is
first set using Registers 73h–77h, as described above. Registers 79h and 7Ah are then used to set a chan-
nel step size and channel number, relative to the nominal setting. The Frequency Hopping Step Size
(fhs[7:0]) is set in increments of 10 kHz with a maximum channel step size of 2.56 MHz. The Frequency
Hopping Channel Select Register then selects channels based on multiples of the step size.
Fcarrier Fnom fhs[7 :0]( fhch[7 :0]10kHz)
For example: if the nominal frequency is set to 900 MHz using Registers 73h–77h and the channel step
size is set to 1 MHz using "Register 7Ah. Frequency Hopping Step Size". For example, if the "Register
79h. Frequency Hopping Channel Select" is set to 5d, the resulting carrier frequency would be 905 MHz.
Once the nominal frequency and channel step size are programmed in the registers, it is only necessary to
program the fhch[7:0] register in order to change the frequency.
Rev. 1.0
247
Si1000/1/2/3/4/5
D7
D6
D5
D4
D3
D2
D1
D0
POR Def.
Add R/W
Function/
Description
79 R/W Frequency Hopping fhch[7] fhch[6] fhch[5] fhch[4] fhch[3] fhch[2] fhch[1] fhch[0]
Channel Select
00h
00h
7A R/W Frequency Hopping fhs[7]
Step Size
fhs[6]
fhs[5]
fhs[4]
fhs[3]
fhs[2]
fhs[1]
fhs[0]
23.3.4. Automatic State Transition for Frequency Change
If registers 79h or 7Ah are changed in either TX or RX mode, the state machine will automatically transition
the chip back to TUNE, change the frequency, and automatically go back to either TX or RX. This feature
is useful to reduce the number of SPI commands required in a Frequency Hopping System. This in turn
reduces microcontroller activity, reducing current consumption. The exception to this is during TX FIFO
mode. If a frequency change is initiated during a TX packet, then the part will complete the current TX
packet and will only change the frequency for subsequent packets.
23.3.5. Frequency Deviation
The peak frequency deviation is configurable from ±0.625 to ±320 kHz. The Frequency Deviation (Δf) is
controlled by the Frequency Deviation Register (fd), address 71 and 72h, and is independent of the carrier
frequency setting. When enabled, regardless of the setting of the hbsel bit (high band or low band), the
resolution of the frequency deviation will remain in increments of 625 Hz. When using frequency modula-
tion the carrier frequency will deviate from the nominal center channel carrier frequency by ±Δf:
f fd[8:0]625Hz
f
fd[8 : 0]
f = peak deviation
625Hz
f
fcarrier
Time
Figure 23.4. Frequency Deviation
The previous equation should be used to calculate the desired frequency deviation. If desired, frequency
modulation may also be disabled in order to obtain an unmodulated carrier signal at the channel center fre-
quency; see “Modulation Type” on page 251 for further details.
248
Rev. 1.0
Si1000/1/2/3/4/5
D7
D6
D5
D4
D3
D2
D1
D0
POR Def.
Add R/W
Function/
Description
71 R/W Modulation Mode trclk[1] trclk[0] dtmod[1] dtmod[0] eninv fd[8] modtyp[1] modtyp[0]
Control 2
00h
20h
72 R/W Frequency Devia- fd[7]
tion
fd[6]
fd[5]
fd[4]
fd[3] fd[2]
fd[1]
fd[0]
23.3.6. Frequency Offset Adjustment
When the AFC is disabled the frequency offset can be adjusted manually by fo[9:0] in registers 73h and
74h. It is not possible to have both AFC and offset as internally they share the same register. The fre-
quency offset adjustment and the AFC both are implemented by shifting the Synthesizer Local Oscillator
frequency. This register is a signed register so in order to get a negative offset it is necessary to take the
twos complement of the positive offset number. The offset can be calculated by the following:
DesiredOffset 156.25Hz(hbsel 1) fo[9:0]
DesiredOffset
fo[9:0]
156.25Hz(hbsel 1)
The adjustment range in high band is ±160 kHz and in low band it is ±80 kHz. For example to compute an
offset of +50 kHz in high band mode fo[9:0] should be set to 0A0h. For an offset of –50 kHz in high band
mode the fo[9:0] register should be set to 360h.
D7
D6
D5
D4
D3
D2
D1
D0
POR
Def.
Add R/W
Function/
Description
73 R/W Frequency Offset
74 R/W Frequency Offset
fo[7]
fo[6]
fo[5]
fo[4]
fo[3]
fo[2]
fo[1] fo[0]
fo[9] fo[8]
00h
00h
23.3.7. Automatic Frequency Control (AFC)
All AFC settings can be easily obtained from the settings calculator. This is the recommended method to
program all AFC settings. This section is intended to describe the operation of the AFC in more detail to
help understand the trade-offs of using AFC.The receiver supports automatic frequency control (AFC) to
compensate for frequency differences between the transmitter and receiver reference frequencies. These
differences can be caused by the absolute accuracy and temperature dependencies of the reference crys-
tals. Due to frequency offset compensation in the modem, the receiver is tolerant to frequency offsets up to
0.25 times the IF bandwidth when the AFC is disabled. When the AFC is enabled, the received signal will
be centered in the pass-band of the IF filter, providing optimal sensitivity and selectivity over a wider range
of frequency offsets up to 0.35 times the IF bandwidth. The trade-off of receiver sensitivity (at 1% PER)
versus carrier offset and the impact of AFC are illustrated in Figure 23.5.
Rev. 1.0
249
Si1000/1/2/3/4/5
Figure 23.5. Sensitivity at 1% PER vs. Carrier Frequency Offset
When AFC is enabled, the preamble length needs to be long enough to settle the AFC. In general, one
byte of preamble is sufficient to settle the AFC. Disabling the AFC allows the preamble to be shortened
from 40 bits to 32 bits. Note that with the AFC disabled, the preamble length must still be long enough to
settle the receiver and to detect the preamble (see “Preamble Length” on page 266). The AFC corrects the
detected frequency offset by changing the frequency of the Fractional-N PLL. When the preamble is
detected, the AFC will freeze for the remainder of the packet. In multi-packet mode the AFC is reset at the
end of every packet and will re-acquire the frequency offset for the next packet. The AFC loop includes a
bandwidth limiting mechanism improving the rejection of out of band signals. When the AFC loop is
enabled, its pull-in-range is determined by the bandwidth limiter value (AFCLimiter) which is located in reg-
ister 2Ah.
AFC_pull_in_range = ±AFCLimiter[7:0] x (hbsel+1) x 625 Hz
The AFC Limiter register is an unsigned register and its value can be obtained from the EZRadioPRO Reg-
ister Calculator spreadsheet.
The amount of error correction feedback to the Fractional-N PLL before the preamble is detected is con-
trolled from afcgearh[2:0]. The default value 000 relates to a feedback of 100% from the measured fre-
quency error and is advised for most applications. Every bit added will half the feedback but will require a
longer preamble to settle.
The AFC operates as follows. The frequency error of the incoming signal is measured over a period of two
bit times, after which it corrects the local oscillator via the Fractional-N PLL. After this correction, some time
is allowed to settle the Fractional-N PLL to the new frequency before the next frequency error is measured.
The duration of the AFC cycle before the preamble is detected can be programmed with shwait[2:0]. It is
advised to use the default value 001, which sets the AFC cycle to 4 bit times (2 for measurement and 2 for
settling). If shwait[2:0] is programmed to 3'b000, there is no AFC correction output. It is advised to use the
default value 001, which sets the AFC cycle to 4 bit times (2 for measurement and 2 for settling).
The AFC correction value may be read from register 2Bh. The value read can be converted to kHz with the
following formula:
AFC Correction = 156.25Hz x (hbsel +1) x afc_corr[7: 0]
250
Rev. 1.0
Si1000/1/2/3/4/5
Frequency Correction
RX TX
Freq Offset Register Freq Offset Register
AFC Freq Offset Register
AFC disabled
AFC enabled
23.3.8. TX Data Rate Generator
The data rate is configurable between 0.123–256 kbps. For data rates below 30 kbps the ”txdtrtscale” bit in
register 70h should be set to 1. When higher data rates are used this bit should be set to 0.
The TX date rate is determined by the following formula in bps:
txdr15:0 1 MHz
DR_TX (bps) = -------------------------------------------------
216 + 5 txdtrtscale
DR_TX(bps) 216 + 5 txdtrtscale
txdr[15:0] = --------------------------------------------------------------------------------
1 MHz
For data rates higher than 100 kbps, Register 58h should be changed from its default of 80h to C0h. Non-
optimal modulation and increased eye closure will result if this setting is not made for data rates higher
than 100 kbps. The txdr register is only applicable to TX mode and does not need to be programmed for
RX mode. The RX bandwidth which is partly determined from the data rate is programmed separately.
D7
D6
D5
D4
D3
D2
D1
D0
POR Def.
Add R/W
Function/
Description
6E R/W TX Data Rate 1 txdr[15] txdr[14] txdr[13] txdr[12] txdr[11] txdr[10] txdr[9] txdr[8]
0Ah
3Dh
6F R/W TX Data Rate 0 txdr[7]
txdr[6] txdr[5] txdr[4] txdr[3]
txdr[2] txdr[1] txdr[0]
23.4. Modulation Options
23.4.1. Modulation Type
The EZRadioPRO transceivers support three different modulation options: Gaussian Frequency Shift Key-
ing (GFSK), Frequency Shift Keying (FSK), and On-Off Keying (OOK). GFSK is the recommended modu-
lation type as it provides the best performance and cleanest modulation spectrum. Figure 23.6
demonstrates the difference between FSK and GFSK for a Data Rate of 64 kbps. The time domain plots
demonstrate the effects of the Gaussian filtering. The frequency domain plots demonstrate the spectral
benefit of GFSK over FSK. The type of modulation is selected with the modtyp[1:0] bits in "Register 71h.
Modulation Mode Control 2". Note that it is also possible to obtain an unmodulated carrier signal by setting
modtyp[1:0] = 00.
modtyp[1:0]
Modulation Source
00
01
10
11
Unmodulated Carrier
OOK
FSK
GFSK (enable TX Data CLK when direct mode is used)
Rev. 1.0
251
Si1000/1/2/3/4/5
TX Modulation Time Domain Waveforms -- FSK vs. GFSK
1.5
TX Modulation Spectrum -- FSK vs GFSK (Continuous PRBS)
-20
1.0
0.5
-40
-60
-80
0.0
-0.5
-1.0
-100
-20
-1.5
1.0
-40
-60
0.5
0.0
-80
-0.5
-1.0
-100
-250 -200 -150 -100
-50
0
50
100
150
200
250
0
50
100 150 200 250 300 350 400 450 500
time, usec
freq, KHz
DataRate
64000.0
TxDev
BT_Filter
0.5
ModIndex
1.0
32000.0
Figure 23.6. FSK vs. GFSK Spectrums
23.4.2. Modulation Data Source
The transceiver may be configured to obtain its modulation data from one of three different sources: FIFO
mode, Direct Mode, and from a PN9 mode. In Direct Mode, the TX modulation data may be obtained from
several different input pins. These options are set through the dtmod[1:0] field in "Register 71h. Modulation
Mode Control 2".
D7
D6
D5
D4
D3
D2
D1
D0
POR Def.
Add R/W
Function/
Description
71 R/W
Modulation
Mode
trclk[1] trclk[0] dtmod[1] dtmod[0] eninv fd[8] modtyp[1] modtyp[0]
00h
Control 2
dtmod[1:0]
Data Source
00
01
10
11
Direct Mode using TX/RX Data via GPIO pin (GPIO configuration required)
Direct Mode using TX/RX Data via SDI pin (only when nSEL is high)
FIFO Mode
PN9 (internally generated)
23.4.2.1. FIFO Mode
In FIFO mode, the transmit and receive data is stored in integrated FIFO register memory. The FIFOs are
accessed via "Register 7Fh. FIFO Access," and are most efficiently accessed with burst read/write opera-
tion.
In TX mode, the data bytes stored in FIFO memory are "packaged" together with other fields and bytes of
information to construct the final transmit packet structure. These other potential fields include the Pream-
ble, Sync word, Header, CRC checksum, etc. The configuration of the packet structure in TX mode is
252
Rev. 1.0
Si1000/1/2/3/4/5
determined by the Automatic Packet Handler (if enabled), in conjunction with a variety of Packet Handler
Registers (see Table 23.4 on page 265). If the Automatic Packet Handler is disabled, the entire desired
packet structure should be loaded into FIFO memory; no other fields (such as Preamble or Sync word are
automatically added to the bytes stored in FIFO memory). For further information on the configuration of
the FIFOs for a specific application or packet size, see “Data Handling and Packet Handler” on page 261.
In RX mode, only the bytes of the received packet structure that are considered to be "data bytes" are
stored in FIFO memory. Which bytes of the received packet are considered "data bytes" is determined by
the Automatic Packet Handler (if enabled), in conjunction with the Packet Handler Registers (see
Table 23.4 on page 265). If the Automatic Packet Handler is disabled, all bytes following the Sync word are
considered data bytes and are stored in FIFO memory. Thus, even if Automatic Packet Handling operation
is not desired, the preamble detection threshold and Sync word still need to be programmed so that the RX
Modem knows when to start filling data into the FIFO. When the FIFO is being used in RX mode, all of the
received data may still be observed directly (in real-time) by properly programming a GPIO pin as the
RXDATA output pin; this can be quite useful during application development.
When in FIFO mode, the chip will automatically exit the TX or RX State when either the ipksent or ipkvalid
interrupt occurs. The chip will return to the IDLE mode state programmed in "Register 07h. Operating
Mode and Function Control 1". For example, the chip may be placed into TX mode by setting the txon bit,
but with the pllon bit additionally set. The chip will transmit all of the contents of the FIFO and the ipksent
interrupt will occur. When this interrupt event occurs, the chip will clear the txon bit and return to TUNE
mode, as indicated by the set state of the pllon bit. If no other bits are additionally set in register 07h
(besides txon initially), then the chip will return to the STANDBY state.
In RX mode, the rxon bit will be cleared if ipkvalid occurs and the rxmpk bit (RX Multi-Packet bit, SPI Reg-
ister 08h bit [4]) is not set. When the rxmpk bit is set, the part will not exit the RX state after successfully
receiving a packet, but will remain in RX mode. The microcontroller will need to decide on the appropriate
subsequent action, depending upon information such as an interrupt generated by CRC, packet valid, or
preamble detect.
23.4.2.2. Direct Mode
For legacy systems that perform packet handling within an MCU or other baseband chip, it may not be
desirable to use the FIFO. For this scenario, a Direct Mode is provided which bypasses the FIFOs entirely.
In TX direct mode, the TX modulation data is applied to an input pin of the chip and processed in "real
time" (i.e., not stored in a register for transmission at a later time). A variety of pins may be configured for
use as the TX Data input function.
Furthermore, an additional pin may be required for a TX Clock output function if GFSK modulation is
desired (only the TX Data input pin is required for FSK). Two options for the source of the TX Data are
available in the dtmod[1:0] field, and various configurations for the source of the TX Data Clock may be
selected through the trclk[1:0] field.
trclk[1:0]
TX/RX Data Clock Configuration
No TX Clock (only for FSK)
00
01
10
11
TX/RX Data Clock is available via GPIO (GPIO needs programming accordingly as well)
TX/RX Data Clock is available via SDO pin (only when nSEL is high)
TX/RX Data Clock is available via the nIRQ pin
The eninv bit in SPI Register 71h will invert the TX Data; this is most likely useful for diagnostic and testing
purposes.
In RX direct mode, the RX Data and RX Clock can be programmed for direct (real-time) output to GPIO
pins. The microcontroller may then process the RX data without using the FIFO or packet handler functions
Rev. 1.0
253
Si1000/1/2/3/4/5
of the RFIC. In RX direct mode, the chip must still acquire bit timing during the Preamble, and thus the pre-
amble detection threshold (SPI Register 35h) must still be programmed. Once the preamble is detected,
certain bit timing functions within the RX Modem change their operation for optimized performance over
the remainder of the packet. It is not required that a Sync word be present in the packet in RX Direct mode;
however, if the Sync word is absent then the skipsyn bit in SPI Register 33h must be set, or else the bit tim-
ing and tracking function within the RX Modem will not be configured for optimum performance.
23.4.2.3. Direct Synchronous Mode
In TX direct mode, the chip may be configured for synchronous or asynchronous modes of modulation. In
direct synchronous mode, the RFIC is configured to provide a TX Clock signal as an output to the external
device that is providing the TX Data stream. This TX Clock signal is a square wave with a frequency equal
to the programmed data rate. The external modulation source (e.g., MCU) must accept this TX Clock sig-
nal as an input and respond by providing one bit of TX Data back to the RFIC, synchronous with one edge
of the TX Clock signal. In this fashion, the rate of the TX Data input stream from the external source is con-
trolled by the programmed data rate of the RFIC; no TX Data bits are made available at the input of the
RFIC until requested by another cycle of the TX Clock signal. The TX Data bits supplied by the external
source are transmitted directly in real-time (i.e., not stored internally for later transmission).
All modulation types (FSK/GFSK/OOK) are valid in TX direct synchronous mode. As will be discussed in
the next section, there are limits on modulation types in TX direct asynchronous mode.
23.4.2.4. Direct Asynchronous Mode
In TX direct asynchronous mode, the RFIC no longer controls the data rate of the TX Data input stream.
Instead, the data rate is controlled only by the external TX Data source; the RFIC simply accepts the data
applied to its TX Data input pin, at whatever rate it is supplied. This means that there is no longer a need
for a TX Clock output signal from the RFIC, as there is no synchronous "handshaking" between the RFIC
and the external data source. The TX Data bits supplied by the external source are transmitted directly in
real-time (i.e., not stored internally for later transmission).
It is not necessary to program the data rate parameter when operating in TX direct asynchronous mode.
The chip still internally samples the incoming TX Data stream to determine when edge transitions occur;
however, rather than sampling the data at a pre-programmed data rate, the chip now internally samples
the incoming TX Data stream at its maximum possible oversampling rate. This allows the chip to accu-
rately determine the timing of the bit edge transitions without prior knowledge of the data rate. (Of course,
it is still necessary to program the desired peak frequency deviation.)
Only FSK and OOK modulation types are valid in TX Direct Asynchronous Mode; GFSK modulation is not
available in asynchronous mode. This is because the RFIC does not have knowledge of the supplied data
rate, and thus cannot determine the appropriate Gaussian lowpass filter function to apply to the incoming
data.
254
Rev. 1.0
Si1000/1/2/3/4/5
VDD_DIG
Px.x
VDD_RF
TX
Direct synchronous modulation. Full
control over the serial interface & using
interrupt. Bitrate clock and modulation
via GPIO’s.
RXp
RXn
NC
Px.x
Matching
GPIO configuration
GP1 : TX DATA clock output
GP2 : TX DATA input
DataCLK
MOD(Data)
Figure 23.7. Direct Synchronous Mode Example
Direct asynchronous FSK modulation.
Modulation data via GPIO2, no data
clock needed in this mode.
VDD_DIG
Px.x
VDD_RF
TX
RXp
RXn
NC
Matching
GPIO configuration
GP2 : TX DATA input
MOD(Data)
Figure 23.8. Direct Asynchronous Mode Example
23.4.2.5. Direct Mode using SPI or nIRQ Pins
It is possible to use the EZRadioPRO Serial Interface signals and nIRQ as the modulation clock and data.
The MISO signal can be configured to be the data clock by programming trclk = 10. If the NSS signal is
LOW then the function of the MISO signal will be SPI data output. If the NSS signal is high and trclk[1:0] is
10 then during RX and TX modes the data clock will be available on the MISO signal. If trclk[1:0] is set to
11 and no interrupts are enabled in registers 05 or 06h, then the nIRQ pin can also be used as the TX/RX
data clock.
Note: The MISO and NSS signals are internal connections. The nIRQ signal is accessed through an
external package pin.
The MOSI signal can be configured to be the data source in both RX and TX modes if dtmod[1:0] = 01. In
a similar fashion, if NSS is LOW the MOSI signal will function as SPI data-in. If NSS is HIGH then in TX
Rev. 1.0
255
Si1000/1/2/3/4/5
mode it will be the data to be modulated and transmitted. In RX mode it will be the received demodulated
data. Figure 23.9 demonstrates using MOSI and MISO as the TX/RX data and clock:
TX on
command
TX off
command
RX on
command
RXoff
command
TX mode
RX mode
NSS
SPI input
don’t care
don’t care
SPI input
MOD input
SPI input
don’t care
don’t care
SPI input
Data output
SPI input
MOSI
MSIO
Data CLK
Output
Data CLK
Output
SPI output
SPI output
SPI output
SPI output
SPI output
Figure 23.9. Microcontroller Connections
If the MISO pin is not used for data clock then it may be programmed to be the interrupt function (nIRQ) by
programming Reg 0Eh bit 3.
23.4.3. PN9 Mode
In this mode the TX Data is generated internally using a pseudorandom (PN9 sequence) bit generator. The
primary purpose of this mode is for use as a test mode to observe the modulated spectrum without having
to provide data.
23.5. Internal Functional Blocks
This section provides an overview some of the key blocks of the internal radio architecture.
23.5.1. RX LNA
Depending on the part, the input frequency range for the LNA is between 240–960 MHz. The LNA provides
gain with a noise figure low enough to suppress the noise of the following stages. The LNA has one step of
gain control which is controlled by the analog gain control (AGC) algorithm. The AGC algorithm adjusts the
gain of the LNA and PGA so the receiver can handle signal levels from sensitivity to +5 dBm with optimal
performance.
In the Si1002/3, the TX and RX may be tied directly. See the TX/RX direct-tie reference design available
on www.silabs.com. When the direct tie is used the lna_sw bit in Register 6Dh, TX Power must be set.
23.5.2. RX I-Q Mixer
The output of the LNA is fed internally to the input of the receive mixer. The receive mixer is implemented
as an I-Q mixer that provides both I and Q channel outputs to the programmable gain amplifier. The mixer
consists of two double-balanced mixers whose RF inputs are driven in parallel, local oscillator (LO) inputs
are driven in quadrature, and separate I and Q Intermediate Frequency (IF) outputs drive the programma-
ble gain amplifier. The receive LO signal is supplied by an integrated VCO and PLL synthesizer operating
between 240–960 MHz. The necessary quadrature LO signals are derived from the divider at the VCO out-
put.
23.5.3. Programmable Gain Amplifier
The programmable gain amplifier (PGA) provides the necessary gain to boost the signal level into the
dynamic range of the ADC. The PGA must also have enough gain switching to allow for large input signals
to ensure a linear RSSI range up to –20 dBm. The PGA has steps of 3 dB which are controlled by the AGC
algorithm in the digital modem.
256
Rev. 1.0
Si1000/1/2/3/4/5
23.5.4. ADC
The amplified IQ IF signals are digitized using an Analog-to-Digital Converter (ADC), which allows for low
current consumption and high dynamic range. The bandpass response of the ADC provides exceptional
rejection of out of band blockers.
23.5.5. Digital Modem
Using high-performance ADCs allows channel filtering, image rejection, and demodulation to be performed
in the digital domain, resulting in reduced area while increasing flexibility. The digital modem performs the
following functions:
Channel selection filter
TX modulation
RX demodulation
AGC
Preamble detector
Invalid preamble detector
Radio signal strength indicator (RSSI)
Automatic frequency compensation (AFC)
®
Packet handling including EZMAC features
Cyclic redundancy check (CRC)
The digital channel filter and demodulator are optimized for ultra low power consumption and are highly
configurable. Supported modulation types are GFSK, FSK, and OOK. The channel filter can be configured
to support bandwidths ranging from 620 kHz down to 2.6 kHz. A large variety of data rates are supported
ranging from 0.123 up to 256 kbps. The AGC algorithm is implemented digitally using an advanced control
loop optimized for fast response time.
The configurable preamble detector is used to improve the reliability of the sync-word detection. The sync-
word detector is only enabled when a valid preamble is detected, significantly reducing the probability of
false detection.
The received signal strength indicator (RSSI) provides a measure of the signal strength received on the
tuned channel. The resolution of the RSSI is 0.5 dB. This high resolution RSSI enables accurate channel
power measurements for clear channel assessment (CCA), carrier sense (CS), and listen before talk (LBT)
functionality.
Frequency mistuning caused by crystal inaccuracies can be compensated by enabling the digital auto-
matic frequency control (AFC) in receive mode.
A comprehensive programmable packet handler including key features of Silicon Labs’ EZMAC is inte-
grated to create a variety of communication topologies ranging from peer-to-peer networks to mesh net-
works. The extensive programmability of the packet header allows for advanced packet filtering which in
turn enables a mix of broadcast, group, and point-to-point communication.
A wireless communication channel can be corrupted by noise and interference, and it is therefore impor-
tant to know if the received data is free of errors. A cyclic redundancy check (CRC) is used to detect the
presence of erroneous bits in each packet. A CRC is computed and appended at the end of each transmit-
ted packet and verified by the receiver to confirm that no errors have occurred. The packet handler and
CRC can significantly reduce the load on the microcontroller reducing the overall current consumption.
The digital modem includes the TX modulator which converts the TX data bits into the corresponding
stream of digital modulation values to be summed with the fractional input to the sigma-delta modulator.
This modulation approach results in highly accurate resolution of the frequency deviation. A Gaussian filter
is implemented to support GFSK, considerably reducing the energy in the adjacent channels. The default
bandwidth-time product (BT) is 0.5 for all programmed data rates, but it may be adjusted to other values.
Rev. 1.0
257
Si1000/1/2/3/4/5
23.5.6. Synthesizer
An integrated Sigma Delta (ΣΔ) Fractional-N PLL synthesizer capable of operating from 240–960 MHz is
provided on-chip. Using a ΣΔ synthesizer has many advantages; it provides flexibility in choosing data
rate, deviation, channel frequency, and channel spacing. The transmit modulation is applied directly to the
loop in the digital domain through the fractional divider which results in very precise accuracy and control
over the transmit deviation.
Depending on the part, the PLL and - modulator scheme is designed to support any desired frequency
and channel spacing in the range from 240–960 MHz with a frequency resolution of 156.25 Hz (Low band)
or 312.5 Hz (High band). The transmit data rate can be programmed between 0.123–256 kbps, and the
frequency deviation can be programmed between ±1–320 kHz. These parameters may be adjusted via
registers as shown in “Frequency Control” on page 245.
TX
Selectable
Divider
Fref = 10 M
PFD
CP
LPF
RX
VCO
N
TX
Modulation
Delta-
Sigma
Figure 23.10. PLL Synthesizer Block Diagram
The reference frequency to the PLL is 10 MHz. The PLL utilizes a differential L-C VCO, with integrated on-
chip inductors. The output of the VCO is followed by a configurable divider which will divide down the sig-
nal to the desired output frequency band. The modulus of the variable divide-by-N divider stage is con-
trolled dynamically by the output from the - modulator. The tuning resolution is sufficient to tune to the
commanded frequency with a maximum accuracy of 312.5 Hz anywhere in the range between 240–
960 MHz.
23.5.6.1. VCO
The output of the VCO is automatically divided down to the correct output frequency depending on the
hbsel and fb[4:0] fields in "Register 75h. Frequency Band Select". In receive mode, the LO frequency is
automatically shifted downwards by the IF frequency of 937.5 kHz, allowing transmit and receive operation
on the same frequency. The VCO integrates the resonator inductor and tuning varactor, so no external
VCO components are required.
The VCO uses a capacitance bank to cover the wide frequency range specified. The capacitance bank will
automatically be calibrated every time the synthesizer is enabled. In certain fast hopping applications this
might not be desirable so the VCO calibration may be skipped by setting the appropriate register.
258
Rev. 1.0
Si1000/1/2/3/4/5
23.5.7. Power Amplifier
The Si1000/1 contains an internal integrated power amplifier (PA) capable of transmitting at output levels
between +1 and +20 dBm. The Si1002/3/4/5 contains a PA which is capable of transmitting output levels
between –8 to +13 dBm. The PA design is single-ended and is implemented as a two stage class CE
amplifier with a high efficiency when transmitting at maximum power. The PA efficiency can only be opti-
mized at one power level. Changing the output power by adjusting txpow[2:0] will scale both the output
power and current but the efficiency will not remain constant. The PA output is ramped up and down to pre-
vent unwanted spectral splatter.
In the Si1002/3 the TX and RX may be tied directly. See the TX/RX direct-tie reference design available on
the Silicon Labs website for more details. When the direct tie is used the lna_sw bit in Register 6Dh, TX
Power must be set to 1.
23.5.7.1. Output Power Selection
The output power is configurable in 3 dB steps with the txpow[2:0] field in "Register 6Dh. TX Power". Extra
output power can allow the use of a cheaper smaller antenna, greatly reducing the overall BOM cost. The
higher power setting of the chip achieves maximum possible range, but of course comes at the cost of
higher TX current consumption. However, depending on the duty cycle of the system, the effect on battery
life may be insignificant. Contact Silicon Labs Support for help in evaluating this tradeoff.
D7
D6
D5
D4
D3
D2
D1
D0
POR
Def.
Add R/W Function/
Description
6D R/W
TX Power
reserved reserved reserved reserved lna_sw txpow[2] txpow[1] txpow[0] 18h
txpow[2:0]
000
Si10x0/1 Output Power
+1 dBm
001
+2 dBm
010
+5 dBm
011
+8 dBm
100
+11 dBm
101
+14 dBm
110
+17 dBm
111
+20 dBm
txpow[2:0]
Si10x2/3/4/5 Output
Power
000
001
010
011
100
101
110
111
–8 dBm
–5 dBm
–2 dBm
+1 dBm
+4 dBm
+7 dBm
+10 dBm
+13 dBm
Rev. 1.0
259
Si1000/1/2/3/4/5
23.5.8. Crystal Oscillator
The transceiver includes an integrated 30 MHz crystal oscillator with a fast start-up time of less than
600 µs when a suitable parallel resonant crystal is used. The design is differential with the required crystal
load capacitance integrated on-chip to minimize the number of external components. By default, all that is
required off-chip is the 30 MHz crystal.
The crystal load capacitance can be digitally programmed to accommodate crystals with various load
capacitance requirements and to adjust the frequency of the crystal oscillator. The tuning of the crystal load
capacitance is programmed through the xlc[6:0] field of "Register 09h. 30 MHz Crystal Oscillator Load
Capacitance". The total internal capacitance is 12.5 pF and is adjustable in approximately 127 steps
(97fF/step). The xtalshift bit provides a coarse shift in frequency but is not binary with xlc[6:0].
The crystal frequency adjustment can be used to compensate for crystal production tolerances. Utilizing
the on-chip temperature sensor and suitable control software, the temperature dependency of the crystal
can be canceled.
The typical value of the total on-chip capacitance Cint can be calculated as follows:
Cint = 1.8 pF + 0.085 pF x xlc[6:0] + 3.7 pF x xtalshift
Note that the coarse shift bit xtalshift is not binary with xlc[6:0]. The total load capacitance Cload seen by
the crystal can be calculated by adding the sum of all external parasitic PCB capacitances Cext to Cint. If
the maximum value of Cint (16.3 pF) is not sufficient, an external capacitor can be added for exact tuning.
Additional information on calculating Cext and crystal selection guidelines is provided in “AN417: Si4x3x
Family Crystal Oscillator.”
If AFC is disabled then the synthesizer frequency may be further adjusted by programming the Frequency
Offset field fo[9:0]in "Register 73h. Frequency Offset 1" and "Register 74h. Frequency Offset 2", as dis-
cussed in “Frequency Control” on page 245.
The crystal oscillator frequency is divided down internally and may be output to the microcontroller through
one of the GPIO pins for use as the System Clock. In this fashion, only one crystal oscillator is required for
the entire system and the BOM cost is reduced. The available clock frequencies and GPIO configuration
are discussed further in “Output Clock” on page 270.
The transceiver may also be driven with an external 30 MHz clock signal through the XOUT pin. When
driving with an external reference or using a TCXO, the XTAL load capacitance register should be set to 0.
D7
D6
D5
D4
D3
D2
D1
D0
POR
Def.
Add R/W Function/Description
09 R/W Crystal Oscillator Load
Capacitance
xtalshift xlc[6]
xlc[5]
xlc[4]
xlc[3]
xlc[2]
xlc[1] xlc[0]
7Fh
23.5.9. Regulators
There are a total of six regulators integrated onto the transceiver. With the exception of the digital regulator,
all regulators are designed to operate with only internal decoupling. The digital regulator requires an exter-
nal 1 µF decoupling capacitor. All regulators are designed to operate with an input supply voltage from
+1.8 to +3.6 V. The output stage of the of PA is not connected internally to a regulator and is connected
directly to the battery voltage.
A supply voltage should only be connected to the VDD pins. No voltage should be forced on the digital reg-
ulator output.
260
Rev. 1.0
Si1000/1/2/3/4/5
23.6. Data Handling and Packet Handler
The internal modem is designed to operate with a packet including a 010101... preamble structure. To con-
figure the modem to operate with packet formats without a preamble or other legacy packet structures con-
tact customer support.
23.6.1. RX and TX FIFOs
Two 64 byte FIFOs are integrated into the chip, one for RX and one for TX, as shown in Figure 23.11.
"Register 7Fh. FIFO Access" is used to access both FIFOs. A burst write to address 7Fh will write data to
the TX FIFO. A burst read from address 7Fh will read data from the RX FIFO.
TX FIFO
RX FIFO
RX FIFO Almost Full
Threshold
TX FIFO Almost Full
Threshold
TX FIFO Almost Empty
Threshold
Figure 23.11. FIFO Thresholds
The TX FIFO has two programmable thresholds. An interrupt event occurs when the data in the TX FIFO
reaches these thresholds. The first threshold is the FIFO almost full threshold, txafthr[5:0]. The value in this
register corresponds to the desired threshold value in number of bytes. When the data being filled into the
TX FIFO crosses this threshold limit, an interrupt to the microcontroller is generated so the chip can enter
TX mode to transmit the contents of the TX FIFO. The second threshold for TX is the FIFO almost empty
threshold, txaethr[5:0]. When the data being shifted out of the TX FIFO drops below the almost empty
threshold an interrupt will be generated. If more data is not loaded into the FIFO then the chip
automatically exits the TX State after the ipksent interrupt occurs. The chip will return to the mode selected
by the remaining bits in SPI Register 07h. For example, the chip may be placed into TX mode by setting
the txon bit, but with the xton bit additionally set. For this condition, the chip will transmit all of the contents
of the FIFO and the ipksent interrupt will occur. When this interrupt event occurs, the chip will clear the txon
bit and return to READY mode, as indicated by the set state of the xton bit. If the pllon bit D1 is set when
entering TX mode (i.e., SPI Register 07h = 0Ah), the chip will exit from TX mode after sending the packet
and return to TUNE mode.
However, the chip will not automatically return to STANDBY mode upon exit from the TX state, in the event
the TX packet is initiated by setting SPI Register 07h = 08h (i.e., setting only txon bit D3). The chip will
instead return to READY mode, with the crystal oscillator remaining enabled. This is intentional; the sys-
tem may be configured such that the host MCU derives its clock from the MCU_CLK output of the RFIC
(through GPIO2), and this clock signal must not be shut down without allowing the host MCU time to pro-
cess any interrupt signals that may have occurred. The host MCU must subsequently perform a WRITE to
SPI Register 07h = 00h to enter STANDBY mode and obtain minimum current consumption.
Rev. 1.0
261
Si1000/1/2/3/4/5
D7
D6
D5
D4
D3
D2
D1
D0
POR
Def.
Add R/W Function/
Description
08 R/W Operating &
Function
antdiv[2] antdiv[1] antdiv[0]
rxmpk
autotx
enldm
ffclrrx
ffclrtx
00h
Control 2
7C R/W
7D R/W
TX FIFO
Control 1
Reserved Reserved txafthr[5] txafthr[4] txafthr[3] txafthr[2] txafthr[1] txafthr[0] 37h
Reserved Reserved txaethr[5] txaethr[4] txaethr[3] txaethr[2] txaethr[1] txaethr[0] 04h
TX FIFO
Control 2
The RX FIFO has one programmable threshold called the FIFO Almost Full Threshold, rxafthr[5:0]. When
the incoming RX data crosses the Almost Full Threshold an interrupt will be generated to the microcon-
troller via the nIRQ pin. The microcontroller will then need to read the data from the RX FIFO.
D7
D6
D5
D4
D3
D2
D1
D0
POR
Def.
Add R/W Function/
Description
7E R/W
RX FIFO
Control
Reserved Reserved rxafthr[5] rxafthr[4] rxafthr[3] rxafthr[2] rxafthr[1] rxafthr[0] 37h
Both the TX and RX FIFOs may be cleared or reset with the ffclrtx and ffclrrx bits. All interrupts may be
enabled by setting the Interrupt Enabled bits in "Register 05h. Interrupt Enable 1" and “Register 06h. Inter-
rupt Enable 2.” If the interrupts are not enabled the function will not generate an interrupt on the nIRQ pin
but the bits will still be read correctly in the Interrupt Status registers.
23.6.2. Packet Configuration
When using the FIFOs, automatic packet handling may be enabled for TX mode, RX mode, or both. "Reg-
ister 30h. Data Access Control" through “Register 4Bh. Received Packet Length” control the configuration,
status, and decoded RX packet data for Packet Handling. The usual fields for network communication
(such as preamble, synchronization word, headers, packet length, and CRC) can be configured to be auto-
matically added to the data payload. The fields needed for packet generation normally change infrequently
and can therefore be stored in registers. Automatically adding these fields to the data payload greatly
reduces the amount of communication between the microcontroller and the transceiver.
The general packet structure is shown in Figure 23.12. The length of each field is shown below the field.
The preamble pattern is always a series of alternating ones and zeroes, starting with a zero. All the fields
have programmable lengths to accommodate different applications. The most common CRC polynominals
are available for selection.
Data
CRC
Preamble
1-255 Bytes
1-4 Bytes
0 or 2
Bytes
Figure 23.12. Packet Structure
An overview of the packet handler configuration registers is shown in Table 23.4.
262
Rev. 1.0
Si1000/1/2/3/4/5
23.6.3. Packet Handler TX Mode
If the TX packet length is set the packet handler will send the number of bytes in the packet length field
before returning to IDLE mode and asserting the packet sent interrupt. To resume sending data from the
FIFO the microcontroller needs to command the chip to re-enter TX mode. Figure 23.13 provides an exam-
ple transaction where the packet length is set to three bytes.
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 8
Data 9
This will be sent in the first transmission
}
}
}
This will be sent in the second transmission
This will be sent in the third transmission
Figure 23.13. Multiple Packets in TX Packet Handler
23.6.4. Packet Handler RX Mode
23.6.4.1. Packet Handler Disabled
When the packet handler is disabled certain fields in the received packet are still required. Proper modem
operation requires preamble and sync when the FIFO is being used, as shown in Figure 23.14. Bits after
sync will be treated as raw data with no qualification. This mode allows for the creation of a custom packet
handler when the automatic qualification parameters are not sufficient. Manchester encoding is supported
but data whitening, CRC, and header checks are not.
Preamble
SYNC
DATA
Figure 23.14. Required RX Packet Structure with Packet Handler Disabled
23.6.4.2. Packet Handler Enabled
When the packet handler is enabled, all the fields of the packet structure need to be configured. Register
contents are used to construct the header field and length information encoded into the transmitted packet
when transmitting. The receive FIFO can be configured to handle packets of fixed or variable length with or
without a header. If multiple packets are desired to be stored in the FIFO, then there are options available
for the different fields that will be stored into the FIFO. Figure 23.15 demonstrates the options and settings
available when multiple packets are enabled. Figure 23.16 demonstrates the operation of fixed packet
length and correct/incorrect packets.
Rev. 1.0
263
Si1000/1/2/3/4/5
RX FIFO Contents:
Transmission:
rx_multi_pk_en = 0
rx_multi_pk_en = 1
Register
Data
txhdlen = 0
fixpklen
txhdlen > 0
fixpklen
Header(s)
Length
Register
Data
0
1
0
1
Data
H
H
FIFO
L
L
Data
Data
Data
Data
Data
Figure 23.15. Multiple Packets in RX Packet Handler
Initial state
PK 1 OK
PK 2 OK
PK 3
PK 4 OK
ERROR
RX FIFO Addr.
RX FIFO Addr.
0
RX FIFO Addr.
RX FIFO Addr.
RX FIFO Addr.
Write
Pointer
0
0
0
0
H
H
H
H
L
L
L
L
Data
Data
Data
Data
Write
Pointer
H
L
H
L
H
L
Data
Data
Data
Write
Pointer
Write
Pointer
H
L
H
L
Data
Write
Pointer
Data
CRC
error
63
63
63
63
63
Figure 23.16. Multiple Packets in RX with CRC or Header Error
264
Rev. 1.0
Si1000/1/2/3/4/5
Table 23.4. Packet Handler Registers
Add R/W Function/Description
D7
D6
D5
D4
D3
D2
D1
D0
POR
Def
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
R/W
R
Data Access Control
EzMAC status
enpacrx
0
lsbfrst
rxcrc1
crcdonly
pksrch
skip2ph
pkrx
enpactx
pkvalid
encrc
crc[1]
pktx
crc[0]
8Dh
—
crcerror
pksent
R/W
R/W
R/W
Header Control 1
Header Control 2
Preamble Length
bcen[3:0]
hdch[3:0]
0Ch
skipsyn
hdlen[2]
hdlen[1]
hdlen[0]
fixpklen
synclen[1] synclen[0] prealen[8] 22h
prealen[7] prealen[6] prealen[5] prealen[4] prealen[3] prealen[2] prealen[1] prealen[0] 08h
R/W Preamble Detection Control preath[4]
preath[3]
sync[30]
sync[22]
sync[14]
sync[6]
preath[2]
sync[29]
sync[21]
sync[13]
sync[5]
preath[1]
sync[28]
sync[20]
sync[12]
sync[4]
preath[0]
sync[27]
sync[19]
sync[11]
sync[3]
rssi_off[2] rssi_off[1] rssi_off[0]
2Ah
2Dh
D4h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
FFh
FFh
FFh
FFh
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Sync Word 3
Sync Word 2
sync[31]
sync[23]
sync[15]
sync[7]
sync[26]
sync[18]
sync[10]
sync[2]
sync[25]
sync[17]
sync[9]
sync[1]
txhd[25]
txhd[17]
txhd[9]
sync[24]
sync[16]
sync[8]
sync[0]
txhd[24]
txhd[16]
txhd[8]
Sync Word 1
Sync Word 0
Transmit Header 3
Transmit Header 2
Transmit Header 1
Transmit Header 0
Transmit Packet Length
Check Header 3
Check Header 2
Check Header 1
Check Header 0
Header Enable 3
Header Enable 2
Header Enable 1
Header Enable 0
Received Header 3
Received Header 2
Received Header 1
Received Header 0
Received Packet Length
txhd[31]
txhd[23]
txhd[15]
txhd[7]
txhd[30]
txhd[22]
txhd[14]
txhd[6]
txhd[29]
txhd[21]
txhd[13]
txhd[5]
txhd[28]
txhd[20]
txhd[12]
txhd[4]
txhd[27]
txhd[19]
txhd[11]
txhd[3]
txhd[26]
txhd[18]
txhd[10]
txhd[2]
txhd[1]
txhd[0]
pklen[7]
chhd[31]
chhd[23]
chhd[15]
chhd[7]
hden[31]
hden[23]
hden[15]
hden[7]
rxhd[31]
rxhd[23]
rxhd[15]
rxhd[7]
pklen[6]
chhd[30]
chhd[22]
chhd[14]
chhd[6]
hden[30]
hden[22]
hden[14]
hden[6]
rxhd[30]
rxhd[22]
rxhd[14]
rxhd[6]
pklen[5]
chhd[29]
chhd[21]
chhd[13]
chhd[5]
hden[29]
hden[21]
hden[13]
hden[5]
rxhd[29]
rxhd[21]
rxhd[13]
rxhd[5]
pklen[4]
chhd[28]
chhd[20]
chhd[12]
chhd[4]
hden[28]
hden[20]
hden[12]
hden[4]
rxhd[28]
rxhd[20]
rxhd[12]
rxhd[4]
pklen[3]
chhd[27]
chhd[19]
chhd[11]
chhd[3]
hden[27]
hden[19]
hden[11]
hden[3]
rxhd[27]
rxhd[19]
rxhd[11]
rxhd[3]
pklen[2]
chhd[26]
chhd[18]
chhd[10]
chhd[2]
hden[26]
hden[18]
hden[10]
hden[2]
rxhd[26]
rxhd[18]
rxhd[10]
rxhd[2]
pklen[1]
chhd[25]
chhd[17]
chhd[9]
chhd[1]
hden[25]
hden[17]
hden[9]
hden[1]
rxhd[25]
rxhd[17]
rxhd[9]
pklen[0]
chhd[24]
chhd[16]
chhd[8]
chhd[0]
hden[24]
hden[16]
hden[8]
hden[0]
rxhd[24]
rxhd[16]
rxhd[8]
R
—
R
—
R
rxhd[1]
rxhd[0]
—
R
rxplen[7]
rxplen[6]
rxplen[5]
rxplen[4]
rxplen[3]
rxplen[2]
rxplen[1]
rxplen[0]
—
23.6.5. Data Whitening, Manchester Encoding, and CRC
Data whitening can be used to avoid extended sequences of 0s or 1s in the transmitted data stream to
achieve a more uniform spectrum. When enabled, the payload data bits are XORed with a pseudorandom
sequence output from the built-in PN9 generator. The generator is initialized at the beginning of the pay-
load. The receiver recovers the original data by repeating this operation. Manchester encoding can be
used to ensure a dc-free transmission and good synchronization properties. When Manchester encoding is
used, the effective datarate is unchanged but the actual datarate (preamble length, etc.) is doubled due to
the nature of the encoding. The effective datarate when using Manchester encoding is limited to 128 kbps.
The implementation of Manchester encoding is shown in Figure 23.18. Data whitening and Manchester
encoding can be selected with "Register 70h. Modulation Mode Control 1". The CRC is configured via
"Register 30h. Data Access Control". Figure 23.17 demonstrates the portions of the packet which have
Manchester encoding, data whitening, and CRC applied. CRC can be applied to only the data portion of
the packet or to the data, packet length and header fields. Figure 23.18 provides an example of how the
Manchester encoding is done and also the use of the Manchester invert (enmaniv) function.
Rev. 1.0
265
Si1000/1/2/3/4/5
Manchester
Whitening
CRC
CRC
(Over data only)
Header/
Address
PK
Length
Preamble
Sync
CRC
Data
Figure 23.17. Operation of Data Whitening, Manchester Encoding, and CRC
Data before Manchester
1
1
1
1
1
1
1
1
0
0
0
1
0
Preamble = 0xFF
First 4bits of the synch. word = 0x2
Data after Machester ( manppol = 1, enmaninv = 0)
Data after Machester ( manppol = 1, enmaninv = 1)
Data before Manchester
0
0
0
0
0
0
0
0
0
0
0
1
0
Preamble = 0x00
First 4bits of the synch. word = 0x2
Data after Machester ( manppol = 0, enmaninv = 0)
Data after Machester ( manppol = 0, enmaninv = 1)
Figure 23.18. Manchester Coding Example
23.6.6. Preamble Detector
The EZRadioPRO transceiver has integrated automatic preamble detection. The preamble length is con-
figurable from 1–255 bytes using the prealen[7:0] field in "Register 33h. Header Control 2" and "Register
34h. Preamble Length", as described in “23.6.2. Packet Configuration” . The preamble detection threshold,
preath[4:0] as set in "Register 35h. Preamble Detection Control 1", is in units of 4 bits. The preamble
detector searches for a preamble pattern with a length of preath[4:0].
If a false preamble detect occurs, the receiver will continuing searching for the preamble when no sync
word is detected. Once preamble is detected (false or real) then the part will then start searching for sync.
If no sync occurs then a timeout will occur and the device will initiate search for preamble again. The time-
out period is defined as the sync word length plus four bits and will start after a non-preamble pattern is
recognized after a valid preamble detection. The preamble detector output may be programmed onto one
of the GPIO or read in the interrupt status registers.
23.6.7. Preamble Length
The preamble detection threshold determines the number of valid preamble bits the radio must receive to
qualify a valid preamble. The preamble threshold should be adjusted depending on the nature of the appli-
cation. The required preamble length threshold will depend on when receive mode is entered in relation to
the start of the transmitted packet and the length of the transmit preamble. With a shorter than recom-
mended preamble detection threshold the probability of false detection is directly related to how long the
receiver operates on noise before the transmit preamble is received. False detection on noise may cause
the actual packet to be missed. The preamble detection threshold is programmed in register 35h. For most
applications with a preamble length longer than 32 bits the default value of 20 is recommended for the pre-
266
Rev. 1.0
Si1000/1/2/3/4/5
amble detection threshold. A shorter Preamble Detection Threshold may be chosen if occasional false
detections may be tolerated. When antenna diversity is enabled a 20-bit preamble detection threshold is
recommended. When the receiver is synchronously enabled just before the start of the packet, a shorter
preamble detection threshold may be used. Table 23.5 demonstrates the recommended preamble detec-
tion threshold and preamble length for various modes.
It is possible to use the transceiver in a raw mode without the requirement for a 010101... preamble. Con-
tact customer support for further details.
Table 23.5. Minimum Receiver Settling Time
Approximate RecommendedPreamble Recommended Preamble
Mode
Receiver
Settling Time
1 byte
Length with 8-Bit
Detection Threshold
20 bits
Length with 20-Bit
Detection Threshold
32 bits
(G)FSK AFC Disabled
(G)FSK AFC Enabled
(G)FSK AFC Disabled
+Antenna Diversity Enabled
(G)FSK AFC Enabled
+Antenna Diversity Enabled
OOK
2 byte
28 bits
40 bits
1 byte
—
64 bits
2 byte
2 byte
8 byte
—
3 byte
—
8 byte
4 byte
8 byte
OOK + Antenna Diversity
Enabled
Note: The recommended preamble length and preamble detection threshold listed above are to achieve 0% PER.
They may be shortened when occasional packet errors are tolerable.
23.6.8. Invalid Preamble Detector
When scanning channels in a frequency hopping system it is desirable to determine if a channel is valid in
the minimum amount of time. The preamble detector can output an invalid preamble detect signal. which
can be used to identify the channel as invalid. After a configurable time set in Register 60h[7:4], an invalid
preamble detect signal is asserted indicating an invalid channel. The period for evaluating the signal for
invalid preamble is defined as (inv_pre_th[3:0] x 4) x Bit Rate Period. The preamble detect and invalid pre-
amble detect signals are available in "Register 03h. Interrupt/Status 1" and “Register 04h. Interrupt/Status
2.”
23.6.9. Synchronization Word Configuration
The synchronization word length for both TX and RX can be configured in Reg 33h, synclen[1:0]. The
expected or transmitted sync word can be configured from 1 to 4 bytes as defined below:
synclen[1:0] = 00—Expected/Transmitted Synchronization Word (sync word) 3.
synclen[1:0] = 01—Expected/Transmitted Synchronization Word 3 first, followed by sync word 2.
synclen[1:0] = 10—Expected/Transmitted Synchronization Word 3 first, followed by sync word 2,
followed by sync word 1.
synclen[1:0] = 1—Send/Expect Synchronization Word 3 first, followed by sync word 2, followed by sync
word 1, followed by sync word 0.
The sync is transmitted or expected in the following sequence: sync 3sync 2sync 1sync 0. The sync
word values can be programmed in Registers 36h–39h. After preamble detection the part will search for
sync for a fixed period of time. If a sync is not recognized in this period then a timeout will occur and the
search for preamble will be re-initiated. The timeout period after preamble detections is defined as the
value programmed into the sync word length plus four additional bits.
Rev. 1.0
267
Si1000/1/2/3/4/5
23.6.10. Receive Header Check
The header check is designed to support 1–4 bytes and broadcast headers. The header length needs to
be set in register 33h, hdlen[2:0]. The headers to be checked need to be set in register 32h, hdch[3:0]. For
instance, there can be four bytes of header in the packet structure but only one byte of the header is set to
be checked (i.e., header 3). For the headers that are set to be checked, the expected value of the header
should be programmed in chhd[31:0] in Registers 3F–42. The individual bits within the selected bytes to be
checked can be enabled or disabled with the header enables, hden[31:0] in Registers 43–46. For example,
if you want to check all bits in header 3 then hden[31:24] should be set to FF but if only the last 4 bits are
desired to be checked then it should be set to 00001111 (0F). Broadcast headers can also be programmed
by setting bcen[3:0] in Register 32h. For broadcast header check the value may be either “FFh” or the
value stored in the Check Header register. A logic equivalent of the header check for Header 3 is shown in
Figure 23.19. A similar logic check will be done for Header 2, Header 1, and Header 0 if enabled.
Example for Header 3
rxhd[31:24]
BIT
Equivalence
comparison
WISE
hden[31:24]
=
BIT
WISE
chhd[31:24]
header3_ok
bcen[3]
Equivalence
comparison
FFh
=
hdch[3]
rxhd[31:24]
Figure 23.19. Header
23.6.11. TX Retransmission and Auto TX
The transceiver is capable of automatically retransmitting the last packet loaded in the TX FIFO. Automatic
retransmission is set by entering the TX state with the txon bit without reloading the TX FIFO. This feature
is useful for beacon transmission or when retransmission is required due to the absence of a valid
acknowledgement. Only packets that fit completely in the TX FIFO can be automatically retransmitted.
An automatic transmission function is available, allowing the radio to automatically start or stop a transmis-
sion depending on the amount of data in the TX FIFO.
When autotx is set in “Register 08. Operating & Function Control 2", the transceiver will automatically enter
the TX state when the TX FIFO almost full threshold is exceeded. Packets will be transmitted according to
the configured packet length. To stop transmitting, clear the packet sent or TX FIFO almost empty inter-
rupts must be cleared by reading register.
268
Rev. 1.0
Si1000/1/2/3/4/5
23.7. RX Modem Configuration
A Microsoft Excel parameter calculator or Wireless Development Suite (WDS) calculator is provided to
determine the proper settings for the modem. The calculator can be found on www.silabs.com or on the
CD provided with the demo kits. An application note is available to describe how to use the calculator and
to provide advanced descriptions of the modem settings and calculations.
23.7.1. Modem Settings for FSK and GFSK
The modem performs channel selection and demodulation in the digital domain. The channel filter band-
width is configurable from 2.6 to 620 kHz. The receiver data-rate, modulation index, and bandwidth are set
via registers 1C–25h. The modulation index is equal to 2 times the peak deviation divided by the data rate
(Rb).
When Manchester coding is disabled, the required channel filter bandwidth is calculated as BW = 2Fd + Rb
where Fd is the frequency deviation and Rb is the data rate.
23.8. Auxiliary Functions
The EZRadioPRO has some auxiliary functions that duplicate the directly accessible MCU peripherals:
ADC, temperature sensor, and 32 kHz oscillator. These auxiliary functions are retained primarily for com-
patibility with the Si4430/1/2. The directly accessed MCU peripherals typically provide lower system cur-
rent consumption and better analog performance. However some of these EZRadioPRO auxiliary
functions offer features not directly duplicated in the MCU directly accessed peripherals, such as the Low
Duty Cycle Mode operation.
23.8.1. Smart Reset
The EZRadioPRO transceiver contains an enhanced integrated SMART RESET or POR circuit. The POR
circuit contains both a classic level threshold reset as well as a slope detector POR. This reset circuit was
designed to produce a reliable reset signal under any circumstances. Reset will be initiated if any of the fol-
lowing conditions occur:
Initial power on, V starts from gnd: reset is active till V reaches V (see table);
DD DD RR
When V decreases below V for any reason: reset is active till V reaches V ;
RR
DD
LD
DD
A software reset via “Register 08h. Operating Mode and Function Control 2”: reset is active for time
T
SWRST
On the rising edge of a V glitch when the supply voltage exceeds the following time functioned limit:
DD
VDD nom.
VDD(t)
reset limit:
0.4V+t*0.2V/ms
actual VDD(t)
showing glitch
0.4V
Reset
TP
t
t=0,
reset:
VDD starts to rise
Vglitch>=0.4+t*0.2V/ms
Figure 23.20. POR Glitch Parameters
Rev. 1.0
269
Si1000/1/2/3/4/5
Table 23.6. POR Parameters
Comment
Parameter
Symbol
VRR
Min
0.85
0.03
0.7
50
Typ
1.3
—
Max
1.75
300
1.3
470
—
Unit
V
Release Reset Voltage
Power-On V Slope
SVDD
VLD
tested V slope region
V/ms
V
DD
DD
Low V Limit
VLD<VRR is guaranteed
1
DD
Software Reset Pulse
Threshold Voltage
Reference Slope
TSWRST
VTSD
k
—
us
—
0.4
0.2
16
V
—
—
V/ms
ms
V
Glitch Reset Pulse
TP
Also occurs after SDN, and
initial power on
5
25
DD
The reset will initialize all registers to their default values. The reset signal is also available for output and
use by the microcontroller by using the default setting for GPIO_0. The inverted reset signal is available by
default on GPIO_1.
23.8.2. Output Clock
The 30 MHz crystal oscillator frequency is divided down internally and may be output on GPIO2. This fea-
ture is useful to lower BOM cost by using only one crystal in the system. The output clock on GPIO2 may
be routed to the XTAL2 input to provide a synchronized clock source between the MCU and the EZRadio-
PRO peripheral. The output clock frequency is selectable from one of 8 options, as shown below. Except
for the 32.768 kHz option, all other frequencies are derived by dividing the crystal oscillator frequency. The
32.768 kHz clock signal is derived from an internal RC oscillator or an external 32 kHz crystal. The default
setting for GPIO2 is to output the clock signal with a frequency of 1 MHz.
D7
D6
D5
D4
D3
D2
D1
D0
POR Def.
Add R/W
Function/
Description
0A R/W
Output Clock
clkt[1] clkt[0] enlfc mclk[2] mclk[1] mclk[0]
06h
mclk[2:0]
000
Modulation Source
30 MHz
001
15 MHz
010
10 MHz
011
4 MHz
100
3 MHz
101
2 MHz
110
1 MHz
111
32.768 kHz
Since the crystal oscillator is disabled in SLEEP mode in order to save current, the low-power 32.768 kHz
clock can be automatically switched to become the output clock. This feature is called enable low fre-
quency clock and is enabled by the enlfc bit in “Register 0Ah. Microcontroller Output Clock." When enlfc =
1 and the chip is in SLEEP mode then the 32.768 kHz clock will be provided regardless of the setting of
mclk[2:0]. For example, if mclk[2:0] = 000, 30 MHz will be provided through the GPIO output pin in all IDLE,
270
Rev. 1.0
Si1000/1/2/3/4/5
TX, or RX states. When the chip enters SLEEP mode, the output clock will automatically switch to
32.768 kHz from the RC oscillator or 32.768 XTAL.
Another available feature for the output clock is the clock tail, clkt[1:0] in “Register 0Ah. Microcontroller
Output Clock." If the low frequency clock feature is not enabled (enlfc = 0), then the output is disabled in
SLEEP mode. Setting the clkt[1:0] field will provide additional cycles of the output clock before it shuts off.
clkt[1:0]
Modulation Source
0 cycles
00
01
10
11
128 cycles
256 cycles
512 cycles
If an interrupt is triggered, the output clock will remain enabled regardless of the selected mode. As soon
as the interrupt is read the state machine will then move to the selected mode. The minimum current con-
sumption will not be achieved until the interrupt is read. For instance, if the EZRadioPRO peripheral is
commanded to SLEEP mode but an interrupt has occurred the 30 MHz XTAL will not be disabled until the
interrupt has been cleared.
23.8.3. General Purpose ADC
The EZRadioPRO peripheral includes an 8-bit SAR ADC independent of ADC0. It may be used for general
purpose analog sampling, as well as for digitizing the EZRadioPRO temperature sensor reading. In most
cases, the ADC0 subsystem directly accessible from the MCU will be preferred over the ADC embedded
inside the EZRadioPRO peripheral. Registers 0Fh "ADC Configuration", 10h "Sensor Offset" and 4Fh
"Amplifier Offset" can be used to configure the ADC operation. Details of these registers are in “AN440:
EZRadioPRO Detailed Register Descriptions.”
Every time an ADC conversion is desired, bit 7 "adcstart/adcdone" in Register 0Fh “ADC Configuration”
must be set to 1. The conversion time for the ADC is 350 µs. After the ADC conversion is done and the
adcdone signal is showing 1, then the ADC value may be read out of “Register 11h: ADC Value." When the
ADC is doing its conversion, the adcstart/adcdone bit will read 0. When the ADC has finished its conver-
sion, the bit will be set to 1. A new ADC conversion can be initiated by writing a 1 to the adcstart/adcdone
bit.
The architecture of the ADC is shown in Figure 23.21. The signal and reference inputs of the ADC are
selected by adcsel[2:0] and adcref[1:0] in register 0Fh “ADC Configuration”, respectively. The default set-
ting is to read out the temperature sensor using the bandgap voltage (VBG) as reference. With the VBG
reference the input range of the ADC is from 0–1.02 V with an LSB resolution of 4 mV (1.02/255). Chang-
ing the ADC reference will change the LSB resolution accordingly.
A differential multiplexer and amplifier are provided for interfacing external bridge sensors. The gain of the
amplifier is selectable by adcgain[1:0] in Register 0Fh. The majority of sensor bridges have supply voltage
(VDD) dependent gain and offset. The reference voltage of the ADC can be changed to either V /2 or
DD
V
/3. A programmable V dependent offset voltage can be added using soffs[3:0] in register 10h.
DD
DD
Rev. 1.0
271
Si1000/1/2/3/4/5
Diff. MUX
Diff. Amp.
Input MUX
aoffs [4:0]
soffs [3:0]
adcsel [2:0]
adcgain [1:0]
GPIO0
GPIO1
GPIO2
8-bit ADC
Temperature Sensor
Vin
adc [7:0]
adcsel [2:0]
Vref
0 -1020mV / 0-255
Ref MUX
VDD / 3
VDD / 2
VBG (1.2V)
adcref [1:0]
Figure 23.21. General Purpose ADC Architecture
Add R/W
Function/
Description
D7
D6
D5
D4
D3
D2
D1
D0
POR
Def.
0F
10
11
R/W
R/W
R
ADC Configuration adcstart/adcdone adcsel[2] adcsel[1] adcsel[0] adcref[1]
adcref[0] adcgain[1] adcgain[0]
00h
00h
—
Sensor Offset
ADC Value
soffs[3]
adc[3]
soffs[2]
adc[2]
soffs[1]
adc[1]
soffs[0]
adc[0]
adc[7]
adc[6]
adc[5]
adc[4]
23.8.4. Temperature Sensor
The EZRadioPRO peripheral includes an integrated on-chip analog temperature sensor independent of
the temperature sensor associated with ADC0. The temperature sensor will be automatically enabled
when the temperature sensor is selected as the input of the EZRadioPRO ADC or when the analog temp
voltage is selected on the analog test bus. The temperature sensor value may be digitized using the EZRa-
dioPRO general-purpose ADC and read out through "Register 10h. ADC Sensor Amplifier Offset." The
range of the temperature sensor is configurable. Table 23.7 lists the settings for the different temperature
ranges and performance.
To use the Temp Sensor:
1. Set the input for ADC to the temperature sensor, "Register 0Fh. ADC Configuration"—adcsel[2:0] = 000
2. Set the reference for ADC, "Register 0Fh. ADC Configuration"—adcref[1:0] = 00
3. Set the temperature range for ADC, "Register 12h. Temperature Sensor Calibration"—tsrange[1:0]
4. Set entsoffs = 1, "Register 12h. Temperature Sensor Calibration"
5. Trigger ADC reading, "Register 0Fh. ADC Configuration"—adcstart = 1
6. Read temperature value—Read contents of "Register 11h. ADC Value"
272
Rev. 1.0
Si1000/1/2/3/4/5
Add R/
W
Function/
Description
D7
D6
D5
D4
D3
D2
D1
D0
POR
Def.
tsrange[1] tsrange[0] entsoffs entstrim tstrim[3]
tstrim[2] vbgtrim[1] vbgtrim[0]
12 R/W
Temperature
20h
Sensor Control
tvoffs[7]
tvoffs[6]
tvoffs[5] tvoffs[4]
tvoffs[3]
tvoffs[2]
tvoffs[1]
tvoffs[0]
13 R/W Temperature Value
Offset
00h
Table 23.7. Temperature Sensor Range
entoff
tsrange[1]
tsrange[0]
Temp. range Unit
Slope
ADC8 LSB
0.5 °C
1 °C
1
1
0
0
1
1
1
0
1
0
1
0
–64 … 64
–64 … 192
0 … 128
°C
°C
°C
°F
°K
8 mV/°C
4 mV/°C
8 mV/°C
4 mV/°F
3 mV/°K
1
0.5 °C
1 °F
1
–40 … 216
0 … 341
0*
1.333 °K
Note: Absolute temperature mode, no temperature shift. This mode is only for test purposes. POR value of
EN_TOFF is 1.
The slope of the temperature sensor is very linear and monotonic. For absolute accuracy better than 10 °C
calibration is necessary. The temperature sensor may be calibrated by setting entsoffs = 1 in “Register
12h. Temperature Sensor Control” and setting the offset with the tvoffs[7:0] bits in “Register 13h. Tempera-
ture Value Offset.” This method adds a positive offset digitally to the ADC value that is read in “Register
11h. ADC Value.” The other method of calibration is to use the tstrim which compensates the analog cir-
cuit. This is done by setting entstrim = 1 and using the tstrim[2:0] bits to offset the temperature in “Register
12h. Temperature Sensor Control.” With this method of calibration, a negative offset may be achieved.
With both methods of calibration better than ±3 °C absolute accuracy may be achieved.
The different ranges for the temperature sensor and ADC8 are demonstrated in Figure 23.22. The value of
the ADC8 may be translated to a temperature reading by ADC8Value x ADC8 LSB + Lowest Temperature
in Temp Range. For instance for a tsrange = 00, Temp = ADC8Value x 0.5 – 64.
Rev. 1.0
273
Si1000/1/2/3/4/5
Temperature Measurement with ADC8
300
250
200
150
100
Sensor Range 0
Sensor Range 1
Sensor Range 2
Sensor Range 3
50
0
-40
-20
0
20
40
60
80
100
Temperature [Celsius]
Figure 23.22. Temperature Ranges using ADC8
23.8.5. Low Battery Detector
A low battery detector (LBD) with digital read-out is integrated into the chip. A digital threshold may be pro-
grammed into the lbdt[4:0] field in "Register 1Ah. Low Battery Detector Threshold". When the digitized bat-
tery voltage reaches this threshold an interrupt will be generated on the nIRQ pin to the microcontroller.
The microcontroller can confirm source of the interrupt by reading "Register 03h. Interrupt/Status 1" and
“Register 04h. Interrupt/Status 2.”
If the LBD is enabled while the chip is in SLEEP mode, it will automatically enable the RC oscillator which
will periodically turn on the LBD circuit to measure the battery voltage. The battery voltage may also be
read out through "Register 1Bh. Battery Voltage Level" at any time when the LBD is enabled. The low bat-
tery detect function is enabled by setting enlbd=1 in "Register 07h. Operating Mode and Function Control
1".
D7
D6
D5
D4
D3
D2
D1
D0
POR
Def.
Add R/W Function/Description
1A
1B
R/W
R
Low Battery Detector
Threshold
lbdt[4] lbdt[3] lbdt[2] lbdt[1] lbdt[0]
vbat[4] vbat[3] vbat[2] vbat[1] vbat[0]
14h
Battery Voltage Level
0
0
0
—
The LBD output is digitized by a 5-bit ADC. When the LBD function is enabled (enlbd = 1 in "Register 07h.
Operating Mode and Function Control 1") the battery voltage may be read at anytime by reading "Register
1Bh. Battery Voltage Level." A battery voltage threshold may be programmed in “Register 1Ah. Low Bat-
tery Detector Threshold". When the battery voltage level drops below the battery voltage threshold an
interrupt will be generated on nIRQ pin to the microcontroller if the LBD interrupt is enabled in “Register
274
Rev. 1.0
Si1000/1/2/3/4/5
06h. Interrupt Enable 2.” The microcontroller will then need to verify the interrupt by reading the interrupt
status register, addresses 03 and 04h. The LSB step size for the LBD ADC is 50 mV, with the ADC range
demonstrated in the table below. If the LBD is enabled the LBD and ADC will automatically be enabled
every 1 s for approximately 250 µs to measure the voltage which minimizes the current consumption in
Sensor mode. Before an interrupt is activated four consecutive readings are required.
BatteryVoltage 1.7 50mV ADCValue
ADC Value
VDD Voltage [V]
< 1.7
0
1
1.7–1.75
1.75–1.8
…
2
…
29
30
31
3.1–3.15
3.15–3.2
> 3.2
23.8.6. Wake-Up Timer and 32 kHz Clock Source
The EZRadioPRO peripheral contains an integrated wake-up timer independent of the SmaRTClock which
can be used to periodically wake the chip from SLEEP mode using the interrupt pin. The wake-up timer
runs from the internal 32.768 kHz RC Oscillator. The wake-up timer can be configured to run when in
SLEEP mode. If enwt = 1 in "Register 07h. Operating Mode and Function Control 1" when entering SLEEP
mode, the wake-up timer will count for a time specified defined in Registers 14–16h, "Wake Up Timer
Period". At the expiration of this period an interrupt will be generated on the nIRQ pin if this interrupt is
enabled. The software will then need to verify the interrupt by reading the Registers 03h–04h, "Interrupt
Status 1 & 2". The wake-up timer value may be read at any time by the wtv[15:0] read only registers 17h–
18h.
The formula for calculating the Wake-Up Period is the following:
32 M 2R
WUT
ms
32.768
WUT Register
wtr[4:0]
Description
R Value in Formula
M Value in Formula
wtm[15:0]
Use of the D variable in the formula is only necessary if finer resolution is required than can be achieved by
using the R value.
Rev. 1.0
275
Si1000/1/2/3/4/5
D7
D6
D5
D4
D3
D2
D1
D0
POR
Def.
Add R/W Function/Description
14 R/W Wake-Up Timer Period 1
wtr[4]
wtr[3]
wtr[2]
wtr[1] wtr[0]
03h
15 R/W Wake-Up Timer Period 2 wtm[15] wtm[14] wtm[13] wtm[12] wtm[11] wtm[10] wtm[9] wtm[8] 00h
16 R/W Wake-Up Timer Period 3 wtm[7] wtm[6] wtm[5] wtm[4] wtm[3] wtm[2] wtm[1] wtm[0] 00h
17
18
R
R
Wake-Up Timer Value 1 wtv[15] wtv[14] wtv[13] wtv[12] wtv[11] wtv[10] wtv[9] wtv[8]
Wake-Up Timer Value 2 wtv[7] wtv[6] wtv[5] wtv[4] wtv[3] wtv[2] wtv[1] wtv[0]
—
—
There are two different methods for utilizing the wake-up timer (WUT) depending on if the WUT interrupt is
enabled in “Register 06h. Interrupt Enable 2.” If the WUT interrupt is enabled then nIRQ pin will go low
when the timer expires. The chip will also change state so that the 30 MHz XTAL is enabled so that the
microcontroller clock output is available for the microcontroller to use to process the interrupt. The other
method of use is to not enable the WUT interrupt and use the WUT GPIO setting. In this mode of operation
the chip will not change state until commanded by the microcontroller. The different modes of operating the
WUT and the current consumption impacts are demonstrated in Figure 23.23.
A 32 kHz XTAL may also be used for better timing accuracy. By setting the x32 ksel bit in Register 07h
"Operating & Function Control 1", GPIO0 is automatically reconfigured so that an external 32 kHz XTAL
may be connected to this pin. In this mode, the GPIO0 is extremely sensitive to parasitic capacitance, so
only the XTAL should be connected to this pin with the XTAL physically located as close to the pin as pos-
sible. Once the x32 ksel bit is set, all internal functions such as WUT, microcontroller clock, and LDC mode
will use the 32 kHz XTAL and not the 32 kHz RC oscillator.
The 32 kHz XTAL accuracy is comprised of both the XTAL parameters and the internal circuit. The XTAL
accuracy can be defined as the XTAL initial error + XTAL aging + XTAL temperature drift + detuning from
the internal oscillator circuit. The error caused by the internal circuit is typically less than 10 ppm.
276
Rev. 1.0
Si1000/1/2/3/4/5
Interrupt Enable enwut =1( Reg 06h)
WUT Period
GPIOX =00001
nIRQ
SPI Interrupt
Read
Chip State
Sleep
Ready
Sleep
Ready
Sleep
Ready
1.5 mA
Sleep
1.5 mA
1.5 mA
Current
Consumption
1 uA
1 uA
1 uA
Interrupt Enable enwut =0( Reg 06h)
WUT Period
GPIOX =00001
nIRQ
SPI Interrupt
Read
Chip State
Sleep
Current
Consumption
1 uA
Figure 23.23. WUT Interrupt and WUT Operation
23.8.7. Low Duty Cycle Mode
The Low Duty Cycle Mode is available to automatically wake-up the receiver to check if a valid signal is
available. The basic operation of the low duty cycle mode is demonstrated in the figure below. If a valid
preamble or sync word is not detected the chip will return to sleep mode until the beginning of a new WUT
period. If a valid preamble and sync are detected the receiver on period will be extended for the low duty
cycle mode duration (TLDC) to receive all of the packet. The WUT period must be set in conjunction with
the low duty cycle mode duration. The R value (“Register 14h. Wake-up Timer Period 1”) is shared
Rev. 1.0
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Si1000/1/2/3/4/5
between the WUT and the TLDC. The ldc[7:0] bits are located in “Register 19h. Low Duty Cycle Mode
Duration.” The time of the TLDC is determined by the formula below:
R
4 2
TLDC ldc [7 : 0 ]
ms
32 .768
Figure 23.24. Low Duty Cycle Mode
23.8.8. GPIO Configuration
Three general purpose IOs (GPIOs) are available. Numerous functions such as specific interrupts, TRSW
control, etc. can be routed to the GPIO pins as shown in the tables below. When in Shutdown mode all the
GPIO pads are pulled low.
Note: The ADC should not be selected as an input to the GPIO in standby or sleep modes and will cause excess cur-
rent consumption.
D7
D6
D5
D4
D3
D2
D1
D0
POR
Def.
Add R/W
Function/
Description
0B R/W
0C R/W
0D R/W
0E R/W
GPIO0
Configuration
gpio0drv[1] gpio0drv[0] pup0
gpio1drv[1] gpio1drv[0] pup1
gpio2drv[1] gpio2drv[0] pup2
gpio0[4] gpio0[3] gpio0[2] gpio0[1] gpio0[0] 00h
gpio1[4] gpio1[3] gpio1[2] gpio1[1] gpio1[0] 00h
gpio2[4] gpio2[3] gpio2[2] gpio2[1] gpio2[0] 00h
GPIO1
Configuration
GPIO2
Configuration
I/O Port
extitst[2] extitst[1] extitst[0]
itsdo
dio2
dio1
dio0
00h
Configuration
The GPIO settings for GPIO1 and GPIO2 are the same as for GPIO0 with the exception of the 00000
default setting. The default settings for each GPIO are listed below:
GPIO
GPIO0
GPIO1
GPIO2
00000—Default Setting
POR
POR Inverted
Output Clock
For a complete list of the available GPIOs see “AN440: EZRadioPRO Detailed Register Descriptions”.
The GPIO drive strength may be adjusted with the gpioXdrv[1:0] bits. Setting a higher value will increase
the drive strength and current capability of the GPIO by changing the driver size. Special care should be
278
Rev. 1.0
Si1000/1/2/3/4/5
taken in setting the drive strength and loading on GPIO2 when the microcontroller clock is used. Excess
loading or inadequate drive may contribute to increased spurious emissions.
Pin 6, ANT may be used as an alternate to control a TR switch. Pin 6 is a hardwired version of GPIO set-
ting 11000, Antenna 2 Switch used for antenna diversity. It can be manually controlled by the antdiv[2:0]
bits in register 08h if antenna diversity is not used. See AN440, register 08h for more details.
23.8.9. Antenna Diversity
To mitigate the problem of frequency-selective fading due to multi-path propagation, some transceiver sys-
tems use a scheme known as antenna diversity. In this scheme, two antennas are used. Each time the
transceiver enters RX mode the receive signal strength from each antenna is evaluated. This evaluation
process takes place during the preamble portion of the packet. The antenna with the strongest received
signal is then used for the remainder of that RX packet. The same antenna will also be used for the next
corresponding TX packet.
This chip fully supports antenna diversity with an integrated antenna diversity control algorithm. The
required signals needed to control an external SPDT RF switch (such as PIN diode or GaAs switch) are
available on the GPIOx pins. The operation of these GPIO signals is programmable to allow for different
antenna diversity architectures and configurations. The antdiv[2:0] bits are found in register 08h “Operating
& Function Control 2.” The GPIO pins are capable of sourcing up to 5 mA of current, so it may be used
directly to forward-bias a PIN diode if desired.
The antenna diversity algorithm will automatically toggle back and forth between the antennas until the
packet starts to arrive. The recommended preamble length for optimal antenna selection is 8 bytes. A spe-
cial antenna diversity algorithm (antdiv[2:0] = 110 or 111) is included that allows for shorter preamble
lengths for beacon mode in TDMA-like systems where the arrival of the packet is synchronous to the
receiver enable. The recommended preamble length to obtain optimal antenna selection for synchronous
mode is 4 bytes.
D7
D6
D5
D4
D3
D2
D1
D0
POR
Def.
Add R/W Function/Description
08 R/W
Operating & Function
Control 2
antdiv[2] antdiv[1] antdiv[0] rxmpk autotx enldm ffclrrx
ffclrtx
00h
Table 23.8. Antenna Diversity Control
antdiv[2:0]
000
RX/TX State
Non RX/TX State
GPIO Ant1
GPIO Ant2
GPIO Ant1
GPIO Ant2
0
1
0
1
1
0
1
0
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
001
010
011
100
101
110
111
Antenna Diversity Algorithm
Antenna Diversity Algorithm
Antenna Diversity Algorithm in Beacon Mode
Antenna Diversity Algorithm in Beacon Mode
23.8.10. RSSI and Clear Channel Assessment
Received signal strength indicator (RSSI) is an estimate of the signal strength in the channel to which the
receiver is tuned. The RSSI value can be read from an 8-bit register with 0.5 dB resolution per bit.
Figure 23.25 demonstrates the relationship between input power level and RSSI value. The absolute value
of the RSSI will change slightly depending on the modem settings. The RSSI may be read at anytime, but
Rev. 1.0
279
Si1000/1/2/3/4/5
an incorrect error may rarely occur. The RSSI value may be incorrect if read during the update period. The
update period is approximately 10 ns every 4 Tb. For 10 kbps, this would result in a 1 in 40,000 probability
that the RSSI may be read incorrectly. This probability is extremely low, but to avoid this, one of the follow-
ing options is recommended: majority polling, reading the RSSI value within 1 Tb of the RSSI interrupt, or
using the RSSI threshold described in the next paragraph for Clear Channel Assessment (CCA).
D7
D6
D5
D4
D3
D2
D1
D0
POR
Def.
Add R/W
Function/Description
26
27
R
Received Signal Strength Indicator
rssi[7]
rssi[6]
rssi[5]
rssi[4]
rssi[3]
rssi[2]
rssi[1]
rssi[0]
—
R/W RSSI Threshold for Clear Channel Indicator rssith[7] rssith[6] rssith[5] rssith[4] rssith[3] rssith[2] rssith[1] rssith[0]
00h
For CCA, threshold is programmed into rssith[7:0] in "Register 27h. RSSI Threshold for Clear Channel
Indicator." After the RSSI is evaluated in the preamble, a decision is made if the signal strength on this
channel is above or below the threshold. If the signal strength is above the programmed threshold then the
RSSI status bit, irssi, in "Register 04h. Interrupt/Status 2" will be set to 1. The RSSI status can also be
routed to a GPIO line by configuring the GPIO configuration register to GPIOx[3:0] = 1110.
RSSI vs Input Power
250
200
150
100
50
0
-120
-100
-80
-60
-40
-20
0
20
In Pow [dBm]
Figure 23.25. RSSI Value vs. Input Power
23.9. Reference Design
Reference designs are available at www.silabs.com for many common applications which include recom-
mended schematics, BOM, and layout. TX matching component values for the different frequency bands
can be found in the application notes “AN435: Si4032/4432 PA Matching” and “AN436:
Si4030/4031/4430/4431 PA Matching.” RX matching component values for different frequency bands can
be found in “AN427: EZRadioPRO Si433x and Si443x RX LNA Matching.”
280
Rev. 1.0
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ꢐ ꢎ
ꢏ ꢎ
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; 9 ꢁ
= :
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Rev. 1.0
281
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282
Rev. 1.0
Si1000/1/2/3/4/5
23.10. Application Notes and Reference Designs
A comprehensive set of application notes and reference designs are available to assist with the develop-
ment of a radio system. A partial list of applications notes is given below.
For the complete list of application notes, latest reference designs and demos visit the Silicon Labs website.
AN361: Wireless MBUS Implementation using EZRadioPRO Devices
AN379: Antenna Diversity with EZRadioPRO
AN414: EZRadioPRO Layout Design Guide
AN415: EZRadioPRO Programming Guide
AN417: Si4x3x Family Crystal Oscillators
AN419: ARIB STD-T67 Narrow-Band 426/429 MHz Measured on the Si4431-A0
AN427: EZRadioPRO Si433x and Si443x RX LNA Matching
AN429: Using the DC-DC Converter on the F9xx Series MCU for Single Battery Operation with the
EZRadioPRO RF Devices
AN432: RX BER Measurement on EZRadioPRO with a Looped PN Sequence
AN435: Si4032/4432 PA Matching
AN436: Si4030/4031/4430/4431 PA Matching
AN437: 915 MHz Measurement Results and FCC Compliance
AN439: EZRadioPRO Quick Start Guide
AN440: Si4430/31/32 Register Descriptions
AN445: Si4431 RF Performance and ETSI Compliance Test Results
AN451: Wireless M-BUS Software Implementation
AN459: 950 MHz Measurement Results and ARIB Compliance
AN460: 470 MHz Measurement Results for China
AN463: Support for Non-Standard Packet Structures and RAW Mode
AN466: Si4030/31/32 Register Descriptions
AN467: Si4330 Register Descriptions
AN514: Using the EZLink Reference Design to Create a Two-Channel PWM Motor Control Circuit
AN539: EZMacPRO Overview
23.11. Customer Support
Technical support for the complete family of Silicon Labs wireless products is available by accessing the
wireless section of the Silicon Labs' website at www.silabs.com/wireless. For MCU support, please visit
www.silabs.com/mcu.
For answers to common questions please visit the wireless and mcu knowledge base at
www.silabs.com/support/knowledgebase.
Rev. 1.0
283
Si1000/1/2/3/4/5
23.12. Register Table and Descriptions
Table 23.9. EZRadioPRO Internal Register Descriptions
Add R/W
Function/Desc
Data
D4
dt[4]
vc[4]
headerr
irxffafull
irssi
enrxffafull
enrssi
POR
Default
D7
0
0
ffovfl
ifferr
iswdet
enfferr
enswdet
swres
D6
0
0
D5
0
0
D3
dt[3]
vc[3]
reserved
iext
D2
dt[2]
vc[2]
reserved
ipksent
ilbd
enpksent
enlbd
rxon
D1
dt[1]
vc[1]
D0
dt[0]
vc[0]
cps[0]
icrcerror
ipor
encrcerror
enpor
xton
00
01
02
03
04
05
06
07
R
R
R
R
R
Device Type
Device Version
Device Status
Interrupt Status 1
Interrupt Status 2
Interrupt Enable 1
Interrupt Enable 2
00111
06h
—
—
—
00h
03h
01h
ffunfl
rxffem
itxffaem
ipreainval
entxffaem
enpreainval
enwt
cps[1]
itxffafull
ipreaval
entxffafull
enpreaval
enlbd
ipkvalid
ichiprdy
enpkvalid
enchiprdy
pllon
iwut
R/W
R/W
enext
enwut
txon
R/W Operating & Function Con-
x32ksel
trol 1
R/W Operating & Function Con-
trol 2
08
09
antdiv[2]
xtalshft
antdiv[1]
xlc[6]
antdiv[0]
xlc[5]
rxmpk
xlc[4]
autotx
xlc[3]
enldm
xlc[2]
ffclrrx
xlc[1]
ffclrtx
xlc[0]
00h
7Fh
R/W
Crystal Oscillator Load
Capacitance
0A
0B
0C
0D
0E
0F
R/W Microcontroller Output Clock
Reserved
gpio0drv[1]
gpio1drv[1]
gpio2drv[1]
Reserved
adcstart/adc-
done
Reserved
gpio0drv[0]
gpio1drv[0]
gpio2drv[0]
extitst[2]
clkt[1]
pup0
pup1
pup2
extitst[1]
adcsel[1]
clkt[0]
gpio0[4]
gpio1[4]
gpio2[4]
extitst[0]
adcsel[0]
enlfc
gpio0[3]
gpio1[3]
gpio2[3]
itsdo
mclk[2]
gpio0[2]
gpio1[2]
gpio2[2]
dio2
mclk[1]
gpio0[1]
gpio1[1]
gpio2[1]
dio1
mclk[0]
gpio0[0]
gpio1[0]
gpio2[0]
dio0
06h
00h
00h
00h
00h
00h
R/W
R/W
R/W
R/W
R/W
GPIO0 Configuration
GPIO1 Configuration
GPIO2 Configuration
I/O Port Configuration
ADC Configuration
adcsel[2]
adcref[1]
adcref[0]
adcgain[1]
adcgain[0]
10
11
12
13
14
15
16
17
18
19
R/W ADC Sensor Amplifier Offset
ADC Value
R/W Temperature Sensor Control
R/W Temperature Value Offset
Reserved
adc[7]
tsrange[1]
tvoffs[7]
Reserved
wtm[15]
wtm[7]
wtv[15]
wtv[7]
ldc[7]
Reserved
adc[6]
Reserved
adc[5]
Reserved
adc[4]
entstrim
tvoffs[4]
wtr[4]
wtm[12]
wtm[4]
wtv[12]
wtv[4]
adcoffs[3]
adc[3]
tstrim[3]
tvoffs[3]
wtr[3]
wtm[11]
wtm[3]
wtv[11]
wtv[3]
adcoffs[2]
adc[2]
tstrim[2]
tvoffs[2]
wtr[2]
wtm[10]
wtm[2]
wtv[10]
wtv[2]
adcoffs[1]
adc[1]
tstrim[1]
tvoffs[1]
wtr[1]
wtm[9]
wtm[1]
wtv[9]
adcoffs[0]
adc[0]
tstrim[0]
tvoffs[0]
wtr[0]
wtm[8]
wtm[0]
wtv[8]
00h
—
R
tsrange[0]
tvoffs[6]
Reserved
wtm[14]
wtm[6]
wtv[14]
wtv[6]
ldc[6]
entsoffs
tvoffs[5]
Reserved
wtm[13]
wtm[5]
wtv[13]
wtv[5]
ldc[5]
20h
00h
03h
00h
01h
—
R/W
R/W
R/W
R
Wake-Up Timer Period 1
Wake-Up Timer Period 2
Wake-Up Timer Period 3
Wake-Up Timer Value 1
Wake-Up Timer Value 2
R
wtv[1]
ldc[1]
wtv[0]
ldc[0]
—
00h
R/W Low-Duty Cycle Mode Dura-
tion
ldc[4]
ldc[3]
ldc[2]
1A
R/W
Low Battery Detector
Threshold
Reserved
Reserved
Reserved
lbdt[4]
lbdt[3]
lbdt[2]
lbdt[1]
lbdt[0]
14h
1B
1C
1D
R
R/W
Battery Voltage Level
IF Filter Bandwidth
0
0
0
vbat[4]
ndec[0]
vbat[3]
filset[3]
vbat[2]
filset[2]
vbat[1]
filset[1]
matap
vbat[0]
filset[0]
ph0size
—
01h
40h
dwn3_bypass
afcbd
ndec[2]
enafc
ndec[1]
afcgearh[2]
R/W AFC Loop Gearshift Over-
ride
afcgearh[1] afcgearh[0] 1p5 bypass
1E
1F
R/W
R/W
AFC Timing Control
Clock Recovery
Gearshift Override
Clock Recovery
Oversampling Ratio
Clock Recovery
Offset 2
Clock Recovery
Offset 1
Clock Recovery
Offset 0
Clock Recovery
Timing Loop Gain 1
Clock Recovery
Timing Loop Gain 0
Received Signal Strength
Indicator
swait_timer[1] swait_timer[0]
shwait[2]
crfast[2]
shwait[1]
crfast[1]
shwait[0]
crfast[0]
anwait[2]
crslow[2]
anwait[1]
crslow[1]
anwait[0]
crslow[0]
0Ah
03h
Reserved
rxosr[7]
rxosr[10]
ncoff[15]
ncoff[7]
Reserved
rxosr[6]
rxosr[9]
ncoff[14]
ncoff[6]
Reserved
crgain[6]
rssi[6]
20
21
22
23
24
25
26
27
R/W
R/W
R/W
R/W
R/W
R/W
R
rxosr[5]
rxosr[8]
ncoff[13]
ncoff[5]
Reserved
crgain[5]
rssi[5]
rxosr[4]
stallctrl
rxosr[3]
ncoff[19]
ncoff[11]
ncoff[3]
crgain2x
crgain[3]
rssi[3]
rxosr[2]
ncoff[18]
ncoff[10]
ncoff[2]
rxosr[1]
ncoff[17]
ncoff[9]
ncoff[1]
crgain[9]
crgain[1]
rssi[1]
rxosr[0]
ncoff[16]
ncoff[8]
ncoff[0]
crgain[8]
crgain[0]
rssi[0]
64h
01h
47h
AEh
02h
8Fh
—
ncoff[12]
ncoff[4]
Reserved
crgain[7]
rssi[7]
rxncocomp
crgain[4]
rssi[4]
crgain[10]
crgain[2]
rssi[2]
R/W
RSSI Threshold for Clear
Channel
rssith[7]
rssith[6]
rssith[5]
rssith[4]
rssith[3]
rssith[2]
rssith[1]
rssith[0]
1Eh
Indicator
28
29
2A
2B
2C
2D
2E
2F
R
R
Antenna Diversity Register 1
Antenna Diversity Register 2
AFC Limiter
adrssi1[7]
adrssib[7]
Afclim[7]
afc_corr[9]
afc_corr[9]
ookcnt[7]
Reserved
adrssia[6]
adrssib[6]
Afclim[6]
afc_corr[8]
afc_corr[9]
ookcnt[6]
attack[2]
adrssia[5]
adrssib[5]
Afclim[5]
afc_corr[7]
ookfrzen
ookcnt[5]
attack[1]
adrssia[4]
adrssib[4]
Afclim[4]
afc_corr[6]
peakdeten
ookcnt[4]
attack[0]
adrssia[3]
adrssib[3]
Afclim[3]
adrssia[2]
adrssib[2]
Afclim[2]
adrssia[1]
adrssib[1]
Afclim[1]
adrssia[0]
adrssib[0]
Afclim[0]
afc_corr[2]
ookcnt[8]
ookcnt[0]
decay[0]
—
—
R/W
R
R/W
R/W
R/W
00h
00h
18h
BCh
26h
AFC Correction Read
OOK Counter Value 1
OOK Counter Value 2
Slicer Peak Hold
afc_corr[5] afc_corr[4] afc_corr[3]
madeten
ookcnt[3]
decay[3]
ookcnt[10]
ookcnt[2]
decay[2]
ookcnt[9]
ookcnt[1]
decay[1]
Reserved
284
Rev. 1.0
Si1000/1/2/3/4/5
Table 23.9. EZRadioPRO Internal Register Descriptions (Continued)
Add R/W
Function/Desc
Data
D4
skip2ph
pkrx
POR
Default
D7
enpacrx
0
D6
lsbfrst
rxcrc1
D5
crcdonly
pksrch
D3
enpactx
pkvalid
D2
encrc
crcerror
D1
crc[1]
pktx
D0
crc[0]
pksent
30
31
R/W
R
Data Access Control
EzMAC status
8Dh
—
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
R/W
R/W
R/W
Header Control 1
Header Control 2
Preamble Length
bcen[3:0]
hdch[3:0]
0Ch
22h
08h
2Ah
2Dh
D4h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
FFh
FFh
FFh
FFh
—
skipsyn
prealen[7]
preath[4]
sync[31]
sync[23]
sync[15]
sync[7]
txhd[31]
txhd[23]
txhd[15]
txhd[7]
pklen[7]
chhd[31]
chhd[23]
chhd[15]
chhd[7]
hden[31]
hden[23]
hden[15]
hden[7]
rxhd[31]
rxhd[23]
rxhd[15]
rxhd[7]
hdlen[2]
prealen[6]
preath[3]
sync[30]
sync[22]
sync[14]
sync[6]
hdlen[1]
prealen[5]
preath[2]
sync[29]
sync[21]
sync[13]
sync[5]
hdlen[0]
prealen[4]
preath[1]
sync[28]
sync[20]
sync[12]
sync[4]
txhd[28]
txhd[20]
txhd[12]
txhd[4]
pklen[4]
chhd[28]
chhd[20]
chhd[12]
chhd[4]
hden[28]
hden[20]
hden[12]
hden[4]
rxhd[28]
rxhd[20]
rxhd[12]
rxhd[4]
fixpklen
prealen[3]
preath[0]
sync[27]
sync[19]
sync[11]
sync[3]
txhd[27]
txhd[19]
txhd[11]
txhd[3]
pklen[3]
chhd[27]
chhd[19]
chhd[11]
chhd[3]
hden[27]
hden[19]
hden[11]
hden[3]
rxhd[27]
rxhd[19]
rxhd[11]
rxhd[3]
synclen[1]
prealen[2]
rssi_off[2]
sync[26]
sync[18]
sync[10]
sync[2]
synclen[0]
prealen[1]
rssi_off[1]
sync[25]
sync[17]
sync[9]
prealen[8]
prealen[0]
rssi_off[0]
sync[24]
sync[16]
sync[8]
R/W Preamble Detection Control
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Sync Word 3
Sync Word 2
Sync Word 1
Sync Word 0
sync[1]
sync[0]
Transmit Header 3
Transmit Header 2
Transmit Header 1
Transmit Header 0
Transmit Packet Length
Check Header 3
Check Header 2
Check Header 1
Check Header 0
Header Enable 3
Header Enable 2
Header Enable 1
Header Enable 0
Received Header 3
Received Header 2
Received Header 1
Received Header 0
Received Packet Length
txhd[30]
txhd[22]
txhd[14]
txhd[6]
pklen[6]
chhd[30]
chhd[22]
chhd[14]
chhd[6]
hden[30]
hden[22]
hden[14]
hden[6]
rxhd[30]
rxhd[22]
rxhd[14]
rxhd[6]
txhd[29]
txhd[21]
txhd[13]
txhd[5]
pklen[5]
chhd[29]
chhd[21]
chhd[13]
chhd[5]
hden[29]
hden[21]
hden[13]
hden[5]
rxhd[29]
rxhd[21]
rxhd[13]
rxhd[5]
txhd[26]
txhd[18]
txhd[10]
txhd[2]
txhd[25]
txhd[17]
txhd[9]
txhd[24]
txhd[16]
txhd[8]
txhd[1]
txhd[0]
pklen[2]
chhd[26]
chhd[18]
chhd[10]
chhd[2]
hden[26]
hden[18]
hden[10]
hden[2]
rxhd[26]
rxhd[18]
rxhd[10]
rxhd[2]
pklen[1]
chhd[25]
chhd[17]
chhd[9]
chhd[1]
hden[25]
hden[17]
hden[9]
hden[1]
rxhd[25]
rxhd[17]
rxhd[9]
pklen[0]
chhd[24]
chhd[16]
chhd[8]
chhd[0]
hden[24]
hden[16]
hden[8]
hden[0]
rxhd[24]
rxhd[16]
rxhd[8]
45
46
47
48
R
R
R
R
—
—
—
—
49
4A
4B
4C-4E
4F
50-5F
60
rxhd[1]
rxhd[0]
rxplen[0]
rxplen[7]
rxplen[6]
rxplen[5]
rxplen[4]
rxplen[3]
rxplen[2]
rxplen[1]
Reserved
adc8[5]
Reserved
R/W
R/W
ADC8 Control
Reserved
Reserved
adc8[4]
adc8[3]
adc8[2]
adc8[1]
adc8[0]
10h
00h
Channel Filter Coefficient
Address
Inv_pre_th[3]
Inv_pre_th[2] Inv_pre_th[1] Inv_pre_th[0] chfiladd[3]
chfiladd[2]
chfiladd[1]
chfiladd[0]
61
62
Reserved
R/W
Crystal Oscillator/
Control Test
pwst[2]
pwst[1]
pwst[0]
Reserved
clkhyst
enbias2x
enamp2x
bufovr
enbuf
24h
63-6C
6D
6E
6F
70
71
72
73
74
75
R/W
R/W
R/W
TX Power
TX Data Rate 1
TX Data Rate 0
Reserved
txdr[15]
txdr[7]
Reserved
trclk[1]
fd[7]
fo[7]
Reserved
Reserved
fc[15]
Reserved
txdr[14]
txdr[6]
Reserved
trclk[0]
fd[6]
fo[6]
Reserved
sbsel
Reserved
txdr[13]
txdr[5]
Reserved
txdr[12]
txdr[4]
Ina_sw
txdr[11]
txdr[3]
manppol
eninv
fd[3]
fo[3]
Reserved
fb[3]
fc[11]
txpow[2]
txdr[10]
txdr[2]
enmaninv
fd[8]
fd[2]
fo[2]
Reserved
fb[2]
fc[10]
txpow[1]
txdr[9]
txdr[1]
enmanch
modtyp[1]
fd[1]
fo[1]
fo[9]
fb[1]
fc[9]
txpow[0]
txdr[8]
txdr[0]
enwhite
modtyp[0]
fd[0]
fo[0]
fo[8]
fb[0]
fc[8]
18h
0Ah
3Dh
0Ch
00h
20h
00h
00h
75h
BBh
R/W Modulation Mode Control 1
R/W Modulation Mode Control 2
R/W
R/W
R/W
R/W
txdtrtscale
dtmod[1]
fd[5]
enphpwdn
dtmod[0]
fd[4]
Frequency Deviation
Frequency Offset 1
Frequency Offset 2
Frequency Band Select
fo[5]
fo[4]
Reserved
hbsel
Reserved
fb[4]
76
R/W Nominal Carrier Frequency
fc[14]
fc[13]
fc[12]
1
77
R/W Nominal Carrier Frequency
0
fc[7]
fc[6]
fc[5]
fc[4]
fc[3]
fc[2]
fc[1]
fc[0]
80h
78
79
Reserved
fhch[5]
R/W Frequency Hopping Chan-
nel Select
fhch[7]
fhs[7]
fhch[6]
fhs[6]
fhch[4]
fhs[4]
fhch[3]
fhs[3]
fhch[2]
fhs[2]
fhch[1]
fhs[1]
fhch[0]
fhs[0]
00h
00h
7A
R/W
Frequency Hopping Step
Size
fhs[5]
7B
7C
7D
7E
7F
Reserved
R/W
R/W
R/W
R/W
TX FIFO Control 1
TX FIFO Control 2
RX FIFO Control
FIFO Access
Reserved
Reserved
Reserved
fifod[7]
Reserved
Reserved
Reserved
fifod[6]
txafthr[5]
txaethr[5]
rxafthr[5]
fifod[5]
txafthr[4]
txaethr[4]
rxafthr[4]
fifod[4]
txafthr[3]
txaethr[3]
rxafthr[3]
fifod[3]
txafthr[2]
txaethr[2]
rxafthr[2]
fifod[2]
txafthr[1]
txaethr[1]
rxafthr[1]
fifod[1]
txafthr[0]
txaethr[0]
rxafthr[0]
fifod[0]
37h
04h
37h
—
Note: Detailed register descriptions are available in “AN440: EZRadioPRO Detailed Register Descriptions.
Rev. 1.0
285
Si1000/1/2/3/4/5
23.13. Required Changes to Default Register Values
The following register writes should be performed during device initialization.
1. The value 0x40 should be written to Register 59h.
2. If the device will be operated in the 240–320 MHz or 480–640 MHz bands at a temperature above
60 °C, then Register 59h should be written to 0x43 and Register 5Ah should be written to 0x02.
286
Rev. 1.0
Si1000/1/2/3/4/5
24. SMBus
The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System
2
Management Bus Specification, version 1.1, and compatible with the I C serial bus. Reads and writes to
the interface by the system controller are byte oriented with the SMBus interface autonomously controlling
the serial transfer of the data. Data can be transferred at up to 1/20th of the system clock as a master or
slave (this can be faster than allowed by the SMBus specification, depending on the system clock used). A
method of extending the clock-low duration is available to accommodate devices with different speed
capabilities on the same bus.
The SMBus interface may operate as a master and/or slave, and may function on a bus with multiple mas-
ters. The SMBus provides control of SDA (serial data), SCL (serial clock) generation and synchronization,
arbitration logic, and START/STOP control and generation. The SMBus peripheral can be fully driven by
software (i.e., software accepts/rejects slave addresses, and generates ACKs), or hardware slave address
recognition and automatic ACK generation can be enabled to minimize software overhead. A block dia-
gram of the SMBus peripheral and the associated SFRs is shown in Figure 24.1.
SMB0CN
SMB0CF
M T S S A A A S
E
I
B E S S S S
A X T T C R C
S M A O K B K
I
N N U X M M M M
S H S T B B B B
T O
E D
R E
R L
Q O
S
M
B
Y H T F C C
O O T S S
L E E 1 0
D
T
00
01
10
11
T0 Overflow
T1 Overflow
TMR2H Overflow
TMR2L Overflow
SCL
SMBUS CONTROL LOGIC
Arbitration
FILTER
Interrupt
Request
SCL Synchronization
SCL Generation (Master Mode)
SDA Control
SCL
Control
C
R
O
S
S
B
A
R
N
Hardware Slave Address Recognition
Hardware ACK Generation
Port I/O
Data Path
SDA
Control
IRQ Generation
Control
SMB0DAT
7 6 5 4 3 2 1 0
SDA
FILTER
S S S S S S S G S S S S S S S E
L L L L L L L C L L L L L L L H
V V V V V V V
6 5 4 3 2 1 0
V V V V V V V A
M M M M M M M C
6 5 4 3 2 1 0 K
SMB0ADR
SMB0ADM
N
Figure 24.1. SMBus Block Diagram
Rev. 1.0
287
Si1000/1/2/3/4/5
24.1. Supporting Documents
It is assumed the reader is familiar with or has access to the following supporting documents:
2
1. The I C-Bus and How to Use It (including specifications), Philips Semiconductor.
2
2. The I C-Bus Specification—Version 2.0, Philips Semiconductor.
3. System Management Bus Specification—Version 1.1, SBS Implementers Forum.
24.2. SMBus Configuration
Figure 24.2 shows a typical SMBus configuration. The SMBus specification allows any recessive voltage
between 3.0 V and 5.0 V; different devices on the bus may operate at different voltage levels. The bi-direc-
tional SCL (serial clock) and SDA (serial data) lines must be connected to a positive power supply voltage
through a pullup resistor or similar circuit. Every device connected to the bus must have an open-drain or
open-collector output for both the SCL and SDA lines, so that both are pulled high (recessive state) when
the bus is free. The maximum number of devices on the bus is limited only by the requirement that the rise
and fall times on the bus not exceed 300 ns and 1000 ns, respectively.
VDD = 5V
VDD = 3V
VDD = 5V
VDD = 3V
Master
Device
Slave
Device 1
Slave
Device 2
SDA
SCL
Figure 24.2. Typical SMBus Configuration
24.3. SMBus Operation
Two types of data transfers are possible: data transfers from a master transmitter to an addressed slave
receiver (WRITE), and data transfers from an addressed slave transmitter to a master receiver (READ).
The master device initiates both types of data transfers and provides the serial clock pulses on SCL. The
SMBus interface may operate as a master or a slave, and multiple master devices on the same bus are
supported. If two or more masters attempt to initiate a data transfer simultaneously, an arbitration scheme
is employed with a single master always winning the arbitration. Note that it is not necessary to specify one
device as the Master in a system; any device who transmits a START and a slave address becomes the
master for the duration of that transfer.
A typical SMBus transaction consists of a START condition followed by an address byte (Bits7–1: 7-bit
slave address; Bit0: R/W direction bit), one or more bytes of data, and a STOP condition. Bytes that are
received (by a master or slave) are acknowledged (ACK) with a low SDA during a high SCL (see
Figure 24.3). If the receiving device does not ACK, the transmitting device will read a NACK (not acknowl-
edge), which is a high SDA during a high SCL.
The direction bit (R/W) occupies the least-significant bit position of the address byte. The direction bit is set
to logic 1 to indicate a "READ" operation and cleared to logic 0 to indicate a "WRITE" operation.
288
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All transactions are initiated by a master, with one or more addressed slave devices as the target. The
master generates the START condition and then transmits the slave address and direction bit. If the trans-
action is a WRITE operation from the master to the slave, the master transmits the data a byte at a time
waiting for an ACK from the slave at the end of each byte. For READ operations, the slave transmits the
data waiting for an ACK from the master at the end of each byte. At the end of the data transfer, the master
generates a STOP condition to terminate the transaction and free the bus. Figure 24.3 illustrates a typical
SMBus transaction.
SCL
SDA
SLA6
SLA5-0
R/W
D7
D6-0
START
Slave Address + R/W
ACK
Data Byte
NACK
STOP
Figure 24.3. SMBus Transaction
24.3.1. Transmitter vs. Receiver
On the SMBus communications interface, a device is the “transmitter” when it is sending an address or
data byte to another device on the bus. A device is a “receiver” when an address or data byte is being sent
to it from another device on the bus. The transmitter controls the SDA line during the address or data byte.
After each byte of address or data information is sent by the transmitter, the receiver sends an ACK or
NACK bit during the ACK phase of the transfer, during which time the receiver controls the SDA line.
24.3.2. Arbitration
A master may start a transfer only if the bus is free. The bus is free after a STOP condition or after the SCL
and SDA lines remain high for a specified time (see Section “24.3.5. SCL High (SMBus Free) Timeout” on
page 290). In the event that two or more devices attempt to begin a transfer at the same time, an arbitra-
tion scheme is employed to force one master to give up the bus. The master devices continue transmitting
until one attempts a HIGH while the other transmits a LOW. Since the bus is open-drain, the bus will be
pulled LOW. The master attempting the HIGH will detect a LOW SDA and lose the arbitration. The winning
master continues its transmission without interruption; the losing master becomes a slave and receives the
rest of the transfer if addressed. This arbitration scheme is non-destructive: one device always wins, and
no data is lost.
24.3.3. Clock Low Extension
2
SMBus provides a clock synchronization mechanism, similar to I C, which allows devices with different
speed capabilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow
slower slave devices to communicate with faster masters. The slave may temporarily hold the SCL line
LOW to extend the clock low period, effectively decreasing the serial clock frequency.
24.3.4. SCL Low Timeout
If the SCL line is held low by a slave device on the bus, no further communication is possible. Furthermore,
the master cannot force the SCL line high to correct the error condition. To solve this problem, the SMBus
protocol specifies that devices participating in a transfer must detect any clock cycle held low longer than
25 ms as a “timeout” condition. Devices that have detected the timeout condition must reset the communi-
cation no later than 10 ms after detecting the timeout condition.
When the SMBTOE bit in SMB0CF is set, Timer 3 is used to detect SCL low timeouts. Timer 3 is forced to
reload when SCL is high, and allowed to count when SCL is low. With Timer 3 enabled and configured to
Rev. 1.0
289
Si1000/1/2/3/4/5
overflow after 25 ms (and SMBTOE set), the Timer 3 interrupt service routine can be used to reset (disable
and re-enable) the SMBus in the event of an SCL low timeout.
24.3.5. SCL High (SMBus Free) Timeout
The SMBus specification stipulates that if the SCL and SDA lines remain high for more that 50 µs, the bus
is designated as free. When the SMBFTE bit in SMB0CF is set, the bus will be considered free if SCL and
SDA remain high for more than 10 SMBus clock source periods (as defined by the timer configured for the
SMBus clock source). If the SMBus is waiting to generate a Master START, the START will be generated
following this timeout. Note that a clock source is required for free timeout detection, even in a slave-only
implementation.
24.4. Using the SMBus
The SMBus can operate in both Master and Slave modes. The interface provides timing and shifting con-
trol for serial transfers; higher level protocol is determined by user software. The SMBus interface provides
the following application-independent features:
Byte-wise serial data transfers
Clock signal generation on SCL (Master Mode only) and SDA data synchronization
Timeout/bus error recognition, as defined by the SMB0CF configuration register
START/STOP timing, detection, and generation
Bus arbitration
Interrupt generation
Status information
Optional hardware recognition of slave address and automatic acknowledgement of address/data
SMBus interrupts are generated for each data byte or slave address that is transferred. When hardware
acknowledgement is disabled, the point at which the interrupt is generated depends on whether the hard-
ware is acting as a data transmitter or receiver. When a transmitter (i.e. sending address/data, receiving an
ACK), this interrupt is generated after the ACK cycle so that software may read the received ACK value;
when receiving data (i.e. receiving address/data, sending an ACK), this interrupt is generated before the
ACK cycle so that software may define the outgoing ACK value. If hardware acknowledgement is enabled,
these interrupts are always generated after the ACK cycle. See Section 24.5 for more details on transmis-
sion sequences.
Interrupts are also generated to indicate the beginning of a transfer when a master (START generated), or
the end of a transfer when a slave (STOP detected). Software should read the SMB0CN (SMBus Control
register) to find the cause of the SMBus interrupt. The SMB0CN register is described in Section 24.4.2;
Table 24.5 provides a quick SMB0CN decoding reference.
24.4.1. SMBus Configuration Register
The SMBus Configuration register (SMB0CF) is used to enable the SMBus Master and/or Slave modes,
select the SMBus clock source, and select the SMBus timing and timeout options. When the ENSMB bit is
set, the SMBus is enabled for all master and slave events. Slave events may be disabled by setting the
INH bit. With slave events inhibited, the SMBus interface will still monitor the SCL and SDA pins; however,
the interface will NACK all received addresses and will not generate any slave interrupts. When the INH bit
is set, all slave events will be inhibited following the next START (interrupts will continue for the duration of
the current transfer).
290
Rev. 1.0
Si1000/1/2/3/4/5
Table 24.1. SMBus Clock Source Selection
SMBCS1 SMBCS0 SMBus Clock Source
0
0
1
1
0
1
0
1
Timer 0 Overflow
Timer 1 Overflow
Timer 2 High Byte Overflow
Timer 2 Low Byte Overflow
The SMBCS1–0 bits select the SMBus clock source, which is used only when operating as a master or
when the Free Timeout detection is enabled. When operating as a master, overflows from the selected
source determine the absolute minimum SCL low and high times as defined in Equation 24.1. Note that the
selected clock source may be shared by other peripherals so long as the timer is left running at all times.
For example, Timer 1 overflows may generate the SMBus and UART baud rates simultaneously. Timer
configuration is covered in Section “27. Timers” on page 330.
1
THighMin = TLowMin = ---------------------------------------------
fClockSourceOverflow
Equation 24.1. Minimum SCL High and Low Times
The selected clock source should be configured to establish the minimum SCL High and Low times as per
Equation 24.1. When the interface is operating as a master (and SCL is not driven or extended by any
other devices on the bus), the typical SMBus bit rate is approximated by Equation 24.2.
fClockSourceOverflow
BitRate = ---------------------------------------------
3
Equation 24.2. Typical SMBus Bit Rate
Figure 24.4 shows the typical SCL generation described by Equation 24.2. Notice that T
is typically
HIGH
twice as large as T
. The actual SCL output may vary due to other devices on the bus (SCL may be
LOW
extended low by slower slave devices, or driven low by contending master devices). The bit rate when
operating as a master will never exceed the limits defined by equation Equation 24.1.
Timer Source
Overflows
SCL
TLow
THigh
SCL High Timeout
Figure 24.4. Typical SMBus SCL Generation
Setting the EXTHOLD bit extends the minimum setup and hold times for the SDA line. The minimum SDA
setup time defines the absolute minimum time that SDA is stable before SCL transitions from low-to-high.
The minimum SDA hold time defines the absolute minimum time that the current SDA value remains stable
after SCL transitions from high-to-low. EXTHOLD should be set so that the minimum setup and hold times
meet the SMBus Specification requirements of 250 ns and 300 ns, respectively. Table 24.2 shows the min-
Rev. 1.0
291
Si1000/1/2/3/4/5
imum setup and hold times for the two EXTHOLD settings. Setup and hold time extensions are typically
necessary when SYSCLK is above 10 MHz.
Table 24.2. Minimum SDA Setup and Hold Times
EXTHOLD
Minimum SDA Setup Time
– 4 system clocks
Minimum SDA Hold Time
0
T
3 system clocks
low
or
1 system clock + s/w delay*
11 system clocks
1
12 system clocks
Note: Setup Time for ACK bit transmissions and the MSB of all data transfers. When using
software acknowledgement, the s/w delay occurs between the time SMB0DAT or
ACK is written and when SI is cleared. Note that if SI is cleared in the same write
that defines the outgoing ACK value, s/w delay is zero.
With the SMBTOE bit set, Timer 3 should be configured to overflow after 25 ms in order to detect SCL low
timeouts (see Section “24.3.4. SCL Low Timeout” on page 289). The SMBus interface will force Timer 3 to
reload while SCL is high, and allow Timer 3 to count when SCL is low. The Timer 3 interrupt service routine
should be used to reset SMBus communication by disabling and re-enabling the SMBus.
SMBus Free Timeout detection can be enabled by setting the SMBFTE bit. When this bit is set, the bus will
be considered free if SDA and SCL remain high for more than 10 SMBus clock source periods (see
Figure 24.4).
292
Rev. 1.0
Si1000/1/2/3/4/5
SFR Definition 24.1. SMB0CF: SMBus Clock/Configuration
Bit
7
6
5
4
3
2
1
0
ENSMB
INH
BUSY
EXTHOLD SMBTOE SMBFTE
SMBCS[1:0]
R/W
Name
Type
Reset
R/W
0
R/W
0
R
0
R/W
0
R/W
0
R/W
0
0
0
SFR Page = 0x0; SFR Address = 0xC1
Bit
Name
Function
7
ENSMB
SMBus Enable.
This bit enables the SMBus interface when set to 1. When enabled, the interface
constantly monitors the SDA and SCL pins.
6
INH
SMBus Slave Inhibit.
When this bit is set to logic 1, the SMBus does not generate an interrupt when slave
events occur. This effectively removes the SMBus slave from the bus. Master Mode
interrupts are not affected.
5
4
BUSY
SMBus Busy Indicator.
This bit is set to logic 1 by hardware when a transfer is in progress. It is cleared to
logic 0 when a STOP or free-timeout is sensed.
EXTHOLD
SMBus Setup and Hold Time Extension Enable.
This bit controls the SDA setup and hold times according to Table 24.2.
0: SDA Extended Setup and Hold Times disabled.
1: SDA Extended Setup and Hold Times enabled.
3
SMBTOE
SMBus SCL Timeout Detection Enable.
This bit enables SCL low timeout detection. If set to logic 1, the SMBus forces
Timer 3 to reload while SCL is high and allows Timer 3 to count when SCL goes low.
If Timer 3 is configured to Split Mode, only the High Byte of the timer is held in reload
while SCL is high. Timer 3 should be programmed to generate interrupts at 25 ms,
and the Timer 3 interrupt service routine should reset SMBus communication.
2
SMBFTE
SMBus Free Timeout Detection Enable.
When this bit is set to logic 1, the bus will be considered free if SCL and SDA remain
high for more than 10 SMBus clock source periods.
1:0 SMBCS[1:0]
SMBus Clock Source Selection.
These two bits select the SMBus clock source, which is used to generate the SMBus
bit rate. The selected device should be configured according to Equation 24.1.
00: Timer 0 Overflow
01: Timer 1 Overflow
10:Timer 2 High Byte Overflow
11: Timer 2 Low Byte Overflow
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24.4.2. SMB0CN Control Register
SMB0CN is used to control the interface and to provide status information (see SFR Definition 24.2). The
higher four bits of SMB0CN (MASTER, TXMODE, STA, and STO) form a status vector that can be used to
jump to service routines. MASTER indicates whether a device is the master or slave during the current
transfer. TXMODE indicates whether the device is transmitting or receiving data for the current byte.
STA and STO indicate that a START and/or STOP has been detected or generated since the last SMBus
interrupt. STA and STO are also used to generate START and STOP conditions when operating as a mas-
ter. Writing a 1 to STA will cause the SMBus interface to enter Master Mode and generate a START when
the bus becomes free (STA is not cleared by hardware after the START is generated). Writing a 1 to STO
while in Master Mode will cause the interface to generate a STOP and end the current transfer after the
next ACK cycle. If STO and STA are both set (while in Master Mode), a STOP followed by a START will be
generated.
The ARBLOST bit indicates that the interface has lost an arbitration. This may occur anytime the interface
is transmitting (master or slave). A lost arbitration while operating as a slave indicates a bus error condi-
tion. ARBLOST is cleared by hardware each time SI is cleared.
The SI bit (SMBus Interrupt Flag) is set at the beginning and end of each transfer, after each byte frame, or
when an arbitration is lost; see Table 24.3 for more details.
Important Note About the SI Bit: The SMBus interface is stalled while SI is set; thus SCL is held low, and
the bus is stalled until software clears SI.
24.4.2.1. Software ACK Generation
When the EHACK bit in register SMB0ADM is cleared to 0, the firmware on the device must detect incom-
ing slave addresses and ACK or NACK the slave address and incoming data bytes. As a receiver, writing
the ACK bit defines the outgoing ACK value; as a transmitter, reading the ACK bit indicates the value
received during the last ACK cycle. ACKRQ is set each time a byte is received, indicating that an outgoing
ACK value is needed. When ACKRQ is set, software should write the desired outgoing value to the ACK
bit before clearing SI. A NACK will be generated if software does not write the ACK bit before clearing SI.
SDA will reflect the defined ACK value immediately following a write to the ACK bit; however SCL will
remain low until SI is cleared. If a received slave address is not acknowledged, further slave events will be
ignored until the next START is detected.
24.4.2.2. Hardware ACK Generation
When the EHACK bit in register SMB0ADM is set to 1, automatic slave address recognition and ACK gen-
eration is enabled. More detail about automatic slave address recognition can be found in Section 24.4.3.
As a receiver, the value currently specified by the ACK bit will be automatically sent on the bus during the
ACK cycle of an incoming data byte. As a transmitter, reading the ACK bit indicates the value received on
the last ACK cycle. The ACKRQ bit is not used when hardware ACK generation is enabled. If a received
slave address is NACKed by hardware, further slave events will be ignored until the next START is
detected, and no interrupt will be generated.
Table 24.3 lists all sources for hardware changes to the SMB0CN bits. Refer to Table 24.5 for SMBus sta-
tus decoding using the SMB0CN register.
Refer to “Limitations for Hardware Acknowledge Feature” on page 299 when using hardware ACK genera-
tion.
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SFR Definition 24.2. SMB0CN: SMBus Control
Bit
7
6
5
4
3
2
1
0
MASTER TXMODE
STA
STO
ACKRQ ARBLOST
ACK
SI
Name
Type
Reset
R
0
R
0
R/W
0
R/W
0
R
0
R
0
R/W
0
R/W
0
SFR Page = 0x0; SFR Address = 0xC0; Bit-Addressable
Bit
Name
Description
Read
Write
7
MASTER SMBus Master/Slave
Indicator. This read-only bit
indicates when the SMBus is
operating as a master.
0: SMBus operating in
slave mode.
1: SMBus operating in
master mode.
N/A
N/A
6
5
4
TXMODE SMBus Transmit Mode
Indicator. This read-only bit
indicates when the SMBus is
operating as a transmitter.
0: SMBus in Receiver
Mode.
1: SMBus in Transmitter
Mode.
STA
SMBus Start Flag.
0: No Start or repeated
Start detected.
1: Start or repeated Start
detected.
0: No Start generated.
1: When Configured as a
Master, initiates a START
or repeated START.
STO
SMBus Stop Flag.
0: No Stop condition
detected.
0: No STOP condition is
transmitted.
1: Stop condition detected 1: When configured as a
(if in Slave Mode) or pend- Master, causes a STOP
ing (if in Master Mode).
condition to be transmit-
ted after the next ACK
cycle.
Cleared by Hardware.
3
2
1
ACKRQ SMBus Acknowledge
0: No Ack requested
1: ACK requested
N/A
Request.
ARBLOST SMBus Arbitration Lost
0: No arbitration error.
1: Arbitration Lost
N/A
Indicator.
ACK
SI
SMBus Acknowledge.
0: NACK received.
1: ACK received.
0: Send NACK
1: Send ACK
0
SMBus Interrupt Flag.
0: No interrupt pending 0: Clear interrupt, and initi-
ate next state machine
event.
1: Force interrupt.
This bit is set by hardware
under the conditions listed in
Table 15.3. SI must be cleared
by software. While SI is set,
SCL is held low and the
SMBus is stalled.
1: Interrupt Pending
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Table 24.3. Sources for Hardware Changes to SMB0CN
Bit
Set by Hardware When:
Cleared by Hardware When:
MASTER
A START is generated.
A STOP is generated.
Arbitration is lost.
A START is detected.
Arbitration is lost.
TXMODE
START is generated.
SMB0DAT is written before the start of an
SMBus frame.
SMB0DAT is not written before the
start of an SMBus frame.
STA
STO
A START followed by an address byte is
received.
A STOP is detected while addressed as a
slave.
Must be cleared by software.
A pending STOP is generated.
Arbitration is lost due to a detected STOP.
A byte has been received and an ACK
response value is needed (only when
hardware ACK is not enabled).
A repeated START is detected as a
MASTER when STA is low (unwanted
repeated START).
ACKRQ
After each ACK cycle.
Each time SI is cleared.
ARBLOST
SCL is sensed low while attempting to
generate a STOP or repeated START
condition.
SDA is sensed low while transmitting a 1
(excluding ACK bits).
The incoming ACK value is low
(ACKNOWLEDGE).
ACK
SI
The incoming ACK value is high
(NOT ACKNOWLEDGE).
Must be cleared by software.
A START has been generated.
Lost arbitration.
A byte has been transmitted and an
ACK/NACK received.
A byte has been received.
A START or repeated START followed by a
slave address + R/W has been received.
A STOP has been received.
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24.4.3. Hardware Slave Address Recognition
The SMBus hardware has the capability to automatically recognize incoming slave addresses and send an
ACK without software intervention. Automatic slave address recognition is enabled by setting the EHACK
bit in register SMB0ADM to 1. This will enable both automatic slave address recognition and automatic
hardware ACK generation for received bytes (as a master or slave). More detail on automatic hardware
ACK generation can be found in Section 24.4.2.2.
The registers used to define which address(es) are recognized by the hardware are the SMBus Slave
Address register (SFR Definition 24.3) and the SMBus Slave Address Mask register (SFR Definition 24.4).
A single address or range of addresses (including the General Call Address 0x00) can be specified using
these two registers. The most-significant seven bits of the two registers are used to define which
addresses will be ACKed. A 1 in bit positions of the slave address mask SLVM[6:0] enable a comparison
between the received slave address and the hardware’s slave address SLV[6:0] for those bits. A 0 in a bit
of the slave address mask means that bit will be treated as a “don’t care” for comparison purposes. In this
case, either a 1 or a 0 value are acceptable on the incoming slave address. Additionally, if the GC bit in
register SMB0ADR is set to 1, hardware will recognize the General Call Address (0x00). Table 24.4 shows
some example parameter settings and the slave addresses that will be recognized by hardware under
those conditions. Refer to “Limitations for Hardware Acknowledge Feature” on page 299 when using hard-
ware slave address recognition.
Table 24.4. Hardware Address Recognition Examples (EHACK = 1)
Hardware Slave Address Slave Address Mask
GC bit Slave Addresses Recognized by
Hardware
SLV[6:0]
SLVM[6:0]
0x34
0x34
0x34
0x34
0x70
0x7F
0x7F
0x7E
0x7E
0x73
0
1
0
1
0
0x34
0x34, 0x00 (General Call)
0x34, 0x35
0x34, 0x35, 0x00 (General Call)
0x70, 0x74, 0x78, 0x7C
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SFR Definition 24.3. SMB0ADR: SMBus Slave Address
Bit
7
6
5
4
3
2
1
0
SLV[6:0]
GC
Name
Type
Reset
R/W
0
R/W
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xF4
Bit
Name
Function
7:1
SLV[6:0]
SMBus Hardware Slave Address.
Defines the SMBus Slave Address(es) for automatic hardware acknowledgement.
Only address bits which have a 1 in the corresponding bit position in SLVM[6:0]
are checked against the incoming address. This allows multiple addresses to be
recognized.
0
GC
General Call Address Enable.
When hardware address recognition is enabled (EHACK = 1), this bit will deter-
mine whether the General Call Address (0x00) is also recognized by hardware.
0: General Call Address is ignored.
1: General Call Address is recognized.
SFR Definition 24.4. SMB0ADM: SMBus Slave Address Mask
Bit
7
6
5
4
3
2
1
0
SLVM[6:0]
EHACK
Name
Type
Reset
R/W
1
R/W
0
1
1
1
1
1
1
SFR Page = 0x0; SFR Address = 0xF5
Bit
Name
Function
7:1
SLVM[6:0]
SMBus Slave Address Mask.
Defines which bits of register SMB0ADR are compared with an incoming address
byte, and which bits are ignored. Any bit set to 1 in SLVM[6:0] enables compari-
sons with the corresponding bit in SLV[6:0]. Bits set to 0 are ignored (can be either
0 or 1 in the incoming address).
0
EHACK
Hardware Acknowledge Enable.
Enables hardware acknowledgement of slave address and received data bytes.
0: Firmware must manually acknowledge all incoming address and data bytes.
1: Automatic Slave Address Recognition and Hardware Acknowledge is Enabled.
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24.4.4. Limitations for Hardware Acknowledge Feature
In some system management bus (SMBus) configurations, the Hardware Acknowledge mechanism of the
SMBus peripheral can cause incorrect or undesired behavior. The Hardware Acknowledge mechanism is
enabled when the EHACK bit (SMB0ADM.0) is set to logic 1.
The configurations to which these limitations do not apply are as follows:
a. All SMBus configurations when Hardware Acknowledge is disabled.
b. All single-master/single-slave SMBus configurations when Hardware Acknowledge is enabled
and the MCU is operating as a master or slave.
c. All multi-master/single-slave SMBus configurations when Hardware Acknowledge is enabled
and the MCU is operating as a slave.
d. All single-master/multi-slave SMBus configurations when Hardware Acknowledge is enabled
and the MCU is operating as a master.
These limitations only apply to the following configurations:
a. All multi-slave SMBus configurations when Hardware Acknowledge is enabled and the MCU is
operating as a slave.
b. All multi-master SMBus configurations when Hardware Acknowledge is enabled and the MCU
is operating as a master.
The following issues are present when operating as a slave in a multi-slave SMBus configuration:
a. When Hardware Acknowledge is enabled and SDA setup and hold times are not extended
(EXTHOLD = 0 in the SMB0CF register), the SMBus hardware will always generate an SMBus
interrupt following the ACK/NACK cycle of any slave address transmission on the bus, whether
or not the address matches the conditions of SMB0ADR and SMB0MASK. The expected
behavior is that an interrupt is only generated when the address matches.
b. When Hardware Acknowledge is enabled and SDA setup and hold times are extended
(EXTHOLD = 1 in the SMB0CF register), the SMBus hardware will only generate an SMBus
interrupt as expected when the slave address transmission on the bus matches the conditions of
SMB0ADR and SMB0MASK. However, in this mode, the Start bit (STA) will be incorrectly
cleared on reception of a slave address before software vectors to the interrupt service routine.
c. When Hardware Acknowledge is enabled and the ACK bit (SMB0CN.1) is set to 1, an
unaddressed slave may cause interference on the SMBus by driving SDA low during an ACK
cycle. The ACK bit of the unaddressed slave may be set to 1 if any device on the bus generates
an ACK.
Impact:
a. Once the CPU enters the interrupt service routine, SCL will be asserted low until SI is cleared,
causing the clock to be stretched when the MCU is not being addressed. This may limit the
maximum speed of the SMBus if the master supports SCL clock stretching. Incompliant SMBus
masters that do not support SCL clock stretching will not recognize that the clock is being
stretched. If the CPU issues a write to SMB0DAT, it will have no effect on the bus. No data
collisions will occur.
b. Once the hardware has matched an address and entered the interrupt service routine, the
firmware will not be able to use the Start bit to distinguish between the reception of an address
byte versus the reception of a data byte. However, the hardware will still correctly acknowledge
the address byte (SLA+R/W).
c. The SMBus master and the addressed slave are prevented from generating a NACK by the
unaddressed slave because it is holding SDA low during the ACK cycle. There is a potential for
the SMBus to lock up.
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Workarounds:
a. The SMBus interrupt service routine should verify an address when it is received and clear SI as
soon as possible if the address does not match to minimize clock stretching. To prevent clock
stretching when not being addressed, enable setup and hold time extensions (EXTHOLD = 1).
b. Detection of Initial Start:
To distinguish between the reception of an address byte at the beginning of a transfer versus
the reception of a data byte when setup and hold time extensions are enabled (EXTHOLD = 1),
software should maintain a status bit to determine whether it is currently inside or outside a
transfer. Once hardware detects a matching slave address and interrupts the MCU, software
should assume a start condition and set the software bit to indicate that it is currently inside a
transfer. A transfer ends any time the STO bit is set or on an error condition (e.g., SCL Low
Timeout).
Detection of Repeated Start:
To detect the reception of an address byte in the middle of a transfer when setup and hold time
extensions are enabled (EXTHOLD = 1), disable setup and hold time extensions (EXTHOLD =
0) upon entry into a transfer and re-enable setup and hold time extensions (EXHOLD = 1) at the
end of a transfer.
c. Schedule a timer interrupt to clear the ACK bit at an interval shorter than 7 bit periods when the
slave is not being addressed. For example, on a 400 kHz SMBus, the ACK bit should be cleared
every 17.5 µs (or at 1/7 the bus frequency, 57 kHz). As soon as a matching slave address is
detected (a transfer is started), the timer which clears the ACK bit should be stopped and its
interrupt flag cleared. The timer should be re-started once a stop or error condition is detected
(the transfer has ended).
A code example demonstrating these workarounds can be found in the SMBus examples folder with the
following default location:
C:\SiLabs\MCU\Examples\C8051F93x_92x\SMBus\F93x_SMBus_Slave_Multibyte_HWACK.c
The SMBus examples folder, along with examples for many additional peripherals, is created when the Sil-
icon Laboratories IDE is installed. The latest version of the IDE may be downloaded from the software
downloads page www.silabs.com/MCUDownloads on the Silicon Laboratories website.
The following issue is present when operating as a master in a multi-master SMBus configuration:
If the SMBus master loses arbitration in a multi-master system, it may cause interference on the SMBus by
driving SDA low during the ACK cycle of transfers which it is not participating. This will occur regardless of
the state of the ACK bit (SMB0CN.1).
Impact:
The SMBus master and slave participating in the transfer are prevented from generating a NACK by the
MCU because it is holding SDA low during the ACK cycle. There is a potential for the SMBus to lock up.
Workaround:
Disable Hardware Acknowledge (EHACK = 0) when the MCU is operating as a master in a multi-master
SMBus configuration.
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24.4.5. Data Register
The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been
received. Software may safely read or write to the data register when the SI flag is set. Software should not
attempt to access the SMB0DAT register when the SMBus is enabled and the SI flag is cleared to logic 0,
as the interface may be in the process of shifting a byte of data into or out of the register.
Data in SMB0DAT is always shifted out MSB first. After a byte has been received, the first bit of received
data is located at the MSB of SMB0DAT. While data is being shifted out, data on the bus is simultaneously
being shifted in. SMB0DAT always contains the last data byte present on the bus. In the event of lost arbi-
tration, the transition from master transmitter to slave receiver is made with the correct data or address in
SMB0DAT.
SFR Definition 24.5. SMB0DAT: SMBus Data
Bit
7
6
5
4
3
2
1
0
SMB0DAT[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xC2
Bit Name
7:0 SMB0DAT[7:0] SMBus Data.
Function
The SMB0DAT register contains a byte of data to be transmitted on the SMBus
serial interface or a byte that has just been received on the SMBus serial interface.
The CPU can read from or write to this register whenever the SI serial interrupt flag
(SMB0CN.0) is set to logic 1. The serial data in the register remains stable as long
as the SI flag is set. When the SI flag is not set, the system may be in the process
of shifting data in/out and the CPU should not attempt to access this register.
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24.5. SMBus Transfer Modes
The SMBus interface may be configured to operate as master and/or slave. At any particular time, it will be
operating in one of the following four modes: Master Transmitter, Master Receiver, Slave Transmitter, or
Slave Receiver. The SMBus interface enters Master Mode any time a START is generated, and remains in
Master Mode until it loses an arbitration or generates a STOP. An SMBus interrupt is generated at the end
of all SMBus byte frames. Note that the position of the ACK interrupt when operating as a receiver
depends on whether hardware ACK generation is enabled. As a receiver, the interrupt for an ACK occurs
before the ACK with hardware ACK generation disabled, and after the ACK when hardware ACK genera-
tion is enabled. As a transmitter, interrupts occur after the ACK, regardless of whether hardware ACK gen-
eration is enabled or not.
24.5.1. Write Sequence (Master)
During a write sequence, an SMBus master writes data to a slave device. The master in this transfer will be
a transmitter during the address byte, and a transmitter during all data bytes. The SMBus interface gener-
ates the START condition and transmits the first byte containing the address of the target slave and the
data direction bit. In this case the data direction bit (R/W) will be logic 0 (WRITE). The master then trans-
mits one or more bytes of serial data. After each byte is transmitted, an acknowledge bit is generated by
the slave. The transfer is ended when the STO bit is set and a STOP is generated. Note that the interface
will switch to Master Receiver Mode if SMB0DAT is not written following a Master Transmitter interrupt.
Figure 24.5 shows a typical master write sequence. Two transmit data bytes are shown, though any num-
ber of bytes may be transmitted. Notice that all of the ‘data byte transferred’ interrupts occur after the ACK
cycle in this mode, regardless of whether hardware ACK generation is enabled.
Interrupts with Hardware ACK Enabled (EHACK = 1)
S
SLA
W
A
Data Byte
A
Data Byte
A
P
Interrupts with Hardware ACK Disabled (EHACK = 0)
S = START
P = STOP
A = ACK
Received by SMBus
Interface
W = WRITE
Transmitted by
SLA = Slave Address
SMBus Interface
Figure 24.5. Typical Master Write Sequence
24.5.2. Read Sequence (Master)
During a read sequence, an SMBus master reads data from a slave device. The master in this transfer will
be a transmitter during the address byte, and a receiver during all data bytes. The SMBus interface gener-
ates the START condition and transmits the first byte containing the address of the target slave and the
data direction bit. In this case the data direction bit (R/W) will be logic 1 (READ). Serial data is then
received from the slave on SDA while the SMBus outputs the serial clock. The slave transmits one or more
bytes of serial data.
If hardware ACK generation is disabled, the ACKRQ is set to 1 and an interrupt is generated after each
received byte. Software must write the ACK bit at that time to ACK or NACK the received byte.
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With hardware ACK generation enabled, the SMBus hardware will automatically generate the ACK/NACK,
and then post the interrupt. It is important to note that the appropriate ACK or NACK value should be
set up by the software prior to receiving the byte when hardware ACK generation is enabled.
Writing a 1 to the ACK bit generates an ACK; writing a 0 generates a NACK. Software should write a 0 to
the ACK bit for the last data transfer, to transmit a NACK. The interface exits Master Receiver Mode after
the STO bit is set and a STOP is generated. The interface will switch to Master Transmitter Mode if
SMB0DAT is written while an active Master Receiver. Figure 24.6 shows a typical master read sequence.
Two received data bytes are shown, though any number of bytes may be received. Notice that the ‘data
byte transferred’ interrupts occur at different places in the sequence, depending on whether hardware ACK
generation is enabled. The interrupt occurs before the ACK with hardware ACK generation disabled, and
after the ACK when hardware ACK generation is enabled.
Interrupts with Hardware ACK Enabled (EHACK = 1)
S
SLA
R
A
Data Byte
A
Data Byte
N
P
Interrupts with Hardware ACK Disabled (EHACK = 0)
S = START
P = STOP
A = ACK
Received by SMBus
Interface
N = NACK
R = READ
SLA = Slave Address
Transmitted by
SMBus Interface
Figure 24.6. Typical Master Read Sequence
24.5.3. Write Sequence (Slave)
During a write sequence, an SMBus master writes data to a slave device. The slave in this transfer will be
a receiver during the address byte, and a receiver during all data bytes. When slave events are enabled
(INH = 0), the interface enters Slave Receiver Mode when a START followed by a slave address and direc-
tion bit (WRITE in this case) is received. If hardware ACK generation is disabled, upon entering Slave
Receiver Mode, an interrupt is generated and the ACKRQ bit is set. The software must respond to the
received slave address with an ACK, or ignore the received slave address with a NACK. If hardware ACK
generation is enabled, the hardware will apply the ACK for a slave address which matches the criteria set
up by SMB0ADR and SMB0ADM. The interrupt will occur after the ACK cycle.
If the received slave address is ignored (by software or hardware), slave interrupts will be inhibited until the
next START is detected. If the received slave address is acknowledged, zero or more data bytes are
received.
If hardware ACK generation is disabled, the ACKRQ is set to 1 and an interrupt is generated after each
received byte. Software must write the ACK bit at that time to ACK or NACK the received byte.
With hardware ACK generation enabled, the SMBus hardware will automatically generate the ACK/NACK,
and then post the interrupt. It is important to note that the appropriate ACK or NACK value should be
set up by the software prior to receiving the byte when hardware ACK generation is enabled.
The interface exits Slave Receiver Mode after receiving a STOP. Note that the interface will switch to Slave
Transmitter Mode if SMB0DAT is written while an active Slave Receiver. Figure 24.7 shows a typical slave
write sequence. Two received data bytes are shown, though any number of bytes may be received. Notice
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that the “data byte transferred” interrupts occur at different places in the sequence, depending on whether
hardware ACK generation is enabled. The interrupt occurs before the ACK with hardware ACK generation
disabled, and after the ACK when hardware ACK generation is enabled.
Interrupts with Hardware ACK Enabled (EHACK = 1)
S
SLA
W
A
Data Byte
A
Data Byte
A
P
Interrupts with Hardware ACK Disabled (EHACK = 0)
S = START
P = STOP
A = ACK
Received by SMBus
Interface
W = WRITE
SLA = Slave Address
Transmitted by
SMBus Interface
Figure 24.7. Typical Slave Write Sequence
24.5.4. Read Sequence (Slave)
During a read sequence, an SMBus master reads data from a slave device. The slave in this transfer will
be a receiver during the address byte, and a transmitter during all data bytes. When slave events are
enabled (INH = 0), the interface enters Slave Receiver Mode (to receive the slave address) when a START
followed by a slave address and direction bit (READ in this case) is received. If hardware ACK generation
is disabled, upon entering Slave Receiver Mode, an interrupt is generated and the ACKRQ bit is set. The
software must respond to the received slave address with an ACK, or ignore the received slave address
with a NACK. If hardware ACK generation is enabled, the hardware will apply the ACK for a slave address
which matches the criteria set up by SMB0ADR and SMB0ADM. The interrupt will occur after the ACK
cycle.
If the received slave address is ignored (by software or hardware), slave interrupts will be inhibited until the
next START is detected. If the received slave address is acknowledged, zero or more data bytes are trans-
mitted. If the received slave address is acknowledged, data should be written to SMB0DAT to be transmit-
ted. The interface enters Slave Transmitter Mode, and transmits one or more bytes of data. After each byte
is transmitted, the master sends an acknowledge bit; if the acknowledge bit is an ACK, SMB0DAT should
be written with the next data byte. If the acknowledge bit is a NACK, SMB0DAT should not be written to
before SI is cleared (Note: an error condition may be generated if SMB0DAT is written following a received
NACK while in Slave Transmitter Mode). The interface exits Slave Transmitter Mode after receiving a
STOP. Note that the interface will switch to Slave Receiver Mode if SMB0DAT is not written following a
Slave Transmitter interrupt. Figure 24.8 shows a typical slave read sequence. Two transmitted data bytes
are shown, though any number of bytes may be transmitted. Notice that all of the ‘data byte transferred’
interrupts occur after the ACK cycle in this mode, regardless of whether hardware ACK generation is
enabled.
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Interrupts with Hardware ACK Enabled (EHACK = 1)
S
SLA
R
A
Data Byte
A
Data Byte
N
P
Interrupts with Hardware ACK Disabled (EHACK = 0)
S = START
P = STOP
N = NACK
Received by SMBus
Interface
R = READ
SLA = Slave Address
Transmitted by
SMBus Interface
Figure 24.8. Typical Slave Read Sequence
24.6. SMBus Status Decoding
The current SMBus status can be easily decoded using the SMB0CN register. The appropriate actions to
take in response to an SMBus event depend on whether hardware slave address recognition and ACK
generation is enabled or disabled. Table 24.5 describes the typical actions when hardware slave address
recognition and ACK generation is disabled. Table 24.6 describes the typical actions when hardware slave
address recognition and ACK generation is enabled. In the tables, STATUS VECTOR refers to the four
upper bits of SMB0CN: MASTER, TXMODE, STA, and STO. The shown response options are only the typ-
ical responses; application-specific procedures are allowed as long as they conform to the SMBus specifi-
cation. Highlighted responses are allowed by hardware but do not conform to the SMBus specification.
Rev. 1.0
305
Si1000/1/2/3/4/5
Table 24.5. SMBus Status Decoding With Hardware ACK Generation Disabled (EHACK = 0)
Values Read
Current SMbus State
Typical Response Options
Valuesto
Write
1110
1100
0
0
0
0
X
0
A master START was gener- Load slave address + R/W into
ated. SMB0DAT.
0
0
X
1100
A master data or address byte Set STA to restart transfer.
1
0
0
1
X
X
1110
-
was transmitted; NACK
received.
Abort transfer.
0
0
1
A master data or address byte Load next data byte into
0
0
X
1100
was transmitted; ACK
received.
SMB0DAT.
End transfer with STOP.
0
1
1
X
X
-
-
End transfer with STOP and start 1
another transfer.
Send repeated START.
1
0
0
X
X
1110
1000
Switch to Master Receiver Mode 0
(clear SI without writing new data
to SMB0DAT).
1000
1
0
X
A master data byte was
received; ACK requested.
Acknowledge received byte;
Read SMB0DAT.
0
0
1
1
1
0
0
1000
-
Send NACK to indicate last byte, 0
and send STOP.
Send NACK to indicate last byte, 1
and send STOP followed by
START.
1110
Send ACK followed by repeated 1
START.
0
0
0
1
0
1
1110
1110
1100
Send NACK to indicate last byte, 1
and send repeated START.
Send ACK and switch to Master 0
Transmitter Mode (write to
SMB0DAT before clearing SI).
Send NACK and switch to Mas-
ter Transmitter Mode (write to
SMB0DAT before clearing SI).
0
0
0
1100
306
Rev. 1.0
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Table 24.5. SMBus Status Decoding With Hardware ACK Generation Disabled (EHACK = 0)
(Continued)
Values Read
Current SMbus State
Typical Response Options
Valuesto
Write
0100
0
0
0
0
0
0
1
X
0
1
X
X
A slave byte was transmitted; No action required (expecting
NACK received. STOP condition).
A slave byte was transmitted; Load SMB0DAT with next data
ACK received. byte to transmit.
A Slave byte was transmitted; No action required (expecting
error detected. Master to end transfer).
0
0
0
0
0
0
0
0
X
X
X
X
0001
0100
0001
-
0101
0010
An illegal STOP or bus error Clear STO.
was detected while a Slave
Transmission was in progress.
1
0
X
A slave address + R/W was
received; ACK requested.
If Write, Acknowledge received
address
0
0
0
0
1
1
0000
0100
If Read, Load SMB0DAT with
data byte; ACK received address
NACK received address.
0
0
0
0
0
1
-
1
1
X
Lost arbitration as master;
If Write, Acknowledge received
0000
slave address + R/W received; address
ACK requested.
If Read, Load SMB0DAT with
0
0
1
0100
data byte; ACK received address
NACK received address.
0
1
0
0
0
0
-
Reschedule failed transfer;
NACK received address.
1110
0001
0000
0
0
X
A STOP was detected while
addressed as a Slave Trans-
mitter or Slave Receiver.
Clear STO.
0
0
X
-
1
1
1
0
X
X
Lost arbitration while attempt- No action required (transfer
ing a STOP.
0
0
0
0
0
1
-
complete/aborted).
A slave byte was received;
ACK requested.
Acknowledge received byte;
Read SMB0DAT.
0000
NACK received byte.
0
0
1
0
1
0
1
0
0
0
0
0
0
0
0
X
X
X
X
0
-
0010
0001
0000
0
0
1
1
1
1
X
X
X
Lost arbitration while attempt- Abort failed transfer.
-
ing a repeated START.
Reschedule failed transfer.
1110
-
Lost arbitration due to a
detected STOP.
Abort failed transfer.
Reschedule failed transfer.
1110
-
Lost arbitration while transmit- Abort failed transfer.
ting a data byte as master.
Reschedule failed transfer.
0
1110
Rev. 1.0
307
Si1000/1/2/3/4/5
Table 24.6. SMBus Status Decoding With Hardware ACK Generation Enabled (EHACK = 1)
Values Read
Current SMbus State
Typical Response Options
Valuesto
Write
1110
1100
0
0
0
0
X
0
A master START was gener- Load slave address + R/W into
ated. SMB0DAT.
0
0
X
1100
A master data or address byte Set STA to restart transfer.
1
0
0
1
X
X
1110
-
was transmitted; NACK
received.
Abort transfer.
0
0
1
A master data or address byte Load next data byte into
0
0
X
1100
was transmitted; ACK
received.
SMB0DAT.
End transfer with STOP.
0
1
1
X
X
-
-
End transfer with STOP and start 1
another transfer.
Send repeated START.
1
0
0
X
1
1110
1000
Switch to Master Receiver Mode 0
(clear SI without writing new data
to SMB0DAT). Set ACK for initial
data byte.
1000
0
0
1
A master data byte was
received; ACK sent.
Set ACK for next data byte;
Read SMB0DAT.
0
0
0
1
0
1000
1000
Set NACK to indicate next data
byte as the last data byte;
Read SMB0DAT.
0
Initiate repeated START.
1
0
0
0
0
1110
1100
Switch to Master Transmitter
Mode (write to SMB0DAT before
clearing SI).
X
0
0
0
A master data byte was
received; NACK sent (last
byte).
Read SMB0DAT; send STOP.
0
1
1
1
0
0
-
Read SMB0DAT; Send STOP
followed by START.
1110
Initiate repeated START.
1
0
0
0
0
1110
1100
Switch to Master Transmitter
Mode (write to SMB0DAT before
clearing SI).
X
308
Rev. 1.0
Si1000/1/2/3/4/5
Table 24.6. SMBus Status Decoding With Hardware ACK Generation Enabled (EHACK = 1)
(Continued)
Values Read
Current SMbus State
Typical Response Options
Valuesto
Write
0100
0
0
0
0
0
0
1
X
0
1
X
X
A slave byte was transmitted; No action required (expecting
NACK received. STOP condition).
A slave byte was transmitted; Load SMB0DAT with next data
ACK received. byte to transmit.
A Slave byte was transmitted; No action required (expecting
error detected. Master to end transfer).
0
0
0
0
0
0
0
0
X
X
X
X
0001
0100
0001
-
0101
0010
An illegal STOP or bus error Clear STO.
was detected while a Slave
Transmission was in progress.
0
0
0
1
X
X
A slave address + R/W was
received; ACK sent.
If Write, Set ACK for first data
byte.
0
0
0
0
0
0
0
0
1
X
1
X
0000
0100
0000
0100
If Read, Load SMB0DAT with
data byte
Lost arbitration as master;
If Write, Set ACK for first data
slave address + R/W received; byte.
ACK sent.
If Read, Load SMB0DAT with
data byte
Reschedule failed transfer
Clear STO.
1
0
0
0
X
X
1110
-
0001
0000
0
0
X
A STOP was detected while
addressed as a Slave Trans-
mitter or Slave Receiver.
0
0
1
0
X
X
Lost arbitration while attempt- No action required (transfer
0
0
0
0
0
0
0
1
0
-
ing a STOP.
complete/aborted).
A slave byte was received.
Set ACK for next data byte;
Read SMB0DAT.
0000
0000
Set NACK for next data byte;
Read SMB0DAT.
0010
0001
0000
0
0
0
1
1
1
X
X
X
Lost arbitration while attempt- Abort failed transfer.
0
1
0
1
0
1
0
0
0
0
0
0
X
X
X
X
X
X
-
ing a repeated START.
Reschedule failed transfer.
1110
-
Lost arbitration due to a
detected STOP.
Abort failed transfer.
Reschedule failed transfer.
1110
-
Lost arbitration while transmit- Abort failed transfer.
ting a data byte as master.
Reschedule failed transfer.
1110
Rev. 1.0
309
Si1000/1/2/3/4/5
25. UART0
UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART.
Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details
in Section “25.1. Enhanced Baud Rate Generation” on page 311). Received data buffering allows UART0
to start reception of a second incoming data byte before software has finished reading the previous data
byte.
UART0 has two associated SFRs: Serial Control Register 0 (SCON0) and Serial Data Buffer 0 (SBUF0).
The single SBUF0 location provides access to both transmit and receive registers. Writes to SBUF0
always access the Transmit register. Reads of SBUF0 always access the buffered Receive register;
it is not possible to read data from the Transmit register.
With UART0 interrupts enabled, an interrupt is generated each time a transmit is completed (TI0 is set in
SCON0), or a data byte has been received (RI0 is set in SCON0). The UART0 interrupt flags are not
cleared by hardware when the CPU vectors to the interrupt service routine. They must be cleared manually
by software, allowing software to determine the cause of the UART0 interrupt (transmit complete or receive
complete).
SFR Bus
Write to
SBUF
TB8
SBUF
SET
(TX Shift)
D
Q
TX
CLR
Crossbar
Zero Detector
Stop Bit
Shift
Data
Start
Tx Control
Tx Clock
Send
Tx IRQ
SCON
TI
UART Baud
Rate Generator
Serial
Port
Interrupt
Port I/O
RI
Rx IRQ
Rx Clock
Rx Control
Load
SBUF
Start
Shift
0x1FF
RB8
Input Shift Register
(9 bits)
Load SBUF
SBUF
(RX Latch)
Read
SBUF
SFR Bus
RX
Crossbar
Figure 25.1. UART0 Block Diagram
310
Rev. 1.0
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25.1. Enhanced Baud Rate Generation
The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by
TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer in Figure 25.2), which is not user-
accessible. Both TX and RX Timer overflows are divided by two to generate the TX and RX baud rates.
The RX Timer runs when Timer 1 is enabled, and uses the same reload value (TH1). However, an
RX Timer reload is forced when a START condition is detected on the RX pin. This allows a receive to
begin any time a START is detected, independent of the TX Timer state.
Timer 1
TL1
UART
Overflow
TX Clock
2
2
TH1
Start
Detected
Overflow
RX Clock
RX Timer
Figure 25.2. UART0 Baud Rate Logic
Timer 1 should be configured for Mode 2, 8-bit auto-reload (see Section “27.1.3. Mode 2: 8-bit Coun-
ter/Timer with Auto-Reload” on page 333). The Timer 1 reload value should be set so that overflows will
occur at two times the desired UART baud rate frequency. Note that Timer 1 may be clocked by one of six
sources: SYSCLK, SYSCLK / 4, SYSCLK / 12, SYSCLK / 48, the external oscillator clock / 8, or an exter-
nal input T1. For any given Timer 1 clock source, the UART0 baud rate is determined by Equation 25.1-A
and Equation 25.1-B.
1
2
A)
B)
--
UartBaudRate = T1_Overflow_Rate
T1CLK
T1_Overflow_Rate = -------------------------
256 – TH1
Equation 25.1. UART0 Baud Rate
Where T1
is the frequency of the clock supplied to Timer 1, and T1H is the high byte of Timer 1 (reload
CLK
value). Timer 1 clock frequency is selected as described in Section “27.1. Timer 0 and Timer 1” on
page 332. A quick reference for typical baud rates and system clock frequencies is given in Table 25.1
through Table 25.2. Note that the internal oscillator may still generate the system clock when the external
oscillator is driving Timer 1.
25.2. Operational Modes
UART0 provides standard asynchronous, full duplex communication. The UART mode (8-bit or 9-bit) is
selected by the S0MODE bit (SCON0.7). Typical UART connection options are shown below.
Rev. 1.0
311
Si1000/1/2/3/4/5
TX
RX
RS-232
LEVEL
XLTR
RS-232
C8051Fxxx
OR
TX
RX
TX
RX
MCU
C8051Fxxx
Figure 25.3. UART Interconnect Diagram
25.2.1. 8-Bit UART
8-Bit UART mode uses a total of 10 bits per data byte: one start bit, eight data bits (LSB first), and one stop
bit. Data are transmitted LSB first from the TX0 pin and received at the RX0 pin. On receive, the eight data
bits are stored in SBUF0 and the stop bit goes into RB80 (SCON0.2).
Data transmission begins when software writes a data byte to the SBUF0 register. The TI0 Transmit Inter-
rupt Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data recep-
tion can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to logic 1. After the stop bit is
received, the data byte will be loaded into the SBUF0 receive register if the following conditions are met:
RI0 must be logic 0, and if MCE0 is logic 1, the stop bit must be logic 1. In the event of a receive data over-
run, the first received 8 bits are latched into the SBUF0 receive register and the following overrun data bits
are lost.
If these conditions are met, the eight bits of data is stored in SBUF0, the stop bit is stored in RB80 and the
RI0 flag is set. If these conditions are not met, SBUF0 and RB80 will not be loaded and the RI0 flag will not
be set. An interrupt will occur if enabled when either TI0 or RI0 is set.
MARK
START
BIT
STOP
BIT
D0
D1
D2
D3
D4
D5
D6
D7
SPACE
BIT TIMES
BIT SAMPLING
Figure 25.4. 8-Bit UART Timing Diagram
25.2.2. 9-Bit UART
9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programma-
ble ninth data bit, and a stop bit. The state of the ninth transmit data bit is determined by the value in TB80
(SCON0.3), which is assigned by user software. It can be assigned the value of the parity flag (bit P in reg-
ister PSW) for error detection, or used in multiprocessor communications. On receive, the ninth data bit
goes into RB80 (SCON0.2) and the stop bit is ignored.
Data transmission begins when an instruction writes a data byte to the SBUF0 register. The TI0 Transmit
Interrupt Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data
reception can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to 1. After the stop bit is
received, the data byte will be loaded into the SBUF0 receive register if the following conditions are met:
312
Rev. 1.0
Si1000/1/2/3/4/5
(1) RI0 must be logic 0, and (2) if MCE0 is logic 1, the 9th bit must be logic 1 (when MCE0 is logic 0, the
state of the ninth data bit is unimportant). If these conditions are met, the eight bits of data are stored in
SBUF0, the ninth bit is stored in RB80, and the RI0 flag is set to 1. If the above conditions are not met,
SBUF0 and RB80 will not be loaded and the RI0 flag will not be set to 1. A UART0 interrupt will occur if
enabled when either TI0 or RI0 is set to 1.
MARK
START
BIT
STOP
BIT
D0
D1
D2
D3
D4
D5
D6
D7
D8
SPACE
BIT TIMES
BIT SAMPLING
Figure 25.5. 9-Bit UART Timing Diagram
25.3. Multiprocessor Communications
9-Bit UART mode supports multiprocessor communication between a master processor and one or more
slave processors by special use of the ninth data bit. When a master processor wants to transmit to one or
more slaves, it first sends an address byte to select the target(s). An address byte differs from a data byte
in that its ninth bit is logic 1; in a data byte, the ninth bit is always set to logic 0.
Setting the MCE0 bit (SCON0.5) of a slave processor configures its UART such that when a stop bit is
received, the UART will generate an interrupt only if the ninth bit is logic 1 (RB80 = 1) signifying an address
byte has been received. In the UART interrupt handler, software will compare the received address with
the slave's own assigned 8-bit address. If the addresses match, the slave will clear its MCE0 bit to enable
interrupts on the reception of the following data byte(s). Slaves that weren't addressed leave their MCE0
bits set and do not generate interrupts on the reception of the following data bytes, thereby ignoring the
data. Once the entire message is received, the addressed slave resets its MCE0 bit to ignore all transmis-
sions until it receives the next address byte.
Multiple addresses can be assigned to a single slave and/or a single address can be assigned to multiple
slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. The master
processor can be configured to receive all transmissions or a protocol can be implemented such that the
master/slave role is temporarily reversed to enable half-duplex transmission between the original master
and slave(s).
Master
Device
Slave
Device
Slave
Device
Slave
Device
V+
RX
TX
RX
TX
RX
TX
RX
TX
Figure 25.6. UART Multi-Processor Mode Interconnect Diagram
Rev. 1.0
313
Si1000/1/2/3/4/5
SFR Definition 25.1. SCON0: Serial Port 0 Control
Bit
7
6
5
4
3
2
1
0
S0MODE
MCE0
REN0
TB80
RB80
TI0
RI0
Name
Type
Reset
R/W
0
R
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Page = 0x0; SFR Address = 0x98; Bit-Addressable
Bit
Name
Function
7
S0MODE Serial Port 0 Operation Mode.
Selects the UART0 Operation Mode.
0: 8-bit UART with Variable Baud Rate.
1: 9-bit UART with Variable Baud Rate.
6
5
Unused Read = 1b. Write = Don’t Care.
MCE0
Multiprocessor Communication Enable.
For Mode 0 (8-bit UART): Checks for valid stop bit.
0: Logic level of stop bit is ignored.
1: RI0 will only be activated if stop bit is logic level 1.
For Mode 1 (9-bit UART): Multiprocessor Communications Enable.
0: Logic level of ninth bit is ignored.
1: RI0 is set and an interrupt is generated only when the ninth bit is logic 1.
4
3
2
1
REN0
TB80
RB80
TI0
Receive Enable.
0: UART0 reception disabled.
1: UART0 reception enabled.
Ninth Transmission Bit.
The logic level of this bit will be sent as the ninth transmission bit in 9-bit UART Mode
(Mode 1). Unused in 8-bit mode (Mode 0).
Ninth Receive Bit.
RB80 is assigned the value of the STOP bit in Mode 0; it is assigned the value of the
9th data bit in Mode 1.
Transmit Interrupt Flag.
Set by hardware when a byte of data has been transmitted by UART0 (after the 8th bit
in 8-bit UART Mode, or at the beginning of the STOP bit in 9-bit UART Mode). When
the UART0 interrupt is enabled, setting this bit causes the CPU to vector to the UART0
interrupt service routine. This bit must be cleared manually by software.
0
RI0
Receive Interrupt Flag.
Set to 1 by hardware when a byte of data has been received by UART0 (set at the
STOP bit sampling time). When the UART0 interrupt is enabled, setting this bit to 1
causes the CPU to vector to the UART0 interrupt service routine. This bit must be
cleared manually by software.
314
Rev. 1.0
Si1000/1/2/3/4/5
SFR Definition 25.2. SBUF0: Serial (UART0) Port Data Buffer
Bit
7
6
5
4
3
2
1
0
SBUF0[7:0]
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Page = 0x0; SFR Address = 0x99
Bit
Name
Function
7:0
SBUF0
Serial Data Buffer Bits 7:0 (MSB–LSB)
This SFR accesses two registers; a transmit shift register and a receive latch register.
When data is written to SBUF0, it goes to the transmit shift register and is held for
serial transmission. Writing a byte to SBUF0 initiates the transmission. A read of
SBUF0 returns the contents of the receive latch.
Rev. 1.0
315
Si1000/1/2/3/4/5
Table 25.1. Timer Settings for Standard Baud Rates
Using The Internal 24.5 MHz Oscillator
Frequency: 24.5 MHz
T1M1
Target
Baud Rate
% Error
Timer Clock SCA1–SCA0
Timer 1
Reload
Value (hex)
Oscillator Source
Baud Rate
(bps)
(pre-scale
select)1
Divide
Factor
2
230400
115200
57600
28800
14400
9600
–0.32%
–0.32%
0.15%
–0.32%
0.15%
–0.32%
–0.32%
0.15%
106
212
426
SYSCLK
SYSCLK
SYSCLK
SYSCLK/4
SYSCLK/12
SYSCLK/12
SYSCLK/48
SYSCLK/48
XX
XX
XX
01
00
00
10
10
1
1
1
0
0
0
0
0
0xCB
0x96
0x2B
0x96
0xB9
0x96
0x96
0x2B
848
1704
2544
10176
20448
2400
1200
Notes:
1. SCA1–SCA0 and T1M bit definitions can be found in Section 27.1.
2. X = Don’t care.
Table 25.2. Timer Settings for Standard Baud Rates
Using an External 22.1184 MHz Oscillator
Frequency: 22.1184 MHz
T1M1
Target
Baud Rate
% Error
Timer Clock SCA1–SCA0
Timer 1
Reload
Value (hex)
Oscillator Source
Baud Rate
(bps)
(pre-scale
select)1
Divide
Factor
2
230400
115200
57600
28800
14400
9600
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
96
192
384
SYSCLK
SYSCLK
SYSCLK
XX
XX
XX
00
00
00
10
10
11
11
11
11
11
11
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0xD0
0xA0
0x40
0xE0
0xC0
0xA0
0xA0
0x40
0xFA
0xF4
0xE8
0xD0
0xA0
0x70
768
SYSCLK / 12
SYSCLK / 12
SYSCLK / 12
SYSCLK / 48
SYSCLK / 48
EXTCLK / 8
EXTCLK / 8
EXTCLK / 8
EXTCLK / 8
EXTCLK / 8
EXTCLK / 8
1536
2304
9216
18432
96
192
384
768
1536
2304
2400
1200
230400
115200
57600
28800
14400
9600
Notes:
1. SCA1–SCA0 and T1M bit definitions can be found in Section 27.1.
2. X = Don’t care.
316
Rev. 1.0
Si1000/1/2/3/4/5
26. Enhanced Serial Peripheral Interface (SPI0)
The Enhanced Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous
serial bus. SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports
multiple masters and slaves on a single SPI bus. The slave-select (NSS) signal can be configured as an
input to select SPI0 in slave mode, or to disable Master Mode operation in a multi-master environment,
avoiding contention on the SPI bus when more than one master attempts simultaneous data transfers.
NSS can also be configured as a chip-select output in master mode, or disabled for 3-wire operation.
Additional general purpose port I/O pins can be used to select multiple slave devices in master mode.
SFR Bus
SPI0CKR
SPI0CFG
SPI0CN
Clock Divide
Logic
SYSCLK
SPI CONTROL LOGIC
SPI IRQ
Data Path
Control
Pin Interface
Control
MOSI
Tx Data
C
R
O
S
S
B
A
R
SPI0DAT
SCK
MISO
NSS
Transmit Data Buffer
Pin
Control
Logic
Port I/O
Shift Register
Rx Data
7 6 5 4 3 2 1 0
Receive Data Buffer
Read
SPI0DAT
Write
SPI0DAT
SFR Bus
Figure 26.1. SPI Block Diagram
Rev. 1.0
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26.1. Signal Descriptions
The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below.
26.1.1. Master Out, Slave In (MOSI)
The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices. It
is used to serially transfer data from the master to the slave. This signal is an output when SPI0 is
operating as a master and an input when SPI0 is operating as a slave. Data is transferred most-significant
bit first. When configured as a master, MOSI is driven by the MSB of the shift register in both 3- and 4-wire
mode.
26.1.2. Master In, Slave Out (MISO)
The master-in, slave-out (MISO) signal is an output from a slave device and an input to the master device.
It is used to serially transfer data from the slave to the master. This signal is an input when SPI0 is
operating as a master and an output when SPI0 is operating as a slave. Data is transferred most-
significant bit first. The MISO pin is placed in a high-impedance state when the SPI module is disabled and
when the SPI operates in 4-wire mode as a slave that is not selected. When acting as a slave in 3-wire
mode, MISO is always driven by the MSB of the shift register.
26.1.3. Serial Clock (SCK)
The serial clock (SCK) signal is an output from the master device and an input to slave devices. It is used
to synchronize the transfer of data between the master and slave on the MOSI and MISO lines. SPI0
generates this signal when operating as a master. The SCK signal is ignored by a SPI slave when the
slave is not selected (NSS = 1) in 4-wire slave mode.
26.1.4. Slave Select (NSS)
The function of the slave-select (NSS) signal is dependent on the setting of the NSSMD1 and NSSMD0
bits in the SPI0CN register. There are three possible modes that can be selected with these bits:
1. NSSMD[1:0] = 00: 3-Wire Master or 3-Wire Slave Mode: SPI0 operates in 3-wire mode, and NSS is
disabled. When operating as a slave device, SPI0 is always selected in 3-wire mode. Since no select
signal is present, SPI0 must be the only slave on the bus in 3-wire mode. This is intended for point-to-
point communication between a master and one slave.
2. NSSMD[1:0] = 01: 4-Wire Slave or Multi-Master Mode: SPI0 operates in 4-wire mode, and NSS is
enabled as an input. When operating as a slave, NSS selects the SPI0 device. When operating as a
master, a 1-to-0 transition of the NSS signal disables the master function of SPI0 so that multiple
master devices can be used on the same SPI bus.
3. NSSMD[1:0] = 1x: 4-Wire Master Mode: SPI0 operates in 4-wire mode, and NSS is enabled as an
output. The setting of NSSMD0 determines what logic level the NSS pin will output. This configuration
should only be used when operating SPI0 as a master device.
See Figure 26.2, Figure 26.3, and Figure 26.4 for typical connection diagrams of the various operational
modes. Note that the setting of NSSMD bits affects the pinout of the device. When in 3-wire master or
3-wire slave mode, the NSS pin will not be mapped by the crossbar. In all other modes, the NSS signal will
be mapped to a pin on the device. See Section “21. Port Input/Output” on page 207 for general purpose
port I/O and crossbar information.
26.2. SPI0 Master Mode Operation
A SPI master device initiates all data transfers on a SPI bus. SPI0 is placed in master mode by setting the
Master Enable flag (MSTEN, SPI0CN.6). Writing a byte of data to the SPI0 data register (SPI0DAT) when
in master mode writes to the transmit buffer. If the SPI shift register is empty, the byte in the transmit buffer
is moved to the shift register, and a data transfer begins. The SPI0 master immediately shifts out the data
serially on the MOSI line while providing the serial clock on SCK. The SPIF (SPI0CN.7) flag is set to logic
1 at the end of the transfer. If interrupts are enabled, an interrupt request is generated when the SPIF flag
is set. While the SPI0 master transfers data to a slave on the MOSI line, the addressed SPI slave device
simultaneously transfers the contents of its shift register to the SPI master on the MISO line in a full-duplex
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operation. Therefore, the SPIF flag serves as both a transmit-complete and receive-data-ready flag. The
data byte received from the slave is transferred MSB-first into the master's shift register. When a byte is
fully shifted into the register, it is moved to the receive buffer where it can be read by the processor by
reading SPI0DAT.
When configured as a master, SPI0 can operate in one of three different modes: multi-master mode, 3-wire
single-master mode, and 4-wire single-master mode. The default, multi-master mode is active when
NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In this mode, NSS is an input to the device, and
is used to disable the master SPI0 when another master is accessing the bus. When NSS is pulled low in
this mode, MSTEN (SPI0CN.6) and SPIEN (SPI0CN.0) are set to 0 to disable the SPI master device, and
a Mode Fault is generated (MODF, SPI0CN.5 = 1). Mode Fault will generate an interrupt if enabled. SPI0
must be manually re-enabled in software under these circumstances. In multi-master systems, devices will
typically default to being slave devices while they are not acting as the system master device. In multi-
master mode, slave devices can be addressed individually (if needed) using general-purpose I/O pins.
Figure 26.2 shows a connection diagram between two master devices in multiple-master mode.
3-wire single-master mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 0. In this
mode, NSS is not used, and is not mapped to an external port pin through the crossbar. Any slave devices
that must be addressed in this mode should be selected using general-purpose I/O pins. Figure 26.3
shows a connection diagram between a master device in 3-wire master mode and a slave device.
4-wire single-master mode is active when NSSMD1 (SPI0CN.3) = 1. In this mode, NSS is configured as an
output pin, and can be used as a slave-select signal for a single SPI device. In this mode, the output value
of NSS is controlled (in software) with the bit NSSMD0 (SPI0CN.2). Additional slave devices can be
addressed using general-purpose I/O pins. Figure 26.4 shows a connection diagram for a master device in
4-wire master mode and two slave devices.
NSS
MISO
MOSI
SCK
GPIO
MISO
MOSI
SCK
Master
Device 1
Master
Device 2
GPIO
NSS
Figure 26.2. Multiple-Master Mode Connection Diagram
Master
Device
Slave
Device
MISO
MOSI
SCK
MISO
MOSI
SCK
Figure 26.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram
Rev. 1.0
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MISO
MOSI
SCK
MISO
MOSI
SCK
Master
Device
Slave
Device
NSS
NSS
GPIO
MISO
MOSI
SCK
Slave
Device
NSS
Figure 26.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram
26.3. SPI0 Slave Mode Operation
When SPI0 is enabled and not configured as a master, it will operate as a SPI slave. As a slave, bytes are
shifted in through the MOSI pin and out through the MISO pin by a master device controlling the SCK
signal. A bit counter in the SPI0 logic counts SCK edges. When 8 bits have been shifted through the shift
register, the SPIF flag is set to logic 1, and the byte is copied into the receive buffer. Data is read from the
receive buffer by reading SPI0DAT. A slave device cannot initiate transfers. Data to be transferred to the
master device is pre-loaded into the shift register by writing to SPI0DAT. Writes to SPI0DAT are double-
buffered, and are placed in the transmit buffer first. If the shift register is empty, the contents of the transmit
buffer will immediately be transferred into the shift register. When the shift register already contains data,
the SPI will load the shift register with the transmit buffer’s contents after the last SCK edge of the next (or
current) SPI transfer.
When configured as a slave, SPI0 can be configured for 4-wire or 3-wire operation. The default, 4-wire
slave mode, is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In 4-wire mode, the
NSS signal is routed to a port pin and configured as a digital input. SPI0 is enabled when NSS is logic 0,
and disabled when NSS is logic 1. The bit counter is reset on a falling edge of NSS. Note that the NSS
signal must be driven low at least 2 system clocks before the first active edge of SCK for each byte
transfer. Figure 26.4 shows a connection diagram between two slave devices in 4-wire slave mode and a
master device.
3-wire slave mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 0. NSS is not
used in this mode, and is not mapped to an external port pin through the crossbar. Since there is no way of
uniquely addressing the device in 3-wire slave mode, SPI0 must be the only slave device present on the
bus. It is important to note that in 3-wire slave mode there is no external means of resetting the bit counter
that determines when a full byte has been received. The bit counter can only be reset by disabling and re-
enabling SPI0 with the SPIEN bit. Figure 26.3 shows a connection diagram between a slave device in 3-
wire slave mode and a master device.
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26.4. SPI0 Interrupt Sources
When SPI0 interrupts are enabled, the following four flags will generate an interrupt when they are set to
logic 1:
All of the following bits must be cleared by software.
The SPI Interrupt Flag, SPIF (SPI0CN.7) is set to logic 1 at the end of each byte transfer. This flag can
occur in all SPI0 modes.
The Write Collision Flag, WCOL (SPI0CN.6) is set to logic 1 if a write to SPI0DAT is attempted when
the transmit buffer has not been emptied to the SPI shift register. When this occurs, the write to
SPI0DAT will be ignored, and the transmit buffer will not be written.This flag can occur in all SPI0
modes.
The Mode Fault Flag MODF (SPI0CN.5) is set to logic 1 when SPI0 is configured as a master, and for
multi-master mode and the NSS pin is pulled low. When a Mode Fault occurs, the MSTEN and SPIEN
bits in SPI0CN are set to logic 0 to disable SPI0 and allow another master device to access the bus.
The Receive Overrun Flag RXOVRN (SPI0CN.4) is set to logic 1 when configured as a slave, and a
transfer is completed and the receive buffer still holds an unread byte from a previous transfer. The new
byte is not transferred to the receive buffer, allowing the previously received data byte to be read. The
data byte which caused the overrun is lost.
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26.5. Serial Clock Phase and Polarity
Four combinations of serial clock phase and polarity can be selected using the clock control bits in the
SPI0 Configuration Register (SPI0CFG). The CKPHA bit (SPI0CFG.5) selects one of two clock phases
(edge used to latch the data). The CKPOL bit (SPI0CFG.4) selects between an active-high or active-low
clock. Both master and slave devices must be configured to use the same clock phase and polarity. SPI0
should be disabled (by clearing the SPIEN bit, SPI0CN.0) when changing the clock phase or polarity. The
clock and data line relationships for master mode are shown in Figure 26.5. For slave mode, the clock and
data relationships are shown in Figure 26.6 and Figure 26.7. Note that CKPHA should be set to 0 on both
the master and slave SPI when communicating between two Silicon Labs C8051 devices.
The SPI0 Clock Rate Register (SPI0CKR) as shown in SFR Definition 26.9 controls the master mode
serial clock frequency. This register is ignored when operating in slave mode. When the SPI is configured
as a master, the maximum data transfer rate (bits/sec) is one-half the system clock frequency or 12.5 MHz,
whichever is slower. When the SPI is configured as a slave, the maximum data transfer rate (bits/sec) for
full-duplex operation is 1/10 the system clock frequency, provided that the master issues SCK, NSS (in 4-
wire slave mode), and the serial input data synchronously with the slave’s system clock. If the master
issues SCK, NSS, and the serial input data asynchronously, the maximum data transfer rate (bits/sec)
must be less than 1/10 the system clock frequency. In the special case where the master only wants to
transmit data to the slave and does not need to receive data from the slave (i.e. half-duplex operation), the
SPI slave can receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency.
This is provided that the master issues SCK, NSS, and the serial input data synchronously with the slave’s
system clock.
SCK
(CKPOL=0, CKPHA=0)
SCK
(CKPOL=0, CKPHA=1)
SCK
(CKPOL=1, CKPHA=0)
SCK
(CKPOL=1, CKPHA=1)
MISO/MOSI
MSB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
NSS (Must Remain High
in Multi-Master Mode)
Figure 26.5. Master Mode Data/Clock Timing
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SCK
(CKPOL=0, CKPHA=0)
SCK
(CKPOL=1, CKPHA=0)
MOSI
MSB
MSB
Bit 6
Bit 6
Bit 5
Bit 5
Bit 4
Bit 4
Bit 3
Bit 3
Bit 2
Bit 2
Bit 1
Bit 1
Bit 0
Bit 0
MISO
NSS (4-Wire Mode)
Figure 26.6. Slave Mode Data/Clock Timing (CKPHA = 0)
SCK
(CKPOL=0, CKPHA=1)
SCK
(CKPOL=1, CKPHA=1)
MOSI
MSB
MSB
Bit 6
Bit 6
Bit 5
Bit 5
Bit 4
Bit 4
Bit 3
Bit 3
Bit 2
Bit 2
Bit 1
Bit 1
Bit 0
Bit 0
MISO
NSS (4-Wire Mode)
Figure 26.7. Slave Mode Data/Clock Timing (CKPHA = 1)
26.6. SPI Special Function Registers
SPI0 is accessed and controlled through four special function registers in the system controller: SPI0CN
Control Register, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate
Register. The four special function registers related to the operation of the SPI0 Bus are described in the
following figures.
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SFR Definition 26.7. SPI0CFG: SPI0 Configuration
Bit
7
6
MSTEN
R/W
0
5
CKPHA
R/W
0
4
CKPOL
R/W
0
3
2
1
SRMT
R
0
Name SPIBSY
SLVSEL
NSSIN
RXBMT
Type
R
0
R
0
R
1
R
1
Reset
1
SFR Page = 0x0; SFR Address = 0xA1
Bit
Name
Function
7
SPIBSY
SPI Busy.
This bit is set to logic 1 when a SPI transfer is in progress (master or slave mode).
6
5
4
3
MSTEN
CKPHA
CKPOL
SLVSEL
Master Mode Enable.
0: Disable master mode. Operate in slave mode.
1: Enable master mode. Operate as a master.
SPI0 Clock Phase.
*
0: Data centered on first edge of SCK period.
1: Data centered on second edge of SCK period.
*
SPI0 Clock Polarity.
0: SCK line low in idle state.
1: SCK line high in idle state.
Slave Selected Flag.
This bit is set to logic 1 whenever the NSS pin is low indicating SPI0 is the selected
slave. It is cleared to logic 0 when NSS is high (slave not selected). This bit does
not indicate the instantaneous value at the NSS pin, but rather a de-glitched ver-
sion of the pin input.
2
1
NSSIN
SRMT
NSS Instantaneous Pin Input.
This bit mimics the instantaneous value that is present on the NSS port pin at the
time that the register is read. This input is not de-glitched.
Shift Register Empty (valid in slave mode only).
This bit will be set to logic 1 when all data has been transferred in/out of the shift
register, and there is no new information available to read from the transmit buffer
or write to the receive buffer. It returns to logic 0 when a data byte is transferred to
the shift register from the transmit buffer or by a transition on SCK. SRMT = 1 when
in Master Mode.
0
RXBMT
Receive Buffer Empty (valid in slave mode only).
This bit will be set to logic 1 when the receive buffer has been read and contains no
new information. If there is new information available in the receive buffer that has
not been read, this bit will return to logic 0. RXBMT = 1 when in Master Mode.
Note: In slave mode, data on MOSI is sampled in the center of each data bit. In master mode, data on MISO is
sampled one SYSCLK before the end of each data bit, to provide maximum settling time for the slave device.
See Table 26.1 for timing parameters.
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SFR Definition 26.8. SPI0CN: SPI0 Control
Bit
7
SPIF
R/W
0
6
WCOL
R/W
0
5
MODF
R/W
0
4
RXOVRN
R/W
3
2
1
0
SPIEN
R/W
0
Name
Type
Reset
NSSMD[1:0]
R/W
TXBMT
R
1
0
0
1
SFR Page = 0x0; SFR Address = 0xF8; Bit-Addressable
Bit
Name
Function
7
SPIF
SPI0 Interrupt Flag.
This bit is set to logic 1 by hardware at the end of a data transfer. If SPI interrupts
are enabled, an interrupt will be generated. This bit is not automatically cleared by
hardware, and must be cleared by software.
6
5
4
WCOL
MODF
Write Collision Flag.
This bit is set to logic 1 if a write to SPI0DAT is attempted when TXBMT is 0. When
this occurs, the write to SPI0DAT will be ignored, and the transmit buffer will not be
written. If SPI interrupts are enabled, an interrupt will be generated. This bit is not
automatically cleared by hardware, and must be cleared by software.
Mode Fault Flag.
This bit is set to logic 1 by hardware when a master mode collision is detected
(NSS is low, MSTEN = 1, and NSSMD[1:0] = 01). If SPI interrupts are enabled, an
interrupt will be generated. This bit is not automatically cleared by hardware, and
must be cleared by software.
RXOVRN
Receive Overrun Flag (valid in slave mode only).
This bit is set to logic 1 by hardware when the receive buffer still holds unread data
from a previous transfer and the last bit of the current transfer is shifted into the
SPI0 shift register. If SPI interrupts are enabled, an interrupt will be generated. This
bit is not automatically cleared by hardware, and must be cleared by software.
3:2 NSSMD[1:0] Slave Select Mode.
Selects between the following NSS operation modes:
(See Section 26.2 and Section 26.3).
00: 3-Wire Slave or 3-Wire Master Mode. NSS signal is not routed to a port pin.
01: 4-Wire Slave or Multi-Master Mode (Default). NSS is an input to the device.
1x: 4-Wire Single-Master Mode. NSS signal is mapped as an output from the
device and will assume the value of NSSMD0.
1
0
TXBMT
SPIEN
Transmit Buffer Empty.
This bit will be set to logic 0 when new data has been written to the transmit buffer.
When data in the transmit buffer is transferred to the SPI shift register, this bit will
be set to logic 1, indicating that it is safe to write a new byte to the transmit buffer.
SPI0 Enable.
0: SPI disabled.
1: SPI enabled.
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SFR Definition 26.9. SPI0CKR: SPI0 Clock Rate
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
SCR[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xA2
Bit
Name
Function
7:0
SCR[7:0]
SPI0 Clock Rate.
These bits determine the frequency of the SCK output when the SPI0 module is
configured for master mode operation. The SCK clock frequency is a divided ver-
sion of the system clock, and is given in the following equation, where SYSCLK is
the system clock frequency and SPI0CKR is the 8-bit value held in the SPI0CKR
register.
SYSCLK
fSCK = ----------------------------------------------------------
2 SPI0CKR[7:0] + 1
for 0 <= SPI0CKR <= 255
Example: If SYSCLK = 2 MHz and SPI0CKR = 0x04,
2000000
fSCK = -------------------------
2 4 + 1
fSCK = 200kHz
SFR Definition 26.10. SPI0DAT: SPI0 Data
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
SPI0DAT[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xA3
Bit Name
7:0 SPI0DAT[7:0] SPI0 Transmit and Receive Data.
Function
The SPI0DAT register is used to transmit and receive SPI0 data. Writing data to
SPI0DAT places the data into the transmit buffer and initiates a transfer when in
Master Mode. A read of SPI0DAT returns the contents of the receive buffer.
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SCK*
T
T
MCKL
MCKH
T
T
MIS
MIH
MISO
MOSI
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
Figure 26.8. SPI Master Timing (CKPHA = 0)
SCK*
T
T
MCKH
MCKL
T
T
MIH
MIS
MISO
MOSI
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
Figure 26.9. SPI Master Timing (CKPHA = 1)
Rev. 1.0
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NSS
T
T
T
SD
SE
CKL
SCK*
T
CKH
T
T
SIH
SIS
MOSI
T
T
T
SDZ
SEZ
SOH
MISO
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
Figure 26.10. SPI Slave Timing (CKPHA = 0)
NSS
T
T
T
SD
SE
CKL
SCK*
T
CKH
T
T
SIH
SIS
MOSI
T
T
T
SDZ
T
SOH
SLH
SEZ
MISO
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
Figure 26.11. SPI Slave Timing (CKPHA = 1)
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Table 26.1. SPI Slave Timing Parameters
Parameter
Description
Min
Max
Units
Master Mode Timing (See Figure 26.8 and Figure 26.9)
T
T
T
T
SCK High Time
1 x T
—
—
—
—
ns
ns
ns
ns
MCKH
MCKL
MIS
SYSCLK
SYSCLK
SCK Low Time
1 x T
1 x T
MISO Valid to SCK Shift Edge
SCK Shift Edge to MISO Change
+ 20
SYSCLK
0
MIH
Slave Mode Timing (See Figure 26.10 and Figure 26.11)
T
T
T
T
T
T
T
T
T
T
NSS Falling to First SCK Edge
Last SCK Edge to NSS Rising
NSS Falling to MISO Valid
NSS Rising to MISO High-Z
SCK High Time
2 x T
2 x T
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SE
SYSCLK
SD
SYSCLK
—
4 x T
SYSCLK
SEZ
SDZ
CKH
CKL
SIS
—
4 x T
SYSCLK
5 x T
5 x T
2 x T
2 x T
—
SYSCLK
SYSCLK
SYSCLK
SCK Low Time
—
—
—
MOSI Valid to SCK Sample Edge
SCK Sample Edge to MOSI Change
SCK Shift Edge to MISO Change
SIH
SOH
SLH
SYSCLK
—
4 x T
8 x T
SYSCLK
SYSCLK
Last SCK Edge to MISO Change
6 x T
SYSCLK
(CKPHA = 1 ONLY)
Note: T
is equal to one period of the device system clock (SYSCLK).
SYSCLK
Rev. 1.0
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27. Timers
Each MCU includes four counter/timers: two are 16-bit counter/timers compatible with those found in the
standard 8051, and two are 16-bit auto-reload timer for use with the ADC, SMBus, or for general purpose
use. These timers can be used to measure time intervals, count external events and generate periodic
interrupt requests. Timer 0 and Timer 1 are nearly identical and have four primary modes of operation.
Timer 2 and Timer 3 offer 16-bit and split 8-bit timer functionality with auto-reload. Additionally, Timer 2 and
Timer 3 have a Capture Mode that can be used to measure the SmaRTClock or a Comparator period with
respect to another oscillator. This is particularly useful when using Capacitive Touch Switches. See Appli-
cation Note AN338 for details on Capacitive Touch Switch sensing.
Timer 0 and Timer 1 Modes:
13-bit counter/timer
Timer 2 Modes:
Timer 3 Modes:
16-bit timer with auto-reload
16-bit timer with auto-reload
16-bit counter/timer
8-bit counter/timer with auto-
reload
Two 8-bit timers with auto-reload Two 8-bit timers with auto-reload
Two 8-bit counter/timers (Timer 0
only)
Timers 0 and 1 may be clocked by one of five sources, determined by the Timer Mode Select bits (T1M–
T0M) and the Clock Scale bits (SCA1–SCA0). The Clock Scale bits define a pre-scaled clock from which
Timer 0 and/or Timer 1 may be clocked (See SFR Definition 27.1 for pre-scaled clock selection).
Timer 0/1 may then be configured to use this pre-scaled clock signal or the system clock. Timer 2 and
Timer 3 may be clocked by the system clock, the system clock divided by 12. Timer 2 may additionally be
clocked by the SmaRTClock divided by 8 or the Comparator0 output. Timer 3 may additionally be clocked
by the external oscillator clock source divided by 8 or the Comparator1 output.
Timer 0 and Timer 1 may also be operated as counters. When functioning as a counter, a counter/timer
register is incremented on each high-to-low transition at the selected input pin (T0 or T1). Events with a fre-
quency of up to one-fourth the system clock frequency can be counted. The input signal need not be peri-
odic, but it should be held at a given level for at least two full system clock cycles to ensure the level is
properly sampled.
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SFR Definition 27.1. CKCON: Clock Control
Bit
7
T3MH
R/W
0
6
T3ML
R/W
0
5
T2MH
R/W
0
4
T2ML
R/W
0
3
2
1
0
Name
Type
Reset
T1M
R/W
0
T0M
R/W
0
SCA[1:0]
R/W
0
0
SFR Page = 0x0; SFR Address = 0x8E
Bit
Name
Function
7
T3MH Timer 3 High Byte Clock Select.
Selects the clock supplied to the Timer 3 high byte (split 8-bit timer mode only).
0: Timer 3 high byte uses the clock defined by the T3XCLK bit in TMR3CN.
1: Timer 3 high byte uses the system clock.
6
T3ML
Timer 3 Low Byte Clock Select.
Selects the clock supplied to Timer 3. Selects the clock supplied to the lower 8-bit timer
in split 8-bit timer mode.
0: Timer 3 low byte uses the clock defined by the T3XCLK bit in TMR3CN.
1: Timer 3 low byte uses the system clock.
5
4
T2MH Timer 2 High Byte Clock Select.
Selects the clock supplied to the Timer 2 high byte (split 8-bit timer mode only).
0: Timer 2 high byte uses the clock defined by the T2XCLK bit in TMR2CN.
1: Timer 2 high byte uses the system clock.
T2ML
Timer 2 Low Byte Clock Select.
Selects the clock supplied to Timer 2. If Timer 2 is configured in split 8-bit timer mode,
this bit selects the clock supplied to the lower 8-bit timer.
0: Timer 2 low byte uses the clock defined by the T2XCLK bit in TMR2CN.
1: Timer 2 low byte uses the system clock.
3
2
T1M
T0M
Timer 1 Clock Select.
Selects the clock source supplied to Timer 1. Ignored when C/T1 is set to 1.
0: Timer 1 uses the clock defined by the prescale bits SCA[1:0].
1: Timer 1 uses the system clock.
Timer 0 Clock Select.
Selects the clock source supplied to Timer 0. Ignored when C/T0 is set to 1.
0: Counter/Timer 0 uses the clock defined by the prescale bits SCA[1:0].
1: Counter/Timer 0 uses the system clock.
1:0 SCA[1:0] Timer 0/1 Prescale Bits.
These bits control the Timer 0/1 Clock Prescaler:
00: System clock divided by 12
01: System clock divided by 4
10: System clock divided by 48
11: External clock divided by 8 (synchronized with the system clock)
Rev. 1.0
331
Si1000/1/2/3/4/5
27.1. Timer 0 and Timer 1
Each timer is implemented as a 16-bit register accessed as two separate bytes: a low byte (TL0 or TL1)
and a high byte (TH0 or TH1). The Counter/Timer Control register (TCON) is used to enable Timer 0 and
Timer 1 as well as indicate status. Timer 0 interrupts can be enabled by setting the ET0 bit in the IE regis-
ter (Section “12.5. Interrupt Register Descriptions” on page 132); Timer 1 interrupts can be enabled by set-
ting the ET1 bit in the IE register (Section “12.5. Interrupt Register Descriptions” on page 132). Both
counter/timers operate in one of four primary modes selected by setting the Mode Select bits T1M1–T0M0
in the Counter/Timer Mode register (TMOD). Each timer can be configured independently. Each operating
mode is described below.
27.1.1. Mode 0: 13-bit Counter/Timer
Timer 0 and Timer 1 operate as 13-bit counter/timers in Mode 0. The following describes the configuration
and operation of Timer 0. However, both timers operate identically, and Timer 1 is configured in the same
manner as described for Timer 0.
The TH0 register holds the eight MSBs of the 13-bit counter/timer. TL0 holds the five LSBs in bit positions
TL0.4–TL0.0. The three upper bits of TL0 (TL0.7–TL0.5) are indeterminate and should be masked out or
ignored when reading. As the 13-bit timer register increments and overflows from 0x1FFF (all ones) to
0x0000, the timer overflow flag TF0 (TCON.5) is set and an interrupt will occur if Timer 0 interrupts are
enabled.
The C/T0 bit (TMOD.2) selects the counter/timer's clock source. When C/T0 is set to logic 1, high-to-low
transitions at the selected Timer 0 input pin (T0) increment the timer register (Refer to Section
“21.3. Priority Crossbar Decoder” on page 211 for information on selecting and configuring external I/O
pins). Clearing C/T selects the clock defined by the T0M bit (CKCON.3). When T0M is set, Timer 0 is
clocked by the system clock. When T0M is cleared, Timer 0 is clocked by the source selected by the Clock
Scale bits in CKCON (see SFR Definition 27.1).
Setting the TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or the input signal
INT0 is active as defined by bit IN0PL in register IT01CF (see SFR Definition 12.7). Setting GATE0 to 1
allows the timer to be controlled by the external input signal INT0 (see Section “12.5. Interrupt Register
Descriptions” on page 132), facilitating pulse width measurements
Table 27.1. Timer 0 Running Modes
TR0
GATE0
INT0
Counter/Timer
Disabled
0
X
0
1
1
X
X
0
1
1
Enabled
1
Disabled
1
Enabled
Note: X = Don't Care
Setting TR0 does not force the timer to reset. The timer registers should be loaded with the desired initial
value before the timer is enabled.
TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as described above for TL0 and TH0.
Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0. The
input signal INT1 is used with Timer 1; the INT1 polarity is defined by bit IN1PL in register IT01CF (see
SFR Definition 12.7).
332
Rev. 1.0
Si1000/1/2/3/4/5
CKCON
TMOD
IT01CF
G
A
T
E
1
C
/
T
1
T
1
M
1
T
1
M
0
G
A
T
E
0
C
/
T
0
T
0
M M
T
0
I
I
I
I
I
I
I
N
0
S
L
1
I
T
3
T
3
T
2
T
2
T
1
T S S
0 C C
N
1
P
L
N
1
S
L
2
N
1
S
L
1
N
1
S
L
0
N
0
P
L
N
0
S
L
2
N
0
S
L
0
M M M M M M A A
L H
1
0
H
L
1 0
Pre-scaled Clock
SYSCLK
0
1
0
1
TF1
TR1
TF0
TR0
IE1
T0
Interrupt
TCLK
TL0
(5 bits)
TH0
(8 bits)
TR0
IT1
GATE0
IE0
IT0
Crossbar
IN0PL
XOR
INT0
Figure 27.1. T0 Mode 0 Block Diagram
27.1.2. Mode 1: 16-bit Counter/Timer
Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The coun-
ter/timers are enabled and configured in Mode 1 in the same manner as for Mode 0.
27.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload
Mode 2 configures Timer 0 and Timer 1 to operate as 8-bit counter/timers with automatic reload of the start
value. TL0 holds the count and TH0 holds the reload value. When the counter in TL0 overflows from all
ones to 0x00, the timer overflow flag TF0 (TCON.5) is set and the counter in TL0 is reloaded from TH0. If
Timer 0 interrupts are enabled, an interrupt will occur when the TF0 flag is set. The reload value in TH0 is
not changed. TL0 must be initialized to the desired value before enabling the timer for the first count to be
correct. When in Mode 2, Timer 1 operates identically to Timer 0.
Both counter/timers are enabled and configured in Mode 2 in the same manner as Mode 0. Setting the
TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or when the input signal INT0
is active as defined by bit IN0PL in register IT01CF (see Section “12.6. External Interrupts INT0 and INT1”
on page 139 for details on the external input signals INT0 and INT1).
Rev. 1.0
333
Si1000/1/2/3/4/5
CKCON
TMOD
IT01CF
G C T T G C T T
I I I I I I I I
N N N N N N N N
T T T T T T S S
3 3 2 2 1 0 C C
M M M M M M A A
A
/
1
1 A
/
0
0
T T M M T T M M
1
1 1 1 0 0 0 0
E 1
1
1
0 E 0
0
1
0
P S S S P S S S
H L H L
1 0
L
L
2
L
1
L
0
L
L
2
L
1
L
0
Pre-scaled Clock
0
1
0
SYSCLK
1
T0
TF1
TR1
TF0
TR0
IE1
TCLK
TL0
(8 bits)
Interrupt
TR0
IT1
IE0
IT0
Crossbar
GATE0
TH0
Reload
(8 bits)
IN0PL
XOR
INT0
Figure 27.2. T0 Mode 2 Block Diagram
27.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)
In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The coun-
ter/timer in TL0 is controlled using the Timer 0 control/status bits in TCON and TMOD: TR0, C/T0, GATE0
and TF0. TL0 can use either the system clock or an external input signal as its timebase. The TH0 register
is restricted to a timer function sourced by the system clock or prescaled clock. TH0 is enabled using the
Timer 1 run control bit TR1. TH0 sets the Timer 1 overflow flag TF1 on overflow and thus controls the
Timer 1 interrupt.
Timer 1 is inactive in Mode 3. When Timer 0 is operating in Mode 3, Timer 1 can be operated in Modes 0,
1 or 2, but cannot be clocked by external signals nor set the TF1 flag and generate an interrupt. However,
the Timer 1 overflow can be used to generate baud rates for the SMBus and/or UART, and/or initiate ADC
conversions. While Timer 0 is operating in Mode 3, Timer 1 run control is handled through its mode set-
tings. To run Timer 1 while Timer 0 is in Mode 3, set the Timer 1 Mode as 0, 1, or 2. To disable Timer 1,
configure it for Mode 3.
334
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CKCON
TMOD
G C T T G C T
T
0
T T T T T T S S
3 3 2 2 1 0 C C
M M M M M M A A
A
T
E
1
/ 1 1 A / 0
T M M T T M M
1
1
0
E
0
0 1 0
H L H L
1 0
Pre-scaled Clock
SYSCLK
0
1
TH0
(8 bits)
TR1
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Interrupt
Interrupt
0
1
T0
TL0
(8 bits)
TR0
Crossbar
GATE0
IN0PL
XOR
INT0
Figure 27.3. T0 Mode 3 Block Diagram
Rev. 1.0
335
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SFR Definition 27.2. TCON: Timer Control
Bit
7
6
5
4
3
IE1
R/W
0
2
IT1
R/W
0
1
IE0
R/W
0
0
IT0
R/W
0
Name
Type
Reset
TF1
R/W
0
TR1
R/W
0
TF0
R/W
0
TR0
R/W
0
SFR Page = 0x0; SFR Address = 0x88; Bit-Addressable
Bit
Name
Function
7
TF1
Timer 1 Overflow Flag.
Set to 1 by hardware when Timer 1 overflows. This flag can be cleared by software
but is automatically cleared when the CPU vectors to the Timer 1 interrupt service
routine.
6
5
TR1
TF0
Timer 1 Run Control.
Timer 1 is enabled by setting this bit to 1.
Timer 0 Overflow Flag.
Set to 1 by hardware when Timer 0 overflows. This flag can be cleared by software
but is automatically cleared when the CPU vectors to the Timer 0 interrupt service
routine.
4
3
TR0
IE1
Timer 0 Run Control.
Timer 0 is enabled by setting this bit to 1.
External Interrupt 1.
This flag is set by hardware when an edge/level of type defined by IT1 is detected. It
can be cleared by software but is automatically cleared when the CPU vectors to the
External Interrupt 1 service routine in edge-triggered mode.
2
IT1
Interrupt 1 Type Select.
This bit selects whether the configured INT1 interrupt will be edge or level sensitive.
INT1 is configured active low or high by the IN1PL bit in the IT01CF register (see
SFR Definition 12.7).
0: INT1 is level triggered.
1: INT1 is edge triggered.
1
0
IE0
IT0
External Interrupt 0.
This flag is set by hardware when an edge/level of type defined by IT1 is detected. It
can be cleared by software but is automatically cleared when the CPU vectors to the
External Interrupt 0 service routine in edge-triggered mode.
Interrupt 0 Type Select.
This bit selects whether the configured INT0 interrupt will be edge or level sensitive.
INT0 is configured active low or high by the IN0PL bit in register IT01CF (see SFR
Definition 12.7).
0: INT0 is level triggered.
1: INT0 is edge triggered.
336
Rev. 1.0
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SFR Definition 27.3. TMOD: Timer Mode
Bit
7
GATE1
R/W
0
6
5
4
3
GATE0
R/W
0
2
1
0
Name
Type
Reset
C/T1
R/W
0
T1M[1:0]
R/W
C/T0
R/W
0
T0M[1:0]
R/W
0
0
0
0
SFR Page = 0x0; SFR Address = 0x89
Bit
Name
Function
7
GATE1
Timer 1 Gate Control.
0: Timer 1 enabled when TR1 = 1 irrespective of INT1 logic level.
1: Timer 1 enabled only when TR1 = 1 AND INT1 is active as defined by bit IN1PL in
register IT01CF (see SFR Definition 12.7).
6
C/T1
Counter/Timer 1 Select.
0: Timer: Timer 1 incremented by clock defined by T1M bit in register CKCON.
1: Counter: Timer 1 incremented by high-to-low transitions on external pin (T1).
5:4
T1M[1:0] Timer 1 Mode Select.
These bits select the Timer 1 operation mode.
00: Mode 0, 13-bit Counter/Timer
01: Mode 1, 16-bit Counter/Timer
10: Mode 2, 8-bit Counter/Timer with Auto-Reload
11: Mode 3, Timer 1 Inactive
3
GATE0
C/T0
Timer 0 Gate Control.
0: Timer 0 enabled when TR0 = 1 irrespective of INT0 logic level.
1: Timer 0 enabled only when TR0 = 1 AND INT0 is active as defined by bit IN0PL in
register IT01CF (see SFR Definition 12.7).
2
Counter/Timer 0 Select.
0: Timer: Timer 0 incremented by clock defined by T0M bit in register CKCON.
1: Counter: Timer 0 incremented by high-to-low transitions on external pin (T0).
1:0
T0M[1:0] Timer 0 Mode Select.
These bits select the Timer 0 operation mode.
00: Mode 0, 13-bit Counter/Timer
01: Mode 1, 16-bit Counter/Timer
10: Mode 2, 8-bit Counter/Timer with Auto-Reload
11: Mode 3, Two 8-bit Counter/Timers
Rev. 1.0
337
Si1000/1/2/3/4/5
SFR Definition 27.4. TL0: Timer 0 Low Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
TL0[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0x8A
Bit
Name
Function
7:0
TL0[7:0]
Timer 0 Low Byte.
The TL0 register is the low byte of the 16-bit Timer 0.
SFR Definition 27.5. TL1: Timer 1 Low Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
TL1[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0x8B
Bit
Name
Function
7:0
TL1[7:0]
Timer 1 Low Byte.
The TL1 register is the low byte of the 16-bit Timer 1.
338
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SFR Definition 27.6. TH0: Timer 0 High Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
TH0[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0x8C
Bit
Name
Function
7:0
TH0[7:0]
Timer 0 High Byte.
The TH0 register is the high byte of the 16-bit Timer 0.
SFR Definition 27.7. TH1: Timer 1 High Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
TH1[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0x8D
Bit
Name
Function
7:0
TH1[7:0]
Timer 1 High Byte.
The TH1 register is the high byte of the 16-bit Timer 1.
Rev. 1.0
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Si1000/1/2/3/4/5
27.2. Timer 2
Timer 2 is a 16-bit timer formed by two 8-bit SFRs: TMR2L (low byte) and TMR2H (high byte). Timer 2 may
operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T2SPLIT bit (TMR2CN.3) defines
the Timer 2 operation mode. Timer 2 can also be used in Capture Mode to measure the SmaRTClock or
the Comparator 0 period with respect to another oscillator. The ability to measure the Comparator 0 period
with respect to the system clock is makes using Touch Sense Switches very easy.
Timer 2 may be clocked by the system clock, the system clock divided by 12, SmaRTClock divided by 8, or
Comparator 0 output. Note that the SmaRTClock divided by 8 and Comparator 0 output is synchronized
with the system clock.
27.2.1. 16-bit Timer with Auto-Reload
When T2SPLIT (TMR2CN.3) is zero, Timer 2 operates as a 16-bit timer with auto-reload. Timer 2 can be
clocked by SYSCLK, SYSCLK divided by 12, SmaRTClock divided by 8, or Comparator 0 output. As the
16-bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in the Timer 2
reload registers (TMR2RLH and TMR2RLL) is loaded into the Timer 2 register as shown in Figure 27.4,
and the Timer 2 High Byte Overflow Flag (TMR2CN.7) is set. If Timer 2 interrupts are enabled (if IE.5 is
set), an interrupt will be generated on each Timer 2 overflow. Additionally, if Timer 2 interrupts are enabled
and the TF2LEN bit is set (TMR2CN.5), an interrupt will be generated each time the lower 8 bits (TMR2L)
overflow from 0xFF to 0x00.
CKCON
T T T T T T S S
3 3 2 2 1 0 C C
MMMMMMA A
T2XCLK[1:0]
00
H L H L
1 0
SYSCLK / 12
To ADC,
SMBus
To SMBus
TMR2H
TL2
Overflow
0
1
01
11
SmaRTClock / 8
Comparator 0
TCLK
TR2
TF2H
TMR2L
Interrupt
TF2L
TF2LEN
TF2CEN
T2SPLIT
TR2
SYSCLK
T2XCLK
TMR2RLL TMR2RLH
Reload
Figure 27.4. Timer 2 16-Bit Mode Block Diagram
27.2.2. 8-bit Timers with Auto-Reload
When T2SPLIT is set, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers oper-
ate in auto-reload mode as shown in Figure 27.5. TMR2RLL holds the reload value for TMR2L; TMR2RLH
holds the reload value for TMR2H. The TR2 bit in TMR2CN handles the run control for TMR2H. TMR2L is
always running when configured for 8-bit Mode.
340
Rev. 1.0
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Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, SmaRTClock divided by 8 or
Comparator 0 output. The Timer 2 Clock Select bits (T2MH and T2ML in CKCON) select either SYSCLK or
the clock defined by the Timer 2 External Clock Select bits (T2XCLK[1:0] in TMR2CN), as follows:
T2MH
T2XCLK[1:0]
TMR2H Clock
Source
T2ML
T2XCLK[1:0]
TMR2L Clock
Source
0
0
0
0
1
00
01
10
11
X
SYSCLK / 12
SmaRTClock / 8
Reserved
0
0
0
0
1
00
01
10
11
X
SYSCLK / 12
SmaRTClock / 8
Reserved
Comparator 0
SYSCLK
Comparator 0
SYSCLK
The TF2H bit is set when TMR2H overflows from 0xFF to 0x00; the TF2L bit is set when TMR2L overflows
from 0xFF to 0x00. When Timer 2 interrupts are enabled (IE.5), an interrupt is generated each time
TMR2H overflows. If Timer 2 interrupts are enabled and TF2LEN (TMR2CN.5) is set, an interrupt is gener-
ated each time either TMR2L or TMR2H overflows. When TF2LEN is enabled, software must check the
TF2H and TF2L flags to determine the source of the Timer 2 interrupt. The TF2H and TF2L interrupt flags
are not cleared by hardware and must be manually cleared by software.
CKCON
T T T T T T S S
3 3 2 2 1 0 C C
T2XCLK[1:0]
MMMMMM A A
Reload
TMR2RLH
To SMBus
H L H L
1 0
SYSCLK / 12
00
0
01
11
SmaRTClock / 8
Comparator 0
TCLK
TF2H
TF2L
TF2LEN
TF2CEN
T2SPLIT
TR2
TMR2H
Interrupt
TR2
1
Reload
TMR2RLL
T2XCLK
SYSCLK
1
0
To ADC,
SMBus
TCLK
TMR2L
Figure 27.5. Timer 2 8-Bit Mode Block Diagram
Rev. 1.0
341
Si1000/1/2/3/4/5
27.2.3. Comparator 0/SmaRTClock Capture Mode
The Capture Mode in Timer 2 allows either Comparator 0 or the SmaRTClock period to be measured
against the system clock or the system clock divided by 12. Comparator 0 and the SmaRTClock period can
also be compared against each other. Timer 2 Capture Mode is enabled by setting TF2CEN to 1. Timer 2
should be in 16-bit auto-reload mode when using Capture Mode.
When Capture Mode is enabled, a capture event will be generated either every Comparator 0 rising edge
or every 8 SmaRTClock clock cycles, depending on the T2XCLK1 setting. When the capture event occurs,
the contents of Timer
2
(TMR2H:TMR2L) are loaded into the Timer 2 reload registers
(TMR2RLH:TMR2RLL) and the TF2H flag is set (triggering an interrupt if Timer 2 interrupts are enabled).
By recording the difference between two successive timer capture values, the Comparator 0 or SmaRT-
Clock period can be determined with respect to the Timer 2 clock. The Timer 2 clock should be much faster
than the capture clock to achieve an accurate reading.
For example, if T2ML = 1b, T2XCLK1 = 0b, and TF2CEN = 1b, Timer 2 will clock every SYSCLK and cap-
ture every SmaRTClock clock divided by 8. If the SYSCLK is 24.5 MHz and the difference between two
successive captures is 5984, then the SmaRTClock clock is as follows:
24.5 MHz/(5984/8) = 0.032754 MHz or 32.754 kHz.
This mode allows software to determine the exact SmaRTClock frequency in self-oscillate mode and the
time between consecutive Comparator 0 rising edges, which is useful for detecting changes in the capaci-
tance of a Touch Sense Switch.
T2XCLK[1:0]
CKCON
T T T T T T S S
3 3 2 2 1 0 C C
MMMMMM A A
SYSCLK/12
Comparator 0
SmaRTClock/8
X0
H L H L
1 0
01
11
0
1
TCLK
TR2
TMR2L
TMR2H
Capture
SYSCLK
T2XCLK1
TF2CEN
TF2H
TF2L
Interrupt
TMR2RLL TMR2RLH
TF2LEN
TF2CEN
T2SPLIT
TR2
T2XCLK1
T2XCLK0
SmaRTClock/8
Comparator 0
0
1
Figure 27.6. Timer 2 Capture Mode Block Diagram
342
Rev. 1.0
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SFR Definition 27.8. TMR2CN: Timer 2 Control
Bit
7
TF2H
R/W
0
6
TF2L
R/W
0
5
TF2LEN
R/W
0
4
3
2
1
0
Name
Type
Reset
TF2CEN T2SPLIT
TR2
R/W
0
T2XCLK[1:0]
R/W
R/W
0
R/W
0
0
0
SFR Page = 0x0; SFR Address = 0xC8; Bit-Addressable
Bit
Name
Function
7
TF2H
Timer 2 High Byte Overflow Flag.
Set by hardware when the Timer 2 high byte overflows from 0xFF to 0x00. In 16 bit
mode, this will occur when Timer 2 overflows from 0xFFFF to 0x0000. When the
Timer 2 interrupt is enabled, setting this bit causes the CPU to vector to the
Timer 2 interrupt service routine. This bit is not automatically cleared by hardware.
6
5
TF2L
Timer 2 Low Byte Overflow Flag.
Set by hardware when the Timer 2 low byte overflows from 0xFF to 0x00. TF2L will
be set when the low byte overflows regardless of the Timer 2 mode. This bit is not
automatically cleared by hardware.
TF2LEN
Timer 2 Low Byte Interrupt Enable.
When set to 1, this bit enables Timer 2 Low Byte interrupts. If Timer 2 interrupts
are also enabled, an interrupt will be generated when the low byte of Timer 2 over-
flows.
4
3
TF2CEN
T2SPLIT
Timer 2 Capture Enable.
When set to 1, this bit enables Timer 2 Capture Mode.
Timer 2 Split Mode Enable.
When set to 1, Timer 2 operates as two 8-bit timers with auto-reload. Otherwise,
Timer 2 operates in 16-bit auto-reload mode.
2
TR2
Timer 2 Run Control.
Timer 2 is enabled by setting this bit to 1. In 8-bit mode, this bit enables/disables
TMR2H only; TMR2L is always enabled in split mode.
1:0 T2XCLK[1:0] Timer 2 External Clock Select.
This bit selects the “external” and “capture trigger” clock sources for Timer 2. If
Timer 2 is in 8-bit mode, this bit selects the “external” clock source for both timer
bytes. Timer 2 Clock Select bits (T2MH and T2ML in register CKCON) may still be
used to select between the “external” clock and the system clock for either timer.
Note: External clock sources are synchronized with the system clock.
00: External Clock is SYSCLK/12. Capture trigger is SmaRTClock/8.
01: External Clock is Comparator 0. Capture trigger is SmaRTClock/8.
10: External Clock is SYSCLK/12. Capture trigger is Comparator 0.
11: External Clock is SmaRTClock/8. Capture trigger is Comparator 0.
Rev. 1.0
343
Si1000/1/2/3/4/5
SFR Definition 27.9. TMR2RLL: Timer 2 Reload Register Low Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
TMR2RLL[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xCA
Bit Name
Function
7:0 TMR2RLL[7:0] Timer 2 Reload Register Low Byte.
TMR2RLL holds the low byte of the reload value for Timer 2.
SFR Definition 27.10. TMR2RLH: Timer 2 Reload Register High Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
TMR2RLH[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xCB
Bit Name
Function
7:0 TMR2RLH[7:0] Timer 2 Reload Register High Byte.
TMR2RLH holds the high byte of the reload value for Timer 2.
344
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SFR Definition 27.11. TMR2L: Timer 2 Low Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
TMR2L[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xCC
Bit Name
7:0 TMR2L[7:0] Timer 2 Low Byte.
Function
In 16-bit mode, the TMR2L register contains the low byte of the 16-bit Timer 2. In 8-
bit mode, TMR2L contains the 8-bit low byte timer value.
SFR Definition 27.12. TMR2H Timer 2 High Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
TMR2H[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xCD
Bit Name
7:0 TMR2H[7:0] Timer 2 Low Byte.
Function
In 16-bit mode, the TMR2H register contains the high byte of the 16-bit Timer 2. In 8-
bit mode, TMR2H contains the 8-bit high byte timer value.
Rev. 1.0
345
Si1000/1/2/3/4/5
27.3. Timer 3
Timer 3 is a 16-bit timer formed by two 8-bit SFRs: TMR3L (low byte) and TMR3H (high byte). Timer 3 may
operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T3SPLIT bit (TMR2CN.3) defines
the Timer 3 operation mode. Timer 3 can also be used in Capture Mode to measure the external oscillator
source or the Comparator 1 period with respect to another oscillator. The ability to measure the
Comparator 1 period with respect to the system clock is makes using Touch Sense Switches very easy.
Timer 3 may be clocked by the system clock, the system clock divided by 12, external oscillator source
divided by 8, or Comparator 1 output. The external oscillator source divided by 8 and Comparator 1 output
is synchronized with the system clock.
27.3.1. 16-bit Timer with Auto-Reload
When T3SPLIT (TMR3CN.3) is zero, Timer 3 operates as a 16-bit timer with auto-reload. Timer 3 can be
clocked by SYSCLK, SYSCLK divided by 12, external oscillator clock source divided by 8, or Comparator 1
output. As the 16-bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in
the Timer 3 reload registers (TMR3RLH and TMR3RLL) is loaded into the Timer 3 register as shown in
Figure 27.7, and the Timer 3 High Byte Overflow Flag (TMR3CN.7) is set. If Timer 3 interrupts are enabled
(if EIE1.7 is set), an interrupt will be generated on each Timer 3 overflow. Additionally, if Timer 3 interrupts
are enabled and the TF3LEN bit is set (TMR3CN.5), an interrupt will be generated each time the lower 8
bits (TMR3L) overflow from 0xFF to 0x00.
CKCON
T T T T T T S S
3 3 2 2 1 0 C C
T3XCLK[1:0]
M MM MMM A A
H L H L
1 0
SYSCLK / 12
External Clock / 8
Comparator 1
00
To ADC
0
01
11
TCLK
TR3
TF3H
TF3L
TF3LEN
TF3CEN
T3SPLIT
TR3
TMR3L
TMR3H
Interrupt
1
T3XCLK1
T3XCLK0
SYSCLK
TMR3RLL TMR3RLH
Reload
Figure 27.7. Timer 3 16-Bit Mode Block Diagram
27.3.2. 8-bit Timers with Auto-Reload
When T3SPLIT is set, Timer 3 operates as two 8-bit timers (TMR3H and TMR3L). Both 8-bit timers oper-
ate in auto-reload mode as shown in Figure 27.8. TMR3RLL holds the reload value for TMR3L; TMR3RLH
holds the reload value for TMR3H. The TR3 bit in TMR3CN handles the run control for TMR3H. TMR3L is
always running when configured for 8-bit Mode.
346
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Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, the external oscillator clock
source divided by 8, or Comparator 1. The Timer 3 Clock Select bits (T3MH and T3ML in CKCON) select
either SYSCLK or the clock defined by the Timer 3 External Clock Select bits (T3XCLK[1:0] in TMR3CN),
as follows:
T3MH
T3XCLK[1:0] TMR3H Clock
Source
T3ML
T3XCLK[1:0] TMR3L Clock
Source
0
0
0
0
1
00
01
10
11
X
SYSCLK / 12
Comparator 1
Reserved
0
0
0
0
1
00
01
10
11
X
SYSCLK / 12
Comparator 1
Reserved
External Clock / 8
SYSCLK
External Clock / 8
SYSCLK
The TF3H bit is set when TMR3H overflows from 0xFF to 0x00; the TF3L bit is set when TMR3L overflows
from 0xFF to 0x00. When Timer 3 interrupts are enabled, an interrupt is generated each time TMR3H over-
flows. If Timer 3 interrupts are enabled and TF3LEN (TMR3CN.5) is set, an interrupt is generated each
time either TMR3L or TMR3H overflows. When TF3LEN is enabled, software must check the TF3H and
TF3L flags to determine the source of the Timer 3 interrupt. The TF3H and TF3L interrupt flags are not
cleared by hardware and must be manually cleared by software.
CKCON
T T T T T T S S
3 3 2 2 1 0 C C
T3XCLK[1:0]
M M M M M M A A
Reload
TMR3RLH
H L H L
1 0
SYSCLK / 12
Comparator 1
00
0
1
01
11
TCLK
TF3H
TF3L
TMR3H
Interrupt
TR3
TF3LEN
TF3CEN
T3SPLIT
TR3
External Clock / 8
Reload
T3XCLK1
T3XCLK0
TMR3RLL
SYSCLK
1
0
TCLK
TMR3L
To ADC
Figure 27.8. Timer 3 8-Bit Mode Block Diagram.
Rev. 1.0
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Si1000/1/2/3/4/5
27.3.3. Comparator 1/External Oscillator Capture Mode
The Capture Mode in Timer 3 allows either Comparator 1 or the external oscillator period to be measured
against the system clock or the system clock divided by 12. Comparator 1 and the external oscillator
period can also be compared against each other.
Setting TF3CEN to 1 enables the Comparator 1/External Oscillator Capture Mode for Timer 3. In this
mode, T3SPLIT should be set to 0, as the full 16-bit timer is used.
When Capture Mode is enabled, a capture event will be generated either every Comparator 1 rising edge
or every 8 external clock cycles, depending on the T3XCLK1 setting. When the capture event occurs, the
contents of Timer 3 (TMR3H:TMR3L) are loaded into the Timer 3 reload registers (TMR3RLH:TMR3RLL)
and the TF3H flag is set (triggering an interrupt if Timer 3 interrupts are enabled). By recording the differ-
ence between two successive timer capture values, the Comparator 1 or external clock period can be
determined with respect to the Timer 3 clock. The Timer 3 clock should be much faster than the capture
clock to achieve an accurate reading.
For example, if T3ML = 1b, T3XCLK1 = 0b, and TF3CEN = 1b, Timer 3 will clock every SYSCLK and cap-
ture every Comparator 1 rising edge. If SYSCLK is 24.5 MHz and the difference between two successive
captures is 350 counts, then the Comparator 1 period is:
350 x (1 / 24.5 MHz) = 14.2 µs.
This mode allows software to determine the exact frequency of the external oscillator in C and RC mode or
the time between consecutive Comparator 0 rising edges, which is useful for detecting changes in the
capacitance of a Touch Sense Switch.
T3XCLK[1:0]
CKCON
T
3
T T
T
2
T
1
T S S
0 C C
3
2
M M M M M M A A
SYSCLK / 12
External Clock / 8
Comparator 1
X0
H L H L
1 0
01
11
0
1
TCLK
TR3
TMR3L
TMR3H
Capture
SYSCLK
T3XCLK1
TF3CEN
TF3H
TF3L
Interrupt
TMR3RLL TMR3RLH
TF3LEN
TF3CEN
T3SPLIT
TR3
T3XCLK1
T3XCLK0
Comparator 1
0
1
External Clock / 8
Figure 27.9. Timer 3 Capture Mode Block Diagram
348
Rev. 1.0
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SFR Definition 27.13. TMR3CN: Timer 3 Control
Bit
7
TF3H
R/W
0
6
TF3L
R/W
0
5
TF3LEN
R/W
0
4
3
2
1
0
Name
Type
Reset
TF3CEN T3SPLIT
TR3
R/W
0
T3XCLK[1:0]
R/W
R/W
0
R/W
0
0
0
SFR Page = 0x0; SFR Address = 0x91
Bit
Name
Function
7
TF3H
Timer 3 High Byte Overflow Flag.
Set by hardware when the Timer 3 high byte overflows from 0xFF to 0x00. In 16 bit
mode, this will occur when Timer 3 overflows from 0xFFFF to 0x0000. When the
Timer 3 interrupt is enabled, setting this bit causes the CPU to vector to the Timer 3
interrupt service routine. This bit is not automatically cleared by hardware.
6
5
TF3L
Timer 3 Low Byte Overflow Flag.
Set by hardware when the Timer 3 low byte overflows from 0xFF to 0x00. TF3L will
be set when the low byte overflows regardless of the Timer 3 mode. This bit is not
automatically cleared by hardware.
TF3LEN
Timer 3 Low Byte Interrupt Enable.
When set to 1, this bit enables Timer 3 Low Byte interrupts. If Timer 3 interrupts are
also enabled, an interrupt will be generated when the low byte of Timer 3 overflows.
4
3
TF3CEN
T3SPLIT
Timer 3 Comparator 1/External Oscillator Capture Enable.
When set to 1, this bit enables Timer 3 Capture Mode.
Timer 3 Split Mode Enable.
When this bit is set, Timer 3 operates as two 8-bit timers with auto-reload.
0: Timer 3 operates in 16-bit auto-reload mode.
1: Timer 3 operates as two 8-bit auto-reload timers.
2
TR3
Timer 3 Run Control.
Timer 3 is enabled by setting this bit to 1. In 8-bit mode, this bit enables/disables
TMR3H only; TMR3L is always enabled in split mode.
1:0 T3XCLK[1:0] Timer 3 External Clock Select.
This bit selects the “external” and “capture trigger” clock sources for Timer 3. If
Timer 3 is in 8-bit mode, this bit selects the “external” clock source for both timer
bytes. Timer 3 Clock Select bits (T3MH and T3ML in register CKCON) may still be
used to select between the “external” clock and the system clock for either timer.
Note: External clock sources are synchronized with the system clock.
00: External Clock is SYSCLK /12. Capture trigger is Comparator 1.
01: External Clock is External Oscillator/8. Capture trigger is Comparator 1.
10: External Clock is SYSCLK/12. Capture trigger is External Oscillator/8.
11: External Clock is Comparator 1. Capture trigger is External Oscillator/8.
Rev. 1.0
349
Si1000/1/2/3/4/5
SFR Definition 27.14. TMR3RLL: Timer 3 Reload Register Low Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
TMR3RLL[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0x92
Bit Name
Function
7:0 TMR3RLL[7:0] Timer 3 Reload Register Low Byte.
TMR3RLL holds the low byte of the reload value for Timer 3.
SFR Definition 27.15. TMR3RLH: Timer 3 Reload Register High Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
TMR3RLH[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0x93
Bit Name
Function
7:0 TMR3RLH[7:0] Timer 3 Reload Register High Byte.
TMR3RLH holds the high byte of the reload value for Timer 3.
350
Rev. 1.0
Si1000/1/2/3/4/5
SFR Definition 27.16. TMR3L: Timer 3 Low Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
TMR3L[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0x94
Bit
Name
Function
7:0
TMR3L[7:0] Timer 3 Low Byte.
In 16-bit mode, the TMR3L register contains the low byte of the 16-bit Timer 3. In
8-bit mode, TMR3L contains the 8-bit low byte timer value.
SFR Definition 27.17. TMR3H Timer 3 High Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
TMR3H[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0x95
Bit
Name
Function
7:0
TMR3H[7:0] Timer 3 High Byte.
In 16-bit mode, the TMR3H register contains the high byte of the 16-bit Timer 3. In
8-bit mode, TMR3H contains the 8-bit high byte timer value.
Rev. 1.0
351
Si1000/1/2/3/4/5
28. Programmable Counter Array
The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU
intervention than the standard 8051 counter/timers. The PCA consists of a dedicated 16-bit counter/timer
and six 16-bit capture/compare modules. Each capture/compare module has its own associated I/O line
(CEXn) which is routed through the Crossbar to Port I/O when enabled. The counter/timer is driven by a
programmable timebase that can select between seven sources: system clock, system clock divided by
four, system clock divided by twelve, the external oscillator clock source divided by 8, Timer 0 overflows, or
an external clock signal on the ECI input pin. Each capture/compare module may be configured to operate
independently in one of six modes: Edge-Triggered Capture, Software Timer, High-Speed Output, Fre-
quency Output,
8 to 11-Bit PWM, or 16-Bit PWM (each mode is described in Section
“28.3. Capture/Compare Modules” on page 355). The external oscillator clock option is ideal for real-time
clock (RTC) functionality, allowing the PCA to be clocked by a precision external oscillator while the inter-
nal oscillator drives the system clock. The PCA is configured and controlled through the system controller's
Special Function Registers. The PCA block diagram is shown in Figure 28.1
Important Note: The PCA Module 5 may be used as a watchdog timer (WDT), and is enabled in this mode
following a system reset. Access to certain PCA registers is restricted while WDT mode is enabled.
See Section 28.4 for details.
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
PCA
16-Bit Counter/Timer
CLOCK
MUX
ECI
SYSCLK
External Clock/8
Capture/Compare
Module 0
Capture/Compare
Module 1
Capture/Compare
Module 2
Capture/Compare
Module 3
Capture/Compare
Module 4
Capture/Compare
Module 5 / WDT
Crossbar
Port I/O
Figure 28.1. PCA Block Diagram
352
Rev. 1.0
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28.1. PCA Counter/Timer
The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte
(MSB) of the 16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches
the value of PCA0H into a “snapshot” register; the following PCA0H read accesses this “snapshot” register.
Reading the PCA0L Register first guarantees an accurate reading of the entire 16-bit PCA0 counter.
Reading PCA0H or PCA0L does not disturb the counter operation. The CPS2–CPS0 bits in the PCA0MD
register select the timebase for the counter/timer as shown in Table 28.1.
When the counter/timer overflows from 0xFFFF to 0x0000, the Counter Overflow Flag (CF) in PCA0MD is
set to logic 1 and an interrupt request is generated if CF interrupts are enabled. Setting the ECF bit in
PCA0MD to logic 1 enables the CF flag to generate an interrupt request. The CF bit is not automatically
cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by soft-
ware. Clearing the CIDL bit in the PCA0MD register allows the PCA to continue normal operation while the
CPU is in Idle mode.
Table 28.1. PCA Timebase Input Options
CPS2
CPS1
CPS0
Timebase
0
0
0
0
0
0
1
1
0
1
0
1
System clock divided by 12
System clock divided by 4
Timer 0 overflow
High-to-low transitions on ECI (max rate = system clock divided
by 4)
1
1
1
1
0
0
1
1
0
1
0
1
System clock
*
External oscillator source divided by 8
Reserved
Reserved
Note: External oscillator source divided by 8 is synchronized with the system clock.
IDLE
PCA0MD
PCA0CN
C W W C C C E
C C C C C C C C
F R C C C C C C
F F F F F F
I
D D P P P C
D T
L E C
L
S S S F
2 1 0
5 4 3 2 1 0
To SFR Bus
PCA0L
read
K
Snapshot
Register
SYSCLK/12
SYSCLK/4
000
001
010
011
100
101
0
Timer 0 Overflow
ECI
Overflow
To PCA Interrupt System
PCA0H
PCA0L
1
CF
SYSCLK
External Clock/8
To PCA Modules
Figure 28.2. PCA Counter/Timer Block Diagram
Rev. 1.0
353
Si1000/1/2/3/4/5
28.2. PCA0 Interrupt Sources
Figure 28.3 shows a diagram of the PCA interrupt tree. There are eight independent event flags that can
be used to generate a PCA0 interrupt. They are: the main PCA counter overflow flag (CF), which is set
upon a 16-bit overflow of the PCA0 counter, an intermediate overflow flag (COVF), which can be set on an
overflow from the 8th, 9th, 10th, or 11th bit of the PCA0 counter, and the individual flags for each PCA
channel (CCF0, CCF1, CCF2, CCF3, CCF4, and CCF5), which are set according to the operation mode of
that module. These event flags are always set when the trigger condition occurs. Each of these flags can
be individually selected to generate a PCA0 interrupt, using the corresponding interrupt enable flag (ECF
for CF, ECOV for COVF, and ECCFn for each CCFn). PCA0 interrupts must be globally enabled before any
individual interrupt sources are recognized by the processor. PCA0 interrupts are globally enabled by set-
ting the EA bit and the EPCA0 bit to logic 1.
(for n = 0 to 5)
PCA0CPMn
PCA0CN
PCA0MD
PCA0PWM
P E C C M T P E
W C A A A O W C
M O P P T G M C
1 M P N n n n F
C C C C C C C C
F R C C C C C C
F F F F F F
C WW C C C E
I D D P P P C
D T L S S S F
L E C 2 1 0
K
A C E
C C
L L
S S
E E
L L
1 0
R O C
S V O
E F V
L
5 4 3 2 1 0
6 n n n
n
n
PCA Counter/Timer 8, 9,
10 or 11-bit Overflow
Set 8, 9, 10, or 11 bit Operation
EPCA0
0
1
PCA Counter/Timer 16-
bit Overflow
0
1
EA
ECCF0
Interrupt
Priority
Decoder
0
1
0
1
0
1
PCA Module 0
(CCF0)
ECCF1
ECCF2
ECCF3
ECCF4
ECCF5
0
1
PCA Module 1
(CCF1)
0
1
PCA Module 2
(CCF2)
0
1
PCA Module 3
(CCF3)
0
1
PCA Module 4
(CCF4)
0
1
PCA Module 5
(CCF5)
Figure 28.3. PCA Interrupt Block Diagram
354
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28.3. Capture/Compare Modules
Each module can be configured to operate independently in one of six operation modes: edge-triggered
capture, software timer, high speed output, frequency output, 8 to 11-bit pulse width modulator, or 16-bit
pulse width modulator. Each module has Special Function Registers (SFRs) associated with it in the CIP-
51 system controller. These registers are used to exchange data with a module and configure the module's
mode of operation. Table 28.2 summarizes the bit settings in the PCA0CPMn and PCA0PWM registers
used to select the PCA capture/compare module’s operating mode. Note that all modules set to use 8, 9,
10, or 11-bit PWM mode must use the same cycle length (8-11 bits). Setting the ECCFn bit in a
PCA0CPMn register enables the module's CCFn interrupt.
Table 28.2. PCA0CPM and PCA0PWM Bit Settings for PCA Capture/Compare Modules
Operational Mode
PCA0CPMn
PCA0PWM
Bit Number
7 6 5 4 3 2 1 0 7 6 5 4-2
1–0
Capture triggered by positive edge on CEXn
Capture triggered by negative edge on CEXn
Capture triggered by any transition on CEXn
Software Timer
X X 1 0 0 0 0 A 0 X B XXX XX
X X 0 1 0 0 0 A 0 X B XXX XX
X X 1 1 0 0 0 A 0 X B XXX XX
X C 0 0 1 0 0 A 0 X B XXX XX
X C 0 0 1 1 0 A 0 X B XXX XX
X C 0 0 0 1 1 A 0 X B XXX XX
0 C 0 0 E 0 1 A 0 X B XXX 00
0 C 0 0 E 0 1 A D X B XXX 01
0 C 0 0 E 0 1 A D X B XXX 10
0 C 0 0 E 0 1 A D X B XXX 11
1 C 0 0 E 0 1 A 0 X B XXX XX
High Speed Output
Frequency Output
8-Bit Pulse Width Modulator (Note 7)
9-Bit Pulse Width Modulator (Note 7)
10-Bit Pulse Width Modulator (Note 7)
11-Bit Pulse Width Modulator (Note 7)
16-Bit Pulse Width Modulator
Notes:
1. X = Don’t Care (no functional difference for individual module if 1 or 0).
2. A = Enable interrupts for this module (PCA interrupt triggered on CCFn set to 1).
3. B = Enable 8th, 9th, 10th or 11th bit overflow interrupt (Depends on setting of CLSEL[1:0]).
4. C = When set to 0, the digital comparator is off. For high speed and frequency output modes, the
associated pin will not toggle. In any of the PWM modes, this generates a 0% duty cycle (output = 0).
5. D = Selects whether the Capture/Compare register (0) or the Auto-Reload register (1) for the associated
channel is accessed via addresses PCA0CPHn and PCA0CPLn.
6. E = When set, a match event will cause the CCFn flag for the associated channel to be set.
7. All modules set to 8, 9, 10 or 11-bit PWM mode use the same cycle length setting.
Rev. 1.0
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28.3.1. Edge-triggered Capture Mode
In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA coun-
ter/timer and load it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and
PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn register are used to select the type of transi-
tion that triggers the capture: low-to-high transition (positive edge), high-to-low transition (negative edge),
or either transition (positive or negative edge). When a capture occurs, the Capture/Compare Flag (CCFn)
in PCA0CN is set to logic 1. An interrupt request is generated if the CCFn interrupt for that module is
enabled. The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt ser-
vice routine, and must be cleared by software. If both CAPPn and CAPNn bits are set to logic 1, then the
state of the Port pin associated with CEXn can be read directly to determine whether a rising-edge or fall-
ing-edge caused the capture.
PCA Interrupt
PCA0CPMn
P E C C M T P E
W C A A A O W C
M O P P T G M C
1 M P N n n n F
PCA0CN
C C
F R
C C C
C C C
F F F
2 1 0
6 n n n
n
n
x x
0 0 0 x
PCA0CPLn
PCA0CPHn
0
1
CEXn
Capture
Port I/O
Crossbar
0
1
PCA
Timebase
PCA0L
PCA0H
Figure 28.4. PCA Capture Mode Diagram
Note: The CEXn input signal must remain high or low for at least 2 system clock cycles to be recognized by the
hardware.
356
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28.3.2. Software Timer (Compare) Mode
In Software Timer mode, the PCA counter/timer value is compared to the module's 16-bit capture/compare
register (PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in
PCA0CN is set to logic 1. An interrupt request is generated if the CCFn interrupt for that module is
enabled. The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt ser-
vice routine, and must be cleared by software. Setting the ECOMn and MATn bits in the PCA0CPMn regis-
ter enables Software Timer mode.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Cap-
ture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
Write to
0
PCA0CPLn
ENB
Reset
Write to
PCA0CPHn
ENB
PCA Interrupt
1
PCA0CPMn
P E C C M T P E
W C A A A O W C
M O P P T G M C
1 M P N n n n F
PCA0CN
C C C C C
F R
C C C
F F F
2 1 0
PCA0CPLn
PCA0CPHn
6 n n n
n
n
x
0
0
0 0
x
0
1
Enable
Match
16-bit Comparator
PCA
Timebase
PCA0L
PCA0H
Figure 28.5. PCA Software Timer Mode Diagram
Rev. 1.0
357
Si1000/1/2/3/4/5
28.3.3. High-Speed Output Mode
In High-Speed Output mode, a module’s associated CEXn pin is toggled each time a match occurs
between the PCA Counter and the module's 16-bit capture/compare register (PCA0CPHn and
PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1. An
interrupt request is generated if the CCFn interrupt for that module is enabled. The CCFn bit is not auto-
matically cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared
by software. Setting the TOGn, MATn, and ECOMn bits in the PCA0CPMn register enables the High-
Speed Output mode. If ECOMn is cleared, the associated pin will retain its state, and not toggle on the next
match event.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Cap-
ture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
Write to
0
PCA0CPLn
ENB
Reset
PCA0CPMn
Write to
PCA0CPHn
P E C C M T P E
W C A A A O W C
M O P P T G M C
1 M P N n n n F
ENB
1
6 n n n
n
n
x
0 0
0 x
PCA Interrupt
PCA0CN
C C C C C
F R
C C C
F F F
2 1 0
PCA0CPLn
PCA0CPHn
0
1
Enable
Match
16-bit Comparator
TOGn
Toggle
0
CEXn
Crossbar
Port I/O
1
PCA
Timebase
PCA0L
PCA0H
Figure 28.6. PCA High-Speed Output Mode Diagram
358
Rev. 1.0
Si1000/1/2/3/4/5
28.3.4. Frequency Output Mode
Frequency Output Mode produces a programmable-frequency square wave on the module’s associated
CEXn pin. The capture/compare module high byte holds the number of PCA clocks to count before the out-
put is toggled. The frequency of the square wave is then defined by Equation 28.1.
FPCA
FCEXn = ----------------------------------------
2 PCA0CPHn
Note: A value of 0x00 in the PCA0CPHn register is equal to 256 for this equation.
Equation 28.1. Square Wave Frequency Output
Where F
is the frequency of the clock selected by the CPS2–0 bits in the PCA mode register,
PCA
PCA0MD. The lower byte of the capture/compare module is compared to the PCA counter low byte; on a
match, CEXn is toggled and the offset held in the high byte is added to the matched value in PCA0CPLn.
Frequency Output Mode is enabled by setting the ECOMn, TOGn, and PWMn bits in the PCA0CPMn reg-
ister. Note that the MATn bit should normally be set to 0 in this mode. If the MATn bit is set to 1, the CCFn
flag for the channel will be set when the 16-bit PCA0 counter and the 16-bit capture/compare register for
the channel are equal.
Write to
0
PCA0CPLn
ENB
Reset
PCA0CPMn
P E C C M T P E
W C A A A O W C
M O P P T G M C
1 M P N n n n F
Write to
PCA0CPHn
ENB
PCA0CPLn
8-bit Adder
PCA0CPHn
1
Adder
Enable
6 n n n
n
n
TOGn
x
0 0 0
x
Toggle
0
CEXn
8-bit
Comparator
match
Enable
Crossbar
Port I/O
1
PCA Timebase
PCA0L
Figure 28.7. PCA Frequency Output Mode
28.3.5. 8-Bit, 9-Bit, 10-Bit and 11-Bit Pulse Width Modulator Modes
Each module can be used independently to generate a pulse width modulated (PWM) output on its associ-
ated CEXn pin. The frequency of the output is dependent on the timebase for the PCA counter/timer, and
the setting of the PWM cycle length (8, 9, 10 or 11-bits). For backwards-compatibility with the 8-bit PWM
mode available on other devices, the 8-bit PWM mode operates slightly different than 9, 10 and 11-bit
PWM modes. It is important to note that all channels configured for 8/9/10/11-bit PWM mode will use
the same cycle length. It is not possible to configure one channel for 8-bit PWM mode and another for 11-
bit mode (for example). However, other PCA channels can be configured to Pin Capture, High-Speed Out-
put, Software Timer, Frequency Output, or 16-bit PWM mode independently.
Rev. 1.0
359
Si1000/1/2/3/4/5
28.3.5.1. 8-Bit Pulse Width Modulator Mode
The duty cycle of the PWM output signal in 8-bit PWM mode is varied using the module's PCA0CPLn cap-
ture/compare register. When the value in the low byte of the PCA counter/timer (PCA0L) is equal to the
value in PCA0CPLn, the output on the CEXn pin will be set. When the count value in PCA0L overflows, the
CEXn output will be reset (see Figure 28.8). Also, when the counter/timer low byte (PCA0L) overflows from
0xFF to 0x00, PCA0CPLn is reloaded automatically with the value stored in the module’s capture/compare
high byte (PCA0CPHn) without software intervention. Setting the ECOMn and PWMn bits in the
PCA0CPMn register, and setting the CLSEL bits in register PCA0PWM to 00b enables 8-Bit Pulse Width
Modulator mode. If the MATn bit is set to 1, the CCFn flag for the module will be set each time an 8-bit
comparator match (rising edge) occurs. The COVF flag in PCA0PWM can be used to detect the overflow
(falling edge), which will occur every 256 PCA clock cycles. The duty cycle for 8-Bit PWM Mode is given in
Equation 28.2.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Cap-
ture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
256 – PCA0CPHn
Duty Cycle = ---------------------------------------------------
256
Equation 28.2. 8-Bit PWM Duty Cycle
Using Equation 28.2, the largest duty cycle is 100% (PCA0CPHn = 0), and the smallest duty cycle is
0.39% (PCA0CPHn = 0xFF). A 0% duty cycle may be generated by clearing the ECOMn bit to 0.
Write to
0
PCA0CPLn
ENB
Reset
PCA0CPHn
PCA0CPLn
Write to
PCA0CPHn
ENB
COVF
1
PCA0PWM
A E C
R C O
S O V
E V F
L
PCA0CPMn
C C
L L
S S
E E
L L
1 0
P E C C M T P E
W C A A A O W C
M O P P T G M C
1 M P N n n n F
6 n n n
n
n
0
x
0
0
0
0 0 x 0
x
8-bit
Comparator
match
SET
CLR
CEXn
Enable
S
R
Q
Q
Crossbar
Port I/O
PCA Timebase
PCA0L
Overflow
Figure 28.8. PCA 8-Bit PWM Mode Diagram
360
Rev. 1.0
Si1000/1/2/3/4/5
28.3.5.2. 9/10/11-bit Pulse Width Modulator Mode
The duty cycle of the PWM output signal in 9/10/11-bit PWM mode should be varied by writing to an “Auto-
Reload” Register, which is dual-mapped into the PCA0CPHn and PCA0CPLn register locations. The data
written to define the duty cycle should be right-justified in the registers. The auto-reload registers are
accessed (read or written) when the bit ARSEL in PCA0PWM is set to 1. The capture/compare registers
are accessed when ARSEL is set to 0.
When the least-significant N bits of the PCA0 counter match the value in the associated module’s cap-
ture/compare register (PCA0CPn), the output on CEXn is asserted high. When the counter overflows from
the Nth bit, CEXn is asserted low (see Figure 28.9). Upon an overflow from the Nth bit, the COVF flag is
set, and the value stored in the module’s auto-reload register is loaded into the capture/compare register.
The value of N is determined by the CLSEL bits in register PCA0PWM.
The 9, 10 or 11-bit PWM mode is selected by setting the ECOMn and PWMn bits in the PCA0CPMn regis-
ter, and setting the CLSEL bits in register PCA0PWM to the desired cycle length (other than 8-bits). If the
MATn bit is set to 1, the CCFn flag for the module will be set each time a comparator match (rising edge)
occurs. The COVF flag in PCA0PWM can be used to detect the overflow (falling edge), which will occur
every 512 (9-bit), 1024 (10-bit) or 2048 (11-bit) PCA clock cycles. The duty cycle for 9/10/11-Bit PWM
Mode is given in Equation 28.2, where N is the number of bits in the PWM cycle.
Important Note About PCA0CPHn and PCA0CPLn Registers: When writing a 16-bit value to the
PCA0CPn registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn
bit to 0; writing to PCA0CPHn sets ECOMn to 1.
2N – PCA0CPn
Duty Cycle = -------------------------------------------
2N
Equation 28.3. 9, 10, and 11-Bit PWM Duty Cycle
A 0% duty cycle may be generated by clearing the ECOMn bit to 0.
Write to
0
PCA0CPLn
R/W when
ARSEL = 1
ENB
(Auto-Reload)
PCA0CPH:Ln
(right-justified)
PCA0PWM
Reset
A E C
C C
L L
S S
E E
L L
1 0
R C O
S O V
E V F
L
Write to
PCA0CPHn
ENB
1
PCA0CPMn
x
R/W when
ARSEL = 0
P E C C M T P E
W C A A A O W C
M O P P T G M C
1 M P N n n n F
(Capture/Compare)
Set “N” bits:
01 = 9 bits
10 = 10 bits
11 = 11 bits
PCA0CPH:Ln
(right-justified)
6 n n n
n
n
0
0 0 x 0
x
match
SET
CEXn
Enable
N-bit Comparator
S
R
Q
Q
Crossbar
Port I/O
CLR
PCA Timebase
PCA0H:L
Overflow of Nth Bit
Figure 28.9. PCA 9, 10 and 11-Bit PWM Mode Diagram
Rev. 1.0
361
Si1000/1/2/3/4/5
28.3.6. 16-Bit Pulse Width Modulator Mode
A PCA module may also be operated in 16-Bit PWM mode. 16-bit PWM mode is independent of the other
(8/9/10/11-bit) PWM modes. In this mode, the 16-bit capture/compare module defines the number of PCA
clocks for the low time of the PWM signal. When the PCA counter matches the module contents, the out-
put on CEXn is asserted high; when the 16-bit counter overflows, CEXn is asserted low. To output a vary-
ing duty cycle, new value writes should be synchronized with PCA CCFn match interrupts. 16-Bit PWM
Mode is enabled by setting the ECOMn, PWMn, and PWM16n bits in the PCA0CPMn register. For a vary-
ing duty cycle, match interrupts should be enabled (ECCFn = 1 AND MATn = 1) to help synchronize the
capture/compare register writes. If the MATn bit is set to 1, the CCFn flag for the module will be set each
time a 16-bit comparator match (rising edge) occurs. The CF flag in PCA0CN can be used to detect the
overflow (falling edge). The duty cycle for 16-Bit PWM Mode is given by Equation 28.4.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Cap-
ture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
65536 – PCA0CPn
Duty Cycle = ----------------------------------------------------
65536
Equation 28.4. 16-Bit PWM Duty Cycle
Using Equation 28.4, the largest duty cycle is 100% (PCA0CPn = 0), and the smallest duty cycle is
0.0015% (PCA0CPn = 0xFFFF). A 0% duty cycle may be generated by clearing the ECOMn bit to 0.
Write to
0
PCA0CPLn
ENB
Reset
Write to
PCA0CPHn
ENB
1
PCA0CPMn
P E C C M T P E
W C A A A O W C
M O P P T G M C
PCA0CPHn
PCA0CPLn
1 M P N n
n
n
F
n
6
n
1
n
n
n
0
0
x
0
x
SET
CLR
match
CEXn
Enable
16-bit Comparator
S
R
Q
Q
Crossbar
Port I/O
PCA Timebase
PCA0H
PCA0L
Overflow
Figure 28.10. PCA 16-Bit PWM Mode
362
Rev. 1.0
Si1000/1/2/3/4/5
28.4. Watchdog Timer Mode
A programmable watchdog timer (WDT) function is available through the PCA Module 5. The WDT is used
to generate a reset if the time between writes to the WDT update register (PCA0CPH2) exceed a specified
limit. The WDT can be configured and enabled/disabled as needed by software.
With the WDTE bit set in the PCA0MD register, Module 5 operates as a watchdog timer (WDT). The Mod-
ule 5 high byte is compared to the PCA counter high byte; the Module 5 low byte holds the offset to be
used when WDT updates are performed. The Watchdog Timer is enabled on reset. Writes to some
PCA registers are restricted while the Watchdog Timer is enabled. The WDT will generate a reset
shortly after code begins execution. To avoid this reset, the WDT should be explicitly disabled (and option-
ally re-configured and re-enabled if it is used in the system).
28.4.1. Watchdog Timer Operation
While the WDT is enabled:
PCA counter is forced on.
Writes to PCA0L and PCA0H are not allowed.
PCA clock source bits (CPS2–CPS0) are frozen.
PCA Idle control bit (CIDL) is frozen.
Module 5 is forced into software timer mode.
Writes to the Module 5 mode register (PCA0CPM5) are disabled.
While the WDT is enabled, writes to the CR bit will not change the PCA counter state; the counter will run
until the WDT is disabled. The PCA counter run control bit (CR) will read zero if the WDT is enabled but
user software has not enabled the PCA counter. If a match occurs between PCA0CPH5 and PCA0H while
the WDT is enabled, a reset will be generated. To prevent a WDT reset, the WDT may be updated with a
write of any value to PCA0CPH5. Upon a PCA0CPH5 write, PCA0H plus the offset held in PCA0CPL5 is
loaded into PCA0CPH5 (See Figure 28.11).
PCA0MD
C W W
D D
D T
C C C E
P P P C
S S S F
2 1 0
PCA0CPH5
I
L
L E C
K
8-bit
Comparator
Match
Reset
Enable
PCA0L Overflow
PCA0CPL5
8-bit Adder
PCA0H
Adder
Enable
Write to
PCA0CPH2
Figure 28.11. PCA Module 5 with Watchdog Timer Enabled
Note that the 8-bit offset held in PCA0CPH5 is compared to the upper byte of the 16-bit PCA counter. This
offset value is the number of PCA0L overflows before a reset. Up to 256 PCA clocks may pass before the
first PCA0L overflow occurs, depending on the value of the PCA0L when the update is performed. The
total offset is then given (in PCA clocks) by Equation 28.5, where PCA0L is the value of the PCA0L register
at the time of the update.
Rev. 1.0
363
Si1000/1/2/3/4/5
Offset = 256 PCA0CPL5 + 256 – PCA0L
Equation 28.5. Watchdog Timer Offset in PCA Clocks
The WDT reset is generated when PCA0L overflows while there is a match between PCA0CPH5 and
PCA0H. Software may force a WDT reset by writing a 1 to the CCF5 flag (PCA0CN.5) while the WDT is
enabled.
28.4.2. Watchdog Timer Usage
To configure the WDT, perform the following tasks:
Disable the WDT by writing a 0 to the WDTE bit.
Select the desired PCA clock source (with the CPS2–CPS0 bits).
Load PCA0CPL5 with the desired WDT update offset value.
Configure the PCA Idle mode (set CIDL if the WDT should be suspended while the CPU is in Idle
mode).
Enable the WDT by setting the WDTE bit to 1.
Reset the WDT timer by writing to PCA0CPH5.
The PCA clock source and Idle mode select cannot be changed while the WDT is enabled. The watchdog
timer is enabled by setting the WDTE or WDLCK bits in the PCA0MD register. When WDLCK is set, the
WDT cannot be disabled until the next system reset. If WDLCK is not set, the WDT is disabled by clearing
the WDTE bit.
The WDT is enabled following any reset. The PCA0 counter clock defaults to the system clock divided by
12, PCA0L defaults to 0x00, and PCA0CPL5 defaults to 0x00. Using Equation 28.5, this results in a WDT
timeout interval of 256 PCA clock cycles, or 3072 system clock cycles. Table 28.3 lists some example time-
out intervals for typical system clocks.
Table 28.3. Watchdog Timer Timeout Intervals1
System Clock (Hz)
24,500,000
PCA0CPL5
255
Timeout Interval (ms)
32.1
16.2
24,500,000
128
24,500,000
32
4.1
2
3,062,500
255
257
2
3,062,500
128
129.5
33.1
2
3,062,500
32
32,000
32,000
32,000
255
24576
12384
3168
128
32
Notes:
1. Assumes SYSCLK/12 as the PCA clock source, and a PCA0L value
of 0x00 at the update time.
2. Internal SYSCLK reset frequency = Internal Oscillator divided by 8.
364
Rev. 1.0
Si1000/1/2/3/4/5
28.5. Register Descriptions for PCA0
Following are detailed descriptions of the special function registers related to the operation of the PCA.
SFR Definition 28.1. PCA0CN: PCA Control
Bit
7
CF
R/W
0
6
CR
R/W
0
5
CCF5
R/W
0
4
CCF4
R/W
0
3
CCF3
R/W
0
2
CCF2
R/W
0
1
CCF1
R/W
0
0
CCF0
R/W
0
Name
Type
Reset
SFR Page = 0x0; SFR Address = 0xD8; Bit-Addressable
Bit
Name
Function
7
CF
PCA Counter/Timer Overflow Flag.
Set by hardware when the PCA Counter/Timer overflows from 0xFFFF to 0x0000.
When the Counter/Timer Overflow (CF) interrupt is enabled, setting this bit causes the
CPU to vector to the PCA interrupt service routine. This bit is not automatically cleared
by hardware and must be cleared by software.
6
CR
PCA Counter/Timer Run Control.
This bit enables/disables the PCA Counter/Timer.
0: PCA Counter/Timer disabled.
1: PCA Counter/Timer enabled.
5:0 CCF[5:0] PCA Module n Capture/Compare Flag.
These bits are set by hardware when a match or capture occurs in the associated PCA
Module n. When the CCFn interrupt is enabled, setting this bit causes the CPU to
vector to the PCA interrupt service routine. This bit is not automatically cleared by
hardware and must be cleared by software.
Rev. 1.0
365
Si1000/1/2/3/4/5
SFR Definition 28.2. PCA0MD: PCA Mode
Bit
7
CIDL
R/W
0
6
WDTE
R/W
1
5
WDLCK
R/W
0
4
3
CPS2
R/W
0
2
CPS1
R/W
0
1
CPS0
R/W
0
0
Name
Type
Reset
ECF
R/W
0
R
0
SFR Page = 0x0; SFR Address = 0xD9
Bit
Name
Function
7
CIDL
PCA Counter/Timer Idle Control.
Specifies PCA behavior when CPU is in Idle Mode.
0: PCA continues to function normally while the system controller is in Idle Mode.
1: PCA operation is suspended while the system controller is in Idle Mode.
6
5
WDTE Watchdog Timer Enable.
If this bit is set, PCA Module 2 is used as the watchdog timer.
0: Watchdog Timer disabled.
1: PCA Module 2 enabled as Watchdog Timer.
WDLCK Watchdog Timer Lock.
This bit locks/unlocks the Watchdog Timer Enable. When WDLCK is set, the Watchdog
Timer may not be disabled until the next system reset.
0: Watchdog Timer Enable unlocked.
1: Watchdog Timer Enable locked.
4
Unused Read = 0b, Write = don't care.
3:1 CPS[2:0] PCA Counter/Timer Pulse Select.
These bits select the timebase source for the PCA counter
000: System clock divided by 12
001: System clock divided by 4
010: Timer 0 overflow
011: High-to-low transitions on ECI (max rate = system clock divided by 4)
100: System clock
101: External clock divided by 8 (synchronized with the system clock)
110: Reserved
111: Reserved
0
ECF
PCA Counter/Timer Overflow Interrupt Enable.
This bit sets the masking of the PCA Counter/Timer Overflow (CF) interrupt.
0: Disable the CF interrupt.
1: Enable a PCA Counter/Timer Overflow interrupt request when CF (PCA0CN.7) is
set.
Note: When the WDTE bit is set to 1, the other bits in the PCA0MD register cannot be modified. To change the
contents of the PCA0MD register, the Watchdog Timer must first be disabled.
366
Rev. 1.0
Si1000/1/2/3/4/5
SFR Definition 28.3. PCA0PWM: PCA PWM Configuration
Bit
7
ARSEL
R/W
0
6
ECOV
R/W
0
5
COVF
R/W
0
4
3
2
1
0
Name
Type
Reset
CLSEL[1:0]
R/W
R
0
R
0
R
0
0
0
SFR Page = 0x0; SFR Address = 0xDF
Bit
Name
Function
7
ARSEL
Auto-Reload Register Select.
This bit selects whether to read and write the normal PCA capture/compare registers
(PCA0CPn), or the Auto-Reload registers at the same SFR addresses. This function
is used to define the reload value for 9, 10, and 11-bit PWM modes. In all other
modes, the Auto-Reload registers have no function.
0: Read/Write Capture/Compare Registers at PCA0CPHn and PCA0CPLn.
1: Read/Write Auto-Reload Registers at PCA0CPHn and PCA0CPLn.
6
5
ECOV
COVF
Cycle Overflow Interrupt Enable.
This bit sets the masking of the Cycle Overflow Flag (COVF) interrupt.
0: COVF will not generate PCA interrupts.
1: A PCA interrupt will be generated when COVF is set.
Cycle Overflow Flag.
This bit indicates an overflow of the 8th, 9th, 10th, or 11th bit of the main PCA counter
(PCA0). The specific bit used for this flag depends on the setting of the Cycle Length
Select bits. The bit can be set by hardware or software, but must be cleared by soft-
ware.
0: No overflow has occurred since the last time this bit was cleared.
1: An overflow has occurred since the last time this bit was cleared.
4:2
Unused
Read = 000b; Write = don’t care.
1:0 CLSEL[1:0] Cycle Length Select.
When 16-bit PWM mode is not selected, these bits select the length of the PWM
cycle, between 8, 9, 10, or 11 bits. This affects all channels configured for PWM which
are not using 16-bit PWM mode. These bits are ignored for individual channels config-
ured to16-bit PWM mode.
00: 8 bits.
01: 9 bits.
10: 10 bits.
11: 11 bits.
Rev. 1.0
367
Si1000/1/2/3/4/5
SFR Definition 28.4. PCA0CPMn: PCA Capture/Compare Mode
Bit
7
6
ECOMn
R/W
0
5
CAPPn
R/W
0
4
CAPNn
R/W
0
3
MATn
R/W
0
2
TOGn
R/W
0
1
PWMn
R/W
0
0
ECCFn
R/W
0
Name PWM16n
Type
R/W
0
Reset
SFR Address, Page: PCA0CPM0 = 0xDA, 0x0; PCA0CPM1 = 0xDB, 0x0; PCA0CPM2 = 0xDC, 0x0
PCA0CPM3 = 0xDD, 0x0; PCA0CPM4 = 0xDE, 0x0; PCA0CPM5 = 0xCE, 0x0
Bit
Name
Function
7
PWM16n 16-bit Pulse Width Modulation Enable.
This bit enables 16-bit mode when Pulse Width Modulation mode is enabled.
0: 8 to 11-bit PWM selected.
1: 16-bit PWM selected.
6
5
4
3
ECOMn Comparator Function Enable.
This bit enables the comparator function for PCA module n when set to 1.
CAPPn Capture Positive Function Enable.
This bit enables the positive edge capture for PCA module n when set to 1.
CAPNn Capture Negative Function Enable.
This bit enables the negative edge capture for PCA module n when set to 1.
MATn
Match Function Enable.
This bit enables the match function for PCA module n when set to 1. When enabled,
matches of the PCA counter with a module's capture/compare register cause the CCFn
bit in PCA0MD register to be set to logic 1.
2
1
0
TOGn
Toggle Function Enable.
This bit enables the toggle function for PCA module n when set to 1. When enabled,
matches of the PCA counter with a module's capture/compare register cause the logic
level on the CEXn pin to toggle. If the PWMn bit is also set to logic 1, the module oper-
ates in Frequency Output Mode.
PWMn Pulse Width Modulation Mode Enable.
This bit enables the PWM function for PCA module n when set to 1. When enabled, a
pulse width modulated signal is output on the CEXn pin. 8 to 11-bit PWM is used if
PWM16n is cleared; 16-bit mode is used if PWM16n is set to logic 1. If the TOGn bit is
also set, the module operates in Frequency Output Mode.
ECCFn Capture/Compare Flag Interrupt Enable.
This bit sets the masking of the Capture/Compare Flag (CCFn) interrupt.
0: Disable CCFn interrupts.
1: Enable a Capture/Compare Flag interrupt request when CCFn is set.
Note: When the WDTE bit is set to 1, the PCA0CPM5 register cannot be modified, and module 5 acts as the
watchdog timer. To change the contents of the PCA0CPM5 register or the function of module 5, the Watchdog
Timer must be disabled.
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SFR Definition 28.5. PCA0L: PCA Counter/Timer Low Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
PCA0[7:0]
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Page = 0x0; SFR Address = 0xF9
Bit Name
7:0 PCA0[7:0] PCA Counter/Timer Low Byte.
Function
The PCA0L register holds the low byte (LSB) of the 16-bit PCA Counter/Timer.
Note: When the WDTE bit is set to 1, the PCA0L register cannot be modified by software. To change the contents of
the PCA0L register, the Watchdog Timer must first be disabled.
SFR Definition 28.6. PCA0H: PCA Counter/Timer High Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
PCA0[15:8]
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Page = 0x0; SFR Address = 0xFA
Bit Name
7:0 PCA0[15:8] PCA Counter/Timer High Byte.
Function
The PCA0H register holds the high byte (MSB) of the 16-bit PCA Counter/Timer.
Reads of this register will read the contents of a “snapshot” register, whose contents
are updated only when the contents of PCA0L are read (see Section 28.1).
Note: When the WDTE bit is set to 1, the PCA0H register cannot be modified by software. To change the contents of
the PCA0H register, the Watchdog Timer must first be disabled.
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SFR Definition 28.7. PCA0CPLn: PCA Capture Module Low Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
PCA0CPn[7:0]
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Addresses: PCA0CPL0 = 0xFB, PCA0CPL1 = 0xE9, PCA0CPL2 = 0xEB,
PCA0CPL3 = 0xED, PCA0CPL4 = 0xFD, PCA0CPL5 = 0xD2
SFR Pages:
PCA0CPL0 = 0x0, PCA0CPL1 = 0x0, PCA0CPL2 = 0x0,
PCA0CPL3 = 0x0, PCA0CPL4 = 0x0, PCA0CPL5 = 0x0
Bit
Name
Function
7:0 PCA0CPn[7:0] PCA Capture Module Low Byte.
The PCA0CPLn register holds the low byte (LSB) of the 16-bit capture module n.
This register address also allows access to the low byte of the corresponding
PCA channel’s auto-reload value for 9, 10, or 11-bit PWM mode. The ARSEL bit
in register PCA0PWM controls which register is accessed.
Note: A write to this register will clear the module’s ECOMn bit to a 0.
SFR Definition 28.8. PCA0CPHn: PCA Capture Module High Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
PCA0CPn[15:8]
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Addresses: PCA0CPH0 = 0xFC, PCA0CPH1 = 0xEA, PCA0CPH2 = 0xEC,
PCA0CPH3 = 0xEE, PCA0CPH4 = 0xFE, PCA0CPH5 = 0xD3
SFR Pages:
PCA0CPH0 = 0x0, PCA0CPH1 = 0x0, PCA0CPH2 = 0x0,
PCA0CPH3 = 0x0, PCA0CPH4 = 0x0, PCA0CPH5 = 0x0
Bit
Name
Function
7:0 PCA0CPn[15:8] PCA Capture Module High Byte.
The PCA0CPHn register holds the high byte (MSB) of the 16-bit capture module n.
This register address also allows access to the high byte of the corresponding
PCA channel’s auto-reload value for 9, 10, or 11-bit PWM mode. The ARSEL bit in
register PCA0PWM controls which register is accessed.
Note: A write to this register will set the module’s ECOMn bit to a 1.
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29. C2 Interface
Si1000/1/2/3/4/5 devices include an on-chip Silicon Labs 2-Wire (C2) debug interface to allow Flash pro-
gramming and in-system debugging with the production part installed in the end application. The C2 inter-
face uses a clock signal (C2CK) and a bi-directional C2 data signal (C2D) to transfer information between
the device and a host system. See the C2 Interface Specification for details on the C2 protocol.
29.1. C2 Interface Registers
The following describes the C2 registers necessary to perform Flash programming through the C2 inter-
face. All C2 registers are accessed through the C2 interface as described in the C2 Interface Specification.
C2 Register Definition 29.1. C2ADD: C2 Address
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
C2ADD[7:0]
R/W
0
0
0
0
0
0
0
0
Bit
Name
Function
7:0 C2ADD[7:0] C2 Address.
The C2ADD register is accessed via the C2 interface to select the target Data register
for C2 Data Read and Data Write commands.
Address
0x00
Description
Selects the Device ID register for Data Read instructions
Selects the Revision ID register for Data Read instructions
0x01
0x02
Selects the C2 Flash Programming Control register for Data
Read/Write instructions
0xB4
Selects the C2 Flash Programming Data register for Data
Read/Write instructions
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C2 Register Definition 29.2. DEVICEID: C2 Device ID
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
DEVICEID[7:0]
R/W
0
0
0
1
0
1
0
0
C2 Address: 0x00
Bit Name
7:0 DEVICEID[7:0] Device ID.
This read-only register returns the 8-bit device ID: 0x16 (Si1000/1/2/3/4/5).
Function
C2 Register Definition 29.3. REVID: C2 Revision ID
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
REVID[7:0]
R/W
Varies
Varies
Varies
Varies
Varies
Varies
Varies
Varies
C2 Address: 0x01
Bit Name
7:0 REVID[7:0] Revision ID.
Function
This read-only register returns the 8-bit revision ID. For example: 0x00 = Revision A.
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C2 Register Definition 29.4. FPCTL: C2 Flash Programming Control
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
FPCTL[7:0]
R/W
0
0
0
0
0
0
0
0
C2 Address: 0x02
Bit Name
7:0 FPCTL[7:0] Flash Programming Control Register.
Function
This register is used to enable Flash programming via the C2 interface. To enable C2
Flash programming, the following codes must be written in order: 0x02, 0x01. Note
that once C2 Flash programming is enabled, a system reset must be issued to
resume normal operation.
C2 Register Definition 29.5. FPDAT: C2 Flash Programming Data
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
FPDAT[7:0]
R/W
0
0
0
0
0
0
0
0
C2 Address: 0xB4
Bit Name
7:0 FPDAT[7:0] C2 Flash Programming Data Register.
Function
This register is used to pass Flash commands, addresses, and data during C2 Flash
accesses. Valid commands are listed below.
Code
0x06
0x07
0x08
0x03
Command
Flash Block Read
Flash Block Write
Flash Page Erase
Device Erase
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29.2. C2 Pin Sharing
The C2 protocol allows the C2 pins to be shared with user functions so that in-system debugging and
Flash programming may be performed. This is possible because C2 communication is typically performed
when the device is in the halt state, where all on-chip peripherals and user software are stalled. In this
halted state, the C2 interface can safely “borrow” the C2CK (RST) and C2D pins. In most applications,
external resistors are required to isolate C2 interface traffic from the user application. A typical isolation
configuration is shown in Figure 29.1.
C8051Fxxx
RST (a)
Input (b)
C2CK
C2D
Output (c)
C2 Interface Master
Figure 29.1. Typical C2 Pin Sharing
The configuration in Figure 29.1 assumes the following:
1. The user input (b) cannot change state while the target device is halted.
2. The RST pin on the target device is used as an input only.
Additional resistors may be necessary depending on the specific application.
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DOCUMENT CHANGE LIST
Revision 0.2 to Revision 1.0
Updated specification tables.
Added Temperature Sensor Settling Time Specification.
Updated power management section to indicate that the low power or precision oscillator must be
selected when entering sleep or suspend mode. Also added a recommendation of executing two NOP
instructions following the wake up from sleep mode.
Updated ADC0 Burst Mode description.
Updated DC0 inductor peak current equation.
Added a note to the OSCICL register description.
Updated Section 20.3 to indicate that when using Auto Reset, the Alarm match value should always be
set to 2 counts less than the desired match value.
Updated Port I/O chapter with additional clarification on 5 V and 3.3 V tolerance.
Updated EZRadioPRO chapter.
Updated QFN-42 landing diagram and stencil recommendations.
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CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Please visit the Silicon Labs Technical Support web page:
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without
notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences
resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the function-
ing of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon
Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose,
nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are
not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which
the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer
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Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
376
Rev. 1.0
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