SI3016-BSR [SILICON]
暂无描述;
SILICON 
Si3016
3.3 V ENHANCED GLOBAL DIRECT ACCESS ARRANGEMENT
Features
Complete DAA includes the following:
Line voltage monitor
84 dB dynamic range TX/RX
Loop current monitor
Integrated analog front end (AFE)
and 2- to 4-wire hybrid
3.2 dBm transmit/receive levels
Parallel handset detection
Integrated ring detector
Caller ID support
Ordering Information
7 µA on-hook line monitor
See page 46.
current
Pulse dialing support
Billing tone detection
3.3 V or 5 V power supply
Direct interface to DSPs
Up to 5000 V isolation
Proprietary isolation technology
Overload protection
Pin Assignments
Si3016
Programmable line interface
z
z
z
z
AC termination
DC termination
QE2
DCT
FILT2
FILT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Ring detect threshold
Ringer impedance
IGND
RX
Polarity reversal detection
REXT
REXT2
REF
C1B
RNG1
RNG2
QB
Applications
VREG2
VREG
V.90 modems
Set-top boxes
Internet appliances
VOIP systems
QE
Voice mail systems Fax machines
Description
U.S. Patent #5,870,046
U.S. Patent #6,061,009
Other Patents Pending
The Si3016 is an integrated direct access arrangement (DAA) line-side
device with a programmable line interface to meet global telephone line
interface requirements. Available in a 16-pin small outline package, it
eliminates the need for an analog front end (AFE), an isolation
transformer, relays, opto-isolators, and a 2- to 4-wire hybrid. The Si3016
dramatically reduces the number of discrete components and cost
required to achieve compliance with global regulatory requirements. The
Si3016 interfaces directly to a Silicon Laboratories integrated DAA
system-side interface.
Functional Block Diagram
Si3016
RX
FILT
FILT2
Hybrid
REF
and DC
DCT
Termination
VREG
Silicon Laboratories
Integrated DAA
VREG2
Isolation
Interface
REXT
Interface
REXT2
RNG1
RNG2
QB
Ring Detect
Off-Hook
QE
QE2
Rev. 1.0 8/06
Copyright © 2006 by Silicon Laboratories
Si3016
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si3016
2
Rev. 1.0
Si3016
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3. Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
4.1. Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
4.2. Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
4.3. Isolation Barrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
4.4. Transmit/Receive Full Scale Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
4.5. Parallel Handset Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
4.6. Line Voltage/Loop Current Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
4.7. Off-Hook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.8. DC Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.9. DC Termination Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.10. AC Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.11. Ring Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.12. Ringer Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.13. DTMF Dialing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.14. Pulse Dialing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.15. Billing Tone Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.16. Billing Tone Filter (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.17. On-Hook Line Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.18. Caller ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.19. Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4.20. Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4.21. Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.22. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.23. Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.24. Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.25. In-Circuit Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.26. Exception Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.27. Revision Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
5. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Appendix A—UL1950 3rd Edition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Appendix B—CISPR22 Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
6. Pin Descriptions: Si3016 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
8. Package Outline: SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Rev. 1.0
3
Si3016
1. Electrical Specifications
All Si3016 electrical specifications are based on the assumption that all specifications listed in the data sheet of the
host processor with the integrated system-side DAA module are met.
Table 1. Recommended Operating Conditions
1
2
2
Symbol
Test Condition
Typ
Unit
Parameter
Min
Max
70
Ambient Temperature
Ambient Temperature
Notes:
T
K-Grade
B-Grade
0
25
25
°C
°C
A
T
–40
85
A
1. The Si3016 specifications are guaranteed when the typical application circuit (including component tolerance) and any
system-side module and any Si3016 are used. See Figure 6, “Si3016 Typical Application Circuit,” on page 9.
2. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated.
4
Rev. 1.0
Si3016
Table 2. Loop Characteristics
(TA = 0 to 70 °C for K-Grade and –40 to 85 °C for B-Grade, See Figure 1)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
DC Termination Voltage
V
V
V
V
V
V
V
V
V
I = 20 mA, ACT = 1
DCT = 11 (CTR21)
—
—
7.5
V
TR
TR
TR
TR
TR
TR
TR
TR
TR
L
DC Termination Voltage
DC Termination Voltage
DC Termination Voltage
DC Termination Voltage
DC Termination Voltage
DC Termination Voltage
DC Termination Voltage
DC Termination Voltage
I = 42 mA, ACT = 1
—
—
40
—
9
—
—
—
—
—
—
—
—
14.5
40
V
V
V
V
V
V
V
V
L
DCT = 11 (CTR21)
I = 50 mA, ACT = 1
L
DCT = 11 (CTR21)
I = 60 mA, ACT = 1
—
L
DCT = 11 (CTR21)
I = 20 mA, ACT = 0
6.0
—
L
DCT = 01 (Japan)
I = 100 mA, ACT = 0
L
DCT = 01 (Japan)
I = 20 mA, ACT = 0
—
9
7.5
—
L
DCT = 10 (FCC)
I = 100 mA, ACT = 0
L
DCT = 10 (FCC)
I = 15 mA, ACT = 0
—
5.2
L
DCT = 00 (Low Voltage)
1
On Hook Leakage Current
Operating Loop Current
Operating Loop Current
I
I
I
V
= –48 V
TR
—
13
13
—
—
—
—
—
7
120
60
7
µA
mA
mA
µA
LK
LP
LP
FCC / Japan Modes
CTR21 Mode
1
DC Ring Current
dc flowing through ring
detection circuitry
2
Ring Detect Voltage
V
V
RT = 0
RT = 1
11
17
15
—
—
—
—
—
22
33
68
0.2
V
RD
RD
RMS
RMS
2
Ring Detect Voltage
V
Ring Frequency
F
Hz
R
3
Ringer Equivalence Number
REN
Notes:
1. R25 and R26 installed.
2. The ring signal is guaranteed to not be detected below the minimum. The ring signal is guaranteed to be detected above
the maximum.
3. RZ = 0. See "4.12. Ringer Impedance" on page 18.
TIP
+
600 Ω
IL
VTR
Si3016
RING
10 µF
–
Figure 1. Test Circuit for Loop Characteristics
Rev. 1.0
5
Si3016
Table 3. DC Characteristics
(TA = 0 to 70 °C for K-Grade and –40 to 85 °C for B-Grade)
Parameter
Symbol
Test Condition
Min
–10
—
Typ
—
Max
10
Unit
µA
Input Leakage Current
Power Supply Current, Analog*
I
L
I
0.3
—
mA
A
*Note: This current is required from the integrated system-side interface to communicate with the Si3016 through the isolation
interface.
Table 4. AC Characteristics
(TA = 0 to 70 °C for K-Grade and –40 to 85 °C for B-Grade; see Figure 6 on page 9)
Parameter
Symbol
Test Condition
Fs = F /5120
Min
7.2
—
Typ
—
Max
11.025
—
Unit
KHz
Hz
Sample Rate
Fs
PLL2
Transmit Frequency Response
Receive Frequency Response
Low –3 dBFS Corner
Low –3 dBFS Corner
FULL = 0 (–1 dBm)
0
—
5
—
Hz
1
Transmit Full Scale Level
V
V
—
1
—
V
FS
FS
PEAK
PEAK
PEAK
2
FULL = 1 (+3.2 dBm)
FULL = 0 (–1 dBm)
FULL = 1 (+3.2 dBm)
—
1.58
1
—
V
V
V
1,3
Receive Full Scale Level
—
—
3
—
1.58
82
—
PEAK
4,5,6
Dynamic Range
DR
DR
ACT=0, DCT=10 (FCC)
—
—
dB
I =100 mA
L
4,5,7
Dynamic Range
ACT=0, DCT=01 (Japan)
—
—
—
—
—
—
—
83
84
—
—
—
—
—
—
—
dB
dB
dB
dB
dB
dB
dB
I =20 mA
L
4,5,6
Dynamic Range
DR
ACT=1, DCT=11(CTR21)
I =60 mA
L
6,8
7,8
Transmit Total Harmonic Distortion
Transmit Total Harmonic Distortion
THD
THD
THD
THD
ACT=0, DCT=10 (FCC)
–85
–76
–74
–82
60
I =100 mA
L
ACT=0, DCT=01 (Japan)
I =20 mA
L
7,8
6,8
Receive Total Harmonic Distortion
Receive Total Harmonic Distortion
ACT=0, DCT=01 (Japan)
I =20 mA
L
ACT=1, DCT=11 (CTR21)
I =60 mA
L
Dynamic Range (Caller ID mode)
DR
VIN = 1 kHz, –13 dBm
CID
Notes:
1. Measured at TIP and RING with 600 Ω termination at 1 kHz, as shown in Figure 1.
2. R2 should be changed to a 243 Ω resistor when the FULLSCALE bit (FULL) is set to 1 (Register 18, bit 7).
3. Receive full scale level will produce –0.9 dBFS at SDO.
4. DR = 20 x log |Vin| + 20 x log (RMS signal/RMS noise).
5. Measurement is 300 to 3400 Hz. Applies to both transmit and receive paths.
6. Vin = 1 kHz, –3 dBFS, Fs = 10300 Hz.
7. Vin = 1 KHz, –6 dBFS, Fs = 10300 Hz.
8. THD = 20 x log (RMS distortion/RMS signal).
9. The AOUT pin is an optional pin located on the integrated system-side module. VD refers to the digital power supply of
the integrated system-side module.
6
Rev. 1.0
Si3016
Table 4. AC Characteristics (Continued)
(TA = 0 to 70 °C for K-Grade and –40 to 85 °C for B-Grade; see Figure 6 on page 9)
Parameter
Symbol
Test Condition
MODE = 0
Min
—
Typ
0.8
1.4
0
Max
—
Unit
Caller ID Full Scale Level (0 dB gain)
V
V
V
CID
CID
PP
PP
Caller ID Full Scale Level (ARX = 00)
V
MODE = 1
—
—
5,6
Gain Accuracy
2-W to SDO, ATX and
ARX = 000, 001, or 010
–0.5
0.5
dB
5,6
Gain Accuracy
2-W to SDO, ATX and
ARX = 011, 1xx
–1
0
1
dB
Notes:
1. Measured at TIP and RING with 600 Ω termination at 1 kHz, as shown in Figure 1.
2. R2 should be changed to a 243 Ω resistor when the FULLSCALE bit (FULL) is set to 1 (Register 18, bit 7).
3. Receive full scale level will produce –0.9 dBFS at SDO.
4. DR = 20 x log |Vin| + 20 x log (RMS signal/RMS noise).
5. Measurement is 300 to 3400 Hz. Applies to both transmit and receive paths.
6. Vin = 1 kHz, –3 dBFS, Fs = 10300 Hz.
7. Vin = 1 KHz, –6 dBFS, Fs = 10300 Hz.
8. THD = 20 x log (RMS distortion/RMS signal).
9. The AOUT pin is an optional pin located on the integrated system-side module. VD refers to the digital power supply of
the integrated system-side module.
Table 5. Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
°C
Operating Temperature Range
Storage Temperature Range
T
–40 to 100
–65 to 150
A
T
°C
STG
Note: Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Table 6. Digital FIR Filter Characteristics—Transmit and Receive
(Sample Rate = 8 kHz, TA = 70 °C for K-Grade and –40 to 85 °C for B-Grade)
Parameter
Symbol
Min
0
Typ
—
Max
3.3
3.6
0.1
—
Unit
kHz
kHz
dB
Passband (0.1 dB)
Passband (3 dB)
Passband Ripple Peak-to-Peak
Stopband
F
(0.1 dB)
F
0
—
(3 dB)
–0.1
—
—
4.4
—
kHz
dB
Stopband Attenuation
Group Delay
–74
—
—
t
12/Fs
—
sec
gd
Note: Typical FIR filter characteristics for Fs = 8000 Hz are shown in Figures 2, 3, 4, and 5.
Rev. 1.0
7
Si3016
Input Frequency—Hz
Input Frequency—Hz
Figure 2. FIR Receive Filter Response
Figure 4. FIR Transmit Filter Response
Input Frequency —Hz
Input Frequency—Hz
Figure 3. FIR Receive Filter Passband Ripple
Figure 5. FIR Transmit Filter Passband Ripple
For Figures 2–5, all filter plots apply to a sample rate of
Fs = 8 kHz. The filters scale with the sample rate as follows:
F(0.1 dB) = 0.4125 Fs
F(–3 dB) = 0.45 Fs
where Fs is the sample frequency.
8
Rev. 1.0
Si3016
6
R 1
7
9
R 1
R 1
+
5
R 1
R 7
R 8
Rev. 1.0
9
Si3016
2. Bill of Materials
Table 7. Si3016 Global Component Values
Component
Value
Supplier(s)
1
150 pF, 3 kV, X7R,±20%
Novacap, Venkel, Johanson, Murata, Panasonic
C1,C4
C2, C31, C32
Not Installed
0.22 µF, 16 V, X7R, ±20%
0.1 µF, 50 V, Elec/Tant, ±20%
0.1 µF, 16 V, X7R, ±20%
560 pF, 250 V, X7R, ±20%
10 nF, 250 V, X7R, ±20%
1.0 µF, 16 V, Tant, ±20%
0.68 µF, 16 V, X7R/Elec/Tant, ±20%
3.9 nF, 16 V, X7R, ±20%
0.01 µF, 16 V, X7R, ±20%
1800 pF, 50 V, X7R, ±20%
1000 pF, 3 kV, X7R, ±10%
Not Installed
2
C3, C13
C5
C6,C16
C7,C8
C9
Novacap, Johanson, Murata, Panasonic
Panasonic
C12
C14
C18,C19
C20
C22
1
C24,C25
3
C30
4
D1,D2
Dual Diode, 300 V, 225 mA
BAV99 Dual Diode, 70 V, 350 mW
Ferrite Bead
Central Semiconductor
Diodes Inc., OnSemiconductor, Fairchild
Murata
D3,D4
FB1,FB2
5
L1, L2
330 μH, DCR < 3 Ω, 120 mA, ±10%
A42, NPN, 300 V
Taiyo-Yuden, ACT, Transtek Magnetics, Cooper Electronics
OnSemiconductor, Fairchild
Q1,Q3
Q2
A92, PNP, 300 V
OnSemiconductor, Fairchild
6
Q4
BCP56T1, NPN, 80 V, 1/2 W
Sidactor, 275 V, 100 A
Not Installed
OnSemiconductor, Fairchild
RV1
Teccor, ST Microelectronics, Microsemi, TI
7
RV2
8
R2
402 Ω, 1/16 W, ±1%
R5
R6
100 kΩ, 1/16 W, ±1%
120 kΩ, 1/16 W, ±5%
5.36 kΩ, 1/4 W, ±1%
9
R7,R8,R15,R16,R17,R19
R9,R10
56 kΩ, 1/10 W, ±5%
R11
9.31 kΩ, 1/16 W, ±1%
78.7 Ω, 1/16 W, ±1%
R12
R13
215 Ω, 1/16 W, ±1%
R18
2.2 kΩ, 1/10 W, ±5%
R24
R25,R26
R27,R28
U1
150 Ω, 1/16 W, ±5%
10 MΩ, 1/16 W, ±5%
10 Ω, 1/10 W, ±5%
Si3021
Silicon Labs
Silicon Labs
U2
Silicon Labs System-Side Device
Zener Diode, 43 V, 1/2 W
Zener Diode, 5.6 V, 1/2 W
Z1
Vishay, Motorola, Rohm
Vishay, Motorola, Rohm
Z4,Z5
Notes:
1. Y2 class capacitors are needed for the Nordic requirements of EN60950 and may also be used to achieve surge performance of 5 kV or better.
2. C13 is used to ensure compliance with on-hook pulse dialing and spark quenching requirements in countries, such as Australia and South Africa. If this
is not a concern, a 0.1 µF cap may be used.
3. Install only if needed for improved radiated emissions performance (10 pF, 16 V, NPO, ±10%).
4. Several diode bridge configurations are acceptable (suppliers include General Semi., Diodes Inc.).
5. See Appendix B for additional requirements.
6. Q4 may require copper on board to meet 1/2 W power requirement. (Contact manufacturer for details.)
7. RV2 can be installed to improve performance from 2500 V to 3500 V for multiple longitudinal surges (270 V, MOV).
8. If supporting +3.2 dBFS voice applications, R2 should be 243 Ω and set the FULLSCALE bit (Reg 18[7]).
9. The R7, R8, R15, and R16, R17, and R19 resistors may each be replaced with a single resistor of 1.62 kΩ, 3/4 W, ±1%.
10
Rev. 1.0
Si3016
3. Analog Output
Figure 7 illustrates an optional application circuit to support the analog output capability of the DAA system-side
module for call progress monitoring purposes. The ARM bits in Register 6 allow the receive path to be attenuated
by 0, –6, or –12 dB. The ATM bits, which are also in Register 6, allow the transmit path to be attenuated by –20,
–26, or –32 dB. Both the transmit and receive paths can also be independently muted.
+5 V
C2
6
R3
3
2
C4
+
–
5
+
AOUT
C5
4
C1
C6
R1
C3
R2
Speaker
Figure 7. Optional Connection to AOUT for a Call Progress Speaker
Table 8. Component Values—Optional Connection to AOUT
Symbol
Value
C1
2200 pF, 16 V, ±20%
0.1 µF, 16 V, ±20%
100 µF, 16 V, Elec. ±20%
820 pF, 16 V, ±20%
10 kΩ, 1/10 W, ±5%
10 Ω, 1/10 W, ±5%
47 kΩ, 1/10 W, ±5%
LM386
C2, C3, C5
C4
C6
R1
R2
R3
U1
Rev. 1.0
11
Si3016
4. Functional Description
The Si3016 is an integrated direct access arrangement The Si3016 chip can be fully programmed to meet
(DAA) that provides a programmable line interface to international requirements and is compliant with FCC,
meet global telephone line interface requirements. The CTR21, JATE, and various other country-specific PTT
device implements Silicon Laboratories’ proprietary specifications as shown in Table 9. In addition, the
capacitive isolation technology which offers the highest Si3016 has been designed to meet the most stringent
level of integration by replacing an analog front end global requirements for out-of-band energy, emissions,
(AFE), an isolation transformer, relays, opto-isolators, immunity, lightning surges, and safety.
and a 2- to 4-wire hybrid with a 16-pin small outline
The Si3016 is intended for single-channel applications.
integrated circuit (SOIC) package in conjunction with a
For multi-channel applications, up to eight Si3044 DAAs
system-side module that is integrated into another
can be daisy-chained together on one serial port.
device.
Table 9. Country Specific Register Settings
Register
Country
16
DCT[1:0]
10
17
LIM
0
18
VOL
0
OHS
0
ACT
RZ
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Argentina
0
1
Australia
1
1
01
0
0
Austria
Bahrain
Belgium
0
0 or 1
11
1
0
0
0
10
0
0
0
0 or 1
11
1
0
1
Brazil
0
0
01
0
0
Bulgaria
Canada
Chile
0
1
11
1
0
0
0
10
0
0
0
0
10
0
0
1
China
0
0
01
0
0
Colombia
Croatia
0
0
10
0
0
0
1
0 or 1
1
11
1
0
1,2
CTR21
0
11
1
0
Cyprus
0
11
1
0
Czech Republic
Denmark
0
1
11
1
0
0
0 or 1
0
11
1
0
Ecuador
0
10
0
0
1
Egypt
0
0
01
0
0
El Salvador
Finland
0
0
10
0
0
0
0 or 1
0 or 1
0 or 1
0 or 1
0
11
1
0
France
0
11
1
0
Germany
Greece
0
11
1
0
0
11
1
0
Guam
0
10
0
0
Hong Kong
0
0
10
0
0
Notes:
1. See "4.9. DC Termination Considerations" on page 17 for more information.
2. CTR21 includes the following countries: Austria, Belgium, Denmark, Finland, France, Germany, Greece,
Iceland, Ireland, Italy, Luxembourg, Netherlands, Norway, Portugal, Spain, Sweden, Switzerland, and the
United Kingdom.
3. Supported for loop current ≥ 20 mA.
12
Rev. 1.0
Si3016
Table 9. Country Specific Register Settings
16
Register
Country
17
LIM
0
1
0
0
1
1
1
0
0
0
0
1
1
1
0
0
1
0
1
1
0
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
18
VOL
0
OHS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
ACT
DCT[1:0]
10
11
RZ
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
0
RT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
Hungary
Iceland
India
0
0 or 1
0
0
10
10
11
0
Indonesia
Ireland
Israel
0
0
0 or 1
0
0 or 1
11
0
Italy
0 or 1
11
0
1
Japan
0
01
01
01
10
11
0
1
Jordan
0
0
1
Kazakhstan
Kuwait
0
0
0
0
Latvia
0 or 1
0
Lebanon
Luxembourg
Macao
0 or 1
11
0
0 or 1
11
0
0
10
01
11
0
1,3
Malaysia
0
0
Malta
0 or 1
0
Mexico
0
10
11
0
Morocco
Netherlands
New Zealand
Nigeria
0 or 1
0
0 or 1
11
0
1
10
11
0
0 or 1
0
Norway
0 or 1
11
0
1
Oman
0
01
01
10
01
10
11
0
1
Pakistan
0
0
Peru
0
0
1
Philippines
0
0
Poland
0
0
Portugal
0 or 1
0
Romania
0
0
0
0
0
0
0
0
10
01
10
10
10
10
10
10
0
1
Russia
0
Saudi Arabia
Singapore
Slovakia
0
0
0
Slovenia
0
South Africa
South Korea
Notes:
0
0
1. See "4.9. DC Termination Considerations" on page 17 for more information.
2. CTR21 includes the following countries: Austria, Belgium, Denmark, Finland, France, Germany, Greece,
Iceland, Ireland, Italy, Luxembourg, Netherlands, Norway, Portugal, Spain, Sweden, Switzerland, and the
United Kingdom.
3. Supported for loop current ≥ 20 mA.
Rev. 1.0
13
Si3016
Table 9. Country Specific Register Settings
16
Register
Country
17
LIM
1
18
VOL
0
OHS
ACT
DCT[1:0]
RZ
0
RT
0
Spain
0
0
0
0
0
0
0
0
0
0
0 or 1
11
11
11
01
01
01
10
11
10
10
Sweden
0 or 1
0
0
1
0
Switzerland
0 or 1
0
0
1
0
1
Syria
0
0
0
0
0
1
Taiwan
0
0
0
0
0
1
Thailand
0
0
0
0
0
UAE
0
0 or 1
0
0
0
0
0
United Kingdom
USA
0
0
1
0
0
0
0
0
Yemen
0
0
0
0
0
Notes:
1. See "4.9. DC Termination Considerations" on page 17 for more information.
2. CTR21 includes the following countries: Austria, Belgium, Denmark, Finland, France, Germany, Greece,
Iceland, Ireland, Italy, Luxembourg, Netherlands, Norway, Portugal, Spain, Sweden, Switzerland, and the
United Kingdom.
3. Supported for loop current ≥ 20 mA.
4.1. Initialization
4.3. Isolation Barrier
When the integrated system-side module and the The Si3016 achieves an isolation barrier through low-
Si3016 are initially powered up, the DAA registers will cost, high-voltage capacitors in conjunction with Silicon
have default values that guarantee the line-side chip Laboratories’ proprietary signal processing techniques.
(Si3016) is powered down with no possibility of loading These techniques eliminate any signal degradation due
the line (i.e., off-hook). An example initialization to capacitor mismatches, common mode interference, or
procedure is outlined below:
noise coupling. As shown in Figure 6 on page 9, the C1,
C4, C24, and C25 capacitors isolate the system side
from the Si3016 (line side). All transmit, receive, control,
ring detect, and caller ID data are communicated through
this barrier.
1. Program the desired sample rate with the Sample
Rate Control Register.
2. Wait until the Si3016 PLL is locked. This time is
between 100 µs and 1 ms.
The isolated communications link is disabled by default.
To enable it, the PDL bit must be cleared. No
communication between the system-side module and
the Si3016 can occur until this bit is cleared. When the
PDL bit is cleared, a check is performed to ensure that
the line-side device is an Si3016 device. If it is not, the
system-side module will not function.
3. Write a 00H into the DAA Control 2 Register. This
powers up the line-side chip (Si3016) and enables
the AOUT for call progress monitoring.
4. Set the desired line interface parameters (i.e.,
DCT[1:0], ACT, OHS, RT, LIM[1:0], and VOL) as
defined by “Country Specific Register Settings”
shown in Table 9, “Country Specific Register
Settings,” on page 12.
4.4. Transmit/Receive Full Scale Level
After this procedure is complete, the Si3016 is ready for The Si3016 supports programmable maximum transmit
ring detection and off-hook.
and receive levels. The full-scale TX/RX level is
established by writing the FULL bit in Register 18. With
FULL = 1, the full scale TX/RX level is increased to
4.2. Power Supply
When on-hook, the Si3016 draws power across the 3.2 dBm to support certain FCC voice applications that
isolation link from the system-side module. When off- require higher TX/RX levels. When FULL = 1, R2 must
hook, power is drawn from the 2-wire line. Thus, no be changed from 402 Ω to 243 Ω. The default full scale
power supply connections are needed for the Si3016.
value is –1 dBm (FULL = 0). Note that this higher TX/
RX full-scale mode must be used in FCC/600 Ω
termination mode.
14
Rev. 1.0
Si3016
determine the following:
4.5. Parallel Handset Detection
When on-hook, detect if a line is connected.
The Si3016 is capable of detecting a parallel handset
going off-hook. When the Si3016 is off-hook, the loop
current can be monitored via the LVCS bits. A significant
drop in loop current can signal a parallel handset going
off-hook. If a parallel handset causes the LVCS bits to
read all 0s, the Drop-Out Detect (DOD) bit may be
checked to verify that a valid line still exists.
When on-hook, detect if a parallel phone is off-hook.
When off-hook, detect if a parallel phone goes on or
off-hook.
Detect if enough loop current is available to operate.
Detect if there is an overload condition which could
damage the DAA (see overload protection feature).
When on-hook, the LVCS bits may also be read to
determine the line voltage. Significant drops in line
voltage may also be used to detect a parallel handset.
For the Si3016 to operate in parallel with another
handset, the parallel handset must have a sufficiently
high dc termination to support two off-hook DAAs on the
same line. The OFF bit in Register 16 is designed to
improve parallel handset operation by changing the dc
impedance from 50 Ω to 800 Ω and reducing the DCT
pin voltage.
4.6.1. Line Voltage Measurement
The Si3016 reports the line voltage with the LVCS bits in
Register 19. LVCS has a full scale of 87 V with an LSB
of 2.75 V. The first code (0 → 1) is skewed such that a 0
indicates that the line voltage is < 3 V. The accuracy of
the LVCS bits is ±20%. The user can read these bits
directly through the LVCS register when it is on-hook
and the MODE bit is set to 1. A typical transfer function
is shown in Figure 8.
4.6.2. Loop Current Measurement
4.6. Line Voltage/Loop Current Sensing
When the Si3016 is off-hook, the LVCS bits measure
loop current in 3 mA/bit resolution. These bits enable
the user to detect another phone going off-hook by
monitoring the dc loop current. The line voltage current
sense transfer function is shown in Figure 9 and is
detailed in Table 10.
The Si3016 has the ability to measure both line voltage
and loop current. The five bit LVCS register reports line
voltage measurements when on-hook, loop current
measurements when off-hook, or on-hook line monitor
data depending on the state of the MODE, OH, and
ONHM bits. Using the LVCS bits, the user can
30
25
20
LVCS
BITS
15
10
5
0
0
3
6
9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63 66 69 72 75 78 81 84 87
Loop Voltage (V)
100
Figure 8. Typical Loop Voltage LVCS Transfer Function
Rev. 1.0
15
Si3016
Overload
30
25
20
15
CTR21
LVCS
BITS
10
5
0
0
3
6
9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63 66 69 72 75 78 81 84 87 90 93
Loop Current (mA)
140
Figure 9. Typical Loop Current LVCS Transfer Function
the 12/Fs filter group delay. If necessary, for the shortest
delay, a higher Fs may be established prior to executing
the off-hook, such as an Fs of 10.286 kHz. The delay
allows for line transients to settle prior to normal use.
Table 10. Loop Current Transfer Function
LVCS[4:0]
Condition
Insufficient line current for normal
operation. Use the DOD bit to determine if
a line is still connected.
00000
4.8. DC Termination
The Si3016 has four programmable dc termination
modes that are selected with the DCT[1:0] bits in
Register 16.
00001
11111
Minimum line current for normal operation.
FCC mode (DCT[1:0] = 10 b), shown in Figure 10, is the
default dc termination mode and supports a transmit full
scale level of –1 dBm at TIP and RING. This mode
meets FCC requirements in addition to the requirements
of many other countries.
Loop current is excessive (overload).
Overload > 140 mA in all modes except
CTR21.
Overload > 54 mA in CTR21 mode.
4.7. Off-Hook
FCC DCT Mode
12
The communication system generates an off-hook
command by setting the OH bit. With the OH bit set, the
system is in an off-hook state.
11
10
9
The off-hook state is used to seize the line for incoming/
outgoing calls and can also be used for pulse dialing.
When the DAA is on-hook, negligible dc current flows
through the hookswitch. When the DAA is placed in the
off-hook state, the hookswitch transistor pair, Q1 and
Q2, turn on. This applies a termination impedance
across TIP and RING and causes dc loop current to
flow. The termination impedance has both an ac and dc
component.
8
7
6
.01 .02 .03 .04 .05 .06 .07 .08 .09 .1 .11
Loop Current (A)
When executing an off-hook sequence, the Si3016
requires 1548/Fs seconds to complete the off-hook and
provide phone-line data on the serial link. This includes
Figure 10. FCC Mode I/V Characteristics
CTR21 mode (DCT[1:0] = 11 b), shown in Figure 11,
16
Rev. 1.0
Si3016
provides current limiting while maintaining a transmit full
scale level of –1 dBm at TIP and RING. In this mode,
the dc termination will current limit before reaching
60 mA if the LIM bit is set.
Low Voltage Mode
10.5
10
9.5
9
CTR21 DCT Mode
45
8.5
8
40
35
7.5
7
30
25
6.5
6
20
15
10
5
5.5
5.0
.01 .02 .03 .04 .05 .06 .07 .08 .09 .1 .11
Loop Current (A)
.015
.055 .06
.02 .025 .03 .035 .04 .045 .05
Loop Current (A)
Figure 13. Low Voltage Mode I/V
Characteristics
Figure 11. CTR21 Mode I/V Characteristics
4.9. DC Termination Considerations
Japan mode (DCT[1:0] = 01 b), shown in Figure 12, is a
lower voltage mode and supports a transmit full scale
level of –2.71 dBm. Higher transmit levels for DTMF
dialing are also supported. See "4.13. DTMF Dialing" on
page 19. The low-voltage requirement is dictated by
countries, such as Japan and Malaysia.
Under certain line conditions, it may be beneficial to use
other dc termination modes not intended for a particular
world region. For instance, in countries that comply with
the CTR21 standard, improved distortion characteristics
can be seen for very low loop current lines by switching
to FCC mode. Thus, after going off-hook in CTR21
mode, the loop current monitor bits (LVCS[4:0]) may be
used to measure the loop current, and if LVCS[4:0] < 6,
it is recommended that FCC mode be used.
Japan DCT Mode
10.5
10
9.5
9
Additionally, for very low-voltage countries, such as
Japan and Malaysia, the following procedure should be
used to optimize distortion characteristics and maximize
transmit levels:
8.5
8
7.5
7
1. When first going off-hook, use the Low Voltage mode
with the VOL bit set to 1.
6.5
6
2. Measure the loop current using the LVCS[4:0] bits.
5.5
3. If LVCS[4:0] ≤ 2, maintain the current settings, and
.01
.05 .06
.09 .1 .11
.07 .08
.02 .03 .04
proceed with normal operation.
Loop Current (A)
4. If LVCS[4:0] > 2 or < 6, switch to Japan mode, leave
the VOL bit set, and proceed with normal operation.
Figure 12. Japan Mode I/V Characteristics
Low Voltage mode (DCT[1:0] = 00b), shown in
Figure 13, is the lowest line voltage mode supported on
the Si3016, with a transmit full scale level of –5 dBm.
Higher transmit levels for DTMF dialing are also
supported. See "4.13. DTMF Dialing" on page 19. This
low-voltage mode is offered for situations that require
very low line voltage operation. It is important to note
that this mode should only be used when necessary, as
the dynamic range will be significantly reduced, and
thus the Si3016 will not be able to transmit or receive
large signals without clipping them.
5. If LVCS[4:0] ≥ 6, switch to FCC mode, set the VOL
bit to 0, and proceed with normal operation.
Note: A single decision of dc termination mode following off-
hook is appropriate for most applications. However,
during PTT testing, a false dc termination I/V curve
may be generated if the dc I/V curve is determined fol-
lowing a single off-hook event.
Finally, Australia has separate dc termination
requirements for line seizure versus line hold. Japan
mode may be used to satisfy both requirements.
However, if a higher transmit level for modem operation
is desired, switch to FCC mode 500 ms after the initial
Rev. 1.0
17
Si3016
off-hook. This will satisfy the Australian dc termination The RDT bit acts as a one shot. Whenever a new ring
requirements.
signal is detected, the one shot is reset. If no new ring
signals are detected prior to the one shot counter
counting down to zero, the RDT bit will return to zero.
4.10. AC Termination
The Si3016 has two ac Termination impedances, which The length of this count (in seconds) is 65536 divided
are selected with the ACT bit.
by the sample rate. The RDT will also be reset to zero
by an off-hook event.
ACT = 0 is a real, nominal 600 Ω termination, which
satisfies the impedance requirements of FCC part 68, The second ring detect method uses the internal serial
JATE, and other countries. This real impedance is set output of the integrated system-side module (SDO) to
by circuitry internal to the Si3016 as well as the resistor transmit ring data. If the link is active (PDL = 0) and the
R2 connected to the REXT pin.
device is not off-hook or not in on-hook line monitor
mode, the ring data will be sent by the system-side
module to the host processor. The waveform on SDO
depends on the state of the RFWE bit.
ACT = 1 is a complex impedance, which satisfies the
impedance requirements of Australia, New Zealand,
South Africa, CTR21, and some European NET4
countries, such as the UK and Germany. This complex When the RFWE bit is 0, SDO will be –32768 (0x8000)
impedance is set by circuitry internal to the Si3016 as while the RNG1-RNG2 voltage is between the
well as the complex network formed by R12, R13, and thresholds. When a ring is detected, SDO will transition
C14 connected to the REXT2 pin.
to +32767 while the ring signal is positive, then go back
to –32768 while the ring is near zero and negative.
Thus, a near square wave is presented on SDO that
4.11. Ring Detection
The ring signal is capacitively coupled from TIP and swings from –32768 to +32767 in cadence with the ring
RING to the RNG1 and RNG2 pins. The Si3016 signal.
supports either full- or half-wave ring detection. With
When the RFWE bit is 1, SDO will sit at approximately
full-wave ring detection, the designer can detect a
+1228 while the RNG1-RNG2 voltage is between the
polarity reversal as well as the ring signal. See "4.18.
thresholds. When the ring goes positive, SDO will
Caller ID" on page 20. The ring detection threshold is
transition to +32767. When the ring signal goes near
zero, SDO will remain near 1228. Then, as the ring
programmable with the RT bit.
The ring detector output can be monitored in one of two goes negative, the SDO will transition to –32768. This
ways. The first method uses the register bits, RDTP, will repeat in cadence with the ring signal.
RDTN, and RDT. The second method uses the SDO
output internal to the integrated system-side module.
simply to observe the MSB of the data. The MSB will
The best way to observe the ring signal on SDO is
The DSP must detect the frequency of the ring signal in toggle in cadence with the ring signal independent of
order to distinguish a ring from pulse dialing by the ring detector mode. This is adequate information for
telephone equipment connected in parallel.
determining the ring frequency. The MSB of SDO will
toggle at the same frequency as the ring signal.
A positive ringing signal is defined as a voltage greater
than the ring threshold across RNG1-RNG2. RNG1 and
RNG2 are pins 5 and 6 of the Si3016. Conversely, a
negative ringing signal is defined as a voltage less than
the negative ring threshold across RNG1-RNG2.
4.12. Ringer Impedance
The ring detector in many DAAs is ac-coupled to the
line with a large, 1 µF, 250 V decoupling capacitor. The
ring detector on the Si3016 is also capacitively coupled
to the line, but it is designed to use smaller, less
expensive 1.8 nF capacitors. Inherently, this network
produces a high ringer impedance to the line of
approximately 800 to 900 kΩ. This value is acceptable
for the majority of countries, including FCC and CTR21.
The first ring detect method uses the ring detect bits,
RDTP, RDTN, and RDT. RDTP and RDTN behavior is
based on the RNG1-RNG2 voltage. Whenever the
signal on RNG1-RNG2 is above the positive ring
threshold, the RDTP bit is set. Whenever the signal on
RNG1-RNG2 is below the negative ring threshold, the
RDTN bit is set. When the signal on RNG1-RNG2 is
between these thresholds, neither bit is set.
Several countries including Poland, South Africa, and
Slovenia, require a maximum ringer impedance that can
be met with an internally-synthesized impedance by
setting the RZ bit in Register 16.
The RDT behavior is also based on the RNG1-RNG2
voltage. When the RFWE bit is a 0 or a 1, a positive
ringing signal will set the RDT bit for a period of time.
The RDT bit will not be set for a negative ringing signal.
18
Rev. 1.0
Si3016
dealing with this problem is to put a parallel RC shunt
across the hookswitch relay. The capacitor is large
(~1 µF, 250 V) and relatively expensive. In the Si3016,
the OHS bit can be used to slowly ramp down the loop
current to pass these tests without requiring additional
components.
4.13. DTMF Dialing
In CTR21 dc termination mode, the DIAL bit should be
set during DTMF dialing if the LVCS[4:0] bits are less
than 12. Setting this bit increases headroom for large
signals. This bit should not be used during normal
operation or if the LVCS[4:0] bits are greater than 11.
4.15. Billing Tone Detection
In Japan dc termination mode, the system-side module
attenuates the transmit output by 1.7 dB to meet
headroom requirements. Similarly, in Low Voltage
termination mode, the system-side module attenuates
the transmit output by 4 dB. However, when DTMF
dialing is desired in these modes, this attenuation must
be removed. This is achieved by entering the FCC dc
termination mode and setting either the FJM or the
FLVM bits. When in the FCC dc termination modes,
these bits will enable the respective lower loop current
termination modes without the associated transmit
attenuation. Increased distortion may be observed,
which is acceptable during DTMF dialing. After DTMF
dialing is complete, the attenuation should be enabled
by returning to either the Japan dc termination mode
(DCT[1:0] = 01b) or the Low Voltage termination mode
(DCT[1:0] = 00b). The FJM and the FLVM bits have no
effect in any other termination mode other than the FCC
dc termination mode.
“Billing tones” or “metering pulses” generated by the
central office can cause modem connection difficulties.
The billing tone is typically either a 12 kHz or 16 kHz
signal and is sometimes used in Germany, Switzerland,
and South Africa. Depending on line conditions, the
billing tone may be large enough to cause major errors
related to the modem data. The Si3016 has a feature
that allows the device to provide feedback as to whether
a billing tone has occurred and when it ends.
Billing tone detection is enabled by setting the BTE bit.
Billing tones less than 1.1 V on the line will be filtered
PK
out by the low-pass digital filter on the Si3016. The ROV
bit is set when a line signal is greater than 1.1 V
,
PK
indicating a receive overload condition. The BTD bit is
set when a line signal (billing tone) is large enough to
excessively reduce the line-derived power supply of the
line-side device (Si3016). When the BTD bit is set, the
dc termination is changed to an 800 Ω dc impedance.
This ensures minimum line voltage levels even in the
presence of billing tones.
Higher DTMF levels may also be achieved if the
amplitude is increased and the peaks of the DTMF
signal are clipped at digital full scale (as opposed to
wrapping). Clipping the signal will produce some
distortion and intermodulation of the signal. Generally,
somewhat increased distortion (between 10–20%) is
acceptable during DTMF signaling. Several dB higher
DTMF levels can be achieved with this technique,
compared with a digital full-scale peak signal.
The OVL bit should be polled following a billing tone
detection. When the OVL bit returns to zero, indicating
that the billing tone has passed, the BTE bit should be
written to zero to return the dc termination to its original
state. It will take approximately one second to return to
normal dc operating conditions. The BTD and ROV bits
are sticky, and they must be written to zero to be reset.
After the BTE, ROV, and BTD bits are all cleared, the
BTE bit can be set to re-enable billing tone detection.
4.14. Pulse Dialing
Pulse dialing is accomplished by going off- and on-hook
to generate make and break pulses. The nominal rate is
10 pulses per second. Some countries have very tight
specifications for pulse fidelity, including make and
break times, make resistance, and rise and fall times. In
a traditional solid-state dc holding circuit, there are a
number of issues in meeting these requirements.
Certain line events, such as an off-hook event on a
parallel phone or a polarity reversal, may trigger the
ROV or the BTD bits, after which the billing tone detector
must be reset. The user should look for multiple events
before qualifying whether billing tones are actually
present.
Although the DAA will remain off-hook during a billing
tone event, the received data from the line will be
corrupted when a large billing tone occurs. If the user
wishes to receive data through a billing tone, an external
LC filter must be added. A modem manufacturer can
provide this filter to users in the form of a dongle that
connects on the phone line before the DAA. This keeps
the manufacturer from having to include a costly LC filter
internal to the modem when it may only be necessary to
support a few countries/customers.
The Si3016 dc holding circuit has active control of the
on-hook and off-hook transients to maintain pulse
dialing fidelity.
Spark quenching requirements in countries, such as
Italy, the Netherlands, South Africa, and Australia deal
with the on-hook transition during pulse dialing. These
tests provide an inductive dc feed, resulting in a large
voltage spike. This spike is caused by the line
inductance and the sudden decrease in current through
the loop when going on-hook. The traditional way of
Rev. 1.0
19
Si3016
Alternatively, when a billing tone is detected, the system The billing tone filter affects the ac termination and
software may notify the user that a billing tone has return loss. The current complex ac termination will
occurred. This notification can be used to prompt the pass worldwide return loss specifications both with and
user to contact the telephone company and have the without the billing tone filter by at least 3 dB. The ac
billing tones disabled or to purchase an external LC filter. termination is optimized for frequency response and
hybrid cancellation, while having greater than 4 dB of
4.16. Billing Tone Filter (Optional)
margin with or without the dongle for South Africa,
In order to operate without degradation during billing Australia, CTR21, German, and Swiss country-specific
tones in Germany, Switzerland, and South Africa, an specifications.
external LC notch filter is required. (The Si3016 can
remain off-hook during a billing tone event, but modem
4.17. On-Hook Line Monitor
data will be lost in the presence of large billing tone The Si3016 allows the user to receive line activity when
signals.) The notch filter design requires two notches, in an on-hook state. This is accomplished through a
one at 12 KHz and one at 16 KHz. Because these low-power ADC located on-chip that digitizes the signal
components are fairly expensive and few countries passed across the RNG1/2 pins and then sends this
supply billing tone support, this filter is typically placed signal digitally across the isolation link to the system-
in an external dongle or added as a population option side module. This mode is typically used to detect caller
for these countries. Figure 14 shows an example billing ID data (see the “Caller ID” section). There are two low-
tone filter.
power ADCs on the Si3016. One is enabled by setting
the ONHM bit in Register 5. This ADC draws
approximately 450 µA of current from the line when
activated. A lower-power ADC also exists on the
Si3016, which enables a reduced current draw from the
line of approximately 7 µA. This lower power ADC is
enabled by setting the MODE bit (in conjunction with the
ONHM bit) to 1. (See the MODE bit description in the
“Control Registers” section.) Regardless of which ADC
is being used, the on-hook line monitor function must be
disabled before the device is taken off-hook. Thus,
ensure that the ONHM bit is cleared before setting the
OH bit.
L1 must carry the entire loop current. The series
resistance of the inductors is important to achieve a
narrow and deep notch. This design has more than
25 dB of attenuation at both 12 KHz and 16 KHz.
C1
C2
L1
The signal to the lower power ADC can be attenuated to
accommodate larger signals. This is accomplished
through the use of the ARX[2:0] bits. It is important to
note that while these ARX bits provide gain to the
normal receive path of the DAA, they also function as
attenuation bits for the on-hook line monitor low-power
ADC. Attenuation settings include 0, 1, 2.2, 3.5, and
5 dB. It is recommended that the new lower-power ADC
be used for on-hook line monitoring.
TIP
L2
To
From Line
DAA
C3
RING
Figure 14. Billing Tone Filter
4.18. Caller ID
The Si3016 provides the designer with the ability to
pass caller ID data from the phone line to a caller ID
decoder connected to the serial port.
Table 11. Component Values—Optional Billing
Tone Filters
4.18.1. Type I Caller ID
Symbol
C1,C2
C3
Value
Type I Caller ID sends the CID data while the phone is
on-hook.
0.027 µF, 50 V, ±10%
0.01 µF, 250 V, ±10%
L1
3.3 mH, >120 mA, <10 Ω, ±10%
10 mH, >40 mA, <10 Ω, ±10%
L2
20
Rev. 1.0
Si3016
In systems where the caller ID data is passed on the
phone line between the first and second rings, the
following method should be utilized to capture the caller
ID data:
passed across the RNG 1/2 pins and presents the
data to the DSP via the SDO signal internal to the
system-side module.
6. Clear the ONHM, MODE, and OFF/SLQ2 bits after
the caller ID data has been received but prior to the
start of the second ring.
1. After identifying a ring signal using one of the
methods described in "4.11. Ring Detection" on page
18, determine when the first ring has completed.
4.18.2. Type II Caller ID
2. Set the OFF/SQL2 bit.This bit resets the ac coupling
network on the ring input in preparation for the caller
ID data. This bit should not be cleared until after the
caller ID data has been received.
Type II Caller ID sends the CID data while the DAA is
off-hook. This mode is often referred to as caller ID/
call waiting (CID/CW). To receive the CID data while off-
hook, the following procedure should be used (also see
Figure 15):
3. Assert the MODE bit and then the ONHM bit. This
enables the lower current caller ID ADC.
1. The Caller Alert Signal (CAS) tone is sent from the
Central Office (CO) and is digitized along with the
line data. The host processor must detect the
presence of this tone.
4. The low-power ADC (which is powered from the
system chip, allowing for approximately 7 µA current
draw from the line) then digitizes the caller ID data
passed across the RNG 1/2 pins and presents the
data to the DSP via the SDO signal internal to the
integrated system-side module.
2. The DAA must then check to see if there is another
parallel device on the same line. This is
accomplished by briefly going on-hook, measuring
the line voltage, and then returning to an off-hook
state.
5. Clear the ONHM, MODE, and OFF/SQL2 bits after
the caller ID data has been received but prior to the
start of the second ring.
a. Set the CALD bit to 1. This disables the
calibration that automatically occurs when going
off-hook.
In systems where the caller ID data is preceded by a
line polarity (battery) reversal, the following method
should be used to capture the caller ID data:
b. With the OH bit set to 1 and the ONHM bit set to
0, set the MODE bit to 1. This forces the DAA to
go on-hook and disables the off-hook counter
that is normally enabled when going back off-
hook.
1. Enable full wave rectified ring detection with the
RFWE bit.
2. Monitor the RDTP and RDTN register bits to identify
whether a polarity reversal or a ring signal has
occurred. A polarity reversal will trip either the RDTP
or RDTN ring detection bits, and thus the full-wave
ring detector must be used to distinguish a polarity
reversal from a ring. The lowest specified ring
frequency is 15 Hz; therefore, if a battery reversal
occurs, the DSP should wait a minimum of 40 ms to
verify that the event observed is a battery reversal
and not a ring signal. This time is greater than half
the period of the longest ring signal. If another edge
is detected during this 40 ms pause, this event is
characterized as a ring signal and not a battery
reversal.
c. Read the LVCS bits to determine the state of the
line.
d. If the LVCS bits read the typical on-hook line
voltage, there are no parallel devices active on
the line, and CID data reception can be
continued.
e. If the LVCS bits read well below the typical on-
hook line voltage, then there are one or more
devices present and active on the same line that
are not compliant with Type II CID. CID data
reception should not be continued.
f. Set the MODE bit to 0 to return to an off-hook
state.
3. Once the signal has been identified as a battery
reversal, the ac coupling network on the ring input
must be reset in preparation for the caller ID data.
Set the OFF/SLQ2 bit. This bit should not be cleared
until after the caller ID data has been received.
3. Immediately after returning to an off-hook state, the
ONHM bit must be set and left enabled for at least
30 ms. This allows the line voltage to settle before
transmitting or receiving any data. After 30 ms, the
ONHM bit should be disabled to allow normal data
transmission and reception.
4. Assert the MODE bit and then the ONHM bit. This
enables the lower current caller ID ADC.
5. The low-power ADC (which is powered from the
system chip, allowing for approximately 7 µA current
draw from the line) then digitizes the caller ID data
Rev. 1.0
21
Si3016
4. If a non-compliant parallel device is present, a reply
tone is not sent by the host tone generator, and the
CO does not proceed with sending the CID data.
operation.
7. The muting of the upstream data path by the host
processor has the effect of muting the handset in a
telephone application so the user cannot hear the
acknowledgement tone and CID data being sent.
5. If all devices on the line are Type II CID compliant,
the host must mute its upstream data output to avoid
the propagation of its reply tone and the subsequent
CID data. After muting its upstream data output, the
host processor must then send an
8. The CALD bit can be set to 0 to reenable the
automatic calibration when going off-hook.
Due to the nature of the low-power ADC, the data
presented on SDO could have up to a 10% dc offset.
The caller ID decoder must use either a high-pass or a
band-pass filter to accurately retrieve the caller ID data.
acknowledgement (ACK) tone back to the CO to
request the transmission of the CID data.
6. The CO then responds with the CID data. After
receiving this, the host processor unmutes the
upstream data output and continues with normal
5
1
2
3
4
CAS Tone
Received
Off-Hook Counter
(1548/Fs)
LINE
On-Hook
Off-Hook
Force On-Hook Fast DCT Mode
Off-Hook
Ack
OH Bit
ONHM Bit
30 ms
CALD Bit
MODE Bit
Notes:
1. The off-hook counter is used to prevent transmission or reception of data for 1548/Fs to allow time for the line voltage to
settle. If the CALD bit is 0, an automatic calibration will also be performed during this time.
2. The caller alert signal (CAS) tone is transmitted from the CO, which signals an incoming call.
3. When the MODE bit is set while the device is off-hook, the device is forced on-hook. This is done to read the line voltage
in the LVCS bits to detect parallel handsets. In this mode, no data is transmitted on the SDO pin.
4. When the device returns off-hook after being forced on-hook using the MODE bit, the normal off-hook counter is
disabled. Additionally, if the CALD bit is set, the automatic calibration will not be performed. The fast DCT mode must be
manually enabled for at least 30 ms in order to properly settle the line voltage. This is done by setting the ONHM bit after
disabling the MODE bit.
5. After allowing the line voltage to settle in fast DCT mode, normal off-hook mode should be entered by disabling the
ONHM bit. If CID data reception is desired, the appropriate signal should be sent to the CO at this time.
Figure 15. Implementing Type II Caller ID on the Si3016
Note: If the OPE bit is enabled before going off-hook, the
4.19. Overload Protection
overload protection circuit can be activated by the line
transients produced by going off-hook. To avoid this,
The Si3016 can detect if an overload condition capable
of damaging the DAA circuit is present. The DAA may
be damaged if excessive line voltage or loop current is
sustained.
the OPE bit should be 0 prior to going off-hook. This bit
can then be set ~25 ms after going off-hook to enable
the overload protection feature.
The overload protection circuit utilizes the LVCS bits to
determine an excessive line current or voltage per the
LVCS bit transfer functions outlined in Figures 8 and 9.
4.20. Analog Output
The integrated system-side module that the Si3016 is
connected to supports an analog output (AOUT) for
driving the call progress speaker found with most of
today’s modems. AOUT is an analog signal that is
comprised of a mix of the transmit and receive signals.
When off-hook, if OPE is set and LVCS = 11111, the dc
termination is disabled (800 Ω presented to the line), the
hookswitch current is reduced, and the OPD bit is set.
22
Rev. 1.0
Si3016
The receive portion of this mixed signal has a 0 dB gain, mode supports the popular wake-up-on-ring feature of
while the transmit signal has a gain of –20 dB.
many modems. To enable it, the PDN bit must be set
and the PDL bit then cleared. When the Si3016 is in
sleep mode, the host processor clock signal may be
stopped or remain active to the system-side module, but
it must be active before waking up the DAA. The
system-side module is non-functional except for the link.
To take the Si3016 out of sleep mode, the system-side
module should be reset.
The transmit and receive signals of the AOUT signal
have independent controls found in Register 6. The
ATM[1:0] bits control the transmit portion, while the
ARM[1:0] bits control the receive portion. The bits only
affect the AOUT signal and do not affect the modem
data. Figure 7 on page 11 illustrates a recommended
application circuit. In the configuration shown, the
LM386 provides a gain of 26 dB. Additional gain In summary, the powerdown/up sequence for sleep
adjustments may be made by varying the voltage mode is as follows:
divider created by R1 and R3.
1. Set the PDN bit and clear the PDL bit.
2. The system-side module clock may stay active or
4.21. Gain Control
stop.
The Si3016 supports multiple receive gain and transmit
attenuation settings. The receive path can support gains
of 0, 3, 6, 9, and 12 dB, as selected with the ARX[2:0]
3. Restore the system-side module clock before
initiating the powerup sequence.
bits. The receive path can also be muted with the RXM 4. Reset the system-side module (after system-side
bit. The transmit path can support attenuations of 0, 3,
6, 9, and 12 dB, as selected with the ATX[2:0] bits. The
transmit path can also be muted with the TXM bit.
module clock is present).
5. Program registers to desired settings.
The Si3016 also supports an additional power-down
mode. When both the PDN and PDL bits are set, the
chipset enters a complete power-down mode and draws
negligible current (deep sleep mode). In this mode, the
ring detect function does not operate. Normal operation
may be restored using the same process for taking the
DAA out of sleep mode.
The gain control bits, ARXB and ATXB, should be set to
0 at all times.
4.22. Clocking
The system-side module that the Si3016 connects to is
integrated onto a host processor and is thus clocked
from the processor. The Si3016 receives all clocking
from this system-side module and does not need any
other clock inputs. The sample rate for the Si3016 is
controlled by the Sample Rate Control register.
4.24. Calibration
The Si3016 initiates an auto-calibration by default
whenever the device goes off-hook or experiences a
loss in line power. Calibration is used to remove any
offsets in the on-chip A/D converter that could affect the
A/D dynamic range. Auto-calibration is typically initiated
after the DAA dc termination stabilizes and takes 512/Fs
seconds to complete. Due to the large variation in line
conditions and line card behavior that can be presented
to the DAA, it may be beneficial to use manual
4.23. Power Management
The Si3016 supports four basic power management
operation modes. The modes are normal operation,
reset operation, sleep mode, and full powerdown mode.
The power management modes are controlled by the
PDN and PDL bits in Register 6.
On powerup or following a reset, the DAA is in reset calibration in lieu of auto-calibration.
operation. In this mode, the PDL bit is set while the PDN
Manual calibration should be executed as close to 512/
Fs seconds as possible before valid transmit/receive
data is expected.
bit is cleared. The system-side module is fully
operational except for the link. No communication
between the system-side module and Si3016 can occur
during reset operation. Note that any register bits
associated with the Si3016 are not valid in this mode.
The following steps should be taken to implement
manual calibration:
1. The CALD (auto-calibration disable) bit must be set
to 1.
The most common mode of operation is the normal
operation. In this mode, the PDL and PDN bits are
cleared. The DAA is fully operational, and the link is
passing information between the system-side module
and the Si3016. The desired sample rate should be
programmed prior to entering this mode.
2. The MCAL (manual calibration) bit must be toggled
to one and then zero to begin and complete the
calibration.
3. The calibration will be completed in 512/Fs seconds.
The Si3016 supports a low-power sleep mode. This
Rev. 1.0
23
Si3016
connecting the RJ-11 jack (TIP and RING) to the
Si3016. To enable this mode, set the AL bit.
4.25. In-Circuit Testing
The Si3016’s advanced design provides the designer
with an increased ability to determine system
functionality during production line tests, as well as
support for end-user diagnostics. Four loopback modes
exist allowing increased coverage of system
components. For three of the test modes, a line-side
power source is needed. While a standard phone line
can be used, the test circuit in Figure 1 on page 5 is
adequate. In addition, an off-hook sequence must be
performed to connect the power source to the line-side
chip.
The final testing mode, internal analog loopback, allows
the system to test the basic operation of the transmit
and receive paths on the line-side chip and the external
components in Figure 6 on page 9. In this test mode,
the data pump provides a digital test waveform on the
system-side module. This data is passed across the
isolation barrier, transmitted to and received from the
line, passed back across the isolation barrier, and
presented back to the data pump from the system-side
module. To enable this mode, clear the HBE bit.
When the HBE bit is cleared, this will cause a dc offset
which affects the signal swing of the transmit signal. In
this test mode, it is recommended that the transmit
signal be 12 dB lower than normal transmit levels. This
lower level will eliminate clipping caused by the dc offset
which results from disabling the hybrid. It is assumed in
this test that the line ac impedance is nominally 600 Ω.
For the startup test mode, no line-side power is
necessary and no off-hook sequence is required. The
startup test mode is enabled by default. When the PDL
bit is set (the default case), the line side is in a power-
down mode and the system-side module is in a digital
loop-back mode. In this mode, data received on SDI is
passed through the internal filters and transmitted on
SDO. This path will introduce approximately 0.9 dB of
attenuation on the SDI signal received. The group delay
of both transmit and receive filters will exist between
SDI and SDO. Clearing the PDL bit disables this mode,
and the SDO data is switched to the receive data from
the line-side. When the PDL bit is cleared, the FDT bit
becomes active, indicating successful communication
between the line-side and DSP-side. This can be used
to verify that the isolation link is operational.
Note: All test modes are mutually exclusive. If more than one
test mode is enabled concurrently, the results are
unpredictable.
4.26. Exception Handling
The Si3016 provides several mechanisms to determine
if an error occurs during operation. Through the
secondary frames of the serial link, the controlling DSP
can read several status bits. The bit of highest
importance is the frame detect bit FDT. This bit indicates
that the system-side module and line-side (Si3016)
device are communicating. During normal operation,
the FDT bit can be checked before reading any bits that
indicate information about the line side. If FDT is not
set, the following bits related to the line side are invalid:
RDT, RDTN, RDTP, LCS[3:0], CBID, REVB[3:0],
LVCS[4:0], ROV, BTD, DOD, OPD, and OVL.
The remaining test modes require an off-hook sequence
to operate. The following sequence defines the off-hook
requirements:
1. Powerup or reset.
2. Program the desired sample rate.
3. Enable the line side by clearing the PDL bit.
4. Issue off-hook
Following powerup and reset, the FDT bit is not set
because the PDL bit defaults to 1. In this state, the link
is not operating, and no information about the line side
5. Delay 1548/Fs sec to allow calibration to occur.
6. Set the desired test mode.
The isolation link digital loopback mode allows the data can be determined. The user must program the desired
pump to provide a digital input test pattern on the sample rate and clear the PDL bit to activate the link.
system-side module and receive that digital test pattern While the system and line side are establishing
back on the system-side module. To enable this mode, communication, the system-side does not generate
set the DL bit. In this mode, the isolation barrier is FSYNC signals. Establishing communication will take
actually being tested. The digital stream is delivered less than 10 ms.
across the isolation capacitor, C1, of Figure 6 on page 9
to the line side device and returned across the same
an off-hook request successfully. If the line side is not
barrier. Note that in this mode, the 0.9 dB attenuation
The FDT bit can also indicate if the line side executes
connected to a phone line (i.e., the user fails to connect
a phone line to the modem), the FDT bit remains
and filter group delays also exist.
The analog loopback mode allows an external device to cleared. The controlling processor must allow sufficient
drive a signal on the telephone line into the Si3016 line- time for the line side to execute the off-hook request.
side device and have it driven back out onto the line. The maximum time for FDT to be valid following an off-
This mode allows testing of external components hook request is 10 ms. If the FDT bit is high, the
24
Rev. 1.0
Si3016
LVCS[4:0] bits indicate the amount of loop current
flowing. If the FDT fails to be set following an off-hook
request, the PDL bit in Register 6 must be set high for at
least 1 ms to reset the line side.
Another useful bit is the communication link error (CLE)
bit. The CLE bit indicates a timeout error for the
isolation link. This condition indicates a severe error in
programming or possibly a defective line-side chip.
4.27. Revision Identification
The Si3016 provides the system designer the ability to
determine the revision of the system-side module and/
or the Si3016. The REVA[3:0] bits identify the revision of
the system-side module. The REVB[3:0] and CBID bits
identify the revision of the Si3016. Table 12 lists revision
values for both chips.
Table 12. Revision Values
Revision
System-Side
Module
Si3016
C
D
E
F
1010
—
—
1100
1101
1110
—
—
Rev. 1.0
25
Si3016
5. Control Registers
Note: Any register not listed here is reserved and must not be written.
Table 13. Register Summary
Register Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
DL
Bit 0
RXE
OH
1
2
Control 1
SR
Control 2
AL
HBE
3:4
5
Reserved
DAA Control 1
DAA Control 2
Reserved
RDTN
RDTP
ONHM
PDN
RDT
6
ATM[1] ARM[1]
PDL
ATM[0] ARM[0]
7:8
9
Sample Rate Control
Reserved
SRC[2:0]
10
11
12
13
14
15
16
Chip A Revision
Line Side Status
Chip B Revision
Line Side Validation
TX/RX Gain Control
International Control 1
REVA[3:0]
LCS[3:0]
ARXB
CLE
TXM
FDT
CBID
REVB[3:0]
ATXB
SAFE
CHK
CIP
ARX[2:0]
RZ
ATX[2:0]
RXM
OFF/
OHS
ACT
DCT[1:0]
RT
SQL2
17
18
19
International Control 2
International Control 3
International Control 4
MCAL
DIAL
CALD
FJM
LIM
OPE
BTE
ROV
BTD
FULL
VOL
FLVM MODE RFWE SQLH
OVL DOD OPD
LVCS[4:0]
26
Rev. 1.0
Si3016
Register 1. Control 1
Bit
D7
SR
D6
D5
D4
D3
D2
D1
DL
D0
Name
Type
R/W
R/W
Reset settings = 0000_0000
Bit
Name
Function
7
SR
Software Reset.
0 = Enables chip for normal operation.
1 = Sets all registers to their reset value.
Note: Bit will automatically clear after being set.
6:2 Reserved Read returns zero.
1
0
DL
Isolation Digital Loopback.
0 = Digital loopback across isolation barrier disabled.
1 = Enables digital loopback mode across isolation barrier. The line side must be enabled
prior to setting this mode.
Reserved Read returns zero.
Register 2. Control 2
Bit
D7
D6
D5
D4
D3
AL
D2
D1
D0
Name
Type
HBE
R/W
RXE
R/W
R/W
Reset settings = 0000_0011
Bit
Name
Function
7:4 Reserved Read returns zero.
3
AL
Analog Loopback.
0 = Analog loopback mode disabled.
1 = Enables external analog loopback mode.
Reserved Read returns zero.
2
1
HBE
Hybrid Enable.
0 = Disconnects hybrid in transmit path.
1 = Connects hybrid in transmit path.
0
RXE
Receive Enable.
0 = Receive path disabled.
1 = Enables receive path.
Rev. 1.0
27
Si3016
Register 3. Reserved
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
Reset settings = 0000_0000
Bit Name
Function
7:0 Reserved Read returns zero.
Register 4. Reserved
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
Reset settings = 0000_0000
Bit
Name
Function
7:0 Reserved Read returns zero.
28
Rev. 1.0
Si3016
Register 5. DAA Control 1
Bit
D7
D6
RDTN
R
D5
RDTP
R
D4
D3
D2
RDT
R
D1
D0
OH
Name
Type
ONHM
R/W
R/W
Reset settings = 0000_0000
Bit
7
Name
Reserved Read returns zero.
Function
6
RDTN
Ring Detect Signal Negative.
0 = No negative ring signal is occurring.
1 = A negative ring signal is occurring.
5
RDTP
Ring Detect Signal Positive.
0 = No positive ring signal is occurring.
1 = A positive ring signal is occurring.
4
3
Reserved Read returns zero.
ONHM
On-Hook Line Monitor.
0 = Normal on-hook mode.
1 = Enables low-power monitoring mode allowing the DSP to receive line activity without
going off-hook. This mode is used for caller-ID detection.
When MODE bit = 1 (Register 18, bit 2), the device consumes ~7 µA from the phone line
when in on-hook line monitor mode. When MODE = 0, the device consumes ~450 µA from
the phone line when in on-hook line monitor mode.
Note: This bit should be cleared before setting the OH bit.
2
RDT
Ring Detect.
0 = Reset either 4.5–9 seconds after last positive ring is detected or when the system exe-
cutes an off-hook.
1 = Indicates a ring is occurring.
1
0
Reserved Read returns zero.
OH
Off-Hook.
0 = Line-side device on-hook.
1 = Causes the line-side chip to go off-hook. This bit operates independently of the OHE bit
and is a logic OR with the off-hook pin when enabled. When the MODE bit (Register 12, bit 2)
is set to 1, the device will go on-hook without enabling the off-hook counter, thus allowing the
device to go immediately (i.e., no timeout required on the counter) back off-hook when the
MODE bit is cleared. This is useful in supporting Type II caller ID.
Note: The ONHM bit should be cleared before setting this bit.
Rev. 1.0
29
Si3016
Register 6. DAA Control 2
Bit
D7
D6
D5
ARM[1]
R/W
D4
D3
D2
D1
ATM[0]
R/W
D0
ARM[0]
R/W
Name
Type
ATM[1]
R/W
PDL
R/W
PDN
R/W
Reset settings = 0111_0000
Bit
7
Name
Reserved Read returns zero.
ATM[1:0] AOUT Transmit Path Level Control.
Function
6,1
00 = –26 dB transmit path attenuation for call progress AOUT pin only.
01 = –20 dB transmit path attenuation for call progress AOUT pin only.
10 = Mutes transmit path for call progress AOUT pin only.
11 = –32 dB transmit path attenuation for call progress AOUT pin only.
5,0
ARM[1:0] AOUT Receive Path Level Control.
00 = –6 dB receive path attenuation for call progress AOUT pin only.
01 = 0 dB receive path attenuation for call progress AOUT pin only.
10 = Mutes receive path for call progress AOUT pin only.
11 = –12 dB receive path attenuation for call progress AOUT pin only.
4
3
PDL
PDN
Powerdown Line-Side Chip.
0 = Normal operation. Program the clock generator before clearing this bit.
1 = Places the Si3016 in lower power mode.
Powerdown.
0 = Normal operation.
1 = Powers down the system-side module. An internal RESET to the system-side module is
required to restore normal operation.
2
Reserved Read returns zero.
Register 7. Reserved
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
Bit
Name
Function
7:0 Reserved Read returns zero.
30
Rev. 1.0
Si3016
Register 8. Reserved
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
Bit
Name
Function
7:0 Reserved Read returns zero.
Register 9. Sample Rate Control
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
SRC[2:0]
R/W
Reset settings = 0000_0000
Bit
7:3 Reserved Read returns zero.
2:0 SRC[2:0] Sample Rate Control.
Name
Function
This 3-bit value controls the sampling rate of the DAA.
000 = 7200 Hz.
001 = 8000 Hz.
010 = 8229 Hz.
011 = 8400 Hz.
100 = 9000 Hz.
101 = 9600 Hz.
110 = 10286 Hz.
111 = Reserved.
Register 10. Reserved
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
Bit
Name
Function
7:0 Reserved Read returns zero.
Rev. 1.0
31
Si3016
Register 11. Chip A Revision
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
REVA[3:0]
R
Reset settings = N/A
Bit Name
Function
7:4 Reserved Read returns zero.
3:0 REVA[3:0] Chip A Revision.
Four-bit value indicating the revision of the integrated system-side module.
Register 12. Line Side Status
Bit
D7
D6
FDT
R
D5
D4
D3
D2
D1
D0
Name
Type
CLE
R/W
LCS[3:0]
R
Reset settings = N/A
Bit
Name
Function
7
CLE
Communications (isolation link) Error.
0 = Communication link between the integrated system-side module and Si3016 is operating
correctly.
1 = Indicates a communication problem between the integrated system-side module and the
Si3016. When it goes high, it remains high until a logic 0 is written to it.
6
FDT
Frame Detect.
0 = Indicates link has not established frame lock.
1 = Indicates link frame lock has been established.
5:4 Reserved Read returns zero.
3:0 LCS[3:0] Loop Current Sense.
Four-bit value returning the loop current. It is decoded from the LVCS bits. See LVCS bits for
line voltage and current monitoring. When off-hook, these bits are decoded as follows from
LVCS[4:0]:
LCS[3:0] = LVCS[4:1] except
when LVCS[4:0] = 11110, LCS[3:0] = 1110 or
when LVCS[4:0] = 00001, LCS[3:0] = 0001.
When on-hook, LCS[3:0] = LVCS[4:1].
32
Rev. 1.0
Si3016
Register 13. Chip B Revision
Bit
D7
D6
CBID
R
D5
D4
D3
D2
D1
D0
ARXB
R/W
ATXB
R/W
Name
Type
REVB[3:0]
R
Reset settings = N/A
Bit
7
Name
Reserved Read returns zero.
CBID Chip B ID.
Function
6
0 = Indicates the line side is domestic only.
1 = Indicates the line side has international support.
5:2 REVB[3:0] Chip B Revision.
Four-bit value indicating the revision of the Si3016 (line-side) chip.
1
ARXB
Receive Gain.
0 = 0 dB gain is applied.
1 = A 6 dB gain is applied to the receive path.
Note: This bit should not be used. The Si3016 has the additional receive gain settings ARX[2:0]. ARXB
should be set to 0 and the ARX bits should be used.
0
ATXB
Transmit Attenuation.
0 = 0 dB gain is applied.
1 = A 3 dB attenuation is applied to the transmit path.
Note: This bit should not be used. The Si3016 has the additional transmit gain settings ATX[2:0]. ATXB
should be set to 0 and the ATX bits should be used.
Rev. 1.0
33
Si3016
Register 14. Line Side Validation
Bit
D7
D6
D5
D4
D3
D2
CHK
R
D1
CIP
R
D0
SAFE
R
Name
Type
Reset settings = 0000_0100
Bit
Name
Function
7:3 Reserved Read returns zero.
2
CHK
Line-Side Chip Verification Performed.
When the line-side device is first enabled, an automatic safety check is performed internally to
ensure that it is the correct device.
0 = A check has been performed on the line-side chip to ensure that it is the proper device.
1 = A check has not yet been performed on the line-side device to ensure that it is the proper
device.
1
0
CIP
Line-Side Chip Verification In Progress
0 = The line-side device check is not in progress.
1 = The line-side device check is currently in progress.
SAFE
Line-Side Chip Verification Result.
This bit is only valid after a line side verification check has been performed. Thus, the CHK
and CIP bits should be clear when this bit is read.
0 = A correct line-side device was detected. Chip operation is normal.
1 = An incorrect line-side device was detected. The integrated system-side module will not
function properly. Register accesses can still be performed, but data transfer will not occur.
34
Rev. 1.0
Si3016
Register 15. TX/RX Gain Control
Bit
D7
D6
D5
ATX[2:0]
R/W
D4
D3
D2
D1
D0
Name
Type
TXM
R/W
RXM
R/W
ARX[2:0]
R/W
Reset settings = 0000_0000
Bit
Name
Function
7
TXM
Transmit Mute.
0 = Transmit signal is not muted.
1 = Mutes the transmit signal.
6:4
ATX[2:0] Analog Transmit Attenuation.
000 = 0 dB attenuation.
001 = 3 dB attenuation.
010 = 6 dB attenuation.
011 = 9 dB attenuation.
1xx = 12 dB attenuation.
Note: The ATXB bit must be 0 if these bits are used.
3
RXM
Receive Mute.
0 = Receive signal is not muted.
1 = Mutes the receive signal.
2:0
ARX[2:0] Analog Receive Gain/On-Hook Line Monitor Receive Attenuation.
This register functions as both a gain setting for the regular DAA receive path and an attenua-
tion setting for the new low-power on-hook line monitor ADC receive path.
Receive Gain
On-Hook Line Monitor Attenuation
000 = 0 dB attenuation.
001 = 1 dB attenuation.
010 = 2.2 dB attenuation.
011 = 3.5 dB attenuation.
1xx = 5 dB attenuation.
000 = 0 dB gain.
001 = 3 dB gain.
010 = 6 dB gain.
011 = 9 dB gain.
1xx = 12 dB gain.
Note: The ARXB bit must be 0 if these bits are used.
Rev. 1.0
35
Si3016
Register 16. International Control 1
Bit
D7
OFF/SQL2
R/W
D6
D5
D4
D3
D2
D1
RZ
D0
RT
Name
Type
OHS
R/W
ACT
R/W
DCT[1:0]
R/W
R/W
R/W
Reset settings = 0000_1000
Bit
Name
OFF/SQL2 DC Termination Off (DAA is off-hook).
Function
7
When the DAA is off-hook, this bit functions as the DC Termination Off bit. When the DAA is
on-hook, this bit functions as the Enhanced Ring Detect Network Squelch bit.
0 = Normal operation.
1 = DC termination disabled and the device presents an 800 Ω dc impedance to the line
which is used to enhance operation with a parallel phone. The DCT pin voltage is also
reduced for improved low line voltage performance.
Enhanced Ring Detect Network Squelch (DAA is on-hook).
To properly receive caller ID data, this bit must be set following a polarity reversal or ring sig-
nal detection and must be left enabled during the reception of caller ID data. It should be dis-
abled before the start of the next ring signal. It is used to recover the offset on the RNG1/2
pins after a polarity reversal or ring signal.
0 = Normal operation.
1 = Enhanced squelch function is enabled.
6
5
OHS
ACT
On-Hook Speed.
0 = The Si3016 will execute a fast on-hook. (Off-hook counter = 1024/Fs seconds.)
1 = The Si3016 will execute a slow, controlled on-hook. (Off-hook counter = 4096/Fs
seconds.)
AC Termination Select.
0 = Selects the real impedance.
1 = Selects the complex impedance.
4
Reserved Read returns zero.
3:2
DCT[1:0] DC Termination Select.
00 = Low Voltage Mode. (Transmit level = –5 dBm).
01 = Japan Mode. Lower voltage mode. (Transmit level = –3 dBm).
10 = FCC Mode. Standard voltage mode. (Transmit level = –1 dBm).
11 = CTR21 Mode. Current limiting mode. (Transmit level = –1 dBm).
1
0
RZ
RT
Ringer Impedance.
0 = Maximum (high) ringer impedance.
1 = Synthesized ringer impedance. C15, R14, Z2, and Z3 must not be installed when setting
this bit. See "4.12. Ringer Impedance" on page 18.
Ringer Threshold Select.
Used to satisfy country requirements on ring detection. Signals below the lower level will not
generate a ring detection; signals above the upper level are guaranteed to generate a ring
detection.
0 = 11 to 22 V
1 = 17 to 33 V
RMS
RMS
36
Rev. 1.0
Si3016
Register 17. International Control 2
Bit
D7
D6
D5
D4
LIM
R/W
D3
D2
D1
D0
Name
Type
MCAL
R/W
CALD
R/W
OPE
R/W
BTE
R/W
ROV
R/W
BTD
R/W
Reset settings = 0000_0000
Bit
7
Name
Reserved Must be zero.
Function
6
MCAL
CALD
LIM
Manual Calibration.
0 = No calibration.
1 = Initiate calibration.
5
4
Auto-Calibration Disable.
0 = Enable auto-calibration.
1 = Disable auto-calibration.
Current Limit
This bit only affects chip operation when the CTR21 dc termination mode is selected.
0 = No current limiting in CTR21 mode.
1 = Enables current limiting in CTR21 mode. The dc termination will current limit before
60 mA.
3
OPE
Overload Protect Enable.
0 = Disable overload protection.
1 = Enable overload protection.
The overload protection feature prevents damage to the DAA when going off-hook with
excessive line current or voltage. When off-hook, if OPE is set and LVCS = 11111, the dc ter-
mination is disabled (800 Ω presented to the line), the hookswitch current is reduced, and the
OPD bit is set. The OPE bit should be written ~25 ms after going off-hook; it should be written
to 0 to reset.
2
BTE
Billing Tone Protect Enable.
0 = Disabled.
1 = Enabled.
When set, the Si3016 will automatically respond to a collapse of the line-derived power supply
during a billing tone event. When off-hook, if BTE = 1 and BTD goes high, the dc termination
is changed to present 800 Ω to the line, and the DCT pin stops tracking the receive input pin.
During normal operation, the DCT pin tracks the receive input.
1
0
ROV
BTD
Receive Overload.
This bit is set when the receive input has an excessive input level (i.e., receive pin goes below
ground). This bit is cleared by writing a zero to this location.
0 = Normal receive input level.
1 = Excessive receive input level.
Billing Tone Detected.
This bit will be set if a billing tone is detected. This bit is cleared by writing a zero to this loca-
tion.
0 = No billing tone detected.
1 = Billing tone detected.
Rev. 1.0
37
Si3016
Register 18. International Control 3
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
FULL
R/W
DIAL
R/W
FJM
R/W
VOL
R/W
FLVM
R/W
MODE
R/W
RFWE
R/W
SQLH
R/W
Reset settings = 0000_0000
Bit
Name
Function
7
FULL Full Scale.
0 = Default.
1 = Transmit/receive full scale = +3.2 dBm.
This bit changes the full scale of the ADC and DAC from –1 dBm min to +3.2 dBm min. When this
bit is set, R2 must be changed from 402 Ω to 243 Ω. This mode can be useful for certain voice
applications and should only be used in the FCC/600 Ω AC Termination mode.
6
5
4
DIAL DTMF Dialing Mode.
This bit should be set during DTMF dialing in CTR21 mode if LCS[3:0] < 6 or
LVCS[4:0] < 12 decimal.
0 = Normal operation.
1 = Increase headroom for DTMF dialing.
FJM Force Japan DC Termination Mode.
0 = Normal Gain
1 = When the DCT[1:0] bits are set to 10b (FCC mode), setting this bit will force the Japan dc ter-
mination mode while allowing for a transmit level of –1 dBm. See "4.13. DTMF Dialing" on page
19.
VOL Line Voltage Adjust.
When set, this bit will adjust the TIP-RING line voltage. Lowering this voltage will improve margin
in low-voltage countries. Raising this voltage may improve large signal distortion performance.
0 = Normal operation.
1 = Lower DCT voltage.
Description
CTR21/FCC
CTR21/FCC+VOL
JAPAN
JAPAN+VOL
DCT
1x
1
OFF
0
0
0
0
0
0
1
1
1
1
1
1
VOL
0
1
0
1
0
1
0
1
0
1
0
1
VDCT
4.00
3.51
3.15
2.87
2.65
2.47
2.33
2.21
2.10
2.01
1.94
1.87
DELTA
0.49 V
0.28 V
0.18 V
0.12 V
0.09 V
0.07 V
01
01
00
00
1x
1x
01
01
00
00
LVMode
LVMode+VOL
CTR21/FCC+OFF
CTR21/FCC+VOL+OFF
JAPAN+OFF
JAPAN+VOL+OFF
LVMode+OFF
LVMode+VOL+OFF
38
Rev. 1.0
Si3016
Bit
Name
Function
3
FLVM Force Low Voltage DC Termination Mode.
0 = Normal gain.
1 = When the DCT[1:0] bits are set to 10b (FCC mode), setting this bit will force the Low Voltage
dc termination mode while allowing for a transmit level of –1 dBm. See "4.13. DTMF Dialing" on
page 19.
2
MODE
MODE Control.
This bit is used to enable the on-hook line monitor ADC and the line voltage monitor.
MODE
0
0
OH
0
0
ONHM
Line Function
on-hook
on-hook
SDO
ring data
line data using 11111 if a line
LVCS[4:0]
0
0
1
the higher
current line
monitor
voltage
exists, or
00000 if no
line voltage
exists
0
0
1
1
1
1
0
0
0
1
0
1
off-hook
line data
loop current
loop current
line voltage
off-hook/Fast DCT mode line data
on-hook
on-hook
ring data
line data using line voltage
the low current
line monitor
1
1
1
0
1
force on-hook
force on-hook
no data is
transmitted on
SDO in this
mode
line data using line voltage
the low current
line voltage
1
line monitor
Notes:
1. If RZ = 1, LVCS[4:0] = either 11111 or 00000 during a ring event. All ones are shown if a line voltage exists; all
zeroes are shown if no line voltage exists.
2. Force on-hook mode puts the Si3016 into an on-hook state without restarting the off-hook counter. This is used to
support Type II caller ID.
3. The MODE bit is in a different register than the OH and ONHM bits. The user should write the registers in a
sequence so as not to pass through an undesired state.
4. Fast DCT mode puts the Si3016 into an off-hook state that is intended to quickly settle the line voltage just after
going off-hook. While in this mode, data transmission is not recommended. This is used to support Type II caller ID.
5. The ONHM bit should be cleared before setting the OH bit. If both bits need to be set, the OH bit should be set
first, and then the ONHM bit should be set in a separate register access.
1
0
RFWE Ring Detector Full Wave Rectifier Enable.
When set, the ring detection circuitry provides full-wave rectification. This will affect the RGDT pin
as well as the data stream presented on SDO during ring detection.
0 = Half Wave.
1 = Full Wave.
SQLH Ring Detect Network Squelch.
This bit must be set, then cleared after at least 1 ms, following a polarity reversal or ring signal
detection. It is used to quickly recover the offset on the RNG1/2 pins after a polarity reversal or
ring signal. If the SQL2 bit is enabled during CID data reception, this bit should not be used.
0 = Normal operation.
1 = Squelch function is enabled.
Rev. 1.0
39
Si3016
Register 19. International Control 4
Bit
D7
D6
D5
LVCS [4:0]
R
D4
D3
D2
OVL
R
D1
DOD
R
D0
OPD
R
Name
Type
Reset settings = 0000_0000
Bit
Name
Function
7:3 LVCS[4:0] Line Voltage/Current Sense.
Represents either the line voltage, loop current, or on-hook line monitor depending on the
state of the MODE, OH, and ONHM bits.
On-Hook Voltage Monitor (2.75 V/bit).
00000 = No line connected.
00001 = Minimum line voltage (V
= 3 V ± 0.5 V).
MIN
11111 = Maximum line voltage (87 V ± 20%).
The line voltage monitor full scale may be modified by changing R5 as follows:
V
= V
+ 4.2 (10M + R5 + 1.6 k)/[(R5 +1.6 k)*5]
MIN
MAX
Off-Hook Loop Current Monitor (3 mA/bit).
00000 = Loop current is less than required for normal operation.
00001 = Minimum normal loop current.
11110 = Maximum normal loop current.
11111 = Loop current is excessive (overload).
Overload > 140 mA in all modes except CTR21.
Overload > 54 mA in CTR21 mode.
2
1
OVL
Overload Detected.
This bit has the same function as ROV in Register 17 but will clear itself after the overload has
been removed. See "4.15. Billing Tone Detection" on page 19. This bit is only masked by the
off-hook counter and is not affected by the BTE bit.
0 = Normal receive input level.
1 = Excessive receive input level.
DOD
Recal/Dropout Detect.
When the line-side device is off-hook, it is powered from the line itself. If this line-derived
power supply collapses, such as when the line is disconnected, this bit is set to 1. Sixteen
frames (16/Fs) after the line-derived power supply returns, this bit is set to 0. When on-hook,
this bit is set to 0.
0 = Normal operation.
1 = Line supply dropout detected when on-hook.
0
OPD
Overload Protect Detected.
0 = Inactive.
1 = Overload protection active.
Note: See description of overload protect operation (OPE bit).
40
Rev. 1.0
Si3016
Rev. 1.0
41
Si3016
APPENDIX A—UL1950 3RD EDITION
Although designs using the Si3016 comply with The bottom schematic of Figure 16 shows the
UL1950, 3rd Edition, and pass all overcurrent and configuration in which the ferrite beads (FB1, FB2) are
overvoltage tests, there are still several issues to on the protected side of the sidactor (RV1). For this
consider.
design, the ferrite beads can be rated at 200 mA.
Figure 16 shows two designs that can pass the UL1950 In a cost-optimized design, it is important to remember
overvoltage tests, as well as electromagnetic emissions. that compliance to UL1950 does not always require
The top schematic of Figure 16 shows the configuration overvoltage tests. It is best to plan ahead and know
in which the ferrite beads (FB1, FB2) are on the which overvoltage tests will apply to your system.
unprotected side of the sidactor (RV1). For this System-level elements in the construction, such as fire
configuration, the current rating of the ferrite beads enclosure and spacing requirements, need to be
needs to be 6 A. However, the higher current ferrite considered during the design stages. Consult with your
beads are less effective in reducing electromagnetic professional testing agency during the design of the
emissions.
product to determine which tests apply to your system.
C24
75 Ω @ 100 MHz, 6 A
1.25 A
FB1
TIP
75 Ω @ 100 MHz, 6 A
RV1
FB2
RING
C25
C24
600 Ω @ 100 MHz, 200 mA
FB1
FB2
1.25 A
TIP
RV1
RING
600 Ω @ 100 MHz, 200 mA
C25
Figure 16. Circuits that Pass all UL1950 Overvoltage Tests
42
Rev. 1.0
Si3016
APPENDIX B—CISPR22 COMPLIANCE
Various countries are expected to adopt the IEC The direct current resistance (DCR) of the listed
CISPR22 standard over the next few years. For inductors is an important consideration. If the DCR of
example, the European Union (EU) has adopted a the inductors used is less than 3 Ω each, then country
standard entitled EN55022, which is based on the PTT specifications which require 300 Ω or less of dc
CISPR22 standard. Adherence to this standard will be resistance at TIP and RING with 20 mA of loop current
necessary to display the CE mark on designs intended can be satisfied with the Japan dc termination mode. If
for sale in the EU. The typical schematic and global bill the DCR of the inductors is at or slightly above 3 Ω, the
of materials (BOM) (see Figure 6 and Table 7) low-voltage termination mode may need to be used to
contained in this data sheet are designed to be satisfy the 300 Ω dc resistance requirement at 20 mA of
compliant to the CISPR22 standard.
loop current. In all cases, "4.9. DC Termination
Considerations" on page 17 should be followed.
If smaller inductors are desired, a notch filter may be
used and compliance to CISPR22 still achieved. As If compliance to the CISPR22 standard and certain
shown in Figure 17, a series capacitor-resistor in other country PTT requirements are not desired, then
parallel with L1 and L2 forms the simple notch filter. L1 and L2 may be removed. If these inductors are
Table 14 shows corresponding values used for C24, removed, C24 and C25 should be increased to 2200 pF,
C25, C38, C39, L1, L2, R31, and R32.
and C9 should be changed to 22 nF, 250 V. With these
changes, PTT compliance in the following countries will
not be achieved: India (I/Fax-03/03 standard), Taiwan
(ID0001 standard), Chile (Decree No. 220 1981
standard), and Argentina (CNC-St2-44.01 standard).
C38
R31
For questions concerning compliance to CISPR22 or
other relevant standards, contact a Silicon Laboratories
technical representative.
L1
FB1
TIP
C24
To
DAA
C39
R32
L2
FB2
RING
C25
Figure 17. Notch Filter for CISPR22
Compliance
Table 14. Notch Filter Component Values
C24/C25 C38/C39
L1/L2
R31/R32
1000 pF
33 pF,
50 V
150 µH, DCR
< 3 Ω, I > 120 mA
680 Ω,
1/10 W
Rev. 1.0
43
Si3016
6. Pin Descriptions: Si3016
QE2
DCT
IGND
C1B
FILT2
FILT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
RX
REXT
REXT2
REF
RNG1
RNG2
QB
VREG2
VREG
QE
Table 15. Si3016 Pin Descriptions
Description
Pin #
Pin Name
1
QE2
Transistor Emitter 2.
Connects to the emitter of Q4.
2
3
4
DCT
IGND
C1B
DC Termination.
Provides dc termination to the telephone network.
Isolated Ground.
Connects to ground on the line-side interface. Also connects to capacitor C2.
Isolation Capacitor 1B.
Connects to one side of isolation capacitor C1. Used to communicate with the system-
side module.
5
6
RNG1
RNG2
Ring 1.
Connects through a capacitor to the TIP lead of the telephone line. Provides the ring
and caller ID signals to the Si3016.
Ring 2.
Connects through a capacitor to the RING lead of the telephone line. Provides the ring
and caller ID signals to the Si3016.
7
8
QB
QE
Transistor Base.
Connects to the base of transistor Q3. Used to go on/off-hook.
Transistor Emitter.
Connects to the emitter of transistor Q3. Used to go on/off-hook.
9
VREG
VREG2
REF
Voltage Regulator.
Connects to an external capacitor to provide bypassing for an internal power supply.
10
11
12
13
Voltage Regulator 2.
Connects to an external capacitor to provide bypassing for an internal power supply.
Reference.
Connects to an external resistor to provide a high-accuracy reference current.
REXT2
REXT
External Resistor 2.
Sets the complex ac termination impedance.
External Resistor.
Sets the real ac termination impedance.
44
Rev. 1.0
Si3016
Table 15. Si3016 Pin Descriptions (Continued)
Description
Pin #
Pin Name
14
RX
Receive Input.
Serves as the receive side input from the telephone network.
15
16
FILT
Filter.
Provides filtering for the dc termination circuits.
FILT2
Filter 2.
Provides filtering for the bias circuits.
Rev. 1.0
45
Si3016
7. Ordering Guide
Part Number
Si3016-KS
Package
Pb-Free
No
Temp Range
0 to 70 °C
16-pin SOIC
16-pin SOIC
16-pin SOIC
Si3016-F-FS
Si3016-BS
Yes
0 to 70 °C
No
–40 to 85 °C
46
Rev. 1.0
Si3016
8. Package Outline: SOIC
Figure 18 illustrates the package details for the Si3016. Table 16 lists the values for the dimensions shown in the
illustration.
16
9
h
E
H
0.010
GA UGE PLA NE
θ
1
8
B
L
Detail F
D
C
A2
A1
A
L1
e
See Detail F
γ
Seating Plane
Figure 18. 16-Pin Small Outline Integrated Circuit (SOIC) Package
Table 16. Package Diagram Dimensions
Symbol
Millimeters
Min
Max
1.75
.25
1.50
.51
A
A1
A2
B
1.35
.10
1.30
.33
C
D
E
e
H
h
.19
.25
9.80
3.80
1.27 BSC
5.80
.25
10.01
4.00
—
6.20
.50
L
L1
γ
.40
1.07BSC
—
1.27
—
0.10
8º
θ
0º
Rev. 1.0
47
Si3016
DOCUMENT CHANGE LIST
Revision 0.2 to Revision 0.3
Pages 9-10: Updated schematic and BOM.
Page 16: updated Figure 13.
Page 44: added Appendix B
Revision 0.3 to Revision 0.41
Table 9 updated.
“Appendix B—CISPR22 Compliance” updated.
The “Ringer Impedance Network” figure and the
“Component Values—Optional Ringer Impedance
Network” table were deleted from the “Ringer
Impedance”section as well as a paragraph
discussing Czech Republic designs.
The “Dongle Applications Circuit” figure was deleted.
Revision 0.41 to Revision 0.42
Page 1: updated Features list.
Table 2, page 5: revised Note 3.
Page 12: added single-channel information to
Functional Description.
Revision 0.42 to Revision 0.44
Table 3 on page 6 updated.
Page 26: removed SB from Register 1, bit 0.
Register 1, bit 0: removed SB and description from
register.
Register 5, bits 6,1 and 5,0: revised transmit path
attenuation transmit and receive controls.
Revision 0.44 to Revision 1.0
Updated "7. Ordering Guide" on page 46.
Updated "4.27. Revision Identification" on page 25.
48
Rev. 1.0
Si3016
NOTES:
Rev. 1.0
49
Si3016
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50
Rev. 1.0
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