SI3209-B-FMR [SILICON]
SLIC, ROHS COMPLIANT, MS-220VJJD-2, QFN-40;
| 型号： | SI3209-B-FMR |
| 厂家： | 
SILICON |
| 描述： | SLIC, ROHS COMPLIANT, MS-220VJJD-2, QFN-40 电信 电信集成电路 |
| 文件： | 总46页 (文件大小：496K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si3226/27 +
Si3208/09
DUAL PROSLIC® WITH DC-DC CONTROLLER
Features
Performs all BORSCHT functions
Ideal for short- or long-loop applications On-hook transmission
Internal balanced or unbalanced ringing Loop or ground start operation
Low power consumption
Low-power sleep mode
Smooth polarity reversal
DTMF generator/decoder
A-Law/µ-Law companding,
linear PCM
Software-programmable parameters:
Ringing frequency, amplitude,
cadence, and waveshape
Two-wire ac impedance
PCM and SPI bus digital interfaces
with programmable interrupts
GCI/IOM-2 mode support
3.3 V operation
GR-909 loop diagnostics
Audio diagnostics with loopback
Pb-free/RoHS-compliant packaging
Transhybrid balance
DC current loop feed (10–45 mA)
Loop closure and ring trip thresholds
Ground key detect threshold
Integrated dc-dc controller
Wideband CODEC (Si3227)
Applications
Customer Premises Equipment (CPE)
Optical Network Terminals (ONT)
Private Branch Exchange (PBX)
Cable EMTAs, ATAs, VoIP
Gateways
Ordering Information
Description
See page 38.
The Si3226/27 Dual ProSLIC® chipsets each consist of a low-voltage CMOS
device integrating both SLIC and CODEC functionality in combination with a high-
voltage linefeed IC (LFIC). The chipset provides two complete foreign exchange
station (FXS) telephony interfaces. The Si3226/27 operate from a single 3.3 V
supply and interface to standard PCM/SPI or GCI bus digital interfaces. A built-in
dc-dc controller automatically generates the optimal battery voltage required for
each line-state, optimizing efficiency and minimizing heat generation. Self-testing
and metallic loop testing (MLT), e.g., GR-909, is facilitated by the built-in DSP,
monitor ADC, and test load. The companion Si3208/09 LFICs are available with
voltage ratings up to –135 V to support high power ringing and the Si3227
supports wideband audio for better-than-PSTN voice quality (see Ordering Guide
below). The Si3226/27 are available in a 64-pin thin quad flat package (TQFP);
the LFICs are available in a 40-pin quad, flat, no-lead package (QFN).
Patents pending
Functional Block Diagram
Si3226/27
Si3208/09
CODEC SLIC
PCM/
GCI
Interface
FSYNC
DRX
DTMF &
Tone Gen
Linefeed
TIP
ADC
Control
DTX
Channel 1
RING
Caller ID
Linefeed
Monitor
CS
SDI
DAC
SPI
Control
Interface
Ringing
Generator
SDO
SCLK
INT
SLIC
Linefeed
Control
CODEC
DSP
TIP
Line Diagnostics
ADC
RST
Channel 2
RING
Linefeed
Monitor
DAC
PCLK
DC-DC Controllers
PLL
VBAT
DC-DC BOM
VDC
Rev. 1.2 10/10
Copyright © 2010 by Silicon Laboratories
Si3226/27 + Si3208/09
Silicon Laboratories Confidential. Information contained herein is covered under non-disclosure agreement (NDA).
Si3226/27 +
Si3208/09
2
Rev. 1.2
Si3226/27 +
Si3208/09
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
4.1. DC Feed Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
4.2. Linefeed Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
4.3. Line Voltage and Current Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
4.4. Power Monitoring and Power Fault Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
4.5. Thermal Overload Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
4.6. Power Dissipation Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
4.7. Loop Closure Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
4.8. Ground Key Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
4.9. Ringing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
4.10. Polarity Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
4.11. Two-Wire Impedance Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
4.12. Transhybrid Balance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
4.13. Tone Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
4.14. DTMF Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
4.15. DC-DC Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
4.16. Wideband Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
4.17. SPI Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
4.18. PCM Interface and Companding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
4.19. General Circuit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
4.20. Metallic Loop Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
5. Pin Descriptions: Si3226/27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
6. Pin Descriptions: Si3226/27 + Si3208/09 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
8. Product Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
9. Package Outline: 64-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
10. Package Outline: 40-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Rev. 1.2
3
Si3226/27 +
Si3208/09
1. Electrical Specifications
Table 1. Absolute Maximum Ratings and Thermal Information1
Parameter
Symbol
Test Condition
Value
Unit
°C
Operating Temperature Range
Storage Temperature Range
T
–40 to 85
–55 to 150
A
T
°C
STG
2
Thermal Resistance, Typical
45
.88
°C/W
W
JA
TQFP-64
3
Continuous Power Dissipation
TQFP-64
P
T = 85 °C
A
D
Maximum Junction Temperature,
Si3226/27
T
125
32
°C
J
2
Thermal Resistance, Typical
°C/W
W
JA
QFN-40
4
Continuous Power Dissipation
P
T = 85 °C
1.87
145
D
A
QFN-40
Maximum Junction Temperature,
T
Continuous
°C
4
J
Si3208/09
Si3226/27
V
V
, V
,
DD DDA
Supply Voltage
–0.5 to 4.0
–0.3 to 3.6
V
V
V
DDC
DDD
Digital Input Voltage
V
IND
Si3208
Si3209
Supply Voltage
V
–0.5 to 4.0
+0.4 to –115
–130
V
V
DD
5
Battery Supply Voltage
V
BAT
6
V
, V
V
TIP or RING Voltage
TIP RING
TIP, RING Current
I
, I
±100
mA
TIP RING
Supply Voltage
V
–0.5 to 4.0
+0.4 to –140
–140
V
V
DD
5
High Battery Supply Voltage
V
BAT
6
V
I
, V
V
TIP or RING Voltage
TIP RING
TIP, RING Current
, I
±100
mA
TIP RING
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operational sections of this data sheet.
2. The thermal resistance of an exposed pad package is assured when the recommended printed circuit board layout
guidelines are followed correctly. The specified performance requires that the exposed pad be soldered to an exposed
copper surface of at least equal size and that multiple vias are added to enable heat transfer between the top-side
copper surface and a large internal/bottom copper plane.
3. Operation of the Si3226 or Si3227 above 125 °C junction temperature will degrade device reliability.
4. Si3208 and Si3209 are equipped with on-chip thermal limiting circuitry that shuts down the circuit when the junction
temperature exceeds the thermal shutdown threshold. The thermal shutdown threshold should normally be set to
145 °C; when in the ringing state the thermal shutdown may be set to 200 °C. For optimal reliability long term operation
of the Si3208/Si3209 above 150 °C junction temperature should be avoided.
5. The dv/dt of the voltage applied to the VBAT pins must be limited to 10 V/µs.
6. Specification requires protection circuit for surge event as shown in typical application circuit.
4
Rev. 1.2
Si3226/27 +
Si3208/09
Table 2. Recommended Operating Conditions1
1
1
1
Parameter
Symbol
Test
Condition
Unit
Min
Typ
Max
o
Ambient Temperature
T
F-grade
G-grade
0
25
25
—
—
70
85
C
A
o
Ambient Temperature
T
–40
—
C
A
Junction Temperature, Si3208/09
Junction Temperature, Si3226/27
Supply Voltage, Si3226/27
T
T
145
125
3.47
°C
°C
V
J
—
J
V
DDC
V
,
3.13
3.3
DDA
, V
V
DDD
Supply Voltage, Si3208/09
3.13
–110
–136
3.3
—
3.47
–15
–15
V
V
V
DD
2
Battery Voltage, Si3208
VBAT
VBAT
2
Battery Voltage, Si3209
—
Notes:
1. All minimum and maximum specifications apply across the recommended operating conditions. Typical values apply at
nominal supply voltages and an operating temperature of 25 °C unless otherwise stated.
2. Operation at minimum voltage dependent upon loop conditions and dc-dc converter configurations.
Rev. 1.2
5
Si3226/27 +
Si3208/09
Table 3. 3.3 V Power Supply Characteristics
(VDD = 3.3 V, TA = 0 to 70 ºC for F-Grade, –40 to 85 ºC for G-Grade)
Parameter
Supply Currents:
Symbol
Test Condition
Min
—
Typ
4.0
0
Max
—
Unit
mA
mA
mA
mA
I
V and V = Hi-Z
DD
T
R
Reset
RST = 0
I
I
—
—
VBAT
Supply Currents:
High Impedance,
Open
I
V and V = Hi-Z
—
13.1
.43
—
DD
VBAT
T
R
—
—
Supply Currents:
Forward/Reverse,
On-hook
I
V
= –48 V
TR
—
—
18.7
1.2
—
—
mA
mA
DD
Automatic Power Save Mode
Enabled
I
I
I
VBAT
Supply Currents:
Forward/Reverse Active,
On-hook
I
V
= –48 V
TR
—
—
27.7
1.2
—
—
mA
mA
DD
Automatic Power Save Mode
Disabled
VBAT
Supply Currents:
Forward/Reverse Active,
Off-hook
I
I
= 18 mA
= –12 V
= 200
—
—
43
—
—
mA
mA
DD
LOOP
V
BAT
2.9 +
VBAT
R
LOAD
1.02*I
LOOP
Automatic Power Save Mode
Disabled
Supply Currents:
Forward/Reverse OHT,
On-hook
I
V
= –48 V
TR
—
—
40.2
1.9
—
—
mA
mA
DD
I
I
VBAT
Supply Currents:
Tip/Ring Open,
On-hook
I
V or V = –48 V
—
—
27
—
—
mA
mA
DD
T
R
V or V = Hi-Z
R
T
0.43
VBAT
Automatic Power Save Mode
Disabled
Supply Currents:
Ringing
I
V
= 55 V
+ 0 V
DC
—
—
27.2
—
—
mA
mA
DD
TR
RMS
balanced, sinusoidal, f = 20 Hz
= –136 V
I
5.6 + I
AVE
VBAT
V
BAT
R
= 5 REN = 1400
LOAD
Notes:
1. All specifications are for a single channel of Si3226/27 using Si3208/09 linefeed IC and based on measurements with all
channels in the same operating state.
2. ILOOP is the dc current in the subscriber loop during the off-hook state.
3. IAVE is the average of the full-wave rectified current in the subscriber loop during ringing (IAVE = IPEAK x 2/) = 36 mA
under the test conditions shown for Ringing Current.
4. IDD = IDDD + IDDA + IDDC
.
6
Rev. 1.2
Si3226/27 +
Si3208/09
Table 4. AC Characteristics
(VDD = 3.13 to 3.47 V, TA = 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade)
Parameter
Overload Level
Test Condition
Min
Typ
Max
Unit
TX/RX Performance
2.5
+35
—
—
—
V
PK
Overload Compression
2-Wire – PCM
2-Wire – PCM or PCM – 2-Wire:
200 Hz to 3.4 kHz
See Figure 12
1
Single Frequency Distortion
+40
—
dB
dB
PCM – 2-Wire – PCM:
200 Hz – 3.4 kHz,
16-bit Linear mode
—
+63
Signal-to-(Noise + Distortion)
Ratio
200 Hz to 3.4 kHz
D/A or A/D 8-bit
Active off-hook, and OHT, any Z
Figure 11
46
—
—
—
—
2
T
Audio Tone Generator Signal-to-
0 dBm0, Active off-hook, and
dB
2
Distortion Ratio
OHT, any Z
T
Intermodulation Distortion
—
—
—
–41
0.2
dB
dB
2
Gain Accuracy
2-Wire to PCM or PCM to 2-Wire
1014 Hz, Any gain setting
0 dBm 0
–0.2
Attenuation Distortion vs.
Frequency
See Figure 5 and 6
See Figure 7 and 8
Group Delay vs. Frequency
3
Gain Tracking
1014 Hz sine wave,
reference level –10 dBm
Signal level:
3 dB to –37 dB
–37 dB to –50 dB
—
—
—
—
—
—
0.25
0.5
dB
dB
dB
µs
–50 dB to –60 dB
—
1.0
Round-Trip Group Delay
1014 Hz, Within same time-slot
450
500
Crosstalk between channels
TX or RX to TX
0 dBm0,
300 Hz to 3.4 kHz
300 Hz to 3.4 kHz
—
—
26
26
—
—
30
30
–75
–75
—
dB
dB
dB
dB
TX or RX to RX
4
2-Wire Return Loss
200 Hz to 3.4 kHz
300 Hz to 3.4 kHz
4
Transhybrid Balance
—
Notes:
1. The input signal level should be 0 dBm0 for frequencies greater than 100 Hz. For 100 Hz and below, the level should
be –10 dBm0. The output signal magnitude at any other frequency is smaller than the maximum value specified.
2. Analog signal measured as VTIP – VRING. Assumes ideal line impedance matching.
3. The quantization errors inherent in the µ/A-law companding process can generate slightly worse gain tracking
performance in the signal range of 3 to –37 dB for signal frequencies that are integer divisors of the 8 kHz PCM
sampling rate.
4. V
, V
, V
= 3.3 V, VBAT = –52 V, no fuse resistors; RL = 600 , ZS = 600 synthesized using RS register
DDA
DDC
DDD
coefficients.
5. The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed –55 dBm.
Rev. 1.2
7
Si3226/27 +
Si3208/09
Table 4. AC Characteristics (Continued)
(VDD = 3.13 to 3.47 V, TA = 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade)
Parameter
Test Condition
Min
Typ
Max
Unit
Noise Performance
C-Message weighted
5
Idle Channel Noise
—
—
—
8
12
–78
—
dBrnC
dBmP
dB
Psophometric weighted
VDDA, VDDD, VDDC = 3.3 V
RX and TX, 200 Hz to 3.4 kHz
Longitudinal Performance
200 kHz to 3.4 kHz
–82
55
PSRR from
Longitudinal to Metallic/PCM
Balance (forward or reverse)
52
40
58
—
—
—
dB
dB
Metallic/PCM to Longitudinal
Balance
200 Hz to 3.4 kHz
Longitudinal Impedance
200 Hz to 3.4 kHz at TIP or RING
—
—
50
25
—
—
Longitudinal Current Capability per
Pin
Active off-hook
60 Hz
mA
RMS
REG 73 = 0x0B
Notes:
1. The input signal level should be 0 dBm0 for frequencies greater than 100 Hz. For 100 Hz and below, the level should
be –10 dBm0. The output signal magnitude at any other frequency is smaller than the maximum value specified.
2. Analog signal measured as VTIP – VRING. Assumes ideal line impedance matching.
3. The quantization errors inherent in the µ/A-law companding process can generate slightly worse gain tracking
performance in the signal range of 3 to –37 dB for signal frequencies that are integer divisors of the 8 kHz PCM
sampling rate.
4. V
, V
, V
= 3.3 V, VBAT = –52 V, no fuse resistors; RL = 600 , ZS = 600 synthesized using RS register
DDA
DDC
DDD
coefficients.
5. The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed –55 dBm.
8
Rev. 1.2
Si3226/27 +
Si3208/09
Table 5. Linefeed Characteristics
(VDD = 3.13 to 3.47 V, TA = 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Maximum Loop Resistance
R
R
= 430 ,R = 0
PROT
—
—
2000
LOOP
DC,MAX
I
= 18 mA, V
= –52V
LOOP
BAT
DC Feed Current*
Differential
Common Mode
Differential + Common Mode
= 18 mA
—
—
—
—
—
—
—
—
—
—
45
30
45
10
4
mA
mA
mA
%
DC Loop Current Accuracy
I
LIM
DC Open Circuit Voltage
Accuracy
Active Mode; V = 48 V,
V
OC
V
– V
TIP
RING
DC Differential Output
Resistance—Ringing
R
I
< I
100
—
—
—
320
4
RING
LOOP
LIM
DC On-Hook Voltage
Accuracy—Ground Start
V
R
I
<I ; V wrt ground,
RING
V
OHTO
ROTO
RING LIM
V
= –51 V
RING
DC Output
Resistance—Ground Start
I
<I ; RING to ground
160
400
—
—
—
—
—
—
640
—
10
10
4
k
%
RING LIM
DC Output Resistance—
Ground Start
R
TIP to ground
TOTO
Loop Closure Detect
Threshold Accuracy
I
I
= 13 mA
= 13 mA
THR
THR
Ground Key Detect
Threshold Accuracy
—
%
Ring Trip
AC detection,
—
mA
Threshold Accuracy
V
= 70 Vpk, no offset,
RING
I
= 80mA
TH
DC detection,
—
—
1
mA
mA
20 V dc offset, I = 13 mA
TH
DC Detection,
—
—
—
—
—
108
134
1
3
48 V DC offset, R
= 1500
loop
Maximum Ringing Amplitude
V
Si3208, Open circuit,
= –110 V
—
—
—
V
V
RING
PK
PK
V
BAT
Si3209, Open Circuit,
= –136 V
V
BAT
Sinusoidal Ringing Total
Harmonic Distortion
R
Si3208: 60 V
, 15 V offset,
RMS
%
THD
0–5 REN
Si3209: 55V
, 48 V offset,
RMS
0–5 REN
Ringing Frequency Accuracy
Ringing Cadence Accuracy
*Note: Absolute value.
f = 16 Hz to 100 Hz
—
—
—
—
1
%
Accuracy of ON/OFF times
50
ms
Rev. 1.2
9
Si3226/27 +
Si3208/09
Table 5. Linefeed Characteristics (Continued)
(VDD = 3.13 to 3.47 V, TA = 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Loop Voltage Sense
Accuracy
Accuracy of boundaries for
each output code;
—
2
4
%
V
– V
= 48 V
TIP
RING
Loop Current
Sense Accuracy
I
= 18 mA
—
—
7
10
—
%
%
LOOP
Power Alarm
Threshold Accuracy
Power Threshold = 1.0 W
= –56 V, I = 40 mA,
15
V
BAT
LOOP
R
= 600
LOAD
*Note: Absolute value.
Table 6. Monitor ADC Characteristics
(VDD = 3.13 to 3.47 V, TA = 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Differential Nonlinearity
(8-bit resolution)
DNLE
—
1
1
5
—
—
—
LSB
Integral Nonlinearity
(8-bit resolution)
INLE
—
—
LSB
%
Gain Error
10
Rev. 1.2
Si3226/27 +
Si3208/09
Table 7. Digital/Characteristics
(VDD = 3.13 to 3.47 V, TA = 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
High Level Input Voltage
Low Level Input Voltage
V
0.7 x V
—
—
—
—
V
DD
V
V
V
IH
DD
V
0.3 x V
—
IL
DD
High Level Output
Voltage
V
DTX, SDO, SDITHRU,
GPIO3a/b,GPIO1a/b,
GPIO2a/b:
V
– 0.6
DD
OH
I = 4 mA
O
Low Level Output
Voltage
V
DTX, SDO, INT,
SDITHRU, GPIO3a/b:
—
—
0.4
V
OL
I = –4 mA
O
GPIO1 a/b, GPIO2 a/b:
—
33
—
—
42
—
0.72
65
I = –40 mA
O
SDITHRU Internal
Pullup Current
µA
µA
Input Leakage Current
I
10
L
Table 8. Switching Characteristics—General Inputs1,2
(VDD = 3.13 to 3.47 V, TA = 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade, CL = 20 pF)
Parameter
Rise Time, RESET
RESET Pulse Width, GCI Mode
Symbol
Min
—
Typ
—
Max
Unit
t
5
ns
µs
µs
r
3,4
t
33/PCLK
33/PCLK
—
—
—
rl
rl
4
RESET Pulse Width, SPI Daisy Chain Mode
t
—
Notes:
1. All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are
VIH = VDD – 0.4 V, VIL = 0.4 V. Rise and Fall times are referenced to the 20% and 80% levels of the waveform.
2. RESET input capacitance = 0.3 pF.
3. The minimum RESET pulse width assumes the SDITHRU pin is tied to ground via a pulldown resistor no greater than
10 k per device.
4. The minimum RESET pulse width is 33/PCLK frequency (i.e. 33/8.192 MHz = 4 µs).
Rev. 1.2
11
Si3226/27 +
Si3208/09
VDD
2
Min. 33 PCLK’s
1
RSTB
Wait time to allow
PLL to lock
3
6
MADC
Offset Cal
Software steps
VBAT
Remaining Cals
5
4
VDC
Figure 1. Powerup and Initialization Sequence
The following Powerup and Initialization Sequence must be followed:
1. VDD must be brought up while RSTB pin is held low.
2. Release RSTB at least 33 PCLK cycles after VDD.
3. Perform on-chip MADC offset calibration from OPEN state.
4. 10 ms is recommended prior to initializing the dc-dc converter after the MADC offset calibration. The VDC
supply must be at the minimum valid voltage to ensure proper operation. The minimum valid voltage is shown in
the application circuit schematic.
5. Bring up VBAT.
6. Perform remaining calibrations (except for common mode balance) from OPEN state.
Note: Repeat from step 3 whenever a hardware reset has been performed.
Powerdown Sequence:
1. Powerdown dc-dc converter.
2. Wait until VBAT is smaller than –10 V.
3. Turn off VDD.
PCLK
Counting of PCLK
Rising Edges
31
30 29 28
5
4
3
2
1
0
1
2
3
4
5
28 29
30
31
External Reset
Internal Reset
Sample Reset
Note: The count of PCLK rising edges during reset will be skewed by 1-2 clocks based on the internal sampling of reset.
Figure 2. Reset Timing Diagram
12
Rev. 1.2
Si3226/27 +
Si3208/09
Table 9. Switching Characteristics—SPI
(VDDA = 3.13 to 3.47 V, TA = 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade, CL = 20 pF)
Parameter
Cycle Time, SCLK
Symbol
Test Conditions
Min
62
—
Typ
—
Max
—
Unit
ns
t
c
Rise Time, SCLK
t
—
25
ns
r
Fall Time, SCLK
t
—
—
25
ns
f
Delay Time, SCLK Fall to SDO Active
t
—
—
20
ns
d1
d2
Delay Time, SCLK Fall to SDO
Transition
t
t
—
—
20
ns
Delay Time, CS Rise to SDO Tri-state
Setup Time, CS to SCLK Fall
—
25
20
25
20
220
—
—
—
—
—
—
—
4
20
—
—
—
—
—
10
ns
ns
ns
ns
ns
ns
ns
d3
t
su1
Hold Time, CS to SCLK Rise
t
h1
Setup Time, SDI to SCLK Rise
Hold Time, SDI to SCLK Rise
Delay Time between Chip Selects
SDI to SDITHRU Propagation Delay
t
su2
t
h2
t
cs
t
d4
Note: All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VDDD –0.4 V, VIL = 0.4 V
tc
tr
tf
SCLK
CS
tsu1
th1
tcs
tsu2
th2
SDI
td1
td3
td2
SDO
td4
SDITHRU
Figure 3. SPI Timing Diagram
Rev. 1.2
13
Si3226/27 +
Si3208/09
Table 10. Switching Characteristics—PCM Highway Interface
(VDD = 3.13 to 3.47 V, TA = 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade, CL = 20 pF)
1
1
1
Parameter
Symbol
Test
Conditions
Units
Min
Typ
Max
PCLK Period
t
122
—
—
3906
—
ns
ns
p
PCLK Jitter Tolerance
t
±8
jitter
2
Valid PCLK Inputs
—
—
—
—
—
—
—
—
512
768
—
—
—
—
—
—
—
—
kHz
kHz
1.024
1.536
1.544
2.048
4.096
8.192
MHz
MHz
MHz
MHz
MHz
MHz
3
FSYNC Period
t
—
40
—
—
—
—
—
125
50
—
—
60
µs
%
fs
PCLK Duty Cycle Tolerance
FSYNC Jitter Tolerance
Rise Time, PCLK
t
dty
t
±120
25
ns
ns
ns
ns
ns
jitter
t
—
r
Fall Time, PCLK
t
—
25
f
Delay Time, PCLK Rise to DTX Active
t
t
—
20
d1
d2
Delay Time, PCLK Rise to DTX
Transition
—
20
Delay Time, PCLK Rise to DTX Tri-
state
t
—
—
20
ns
d3
4
Setup Time, FSYNC to PCLK Fall
Hold Time, FSYNC to PCLK Fall
Setup Time, DRX to PCLK Fall
Hold Time, DRX to PCLK Fall
FSYNC Pulse Width
t
25
20
25
20
—
—
—
—
—
—
—
ns
ns
ns
ns
su1
t
h1
t
—
su2
t
—
h2
t
t
125 µs–t
p
wfs
p
Notes:
1. All timing is referenced to the 50% level of the waveform. Input test levels are VIH – VI/O – 0.4 V, VIL = 0.4 V.
2. A constant PCLK and FSYNC are required.
3. FSYNC source is assumed to be 8 kHz under all operating conditions.
4. Spec applies to PCLK fall to DTX tristate when that mode is selected.
14
Rev. 1.2
Si3226/27 +
Si3208/09
tr
tf
tp
PCLK
th1
twfs
tsu1
tfs
FSYNC
tsu2
th2
DRX
DTX
td2
td1
td3
Figure 4. PCM Highway Interface Timing Diagram
Table 11. Switching Characteristics—GCI Highway Serial Interface
(VDD = 3.13 to 3.47 V, TA = 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade)
1
Symbol
Test
Conditions
Min
Typ
Max
Units
Parameter
PCLK Period (2.048 MHz PCLK Mode)
PCLK Period (4.096 MHz PCLK Mode)
t
t
—
—
—
40
—
—
—
—
—
—
—
25
20
25
20
488
244
125
50
±8
—
—
—
ns
ns
µs
%
p
p
2
FSYNC Period
t
—
fs
PCLK Duty Cycle Tolerance
PCLK Jitter Tolerance
t
60
—
dty
t
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
jitter
jitter
FSYNC Jitter Tolerance
±120
25
25
20
20
20
—
Rise Time, PCLK
t
—
r
Fall Time, PCLK
t
—
f
Delay Time, PCLK Rise to DTX Active
t
t
t
—
d1
d2
d3
Delay Time, PCLK Rise to DTX Transition
—
3
Delay Time, PCLK Rise to DTX Tristate
—
Setup Time, FSYNC Rise to PCLK Fall
Hold Time, PCLK Fall to FSYNC Fall
Setup Time, DRX Transition to PCLK Fall
Hold Time, PCLK Falling to DRX Transition
FSYNC Pulse Width
t
—
su1
t
—
—
h1
t
—
—
su2
t
—
—
h2
t
t /2
—
—
wfs
p
Notes:
1. All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VO – 0.4 V and VIL = 0.4 V.
Rise and fall times are referenced to the 20% and 80% levels of the waveform.
2. FSYNC source is assumed to be 8 kHz under all operating conditions.
3. Specification applies to PCLK fall to DTX tristate when that mode is selected.
Rev. 1.2
15
Si3226/27 +
Si3208/09
tr
tf
tp
PCLK
th1
tsu1
tfs
FSYNC
tsu2
th2
Frame 0,
Bit 0
DRX
DTX
td1
td2
td3
Frame 0,
Bit 0
Figure 5. GCI Highway Interface Timing Diagram (2.048 MHz PCLK Mode)
tr
tf
tc
PCLK
th1
tfs
tsu1
FSYNC
tsu2
th2
Frame 0,
Bit 0
DRX
DTX
td1
td3
td2
Frame 0,
Bit 0
Figure 6. GCI Highway Interface Timing Diagram (4.096 MHz PCLK Mode)
16
Rev. 1.2
Si3226/27 +
Si3208/09
RX Attenuation Distortion
5
0
−5
−10
−15
−20
−25
−30
−35
−40
−45
0
250 500 750 1000 1250 1500 1750 2000 2250 2500 2750 3000 3250 3500 3750 4000 4250 4500 4750 5000
Frequency (Hz)
RX Pass−Band Detail
0.4
0.2
0
−0.2
−0.4
−0.6
−0.8
−1
−1.2
0
250 500 750 1000 1250 1500 1750 2000 2250 2500 2750 3000 3250 3500 3750 4000 4250 4500 4750 5000
Frequency (Hz)
Figure 7. RX Attenuation Distortion
Rev. 1.2
17
Si3226/27 +
Si3208/09
TX Attenuation Distortion
5
0
−5
−10
−15
−20
−25
−30
−35
−40
−45
0
250 500 750 1000 1250 1500 1750 2000 2250 2500 2750 3000 3250 3500 3750 4000 4250 4500 4750 5000
Frequency (Hz)
TX Pass−Band Detail
0.4
0.2
0
−0.2
−0.4
−0.6
−0.8
−1
−1.2
0
250 500 750 1000 1250 1500 1750 2000 2250 2500 2750 3000 3250 3500 3750 4000 4250 4500 4750 5000
Frequency (Hz)
Figure 8. TX Attenuation Distortion
18
Rev. 1.2
Si3226/27 +
Si3208/09
TX Group Delay Distortion
1100
1000
900
800
700
600
500
400
300
200
100
0
200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400 2600 2800 3000 3200 3400
Frequency (Hz)
Figure 9. Transmit Group Delay Distortion
RX Group Delay Distortion
1100
1000
900
800
700
600
500
400
300
200
100
0
200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400 2600 2800 3000 3200 3400
Frequency (Hz)
Figure 10. Receive Group Delay Distortion
Rev. 1.2
19
Si3226/27 +
Si3208/09
Acceptable
Figure 11. Transmit and Receive Path SNDR
9
8
7
6
5
4
Fundamental
Output Power
(dBm0)
Acceptable
Region
3
2.6
2
1
0
1
2
3
4
5
6
7
8
9
Fundamental Input Power (dBm0)
Figure 12. Overload Compression Performance
20
Rev. 1.2
Si3226/27 +
Si3208/09
2. Typical Application Circuits
V D C
D
G N
R B N V G
V B A T b
V B R N G
V B A T
R B N V G
V B A T a
V B R N G
V B A T
E G N D
E G N D
V D C
D
G N
R 2 1 0
R 1 1 0
b
a
V B A T
V B A T
V B A T b
V B A T a
V C C
D G N
3
+ 3 V
V D D R E G
3 8
V D D A
N D G D
2 9
5 8
3 0
D V D A
V D D D
V D D C
S V D C
D V D D
N D G A
5 7
2 4
8
D V D C
Rev. 1.2
21
Si3226/27 +
Si3208/09
Kelvin Connect Jumper
to Resistor
J120, R133
J123, R132
J124, R122
Can be used to measure the input and output power
J123
2
1
VDC
IDcDcA
R132
0.05
VDC
VDC
GND
This design is optimized for VDC=7V-20V
Snubber
C133 68pF
C120
10uF
C121
0.1uF
NI
VDC
R130
150
C120 is an
optional input
decoupling cap
In place of C130
Kelvin Connect Jumper
to Resistor
R138
0
J124 IVbatA
2
T120
8
1
N=3
R137 15
NI
D120
R122
1
7
5.11
ES1F
*2
VOUT
N=2
R122 forms a LPF with
the decoupling cap of
the linefeed
R136
0
4
6
N=1
NI
MOSFET DRIVER
8uH
R123
220
*3
Iripple
>
105mA
C132
0.1uF
C126
0.1uF
C122
0.1uF
C131
10uF
R125
681K
5
+
C127
Q121
470pF
For 7V-20V, 0C-85C
200V FET
25V
*4
MMBT3906-7-F
Q120
FQT7N10
*1
DCDRV
Q120B
FQD7N20L
NI
*1
Fet must have Qgate <=10nC
NI
Icontinuous
> 1A;
C128
470pF
Fairchild FQT7N10
Zetex ZXMN10A11G
Vishay IRFL110
Q122
R126
68K
25V
R124
0
BSS138
C123
0.22uF
Zetex ZXMN10A08G
Fet must have
Qgate <=10nC
Icontinuous
>
1A
Fairchild FQT7N20L
IRF IRFL4315
SDCH
SDCL
STMICRO STD5N20L
JUMPER
J125
Q123
MMBT3904
R121
0.1
Route as
a differnetial pair
IR121
C124
0.22uF
C125
0.22uF
Load for Ambient -40C-85C
LAYOUT NOTES
-------------------------------------------------------------------------------------------
1) Dual Layout with Q120, Q120B DPAK and SOT-223
2) Minimize loop C121, T120, Q120, and R121
NOTES
*1. Voltage Rating FET:
Voltage Rating of C122, C123,
C124, C125, and C131
3) Place C130/C120 close to C121
(Vringrms*CrestFactor+VringOffset +Overhead)
4) Minimize loop C122, D120, T120, and R121
--------------------------------------------
N
+
VDC
+
Margin
Margin
should be
>
5) Place C123, C124,C15 and C131 close to C122
6) Minimize loop C126, Q121, Q120, R121, and SDCL
7) SDCL Connects to GND only at R121.
VringRMS*CrestFactor
+
VRingOffset
+
Overhead
*2. Voltage Rating D120:
peak POUT (Vringrms*CrestFactor
=
+
VringOffset
+
Overhead)
*
(Vringrms*CrestFactor)
------------------------
RenLoad (ohms)
(Vringrms*CrestFactor+VringOffset +Overhead)
*3. High Voltage inputs 20V-50 Require 25uH and N=2
+
N*VDC
+
8) Localize switcher gnd, attach to gnd plane at single point
*4. 5V VDC will require
a
logic level FET such as the FQT7n10L
9) VOUT nets should be routed with
a trace no less than 30mils. This is a high voltage net.
Keep these nets isolated from other nets.
10) Minimize loop T120, R130, C133, R127/R128
Figure 14. DC-DC Converter (A)
Kelvin Connect Jumper
J120, R133
J123, R132
J124, R122
Can be used to measure the input and output power
to Resistor
J223
2
1
VDC
IDcDcB
R232
0.05
VDC
VDC
GND
This design is optimized for VDC=7V-20V
Snubber
C233 68pF
C220
10uF
C221
0.1uF
NI
VDC
R230
150
C120 is an
optional input
decoupling cap
In place of C130
Kelvin Connect Jumper
to Resistor
R238
0
J224 IVbatB
2
T220
8
1
N=3
R237 15
NI
D220
R222
1
7
5.11
ES1F
*2
VOUT
N=2
R122 forms a LPF with
the decoupling cap of
the linefeed
R236
0
4
6
N=1
NI
MOSFET DRIVER
8uH
R223
220
*3
Iripple
>
105mA
C232
0.1uF
C226
0.1uF
C222
0.1uF
C231
10uF
R225
5
+
C227
Q221
681K
470pF
For 7V-20V, 0C-85C
200V FET
25V
*4
MMBT3906-7-F
Q220
FQT7N10
*1
DCDRV
Q220B
FQD7N20L
NI
*1
Fet must have Qgate <=10nC
NI
Icontinuous
> 1A;
C228
470pF
Fairchild FQT7N10
Zetex ZXMN10A11G
Vishay IRFL110
Q222
R226
68K
25V
R224
0
BSS138
C223
0.22uF
Zetex ZXMN10A08G
Fet must have
Qgate <=10nC
Icontinuous
>
1A
Fairchild FQT7N20L
IRF IRFL4315
SDCH
SDCL
STMICRO STD5N20L
JUMPER
J225
Q223
MMBT3904
R221
0.1
Route as
a
differnetial pair
IR121
C224
0.22uF
C225
0.22uF
Load for Ambient -40C-85C
LAYOUT NOTES
-------------------------------------------------------------------------------------------
1) Dual Layout with Q120, Q120B DPAK and SOT-223
2) Minimize loop C121, T120, Q120, and R121
NOTES
*1. Voltage Rating FET:
Voltage Rating of C122, C123,
C124, C125, and C131
3) Place C130/C120 close to C121
(Vringrms*CrestFactor+VringOffset +Overhead)
4) Minimize loop C122, D120, T120, and R121
--------------------------------------------
N
+
VDC
+
Margin
Margin
should be
>
5) Place C123, C124,C15 and C131 close to C122
6) Minimize loop C126, Q121, Q120, R121, and SDCL
7) SDCL Connects to GND only at R121.
VringRMS*CrestFactor
+
VRingOffset
+
Overhead
*2. Voltage Rating D120:
peak POUT (Vringrms*CrestFactor
=
+
VringOffset
+
Overhead)
*
(Vringrms*CrestFactor)
------------------------
RenLoad (ohms)
(Vringrms*CrestFactor+VringOffset +Overhead)
*3. High Voltage inputs 20V-50 Require 25uH and N=2
+
N*VDC
+
8) Localize switcher gnd, attach to gnd plane at single point
*4. 5V VDC will require
a
logic level FET such as the FQT7n10L
9) VOUT nets should be routed with
a trace no less than 30mils. This is a high voltage net.
Keep these nets isolated from other nets.
10) Minimize loop T120, R130, C133, R127/R128
Figure 15. DC-DC Converter (B)
22
Rev. 1.2
Si3226/27 +
Si3208/09
VBAT_REF
VBAT_REF
VBAT
VBAT_REF
R156
0
This Connection Forces VBAT_REF
to be local to this page
D154
C150
0.22uF
NI D153
ES1D
140V
NI
RT150
PTC
J150
Load
1
2
Option
ITipA
RF150
R150
1
2
NI
Load
15
Option
TIP_ext
1250T
TIP
Optional Cap:
Improves noise
performance
Current Limiting Resistors
for the LineFeed
Load
VBAT_REF
D150
Load
Option
Load
Load
Option
Option
Option
P1101SC
They provide Protection
during Surge and
Recommended
D155
for Australia
VBAT_REF
U151
PowerCross
NI
4
5
K2
K2
C108
NI
3
NC
0.01uF
200V
1
8
BAV23A
NI
K1
K1
D151
P1101SC
D152
P1101CA2
TISP61089BDR
NI
RF151
1250T
R151
15
1
2
NI
Load
RING_ext
Option
RING
J151
PROTECTION LOAD OPTIONS
Long Loop >500ft
RT151
PTC
1
2
Short Loop
< 500ft
IRngA
Load
Option
Option 1: (Recommended)
Option 1: VBAT
< 95V
Ux51: BOURNS TISP61089BDR
Dx50, Dx51: Littelfuse P1101SC
RFx50, RFx51: Littelfuse F1250T
RTx50, RTx51: BOURNS MF-SM013/250 PPTC
Rx55, Rx56, Cx50
Option 2: VBAT <95V
Dx52: LittelFuse P1101CA2
RFx50, RFx51: Littelfuse F1250T
Option 3:
Ux51: ST LCP1521S
RFx50, RFx51: BOURNS B0500T
Rx55, Rx56, Cx50
VBAT
LAYOUT NOTES
VBAT
----------------------------
1) Place Cx50 as close as possible to pin
G
(pin 2) of Ux50 and pin -Vref (pin 2) of Ux51.
2) OverLay the pads of RTX50 and RFX50. Also RTX51 and RFX51
3) Connect K1 pins of Ux51 together under package.
4) Connect K2 pins of Ux51 together under package.
5) Dual layout Ux51 for TISP61089HDM
EGND
6) Tip and Ring Traces should be 20mil from the connector to the line feed.
a very low impedance path to Chassis GND. This GND will experiance >100A surges.
7) Protection GND should be be
Figure 16. Protection (A)
VBAT_REF
VBAT_REF
VBAT
VBAT_REF
R256
0
This Connection Forces VBAT_REF
to be local to this page
D254
C250
0.22uF
NI D253
ES1D
140V
NI
RT250
PTC
J250
Load
1
2
Option
ITipB
RF250
R250
1
2
NI
Load
15
Option
TIP_ext
1250T
TIP
Optional Cap:
Improves noise
performance
Current Limiting Resistors
for the LineFeed
Load
VBAT_REF
D250
Load
Option
Load
Load
Option
Option
Option
P1101SC
They provide Protection
during Surge and
Recommended
D255
for Australia
VBAT_REF
U251
PowerCross
NI
4
5
K2
K2
C208
NI
3
NC
0.01uF
200V
1
8
BAV23A
NI
K1
K1
D251
P1101SC
D252
P1101CA2
TISP61089BDR
NI
RF251
1250T
R251
15
1
2
NI
Load
RING_ext
Option
RING
J251
PROTECTION LOAD OPTIONS
Long Loop >500ft
RT251
PTC
1
2
Short Loop
< 500ft
IRngB
Load
Option
Option 1: (Recommended)
Option 1: VBAT
< 95V
Ux51: BOURNS TISP61089BDR
Dx50, Dx51: Littelfuse P1101SC
RFx50, RFx51: Littelfuse F1250T
RTx50, RTx51: BOURNS MF-SM013/250 PPTC
Rx55, Rx56, Cx50
Option 2: VBAT <95V
Dx52: LittelFuse P1101CA2
RFx50, RFx51: Littelfuse F1250T
Option 3:
Ux51: ST LCP1521S
RFx50, RFx51: BOURNS B0500T
Rx55, Rx56, Cx50
VBAT
LAYOUT NOTES
VBAT
----------------------------
1) Place Cx50 as close as possible to pin
G
(pin 2) of Ux50 and pin -Vref (pin 2) of Ux51.
2) OverLay the pads of RTX50 and RFX50. Also RTX51 and RFX51
3) Connect K1 pins of Ux51 together under package.
4) Connect K2 pins of Ux51 together under package.
5) Dual layout Ux51 for TISP61089HDM
EGND
6) Tip and Ring Traces should be 20mil from the connector to the line feed.
7) Protection GND should be be
a very low impedance path to Chassis GND. This GND will experiance >100A surges.
Figure 17. Protection (B)
Rev. 1.2
23
Si3226/27 +
Si3208/09
V D D
1 4
3 4
3 7
3 8
3 9
3 2
I C
I C
I C
N D D G
1 8
A G N D
3 6
V B A T a
V B A T b
_ 1
_ 2
V B A T
V B A T
24
Rev. 1.2
Si3226/27 +
Si3208/09
3. Bill of Materials
Table 12. Si3226/7 Bill of Materials
Qty
1
Reference
C3
Value
10uF
Rating
Volt
6.3V
50V
25V
50V
-95V
Tol
±20%
±0.25pF
±20%
±20%
Type
X5R
PCB Footprint
C0603
Mfr Part #
Mfr
C0603X5R6R3-106M
C0402HQN500-5R6C
C1210X7R250-106M
C0402X7R500-471M
P1101SCL
Venkel
Venkel
Venkel
Venkel
Littelfuse
2
C109 C110
C120 C220
C128 C228
5.6pF
NPO
C0402
2
10uF
X7R
C1210
2
470pF
P1101SC
X7R
C0402
4
D150 D151
D250 D251
Thyristors
DO-214AA
2
2
2
D152 D252 P1101CA2
-95V
200V
140V
Thyristors
Single
DO-214AA-3
DO-214AC
DO-35
P1101CA2L
ES1D
Littelfuse
D153 D253
D154 D254
ES1D
140V
1.0A
Diodes Inc.
500mW
Zener
1N5275B
Micro Com-
mercial Co
2
2
D155 D255
BAV23A
400mA
5.5A
200V
200V
DUAL
Nchan
SOT23-KKA
DPAK-G2SD
BAV23A
Diodes Inc.
Fairchild
Q120B
Q220B
FQD7N20
L
FQD7N20L
4
RF150RF151
RF250 RF251
1250T
1.25A
600V
TelCom
FUSE-F1250T
F1250T
Littelfuse
3
5
R4 R5 R6
0
1A
ThickFilm
ThickFilm
R0402
R0402
CR0402-16W-000
CR0402-16W-103J
Venkel
Venkel
R15 R16 R20
R21 R22
10K
1/16W
±5%
±5%
2
2
3
R136 R236
R137 R237
0
2A
ThickFilm
ThickFilm
Loop
R1206
R1206
CR1206-4W-000
CR1206-4W-150J
151-201-RC
Venkel
Venkel
15
1/4W
TP14 TP20
TP21
WHITE
TESTPOINT
Kobiconn
4
TP15 TP16
TP18 TP19
BLACK
Loop
TESTPOINT
151-203-RC
Kobiconn
2
2
8
U152 U252 LCP1521S
-150V
6.3V
10V
SLIC
X5R
X7R
SO8N6.0P1.27
C0603
LCP1521S
ST
C1 C6
10uF
±20%
±10%
C0603X5R6R3-106M
C0402X7R100-104K
Venkel
Venkel
C2 C4 C5 C7
C60 C100
0.1uF
C0402
C107 C200
1
C8
4.7nF
16V
±10%
±10%
X7R
X7R
C0402
C0805
C0402X7R160-472K
C0805X7R201-103K
Venkel
Venkel
10
C101 C102
C103 C104
C108 C201
C202 C203
C204 C208
0.01uF
200V
6
C105 C122
C132 C205
C222 C232
0.1uF
200V
±20%
X7R
C1206
C1206X7R201-104M
Venkel
Rev. 1.2
25
Si3226/27 +
Si3208/09
Table 12. Si3226/7 Bill of Materials
Qty
2
Reference
Value
100pF
0.1uF
Rating
Volt
6V
Tol
Type
X7R
X7R
PCB Footprint
C0402
Mfr Part #
Mfr
C111 C211
±10%
±10%
C0402X7R6R0-101K
C0603X7R250-104K
Venkel
Venkel
4
C121 C126
C221 C226
25V
C0603
8
C123 C124
C125 C150
C223 C224
C225 C250
0.22uF
250V
±20%
X7R
C1812
C1812X7R251-224M
Venkel
2
1
2
2
2
4
C127 C227
C130
470pF
220uF
10uF
50V
25V
±20%
±20%
±20%
±5%
X7R
C0402
C0402X7R500-471M
EEUFC1E221
Venkel
Panasonic
Nichicon
Venkel
555mA
1.0A
Alum_Elec C3.5X8MM-RAD
C131 C231
C133 C233
D120 D220
200V
200V
300V
Alum_Elec
COG
C5X10MM-RAD
C0805
UVZ2D100MPD
C0805C0G201-680J
ES1F
68pF
ES1F
Single
DO-214AC
Fairchild
Samtec
JS1 JS4 JS5
JS6
CONN
SOCKET
5x2
Socket
CONN2X5-SSQ
SSQ-105-24-F-D
1
JS2
CONN
SOCKET
2x2/SM
Socket
Header
CONN-2X2-SSM
CONN-2X2-TSM
SSM-102-L-DV
Samtec
Samtec
1
2
JS3
HEADER
2x2/SM
TSM-102-02-T-DV
J1 J2
RJ-11
RJ-11
RJ11-6-SMT
CONN-1X2
5555077-2
AMP
11 J5 J123 J124 JUMPER
J125 J150
Header
TSW-102-07-T-S
Samtec
J151 J223
J224 J225
J250 J251
2
2
Q120 Q220
FQT7N10
1.7A
100V
40V
Nchan
PNP
SOT223-GDS
SOT23-BEC
FQT7N10
Fairchild
Q121 Q221 MMBT390 200mA
6-7-F
MMBT3906-7-F
Diodes Inc.
2
2
Q122 Q222
BSS138
200mA
50V
40V
Nchan
NPN
SOT23-GSD
SOT23-BEC
BSS138
Zetex
Q123 Q223 MMBT390 200mA
4
MMBT3904
Fairchild
4
RT150RT151
RT250 RT251
PTC
3A
250V
TelCom
PTC-MF-SM013
MF-SM013/250-2
Bourns
1
6
R2
49.9K
0
1/16W
1A
±0.5%
±1%
ThickFilm
ThickFilm
R0603
R0402
CR0603-16W-4992D
CR0402-16W-000
Venkel
Venkel
R3 R7 R8
R64 R124
R224
3
R11 R121
R221
0.1
1/2W
ThickFilm
R1210
LCR1210-R100F
Venkel
26
Rev. 1.2
Si3226/27 +
Si3208/09
Table 12. Si3226/7 Bill of Materials
Qty
Reference
Value
Rating
Volt
Tol
Type
PCB Footprint
Mfr Part #
Mfr
5
R13 R19 R60
R61 R62
10K
1/16W
±5%
ThickFilm
R0402
CR0402-16W-103J
Venkel
1
2
6
R17
137K
825K
681K
1/16W
1/10W
1/10W
±1%
±1%
±1%
ThickFilm
ThickFilm
ThickFilm
R0402
R0805
R0805
CR0402-16W-1373F
CR0805-10W-8253F
CR0805-10W-6813F
Venkel
Venkel
Venkel
R100 R200
R101 R102
R125 R201
R202 R225
4
R103 R104
R203 R204
301K
1/16W
±1%
ThickFilm
R0603
CR0603-16W-3013F
Venkel
2
4
R105 R205
590K
1/10W
1/8W
±1%
±1%
ThickFilm
ThickFilm
R0805
R1206
CR0805-10W-5903F
CR1206-8W-1474F
Venkel
Venkel
R106 R107
R206 R207
1.47M
4
R108 R109
R208 R209
110K
1/16W
±1%
±1%
ThickFilm
R0402
CR0402-16W-1103F
Venkel
2
5
R110 R210
0
2A
ThickFilm
ThickFilm
R0805
R0805
CR0805-10W-000
Venkel
Venkel
R111 R150
R151 R250
R251
15
1/10W
CR0805-10W-15R0F
2
2
2
2
2
4
R122 R222
R123 R223
R126 R226
R130 R230
R132 R232
5.11
220
68K
150
0.05
0
1/10W
1/16W
1/16W
1/4W
1/2W
2A
±1%
±5%
±1%
±1%
±1%
ThickFilm
ThickFilm
ThickFilm
ThickFilm
ThickFilm
ThickFilm
R0805
R0402
R0402
R1206
R1210
R1206
CR0805-10W-5R11F
CR0402-16W-221J
CR0402-16W-6802F
CR1206-4W-1500F
LCR1210-R050F
Venkel
Venkel
Venkel
Venkel
Venkel
Venkel
R138 R156
R238 R256
CR1206-4W-000
6
TP1 TP2 TP3
TP4 TP9
TP10
WHITE
Loop
TESTPOINT
151-201-RC
Kobiconn
1
2
1
TP17
T120 T220
U1
BLACK
8uH
Loop
SLIC
TESTPOINT
151-203-RC
UTB01701s
Si3227-D-FQ
Kobiconn
UMEC
5A, 25W
XFMR-UTB01701s
Si3227
3.3V
QFP64N12X12P0.
5
SiLabs
1
1
U60
AT25010A
5V
Serial
SLIC
SO8N6.0P1.27
AT25010A
ATMEL
SiLabs
U100
Si3209/
QFN40
–135V
QFN40N6X6P0.5
Si3209-B-FM
2
U151 U251
TISP6108
9BDR
–150V
SLIC
SO8N6.0P1.27
TISP61089BDR
Bourns
Rev. 1.2
27
Si3226/27 +
Si3208/09
4. Functional Description
Si3208/09
Si3226/27
SLIC
Linefeed
Control
CODEC
PCM/
GCI
Interface
FSYNC
DTMF &
Tone Gen
DRX
DTX
TIP
ADC
Channel 1
RING
Caller ID
Linefeed
Monitor
CS
SDI
DAC
SPI
Control
Interface
Ringing
Generator
SDO
SCLK
INT
SLIC
Linefeed
Control
CODEC
DSP
TIP
Line Diagnostics
ADC
RST
Channel 2
RING
Linefeed
Monitor
DAC
PCLK
DC-DC Controllers
PLL
VBAT
DC-DC BOM
VDC
®
The Dual ProSLIC chipset includes the Si3226/27 low- The linefeed ICs (Si3208/09) provide programmable on-
voltage IC and the Si3208/09 high-voltage linefeed IC. hook voltage, programmable off-hook loop current,
The Dual ProSLIC provides all SLIC, codec, DTMF reverse battery operation, loop or ground start
detection, and signal generation functions needed for operation, and on-hook transmission. Loop current and
two complete analog telephone interfaces. The Dual voltage are continuously monitored using an A/D
ProSLIC performs all battery, over-voltage, ringing, converter in the Si3226/27. The Si3208 supports battery
supervision, codec, hybrid, and test (BORSCHT) voltages up to 110 V, sufficient for most ringing signals.
functions; it also supports extensive metallic loop testing The Si3209 supports battery voltages up to 135 V for
capabilities.
higher-voltage ringing applications.
The Si3226 provides a standard voice-band (200 Hz– The Dual ProSLIC supports balanced 5 REN ringing
3.4 kHz) audio codec. The Si3227 provides an audio with or without a programmable dc offset. The available
codec with both wideband (50 Hz–7 kHz) and standard offset, frequency, waveshape, and cadence options are
voice-band (200 Hz–3.4 kHz) modes. The wideband designed to ring the widest variety of terminal devices
mode provides an expanded audio band with a 16 kHz and to reduce external controller requirements.
sample rate for enhanced audio quality while the
A complete audio transmit and receive path is
standard voice-band mode provides standard telephony
integrated, including ac impedance and hybrid gain.
audio. The Si3226/27 provides two independent,
These features are software-programmable, allowing a
programmable, dc-dc converter controllers, each of
single hardware design to meet global requirements.
which reacts to line conditions to provide the optimal
Digital voice data transfer occurs over a standard PCM
battery voltage required for each line-state.
bus. Control data is transferred using a standard SPI.
The Si3226/27 is available in a 64-pin TQFP; the
Si3208/09 are available in a 40-pin QFN.
28
Rev. 1.2
Si3226/27 +
Si3208/09
4.1. DC Feed Characteristics
4.4. Power Monitoring and Power Fault
Detection
Dual ProSLIC internal linefeed circuitry provides
completely programmable dc feed characteristics.
Linefeed characteristics for each channel are
independently configurable.
The Dual ProSLIC's line monitoring functions are used
to continuously protect the linefeed IC (LFIC) against
excessive power conditions. The LFIC contains an on-
chip, analog sensing diode that provides real-time
temperature data to the Si3226/27 and turns off the
LFIC when a preset threshold is exceeded. The LFIC
status is reflected in a Si3226/27 register bit.
When in the active state, each ProSLIC channel
operates in one of three dc linefeed operating regions: a
constant-voltage region, a constant-current region, or a
resistive region, as shown in Figure 19. The constant-
voltage region has a low resistance, typically 160 .
The constant-current region approximates infinite
resistance.
If the Si3226/27 detects a fault condition or overpower
condition on any channel, it automatically sets that
channel to the open state and generates a "power
alarm" interrupt. The interrupt can be masked, but the
automatic transition to open is not recommended to be
masked. The various power alarms and linefeed faults
supporting automatic intervention are described below.
I_ILIM
I_RFEED
I_VLIM
ILOOP (mA)
1. LFIC total power exceeded.
2. Excessive foreign current or voltage on TIP and/or
RING.
3. LFIC thermal shutdown event; this event is
automatically performed, and no intervention by the
V_ILIM
4. Si3226/27 is required.
Resistive Region
V_RFEED
V_VLIM
4.5. Thermal Overload Shutdown
Constant V Region
If the LFIC die temperature exceeds the programmed
junction temperature threshold, the LFIC will go to an
open state without any assistance from the Si3226/27.
VTR(V)
Figure 19. Dual ProSLIC DC Feed
Characteristics
4.2. Linefeed Operating States
The linefeed interface includes eight different register-
programmable operating states as listed in Table 13.
The Open state is the default condition in the absence
of any preloaded register settings. The device may also
automatically enter the open state in the event of a
linefeed fault condition.
4.3. Line Voltage and Current Monitoring
The Dual ProSLIC continuously monitors the TIP, RING,
and battery voltages and currents via an on-chip ADC
and stores the resulting values in individual register
addresses. Additionally, the loop voltage (V –V
),
TIP
RING
loop current, and longitudinal current values are
calculated based on the TIP and RING measurements
and are stored in unique register locations for further
processing. The ADC updates all registers at a rate of
2 kHz or greater.
Rev. 1.2
29
Si3226/27 +
Si3208/09
Table 13. Linefeed Operating States
Description
Linefeed State
Open
Output is high-impedance, and all line supervision functions are powered down. Audio is
powered down. This is the default state after powerup or following a hardware reset. This
state can also be used in the presence of line fault conditions and to generate open switch
intervals (OSIs). This state is used in line diagnostics mode as a high-Z state during line-
feed testing. A power fault condition may also force the device into the open state.
Forward Active
Reverse Active
Linefeed circuitry and audio are active. In Forward Active state, the TIP lead is more posi-
tive than the RING lead; in Reverse Active state, the RING lead is more positive than the
TIP lead. Loop closure and ground key detect circuitry are active.
Forward OHT
Reverse OHT
Provides data transmission during an on-hook loop condition (e.g., transmitting caller ID
data between ringing bursts). Linefeed circuitry and audio are active. In Forward OHT
state, the TIP lead is more positive than the RING lead; in Reverse OHT state, the RING
lead is more positive than the TIP lead.
TIP Open
Provides an active linefeed on the RING lead and sets the TIP lead to high impedance
(>400 k) for ground start operation in forward polarity. Loop closure and ground key
detect circuitry are active.
RING Open
Provides an active linefeed on the TIP lead and sets the RING lead to high impedance
(>400 k) for ground start operation in reverse polarity. Loop closure and ground key
detect circuitry are active.
Ringing
Drives programmable ringing signal onto TIP and RING leads with or without dc offset.
Line Diagnostics
The channel selected is put into diagnostic mode. In this mode, the selected channel has
special diagnostic resources available.
30
Rev. 1.2
Si3226/27 +
Si3208/09
4.6. Power Dissipation Considerations
4.10. Polarity Reversal
The Dual ProSLIC is designed to source loops up to The Dual ProSLIC supports polarity reversal for
20 kft as well as short loop applications. The LFIC message waiting and various other signaling modes.
provides all battery sourcing functions and is, therefore, The ramp rate can be programmed for a smooth or
the determining factor regarding power dissipation in a abrupt transition to accommodate different application
specific application. The Dual ProSLIC provides an on- requirements.
chip dc-dc controller that can dynamically reduce the
battery supply to ideally match the required line feed
4.11. Two-Wire Impedance Synthesis
voltage.
The ac two-wire impedance synthesis is generated on-
chip using a DSP-based scheme to optimally match the
output impedance of the Dual ProSLIC to the
4.7. Loop Closure Detection
The Dual ProSLIC provides a completely programmable impedance of the subscriber loop and minimize the
loop closure detection mechanism. The loop closure receive path signal reflected back onto the transmit
detection scheme provides two unique thresholds to path. Most real or complex two-wire impedances can be
allow hysteresis, and also includes a programmable generated by using the coefficient generator software to
debounce filter to eliminate false detection. A loop simulate the desired line conditions and generate the
closure detect status bit provides continuous status, and required register coefficients.
a maskable interrupt bit is also provided.
4.12. Transhybrid Balance Filter
4.8. Ground Key Detection
The transhybrid balance function is implemented on-
The Dual ProSLIC provides a ground key detect chip using a DSP-based scheme to effectively cancel
mechanism using a programmable architecture similar the reflected receive path signal from the transmit path.
to the loop closure scheme. The ground key detect The coefficient generator software is used to optimize
scheme provides two unique thresholds to allow the filter coefficients.
hysteresis and also includes a programmable debounce
filter to eliminate false detection. A ground key detect
4.13. Tone Generators
status bit provides continuous status, and a maskable The Dual ProSLIC includes two digital tone generators
interrupt bit is also provided.
that allow a wide variety of single- or dual-tone
frequency and amplitude combinations. Each tone
generator has its own set of registers that hold the
4.9. Ringing Generation
The Dual ProSLIC provides the ability to generate a desired frequency, amplitude, and cadence to allow
programmable sinusoidal or trapezoidal ringing generation of DTMF and call progress tones for different
waveform, with or without dc offset. The ringing requirements. The tones can be directed to either
frequency, wave shape, cadence, and offset are all receive or transmit paths.
register-programmable. Using
scheme, the ringing signal is applied to both the TIP and
a
balanced ringing
4.14. DTMF Detection
RING leads using dual ringing waveforms that are 180° In DTMF, two tones generate a DTMF digit. One tone is
out of phase with each other. The resulting ringing chosen from the four possible row tones, and one tone
signal seen across TIP-RING is twice the amplitude of is chosen from the four possible column tones. The sum
the ringing waveform on either the TIP or RING lead, of these tones constitutes one of 16 possible DTMF
which allows the ringing circuitry to be forced to digits. The Dual ProSLIC performs DTMF detection
withstand only half the total ringing amplitude seen using an algorithm to compute the DFT for each of the
across TIP-RING.
eight DTMF frequencies and their second harmonics. At
the end of the DFT computation, the squared
magnitudes of the DFT results for the 8 DTMF
fundamental tones are computed. The row and column
results are sorted to determine the strongest tones, and
checks are made to determine if the strongest row and
column tones constitute a DTMF digit.
Rev. 1.2
31
Si3226/27 +
Si3208/09
4.15. DC-DC Controller
4.19. General Circuit Interface
The controller operates a dc-dc converter circuit that The
Dual
ProSLIC
supports
an
alternative
converts a single positive dc input voltage into an communication interface to the SPI and PCM control
independent negative battery voltage for each channel. and data interface. The General Circuit Interface (GCI)
In addition to eliminating external high-voltage power is used for transmission and reception of both control
supplies, the dc-dc controller allows the Dual ProSLIC and data information onto a GCI bus. The PCM and GCI
to dynamically control the battery voltage to the interfaces are both 4-wire interfaces and share the
minimum required for any given operating state same pins. In GCI mode, the four-wire SPI control
according to the programmed linefeed parameters.
interface is used as hard-wired channel selector pins.
The selection between PCM and GCI modes is
performed when coming out of reset using the
4.16. Wideband Audio
The Si3226 supports a narrowband (200 Hz–3.4 kHz) SDITHRU pin.
audio codec. The Si3227 supports software-
selectable wideband (50 Hz–7 kHz) and narrowband
a
4.20. Metallic Loop Testing
(200 Hz–3.4 kHz) audio codec. The Si3227 wideband The Dual ProSLIC includes the ability to detect multiple
mode provides an expanded audio band at a 16-bit, fault conditions within the line card as well as on the T/R
16 kHz sample rate for enhanced audio quality while pair.
maintaining standard telephony audio compatibility. In
wideband operation, two time slots are used to transmit
the wideband signal and each slot contains 8-bits of the
16-bit sample. These two time slots are transmitted and
received half a frame apart, but within the same 8 kHz
frame.
1. Hazardous Potential Test—This test checks for ac
voltage >50 V
or dc voltage >135 V on T-G or R-
rms
G. If a hazardous voltage is encountered, test access
MUST release within two seconds of the time when it
was initiated using a preset threshold.
2. Foreign ElectroMotive Force Test—Checks T-G or
R-G for ac voltage >10 V , dc voltage >6 V. Uses
same threshold as for hazardous voltage test.
4.17. SPI Control Interface
rms
The controller interface to the Dual ProSLIC is a 4-wire
interface modeled after microcontroller and serial
peripheral devices. The interface consists of a clock
(SCLK), chip select (CS), serial data input (SDI), and
3. Resistive Faults Test—Checks for dc resistance from
T-R, T-G or R-G. Any measurement <150 k is
considered a resistive fault.
serial data output (SDO). In addition, the Dual ProSLIC 4. Receiver-Off-Hook Test—Distinguishes between a
devices feature a serial data through output (SDITHRU)
to support operation of up to 16 devices (up to 32
channels) using a single chip select line. The device
operates with both 8-bit and 16-bit SPI controllers.
T-R resistive fault and an off-hook condition.
5. Ringers Test—Checks for the presence of REN
across T-R. Result are >0.175REN and <5REN for a
valid load.
4.18. PCM Interface and Companding
The Dual ProSLIC contains a flexible, programmable
6. Ringing Voltage Verification—Uses current voltage
sensing capability.
interface for the transmission and reception of digital 7. Test-In Diagnostics—The Dual ProSLIC can switch
PCM samples. PCM data transfer is controlled by the
PCM clock (PCLK) and frame sync (FSYNC) inputs as
well as the PCM Mode Select, PCM Transmit Start, and
PCM Receive Start settings.
in a preset load impedance to test the SLIC/codec
functionality using a known set of conditions.
The interface can be configured to support from 8 to
128 8-bit time slots in each 125 µs frame,
corresponding to a PCM clock (PCLK) frequency range
of 512 kHz to 8.192 MHz. 1.544 MHz is also supported.
The Dual ProSLIC supports both µ-255 Law (µ-Law)
and A-law companding formats in addition to 16-bit
linear data mode with no companding.
32
Rev. 1.2
Si3226/27 +
Si3208/09
5. Pin Descriptions: Si3226/27
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
HVCLKb
PCLK
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
DRINGb
URINGb
DTIPb
UTIPb
IBIASb
CAPLB
IREF
VDDD
GNDD
DCFFb
SDCHb
SDCLb
DCDRVb
VDDC
Si3226/27
64-Lead TQFP
Top VIew
QGND
GNDA
VDDA
DCDRVa
SDCLa
SDCHa
DCFFa
SDO
ISNS
IBIASa
UTIPa
DTIPa
URINGa
DRINGa
SDITHRU
HVDATA
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
Rev. 1.2
33
Si3226/27 +
Si3208/09
Table 14. Si3226/27 Pin Descriptions
Pin #
Symbol
Description
1
2
SRINGDCa
SRINGACa
STIPACa
RING DC Sense Input.
RING AC Sense Input.
3
TIP AC Sense Input.
4
STIPDCa
CAPPa
TIP DC Sense Input.
5
Metallic Loop Filter Capacitor-Positive Terminal.
Metallic Loop Filter Capacitor-Negative Terminal.
Battery Sensing Input.
6
CAPMa
7
SVBATa
8
SVDC
DC-DC Input Power Rail Sensor.
General Purpose I/O / Power Offloading Output.
9
GPIO3a / PWROa
10
GPIO2a / SRINGCa /
TRD2a
5 V tolerant I/O
General Purpose I/O / RING Coarse Sense Input / Test Relay
Driver.
11
GPIO1a / STIPCa / TRD1a
5 V tolerant I/O
General Purpose I/O / TIP Coarse Sense Input / Test Relay
Driver.
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
CS
Chip Select Input.
FSYNC
SDI
Frame Sync Clock Input.
Serial Port Data Input.
HVCLKa
SCLK
Line-Driver IC Clock Output.
Serial Port Bit Clock Input.
Line-Driver IC Data Output
Serial Data Daisy Chain Output.
Serial Port Data Output.
HVDATA
SDITHRU
SDO
DCFFa
SDCHa
SDCLa
DCDRVa
VDDC
DC Flexible Function I/O A.
DC-DC Current Monitor Input-High Terminal.
DC-DC Current Monitor Input-Low Terminal.
DC-DC Drive Output.
DC-DC Switch Driver Power Supply.
DC-DC Drive Output.
DCDRVb
SDCLb
SDCHb
DCFFb
GNDD
VDDD
DC-DC Current Monitor Input-Low Terminal.
DC-DC Current Monitor Input-High Terminal.
DC Flexible Function I/O B
Digital Ground.
Digital Supply Voltage.
PCLK
PCM Bus Clock Input.
HVCLKb
Line-Driver IC Clock Output.
34
Rev. 1.2
Si3226/27 +
Si3208/09
Table 14. Si3226/27 Pin Descriptions (Continued)
Pin #
Symbol
Description
33
34
35
36
37
38
39
DTXEN
Transmit PCM Enable Output.
Transmit PCM Data Output.
Receive PCM Data Input.
Interrupt Output.
DTX
DRX
INT
RST
Reset Input.
VDDREG
Regulated Core Power Supply.
GPIO1b / STIPCb / TRD1b
5 V tolerant I/O
General Purpose I/O / TIP Coarse Sense Input / Test Relay
Driver.
40
GPIO2b / SRINGCb /
TRD2b
5 V tolerant I/O
General Purpose I/O / RING Coarse Sense Input / Test Relay
Driver.
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
GPIO3b / PWROb
SVBATb
CAPMb
CAPPb
STIPDCb
STIPACb
SRINGACb
SRINGDCb
DRINGb
URINGb
DTIPb
General Purpose I/O / Power Offloading Output.
Battery Sensing Input.
Differential Loop Filter Capacitor-Negative Term.
Differential Loop Filter Capacitor-Positive Term.
TIP DC Sense Input.
TIP AC Sense Input.
RING AC Sense Input.
RING DC Sense Input.
RING Pull-Down Current Driver Output.
RING Pull-Up Current Driver Output.
TIP Pull-Down Current Driver Output.
TIP Pull-Up Current Driver Output.
Line Driver IC Bias Current Output.
Longitudinal Balance Calibration Capacitor.
Current Reference Input.
UTIPb
IBIASb
CAPLB
IREF
QGND
Quiet Ground Reference Input.
Analog Ground.
GNDA
VDDA
Analog Supply Voltage.
ISNS
Line Current Sense Input.
IBIASa
Line Driver IC Bias Current Output.
TIP Pull-Up Current Driver Output.
TIP Pull-Down Current Driver Output.
RING Pull-Up Current Driver Output.
RING Pull-Down Current Driver Output.
UTIPa
DTIPa
URINGa
DRINGa
Rev. 1.2
35
Si3226/27 +
Si3208/09
6. Pin Descriptions: Si3226/27 + Si3208/09
40
39
38
37
36
35
34
33
32
31
1
2
30
29
28
27
26
25
24
23
22
21
IC
NC
IC
NC
3
RING_1
NC
RING_2
NC
Si3208/09
4
40-Lead QFN
(epad)
5
TIP_2
NC
TIP_1
NC
6
7
Top View
IC
IC
8
IRINGN_2
IRINGP_2
ITIPN_2
IRINGN_1
IRINGP_1
ITIPN_1
9
10
11
12
13
14
15
16
17
18
19
20
Table 15. Si3208/09 Pin Descriptions
QFN Pin #
Symbol
IC
Description
1
2
Internal connection; leave unbiased.
No Connect. Leave unbiased.
Ring Channel 1 Input/Output.
No Connect. Leave unbiased.
Tip Channel 1 Input/Output.
NC
3
RING_1
NC
4
5
TIP_1
NC
6
No Connect. Leave unbiased.
Internal connection; leave unbiased.
7
IC
8
IRINGN_1
IRINGP_1
ITIPN_1
ITIPP_1
IBIAS_1
ISNS
Negative Ring Current Control Channel 1 Input.
Positive Ring Current Control Channel 1 Input.
Negative Tip Current Control Channel 1 Input.
Positive Tip Current Control Channel 1 Input.
Current Bias Channel 1 Input.
9
10
11
12
13
Current Sense Output.
36
Rev. 1.2
Si3226/27 +
Si3208/09
Table 15. Si3208/09 Pin Descriptions (Continued)
QFN Pin #
14
Symbol
Description
VDD
HVCLK_1
HVDATA
HVCLK_2
DGND
IBIAS_2
ITIPP_2
ITIPN_2
IRINGP_2
IRINGN_2
IC
IC Supply Voltage Input.
15
High-Voltage IC Clock Channel 1 Input.
High-Voltage IC Data Input/Output.
High-Voltage IC Clock Channel 2 Input.
Digital Ground.
16
17
18
19
Current Bias Channel 2 Input.
20
Positive Tip Current Control Channel 1 Input.
Negative Tip Current Control Channel 2 Input.
Positive Ring Current Control Channel 2 Input.
21
22
23
Negative Ring Current Control Channel 2 Input.
Internal connection; leave unbiased.
No Connect. Leave unbiased.
24
25
NC
26
TIP_2
NC
Tip Channel 2 Input/Output.
27
No Connect. Leave unbiased.
28
RING_2
NC
Ring Channel 2 Input/Output.
29
No Connect. Leave unbiased.
30
IC
Internal connection; leave unbiased.
Internal connection; leave unbiased.
Operating Battery Voltage Channel 2 Input.
No Connect. Leave unbiased.
31
IC
32
VBAT_2
NC
33
34
IC
Internal connection; leave unbiased.
No Connect. Leave unbiased.
35
NC
36
AGND
IC
Analog Ground.
37
Internal connection; leave unbiased.
Internal connection; leave unbiased.
Operating Battery Voltage Channel 1 Input.
Internal connection; leave unbiased.
38
IC
39
VBAT_1
IC
40
epad
Exposed Die Attach Paddle.
For adequate thermal management, the exposed die paddle should be
soldered to a printed circuit board pad that is connected to an electri-
cally-isolated low-impedance inner layer and/or backside thermal
plane(s) using multiple thermal vias. Do not connect this pad to ground.
Rev. 1.2
37
Si3226/27 +
Si3208/09
7. Ordering Guide
1
2
Description
Temperature
Range
Part Number
Package
Si3226-E-FQ
Si3226-E-GQ
Si3227-E-FQ
Si3227-E-GQ
Si3208-B-FM
Si3208-B-GM
Si3209-B-FM
Si3209-B-GM
Notes:
Dual ProSLIC
Dual ProSLIC
TQFP-64
TQFP-64
TQFP-64
TQFP-64
QFN-40
QFN-40
QFN-40
QFN-40
0 to 70 C
–40 to 85 C
0 to 70 C
Dual ProSLIC, wideband
Dual ProSLIC, wideband
–110 V line-feed IC
–110 V line-feed IC
–135 V line-feed IC
–135 V line-feed IC
–40 to 85 C
0 to 70 C
–40 to 85 C
0 to 70 C
–40 to 85 C
1. Adding the suffix “R” to the end of the part number (e.g., Si3226-E-FQR) denotes tape-and-reel packaging.
2. All packages are RoHS-compliant.
38
Rev. 1.2
Si3226/27 +
Si3208/09
8. Product Identification
The product identification number is a finished goods part number or is specified by a finished goods part number,
such as a special customer part number.
Example:
Si3227-E-FQR
Shipping Option
Blank = Trays
Product Designator
R = Tape and Reel
Product Revision
Package Type
Q = TQFP-64
Part Type / Lead Finish
F = Commercial / RoHS-Compliant
G = Industrial / RoHS-Compliant
Si3208-B-FMR
Shipping Option
Blank = Trays
R = Tape and Reel
Product Designator
Product Revision
Package Type
M = QFN-40
Part Type / Lead Finish
F = Commercial / RoHS-Compliant
G = Industrial / RoHS-Compliant
Rev. 1.2
39
Si3226/27 +
Si3208/09
9. Package Outline: 64-Pin TQFP
Figure 20 illustrates the package details for the Si3226/27. Table 16 lists the values for the dimensions shown in
the illustration.
Figure 20. 64-pin Thin Quad Flat Package (TQFP)
Table 16. 64-pin TQFP Dimensions
Dimension
Min
—
Nom
—
Max
1.20
0.15
1.05
0.27
0.20
Dimension
Min
Nom
Max
A
E
E1
L
12.00 BSC.
A1
0.05
0.95
0.17
0.09
—
10.00 BSC.
A2
1.00
0.45
—
0.60
—
0.75
0.20
0.20
0.08
0.08
7
b
0.22
aaa
bbb
ccc
ddd
c
—
—
—
D
D1
12.00 BSC.
10.00 BSC.
0.50 BSC.
—
—
—
—
e
0
3.5
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. This package outline conforms to JEDEC MS-026, variant ACD.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
40
Rev. 1.2
Si3226/27 +
Si3208/09
Figure 21. 64-pin TQFP Land Pattern
Table 17. 64-pin TQFP Land Pattern Dimensions
Dimension
MIN
MAX
11.40
11.40
C1
C2
E
11.30
11.30
0.50 BSC
0.20
X
0.30
1.50
Y
1.40
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This land pattern design is based on the IPC-7351 guidelines.
Solder Mask Design
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to
be 60 µm minimum, all the way around the pad.
Stencil Design
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder
paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
Card Assembly
7. A No-Clean, Type-3 solder paste is recommended.
8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
Rev. 1.2
41
Si3226/27 +
Si3208/09
10. Package Outline: 40-Pin QFN
Figure 22 illustrates the package details for the Si3208/09. Table 18 lists the values for the dimensions shown in
the illustration.
Figure 22. 40-pin QFN Package
Table 18. 40-pin QFN Package Dimensions
Dimension
Min
0.80
0.00
0.18
Nom
0.85
Max
0.90
0.05
0.30
Dimension
Min
4.00
0.30
0.03
—
Nom
4.10
0.40
0.05
—
Max
4.20
0.50
0.08
0.10
0.10
0.08
0.10
A
E2
L
A1
0.02
b
0.25
L1
D
6.00 BSC.
4.10
aaa
bbb
ccc
ddd
D2
4.00
4.20
—
—
e
E
0.50 BSC.
6.00 BSC.
—
—
—
—
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-220, variation VJJD-2.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for small body components.
42
Rev. 1.2
Si3226/27 +
Si3208/09
Figure 23. 40-Pin QFN Land Pattern
Rev. 1.2
43
Si3226/27 +
Si3208/09
Table 19. 40-pin QFN Land Pattern Dimensions
Dimension
MIN
MAX
e
0.50 BSC.
C1
C2
X1
X2
Y1
Y2
5.80
5.80
0.15
4.10
0.75
4.10
5.90
5.90
0.25
4.20
0.85
4.20
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on IPC-SM-782 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least
Material Condition (LMC) is calculated based on a Fabrication Allowance of
0.05 mm.
Solder Mask Design
5. All metal pads are to be non-solder mask defined (NSMD). Clearance
between the solder mask and the metal pad is to be 60 µm minimum, all the
way around the pad.
Stencil Design
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls
should be used to assure good solder paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter
pads.
9. A 4x4 array of 0.80 mm square openings on 1.05 mm pitch should be used for
the center ground pad.
Card Assembly
10. A No-Clean, Type-3 solder paste is recommended.
11. The recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
44
Rev. 1.2
Si3226/27 +
Si3208/09
Revision 1.0 to Revision 1.1
DOCUMENT CHANGE LIST
Revision 0.2 to Revision 0.32
Updated Ordering Guide for revision E silicon.
Updated Maximum Ringing Amplitude values and
DC Differential Output Resistance in Table 5
Linefeed Characteristics.
Added Si3208 and Si3209.
Removed Si3203, Si3205, and Si3206.
Added Powerup and Initialization Sequence diagram
to section 1.
Added pin-outs and package drawings for Si3208
and Si3209.
Added Reset timing diagram to section 1.
Updated pin-out for Si3226.
Updated bill of materials.
Added PCKLK Jitter tolerance to Table 10,
“Switching Characteristics—PCM Highway
Interface,” on page 14.
Updated “2. Typical Application Circuits” and added
dc-dc converter schematics.
Added PCKLK Jitter tolerance to Table 11,
“Switching Characteristics—GCI Highway Serial
Interface,” on page 15.
Updated tables.
Revision 0.32 to Revision 0.33
Updated the number of devices that can be daisy
chained in section "4.17. SPI Control Interface‚" on
page 32.
Changed package type for Si3208.
Deleted QFN-32 drawing.
Updated dc-dc converter schematic.
Updated bills of materials.
Added land pattern, solder mask, stencil and card
assembly guidelines.
Updated max V
values.
BAT
Updated Application Circuit and Bill of Materials in
sections 2 and 3.
Updated thermal shutdown thresholds.
Updated Si3208/09 pin descriptions.
Revision 1.1 to Revision 1.2
Revision 0.33 to Revision 1.0
Updated schematics in “2. Typical Application
Circuits”
Added pin-out diagrams for Si3226/27 and Si3208/
09
Updated Bill of Materials in “3. Bill of Materials”.
Updated schematic and BOM in section “3. Bill of
Materials”.
Updated power up sequence diagram in “1.
Electrical Specifications”
Updated former Tables 1-9. Removed former Table
7. See AN317 Section 2.2.1 for DC Feed
characteristics detail.
Updated section “4.16. Wideband Audio”
Added powerdown sequence
Added Figure 7, “RX Attenuation
Distortion.”Figure 8, “TX Attenuation
Distortion.”Figure 9, “Transmit Group Delay
Distortion.”Figure 10, “Receive Group Delay
Distortion.”.
Updated section “4. Functional Description”.
Updated section “5. Pin Descriptions: Si3226/27”
and section “6. Pin Descriptions: Si3226/27 +
Si3208/09”.
Updated section “9. Package Outline: 64-Pin TQFP”
and section “10. Package Outline: 40-Pin QFN”.
Deleted LFIC 48-pin eTQFP and 32-pin QFN
package references.
Added REG 73 = 0x0B to Longitudinal test
conditions
Rev. 1.2
45
Si3226/27 +
Si3208/09
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Please visit the Silicon Labs Technical Support web page:
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-
sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap-
plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Silicon Laboratories, Silicon Labs, and ProSLIC are trademarks of Silicon Laboratories Inc.
Other products or brand names mentioned herein are trademarks or registered trademarks of their respective holders.
46
Rev. 1.2
相关型号：
SI3210-E-FM
Perfroms all BORSCHT functions DC-DC controller provides tracking battery fromm a 3.3-35V input
SILICON
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