SI32170-B-FM1R [SILICON]
Telecom Circuit,;
| 型号： | SI32170-B-FM1R |
| 厂家： | 
SILICON |
| 描述： | Telecom Circuit, 电信 电信集成电路 |
| 文件： | 总64页 (文件大小：1212K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si3217x
Si3291x
PROSLIC® SINGLE-CHIP FXS SOLUTION WITH FXO OPTION
Si3217x Features
Performs all BORSCHT functions
Ideal for short to medium loops
Global programmability
Tracking dc-dc controller
Patented low-power ringing
Wideband voice support
Simplified configuration and diagnostics DTMF detection
Supported by ProSLIC API
Low power standby operation
Pulse metering
3.3 V operation
Pb-free/RoHS-compliant packaging
Si3291x Features
Greater than 5 kV isolation
Global programmability
Up to +6 dBm TX/RX level
Parallel handset detection
Type I and II caller ID support
Integrated ring detector
Programmable digital hybrid
Applications
Ordering Information
See page 48.
Customer Premise Equipment (CPE)
VoIP DSL Gateways and Routers
Wireless Local Loop (WLL)
Integrated Access Devices (IAD)
Analog Terminal Adapters (ATA)
Small Office/Home Office (SOHO)
PBX
Pin Assignments
Si3217x
Description
The Si3217x is a family of pin-compatible single-channel ProSLIC products that
implement a complete foreign exchange station (FXS) telephony interface solution in
accordance with all relevant LSSGR, ITU, and ETSI specifications. Select parts in
the series also implement Silicon Laboratories' patented capacitive isolation
technology to enable seamless connection to Si3291x series foreign exchange office
(FXO) line-side devices. The Si3217x ProSLIC ICs operate from a 3.3 V supply and
interface to standard PCM/SPI digital interfaces. The Si3217x integrated dc-dc
controller automatically generates the optimal battery voltages required for each line-
state. Si3217x ICs are available with voltage ratings of –110 V or –135 V to support a
wide range of ringing voltages. See the Ordering Guide for the voltage rating of each
Si3217x version. The Si3217x is available in a 5 x 7 mm 42-pin QFN package. The
Si3291x is available in a 16-pin SOIC package.
42
VDDHV
SDI
41 40 39 38 37 36
EPAD2
35
34
33
32
31
30
29
28
27
26
25
24
23
22
NC
1
2
3
4
GPIO1/STIPC
GPIO2/SRINGC
SRINGDC
SRINGAC
STIPAC
SDO
SCLK
SDITHRU
5
6
CS
FSYNC
PCLK
7
STIPDC
VDDA
QGND
IREF
8
9
INT
EPAD1
C2A/NC
C1A/NC
10
11
12
13
14
CAPM
DTX
DRX
CAPP
CAPLB
SVBAT
15 16 17 18 19 20 21
DCFF
Functional Block Diagram
Si3291x
1
16
15
14
13
12
11
10
9
DCT2
IGND
DCT3
QB
QE
DCT
RX
CODEC
ADC
SLIC
Linefeed
Control
PCM/
GCI
Interface
FSYNC
DRX
DTMF &
Tone Gen
TIP
2
3
4
5
6
7
8
DTX
FXS
FXO
RING
Caller ID
Linefeed
Monitor
CS
SDI
DAC
IB
SPI
Control
Interface
Ringing
Generator
SDO
SCLK
INT
TIP
RX
Optional FXO
Hybrid and
dc
Termination
C1B
C2B
VREG
RNG1
QE2
DCT
VREG
IGND
C1A C1B
C2A C2B
DSP
Isolation
Interface
Isolation
Interface
Line Diagnostics
SC
RST
CID
QB
QE
VREG2
RNG2
Control
Ring Detect
Off-Hook
RING
PCLK
DC-DC Controller
PLL
Si3217x
Si3291x
Patents pending
Rev. 1.4 3/13
Copyright © 2013 by Silicon Laboratories
Si3217x/3291x
Si3217x/3291x
2
Rev. 1.4
Si3217x/3291x
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2. Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
3. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
4. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
5. FXS Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
5.1. DC Feed Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
5.2. Linefeed Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
5.3. Line Voltage and Current Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
5.4. Power Monitoring and Power Fault Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
5.5. Thermal Overload Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
5.6. Loop Closure Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
5.7. Ground Key Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
5.8. Ringing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
5.9. Polarity Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
5.10. Two-Wire Impedance Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
5.11. Transhybrid Balance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
5.12. Tone Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
5.13. DTMF Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
5.14. Pulse Metering (Si32170/1 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
5.15. DC-DC Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
5.16. Wideband Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
5.17. In-Circuit and Metallic Loop Testing (MLT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
6. FXO Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
6.1. Isolation Barrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
6.2. Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
6.3. In-Circuit Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
6.4. Transmit/Receive Full-Scale Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
6.5. Line Voltage Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
6.6. Loop Current Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
6.7. Parallel Handset Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
6.8. DC Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
6.9. AC Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
6.10. Ring Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
6.11. Ring Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
6.12. Ringer Impedance and Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
6.13. Pulse Dialing and Spark Quenching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
6.14. Receive Overload Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
6.15. On-Hook Line Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
6.16. Transhybrid Balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
7. System Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
7.1. SPI Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Rev. 1.4
3
Si3217x/3291x
7.2. PCM Interface and Companding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
8. Pin Descriptions: Si3217x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
9. Pin Descriptions: Si3291x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
10. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
11. Product Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
12. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
12.1. 42-Pin QFN/LGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
12.2. 42-Pin QFN/NBA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
13. PCB Land Pattern Si3217x QFN (LGA or NBA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
13.1. QFN PCB Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
13.2. QFN Solder Mask Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
13.3. QFN Stencil Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
13.4. QFN Card Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
14. Package Outline: 16-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
15. PCB Land Pattern Si3291x SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
16. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
16.1. Si3217x LGA Package Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
16.2. Si3217x LGA Package Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . .59
16.3. Si3217x NBA Package Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
16.4. Si3217x NBA Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
16.5. Si32919 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
16.6. Si3291x Top Mark Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
4
Rev. 1.4
Si3217x/3291x
1. Electrical Specifications
Table 1. Recommended Operating Conditions1
Symbol
Test Condition
Min*
Typ
Max*
Unit
Parameter
Ambient Temperature
T
F-grade
G-grade
0
25
25
—
70
85
°C
°C
°C
A
–40
—
Silicon Junction Temperature,
QFN-42
T
Linefeed Die
145
JHV
Supply Voltage, Si3217x
V
, V
,
3.13
3.3
3.47
V
DDD DDA
V
DDHV
2
Battery Voltage, Si32171/6/8
V
–110
–136
–95
–15
–15
V
V
BAT
BAT
2
Battery Voltage, Si32170/7/9
V
–130
Notes:
1. All minimum and maximum specifications apply across the recommended operating conditions. Typical values apply at
nominal supply voltages and an operating temperature of 25 °C unless otherwise stated.
2. Operation at minimum voltage dependent upon loop conditions and dc-dc converter configuration.
Table 2. Power Supply Characteristics for Si3217x
(VDD = 3.3 V, TA = 0 to 70 ºC)
Parameter
Symbol
Test Condition
Min
—
Typ
9.7
0.0
Max
—
Unit
mA
mA
I
DD
Supply Currents:
Reset
V and V = Hi-Z , RST = 0
T
R
I
I
—
—
VBAT
Supply Currents:
High Impedance, Open
I
V and V = Hi-Z, FXO disabled
—
—
13.2
0.47
—
—
mA
mA
DD
T
R
VBAT
Supply Currents:
I
V
= –48 V, FXO disabled, Auto-
—
11.2
—
mA
DD
TR
Forward/Reverse, On-hook
matic Power Save Mode enabled
I
I
I
—
—
0.44
27.2
—
—
mA
mA
VBAT
Supply Currents:
Forward/Reverse, On-hook
I
V
= –48 V, FXO disabled, Auto-
TR
DD
matic Power Save Mode
disabled
—
—
1.4
—
—
mA
mA
VBAT
Supply Currents:
Tip/Ring Open, On-hook
I
V or V = –48 V,
V or V = Hi-Z,
FXO disabled, Automatic
Power Save Mode enabled
12.5
DD
T
R
R T
—
—
0.4
—
—
mA
mA
VBAT
Supply Currents:
I
V or V = –48 V,
26.3
DD
T
R
Tip/Ring Open, On-hook
V or V = Hi-Z,
R
T
FXO disabled, Automatic
I
—
0.95
—
mA
Power Save Mode disabled
VBAT
Notes:
1. ILOOP is the dc current in the subscriber loop during the off-hook state.
2. IDD = IDDD + IDDA + IDDC
.
3. Refer to AN340 for power supply consumption of the recommended applications circuit, including dc-dc converter.
Rev. 1.4
5
Si3217x/3291x
Table 2. Power Supply Characteristics for Si3217x (Continued)
(VDD = 3.3 V, TA = 0 to 70 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Supply Currents:
Forward/Reverse OHT,
On-hook
I
V
=48 V, FXO disabled
—
40.6
—
mA
DD
TR
I
I
I
—
—
2.3
—
—
mA
mA
VBAT
Supply Currents:
Forward/Reverse Active,
Off-hook
I
I
= 20 mA R = 200 Ω,
LOAD
44.2
DD
LOOP
FXO disabled
—
—
22.0
28
—
—
mA
mA
VBAT
Supply Currents:
Ringing
I
V
=55V
+ 0 VDC, balanced,
RMS
DD
TR
FXO disabled
sinusoidal, f = 20 Hz, R
REN = 1400 Ω
= 5
—
—
—
—
—
38.2
10.0
6.3
—
—
—
—
0
mA
mA
mA
mA
mA
LOAD
VBAT
System Side FXO Supply
Current
I
I
I
I
FXO enabled
DD
DD
DD
DD
System Side FXO Supply
Current
FXO enabled, FXO in Sleep Mode
System Side FXO Supply
Current
FXO enabled, FXO in Full Power
Down Mode
0.1
System Side FXO Supply
Current
FXO disabled
—
Notes:
1. ILOOP is the dc current in the subscriber loop during the off-hook state.
2. IDD = IDDD + IDDA + IDDC
.
3. Refer to AN340 for power supply consumption of the recommended applications circuit, including dc-dc converter.
Table 3. AC Characteristics for FXS
(VDD = 3.13 to 3.47 V, TA = 0 to 70 °C)
Parameter
Test Condition
Min
Typ
Max
Unit
TX/RX Performance
Overload Level
2.5
—
—
—
—
V
PK
Overload Compression
2-Wire – PCM
Figure 15
Notes:
1. The input signal level should be 0 dBm0 for frequencies greater than 100 Hz. For 100 Hz and below, the level should
be –10 dBm0. The output signal magnitude at any other frequency is smaller than the maximum value specified.
2. Analog signal measured as VTIP – VRING. Assumes ideal line impedance matching.
3. The quantization errors inherent in the µ/A-law companding process can generate slightly worse gain tracking
performance in the signal range of 3 to –37 dB for signal frequencies that are integer divisors of the 8 kHz PCM
sampling rate.
4. VDDD, VDDA, VDDHV = 3.3 V, VBAT = –52 V, no fuse resistors; RL = 600 , ZS = 600 synthesized using RS register
coefficients.
5. The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed –55 dBm.
6. 0 dBm 0 is equal to 0 dBm into 600 .
6
Rev. 1.4
Si3217x/3291x
Table 3. AC Characteristics for FXS (Continued)
(VDD = 3.13 to 3.47 V, TA = 0 to 70 °C)
Parameter
Test Condition
Min
Typ
Max
Unit
1
Single Frequency Distortion
2-Wire – PCM or PCM – 2-Wire:
200 Hz to 3.4 kHz
+35
40
—
dB
PCM – 2-Wire – PCM:
200 Hz – 3.4 kHz,
16-bit Linear mode
—
—
—
–63
—
dB
Signal-to-(Noise + Distortion)
200 Hz to 3.4 kHz
D/A or A/D 8-bit
Figure 14
2
Ratio
Active off-hook, and OHT, any Z
T
Audio Tone Generator Signal-to-
Distortion Ratio
0 dBm0, Active off-hook, and
46
—
—
—
—
dB
dB
2
OHT, any Z
T
Intermodulation Distortion
–41
2
Gain Accuracy
2-Wire to PCM or PCM to 2-Wire
1014 Hz, Any gain setting
–0.2
—
0.2
dB
—
6
Attenuation Distortion vs.
Frequency
0 dBm 0
See Figure 16 and 17
Group Delay vs. Frequency
See Figure 18 and 19
3
Gain Tracking
1014 Hz sine wave,
reference level –10 dBm
Signal level:
—
—
—
3 dB to –37 dB
–37 dB to –50 dB
—
—
—
—
26
26
—
—
0.25
0.5
1.0
500
—
dB
dB
dB
µs
–50 dB to –60 dB
—
Round-Trip Group Delay
1014 Hz, Within same time-slot
200 Hz to 3.4 kHz
450
30
30
4
2-Wire Return Loss
dB
dB
4
Transhybrid Balance
300 Hz to 3.4 kHz
—
Notes:
1. The input signal level should be 0 dBm0 for frequencies greater than 100 Hz. For 100 Hz and below, the level should
be –10 dBm0. The output signal magnitude at any other frequency is smaller than the maximum value specified.
2. Analog signal measured as VTIP – VRING. Assumes ideal line impedance matching.
3. The quantization errors inherent in the µ/A-law companding process can generate slightly worse gain tracking
performance in the signal range of 3 to –37 dB for signal frequencies that are integer divisors of the 8 kHz PCM
sampling rate.
4. VDDD, VDDA, VDDHV = 3.3 V, VBAT = –52 V, no fuse resistors; RL = 600 , ZS = 600 synthesized using RS register
coefficients.
5. The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed –55 dBm.
6. 0 dBm 0 is equal to 0 dBm into 600 .
Rev. 1.4
7
Si3217x/3291x
Table 3. AC Characteristics for FXS (Continued)
(VDD = 3.13 to 3.47 V, TA = 0 to 70 °C)
Parameter
Test Condition
Min
Typ
Max
Unit
Noise Performance
C-Message weighted
5
Idle Channel Noise
—
—
—
8
12
–78
—
dBrnC
dBmP
dB
Psophometric weighted
RX and TX, 200 Hz to 3.4 kHz
–82
55
PSRR from V
, V
,
DDA
DDD
V
@ 3.3 V
DDHV
Longitudinal Performance
200 Hz to 1 kHz
Longitudinal to Metallic/PCM
Balance (forward or reverse)
58
53
40
60
58
—
—
—
—
dB
dB
dB
1 kHz to 3.4 kHz
Metallic/PCM to
200 Hz to 3.4 kHz
Longitudinal Balance
Longitudinal Impedance
200 Hz to 3.4 kHz at TIP or RING
—
—
50
25
—
—
Longitudinal Current Capability
Active off-hook 60 Hz
Reg 73 = 0x0B
mA
Notes:
1. The input signal level should be 0 dBm0 for frequencies greater than 100 Hz. For 100 Hz and below, the level should
be –10 dBm0. The output signal magnitude at any other frequency is smaller than the maximum value specified.
2. Analog signal measured as VTIP – VRING. Assumes ideal line impedance matching.
3. The quantization errors inherent in the µ/A-law companding process can generate slightly worse gain tracking
performance in the signal range of 3 to –37 dB for signal frequencies that are integer divisors of the 8 kHz PCM
sampling rate.
4. VDDD, VDDA, VDDHV = 3.3 V, VBAT = –52 V, no fuse resistors; RL = 600 , ZS = 600 synthesized using RS register
coefficients.
5. The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed –55 dBm.
6. 0 dBm 0 is equal to 0 dBm into 600 .
8
Rev. 1.4
Si3217x/3291x
Table 4. Linefeed Characteristics for FXS
(VDD = 3.13 to 3.47 V, TA = 0 to 70 °C)
Symbol
Test Condition
= 430
Min
Typ
Max
Unit
Parameter
Maximum Loop Resistance
R
R
—
—
2000
LOOP
DC,MAX
I
= 18 mA, V
= –52 V,
LOOP
BAT
R
= 0
PROT
DC Feed Current
Differential
Common Mode
Differential + Common Mode
= 18 mA
—
—
—
—
—
—
—
—
—
—
45
30
45
10
4
mA
mA
mA
%
DC Loop Current Accuracy
I
LIM
DC Open Circuit Voltage
Accuracy
Active Mode; V = 48 V,
V
OC
V
– V
TIP
RING
DC Differential Output
Resistance
R
I
< I
160
—
—
—
640
4
DO
LOOP
LIM
DC On-Hook Voltage
Accuracy—Ground Start
V
R
I
<I ; V wrt ground,
RING
V
OHTO
ROTO
RING LIM
V
= –51 V
RING
DC Output
Resistance—Ground Start
I
<I ; RING to ground
160
400
—
—
—
—
—
—
640
—
10
10
4
k
%
RING LIM
DC Output Resistance—
Ground Start
R
TIP to ground
TOTO
Loop Closure Detect
Threshold Accuracy
I
I
= 13 mA
= 13 mA
THR
THR
Ground Key Detect
Threshold Accuracy
—
%
Ring Trip
AC detection,
—
mA
Threshold Accuracy
V
= 70 Vpk, no offset,
RING
I
= 80mA
TH
DC detection,
—
—
—
—
—
—
1
1
mA
mA
20 V dc offset, I = 13 mA
TH
DC Detection,
3
48 V DC offset, R
= 1500
loop
Ringing Amplitude*
V
Si32171/6/8 Open circuit,
= –110 V
108
132
—
—
—
—
V
V
RINGING
PK
PK
V
BAT
Si32170/7/9 Open circuit,
= –136 V
V
BAT
Sinusoidal Ringing Total
Harmonic Distortion
R
Si32171/6/8 : 60 V
,
%
THD
RMS
15 V
, 0–5 REN
OFFSET
Si32170/7/9 : 55 V
,
RMS
48 V
, 0–5 REN
OFFSET
Ringing Frequency Accuracy
Ringing Cadence Accuracy
f = 16 Hz to 60 Hz
Accuracy of ON/OFF times
– V = 48 V
—
—
—
—
—
2
1
50
4
%
ms
%
Loop Voltage Sense
Accuracy
V
TIP
RING
Rev. 1.4
9
Si3217x/3291x
Table 4. Linefeed Characteristics for FXS (Continued)
(VDD = 3.13 to 3.47 V, TA = 0 to 70 °C)
Symbol
Test Condition
= 18 mA
Min
Typ
Max
Unit
Parameter
Loop Current
I
—
7
10
%
LOOP
Sense Accuracy
Power Alarm
Threshold Accuracy
Power Threshold = 1.0 W
= –56 V, I = 40 mA,
—
15
—
%
V
BAT
LDDD
R
= 600
LOAD
Test Load Impedance
Test Load Voltage
R
HVIC_STATE_SPARE[23] = 1;
3.6
±5
5.3
7.7
k
TEST
V 50 V
T/R
V
HVIC_STATE_SPARE[23] = 1
±50
V
TL
*Note: Ringing amplitude is set for 108 or 128 V peak and measured at TIP-RING using no series protection resistance.
Table 5. Monitor ADC Characteristics for FXS
(VDD = 3.13 to 3.47 V, TA = 0 to 70 °C)
Symbol
Test Condition
Min
Typ
Max
Unit
Parameter
Differential Nonlinearity
DNLE
INLE
—
—
1
1
—
—
LSB
LSB
Integral Nonlinearity
(8-bit resolution)
Gain Error
—
5
—
%
Table 6. Loop Characteristics for FXO
(VD = 3.0 to 3.6 V, TA = 0 to 70 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
DC Termination Voltage
V
V
V
V
V
V
V
I = 20 mA, ILIM = 0
DCV = 00, MINI = 11, DCR = 0
—
—
—
—
—
—
—
—
6.0
V
TR
TR
TR
TR
TR
TR
TR
L
DC Termination Voltage
DC Termination Voltage
DC Termination Voltage
DC Termination Voltage
DC Termination Voltage
DC Termination Voltage
I = 120 mA, ILIM = 0
9
—
7.5
—
V
V
V
V
V
V
L
DCV = 00, MINI = 11, DCR = 0
I = 20 mA, ILIM = 0
—
9
L
DCV = 11, MINI = 00, DCR = 0
I = 120 mA, ILIM = 0
L
DCV = 11, MINI = 00, DCR = 0
I = 20 mA, ILIM = 1
—
40
—
7.5
—
L
DCV = 11, MINI = 00, DCR = 0
I = 60 mA, ILIM = 1
L
DCV = 11, MINI = 00, DCR = 0
I = 50 mA, ILIM = 1
40
L
DCV = 11, MINI = 00, DCR = 0
On-Hook Leakage Current
Operating Loop Current
Operating Loop Current
I
I
I
V
= –48 V
TR
—
10
10
—
—
—
5
µA
mA
mA
LK
LP
LP
MINI = 00, ILIM = 0
MINI = 00, ILIM = 1
120
60
*Note: The ring signal will not be detected below the minimum. The ring signal will be detected above the maximum.
10
Rev. 1.4
Si3217x/3291x
Table 6. Loop Characteristics for FXO (Continued)
(VD = 3.0 to 3.6 V, TA = 0 to 70 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
DC Ring Current
dc current flowing through ring
detection circuitry
—
1.5
3
µA
*
*
*
Ring Detect Voltage
Ring Detect Voltage
Ring Detect Voltage
Ring Frequency
V
V
V
RT2 = 0, RT = 0
RT2 = 0, RT = 1
RT2 = 1, RT = 1
13.5
19.35
40.5
13
15
21.5
45
16.5
23.65
49.5
68
V
V
V
RD
RD
RD
rms
rms
rms
F
—
Hz
R
Ringer Equivalence Number
REN
—
—
0.2
*Note: The ring signal will not be detected below the minimum. The ring signal will be detected above the maximum.
Table 7. AC Characteristics for FXO
(VD = 3.0 to 3.6 V, TA = 0 to 70 °C, Fs = 8000 Hz)
Parameter
Symbol
Test Condition
Min
—
—
—
—
—
—
—
—
—
Typ
5
Max
—
—
—
—
—
—
—
—
—
Unit
Hz
Receive Frequency Response
Receive Frequency Response
Low –3 dBFS Corner, FILT = 0
Low –3 dBFS Corner, FILT = 1
FULL = 0 (0 dBm)
200
1.1
Hz
1
Transmit Full-Scale Level
V
V
V
FS
FS
PEAK
PEAK
PEAK
PEAK
PEAK
Note 2
FULL = 1 (+3.2 dBm)
1.58
2.16
1.1
V
V
V
V
V
Note 2
FULL2 = 1 (+6.0 dBm)
1,3
Receive Full-Scale Level
FULL = 0 (0 dBm)
Note 2
FULL = 1 (+3.2 dBm)
1.58
2.16
80
Note 2
FULL2 = 1 (+6.0 dBm)
PEAK
4,5,6
Dynamic Range
DR
DR
DR
ILIM = 0, DCV = 11, MINI=00
dB
DCR = 0, I = 100 mA
L
4,5,6
Dynamic Range
ILIM = 0, DCV = 00, MINI=11
—
—
80
80
—
—
dB
dB
DCR = 0, I = 20 mA
L
4,5,6
Dynamic Range
ILIM = 1, DCV = 11, MINI=00
DCR = 0, I = 50 mA
L
Notes:
1. Measured at TIP and RING with 600 termination at 1 kHz, as shown in Figure 1 on page 13.
2. With FULL = 1, the transmit and receive full-scale level of +3.2 dBm can be achieved with a 600 ac termination. While
the transmit and receive level in dBm varies with reference impedance, the DAA will transmit and receive 1 dBV into all
reference impedances. With FULL2 = 1, the transmit and receive full-scale level of +6.0 dBm can be achieved with a
600 termination. In this mode, the DAA will transmit and receive +1.5 dBV into all reference impedances.
3. Receive full-scale level produces –0.9 dBFS at DTX.
4. DR = 20 x log (RMS VFS/RMS Vin) + 20 x log (RMS Vin/RMS noise). The RMS noise measurement excludes harmonics.
Here, VFS is the 0 dBm full-scale level per Note 1 above.
5. Measurement is 300 to 3400 Hz. Applies to both transmit and receive paths.
6. Vin = 1 kHz, –3 dBFS.
7. THD = 20 x log (RMS distortion/RMS signal).
8. DRCID = 20 x log (RMS VCID/RMS VIN) + 20 x log (RMS VIN/RMS noise). VCID is the 1.5 V full-scale level with the
enhanced caller ID circuit. With the typical CID circuit, the VCID full-scale level is 6 V peak, and the DRCID decreases to
50 dB.
9. Refer to Tables 8–9 for relative gain accuracy characteristics (passband ripple).
10. Analog hybrid only. ZACIM controlled by ACIM in Register 30.
Rev. 1.4
11
Si3217x/3291x
Table 7. AC Characteristics for FXO (Continued)
(VD = 3.0 to 3.6 V, TA = 0 to 70 °C, Fs = 8000 Hz)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Transmit Total Harmonic Distor-
tion
THD
ILIM = 0, DCV = 11, MINI=00
—
–72
—
dB
6,7
DCR = 0, I = 100 mA
L
Transmit Total Harmonic Distor-
tion
THD
THD
THD
ILIM = 0, DCV = 00, MINI=11
—
—
—
–78
–78
–78
—
—
—
dB
dB
dB
dB
6,7
DCR = 0, I = 20 mA
L
Receive Total Harmonic Distor-
ILIM = 0, DCV = 00, MINI=11
6,7
tion
DCR = 0, I = 20 mA
L
Receive Total Harmonic Distor-
ILIM = 1,DCV = 11, MINI=00
6,7
tion
DCR = 0, I = 50 mA
L
8
Dynamic Range (Caller ID mode)
DR
VIN = 1 kHz, –13 dBFS
—
—
62
1.5
0
—
—
CID
8
Caller ID Full-Scale Level
V
V
PEAK
CID
6,9
Gain Accuracy
2-W to DTX,
–0.5
0.5
dB
TXG2, RXG2, TXG3,
and RXG3 = 0000
10
Transhybrid Balance
300–3.4 kHz, ZACIM = ZLINE
1 kHz, ZACIM = ZLINE
20
—
25
—
30
—
—
—
—
dB
dB
dB
10
Transhybrid Balance
Two-Wire Return Loss
300–3.4 kHz, all ac
terminations
Two-Wire Return Loss
1 kHz, all ac terminations
—
32
—
dB
Notes:
1. Measured at TIP and RING with 600 termination at 1 kHz, as shown in Figure 1 on page 13.
2. With FULL = 1, the transmit and receive full-scale level of +3.2 dBm can be achieved with a 600 ac termination. While
the transmit and receive level in dBm varies with reference impedance, the DAA will transmit and receive 1 dBV into all
reference impedances. With FULL2 = 1, the transmit and receive full-scale level of +6.0 dBm can be achieved with a
600 termination. In this mode, the DAA will transmit and receive +1.5 dBV into all reference impedances.
3. Receive full-scale level produces –0.9 dBFS at DTX.
4. DR = 20 x log (RMS VFS/RMS Vin) + 20 x log (RMS Vin/RMS noise). The RMS noise measurement excludes harmonics.
Here, VFS is the 0 dBm full-scale level per Note 1 above.
5. Measurement is 300 to 3400 Hz. Applies to both transmit and receive paths.
6. Vin = 1 kHz, –3 dBFS.
7. THD = 20 x log (RMS distortion/RMS signal).
8. DRCID = 20 x log (RMS VCID/RMS VIN) + 20 x log (RMS VIN/RMS noise). VCID is the 1.5 V full-scale level with the
enhanced caller ID circuit. With the typical CID circuit, the VCID full-scale level is 6 V peak, and the DRCID decreases to
50 dB.
9. Refer to Tables 8–9 for relative gain accuracy characteristics (passband ripple).
10. Analog hybrid only. ZACIM controlled by ACIM in Register 30.
12
Rev. 1.4
Si3217x/3291x
TIP
+
600
10F
IL
Si3291x
VTR
–
RING
Figure 1. Test Circuit for Loop Characteristics
Table 8. Digital FIR Filter Characteristics for FXO—Transmit and Receive
(VD = 3.0 to 3.6 V, Sample Rate = 8 kHz, TA = 0 to 70 °C)
Parameter
Symbol
Min
0
Typ
—
Max
3.3
3.6
0.1
—
Unit
kHz
kHz
dB
Passband (0.1 dB)
Passband (3 dB)
Passband Ripple Peak-to-Peak
Stopband
F
(0.1 dB)
F
0
—
(3 dB)
–0.1
—
—
4.4
—
kHz
dB
Stopband Attenuation
Group Delay
–74
—
—
t
12/Fs
—
s
gd
Note: Typical FIR filter characteristics for Fs = 8000 Hz are shown in Figures 2, 3, 4, and 5.
Table 9. Digital IIR Filter Characteristics for FXO—Transmit and Receive
(VD = 3.0 to 3.6 V, Sample Rate = 8 kHz, TA = 0 to 70 °C)
Parameter
Symbol
Min
0
Typ
—
Max
3.6
0.2
—
Unit
kHz
dB
Passband (3 dB)
Passband Ripple Peak-to-Peak
Stopband
F
(3 dB)
–0.2
—
—
4.4
kHz
dB
Stopband Attenuation
Group Delay
–40
—
—
—
t
1.6/Fs
—
s
gd
Note: Typical IIR filter characteristics for Fs = 8000 Hz are shown in Figures 6, 7, 8, and 9. Figures 10 and 11 show group
delay versus input frequency.
Rev. 1.4
13
Si3217x/3291x
Figure 2. FIR Receive Filter Response
Figure 4. FIR Transmit Filter Response
Figure 3. FIR Receive Filter Passband Ripple
Figure 5. FIR Transmit Filter Passband Ripple
For Figures 1–5, all filter plots apply to a sample rate of
Fs = 8 kHz.
For Figures 6–9, all filter plots apply to a sample rate of
Fs = 8 kHz.
14
Rev. 1.4
Si3217x/3291x
Figure 6. IIR Receive Filter Response
Figure 7. IIR Receive Filter Passband Ripple
Figure 8. IIR Transmit Filter Response
Figure 9. IIR Transmit Filter Passband Ripple
Figure 10. IIR Receive Group Delay
Figure 11. IIR Transmit Group Delay
Rev. 1.4
15
Si3217x/3291x
Table 10. Digital I/O Characteristics
(VDD = 3.13 to 3.47 V, TA = 0 to 70 °C)
Parameter
Symbol
Test Condition
Min
0.7 x V
—
Typ
—
Max
Unit
V
High Level Input Voltage
Low Level Input Voltage
V
V
DD
IH
DD
V
—
0.3 x V
—
V
IL
DD
High Level Output
Voltage*
V
DTX, SDO, SDITHRU,
GPIO1/STIPC, GPIO2/SRINGC:
V
– 0.6
DD
—
V
OH
I = –4 mA
O
C1A, C2A:
I = –2 mA
O
Low Level Output
Voltage*
V
DTX, SDO, INT,
SDITHRU,
—
—
0.4
V
OL
GPIO1/STIPC, GPIO2/SRINGC:
I = 4 mA
O
C1A, C2A:
I = 2 mA
O
SDITHRU and RST
33
—
42
—
65
10
µA
µA
Internal Pullup Current
Input Leakage Current
I
L
*Note: VIH/VIL, VOH/VOL do not apply to C1A/C2A.
Table 11. Switching Characteristics—General Inputs1
(VDD = 3.13 to 3.47 V, TA = 0 to 70 °C, CL = 20 pF)
Parameter
Symbol
Min
Typ
—
Max
Unit
Rise Time, RST
t
—
5
ns
µs
r
3
RST Pulse Width, SPI Daisy Chain Mode
t
33/PCLK
—
—
rl
Notes:
1. All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are
VIH = VDD – 0.4 V, VIL = 0.4 V. Rise and Fall times are referenced to the 20% and 80% levels of the waveform.
2. The minimum RST pulse width assumes the SDITHRU pin is tied to ground via a pulldown resistor no greater than
10 k per device.
3. The minimum RST pulse width is 33/PCLK frequency (i.e. 33/8.192 MHz = 4 µs).
16
Rev. 1.4
Si3217x/3291x
Table 12. Switching Characteristics—SPI
(VDDA = 3.13 to 3.47 V, TA = 0 to 70 °C, CL = 20 pF)
Parameter
Symbol
Test Conditions
Min
62
—
Typ
—
Max
—
Unit
ns
Cycle Time SCLK
t
c
Rise Time, SCLK
t
—
25
ns
r
Fall Time, SCLK
t
—
—
25
ns
f
Delay Time, SCLK Fall to SDO Active
t
—
—
20
ns
d1
d2
Delay Time, SCLK Fall to SDO
Transition
t
t
—
—
20
ns
Delay Time, CS Rise to SDO Tri-state
Setup Time, CS to SCLK Fall
—
25
20
25
20
220
—
—
—
—
—
—
—
4
20
—
—
—
—
—
10
ns
ns
ns
ns
ns
ns
ns
d3
t
su1
Hold Time, CS to SCLK Rise
t
h1
Setup Time, SDI to SCLK Rise
Hold Time, SDI to SCLK Rise
Delay Time between Chip Selects
SDI to SDITHRU Propagation Delay
t
su2
t
h2
t
cs
t
d4
Note: All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VDDD –0.4 V, VIL = 0.4 V
tc
tr
tf
SCLK
CS
tsu1
th1
tcs
tsu2
th2
SDI
td1
td3
td2
SDO
td4
SDITHRU
Figure 12. SPI Timing Diagram
Rev. 1.4
17
Si3217x/3291x
Table 13. Switching Characteristics—PCM Highway Interface
(VDD = 3.13 to 3.47 V, TA = 0 to 70 °C, CL = 20 pF)
1
1
1
Parameter
Symbol
Test
Conditions
Units
Min
Typ
Max
PCLK Period (–40 to +85 °C)
PCLK Period (0 to +70 °C)
PCLK Jitter Tolerance for FXS
PCLK Jitter Tolerance for FXO
t
122
122
—
—
—
—
—
1953
3906
8
ns
ns
p(industrial)
t
p(commercial)
t
ns
RMS
jitter(FXS)
t
—
2
ns
jitter(FXO)
2
Valid PCLK Inputs
—
—
—
—
—
—
—
—
512
768
—
—
—
—
—
—
—
—
kHz
kHz
1.024
1.536
1.544
2.048
4.096
8.192
MHz
MHz
MHz
MHz
MHz
MHz
3
FSYNC Period
t
—
40
—
—
—
—
—
125
50
—
—
60
µs
%
fs
PCLK Duty Cycle Tolerance
t
dty
4
FSYNC Jitter Tolerance
t
±120
25
ns
ns
ns
ns
ns
jitter
Rise Time, PCLK
t
—
r
Fall Time, PCLK
t
—
25
f
Delay Time, PCLK Rise to DTX Active
t
t
—
20
d1
d2
Delay Time, PCLK Rise to DTX
Transition
—
20
Delay Time, PCLK Rise to DTX Tri-
state
t
—
—
20
ns
d3
6
Setup Time, FSYNC to PCLK Fall
Hold Time, FSYNC to PCLK Fall
Setup Time, DRX to PCLK Fall
Hold Time, DRX to PCLK Fall
FSYNC Pulse Width
t
25
20
25
20
—
—
—
—
—
—
—
ns
ns
ns
ns
su1
t
h1
t
—
su2
t
—
h2
t
t
125 µs–t
p
wfs
p
Notes:
1. All timing is referenced to the 50% level of the waveform. Input test levels are VIH – VI/O – 0.4 V, VIL = 0.4 V.
2. A constant PCLK and FSYNC are required.
3. FSYNC source is assumed to be 8 kHz under all operating conditions.
4. FSYNC Jitter Tolerance relative to PCLK.
5. 256 kHz PCLK is only valid for 0 to 70 °C operation.
6. Specification applies to PCLK fall to DTX tristate when that mode is selected.
18
Rev. 1.4
Si3217x/3291x
Table 14. Absolute Maximum Ratings and Thermal Information1
Symbol
Test Condition
Value
Unit
Parameter
Storage Temperature Range
T
–55 to 150
°C
STG
2
Thermal Resistance, Typical
QFN-42 (LGA & NBA)
53
33
°C/W
JA
JB
JC
39
3,4
Continuous Power Dissipation
QFN-42 (LGA & NBA)
P
T = 85 °C
0.75
W
°C
D
A
Maximum Junction Temperature,
QFN-42 (Linefeed Die)
T
Continuous
145
125
85
JHV
Maximum Junction Temperature
QFN-42 (Low Voltage Die)
T
°C
JLV
2
Thermal Resistance, Typical
°C/W
W
JA
SOIC-16
3
Continuous Power Dissipation
SOIC-16
P
T = 85 °C
0.47
125
D
A
Maximum Junction Temperature
SOIC-16
T
°C
J
Si3217x
Supply Voltage
V
V
–0.5 to 4.0
V
DDD, DDA,
V
DDHV
Digital Input Voltage
V
–0.3 to 3.6
+0.4 to –115
+0.4 to –140
–130
V
V
IND
BAT
BAT
5
Battery Supply Voltage , Si32171/6/8
V
5
Battery Supply Voltage , Si32170/7/9
V
V
6
Tip or Ring Voltage, Si32171/6/8
V
, V
V
TIP RING
6
Tip or Ring Voltage, Si32170/7/9
V
I
, V
–140
V
TIP RING
TIP, RING Current
, I
±100
mA
TIP RING
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operational sections of this data sheet.
2. The thermal resistance of an exposed pad package is assured when the recommended printed circuit board layout
guidelines are followed correctly. The specified performance requires that the exposed pad be soldered to an exposed
copper surface of at least equal size and that multiple vias are added to enable heat transfer between the top-side
copper surface and a large internal/bottom copper plane.
3. Operation of the Si3217x or Si3291x above 125 °C junction temperature may degrade device reliability.
4. Si3217x linefeed is equipped with on-chip thermal limiting circuitry that shuts down the circuit when the junction
temperature exceeds the thermal shutdown threshold. The thermal shutdown threshold should normally be set to 145
°C; when in the ringing state with cadence the thermal shutdown may be set to 200 °C. For optimal reliability long term
operation of the Si3217x linefeed above 150 °C junction temperature should be avoided.
5. The dv/dt of the voltage applied to the VBAT pins must be limited to 10 V/µs.
6. Specification requires circuit for surge event as shown in typical application circuit.
Rev. 1.4
19
Si3217x/3291x
tr
tf
tp
PCLK
th1
twfs
tsu1
tfs
FSYNC
tsu2
th2
DRX
td2
td1
td3
DTX
Figure 13. PCM Highway Interface Timing Diagram
Acceptable Region
Figure 14. Transmit and Receive Path SNDR
20
Rev. 1.4
Si3217x/3291x
9
8
7
6
5
4
Fundamental
Output Power
(dBm0)
Acceptable
Region
3
2.6
2
1
0
1
2
3
4
5
6
7
8
9
Fundamental Input Power (dBm0)
Figure 15. Overload Compression Performance
Rev. 1.4
21
Si3217x/3291x
RX Attenuation Distortion
5
0
−5
−10
−15
−20
−25
−30
−35
−40
−45
0
250 500 750 1000 1250 1500 1750 2000 2250 2500 2750 3000 3250 3500 3750 4000 4250 4500 4750 5000
Frequency (Hz)
RX Pass−Band Detail
0.4
0.2
0
−0.2
−0.4
−0.6
−0.8
−1
−1.2
0
250 500 750 1000 1250 1500 1750 2000 2250 2500 2750 3000 3250 3500 3750 4000 4250 4500 4750 5000
Frequency (Hz)
Figure 16. Receive Path Frequency Response
22
Rev. 1.4
Si3217x/3291x
TX Attenuation Distortion
5
0
−5
−10
−15
−20
−25
−30
−35
−40
−45
0
250 500 750 1000 1250 1500 1750 2000 2250 2500 2750 3000 3250 3500 3750 4000 4250 4500 4750 5000
Frequency (Hz)
TX Pass−Band Detail
0.4
0.2
0
−0.2
−0.4
−0.6
−0.8
−1
−1.2
0
250 500 750 1000 1250 1500 1750 2000 2250 2500 2750 3000 3250 3500 3750 4000 4250 4500 4750 5000
Frequency (Hz)
Figure 17. Transmit Path Frequency Response
Rev. 1.4
23
Si3217x/3291x
TX Group Delay Distortion
1100
1000
900
800
700
600
500
400
300
200
100
0
200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400 2600 2800 3000 3200 3400
Frequency (Hz)
Figure 18. Transmit Group Delay Distortion
RX Group Delay Distortion
1100
1000
900
800
700
600
500
400
300
200
100
0
Typical Response
200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400 2600 2800 3000 3200 3400
Frequency (Hz)
Figure 19. Receive Group Delay Distortion
24
Rev. 1.4
Si3217x/3291x
2. Schematics
V B A T
D N E G
C
V D
D
G N
D V D H V
V D D H V
1
V B A T
3 6
G
D V D R E
B I W A H S
B I W A H S
HW
4 2
2
1 9
E P A D
E P A D
D V D A
D V D D
N D G D
V D D A
V D D D
2 8
1 8
1
D
G N
Rev. 1.4
25
Si3217x/3291x
- 7 - F
D 3 0 0 M 4 S M B
- 7 - F
D 3 0 0 M 4 S M B
26
Rev. 1.4
Si3217x/3291x
Q122
Q121
Rev. 1.4
27
Si3217x/3291x
R 1 2 8
R 1 2 7
R 1 2 6
R 1 2 0
28
Rev. 1.4
Si3217x/3291x
F
R E - V
A
A
2
7
6
t
t
Rev. 1.4
29
Si3217x/3291x
3. Bill of Materials
Table 15. Si3217x/Si3291x Bill of Materials (Excluding DC-DC)
Reference
Description
Mfr Part Number
Mfr
C1
CAP, 10uF, 6.3V, ±20%, X5R, 0603
C0603X5R6R3-106M
Venkel
(Not Installed)
D1
DIO, SINGLE, 250V, 200mA, SOT323
RES, 590K, 1/10W, ±1%, ThickFilm, 0805
CAP, 0.1uF, 10V, ±10%, X7R, 0402
BAS21HT1
On Semi
Venkel
Venkel
(Not Installed)
R105
(Not Installed)
CR0805-10W-5903F
C0402X7R100-104K
C2 C4 C7 C100
C107
C6
C8
CAP, 10uF, 6.3V, ±20%, X5R, 0603
CAP, 4.7nF, 16V, ±10%, X7R, 0402
CAP, 0.01uF, 200V, ±10%, X7R, 0805
C0603X5R6R3-106M
C0402X7R160-472K
C0805X7R201-103K
Venkel
Venkel
Venkel
C101 C102
C103 C104
C105
J1
CAP, 0.1uF, 200V, ±20%, X7R, 1206
1 Port SMT RJ11
C1206X7R201-104M
5555077-2
Venkel
AMP
R1
RES, 15 Ohm, 1/10W, ±1%, ThickFilm, 0805
RES, 49.9K, 1/16W, ±0.5%, ThickFilm, 0603
RES, 137K, 1/16W, ±1%, ThickFilm, 0402
RES, 10K, 1/16W, ±5%, ThickFilm, 0402
RES, 681K, 1/10W, ±1%, ThickFilm, 0805
RES, 1K, 1/10W, ±1%, ThickFilm, 0603
RES, 1.47M, 1/8W, ±1%, ThickFilm, 1206
RES, 110K, 1/16W, ±1%, ThickFilm, 0402
RES, 0 Ohm, 2A, ThickFilm, 0805
CR0805-10W-15R0F
CR0603-16W-4992D
CR0402-16W-1373F
CR0402-16W-103J
CR0805-10W-6813F
CR0603-10W-1001F
CR1206-8W-1474F
CR0402-16W-1103F
CR0805-10W-000
Si32178/9-B-FM1
C0805X7R201-103K
C1206X7R201-104M
MF-SM013/250-2
Venkel
Venkel
Venkel
Venkel
Venkel
Venkel
Venkel
Venkel
Venkel
SiLabs
Venkel
Venkel
Bourns
R2
R17
R19
R101 R102
R103 R104
R106 R107
R108 R109
R110
U1
Single SLIC Integrated HV Interface, wideband, DAA
CAP, 0.01uF, 200V, ±10%, X7R, 0805
CAP, 0.1uF, 200V, ±20%, X7R, 1206
C108
C150
RT150 RT151
PTC, Telecom PTC Resettable Fuses, SMT
R150 R151
U151
RES, 15 Ohm, 1/10W, ±1%, ThickFilm, 0805
SLIC Protector
CR0805-10W-15R0F
TISP61089BDR
Venkel
Bourns
Venkel
C230 C231
CAP, 120pF, 250V, ±10%, X7R, 0805
C0805X7R251-121K
(Not Installed)
C232
(Not Installed)
CAP, 68pF, 250VRMS, ±10%, Y2, 1808
RES, 15M, 1/8W, ±5%, ThickFilm, 0805
GA342D1XGF680JY02L
CR0805-8W-156J
MuRata
Venkel
R230 R232
(Not Installed)
30
Rev. 1.4
Si3217x/3291x
Table 15. Si3217x/Si3291x Bill of Materials (Excluding DC-DC) (Continued)
Reference
Description
Mfr Part Number
Mfr
R231 R233
RES, 5.1M, 1/8W, ±5%, ThickFilm, 0805
CR0805-8W-515J
Venkel
(Not Installed)
R236 R237
RES, 20M, 1/8W, ±5%, ThickFilm, 0805
CR0805-8W-206J
Venkel
(Not Installed)
C201 C202
C203
CAP, 33pF, 250VRMS, ±5%, Y2, 1808
CAP, 3900pF, 250V, ±20%, X7R, 0805
CAP, 1uF, 100V, ±10%, X7R, 1210
CAP, 0.1uF, 10V, ±10%, X7R, 0402
CAP, 2.7nF, 50V, ±20%, X7R, 0603
CAP, 680pF, 250VRMS, ±10%, Y2, 1808
CAP, 0.01uF, 10V, ±20%, X7R, 0402
DIO, DUAL Series, 300V, 225mA, SOT23
FERRITE BEAD, 600 @100MHZ
GA342D1XGF330JY02L
C0805X7R251-392M
C1210X7R101-105K
C0402X7R100-104K
C0603X7R500-272M
SCC1808X681K502T
C0402X7R100-103M
MMBD3004S-7-F
MuRata
Venkel
C204
Venkel
C205 C206
C207
Venkel
Venkel
C208 C209
C210
Holy Stone
Venkel
D201 D202
Diodes Inc.
MuRata
FB201 FB202
FB203 FB204
BLM18AG601SN1
J2
Q201 Q203
Q202
1 Port SMT RJ11
5555077-2
AMP
On Semi
On Semi
On Semi
Littelfuse
Venkel
Venkel
Venkel
Venkel
Venkel
Venkel
Venkel
Venkel
Venkel
Venkel
SiLabs
TRANSISTOR, NPN, High Voltage, SOT23
TRANSISTOR, PNP, High Voltage, SOT23
TRANSISTOR, NPN, DRIVER, SOT23
SIDACTOR BI 275V 250A DO-214AA
RES, 1.07K, 1/2W, ±1%, ThickFilm, 2010
RES, 150 Ohm, 1/16W, ±1%, ThickFilm, 0402
RES, 3.65K, 1/2W, ±1%, ThickFilm, 2010
RES, 2.49K, 1/2W, ±1%, ThickFilm, 2010
RES, 100K, 1/16W, ±5%, ThickFilm, 0402
RES, 20M, 1/8W, ±5%, ThickFilm, 0805
RES, 1M, 1/16W, ±1%, ThickFilm, 0402
RES, 536 Ohm, 1/4W, ±1%, ThickFilm, 1206
RES, 73.2 Ohm, 1/2W, ±1%, ThickFilm, 2010
RES, 56.2 Ohm, 1/16W, ±1%, ThickFilm, 0402
MMBTA42LT1
MMBTA92LT1
Q204 Q205
RV201
R201
MMBTA06LT1
P3100SBL
CR2010-2W-1071F
CR0402-16W-1500F
CR2010-2W-3651F
CR2010-2W-2491F
CR0402-16W-104J
CR0805-8W-206J
CR0402-16W-1004F
CR1206-4W-5360F
CR2010-2W-73R2F
CR0402-16W-56R2F
Si32919-A-FS
R202
R203
R204
R205 R206
R207 R208
R209
R210
R211
R212 R213
U202
IC, Global DAA Line Side w/Voice features attaches to
the Si3217x SLIC
Z201
DIO, ZENER, 43V, 500 mW, SOD123
BZT52C43-7-F
Diodes Inc.
Rev. 1.4
31
Si3217x/3291x
Table 16. Si3217x Flyback DC-DC Bill of Materials
Reference
Description
Mfr Part Number
Mfr
C124 C125
CAP, 0.1uF, 200V, ±20%, X7R, 1206
C1206X7R201-104M
Venkel
(Not Installed)
C128
(Not Installed)
CAP, 470pF, 50V, ±20%, X7R, 0402
CAP, 68pF, 200V, ±5%, COG, 0805
C0402X7R500-471M
C0805C0G201-680J
C0603X7R101-471K
BAS16XV2T1G
Venkel
Venkel
Venkel
On Semi
Vishay
Venkel
Venkel
C133
(Not Installed)
C134
(Not Installed
CAP, 470pF, 100V, ±10%, X7R, 0603
DIO, SWITCH, 200mA, 75V, SOD523
DIO, ZENER, 75V, 200 mW, SOD323
RES, 150 Ohm, 1/4W, ±1%, ThickFilm, 1206
RES, 15 Ohm, 1/4W, ±5%, ThickFilm, 1206
D125
(Not Installed)
D126
(Not Installed)
BZX384C75-V
R130
(Not Installed)
CR1206-4W-1500F
CR1206-4W-150J
R139
(Not Installed)
C121 C126
C122 C123
C127
CAP, 0.1uF, 25V, ±20%, X7R, 0603
CAP, 0.1uF, 200V, ±20%, X7R, 1206
CAP, 470pF, 50V, ±20%, X7R, 0402
C0603X7R250-104M
C1206X7R201-104M
C0402X7R500-471M
EEUFC1J680
Venkel
Venkel
Venkel
C130
CAP, 68uF, 63V, ±20%, AL, 8X11.5MM,
Low Impedance
Panasonic
D120
Q120
DIO, FAST, 300V, 1A, SMA
ES1F
Fairchild
Zetex
TRANSISTOR, MOSFET, N-CHNL,
2.0W Switching, SOT223
ZXMN10A11G
Q121
Q122
TRANSISTOR, PNP, SOT23
MMBT3906-7-F
BSS138
Diodes Inc.
Zetex
TRANSISTOR, MOSFET, N-CHNL,
360mW Small signal, SOT23
Q123
R100
TRANSISTOR, NPN, GP, SOT23
RES, 1.65M, 1/10W, ±1%, ThickFilm, 0805
RES, 0.1 Ohm, 1/2W, ±1%, ThickFilm, 1210
RES, 15 Ohm, 1/4W, ±5%, ThickFilm, 1206
RES, 220 Ohm, 1/16W, ±5%, ThickFilm, 0402
RES, 0 Ohm, 1A, ThickFilm, 0402
MMBT3904
Fairchild
Venkel
Venkel
Venkel
Venkel
Venkel
Venkel
Venkel
Venkel
CR0805-10W-1654F
LCR1210-R100F
CR1206-4W-150J
CR0402-16W-221J
CR0402-16W-000
CR0805-10W-6813F
CR0402-16W-683J
CR0402-16W-000
R121
R122
R123
R124 R140
R125
RES, 681K, 1/10W, ±1%, ThickFilm, 0805
RES, 68K, 1/16W, ±5%, ThickFilm, 0402
RES, 0 Ohm, 1A, ThickFilm, 0402
R126
R141 R142
T120
TRANSFORMER, Flyback, 8.0uH Primary, 100nH
Leakage, 1:3, 1 Tap, SMT
UTB01890s
UTB01701s
UMEC
UMEC
XF0086-EP7S
XFMRS Inc
32
Rev. 1.4
Si3217x/3291x
Table 17. Si3217x Buck Boost DC-DC Bill of Materials
Reference
C122
Description
Mfr Part Number
C0603X7R101-104M
ECA2AM100
Manufacturer
Venkel
CAP, 0.1uF, 100V, ±20%, X7R, 0603
CAP, 10uF, 100V, ±20%, AL, 5X11MM
CAP, 0.1uF, 25V, ±20%, X7R, 0603
CAP, 0.01uF, 10V, ±20%, X7R, 0402
DIO, FAST, 200V, 1A SMA
C120 C123
C121 C125
C126
Panasonic
Venkel
C0603X7R250-104M
C0402X7R100-103M
ES1D
Venkel
D120
Diodes Inc.
Diodes Inc.
Cooper Bussman
Zetex
D121
DIO, SWITCH, 75V, 300mA, SOT23
Power Inductor, Shielded
BAS16-7-F
L120
DR127-101-R
Q120
TRANSISTOR, PNP, 140V,
ZXTP2014G
MEDIUM POWER LOW SAT, SOT223
Q121
R100
TRANSISTOR, NPN, SOT23
MMBT2222LT1
CR0805-10W-1654F
CR0402-16W-1R00F
On Semi
Venkel
Venkel
RES, 1.65M, 1/10W, ±1%, ThickFilm, 0805
RES, 1.0 Ohm, 1/16W, ±1%, ThickFilm, 0402
R120 R126
R127 R128
R122
R124
RES, 15 Ohm, 1/10W, ±1%, ThickFilm, 0805
RES, 120 Ohm, 1/10W, ±1%, ThickFilm, 0603
RES, 200 Ohm, 1/10W, ±1%, ThickFilm, 0603
RES, 47K, 1/16W, ±1%, ThickFilm, 0402
CR0805-10W-15R0F
CR0603-10W-1200F
CR0603-10W-2000F
CR0402-16W-4702F
Venkel
Venkel
Venkel
Venkel
R125
R129 R130
Rev. 1.4
33
Si3217x/3291x
4. Overview
5. FXS Features
The Si3217x series provides all SLIC, codec, DTMF
detection, and signal generation functions needed for
one complete analog telephone interface. The Si3217x
performs all battery, over-voltage, ringing, supervision,
codec, hybrid, and test (BORSCHT) functions; it also
supports extensive metallic loop testing capabilities.
5.1. DC Feed Characteristics
ProSLIC internal linefeed circuitry provides completely
programmable dc feed characteristics.
When in the active state, the ProSLIC operates in one of
three dc linefeed operating regions: a constant-voltage
region, a constant-current region, or a resistive region,
as shown in Figure 25. The constant-voltage region has
a low resistance, typically 160 . The constant-current
region approximates infinite resistance.
The Si3217x provides a standard voice-band (200 Hz–
3.4 kHz) audio codec and, optionally, an audio codec
with both wideband (50 Hz–7 kHz) and standard voice-
band modes. The wideband mode provides an
expanded audio band with a 16 kHz sample rate for
enhanced audio quality while the standard voice-band
mode provides standard telephony audio bandwidth.
The Si3217x incorporates a programmable dc-dc
converter controller that reacts to line conditions to
provide the optimal battery voltage required for each
line-state. Si3217x ICs are available with voltage ratings
of –110 V or –135 V to support a wide range of ringing
voltages; see "10. Ordering Guide‚" on page 48 for the
voltage rating of each Si3217x version.
I_ILIM
I_RFEED
I_VLIM
ILOOP (mA)
V_ILIM
Programmable on-hook voltage, programmable off-
hook loop current, reverse battery operation, loop or
ground start operation, and on-hook transmission are
supported. Loop current and voltage are continuously
monitored by an integrated monitoring ADC.
Resistive Region
V_RFEED
V_VLIM
Constant V Region
V
TR(V)
Figure 25. Dual ProSLIC DC Feed
Characteristics
The Si3217x supports balanced 5 REN ringing with or
without a programmable dc offset. The available voltage
offset, frequency, waveshape, and cadence options are
designed to ring the widest variety of terminal devices
and to reduce external controller requirements.
5.2. Linefeed Operating States
The linefeed interface includes eight different register-
programmable operating states as listed in Table 18.
The Open state is the default condition in the absence
of any preloaded register settings. The device may also
automatically enter the open state in the event of a
linefeed fault condition.
A complete audio transmit and receive path is
integrated, including ac impedance and hybrid gain.
These features are software-programmable, allowing a
single hardware design to meet global requirements.
Select part numbers in the series also implement Silicon
Laboratories’ capacitive isolation technology to enable a
seamless connection to Si3291x DAA ICs. Digital voice
data transfer occurs over a standard PCM bus. Control
data is transferred using a standard SPI. Si3217x ICs
are available in a 42-pin QFN package. The Si3291x
devices are available in a 16-pin SOIC.
5.3. Line Voltage and Current Monitoring
The ProSLIC continuously monitors the TIP, RING, and
battery voltages and currents via an on-chip ADC and
stores the resulting values in individual RAM locations.
Additionally, the loop voltage (V –V
), loop current,
TIP
RING
and longitudinal current values are calculated based on
the TIP and RING measurements and are stored in
unique register locations for further processing. The
ADC updates all registers at a rate of 2 kHz or greater.
34
Rev. 1.4
Si3217x/3291x
The various power alarms and linefeed faults supporting
automatic intervention are described below.
5.4. Power Monitoring and Power Fault
Detection
1. Total power exceeded.
The Si3217x line monitoring functions are used to
continuously protect against excessive power
conditions. The Si3217x contains an on-chip, analog
sensing diode that provides real-time temperature data
and turns off the device when a preset threshold is
exceeded.
2. Excessive foreign current or voltage on TIP and/or
RING.
3. Thermal shutdown event.
5.5. Thermal Overload Shutdown
If the die temperature exceeds the maximum junction
temperature threshold, TJmax, of 145 °C or 200 °C, the
device has the ability to shut itself down to a low-power
state without user intervention. The thermal shutdown
circuit contains a sufficient amount of hysteresis and/or
turn-on delay time so as to remain shut down during a
power cross event, where 50 Hz or 60 Hz, 600 V, is
connected to TIP and/or RING.
If the Si3217x detects a fault condition or overpower
condition, it automatically sets that device to the open
state and generates a "power alarm" interrupt.
The interrupt can be masked, but masking the
automatic transition to open is not recommended since
it is used to protect the Si3217 HVIC under excessive
power conditions.
Table 18. Linefeed Operating States
Linefeed State
Description
Open
Output is high-impedance, and all line supervision functions are powered down. Audio is
powered down. This is the default state after powerup or following a hardware reset. This
state can also be used in the presence of line fault conditions and to generate open switch
intervals (OSIs). This state is used in line diagnostics mode as a high impedance state
during linefeed testing. A power fault condition may also force the device into the open
state.
Forward Active
Reverse Active
Linefeed circuitry and audio are active. In Forward Active state, the TIP lead is more posi-
tive than the RING lead; in Reverse Active state, the RING lead is more positive than the
TIP lead. Loop closure and ground key detect circuitry are active.
Forward OHT
Reverse OHT
Provides data transmission during an on-hook loop condition (e.g., transmitting caller ID
data between ringing bursts). Linefeed circuitry and audio are active. In Forward OHT
state, the TIP lead is more positive than the RING lead; in Reverse OHT state, the RING
lead is more positive than the TIP lead.
TIP Open
Provides an active linefeed on the RING lead and sets the TIP lead to high impedance
(>400 k) for ground start operation in forward polarity. Loop closure and ground key
detect circuitry are active.
RING Open
Provides an active linefeed on the TIP lead and sets the RING lead to high impedance
(>400 k) for ground start operation in reverse polarity. Loop closure and ground key
detect circuitry are active.
Ringing
Drives programmable ringing signal onto TIP and RING leads with or without dc offset.
Line Diagnostics
The channel is put into diagnostic mode. In this mode, the channel has special diagnostic
resources available.
Rev. 1.4
35
Si3217x/3291x
5.6. Loop Closure Detection
5.10. Two-Wire Impedance Synthesis
The Si3217x provides a completely programmable loop The ac two-wire impedance synthesis is generated on-
closure detection mechanism. The loop closure chip using a DSP-based scheme to optimally match the
detection scheme provides two unique thresholds to output impedance of the Si3217x to the reference
allow hysteresis, and also includes a programmable impedance. Most real or complex two-wire impedances
debounce filter to eliminate false detection. A loop can be generated with appropriate register coefficients.
closure detect status bit provides continuous status, and
5.11. Transhybrid Balance Filter
a maskable interrupt bit is also provided.
The trans-hybrid balance function is implemented on-
chip using a DSP-based scheme to effectively cancel
5.7. Ground Key Detection
The Si3217x provides a ground key detect mechanism the reflected receive path signal from the transmit path.
using a programmable architecture similar to the loop
5.12. Tone Generators
closure scheme. The ground key detect scheme
provides two unique thresholds to allow hysteresis and The Si3217x includes two digital tone generators that
also includes a programmable debounce filter to allow a wide variety of single- or dual-tone frequency
eliminate false detection. A ground key detect status bit and amplitude combinations. Each tone generator has
provides continuous status, and a maskable interrupt bit its own set of registers that hold the desired frequency,
is also provided.
amplitude, and cadence to allow generation of DTMF
and call progress tones for different requirements. The
tones can be directed to either receive or transmit paths.
5.8. Ringing Generation
The Si3217x provides the ability to generate a
programmable sinusoidal or trapezoidal ringing
waveform, with or without dc offset. The ringing
frequency, wave shape, cadence, and offset are all
register-programmable. Three ringing modes are
supported: balanced, unbalanced, and low-power
ringing (LPR). Figure 26 illustrates the fundamental
differences between the three ringing modes.
5.9. Polarity Reversal
The Si3217x supports polarity reversal for message
waiting and various other signaling modes. The ramp
rate can be programmed for a smooth or abrupt
transition to accommodate different application
requirements.
Balanced
Unbalanced
LPR
GND
GND
TIP
GND
TIP
RING
VBAT
TIP
RING
VBAT
RING
VBAT
Figure 26. Ringing Modes
36
Rev. 1.4
Si3217x/3291x
5.13. DTMF Detection
5.17. In-Circuit and Metallic Loop Testing
(MLT)
In DTMF, two tones generate a DTMF digit. One tone is
chosen from four possible row tones, and one tone is
chosen from four possible column tones. The sum of
these tones constitutes one of 16 possible DTMF digits.
Select Si3217x ICs support DTMF detection as outlined
in "10. Ordering Guide‚" on page 48. The DTMF
detector can be utilized by the FXS or FXO interface.
A rich set of features is provided for in-circuit testing of
the FXS system and the connected telephone line
(MLT):
Tone generators
Audio diagnostic filters
Digital and analog loop-back modes
Internal test load
5.14. Pulse Metering (Si32170/1 Only)
The pulse metering system for the Si32170/1 is
designed to inject a 12 or 16 kHz billing tone into the
Monitor ADC
DSP algorithms
audio path with maximum amplitude of 2.5 V
at TIP
RMS
Using these facilities, it is possible to test the Si3217x’s
dc-dc converter, codec, line-feed, PCM bus interface,
DSP, SPI bus interface, and call progress state-machine
as well as testing the connected telephone line and
external protection circuitry.
and RING into a 200 ac load impedance. The tone is
generated in the DSP via a table lookup that guarantees
spectral purity by not allowing drift. The tone will ramp
up until it reaches a host-programmed threshold, at
which point it will maintain that level until instructed to
ramp down, thus creating a trapezoidal envelope.
The audio diagnostic filters on the FXS are intended to
provide programmable filtering of the TX digital audio
signal and calculate the peak and/or average signal
power of the filters’ outputs. The signal powers are then
The amplitude is controlled by an automatic gain control
circuit (AGC). While the tone is ramping up, the AGC
takes the feedback audio and applies it to a band pass
filter, which is programmed for the 12 or 16 kHz
frequency of interest. When the peak is detected, the
ramp is stopped.
compared
to
programmable
thresholds.
The
programmable filters can be used to band-pass filter a
certain tone or notch out certain tones, so that the signal
power measurements are frequency selective. This
filtering is useful in a telephony system because it can
measure harmonic distortion, intermodulation, noise,
etc.
See AN340 section 2.3.9 for additional details and
considerations on Pulse Metering.
5.15. DC-DC Controller
The Si3217x incorporates an internal test load with a
5 k nominal value that can be connected across Tip/
Ring (Figure 27). The audio diagnostics system and
built-in test load can be used to test the FXS interface
(Si3217x) itself without requiring an external load, a
connected line, or any relays. This facility can be used
for production and in-service testing of such things as:
The Si3217x integrates a dc-dc controller that operates
from
a single positive dc input. The controller
dynamically manages an external dc-dc converter
circuit to generate the optimal battery voltage for each
operating state.
5.16. Wideband Audio
Select Si3217x ICs support a software-selectable
wideband (50 Hz–7 kHz) and narrowband (200 Hz–
3.4 kHz) audio codec. The wideband mode provides an
expanded audio band at a 16-bit, 16 kHz sample rate
for enhanced audio quality while maintaining standard
telephony audio compatibility. Wideband audio samples
are transmitted and received on the PCM interface
using two consecutive 8 kHz frames.
Dial tone draw/break
Audio quality measurements
Pulse digit detection
DC feed
Ringtrip
Polarity reversal
Transmission loss
Rev. 1.4
37
Si3217x/3291x
MLT, e.g., GR-909, is facilitated by the built-in DSP, Ringers Test – Measures the magnitude of the
monitor ADC, and test load. They provide the ability to
detect multiple fault conditions within the CPE as well as
on the Tip/Ring pair (T-R). Thirteen different measured
and/or calculated parameters are reported by the
Monitor ADC. Host software for use in conjunction with
the ProSLIC API is available from Silicon Labs. Typical
MLT tests include:
connected ring load (REN) across T-R. Results are
> 0.175 REN and < 5 REN for a valid load
AC Line Impedance (line length) – T-R, T-G, and R-
G. Generates a tone at several specific frequencies
(audio band) and measures the reflected signal
amplitude (complex spectrum) that comes back (with
transhybrid balance filter disabled). The reflected
signal is then used to calculate the line impedance
based on certain assumptions of wire gauge, etc.
Hazardous Potential Test – This checks for ac
voltage > 50 V
or dc voltage > 135 V between
RMS
Line Capacitance – T-R, T-G, R-G. Generates a
linear ramp function with polarity reversal, and
measures the time constant.
Tip and Ground (T-G) or Ring and Ground (R-G).
Foreign Electromotive Force Test – Checks T-G or
R-G for ac voltage > 10 V
or dc voltage > 6 V.
RMS
Diagnostic information is available even in the presence
of fault conditions that cause the system’s protection
devices (fuses, PTCs, etc.) to open. A high-impedance
sensing path (pins SRINGC and STIPC) can be used to
measure the conditions on Tip/Ring even when the FXS
system is effectively disconnected from the line. No
relay is required and this sensing path inherently meets
Dielectric Withstand per GR-49 (> 1000 V).
Uses same threshold as for hazardous voltage test.
Resistive Faults Test – Checks for dc resistance
from T-R, T-G or R-G. Any measurement < 150 k is
considered a resistive fault.
Receiver-Off-Hook Test – Distinguishes between a
T-R resistive fault and an off-hook condition.
Test Load
TIP
RTL = 5.3 k (typical)
RING
HVIC_STATE_SPARE[23]
0 = Test Load OFF
1 = Test Load ON
Figure 27. Si3217x Internal Test Load Circuit
38
Rev. 1.4
Si3217x/3291x
6.5. Line Voltage Measurement
6. FXO Features
Line voltage can be measured in both on-hook and off-
hook states with a resolution of 1V per bit and a range of
6.1. Isolation Barrier
The Si32178/9 and Si3291x achieve an isolation barrier -128 to 127V. Values between –3 to 3 V can, optionally,
through low-cost, high-voltage capacitors in conjunction be forced to zero to mask measurements between –2 to
with Silicon Laboratories’ patented signal processing 2 V, which may be unpredictable.
techniques.
Polarity reversal detection is triggered whenever the
The isolation barrier provides greater than 5 kV sign of the measured value changes between positive
isolation.
and negative states.
6.2. Power Management
6.6. Loop Current Measurement
The Si32178/9 FXO circuitry supports four power Loop current sensing is available in the off-hook state.
management modes: reset mode, normal mode, sleep Loop currents are measurable down to the minimum
mode and powerdown mode. When in reset mode, the operating loop current of the DAA, which is
Si32178/9 FXO is operational, except for the programmable to 10, 12, 14 or 16mA. Currents can be
communication link to the line-side device (Si3291x). In measured with a resolution of 1.1 or 3.3 mA over a
normal mode, the chipset is fully operational. Sleep range of 0 to 127 mA. If the loop current exceeds the
mode provides a low-power state that only supports ring programmed current limit of the device (160 mA or
detection, ring validation and wake-up-on-ring features. 60 mA), an over-current event is reported.
The powerdown mode puts the chipset in a non-
6.7. Parallel Handset Detection
functional state that requires the least power. Normal
operation can be restored by issuing a reset.
The integrated line sensing capabilities of the Si32178/9
can be used to detect a parallel handset going off-hook.
When off-hook, a significant change in loop current
6.3. In-Circuit Testing
Six FXO loopback modes are available to support signals a parallel phone off-hook or on-hook event.
production line testing and end-user diagnostics. Four When on-hook, a significant drop in line-voltage signals
of the test modes require a line-side power source.
a parallel phone off-hook event.
6.4. Transmit/Receive Full-Scale Level
6.8. DC Termination
The Si32178/9 supports programmable maximum The DAA has programmable settings for the dc
transmit and receive levels. The default signal level impedance, current limiting, minimum operational loop
supported by the Si32178/9 is 0 dBm into a 600 load. current and TIP/RING voltage. The dc impedance of the
Two additional modes of operation offer increased DAA is normally represented with a 50 slope as
transmit and receive level capability to enable use of the shown in Figure 28, but can be changed to an 800
DAA in applications that require higher signal levels. slope. This higher dc termination presents a higher
The full-scale mode increases the full-scale signal level resistance to the line as loop current increases.
to +3.2 dBm into a 600 load or 1 dBV into all
reference impedances. The enhanced full-scale mode
increases the full-scale signal level to +6.0 dBm into a
600 load or 1.5 dBV into all reference impedances.
The full-scale and enhanced full-scale modes provide
the ability to trade off TX power and TX distortion for a
peak signal. By using the programmable digital gain
registers in conjunction with the enhanced full-scale
signal level mode, a specific power level (+3.2 dBm for
example) can be achieved across all ac termination
settings.
FCC DCT Mode
12
11
10
9
8
7
6
.01 .02 .03 .04 .05 .06 .07 .08 .09 .1 .11
Loop Current (A)
Figure 28. FCC Mode I/V Characteristics
Rev. 1.4
39
Si3217x/3291x
For applications requiring current limiting per the TBR21
standard, the ILIM bit may be set to select this mode. In
this mode, the dc I/V curve is changed to a 2000
slope above 40 mA, as shown in Figure 29. This allows
the DAA to operate with a 50 V, 230 feed, which is the
maximum linefeed specified in the TBR21 standard.
Table 19. AC Termination Settings for the
Si3291x Line-Side Devices
Si32911
Si32919
AC Termination
ü
ü
ü
ü
600
900
TBR21 DCT Mode
45
ü
270 + (750 || 150 nF)
275 + (780 || 150 nF)
40
35
30
25
20
15
10
ü
220 + (820 || 120 nF)
220 + (820 || 115 nF)
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
370 + (620 || 310 nF)
320 + (1050 || 230 nF)
370 + (820 || 110 nF)
270 + (750 || 150 nF)
275 + (780 || 115 nF)
120 + (820 || 110 nF)
350 + (1000 || 210 nF)
200 + (680 || 100 nF)
600 + 2.16 µF
5
.015 .02 .025 .03 .035 .04 .045 .05 .055 .06
Loop Current (A)
Figure 29. TBR21 Mode I/V Characteristics
6.9. AC Termination
900 + 1 µF
The Si32911 is optimized to support only CTR21/TBR21
and FCC-compliant countries. The Si32919 is a
globally-compliant DAA solution. The following table
highlights the available ac termination settings in each
device:
900 + 2.16 µF
600 + 1 µF
Global complex impedance
6.10. Ring Detection
The Si32178/9 supports either full- or half-wave ring
detection. With full-wave ring detection, the designer
can detect a polarity reversal of the ring signal. See
“Transhybrid Balance” on page 41. The Si32919
supports three programmable ring thresholds: 15 V
±10%, 21 V ±10%, and 45 V ±10%. The Si32911
supports 15 V ±10%.
40
Rev. 1.4
Si3217x/3291x
6.11. Ring Validation
6.14. Receive Overload Detection
Ring validation prevents false triggering of a ring The Voice DAA chipset is capable of monitoring and
detection by validating the ring parameters. Invalid reporting receive overload conditions on the line. Billing
signals, such as a line-voltage change when a parallel tones, parallel phone off-hook events, polarity reversals
handset goes off-hook, pulse dialing, or a high-voltage and other disturbances on the line may trigger multiple
line test are ignored. Ring validation can be enabled levels of overload detection.
during normal operation and in sleep mode when a valid
external PCLK signal is supplied.
Certain events, such as billing tones, can be sufficiently
large to disrupt the line-derived power supply of an
The ring validation circuit calculates the time between Si3291x line side device. The Si3291x devices support
alternating crossings of positive and negative ring a dynamically-enabled high-impedance mode to ensure
thresholds for a programmed period of time to validate that they maintain the off-hook line state during these
that the ring frequency is within tolerance. High and low events.
frequency tolerances are also programmable.
6.15. On-Hook Line Monitor
6.12. Ringer Impedance and Threshold
The on-hook line monitor mode allows the Si32178/9 to
The ring detector on the Si3291x device is resistively receive line activity when in an on-hook state. This
coupled to the line. This coupling produces a high ringer mode is typically used to detect caller ID data (see
impedance to the line of approximately 20 Mto meet “6.16. Transhybrid Balance” ). Caller ID data can be
the majority of country PTT specifications including FCC gained up or attenuated in the device.
and TBR21.
6.16. Transhybrid Balance
A synthesized ringer impedance can also be enabled to
The Si32178/9 contains an on-chip analog hybrid that
comply with maximum ringer impedance specifications
performs the 2- to 4-wire conversion and near-end echo
of several countries including Poland, South Africa, and
cancellation. This hybrid circuit is adjusted for each ac
Slovenia.
termination setting selected to achieve a minimum
transhybrid balance of 20 dB when the line impedance
matches the selected ac termination.
6.13. Pulse Dialing and Spark Quenching
Pulse dialing is accomplished by going off- and on-hook
to generate make and break pulses. The nominal rate is The Si3217x also offers a programmable digital hybrid
10 pulses per second. Some countries have strict stage for additional near-end echo cancellation. For
specifications for pulse fidelity including make and each ac termination setting, the hybrid can be
break times, make resistance, and rise and fall times. In programmed with coefficients to increase cancellation of
a traditional, solid-state dc holding circuit, there are a real-world line impedances. This digital filter can
number of issues in meeting these requirements. The produce 10 dB or greater of near-end echo cancellation
Si3217x dc holding circuit has active control of the on- in addition to the trans-hybrid loss from the analog
and off-hook transients to maintain pulse dialing fidelity. hybrid circuitry.
Spark quenching requirements in countries, such as
Italy, the Netherlands, South Africa, and Australia, deal
with the on-hook transition during pulse dialing. The
Si32919 supports three distinct on-hook speeds to pass
spark quenching tests without additional BOM
components.
Rev. 1.4
41
Si3217x/3291x
7.2. PCM Interface and Companding
7. System Interfaces
The Si3217x contains
interface for the transmission and reception of digital
a
flexible, programmable
7.1. SPI Control Interface
The controller interface to the Si3217x is a 4-wire PCM samples. PCM data transfer is controlled by the
interface modeled after microcontroller and serial PCM clock (PCLK) and frame sync (FSYNC) inputs as
peripheral devices. The interface consists of a clock well as the PCM Mode Select, PCM Transmit Start, and
(SCLK), chip select (CS), serial data input (SDI), and PCM Receive Start settings.
serial data output (SDO). In addition, the ProSLIC
The interface can be configured to support from 8 to
devices feature a serial data through output (SDITHRU)
128 8-bit time slots in each 125 µs frame,
to support operation of up to 16 channels using a single
corresponding to a PCM clock (PCLK) frequency range
chip select line. The FXS port and FXO port (if available
of 256 kHz to 8.192 MHz. 1.544 MHz is also supported.
and enabled) each occupy one SPI channel. The device
The Si3217x supports both µ-255 Law (µ-Law) and A-
operates with both 8-bit and 16-bit SPI controllers.
law companding formats in addition to 16-bit linear data
mode with no companding.
42
Rev. 1.4
Si3217x/3291x
8. Pin Descriptions: Si3217x
42
VDDHV
SDI
41 40 39 38 37 36
EPAD2
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
1
2
3
4
GPIO1/STIPC
GPIO2/SRINGC
SRINGDC
SRINGAC
STIPAC
STIPDC
VDDA
SDO
SCLK
SDITHRU
5
6
CS
FSYNC
PCLK
7
8
9
INT
QGND
EPAD1
C2A/NC
C1A/NC
10
11
12
13
14
IREF
CAPM
DTX
DRX
CAPP
CAPLB
15 16 17 18 19 20 21 22
DCFF
SVBAT
Pin #
Pin Name
Description
1
VDDHV
IC Voltage Supply.
Serial Port Data Input.
Serial port control data input.
2
3
SDI
Serial Port Data Output.
Serial port control data output.
SDO
Serial Port Bit Clock Input.
4
5
6
SCLK
SDITHRU
CS
Serial port clock input. Controls the serial data on SDO and latches the data on
SDI.
SDI Passthrough.
Cascaded SDI output signal for daisy-chain mode.
Chip Select Input.
Active low. When inactive, SCLK and SDI are ignored and SDO is high impedance.
When active, the serial port is operational.
Frame Sync Clock Input.
7
FSYNC
8 kHz frame synchronization signal for the PCM bus. May be short or long pulse
format.
PCM Bus Clock Input.
Clock input for PCM bus timing.
8
9
PCLK
INT
Interrupt Output.
Maskable interrupt output. Open drain output for wire-ORed operation.
Si32178/9 only: Connects to one side of the isolation capacitor C1. Used to com-
municate with the FXO line-side device. For versions of Si3217x that do not sup-
port an FXO I/F or if the FXO line-side device is not populated this pin should be left
unbiased.
10
C2A/NC
Rev. 1.4
43
Si3217x/3291x
Pin #
Pin Name
Description
Si32178/9 only: Connects to one side of the isolation capacitor C2. Used to com-
municate with the FXO line-side device. For versions of Si3217x that do not sup-
port an FXO I/F or if the FXO line-side device is not populated this pin should be left
unbiased.
11
C1A/NC
Transmit PCM Data Output.
12
13
DTX
DRX
Output data to PCM bus.
Transmit PCM Data Input.
Input data from PCM bus.
DC Feed-Forward/High Current General Purpose Output.
14
15
DCFF
SDCH
Feed-forward drive of external bipolar transistors to improve dc-dc converter effi-
ciency
DC Monitor.
DC-DC converter monitor input used to detect overcurrent situations in the con-
verter
DC Monitor.
16
17
SDCL
DC-DC converter monitor input used to detect overcurrent situations in the con-
verter.
DC Drive/Battery Switch.
DCDRV
DC-DC converter control signal output which drives external bipolar transistor.
IC Voltage Supply.
18
19
VDDD
Digital power supply for internal digital circuitry.
VDDREG
Regulated Core Power Supply.
Reset Input.
20
21
RST
Active low input. Hardware reset used to place all control registers in the default
state.
DC-DC Input Voltage Sensor.
SVDC
Serves V input to dc-dc converter.
DC
VBAT Sense.
22
23
24
SVBAT
CAPLB
CAPP
Analog current input used to sense voltage on dc-dc converter output voltage lead.
Calibration Capacitor.
SLIC Stabilization Capacitor.
Capacitor used in low pass filter to stabilize SLIC feedback loops.
SLIC Stabilization Capacitor.
25
CAPM
Capacitor used in low pass filter to stabilize SLIC feedback loops.
Current Reference Input.
26
27
IREF
Connects to an external resistor used to provide a high accuracy reference current.
QGND
Quiet Ground Reference Input.
44
Rev. 1.4
Si3217x/3291x
Pin #
Pin Name
Description
Analog Supply Voltage.
28
VDDA
Analog power supply for internal analog circuitry.
TIP DC Sense.
29
30
STIPDC
STIPAC
Analog current input used to sense voltage on the TIP lead.
TIP AC Sense Input.
Analog ac input used to detect voltage on the TIP lead.
RING AC Sense Input.
31
32
SRINGAC
SRINGDC
Analog ac input used to detect voltage on the RING lead
RING DC Sense Input.
Analog current input used to sense voltage on the RING lead.
General Purpose I/O.
GPIO2
SRINGC
33
34
RING Coarse Sense Input.
Voltage sensing outside protection circuit.
General Purpose I/O.
GPIO1
STIPC
TIP Coarse Sense Input.
Voltage sensing outside protection circuit.
No Connect.
This pin should be left unbiased.
35
36
37
38
NC
VBAT
NC
Battery Voltage Supply.
Connect to battery supply from dc-dc converter.
No Connect.
This pin should be left unbiased.
RING Terminal.
RING
Connect to the RING lead of the subscriber loop.
No Connect.
39
40
NC
TIP
This pin should be left unbiased.
TIP Terminal.
Connect to the TIP lead of the subscriber loop.
No Connect.
This pin should be left unbiased.
41
42
—
NC
NC
No Connect.
This pin is internally connected to EPAD2 and should be left unbiased.
Exposed paddle.
Connect to ground.
EPAD1
Exposed paddle.
—
EPAD2
Connect to electrically-isolated low thermal impedance inner layer and/or backside
thermal plane using multiple thermal vias.
Rev. 1.4
45
Si3217x/3291x
9. Pin Descriptions: Si3291x
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DCT2
IGND
DCT3
QB
QE
DCT
RX
IB
QE2
C1B
C2B
VREG
RNG1
SC
VREG2
RNG2
Pin # Pin Name
Transistor Emitter.
Description
1
2
3
4
QE
DCT
RX
Connects to the emitter of Q3.
DC Termination.
Provides dc termination to the telephone network.
Receive Input.
Serves as the receive side input from the telephone network.
Internal Bias.
IB
Provides a bias voltage to the device.
Isolation Capacitor 1B.
5
C1B
Connects to one side of isolation capacitor C1. Used to communicate with the
system-side device (Si32178/9).
Isolation Capacitor 2B.
6
7
8
C2B
Connects to one side of isolation capacitor C2. Used to communicate with the
system-side device (Si32178/9).
Voltage Regulator.
VREG
RNG1
Connects to an external capacitor to provide bypassing for an internal power supply.
Ring 1.
Connects through a resistor to the TIP lead of the telephone line. Provides the ring and caller
ID signals to the DAA.
Ring 2.
9
RNG2
Connects through a resistor to the RING lead of the telephone line. Provides the ring and
caller ID signals to the DAA.
Voltage Regulator 2.
10
11
VREG2
SC
Connects to an external capacitor to provide bypassing for an internal power supply.
SC Connection.
Enables external transistor network. Should be tied through a 0 resistor to I
.
GND
46
Rev. 1.4
Si3217x/3291x
Pin # Pin Name
Description
Transistor Emitter 2.
12
13
14
15
16
QE2
QB
Connects to the emitter of Q4.
Transistor Base.
Connects to the base of transistor Q4.
DC Termination 3.
DCT3
IGND
DCT2
Provides dc termination to the telephone network.
Isolated Ground.
Connects to ground on the line-side interface.
DC Termination 2.
Provides dc termination to the telephone network.
Rev. 1.4
47
Si3217x/3291x
10. Ordering Guide
Table 20. Si3217x-3291x Ordering Guide1
P/N
Description
Package Max V
Temperature
BAT
2
2
2
2
Si32170-B-FM1
Si32170-B-GM1
Si32171-B-FM1
Si32171-B-GM1
Narrowband FXS, PCM Interface, DTMF detection,
pulse metering
LGA
LGA
LGA
LGA
–136 V
0 to 70 °C
Narrowband FXS, PCM Interface, DTMF detection,
pulse metering
–136 V
–110 V
–110 V
–40 to 85 °C
0 to 70 °C
Narrowband FXS, PCM Interface, DTMF detection,
pulse metering
Narrowband FXS, PCM Interface, DTMF detection,
pulse metering
–40 to 85 °C
2
2
2
2
2
Si32176-B-FM1
Si32176-B-GM1
Si32177-B-FM1
Si32177-B-GM1
Si32178-B-FM1
Wideband capable FXS, PCM Interface
Wideband capable FXS, PCM Interface
Wideband capable FXS, PCM Interface
Wideband capable FXS, PCM Interface
LGA
LGA
LGA
LGA
LGA
–110 V
–110 V
–136 V
–136 V
–110 V
0 to 70 °C
–40 to 85 °C
0 to 70 °C
–40 to 85 °C
0 to 70 °C
Wideband capable FXS with FXO support,
PCM Interface, DTMF detection
2
2
2
3
Si32178-B-GM1
Si32179-B-FM1
Si32179-B-GM1
Si32171-B-FM
Si32171-B-GM
Wideband capable FXS with FXO support,
PCM Interface, DTMF detection
LGA
LGA
LGA
–110 V
–136 V
–136 V
–110 V
–110 V
–40 to 85 °C
0 to 70 °C
Wideband capable FXS with FXO support,
PCM Interface, DTMF detection
Wideband capable FXS with FXO support,
PCM Interface, DTMF detection
–40 to 85 °C
0 to 70 °C
Narrowband FXS, PCM Interface, DTMF detection,
pulse metering
NBA
NBA
3
Narrowband FXS, PCM Interface, DTMF detection,
pulse metering
–40 to 85 °C
3
3
3
3
3
Si32176-B-FM
Si32176-B-GM
Si32177-B-FM
Si32177-B-GM
Si32178-B-FM
Wideband capable FXS, PCM Interface
Wideband capable FXS, PCM Interface
Wideband capable FXS, PCM Interface
Wideband capable FXS, PCM Interface
NBA
NBA
NBA
NBA
NBA
–110 V
–110 V
–136 V
–136 V
–110 V
0 to 70 °C
–40 to 85 °C
0 to 70 °C
–40 to 85 °C
0 to 70 °C
Wideband capable FXS with FXO support,
PCM Interface, DTMF detection
3
Si32178-B-GM
Wideband capable FXS with FXO support,
PCM Interface, DTMF detection
NBA
–110 V
–40 to 85 °C
Notes:
1. Adding the suffix "R" to the part number (e.g. Si32176-B-FM1R) denotes tape and reel.
2. LGA – Land Grid Array.
3. NBA – No Ball Array. Not recommended for new designs. This package must be used only with high Tg PCB material
(> 170 °C) when using Pb-free solder profiles.
48
Rev. 1.4
Si3217x/3291x
FXO P/N
Region
Ringer
On-hook
Temperature
Thresholds
Speeds
Si32911-A-FS
Si32911-A-GS
Si32919-A-FS
Si32919-A-GS
FCC/CTR21
FCC/CTR21
Global
1
1
3
3
2
2
3
3
0 to 70 °C
–40 to 85 °C
0 to 70 C
Global
–40 to 85 °C
Note: Adding the suffix “R” to the part number (e.g., Si32919-A-FSR) denotes tape and reel.
Table 21. Si3217x Revision C Evaluation Kit Ordering Guide
Part Number
Description
V
Max
BAT
Si32171FBMB-EVB
Wideband capable FXS with DTMF detection and pulse metering,
110 V Flyback (MOSFET transformer based) dc-dc converter EVB
–110 V
–85 V
Si32176PB10SL0-EVB Wideband FXS, 85 V PMOS buck-boost (PMOS FET and inductor based)
dc-dc converter EVB for V in the range 3.3 to 5.5 V
DC
Si32176PB10SL2-EVB
Wideband FXS, 110 V PMOS buck-boost (PMOS FET and inductor
–110 V
based) dc-dc converter EVB for V nominally 12 V. 1FXS/2FXS dual
DC
population board (2FXS version Si32260PB20SL2-EVB)
Si32176BBMB-EVB
Si32177FBMB-EVB
Wideband FXS, 100 V buck-boost (BJT inductor based) dc-dc converter
EVB
–100 V
–136 V
Wideband FXS, 136 V flyback (MOSFET transformer based) dc-dc
converter EVB
Rev. 1.4
49
Si3217x/3291x
11. Product Identification
The product identification number is a finished goods part number or is specified by a finished goods part number,
such as a special customer part number.
Example:
Si32178-B-FM1R
Shipping Option
Blank = Trays
Product Designator
R = Tape and Reel
Product Revision
Package Type
M1 = QFN/LGA
M = QFN/NBA
S = SOIC
Part Type / Lead Finish
F = Commercial / RoHS-Compliant
G = Industrial / RoHS-Compliant
50
Rev. 1.4
Si3217x/3291x
12. Package Outline
12.1. 42-Pin QFN/LGA
Figure 30 illustrates the package details for the Si3217x. Table 22 lists the values for the dimensions shown in the
illustration.
Figure 30. 42-Pin QFN/LGA Package
Table 22. 42-Pin QFN/LGA Package Diagram Dimensions
Dimension
Min
0.80
0.20
Nom
0.85
Max
0.90
0.30
A
b
0.25
D
5.00 BSC
3.40
D2
e
3.35
3.45
0.50 BSC
7.00 BSC
5.40
E
E2
E3
E4
L
5.35
1.65
3.15
0.35
0.05
—
5.45
1.75
3.25
0.45
0.15
0.10
0.10
1.70
3.20
0.40
L1
aaa
bbb
ccc
ddd
0.10
—
—
—
—
—
0.08
0.10
—
—
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification
for Small Body Components.
Rev. 1.4
51
Si3217x/3291x
12.2. 42-Pin QFN/NBA
Figure 30 illustrates the package details for the Si3217x. Table 22 lists the values for the dimensions shown in the
illustration.
Figure 31. 42-Pin QFN/NBA Package
Table 23. 42-Pin QFN/NBA Package Diagram Dimensions
Dimension
Min
0.60
0.20
Nom
0.65
Max
0.70
0.30
A
b
0.25
D
5.00 BSC
3.40
D2
e
3.35
3.45
0.50 BSC
7.00 BSC
5.40
E
E2
E3
E4
L
5.35
1.65
3.15
0.35
0.05
—
5.45
1.75
3.25
0.45
0.15
0.10
0.10
1.70
3.20
0.40
L1
aaa
bbb
ccc
ddd
0.10
—
—
—
—
—
0.08
0.10
—
—
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification
for Small Body Components.
52
Rev. 1.4
Si3217x/3291x
13. PCB Land Pattern Si3217x QFN (LGA or NBA)
Table 24. PCB Land Pattern
Dimension
mm
C1
C2
E
4.60
6.60
0.50
0.30
3.45
0.45
1.75
3.25
5.45
X1
X2
Y1
Y2
Y3
Y4
Notes:
General
1. All dimensions shown are in millimeters (mm).
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is
calculated based on a Fabrication Allowance of 0.05 mm.
Rev. 1.4
53
Si3217x/3291x
13.1. QFN PCB Design
1. High-Tg PCB materials (Glass Transition Temperature 170 °C) are recommended for Pb-Free reflow profiles
per standard industry practice. This is required for reliable board assembly when using the NBA package.
2. PCB design must ensure sufficient thermal relief for high power operation of the device. See layout guidelines in
application note AN340 for further details.
3. A minimum of four vias are required under each E-Pad. Eight or more vias are recommended.
4. Via diameter should be between 0.20 and 0.31 mm.
5. Metal-to-Metal distance between outer edge of via diameter and closest edge of device perimeter pad must be
1.00 mm (dimension "X" below).
6. Vias may be placed as desired within the non-hatched area of the E-Pads. Final via size and count is
dependent on the choice of PCB materials and the total thermal relief provided by the internal Cu plane in the
PCB.
7. Vias should either be filled or tented on the top side of the board to prevent solder thieving under the device.
54
Rev. 1.4
Si3217x/3291x
13.2. QFN Solder Mask Design
All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad
is to be 60 µm minimum, all the way around the pad.
13.3. QFN Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good
solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
4. A 1x2 array of 1.40 mm square openings on 1.7 mm pitch should be used for the top center pad and a 2x2 array
of 1.35 mm square openings on 1.7 mm pitch should be used for the bottom center pad (as shown below).
13.4. QFN Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020D specification for Small Body
Components.
Rev. 1.4
55
Si3217x/3291x
14. Package Outline: 16-Pin SOIC
Figure 32 illustrates the package details for the Si3291x. Table 25 lists the values for the dimensions shown in the
illustration.
Figure 32. 16-Pin Small Outline Integrated Circuit (SOIC) Package
56
Rev. 1.4
Si3217x/3291x
Table 25. 16-Pin SOIC Package Diagram Dimensions
Dimension
Min
—
Max
1.75
0.25
—
A
A1
A2
b
0.10
1.25
0.31
0.17
0.51
0.25
c
D
9.90 BSC
6.00 BSC
3.90 BSC
1.27 BSC
E
E1
e
L
0.40
1.27
L2
h
0.25 BSC
0.25
0°
0.50
8°
θ
aaa
bbb
ccc
ddd
0.10
0.20
0.10
0.25
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MS-012, Variation AC.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
Rev. 1.4
57
Si3217x/3291x
15. PCB Land Pattern Si3291x SOIC
Table 26. PCB Land Pattern
Dimension
Feature
(mm)
5.40
1.27
0.60
1.55
C1
E
Pad Column Spacing
Pad Row Pitch
Pad Width
X1
Y1
Pad Length
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X165-16N
for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card
fabrication tolerance of 0.05mm is assumed.
58
Rev. 1.4
Si3217x/3291x
16. Top Markings
16.1. Si3217x LGA Package Top Marking
16.2. Si3217x LGA Package Top Marking Explanation
Line 1 Marking:
Line 2 Marking:
Device Part Number
e.g., 32178-FM1
YY = Year
WW = Work Week
Assigned by the Assembly House. Corresponds to
the year and work week of the assembly release.
TTTTTT = Mfg Code
Manufacturing Code from the Assembly Purchase
Order form.
Circle = 0.5 mm Diameter
Lower Left-Justified
Pin 1 Identifier
“e4” Pb-Free Symbol
e.g., KR
Line 3 Marking:
Circle = 1.3 mm Diameter
Center-Justified
Country of Origin
ISO Code Abbreviation
Rev. 1.4
59
Si3217x/3291x
16.3. Si3217x NBA Package Top Marking
16.4. Si3217x NBA Top Marking Explanation
Line 1 Marking:
Line 2 Marking:
Device Part Number
e.g., Si32178/9-FM
YY = Year
WW = Work Week
Assigned by the Assembly House. Corresponds
to the year and work week of the assembly
release.
TTTTTT = Mfg Code
Assembly Lot Manufacturing Code.
Circle = 0.5 mm Diameter
Lower Left-Justified
Pin 1 Identifier
Line 3 Marking:
Circle = 1.3 mm Diameter
Center-Justified
“e4” Pb-Free Symbol
e.g., TW
Country of Origin
ISO Code Abbreviation
60
Rev. 1.4
Si3217x/3291x
16.5. Si32919 Top Mark
16.6. Si3291x Top Mark Explanation
Line 1 Marking:
Line 2 Marking:
Customer Part Number
Si32919-A-FS
Circle = 1.3 mm Diameter
“e3” Pb-Free Symbol
YY = Year
WW = Work Week
Assigned by the Assembly House. Corresponds
to the year and work week of the assembly
release.
TTTTTT = Mfg Code
Manufacturing Code
Rev. 1.4
61
Si3217x/3291x
Revision 0.11 to Revision 0.12
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.11
Added description of maximum battery ratings to
front page description.
Corrected name of pin 34 on Si3217 pin assignment
Deleted operating temperature range in Table 1.
diagrams.
Changed TA from 70°C to 85°C for continuous
Corrected names and descriptions for Si3217 pins
power dissipation entries in Table 1.
numbers 10, 11, 21, and 22.
Added -130V rated devices to Table 1.
Expanded descriptions for Si3217 pins numbers 35,
Replaced TBD for SOIC-16 Continuous Power
37,39, 41 and 42.
Dissipation.
Changed EPAD names to match reference design
Added Battery Voltage row for Si3217xH to Table 2.
Updated supply currents in Table 3.
schematics.
Removed footnote from Si3217 pin descriptions
Added Ringing Amplitude information for –130 V
table.
rated devices to Table 5.
Added C1A, C1B, C2A, C2B pin names to
Edited second and third paragraphs in the Overview
Functional Block Diagram.
Section with information about -130V rated ICs.
Added entries for C1A, and C2A to Table 11, “DC
Updated the FXS table in the Ordering Guide.
Characteristics”.
Added G-grade devices under Product Identification.
Harmonized IO polarities of for VOH and VOL test
Added part number information to Package Outline
conditions for outputs in Table 11.
descriptions in sections 10 and 11.
Deleted references to relay drivers in Table 11.
Revision 0.12 to Revision 1.0
Corrected GPIO1/STIPC and GPIO2/SRINGC
entries in Table 11.
Renamed Si32176H to Si32177.
Deleted INT entry for V in Table 11.
OH
Updated descriptions of voltage ratings in the
Description section on front page and the Overview
section.
Added Si3291x to title.
Added image and pin assignment diagram for
Updated Ordering Guide.
Si3291x to cover page.
Updated V
entries in Table 1 and Table 2.
Deleted VBAT = –135 V and VBAT = –130 V entries
BAT
from Ringing Amplitude row of Table 5.
Added V
and V
entries to Table 1.
TIP
RING
Clarified titles of Tables 4 through 8 to indicate FXS
Updated front page Description section.
Updated Table 14.
or FXO.
Corrected references in footnote 1 of Table 8.
Added Figures 1 through 11.
Updated Table 1, 2, 3, 4, 5, 10, and 13.
Added Typical Applications schematics.
Added Figure 20, 21, 22, and 19.
Added Tables 9 and 10.
Replaced Si32911/19 with Si3291x throughout.
Replaced Si3217 with Si3217x throughout.
Replaced Si3291 with Si3291x throughout.
Deleted G-Grade from Table 2
Updated section “4. Overview” , “5.4. Power
Monitoring and Power Fault Detection” , “5.14. Pulse
Metering (Si32170/1 Only)” , “5.17. In-Circuit and
Metallic Loop Testing (MLT)” , “8. Pin Descriptions:
Si3217x” , “9. Pin Descriptions: Si3291x” , and “14.
Package Outline: 16-Pin SOIC” .
Removed 3.3 V from title of Table 3.
Filled-in Typical supply currents in Table 3.
Added system-side FXO supply current rows to
Table 3.
Added reference to AN340 to the Calibration Time
row in Table 5.
Corrected footnote in Table 5.
Deleted Si32175-A-FM and Si32177-A-FM from
Ordering Guide.
Added Section 9 Product Identification.
62
Rev. 1.4
Si3217x/3291x
Revision 1.0 to Revision 1.1
Removed ringing amplitude with 5 REN load from
Table 4 because these values were specified with an
invalid RDO of 100
Decreased maximum PCLK period to 1953 ns (was
3906 ns) in Table 13 and added PCLK jitter
tolerance of ±8 ns
Updated schematics, BOMs and added buck-boost
dc-dc converter schematics
Added package top mark drawings
Added PCB land patterns and soldering notes
Revision 1.1 to Revision 1.2
Added LGA package information.
Corrected thermal resistance, , to 53°C/W and
JA
adjusted maximum continuous power dissipation,
PD, to 0.75W.
Added definition of dBm0.
Added specification for RST (with overbar) internal
pull up current (same as SDITHRU).
Added support for PCLK as low as 256kHz (3906ns
period) for commercial temperature parts only (0°C
to +70°C).
Changed PCLK jitter tolerance spec for FXS to
8nsRMS
Added PCLK jitter tolerance for FXO devices -
2nsRMS
Corrected SDCL connection in top level schematic to
make it clear that it is not connected directly to
ground.
Revision 1.2 to Revision 1.3
Added industrial temperature (–40 to 85 °C) options
for the Si32178 and Si3219x devices.
Revision 1.3 to Revision 1.4
Added new part numbers Si32170 and Si32179
Corrected formatting
Added additional thermal resistance values and
JB
JC
Standardized test condition for supply currents
measurement and values in Table 2 for Forward/
Reverse Active, Off-hook state to match data sheets
of other current ProSLICs
Rev. 1.4
63
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Disclaimer
Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or
intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical"
parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes
without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included
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