SI3220PPT-EVB [SILICON]
EVALUATION BOARD FOR THE Si3220 DUAL PROSLIC; 评估板为Si3220双信道ProSLIC
| 型号： | SI3220PPT-EVB |
| 厂家： | 
SILICON |
| 描述： | EVALUATION BOARD FOR THE Si3220 DUAL PROSLIC |
| 文件： | 总16页 (文件大小：778K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si3220PPT-EVB
EVALUATION BOARD FOR THE Si3220 DUAL PROSLIC
Description
Features
This document describes the operation of the Silicon Silicon Laboratories Dual ProSLIC device
Laboratories Si3220 Dual ProSLIC™ device evaluation
platform. The Dual ProSLIC evaluation platform is
designed to provide observation of the ProSLIC’s
functionality. The Dual ProSLIC platform consists of a
ProSLIC motherboard, an Si3220 daughter card
(Si3220DC0-EVB), and the ProSLIC LINC™ software.
The ProSLIC LINC software is a GUI-based program
that can run in Microsoft Windows® environments.
Equipment requirements:
PC running Windows 95, 98, ME, NT, or 2000
5 V, 1 A power supply
Stackable cards for up to 16 channels
All components necessary for linecard
implementation
Layout for optional secondary protections
Control I/O through standard parallel port
On-board oscillator for stand-alone operation
PCM I/O set up for Audio Precision System 2 or
Wandel and Goltermann PCM-4
Full access to PCM highway
ProSLIC power selection (3 V or 5 V)
3 V, 1 A power supply (optional)
–24 V, 0.5 A power supply
–75 V, 0.5 A power supply
Balanced audio generator and analyzer (optional)
(e.g., Audio Precision System 2 and/or HP TIMS set
and/or Wandel and Goltermann PCM-4)
8 kHz PCM signal generator and analyzer (optional)
(e.g., Audio Precision System 2 and Audio Precision
SIA-2322 and/or Wandel and Goltermann PCM-4)
Function Block Diagram
VBHI, VBLO, +3 V, +5 V
Power In
Parallel Port
PCM Transmit
Si3220
PCM Receive
Si3220DC0-EVB
Rev. 1.2 4/03
Copyright © 2003 by Silicon Laboratories
Si3220PPT-EVB-12
Si3220PPT-EVB
PCLK and FS signals. The DIP switch (S2) sets the
PCLK frequency and controls the FS enable. See
Table 1 for S2 settings. JP3 and JP4 select this internal
clock source or an external PCM clock source. The
ProSLIC motherboard has been designed to directly
connect to an Audio Precision SIA-2322 Serial Interface
Adapter through the 15 pin d-connectors P2 and P3.
See Table 2 for the Audio Precision settings. The
ProSLIC evaluation board has also been designed to
interface with a Wandel and Goltermann PCM-4 through
ProSLIC LINC Evaluation Software
The ProSLIC LINC software is an executable program
that allows control and monitoring of the ProSLIC. It
utilizes the primary LPT port of a standard PC to
communicate to the ProSLIC’s SPI port.
To install the software, insert the Silicon Laboratories
ProSLIC CD into the computer. The setup routine can
be invoked by running the setup.exe program in the root
directory of the CD.
Invoking the ProSLIC LINC is achieved by double J8, J9, J10, and J11. See Table 3 for PCM-4 settings. A
clicking the ProSLIC LINC icon. Refer to the ProSLIC header, J5, allows access to the ProSLIC’s PCM signals
LINC User Guide for software operation.
for connection to other PCM testing devices or an actual
telephone system PCM bus. TIP and RING of the
two-wire analog interface is present at the RJ-11
connectors, J1 and J11 of the Dual ProSLIC daughter
card.
The schematics of the ProSLIC motherboard are found
in Figures 8, 9, and 10. Figure 8 shows the connections
from the motherboard to the daughter card. Figure 9
illustrates the LPT port connection to the SPI drivers.
The PCM highway and LED indicators are shown in
Figure 10.
The ProSLIC evaluation board is voltage programmable
with specific jumper settings. JP1 selects 3 V or 5 V
ProSLIC operation. JP2 selects 3 V or 5 V PCM source
level compatibility. These should be placed on the
expected setting.
Power is connected to the ProSLIC at J2, J3 and J4.
The 5 V is always required for the buffers, U2 and U3, to
interface to the parallel port. The ProSLIC can be
powered from 5 V or 3 V with the placement of a jumper
on JP1. The Protection Return connections on J6
should be connected to an appropriate ground for
TIP/RING fault testing. This return is tied to signal
ground on-board though it has a dedicated trace for
high current conditions. Serial control of the ProSLIC is
achieved by toggling select bits of a standard parallel
port. The parallel port connection is available at P1 and
J1.
Si3220PPT-EVB Dual ProSLIC Evaluation
Board Description
The schematics for the Dual ProSLIC evaluation
daughter card are shown in Figures 1 through 4. The
schematic in Figure 1 shows the Dual ProSLIC linecard
implementation. All circuitry pertaining to the telephony
function of the Dual ProSLIC is found here. Figure 2
contains a number of options for secondary fault
protection. Secondary protection components can be
selected for a given level of protection against expected
faults. Figure 3 is the schematic that describes the serial
control interface, PCM interface, daisy chain ports, and
power supply filtering and connections. These
schematics represent typical linefeed components for
the ProSLIC. Figure 4 is the circuit for an optional third
battery switch. This circuit should be installed for testing
with medium length loops where VBATL and VBATH
may be used as off-hook batteries and VBATR is
maximized for ringing. Follow the instructions on this
schematic page to change the hardware. To change the
battery switch logic to use the ringing battery, perform
the following steps in the LINC software:
1. Click “User Mode” on.
2. Write RLYCON=0x3B.
3. Click “User Mode” off.
The layout of the Dual ProSLIC evaluation daughter
card is found in Figures 5, 6, and 7. Figure 5 shows the
component placement while Figures 6 and 7 show the
two layers of component interconnect. For optimum
thermal performance of the Si3200, the daughter card
has inner VDD and GND layers. These layers are
omitted from the figures in this data sheet. The signal
flow is digital PCM on the left to two-wire analog on the
right.
Multiple dual ProSLIC cards can be daisy-chained by
stacking the cards. Stack up to eight cards by aligning
JS1–JS5 and pressing together. The ProSLIC LINC
Software allows channel selection for RAM and register
manipulation.
Signal requirements for ProSLIC operation are PCLK
(PCM clock), FS (frame sync), and Serial IO. The
ProSLIC motherboard has a local oscillator with a
programmable logic device to provide the ProSLIC
2
Rev. 1.2
Si3220PPT-EVB
7. Turn the power supplies on and press the ProSLIC
Si3220PPT-EVB Dual ProSLIC Evaluation
Platform Setup
motherboard reset button (S1).
8. Click the “Reinitialize” button in the ProSLIC LINC software
panel.
To prepare the Dual ProSLIC evaluation platform for
use, perform the following steps:
1. Set power supplies to 3.3 V, 5 V, –24 V, and –75 V.
The Dual ProSLIC is now ready to perform its linecard
function.
2. With these supplies off, connect them to J2, J3, and J4
To achieve an end-to-end connection with 600 Ω:
1. Verify that R11 is shorted.
2. Click RESET.
3. Click REINITIALIZE.
4. Click REGISTER SET.
corresponding to the silk screen designators.
3. Connect the PC’s parallel port (LPT1) to P1 (or J1) using a
25 pin D male-to-male cable.
4. Select the on-board PCM clock source or select external
PCM source with JP3, JP4 and connect an Audio
Precision SIA-2322 to P2 and P3 or a Wandel and
Goltermann PCM-4 to J8, J9, J10, and J11.
5. Click Broadcast box.
6. Write “1” to LINEFEED register.
5. TIP/RING connection can be made from the RJ-11s to a
This connects the evaluation platform end-to-end per
phone or telephony test equipment.
daughter card RF-11 connector pairs.
6. Invoke the ProSLIC LINC software.
Table 1. On-Board PCLK Settings (S2)
S2-1,2,3
S2-4
S2-5
S2-6
S2-7
S2-8
PCLK frequency
unused unused unused unused
FS enable
0,0,0 = 8.192 MHz
0,0,1 = 4.096 MHz
0,1,0 = 2.048 MHz
0,1,1 = 1.024 MHz
1,x,x = 512 kHz
x
x
x
x
0 = FS disabled
1 = FS enabled
Note: 1 = on.
Table 2. Audio Precision SIA-2322 DIP Switch Setting
Receiver Mode
00000110 01111101
Note: 256 kHz PCLK and 8 kHz FS.
Transmitter Mode
00000110 01111101
10111001
01111001
1000001
01111001
Table 3. Wandel and Goltermann PCM-4 Settings
General Configuration
General Configuration
General Configuration
2.14
3.13
4.13
For µ-law add the following:
General Configuration
General Configuration
7.12
7.22
Rev. 1.2
3
TP1
VDD
J1
VDD
U2
Protection
TIPa_ext
Si3200
6
5
4
3
2
1
TIPa
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
TIPa
TIP
NC
ITIPP
ITIPN
RINGa
RINGa_ext RINGa
RING THERM
VBAT IRINGP
VBATH IRINGN
VBATL
GND
VDD
NC
NC
BATSEL
TP2
BATSWa
402k
RJ-11 SMD
C32
0.1u
100V
C30
0.1u
100V
R6
40.2k
BATSELa
VBATa
epad
GND
R2
C2
VBLO
VBATH
0.1u
100V
X7R
0.1u
100V
X7R
R4
R3
4.7k
4.7k
J2
C1
R1
1
2
TRD1a
TRD2a
GPOa
J3
402k
1
2
J4
U1
1
2
C3
10n
C4
10n
100V
100V
R5
806k
182
GPOa
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
GPOa
SVBATa
RPOa
RPIa
GPOa
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
TP5 TP6 TP7 TP8
/CS
/CS
SDITHRU
SDI
R8
R7
SDITHRU
SDI
SDO
RNIa
182
RNOa
CAPPa
CAPMa
QGND
IREF
CAPMb
CAPPb
RNOb
RNIb
SDO
C5
C6
SCLK
SCLK
VDD4
GND4
/INT
PCLK
GND3
VDD3
DTX
1u
6V
1u
6V
/INT
PCLK
R10
R17
40.2k
182
C15 C16
Si3220
1u
6V
1u
6V
DTX
DRX
FSYNC
/RESET
RPIb
RPOb
SVBATb
DRX
FSYNC
/RST
R18
R15
182
806k
C13
10n
100V
C14
10n
100V
R11
402k
J5
C11 0.1u
100V
X7R
C12 0.1u
100V
X7R
1
2
R13
R14
4.7k
4.7k
GPOb
GPOb
GPOb
J6
TP3
1
2
TRD2b
TRD1b
VDD
R12
402k
J7
J11
U3
1
2
Protection
Si3200
6
5
4
3
2
1
TIPb
1
2
3
4
5
6
7
8
16
TIPb_ext
TIPb
TIP
NC
ITIPP
ITIPN
15
14
13
12
11
10
9
RINGb
RINGb_ext RINGb
RING THERM
VBAT IRINGP
VBATH IRINGN
VBATL
GND
VDD
NC
NC
BATSEL
BATSWb
RJ-11 SMD
R16
40.2k
TP4
BATSELb
VBATb
C33
0.1u
100V
C31
0.1u
100V
epad
GND
VBLO
VBATH
Figure 1. Si3220DC-EVB Evaluation Circuit (1 of 4)
RF1
RF5
1
2
F1250T
TIPa_ext
TIPA
NI TS250-130-RA
Optional*
D3
NI
P0901SC
Optional*
RV1
TIP
U4
K1
G
NC
K2
1
2
3
6
5
4
NC
8
7
6
5
1
2
3
4
K1
A
A
K2
VREF GND
RING
NC
D4
NI
P0901SC
Optional*
C36
0.1u
100V
C37
0.1u
100V
TISP61089B
B1101UC
Optional*
RF6
VBPROT
RINGa_ext
RINGA
NI TS250-130-RA
Optional*
RF2
1
2
RF11
F1250T
1
2
F1250T
RF15
TIPb_ext
TIPB
NI TS250-130-RA
Optional*
D13
NI
Optional*
P0901SC
RV2
TIP
U5
K1
G
NC
K2
1
2
3
6
5
4
NC
8
7
6
5
1
2
3
4
K1
A
A
K2
VREF GND
RING
NC
D14
NI
Optional*
P0901SC
C38
0.1u
100V
C39
0.1u
100V
TISP61089B
B1101UC
Optional*
RF16
VBPROT
RINGb_ext
RINGB
NI TS250-130-RA
Optional*
RF12
1
2
F1250T
* Optional protection devices:
Battery tracking over voltage protection devices are required when using maximum battery voltage on Si3200.
Fixed voltage thyristor protection devices, D3, D4, D13, D14 can be used in certain cases. The selection of the thyristor
device voltage depends on the required battery voltage for ringing. The maximum clamp voltage for the device must be
under the Si3200 maximum voltage. The minimum clamping voltage of the device must be above the maximum battery
voltage. For example, the Teccor P0901SC is shown for applications that operate from a maximum negative battery of
-72V.
Over current devices should be selected for application requirements and over voltage protection device current limitations.
Figure 2. Si3220DC-EVB Evaluation Circuit (protection) (2 of 4)
JP2
SDO
/CS
SCLK
SDI
1
3
5
7
2
4
6
8
DTX
PCLK
FSYNC
DRX
JS1
JS2
9 10
JP1
AUX Cntl
CONN SOCKET 5x2
CONN SOCKET 2x2/SM
CONN HEADER 2x2/SM
(Farside)
SDITHRU
SDI
VDD
SDO
SCLK
/CS
JS4
JS3
2
4
6
8
10
1
3
5
7
9
9
7
5
3
1
10
8
6
4
2
2
4
6
8
10
1
3
5
7
9
9
7
5
3
1
10
8
6
4
2
/INT
PCLK
DRX
DTX
FSYNC
/RESET
VBRNG
CONN SOCKET 5x2
CONN SOCKET 5x2
VBLO
VBHI
JS5
1
2
3
4
5
CONN SOCKET 5x2
6
7
8
9
Thermal pad vias
VDD
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
C20
0.1u
C21
0.1u
C22
0.1u
C23
0.1u
C24
0.1u
C25
0.1u
VBLO
C34
0.1u
100V
C35
0.1u
100V
Figure 3. Si3220DC-EVB Evaluation Circuit (interconnect) (3 of 4)
For three battery operation:
D1
Q1 CXT5551
VBATa
a) Install the switch components for both channels
as described at left side of this schematic page.
b) Move zero Ohm resistor from R120 to R121
c) Move 40.2kOhm resistors from R6 and R16
and place them in R9 and R19.
NI DL4003
R103
VBHI
R102
10k
402k
CXT5401
Q2
R120
0
R121
NI
*
R101
NI
VBHI
VBRNG
D100
*
VDD
3V
R101/R111 2.4k
5V
3.9k
BATSELa
BATSELb
DL4003
VBATH
*
R111
NI
VBPROT
CXT5401
R9
Q3
BATSWa
BATSWb
GPOa
GPOb
NI
R112
10k
R19
R113
402k
D11
NI
VBATb
Q4 CXT5551
NI DL4003
VBHI
Figure 4. Si3220DC-EVB Evaluation Circuit Third Battery (4 of 4)
Si3220PPT-EVB
Bill of Materials
Table 4. Si3220DC0-EVB Application Circuit
Component(s)
C1, C2, C11, C12
C3, C4, C13, C14
C5, C15
Value
Function
100 nF, 100 V, X7R, ±20%
10 nF, 100 V, X7R, ±20%
1 µF, 6.3 V, X7R, ±20%
Filter capacitors for TIP, RING ac sensing inputs.
TIP/RING compensation capacitors.
Low pass filter capacitors to stabilize common mode SLIC
feedback loops.
C6, C16
1 µF, 6.3 V, X7R, ±20%
Low pass filter capacitors to stabilize differential SLIC
feedback loops.
C30–C33
C20–C25
R1, R2, R11, R12
R3, R4, R13, R14
R5, R15
R6, R16
R7, R8, R17, R18
R10
0.1 µF, 100 V, Y5V
0.1 µF, 10 V, Y5V
Decoupling for battery voltage supply pins.
Decoupling for analog and digital chip supply pins.
Sense resistors for TIP and RING voltage sensing nodes.
Sense resistors for TIP, RING ac sensing inputs.
Sense resistor for battery voltage sensing nodes.
Sets bias current for battery switching circuit.
Bias resistors for internal transconductance amplifier.
Generates a high accuracy reference current.
402 kΩ, 1/10 W, ±1%
4.7 kΩ, 1/10 W, ±1%
806 kΩ, 1/10 W, ±1%
40.2 kΩ, 1/10 W, ±5%
182 Ω, 1/10 W, ±1%
40.2 kΩ, 1/10 W, ±1%
Table 5. Si3220DC0-EVB Protection Circuit
Component(s)
C36–C39
D3, D4,D13,D14*
RF1, RF2,RF11,RF12
RF5, RF6,RF15,RF16*
RV1,RV2,U4,U5
Description
0.1 µF, 100 V, Y5V
Teccor P0721SC transient voltage suppressor
Teccor F1250T, 250 V/1.25 A, TeleLink fuse
Raychem TS-250-130-RA resettable fuse
Function/Comments
Decoupling for B1101UC and TISP61089B.
Overvoltage protection (optional).
Overcurrent protection.
Overcurrent protection PTC (optional).
Battery-tracking overvoltage protection.
Teccor B1101UC Dual Negative BATTRAX
SLIC Protector or Bourns TISP61089B
*Note: Optional protection components not used on Si3232DC0-EVB. Usage depends on application.
8
Rev. 1.2
Figure 5. Si3220DC-EVB Silkscreen
Figure 6. Si3220DC-EVB Component Side
Figure 7. Si3220DC-EVB Solder Side
Power
LPT Port
JS1
JS2
JS3
9
7
5
3
1
10
8
6
4
2
9
7
5
3
1
10
8
6
4
2
CONN SOCKET 5x2
CONN SOCKET 2x2
SDI
DIN
TEST
SDO
SCLK
/CS
+VIN
VDD
CONN SOCKET 5x2
SPI
JS4
VBRNG
2
4
6
8
10
1
3
5
7
9
2
4
6
8
10
1
3
5
7
9
External PCM
/INT
VRNGSOURCE
DOUT
JS3
PCLK
DRX
DTX
FSYNC
/RESET
PCM
CONN SOCKET 5x2
VBLO
VBHI
ProSLIC Motherboard
JS5
CONN SOCKET 5x2
Figure 8. ProSLIC Motherboard (ProSLIC IF)
VDD
+5V
R1
R2
R3
U1
200k
200k
S1 Reset
Push Button
13
14
15
16
17
18
19
20
21
22
23
24
12
11
10
9
8
7
6
5
4
3
GND
B8
B7
B6
B5
B4
B3
B2
GND
GND
A8
A7
A6
A5
A4
A3
A2
P1
/RESET
TEST
/CS
SDI
DIN
/RESET
TEST
/CS
SDI
DIN
/RST
/STROBE
/AUTOFD
D0
ERROR
D1
INIT
D2
/SELECT
D3
1
14
2
15
3
16
4
17
5
18
6
19
7
20
8
21
9
22
10
23
11
24
12
25
13
TP D6
TP D5
/CS_IN
SDI_IN
SCLK_IN
OUT_EN
DIN
SCLK
SCLK
B1
OEB
VCCB
VCCB
A1
DIR
VCCA
R6
470
2
1
VDD
D4
C1
100 pF
C2
4245A
0.1 uF
6Vmin
D5
D5
Two Package Widths
R7 NI
D6
D6
D7
J1
R4
R5
TEST_IN
D7
10k
10k
/ACK
BUSY
PAPEREND
SELECT
1
3
5
7
2
4
6
U2
13
14
15
16
17
18
19
20
21
22
23
24
12
11
10
9
8
7
6
5
4
3
GND
B8
B7
B6
B5
B4
B3
B2
B1
GND
GND
A8
A7
A6
A5
A4
A3
A2
8
9
10
12
14
16
18
20
22
24
26
11
13
15
17
19
21
23
25
DTX
DTX
DOUT
SDO
/INT
DB25F
Parallel port
DOUT
SDO
/INT
TEST
TEST
OEB
VCCB
VCCB
A1
DIR
VCCA
2
1
HEADER 13X2
Parallel Port Hdr
4245A
SPARE DIGITAL OUT
SDO_OUT
/INT_OUT
Two Package Widths
SDO_OUT
TEST _OUT
CON3
CON3
CON3
+VIN
J2
J3
J4
+5V
VDD
+3V
+5V
VBRNG
VBHI
VBLO
C3
C4
C5
C6
C7
C8
C9
C10
C11
+5V
VDD +3V
L1
L2
CON3
CON3
0.1 uF
6Vmin
0.1 uF
6Vmin
0.1 uF
6Vmin
0.1 uF
6Vmin
0.1 uF
6Vmin
0.1 uF
6Vmin
0.1 uF
6Vmin
0.1 uF
6Vmin
0.1 uF
6Vmin
JP1
3
1
1
3
2
2
J5
J6
1
2
3
1-2 : 3V operation
2-3 : 5V operation
EMI Filt
EMI Filt
D1
C12
C13
C14
D2
Zener
6.8V
0.1 uF
6Vmin
100uF
10Vmin
100uF
10Vmin
Zener
6.8V
3V or 5V oper
Component Power Selection
VRNGSOURCE
Single point connection
to ground plane
Ringing Source Input
Figure 9. ProSLIC Motherboard (LPT to SPI)
VDD
+5V
+5V
+5V +3V
PCM bus
1
PCMVDD
1-2 : 3V
2
3
R8
R9
2-3 : 5V
330
330
JP2
C15
0.1 uF
6Vmin
D3
D4
+5V
DB15F
To Audio Prec TX
P2
U5
1
4
8
5
OE VDD
U3
13
GND
12
11
10
9
8
7
6
5
4
3
GNDOUT
GND
GND
A8
A7
A6
A5
A4
A3
A2
14
15
16
17
18
19
20
21
22
23
24
B8
B7
B6
B5
B4
B3
B2
B1
INTFSYNC
32.768MHz
U6
FPGA
PLCC-44
/RESET
EXTDRX
EXTFSYNC
JP6
DRX
FSYNC
PCLK
EXTDRX
INTDRX
EXTDTX
15
16
17
18
19
20
21
22
25
26
27
28
29
30
31
32
37
38
39
40
41
42
43
44
3
4
5
6
7
10
8
6
4
2
9
7
5
3
1
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
1
1-2: Int
2
FS
EXTDRX
EXTPCLK
EXTDTX
2-3: Ext
3
A1
DIR
VCCA
OEB
VCCB
VCCB
INTDTX
2
1
EXTFSYNC
INTFSYNC
EXTPCLK
INTPCLK
JP3
NI
4245A
Two Package Widths
R11 NI
EXTFSYNC
INTPCLK
S2 DIP Switch
JP5
S1
S2
S3
S4
S5
S6
S7
S8
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
I/O8
I/O9
1
3
5
7
2
4
6
8
To ProSLICs
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
DTX/DRX loopback
U4
9
10
8
9
10
DB15M
To Audio Prec RX
P3
NI
1
2
1-2: Int
PCK
12
11
10
9
8
7
6
5
4
3
13
14
15
16
17
18
19
20
21
22
23
24
2-3: Ext
3
GND
GND
A8
A7
A6
A5
A4
A3
A2
GND
B8
B7
B6
B5
B4
B3
B2
B1
CLK
11
35
33
24
/CS
SCLK
/INT
Y0
Y1/RESET
Y2/SCLK
SDO/IN1
/CS LED
JP4
1
2
3
4
5
6
7
8
SCLK LED
/INT LED
SDO LED
SDI LED
} LED drive
SDO_OUT
SDI
EXTPCLK
J8
J9
13
14
36
2
ispEN
SDI/IN0
MODE/IN2
GOE0/IN3
Omit Pin 5
EXTDRX
EXTFSYNC
DTX
EXTDTX
+5V
A1
DIR
VCCA
OEB
VCCB
VCCB
2
1
J7
HEADER 8X1
D7
TEST_IN
4245A
Two Package Widths
D7
C16
J13
NI
EXTPCLK
EXTDTX
C17
R10
10k
0.1 uF
6Vmin
0.01 uF
6Vmin
J10
J11
External PCM
On-board PCM Clocks
Figure 10. ProSLIC Motherboard (PCM)
Si3220PPT-EVB
Document Change List
Revision 1.1 to Revision 1.2
Figure 2 updated.
Tables 4 and 5 added.
Rev. 1.2
15
Si3220PPT-EVB
Contact Information
Silicon Laboratories Inc.
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Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Email: productinfo@silabs.com
Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
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16
Rev. 1.2
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