SI3462-E01-GMR_技术文档

Si3462

SINGLE-PORT IEEE 802.3AT POE/POE+ PSE INTERFACE

Features

Pin Assignments

Short-circuit output fault



IEEE 802.3at^TMcompliant PSE

Autonomous operation requires no

host processor interface

Complete reference design

available, including Si3462 controller

and schematic:

protection

Si3462

GND

LED status signal (detect,

power good, output fault)

UNH Interoperability Test Lab

report available

Extended operating range

(–40 to +85 °C)



1

2

3

4

5

10

9

CLSMARK

DC1

STATUS

ISENSE

RST

Low-cost BOM

8

VDD

Compact PCB footprint

Operates directly from a +50 V

isolated supply

7

DC2

VSENSE

DETA

11-Pin Quad Flat No-Lead (QFN)

package

6

CLSMODE

Tiny 3x3 mm PCB footprint;

RoHS-compliant

Supports up to 30 W maximum

output power (Class 4)



No-classify modes force power

after valid detection

Eliminates 10 BOM

components

Robust 3-point detection algorithm

eliminates false detection events

IEEE-compliant disconnect

Inrush current control

11-pin QFN (3x3 mm)

Top View—Pads on bottom of package

Applications



IEEE 802.3at endpoints and

midspans

Environment A and B PSEs

Embedded PSEs



Set-top boxes

FTTH media converters

Cable modem and DSL gateways



Description

The Si3462 is a single-port power management controller for IEEE 802.3at-

compliant Power Sourcing Equipment (PSE). The Si3462 can be powered

from a 50 V input using a shunt regulator, or, to save power, it can be powered

from 50 V and 3.3 V power supplies. The IEEE-required Powered Device (PD)

detection feature uses a robust 3-point algorithm to avoid false detection

events. The Si3462's reference design kit also provides full IEEE-compliant

classification and PD disconnect. Intelligent protection circuitry includes input

under-voltage lockout (UVLO), classification-based current limiting, and output

short-circuit protection. The Si3462 is designed to operate completely

independently of host processor control. An LED status signal is provided to

indicate the port status, including detection, power good, and output fault

event information. The Si3462 is pin-programmable to support four available

power levels, endpoint and mid-span applications, and auto-retry or restart

after disconnect functions. A comprehensive reference design kit is available

(Si3462-EVB), including a complete schematic and bill of materials. The

Si3462 also features “no-classify” modes, for circumstances where detection

is desired but classification steps can be skipped. Example applications

include dedicated, point-to-point connections for IP cameras, point-of-sale

terminals, and wireless access points where the application power

requirements are well understood. These modes allow elimination of

classification-related components from the bill of materials.

Rev. 1.0 11/11

Si3462

2

Rev. 1.0

Si3462

TABLE OF CONTENTS

Section

Page

1. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2. Si3462 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

2.1. Si3462-EVB Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

2.2. PSE Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

3. Typical Si3462-EVB Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

4. Si3462-EVB Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

4.1. Reset State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

4.2. Operating Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

5. Operating Mode Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

5.1. Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

5.2. Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

5.3. Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

5.4. Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

5.5. Disconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

5.6. UVLO and OVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

5.7. Status LED Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

6. Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

6.1. Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

6.2. External Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

6.3. Input DC Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

7. Si3462 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

9. Package Outline: 11-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

10. Solder Paste Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

10.1. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

11. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

11.1. Si3462 Top Marking (QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

11.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Rev. 1.0

3

Si3462

1. Typical Application Schematic

+50V

V_IN

+

+50V

Optional 3.3V regulator

V_DD

+3.3V

Detect

&

Mark

V_OUT

48 V

VDD

CLSMARK

DC1

DC2

CLSMODE

Classification

(Optional)

and

PSE

output

(to port

Gate drive

Si3462

DETA

VSENSE

RST

magnetics)

ISENSE

STATUS

DETECT

FAULT

GND

PGOOD

GND

-

GND

Note: Refer to the Si3462-EVB User Guide for complete schematic details

Figure 1. Si3462 Typical Application Schematic

4

Rev. 1.0

Si3462

2. Electrical Specifications

The following specifications apply to the Si3462 controller. Refer to Tables 3 and 6 and the Si3462-EVB User's

Guide and schematics for additional details about the electrical specifications of the Si3462-EVB reference design.

Table 1. Recommended Operating Conditions

Symbol

Test Conditions

Min

Typ

Max

Unit

Description

T

–40

—

25

75

+85

—

°C

Operating Temperature Range

Thermal Impedance

A



No airflow

°C/W

JA

During all operating modes

(detect, classification, disconnect)

VDD

2.7

3.3

3.6

V

VDD Input Supply Voltage

Table 2. Electrical Characteristics*

Symbol

Test Conditions

Min

Typ

Max

Unit

Description

Digital Pins: CLSMARK, DC1, DC2, CLSMODE, STATUS (Output mode), RST

I

= –3 mA

= –10 µA

0.7 x VDD

VDD – 0.1

—

OH

V

Output High Voltage

Output Low Voltage

OH

I

OH

I

= 8.5 mA

= 10 µA

—

0.6

0.1

OL

V

OL

I

OL

V

Any digital pin

0.7 x VDD

V

Input High Voltage

Input Low Voltage

Input Leakage Current

IH

V

I

—

0.6

—

IL

V

= 0 V

IN

±1

µA

IL

Analog Pins: ISENSE, VSENSE, DETA, STATUS (Input mode)

—

5

—

pF

µA

Input Capacitance

I

±1

Input Leakage Current

IL

*Note: VDD = 2.7 to 3.6 V, –40 to +85 °C unless otherwise specified.

Rev. 1.0

5

Si3462

2.1. Si3462-EVB Performance Characteristics

When implemented according to the recommended external component and layout guidelines for the Si3462-EVB,

the Si3462 enables the following performance specifications in single-port PSE applications. Refer to the Si3462-

EVB User's Guide and schematics for details.

Table 3. Selected Electrical Specifications (Si3462-EVB)

Typ¹

Symbol

Test Conditions

Min

Max

Unit

Description

Power Supplies

V

Input Supply

V

–40 to +85 °C

ambient range

45

—

50

42

60

3.3

49

57

45

V

IN

Range

V

Input UVLO

UVLO

OVLO

UVLO turn-off

IN

Voltage

voltage at V

IN

V

Input OVLO

OVLO turn-off

voltage at V

57

—

IN

Voltage

IN

VDD Supply Voltage

Range

V

Si3462 supply

voltage range

3.15

—

3.45

—

DD

Output Supply

Voltage

V

PSE output

OUT

voltage at V = 50 V and

IN

I

= 350 mA

OUT

Supply Current

I

Current into the V node

(not including shunt regulator)

—

8.0

10.5

—

mA

V

IN

DD

Detection Specifications

Detection Voltage

V

Detection point 1

Detection point 2

Detection point 3

4.0

8.0

4.0

DET

Detection Current

I

Short circuit

—

3

mA

DET

Minimum Signature

Resistance

R

15

17

19

k

DETmin

Maximum Signature

Resistance

26.5

29

33

k

DETmax

Classification Specifications⁵

Classification Voltage

V

I

0 mA < I

< 45 mA

15.5

55

—

20.5

95

V

CLASS

Classification Cur-

rent Limit

Measured with 100 

across V

75

mA

CLASS

OUT

Notes:

1. Typical specifications are based on an ambient operating temperature of 25 °C and VIN = +50 V unless otherwise

specified.

2. Absolute classification current limits are configurable. See “5.2. Classification” and "5.3. Power-Up" on page 14.

3. Typical ICUT values are adjusted according to the input voltage to provide power limiting with approximately 5% margin

against the 802.3 requirements. The maximum ICUT values are consistent with the IEEE requirement that Icut

maximum is less than 400 mA at the minimum allowed Vout of 44 V or 684 mA for PoE+ mode at the minimum allowed

Vout of 50 V.

4. Overload current is within limits, typically in less than 1 ms.

5. Classification is optional in some operating modes. Refer to Table 6 for operating modes.

6. Classification Mark is only required for Type 2/Class 4 support

6

Rev. 1.0

Si3462

Table 3. Selected Electrical Specifications (Si3462-EVB) (Continued)

Typ¹

—

Symbol

Test Conditions

Min

Max

Unit

Description

Classification

Current Region

I

_

Class 0

Class 1

Class 2

Class 3

Class 4

0

8

5

mA

V

CLASS REGION

—

13

21

31

45

10

9

16

25

35

7

—

6

Mark Voltage

V

8.5

—

MARK

6

Mark Current

I

Short circuit

—

mA

MARK_LIM

Protection and Current Control

Overload Current

Threshold

I

Class 0 and

Class 4 PoE

15,400/V

16,170/V

17,600/V

mA

CUT

OUT

2,3

Class 1

4,000/V

7,000/V

4,200/V

7,350/V

4,600/V

8,000/V

mA

OUT

Class 2

OUT

Class 3

15,400/V

30,000/V

400

16,170/V

31,500/V

425

17,600/V

34,200/V

450

OUT

Class 4 PoE+

Overload Current

Limit

I

Class 0/1/2/3 and Class 4

LIM

4

PoE; Output = 100  across

V

OUT

I

PoE+

684

50

750

60

825

75

mA

ms

Class 4 PoE+; Output = 50 

across V

LIM

OUT

Overload Time

T

Class 0/1/2/3 and Class 4

LIM

PoE; Output = 100  across

V

OUT

Class 4 PoE+;

Output = 50  across V

14

5

17

20

10

ms

OUT

Disconnect Current

I

Disconnect current

7.5

mA

MIN

Efficiency

—

System Efficiency

(P @ V ) to

93

%



IN

(P

@ V

)

OUT

Notes:

1. Typical specifications are based on an ambient operating temperature of 25 °C and VIN = +50 V unless otherwise

specified.

2. Absolute classification current limits are configurable. See “5.2. Classification” and "5.3. Power-Up" on page 14.

3. Typical ICUT values are adjusted according to the input voltage to provide power limiting with approximately 5% margin

against the 802.3 requirements. The maximum ICUT values are consistent with the IEEE requirement that Icut

maximum is less than 400 mA at the minimum allowed Vout of 44 V or 684 mA for PoE+ mode at the minimum allowed

Vout of 50 V.

4. Overload current is within limits, typically in less than 1 ms.

5. Classification is optional in some operating modes. Refer to Table 6 for operating modes.

6. Classification Mark is only required for Type 2/Class 4 support

Rev. 1.0

7

Si3462

Table 4. Thermal Characteristics

Symbol

Test Conditions

Min

Typ

Max

Unit

Description



No airflow

—

75

—

°C/W

°C

Thermal Impedance

Junction Temperature

JA

TJ

–40

125

Table 5. Absolute Maximum Ratings*

Parameter

Conditions

Max Rating

Unit

–55 to +125

–65 to +150

–0.3 to 5.8

–0.3 to 4.2

°C

V

Ambient Temperature Under Bias

Storage Temperature

VDD > 2.2 V

Voltage on RST or any I/O pin with respect to GND

Voltage on VDD with respect to GND

V

Maximum Total Current through VDD

and GND

500

100

mA

Maximum Output Current into CLSMARK, DC1,

DC2, CLSMODE, STATUS, ISENSE, RST,

VSENSE, DETA (any I/O pin)

Human Body Model

–2 kV to +2 kV

260

V

ESD Tolerance

Soldering, 10 seconds maximum

°C

Lead Temperature

*Note: Stresses above those listed in this table may cause permanent device damage. This is a stress rating only, and

functional operation of the devices at these or any conditions above those indicated in the operational listings of this

specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

8

Rev. 1.0

Si3462

2.2. PSE Timing Characteristics

When implemented in accordance with the recommended external components and layout guidelines, the Si3462

controller enables the following typical performance characteristics in single-port PSE applications. Refer to the

Si3462-EVB applications note, schematics, and user's guide for more details.

Table 6. PSE Timing

Description

Symbol

Test Conditions

Min

Typ

Max

Unit

—

Endpoint Detection

Delay Cycle

Time from PD connection to port to

completion of detection process.

t

90

—

460

—

ms

DET_CYCLE

Detection Time

Time required to measure PD

signature resistance.

t

90

60

ms

DETECT

—

Classification Delay

Cycle

Class 0/1/2/3;

Time from successful detect mode

to classification complete.

t

CLASS_CYCLE

Class 4, two event classification;

Time from successful detect mode

to classification complete.

99

ms

—

Classification Time

Class 0/1/2/3 and Class 4 PoE;

Class 4 PoE+

30

69

ms

t

CLASS

Power-Up Turn-On

Delay

Class 0/1/2/3 and Class 4 PoE;

Time from when a valid detection is

76

ms

completed until V

power is

OUT

applied

t

PWRUP

—

Class 4 PoE+;

Time from when a valid detection is

112

ms

s

completed until V

power is

OUT

applied

—

Midspan Detect Back-

off Time

t

2.0

BOM

Error Delay Time

Time from error to restart of detec-

tion in auto-restart mode.

T

2.0

—

s

ed

—

Disconnect Delay

350

ms

t

DC_DIS

Note: These typical specifications are based on an ambient operating temperature of 25 °C and V = +50 V.

IN

Rev. 1.0

9

Si3462

3. Typical Si3462-EVB Waveforms

Note: Voltages are negative going with respect to the positive input.

Powering a PoE+ Device

Powering a PoE Device

Detection Time

Ch1: PoE output voltage referenced to the +50V rail

Mark Pulse

Detection

g

Two event classification

Classification

T_DETECT

Power-on

Classification and Power-up

Delay PoE+

Classification and Power-up

Delay PoE

Midspan Backoff after bad

Classification result

Ch1: PoE output voltage referenced to the +50V rail

Detection

t_{CLASS_CYCLE}

t_BOM

Classification

t_PWRUP

Classification

t_PWRUP

PoE+ Current Limit Response

PoE Current Limit Response

Overload During Classification

t_LIM

PoE+

PoE

Figure 2. Typical Si3462-EVB Waveforms

10

Rev. 1.0

Si3462

4. Si3462-EVB Functional Description

In combination with low-cost external components, the Si3462 controller provides a complete PSE solution for

embedded PoE applications. The Si3462-EVB reference design operates from a +50 V isolated power supply and

delivers power to the powered device.

Refer to the Si3462-EVB User's Guide and schematics for descriptions in the following sections.

The basic sequence of applying power is shown in Figure 3. Following is the description of the function that must

be performed in each phase.

Ch1: PoE output voltage referenced to the +50V rail

-2.8V

-10V

Detection

-15.5V

-20.5V

Classification

-44V

Power-on

-57V

t_{CLASS_CYCLE}

t_PWRUP

t_{DET_CYCLE}

Figure 3. Basic Power-up Sequence

Rev. 1.0

11

Si3462

4.1. Reset State

At power-up or if reset is held low, the Si3462 is in an inactive state with the pass FET Q4 off.

4.2. Operating Mode Configuration

At power-up, the Si3462 reads the voltage on the STATUS pin, which is set by a DIP switch and a resistor network.

The STATUS pin voltage level configures all of the Si3462's operating modes as summarized in Table 7.

Table 7. Operating Modes^1,2,3,4,5

Status Pin Voltage

(V)

Operating Mode

PSE

Type

Midspan/

Endpoint

Restart Action on Available Classification Classification

5

Fault or Overload

Event Condition

Power

30 W

7 W

BOM

Mark BOM

< 0.122

2

1

2

Midspan

Restart after

disconnection

No

0.122 to 0.338

0.338 to 0.548

0.548 to 0.756

Restart after

Yes

No

disconnection

Restart after

disconnection

15.4 W

30 W

Restart after

Yes

disconnection

0.756 to 0.961

0.961 to 1.162

1.162 to 1.366

1.366 to 1.575

1.575 to 1.784

2

1

2

Midspan

Endpoint

Auto restart after 2 s

30 W

7 W

No

Yes

No

Yes

No

15.4 W

30 W

Yes

No

Restart after

disconnection

1.784 to 1.990

1.990 to 2.196

2.196 to 2.407

Notes:

1

2

Endpoint

Restart after

disconnection

7 W

15.4 W

30 W

Yes

No

Restart after

disconnection

Restart after

disconnection

Yes

1. After power-up, the STATUS pin drives the base of an NPN transistor that controls an LED.

2. There is a trade-off in selecting the mode setting resistor values between voltage step accuracy and additional worst-

case supply current. For high-value resistors, the base current will alter the voltage steps while low-value resistors may

place higher load on the STATUS pin while driving the LED. The suggested resulting parallel resistance used by the

Si3462-EVB is 2.0 k.

3. Each mode setting resistor should be connected either to GND or +3.3 V through the DIP switch. Care should be taken

not to short the +3.3 V supply to GND.

4. A reset is required after a DIP switch position change for the new mode to take effect.

5. Refer to the Si3462-EVB User Guide to understand the components required to support Classification and Mark.

12

Rev. 1.0

Si3462

Table 7. Operating Modes^1,2,3,4,5(Continued)

Operating Mode

Status Pin Voltage

(V)

PSE

Type

Midspan/

Endpoint

Restart Action on Available Classification Classification

5

Fault or Overload

Event Condition

Power

BOM

Mark BOM

2.407 to 2.618

2.618 to 2.838

2.838 to 3.044

>3.044

2

1

2

Endpoint

Auto restart after 2 s

30 W

7 W

No

Yes

No

15.4 W

30 W

No

Yes

Notes:

1. After power-up, the STATUS pin drives the base of an NPN transistor that controls an LED.

2. There is a trade-off in selecting the mode setting resistor values between voltage step accuracy and additional worst-

case supply current. For high-value resistors, the base current will alter the voltage steps while low-value resistors may

place higher load on the STATUS pin while driving the LED. The suggested resulting parallel resistance used by the

Si3462-EVB is 2.0 k.

3. Each mode setting resistor should be connected either to GND or +3.3 V through the DIP switch. Care should be taken

not to short the +3.3 V supply to GND.

4. A reset is required after a DIP switch position change for the new mode to take effect.

5. Refer to the Si3462-EVB User Guide to understand the components required to support Classification and Mark.

Rev. 1.0

13

Si3462

5. Operating Mode Sequencing

5.1. Detection

After power-up the Si3462 enters the detection state with the pass FET off. Prior to turning the FET on, a valid

detection sequence must take place.

According to the IEEE specifications, the detection process consists of sensing a nominal 25 k signature

resistance in parallel with up to 0.15 µF of capacitance. To eliminate the possibility of false detection events, the

Si3462-EVB reference design performs a robust 3-point detection sequence by varying the voltage across the load

that connects to the +50 V supply rail and returns to GND via D3, Q14, R26, and R37. R37 serves as a current

sensing resistor, and the Si3462 monitors the voltage drop across it during the detection process.

At the beginning of the detection sequence, V

is at zero; then, it is varied from 4 to 8 V and then back to 4 V for

OUT

20+20+50 ms at each respective level. If the PD's signature resistance is in the RGOOD range of 17 to 29 k, the

Si3462 proceeds to classification and power-up. If the PD resistance is not in this range, the detection sequence

repeats continuously.

Detection is sequenced approximately every 400 ms for endspan and 2.2 seconds for midspan configurations and

repeats until RGOOD is sensed, indicating a valid PD has been detected. The STATUS LED (D2) is flashed at a

rate of about 1.5 Hz to indicate the PSE is searching for a valid PD.

5.2. Classification

After a valid PD is detected, the PSE interrogates the PD to find its power requirement. This procedure is called

classification and may be carried out in different ways. The Si3462 implements the one-event classification for

Type1 PDs and the two-event classification for Type2 PDs.

For one-event classification, the pass FET Q4 is turned on and programmed for an output voltage of 18 V with a

current limit of 75 mA for 30 ms. For the two-event classification, the 18 V pulse is output twice with an 8.5 V

amplitude mark pulse for 10 ms between the two classification pulses. The current measured at the ISENSE input

during the classification process determines the class level of the PD (refer to Table 3 on page 6 for current

ranges).

If the Si3462-EVB has 30 W of available power, it attempts to classify a Type2 PD first by the two-event method. If

the detected class is other than Class 4 or there is less than 30 W of power available, the Si3462 tries to classify a

Type1 PD using the one-event method.

If the class level of the PD is not within the supported range as set by the initial voltage on the Si3462's STATUS

pin (refer to the Operating Mode Configuration section above), an error is declared, and the LED blinks rapidly at a

10 Hz rate. This is referred to as classification-based power denial. If the class level is in the supported range, the

Si3462 proceeds to power-up. This is referred to as classification-based power granting.

If the classification level is at a greater power than can be supported based on the voltage read by the STATUS pin

during start-up, an error condition is reported by flashing the LED at a 10 Hz rate for two seconds before the state

machine goes back to the detection cycle.

The Si3462 also features “no-classify” modes for circumstances where detection is desired but classification steps

can be skipped. Example applications include dedicated, point-to-point connections for IP cameras, point-of-sale

terminals, and wireless access points where the application power requirements are well understood. These

modes allow elimination of classification-related components from the bill of materials. Please refer to the Si3462-

EVB user guide for further details.

5.3. Power-Up

After successful classification, the pass FET is turned on with an initial current limit of 425 mA (for all PD classes),

and the respective ILIM values (indicated in Table 3) take effect after the FET is fully turned on. After power-up is

complete, power is applied to V

as long as there is not an overcurrent fault, disconnect, or input undervoltage

OUT

(UVLO) or overvoltage (OVLO) condition. The STATUS LED is continuously lit when power is applied.

If the output power exceeds the level of the power requested during classification, the Si3462 will declare an error

and shut down the port, flashing the LED rapidly to indicate the error. Depending on the initial voltage on the

STATUS pin, the Si3462 will wait either 2.2 seconds or until the PD has been disconnected before it enters the

detection phase again to look for a valid load.

14

Rev. 1.0

Si3462

5.4. Overload Protection

The Si3462 implements a two-level overload protection scheme. The output current is limited to ILIM, and the

output is shut down if the current exceeds ICUT for more than 60 ms. If current limitation persists for more than

15 ms in case of PoE+ Class 4 loads, the output is shut down to protect the pass FET. Current limit values are

dynamically set according to the power level granted during the classification process and the effective output

voltage (refer to Table 3 on page 6 for current limit values).

A special 425 mA current limit applies until the FET is fully turned on. If the FET does not fully turn on in the first

75 ms due to an overload condition, an error is declared. The maximum time that the 425 mA inrush current is

supplied is about 70 ms due to a 5 ms period to initially ramp the FET gate voltage.

The overload protection is implemented using a timer with a timeout set to 60 ms. If the output current exceeds the

I

threshold, the timer counts up; otherwise, if the output current drops below ICUT, the timer counts down

CUT

towards zero at 1/16th the rate. If the timer reaches the set timeout, an overcurrent fault is declared; the channel is

shut down (by turning off the external pass FET), and the status LED flashes rapidly at a rate of 10 Hz.

If the Si3462 was configured in the “automatic restart” mode during start-up, it will automatically resume the

detection process after 2.2 seconds. In the “restart after disconnect” mode of operation, the status LED will flash

rapidly, and the Si3462 will not resume detection until it senses a resistance higher than 150 k. This condition can

normally be achieved by removing the Ethernet cable from the Si3462-EVB's RJ-45 jack labeled “PoE”. Then, the

detection process begins; the status LED blinks at a rate of 1.5 Hz, and the Si3462 is allowed to go into

classification and power-up mode if a valid PD signature resistance is detected.

5.5. Disconnect

The Si3462 implements a robust disconnect algorithm. If the output current level drops below 7.5 mA typical for

more than 350 ms, the Si3462 declares a PD disconnect event, and the pass FET is turned off. The Si3462

automatically resumes the detection process after 500 ms.

5.6. UVLO and OVLO

The Si3462-EVB reference design is optimized for 50 V nominal input voltages (44 V minimum to 57 V maximum).

If the input voltage drops below 42 V, a UVLO condition is declared, which generates the error condition (LED

flashing rapidly). An undervoltage event is a fault condition reported through the status LED as a rapid blinking of

10 flashes per second. In the same way, if the input voltage exceeds 60 V, an OVLO condition is declared. In both

cases, the output is shut down.

The UVLO and OVLO conditions are continuously monitored in all operating states.

5.7. Status LED Function

During the normal detection sequence, the STATUS LED flashes at approximately 1.5 times per second as the

detection process continues. After successful power up, the LED glows continuously. If there is an error condition

(i.e., class level is beyond programmed value or a fault or over current condition has been detected), the LED

flashes rapidly at 10 times per second. This occurs for two seconds for normal error delay, and the detection

process will automatically start again after 2.2 s unless a “restart after disconnect condition” was set during the

initial configuration. Power will not be provided until an open circuit condition is detected. Once the Si3462-EVB

detects an open circuit condition, the LED blinks at 1.5 times per second.

If the Powered Device (PD) is disconnected so that a disconnect event occurs, the LED will start flashing at 1.5

times per second once the detect process resumes.

Rev. 1.0

15

Si3462

6. Design Considerations

6.1. Isolation

The Si3462-EVB's PSE output power at VOUT is not isolated from the input power source (VIN). Isolation of PSE

output power requires that the input be isolated from earth ground. Typically, an ac-to-dc power supply is used to

provide the 50 V power so the output of this supply is isolated from earth ground.

6.2. External Component Selection

Detailed notes on external component selection are provided in the Si3462-EVB User's Guide schematics and

BOM. In general, these recommendations must be followed closely to ensure output power stability, surge

protection (surge protection diode), and overall IEEE 802.3 compliance.

6.3. Input DC Supply

The Si3462-EVB reference design requires an isolated 50 V nominal dc input voltage (with a minimum of 44 V and

a maximum of 57 V).

The input power supply should be rated for at least 10% higher power level than the output power level chosen.

This is primarily to account for the losses in the current-sensing resistor, the pass FET, and the series protection

diode of the Si3462-EVB reference design. For example, to support a Class 0 PSE, the input supply should be

capable of supplying at least 16.94 W (15.4 W x 1.10 = 16.94 W).

The power supply also needs to be able to source 425 mA for 60 ms for normal operation or 885 mA for 15 ms for

high power (PoE+) operation.

The Si3462-EVB reference design does not regulate the output voltage during the power-on state; therefore, the

input dc supply should meet the ripple and noise specifications of the IEEE 802.3 standard.

The Si3462-EVB reference design includes an optional 3.3 V shunt regulator that uses the 50 V input to generate

the 3.3 V supply voltage for the Si3462 controller. Alternatively, an external 3.3 V power source may be used.

16

Rev. 1.0

Si3462

7. Pin Descriptions

Si3462 pin functionality is described in Table 8. Note that the information applies to the Si3462 device pins, while

the Si3462-EVB User's Guide describes the inputs and outputs of the evaluation system.

Refer to the complete Si3462-EVB schematics and BOM listing for information about the external components

needed for the complete PSE application circuit.

Si3462

1

2

3

4

5

10

9

CLSMARK

DC1

STATUS

ISENSE

RST

8

VDD

GND

7

DC2

VSENSE

DETA

6

CLSMODE

11-pin QFN (3x3 mm)

Top View—Pads on bottom of package

Table 8. Si3462 Pin Functionality

Pin #

Pin Name

Pin Type

Pin Function

Logic high on this output increases the current capability of the

detection circuitry while used for mark pulse generation. Refer to

the Si3462-EVB schematics. If classification mark is not utilized,

this signal is ignored.

1

CLSMARK

Digital output

This is a PWM output providing the dc control voltage for the

detection circuitry. It is also combined with the DC2 output in a

ratio of 1:256 to provide the gate control voltage of the pass FET.

2

DC1

Digital output

3

4

VDD

DC2

Power

3.3 V power supply input.

This is a PWM output that (combined with the DC1 output) pro-

vides the gate control voltage of the pass FET with high resolution.

Digital output

This is an open drain output. When high, it enables the feedback

path controlling the 18 V classification voltage. If classification is

not utilized, this signal is ignored.

5

6

CLSMODE

DETA

Digital output

Analog input

DETA is an analog input pin. During the detection process, the

DC1 pin duty cycle is varied to generate filtered dc voltages

across the load, and the voltage drop across a current sensing

resistor is measured through the DETA input.

7

8

VSENSE

RST

Analog input

Digital input

VSENSE is an analog input used for sensing the input dc voltage.

Active low reset input. When low, it places the Si3462 device into

an inactive state. When pulled high, the device begins the detec-

tion process sequence.

ISENSE is an analog input connected to a current sense resistor

for output current sensing.

9

ISENSE

Analog input

Rev. 1.0

17

Si3462

Table 8. Si3462 Pin Functionality (Continued)

Pin #

Pin Name

Pin Type

Analog in/Digital out

GND

Pin Function

At power-up, the voltage on this pin is sensed to configure the

PSE available power, mid span/end span timing mode and the

device's restart behavior when a fault condition is detected. Refer

to "4.2. Operating Mode Configuration" on page 12.

After reading the voltage present at this pin at power-up, the

STATUS pin becomes a digital output used to control an external

LED, which indicates when a detect, power good, or output fault

condition has occurred. Logic high turns the LED on, and logic low

turns the LED off. Refer to "5.7. Status LED Function" on page 15.

10

STATUS

GND

11

Ground connection for the Si3462.

18

Rev. 1.0

Si3462

8. Ordering Guide

Ordering Part Number

Description

Package

Information

Temperature Range

(Ambient)

Si3462-E01-GM

Single-port PSE controller

11-pin,

–40 to 85 °C

3 x 3 mm QFN.

RoHS compliant

Si3462-EVB

Si3462 evaluation board and reference

design kit

Evaluation board

N/A

Notes:

1. Add R to part number to denote tape-and-reel option (e.g., Si3462-E01-GMR).

2. The ordering part number above is not the same as the device mark. See "11. Top Marking" on page 23 for more

information.

Rev. 1.0

19

Si3462

9. Package Outline: 11-Pin QFN

Figure 4 illustrates the package details for the Si3462. Table 9 lists the values for the dimensions shown in the

illustration. The Si3462 is packaged in an industry-standard, 3x3 mm, RoHS-compliant, 11-pin QFN package.

Figure 4. QFN-11 Package Drawing

Table 9. Package Diagram Dimensions

Dimension

Min

0.80

0.03

Nom

0.90

Max

1.00

0.11

A

A1

A3

b

0.07

0.25 REF

0.25

0.18

1.30

0.30

1.40

D

3.00 BSC.

1.35

D2

e

0.50 BSC.

3.00 BSC.

2.25

E

E2

L

2.20

.45

—

2.30

.65

.55

aaa

bbb

ddd

eee

—

0.15

0.05

0.08

—

Notes:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to JEDEC outline MO-243, variation VEED except for

custom features D2, E2, and L which are toleranced per supplier designation.

4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C

specification for Small Body Components.

20

Rev. 1.0

Si3462

10. Solder Paste Mask

b

0.10 mm

0.50 mm

0.35 mm

LT

0.50 mm

0.30 mm

0.20 mm

0.35 mm

L

0.30 mm

0.20 mm

E2

0.70 mm

0.60 mm

0.20 mm

0.30 mm

k

e

E

Figure 5. Solder Paste Mask

Rev. 1.0

21

Si3462

10.1. PCB Land Pattern

b

0.10 mm

0.50 mm

0.35 mm

LT

0.30 mm

0.20 mm

L

E2

0.20 mm

0.30 mm

k

0.10 mm

e

E

Figure 6. Typical QFN-11 Land Diagram

22

Rev. 1.0

Si3462

11. Top Marking

11.1. Si3462 Top Marking (QFN)

6201

ETTT

YWW+

11.2. Top Marking Explanation

Line 1 Marking:

Pin 1 Identifier

Product ID

Circle = 0.25 mm Diameter

6201

62 = Si3462; 01 = Firmware Revision 01

Line 2 Marking:

Line 3 Marking:

ETTT = Trace Code

YWW = Date Code

Lead-Free Designator

Assembly trace code

E = Product revision

TTT = Assembly trace code

Assigned by the Assembly contractor.

Y = Last Digit of Current Year (ex: 2009 = 9)

WW = Current Work Week

+

Rev. 1.0

23

Smart.

Connected.

Energy-Friendly

Products

www.silabs.com/products

Quality

www.silabs.com/quality

Support and Community

community.silabs.com

Disclaimer

Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers

using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific

device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories

reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy

or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply

or express copyright licenses granted hereunder to design or fabricate any integrated circuits. The products must not be used within any Life Support System without the specific

written consent of Silicon Laboratories. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected

to result in significant personal injury or death. Silicon Laboratories products are generally not intended for military applications. Silicon Laboratories products shall under no

circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.

Trademark Information

Silicon Laboratories Inc., Silicon Laboratories, Silicon Labs, SiLabs and the Silicon Labs logo, CMEMS®, EFM, EFM32, EFR, Energy Micro, Energy Micro logo and combinations

thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZMac®, EZRadio®, EZRadioPRO®, DSPLL®, ISOmodem ®, Precision32®, ProSLIC®, SiPHY®,

USBXpress® and others are trademarks or registered trademarks of Silicon Laboratories Inc. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or registered trademarks of

ARM Holdings. Keil is a registered trademark of ARM Limited. All other products or brand names mentioned herein are trademarks of their respective holders.

Silicon Laboratories Inc.

400 West Cesar Chavez

Austin, TX 78701

USA

http://www.silabs.com


型号：	SI3462-E01-GMR
厂家：	SILICON
描述：	Telecom Circuit, 1-Func, QFN-11 电信电信集成电路
文件：	总24页 (文件大小：1493K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SI3462-E01-GMR [SILICON]

相关型号：

SI3464DV

SI3464DV-T1-GE3

SI3465DV

SI3465DV-T1-E3

SI3465DV-T1-GE3

SI3467DV

SI3467DV-T1-E3

SI3467DV_08

SI3469DV

SI3469DV-T1

SI3469DV-T1-E3

SI3469DV_08