SI3480-A01-GMR_技术文档

Si3480

Si3480 POWER MANAGEMENT CONTROLLER

Features

 Enables use of a smaller power  Pin programmable for overall

supply for a 4 or 8 port PoE

system

power supply capacity, port

power level, port priority, and

detection timing

 Self-contained solution operates

without the need for a host for

unmanaged operation

 LED indication of port status and

overall power consumption

No software required



20-pin Quad flat package

(4x4 mm)

4x4 mm PCB footprint; RoHS

compliant

No data isolation required

 Fully compliant with IEEE 802.3

clause 33 for Power over Ethernet

including the 802.3at amendment

for higher power (30 W category 2

ports)

Ordering Information:

See Ordering Guide on page 9.



Extended operating temperature

range (–40 to +85 °C)

Pin Assignments

(Top View)

Description

The Si3480 is a power manager intended for use with the Si3452 Power

over Ethernet (PoE) controller. The Si3480 enables the use of a smaller,

lower cost, and more efficiently-utilized power supply in an unmanaged

PoE Power Sourcing Equipment (PSE) system.

SDA

GND

VDD

RST

NC

1

2

3

4

5

15 PRIOCFG

14 ALTCFG

The Si3452 is capable of delivering over 30 W per port, which means that,

in a typical 8-port system, a 240 W power supply would have to be used

to avoid overload. Typically, not all ports are used at full power; so, a

smaller power supply in the range of 30 to 150 W can be used along with

the Si3480 power management controller.

13

12

11

LED8

LED7

LED6

The Si3480 power management controller is pin programmed. The pins

are used to set the power supply capacity, the number of low power

(category 1, 15.4 W), and high power (category 2, 30 W) ports, the port

priority, and the detection timing (Alternative A or Alternative B). The

Si3480 uses the real time overload and current monitoring capability of

the Si3452 to manage power for up to eight ports. Power management is

based on actual consumption rather than mere classification in order to

supply power to the greatest number of ports.

The Si3480 also provides LED drive to indicate port status and drive an

LED bar graph display to indicate the power supply capacity in use. If a

port is denied power due to power supply capacity limitations, the LED

indicators provide a simple and intuitive indication, helping a user

recognize and correct the overload situation by rebalancing loads or

adding mid-span power injectors to ports that would not otherwise be

powered. In case of a port overload, the port is easily re-enabled by

disconnecting the Powered Device (PD) and then reconnecting the PD

after correcting the overload situation.

Rev. 1.1 1/15

Si3480

Functional Block Diagram

Configuration Pins

Power Provided

Port Power

Port Priority

Detection Timing

Si3480

Power

Management

Controller

Si3452

PoE

Controllers

Power

Meter

LEDs

Port

Status

LEDs

2

Rev. 1.1

Si3480

TABLE OF CONTENTS

Section

Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

3.1. Device Initialization and Configuration Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

2

3.2. I C Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

3.3. LED Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

4. LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

4.1. Start-Up LED Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

4.2. Port Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

4.3. Power Meter LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

7. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

8. Landing Pattern: 20-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

9. Top Marking: 20-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Rev. 1.1

3

Si3480

1. Electrical Specifications

Table 1. Recommended Operating Conditions

Description

Symbol

Test Conditions

Min

Typ

Max

Units

Operating Temperature

Range

T

No airflow

–40

—

85

°C

A

V

Supply Voltage

V

All operating modes

2.7

—

3.6

—

V

DD

LED Current

I

LEDBANK pin at 50% duty cycle

20

mA

LED

Table 2. Absolute Maximum Ratings

Parameter

Conditions

Min

–55

–65

–0.3

—

Typ

—

Max

Units

°C

Ambient Temperature under Bias

Storage Temperature

125

150

5.8

—

°C

Voltage on any I/O with respect to GND

V

> 2.2 V

—

V

DD

Voltage on V with respect to GND

—

4.2

V

DD

Maximum Total LED Current

Maximum LED Current per Pin

—

500

100

mA

—

Note: Stresses above those listed under absolute maximum ratings may cause permanent damage to the

device. This is a stress rating only, and functional operation of the devices at those or any other conditions

above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating

conditions for extended periods may affect device reliability.

Table 3. Electrical Characteristics*

Description

Symbol

Test Conditions

Min

Typ

Max

Units

RST, SCL, SDA,

ALTCFG

Input High

V

2.0

—

V

IH

RST, SCL, SDA,

ALTCFG

Input Low

V

—

0.8

±1

V

µA

V

IL

RST, and all CFG pins

SCL and SDA high

Input Leakage Current

I

IL

Output Low

(LED pins, SCL and SDA)

I

= 8.5 mA

= 25 mA

—

1.0

0.6

—

OL

V

OL

Output High

(LED Pins)

I

= –3 mA

= –10 mA

—

–0.8

DD

V

–0.7

DD

—

OH

V

OH

I

V

OH

Sense Accuracy for Analog

Configuration Pins

∆V

Percent of V

–1.5

—

+1.5

%

SENSE

DD

VDD = 3.0 V

VDD = 3.6 V

—

10

13

I

mA

V

Current

DD

*Note: V_DD= 2.7 to 3.6 V, –40 to 85 °C unless otherwise noted.

4

Rev. 1.1

Si3480

2. Typical Application Schematic

- 5 2 V

+ 3 V 3

- 5 2 V _ R T N

+ 3 V 3 _ R T N

1 0 K R 1 0 3

1 K

R 1 0 2

R 1 0 1

- 5 2 V

- 5 2 V _ R T N

N

T T O B U S H P U S W

S W

1 0 K

R 1 0 0

1

L E D _ 4 _ 8

L E D _ 3 _ 7

L E D _ 2 _ 6

L E D _ 1 _ 5

B a n k

D

G N

2

V D D

3

+ 3 V

3

L E D _ 4 _ 8

L E D _ 3 _ 7

L E D _ 2 _ 6

L E D _ 1 _ 5

R 1 1 7

R 1 1 6

B a n k

R 1 1 3

R 1 1 5

R 1 1 2

R 1 1 4

Rev. 1.1

5

Si3480

3. Functional Description

3.1. Device Initialization and Configuration Pins

The Si3480 will discover Si3452 devices at addresses 0x20 and 0x21 at power up. If only one device is found, it

will manage the power for four ports. If two devices are found, the Si3480 will manage power for eight ports. For the

case of eight ports, ports 1–4 are associated with the Si3452 at address 0x20, and ports 5–8 are associated with

device 0x21. After power-up, the CFG pins are measured to determine how power is to be managed.

3.1.1. Pin PWRCFG

The voltage on pin PWRCFG specifies the power provided by the system power supply. The power provided is:

P

= 200 x V

/ V (Watts)

PWRCFG DD

PROVIDED

The total power provided is the rating of the main power supply for continuous output. The amount of total power

provided depends on the expected usage. 30 W of total power provided might be realistic for a four-port system

that only supports 15.4 W per port and is not expected to have PDs on all ports. 150 W of total power might be

realistic for an eight port system that supports 30 W per port and is expected to have category 2 PDs connected to

all ports.

To avoid overloads, a port will not be granted power unless the power consumed plus the power requested

according to classification (4, 7, 15.4, or 30 W) allows for 15% power supply reserve. If, due to variation in power

over time, the total power consumed by all the loads exceeds the power supply capacity, the power manager will

shut down ports in priority order.

3.1.2. Pin POECFG

The voltage on the POECFG pins determines how many ports are enabled for 30 W maximum per port. If the

voltage is at ground, no ports will be enabled for 30 W maximum. If the voltage is at V , all ports are enabled for

DD

30 W maximum. The number of ports enabled for 30 W is:

N = 8 x V

/ V rounded to the nearest integer

DD

POECFG

In a four-port system, V

> V / 2 means that 30 W is enabled on all ports.

DD

POECFG

If a port is enabled for 30 W maximum, special high-current Ethernet transformers should be used, and the user

should be aware that the wiring to the PD should be category 5E or better or category 5 manufactured after 1995

(See 802.3 clause 33 for details).

3.1.3. Pin PRIOCFG

The Si3452 implements a port priority set according to the voltage on pin PRIOCFG. Low priority ports may be

turned off if a high priority port is requesting power. Also, low-priority ports are shut down before high-priority ports

in case the power supply is overloaded. Similar to the POECFG pin, the number of ports that are high priority is:

N = 8 x V

/ V rounded to the nearest integer

DD

PRIORITYCFG

3.1.4. Pin ALTCFG

The Si3480 can be set to put the Si3452 parts in either Alternative A or Alternative B timing mode. Alternative A is

used when the power is applied to wire pairs 1,2 and 3,6. Alternative B is used when the power is applied to wire

pairs 4,5 and 7,8. Timing between detection pulses is less than 0.5 s for Alternative A and greater than two

seconds for Alternative B. The timing is Alternative A if pin ALTCFG is tied low and Alternative B if the pin is tied

high.

2

3.2. I C Communication

2

The open drain Si3480 pins (SDA, SCL, and INT) are for I C communication and connect to the Si3452/53 pins

with the same name. See the Si3452/53 data sheet for more detailed information.

3.3. LED Control

The LED pins each connect to two LEDs. The LED being driven is determined by the LEDBANK pin in a normal

multiplexing fashion. The LEDBANK pin is driven at 500 Hz (1 msec high and 1 ms low).

6

Rev. 1.1

Si3480

4. LEDs

Upon power application or reset (by SW1 in the upper left corner), the Si3480 probes to see whether there are one

or two Si3452 ICs connected (4 or 8 ports). The Si3480 then controls the LED display in the start-up sequence

described and automatically starts managing the power among the ports as determined by the configuration pins.

After start-up, the Si3480 controls the power meter and port status LEDs give a visual indication of the status.

4.1. Start-Up LED Sequence

During start-up, the LEDs are lit in the sequence listed in Table 4 (1 second for each step).

Table 4. LED Sequence

Step

Action

1

All LEDs on.

Port 1 LED and either four or eight power meter LEDs to indicate the number of 4-port controllers found by the

Si3480 (no LEDs if no controllers are found).

2

3

4

5

Port 2 LED and zero to eight power meter LEDs to indicate the provided power as determined by reading the volt-

age at the PWRCFG pin in 25 W steps (e.g. two LEDs is 50 W).

Port 3 LED and zero to eight power meter LEDs to indicate the number of PoE+ ports as determined by reading

the voltage at the POECFG pin.

Port 4 LED and zero to eight power meter LEDs to indicate the number of high-priority ports as determined by

reading the voltage at the PRIOCFG pin.

4.2. Port Status LEDs

After the start-up sequence, the port status LEDs display the patterns listed in Table 5 to indicate port status.

Table 5. Port LED Pattern Definitions

Port LED Pattern

Flashing once every two seconds

Continuously lit

Meaning

Detection and Classification in process

PoE port is on

Blinks off once every two seconds

Flashing five times per second

Flashing twice every two seconds

PoE+ port is on with a class 4 PD load (30 W granted)

Port overloaded

Power denied due to lack of power

For a port overload, an open circuit must be seen before the port is re-enabled; that is, the PD must be unplugged,

and the overload must be cleared.

Ports are turned off in priority order if more than the available power is being consumed. If the amount of power

consumed is >10% more than the available power, all low-priority ports are shut off immediately.

Ports are not granted power unless there is enough power available to grant the requested power (based on

classification) with 15% margin. The 15% margin generally avoids situations where a port is granted power and

then later turned off due to lack of power.

If a port is turned off or denied power due to a lack of available power, the LED continues flashing twice every two

seconds until enough power is available to turn the port on or the PD is unplugged.

4.3. Power Meter LEDs

The power meter LEDs light consecutively, indicating the amount of power that is being consumed. There are eight

LEDs in the power meter. The LEDs will light in bar graph fashion:

Number_LEDs_Lit = 8 x Total_Power_Consumed / (0.85 x Provided_Power – 4 W) (rounded down)

The eighth power meter LED is generally a red LED. If this LED is lit, it means that there is not enough power

available to grant even a Class 1 load power and maintain a 15% margin. The eighth LED is flashed five times per

second if the Si3452 controllers report a power supply undervoltage.

Rev. 1.1

7

Si3480

5. Pin Descriptions

SDA

GND

VDD

RST

NC

1

2

3

4

5

15 PRIOCFG

14 ALTCFG

13

12

11

LED8

LED7

LED6

Table 6. Si3480 Pin Descriptions

Pin # Pin Name

Pin Type

Pin Function

1

2

3

4

5

6

SDA

GND

VDD

RST

NC

Open Collector Connect to Si3452 SDA and pull-up resistor.

Power

Input

Ground.

VDD.

Reset (a low will reset the Si3480).

Do not connect to this pin.

NC

LED1

Output

7

LED2

Output

Pins LED1–LED4 work with Pin LEDBANK to drive the eight power

meter LEDs.

8

LED3

LED4

LED5

LED6

LED7

LED8

Output

9

10

11

12

13

Pins LED5 – LED8 work with Pin LEDBANK to drive the eight port status

LEDs.

Low is Alternative A timing, High is Alternative B timing. See "3.1.4. Pin

ALTCFG" on page 6.

14

15

16

ALTCFG

PRIOCFG

POECFG

Input

This pin sets the number of ports that are high priority. See "3.1.3. Pin

PRIOCFG" on page 6.

The pin sets the number of ports that are high power. See "3.1.2. Pin

POECFG" on page 6.

17

18

19

20

PWRCFG

LEDBANK

INT

Input

Output

Input

This pin sets the power provided. See "3.1.1. Pin PWRCFG" on page 6.

This pin determines which LED bank is being turned on.

Connect to Si3452 INT and pull up resistor.

SCL

Open Collector Connect to Si3452 SCL and pull up resistor.

8

Rev. 1.1

Si3480

6. Ordering Guide

Ordering Part Number

Description

Package Information

20 pin 4x4 mm QFN

RoHS compliant

Si3480-A01-GM

Power management controller

An eight-port evaluation kit with the Si3480, two

Si3452 controllers and the Si3500 for generating

the 3.3 V supply from the PoE supply

Si3480 Kit

Evaluation Board

Notes:

1. Add “R” to the part number to denote tape and reel option (Si3480-A01-GMR)

2. The ordering part number is not the same as the device mark. See “9. Top Marking: 20-Pin QFN” for device marking

information.

Rev. 1.1

9

Si3480

7. Package Outline

Figure 2 illustrates the package details for the Si3480. Table 7 lists the values for the dimensions shown in the

illustration.

Figure 2. QFN-20 Package Drawing

Table 7. QFN-20 Package Dimensions

Dimension

Min

Typ

Max

Dimension

Min

Typ

Max

A

0.80

0.00

0.18

0.90

0.02

1.00

0.05

0.30

L

0.45

0.00

—

0.55

—

0.65

0.15

0.10

0.05

0.08

—

A1

L1

b

0.25

aaa

bbb

ddd

eee

Z

—

D

D2

4.00 BSC.

2.15

—

2.00

2.25

—

e

0.50 BSC.

4.00 BSC.

2.15

—

E

—

0.43

0.18

E2

Y

—

Notes:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to the JEDEC Solid State Outline MO-220, variation VGGD except for

custom features D2, E2, Z, Y, and L which are toleranced per supplier designation.

4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body

Components.

10

Rev. 1.1

Si3480

8. Landing Pattern: 20-Pin QFN

Figure 3 illustrates the landing pattern for the Si3480. Table 8 lists the values for the dimensions shown in the

illustration.

Figure 3. QFN-20 Recommended PCB Land Pattern

Table 8. QFN-20 PCB Land Pattern Dimensions

Dimension

Min

Max

Dimension

Min

Max

C1

C2

E

3.70

0.50

X2

Y1

Y2

2.15

0.90

2.15

2.25

1.00

2.25

X1

0.20

0.30

Notes:

General

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.

3. This Land Pattern Design is based on the IPC-7351 guidelines.

Solder Mask Design

4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder

mask and the metal pad is to be 60 m minimum, all the way around the pad.

Stencil Design

5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used

to assure good solder paste release.

6. The stencil thickness should be 0.125 mm (5 mils).

7. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.

8. A 2x2 array of 0.95mm openings on a 1.1 mm pitch should be used for the center pad to

assure the proper paste volume (71% Paste Coverage).

Card Assembly

9. A No-Clean, Type-3 solder paste is recommended.

10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small

Body Components.

Rev. 1.1

11

Si3480

9. Top Marking: 20-Pin QFN

Figure 4 illustrates the top markings for the Si3480. Table 9 explains the values for the markings shown in the

illustration.

3480A

01

TTTTT

YYWW+

Figure 4. Si3480 Top Marking

Table 9. Top Marking Explanations

Pin 1 Identifier

Product ID

Circle, 0.25 mm diameter

Si3480A

Line 1 Marking:

Line 2 Marking:

Line 3 Marking:

01 = Firmware revision 01

TTTTT = Trace Code

YYWW = Date Code

Lead Free Designator

Assigned by Assembly Contractor

YY = Last 2 digits of current year

(ex. = 2010)

Line 4 Marking:

WW = Current Work Week

+

12

Rev. 1.1

Si3480

DOCUMENT CHANGE LIST

Revision 0.1 to Revision 1.0

 Updated Table 3

Updated typical output low, typical output high, and

sense accuracy.

Updated pin description.

Revision 1.0 to Revision 1.1

 Added “Not Recommended for New Designs”

watermark.

Rev. 1.1

13

Si3480

CONTACT INFORMATION

Silicon Laboratories Inc.

400 West Cesar Chavez

Austin, TX 78701

Tel: 1+(512) 416-8500

Fax: 1+(512) 416-9669

Toll Free: 1+(877) 444-3032

Please visit the Silicon Labs Technical Support web page:

https://www.siliconlabs.com/support/pages/contacttechnicalsupport.aspx

and register to submit a technical support request.

Patent Notice

Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analog-

intensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team.

The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.

Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from

the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed fea-

tures or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warran-

ty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any

liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation

consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intend-

ed to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where

personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized

application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.

Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.

Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.

14

Rev. 1.1


型号：	SI3480-A01-GMR
厂家：	SILICON
描述：	Power Supply Support Circuit, Fixed, 1 Channel, 4 X 4 MM, ROHS COMPLIANT, MO-220VGGD, QFN-20
文件：	总14页 (文件大小：137K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SI3480-A01-GMR [SILICON]

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