SI4112G [SILICON]
DUAL-BAND RF SYNTHESIZER WITH INTEGRATED VCOS FOR GSM AND GPRS WIRELESS COMMUNICATIONS; 集成VCO用于GSM和GPRS无线通讯双频RF合成器
| 型号： | SI4112G |
| 厂家： | 
SILICON |
| 描述： | DUAL-BAND RF SYNTHESIZER WITH INTEGRATED VCOS FOR GSM AND GPRS WIRELESS COMMUNICATIONS |
| 文件： | 总32页 (文件大小：468K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si4133G
Si4123G/22G/13G/12G
DUAL-BAND RF SYNTHESIZER WITH INTEGRATED VCOS
FOR GSM AND GPRS WIRELESS COMMUNICATIONS
Features
ꢀ
Dual-Band RF Synthesizers ꢀ Fast Settling Time: 140 µs
ꢁ RF1: 900 MHz to 1.8 GHz
ꢁ RF2: 750 MHz to 1.5 GHz
IF Synthesizer
ꢀ
ꢀ
ꢀ
ꢀ
Low Phase Noise
Programmable Power Down Modes
1 µA Standby Current
Si4133G-BT
ꢀ
ꢀ
ꢀ
ꢁ IF: 500 MHz to 1000 MHz
18 mA Typical Supply Current
Integrated VCOs, Loop Filters, ꢀ 2.7 V to 3.6 V Operation
Varactors, and Resonators ꢀ Packages: 24-Pin TSSOP and
Minimal External Components
Required
Ordering Information:
28-Pin MLP
See page 28.
Applications
Pin Assignments
ꢀ
GSM, DCS1800, and PCS1900 ꢀ GPRS Data Terminals
Cellular Telephones HSCSD Data Terminals
ꢀ
Si4133G-BT
Description
SCLK
SDATA
GNDR
RFLD
SENB
1
24
23
22
21
20
19
18
17
16
15
14
13
VDDI
2
The Si4133G is a monolithic integrated circuit that performs both IF and
dual-band RF synthesis for GSM and GPRS wireless communications
applications. The Si4133G includes three VCOs, loop filters, reference and
VCO dividers, and phase detectors. Divider and power down settings are
programmable through a three-wire serial interface.
IFOUT
GNDI
IFLB
3
4
RFLC
5
IFLA
GNDR
RFLB
6
GNDD
VDDD
GNDD
XIN
7
RFLA
8
Functional Block Diagram
GNDR
GNDR
RFOUT
VDDR
9
10
11
12
Reference
Amplifier
÷ 65
XIN
RFLA
RFLB
PWDNB
AUXOUT
Phase
Detector
RF1
RF2
IF
Power
Down
PW DNB
RFOUT
÷ N
÷ N
÷ N
Control
Si4133G-BM
SDATA
SCLK
RFLC
RFLD
Phase
Serial
Interface
Detector
22-bit
Data
SENB
28
27
26
25
24
23
22
Register
1
2
3
4
5
6
7
21
20
19
18
17
16
15
G NDR
RFLD
RFLC
G NDR
RFLB
RFLA
G NDR
G NDI
IFLB
Phase
Test
Mux
AUXOUT
IFOUT
Detector
IFLA
IFLA
IFLB
G NDD
VDDD
G NDD
XIN
8
9
10
11
12
13
14
Patents pending
Rev. 1.1 4/01
Copyright © 2001 by Silicon Laboratories
Si4133G-DS11
Si4133G
2
Rev. 1.1
Si4133G
TABLE OF CONTENTS
Section
Page
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Setting the VCO Center Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Self-Tuning Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Output Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
PLL Loop Dynamics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
RF and IF Outputs (RFOUT and IFOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Reference Frequency Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Power Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Auxiliary Output (AUXOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Pin Descriptions: Si4133G-BT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Pin Descriptions: Si4133G-BM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Si4133G Derivative Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Package Outline: Si4133G-BT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Package Outline: Si4133G-BM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Rev. 1.1
3
Si4133G
Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Temperature
Symbol
TA
Test Condition
Min
–20
2.7
Typ
25
Max
85
Unit
°C
V
Supply Voltage
VDD
3.0
—
3.6
0.3
Supply Voltages Difference
V∆
(VDDR – VDDD),
–0.3
V
(VDDI – VDDD
)
Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at 3.0 V and an operating temperature of 25°C unless otherwise stated.
1,2
Table 2. Absolute Maximum Ratings
Parameter
Symbol
VDD
IIN
Value
–0.5 to 4.0
±10
Unit
V
DC Supply Voltage
Input Current3
mA
V
Input Voltage3
VIN
–0.3 to VDD+0.3
–55 to 150
oC
Storage Temperature Range
TSTG
Notes:
1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2. This device is a high performance RF integrated circuit with an ESD rating of < 2 kV. Handling and assembly of
this device should only be done at ESD-protected workstations.
3. For signals SCLK, SDATA, SENB, PWDNB and XIN.
4
Rev. 1.1
Si4133G
Table 3. DC Characteristics
(VDD = 2.7 to 3.6 V, TA = –20 to 85°C
Parameter
Typical Supply Current1
RF1 Mode Supply Current1
RF2 Mode Supply Current1
IF Mode Supply Current1
Standby Current
Symbol
Test Condition
Min
—
Typ
18
13
12
10
1
Max
31
Unit
mA
mA
mA
mA
µA
V
RF1 and IF Operating
—
17
—
17
—
14
PWDNB = 0
VIH = 3.6 V,
—
—
High Level Input Voltage2
Low Level Input Voltage2
High Level Input Current2
VIH
VIL
IIH
0.7 VDD
—
—
—
—
—
0.3 VDD
10
V
–10
µA
V
DD = 3.6 V
Low Level Input Current2
IIL
VIL = 0 V,
–10
—
10
µA
VDD= 3.6 V
High Level Output Voltage3
Low Level Output Voltage3
Notes:
VOH
VOL
IOH = –500 µA
IOH = 500 µA
VDD–0.4
—
—
—
—
V
V
0.4
1. RF1 = 1.55 GHz, RF2 = 1.2 GHz, IF = 800 MHz
2. For signals SCLK, SDATA, SENB, and PWDNB.
3. For signal AUXOUT.
Rev. 1.1
5
Si4133G
Table 4. Serial Interface Timing
(VDD = 2.7 to 3.6 V, TA = –20 to 85°C)
Parameter1
Symbol
Test Condition
Min
Typ
Max
Unit
SCLK Cycle Time
tclk
tr
Figure 1
Figure 1
Figure 1
Figure 1
Figure 1
Figure 2
Figure 2
Figure 2
Figure 2
Figure 2
Figure 2
40
—
—
10
10
5
—
—
—
—
—
—
—
—
—
—
—
—
50
50
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK Rise Time
SCLK Fall Time
tf
SCLK High Time
th
SCLK Low Time
tl
SDATA Setup Time to SCLK↑2
SDATA Hold Time from SCLK↑2
SENB↓ to SCLK↑ Delay Time2
SCLK↑ to SENB↑ Delay Time2
SENB↑ to SCLK↑ Delay Time2
SENB Pulse Width
tsu
thold
ten1
ten2
ten3
tw
0
10
12
12
10
Notes:
1. All timing is referenced to the 50% level of the waveform, unless otherwise noted.
2. Timing is not referenced to 50% level of waveform. See Figure 2.
tr
tf
80%
50%
20%
SCLK
th
tl
tclk
Figure 1. SCLK Timing Diagram
6
Rev. 1.1
Si4133G
tsu
thold
SCLK
SDATA
SENB
D17
D16
D15
A1
A0
ten3
ten1
ten2
tw
Figure 2. Serial Interface Timing Diagram
First bit
Last bit
clocked in
clocked in
D
D
D
D
D
D
D
D
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
3
A
2
A
1
A
0
17 16 15 14 13 12 11 10
data
field
address
field
Figure 3. Serial Word Format
Rev. 1.1
7
Si4133G
Table 5. RF and IF Synthesizer Characteristics
(VDD = 2.7 to 3.6 V, TA = –20 to 85°C)
Parameter1
Symbol
Test Condition
Min
Typ
Max
Unit
XIN Input Frequency
fREF
—
13
—
—
MHz
VPP
Reference Amplifier Sensitivity
VREF
0.5
VDD
+0.3
Phase Detector Update Frequency
fφ
fφ = fREF/R
200
—
KHz
MHz
fCEN
947
1720
RF1 Center Frequency Range
RF2 Center Frequency Range
IF VCO Center Frequency
Tuning Range from fCEN
RF1 VCO Pushing
fCEN
fCEN
789
526
–5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
–7
–8
—
—
—
—
—
—
—
—
—
1429
952
5
MHz
MHz
Note: LEXT ±10%
Open loop
—
%
0.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
MHz/V
MHz/V
MHz/V
MHzPP
MHzPP
MHzPP
dBc/Hz
dBc/Hz
deg rms
dBc/Hz
dBc/Hz
deg rms
dBc/Hz
deg rms
dBc
RF2 VCO Pushing
0.4
IF VCO Pushing
0.3
RF1 VCO Pulling
VSWR = 2:1, all
phases, open loop
0.4
RF2 VCO Pulling
0.1
IF VCO Pulling
0.1
RF1 Phase Noise
1 MHz offset
3 MHz offset
–132
–142
0.9
RF1 Integrated Phase Error
RF2 Phase Noise
100 Hz to 100 kHz
1 MHz offset
–134
–144
0.7
3 MHz offset
RF2 Integrated Phase Error
IF Phase Noise
100 Hz to 100 kHz
100 kHz offset
100 Hz to 100 kHz
Second Harmonic
–117
0.4
IF Integrated Phase Error
RF1 Harmonic Suppression
RF2 Harmonic Suppression
IF Harmonic Suppression
RFOUT Power Level
–26
–26
–26
–2
dBc
dBc
ZL = 50 Ω
dBm
IFOUT Power Level
ZL = 50 Ω
–6
–1
—
—
—
—
—
—
—
dBm
RF1 Reference Spurs
Offset = 200 kHz
Offset = 400 kHz
Offset = 600 kHz
Offset = 200 kHz
Offset = 400 kHz
Offset = 600 kHz
Figures 4, 5
–70
–75
–80
–75
–80
–80
140
dBc
dBc
dBc
RF2 Reference Spurs
dBc
dBc
dBc
Power Up Request to Synthesizer
Ready Time, RF1, RF2, IF2
tpup
tpdn
µs
Power Down Request to Synthesizer Off
Figures 4, 5
—
—
100
ns
Time3
Notes:
1. RF1 = 1.55 GHz, RF2 = 1.2 GHz, IF = 550 MHz for all parameters unless otherwise noted.
2. From power up request (PWDNB↑ or SENB↑ during a write of 1 to bits PDIB and PDRB in Register 2) to RF and IF
synthesizers ready (settled to within 0.1 ppm frequency error). Typical settling time to 5 degrees phase error is 120 µs.
3. From power down request (PWDNB↓, or SENB↑ during a write of 0 to bits PDIB and PDRB in Register 2) to supply
current equal to IPWDN
.
8
Rev. 1.1
Si4133G
RF and IF synthesizers settled to
within 0.1 ppm frequency error.
RF and IF synthesizers settled to
w ithin 0.1 ppm frequency error.
tpup
tpdn
t
t
pup
pdn
IT
IT
IPW DN
IPW D N
PW DNB
SENB
PDIB =
PDRB = 1
1
PDIB =
PDRB = 0
0
SDATA
Figure 5. Hardware Power Management Timing
Diagram
Figure 4. Software Power Management Timing
Diagram
Rev. 1.1
9
Si4133G
TRACE A: Ch1 FM Gate Time
A Offset
133.59375
us
800
Hz
Real
160
Hz
/div
-800
Hz
Stop: 299.21875 us
Start: 0 s
Figure 6. Typical Transient Response RF1 at 1.6 GHz
with 200 kHz Phase Detector Update Frequency
10
Rev. 1.1
Si4133G
−60
−70
−80
−90
−100
−110
−120
−130
−140
102
103
104
105
106
Offset Frequency (Hz)
Figure 7. Typical RF1 Phase Noise at 1.6 GHz
with 200 kHz Phase Detector Update Frequency
Figure 8. Typical RF1 Spurious Response at 1.6 GHz
with 200 kHz Phase Detector Update Frequency
Rev. 1.1
11
Si4133G
−60
−70
−80
−90
−100
−110
−120
−130
−140
102
103
104
105
106
Offset Frequency (Hz)
Figure 9. Typical RF2 Phase Noise at 1.2 GHz
with 200 kHz Phase Detector Update Frequency
Figure 10. Typical RF2 Spurious Response at 1.2 GHz
with 200 kHz Phase Detector Update Frequency
12
Rev. 1.1
Si4133G
−70
−80
−90
−100
−110
−120
−130
−140
−150
102
103
104
105
106
Offset Frequency (Hz)
Figure 11. Typical IF Phase Noise at 550 MHz
with 200 kHz Phase Detector Update Frequency
Figure 12. IF Spurious Response at 550 MHz
with 200 kHz Phase Detector Update Frequency
Rev. 1.1
13
Si4133G
Si4133G-BT
From
1
2
24
23
22
21
20
19
18
17
16
15
14
13
System
SENB
VDDI
SCLK
0.022µ F
VDD
Controller
SDATA
GNDR
RFLD
RFLC
GNDR
RFLB
RFLA
GNDR
GNDR
RFOUT
VDDR
10nH 560pF
3
IFOUT
GNDI
IFOUT
4
Printed Trace
Inductor or
5
IFLB
Chip Inductor
6
Printed Trace
Inductors
IFLA
7
GNDD
VDDD
GNDD
XIN
VDD
0.022µ F
8
9
560 pF
10
11
12
External Clock
PDWNB
560pF 2nH
RFOUT
PW DNB
AUXOUT
0.022µ F
VDD
AUXOUT
Figure 13. Typical Application Circuit: Si4133G-BT
VDD
From
0.022µ F
System
10nH 560pF
Controller
IFOUT
28
27
26
25
24
23
22
Printed Trace
Inductor or
Chip Inductor
1
2
3
4
5
6
7
21
20
19
18
17
16
15
GNDR
GNDI
IFLB
RFLD
RFLC
GNDR
RFLB
RFLA
GNDR
IFLA
Printed Trace
Inductors
GNDD
VDDD
GNDD
XIN
VDD
Si4133G-BM
0.022µF
560pF
External Clock
8
9
10
11
12
13
14
VDD
0.022µF
AUXOUT
RFOUT
PW DNB
2nH 560pF
Figure 14. Typical Application Circuit: Si4133G-BM
14
Rev. 1.1
Si4133G
The Si4133G is programmed serially with 22-bit words
comprised of 18-bit data fields and 4-bit address fields.
Functional Description
The Si4133G is a monolithic integrated circuit that When the serial interface is enabled (i.e., when SENB is
performs IF and dual-band RF synthesis for many low) data and address bits on the SDATA pin are
wireless applications such as GSM, DCS1800, and clocked into an internal shift register on the rising edge
PCS1900. Its fast transient response also makes the of SCLK. Data in the shift register is then transferred on
Si4133G especially well suited to GPRS and HSCSD the rising edge of SENB into the internal data register
multislot applications where channel switching and addressed in the address field. The serial interface is
settling times are critical. This integrated circuit (IC), disabled when SENB is high.
with a minimum number of external components, is all
that is necessary to implement the frequency synthesis
functions and addresses. The internal shift register will
function.
Table 10 on page 20 summarizes the data register
ignore any leading bits before the 22 required bits.
The Si4133G has three complete phase-locked loops
(PLLs) with integrated voltage-controlled oscillators
Setting the VCO Center Frequencies
(VCOs). The low phase noise of the VCOs makes the The PLLs can adjust the IF and RF output frequencies
Si4133G suitable for use in demanding wireless ±5% with respect to their VCO center frequencies. Each
communications applications. Also integrated are phase center frequency is established by the value of an
detectors, loop filters, and reference dividers. The IC is external inductance connected to the respective VCO.
programmed through a three-wire serial interface.
Manufacturing tolerances of ±10% for the external
inductances are acceptable. The Si4133G will
compensate for inaccuracies in each inductance by
executing a self-tuning algorithm following PLL power-
up or following a change in the programmed output
frequency.
One PLL is provided for IF synthesis, and two PLLs are
provided for dual-band RF synthesis. One RF VCO is
optimized to have its center frequency set between
947 MHz and 1720 MHz, while the second RF VCO is
optimized to have its center frequency set between
789 MHz and 1429 MHz. The IF VCO is optimized to Because the total tank inductance is in the low nH
have its center frequency set between 526 MHz and range, the inductance of the package needs to be
952 MHz. Each PLL can adjust its output frequency by considered in determining the correct external
±5% relative to its VCO center frequency.
inductance. The total inductance (LTOT) presented to
each VCO is the sum of the external inductance (LEXT
and the package inductance (LPKG). Each VCO has a
nominal capacitance (CNOM) in parallel with the total
inductance, and the center frequency is as follows:
)
The center frequency of each of the three VCOs is set
by connection of an external inductance. Inaccuracies in
the value of the inductance are compensated for by the
Si4133G’s proprietary self-tuning algorithm. This
algorithm is initiated each time the PLL is powered-up
(by either the PWDNB pin or by software) and/or each
time a new output frequency is programmed.
1
fCEN = ---------------------------------------------
2π LTOT CNOM
or
The two RF PLLs share a common output pin, so only
one PLL is active at a given time. Because the two
VCOs can be set to have widely separated center
frequencies, the RF output can be programmed to
service different frequency bands, thus making the
Si4133G ideal for use in dual-band cellular handsets.
1
fCEN = ----------------------------------------------------------------------
2π (LPKG + LEXT) CNOM
Tables 6 and 7 summarize these characteristics for
each VCO.
The unique PLL architecture used in the Si4133G
produces a transient response that is superior in speed
to fractional-N architectures without suffering the high
phase noise or spurious modulation effects often
associated with those designs.
Serial Interface
A timing diagram for the serial interface is shown in
Figure 2 on page 7. Figure 3 on page 7 shows the
format of the serial word.
Rev. 1.1
15
Si4133G
in addition to 2.3 nH of LPKG (Si4133G-BT), will present
the correct total inductance to the VCO. In
manufacturing, the external inductance can vary ±10%
of its nominal value and the Si4133G will correct for the
variation with the self-tuning algorithm.
Table 6. Si4133G-BT VCO Characteristics
VCO Fcen Range Cnom Lpkg
Lext Range
(nH)
(MHz)
(pF)
(nH)
Min Max
Min
0.0
0.3
2.2
Max
4.6
In most cases, particularly for the RF VCOs, the
requisite value of the external inductance is small
enough to allow a PC board trace to be utilized. During
initial board layout, a length of trace approximating the
desired inductance can be used. For more information,
please refer to Application Note 31.
RF1 947 1720 4.3
RF2 789 1429 4.8
2.0
2.3
2.1
6.2
IF
526 952
6.5
12.0
Self-Tuning Algorithm
Table 7. Si4133G-BM VCO Characteristics
The self-tuning algorithm is initiated immediately
following power-up of a PLL or, if the PLL is already
powered, following a change in its programmed output
frequency. This algorithm attempts to tune the VCO so
that its free-running frequency is near the desired output
frequency. In so doing, the algorithm will compensate
for manufacturing tolerance errors in the value of the
external inductance connected to the VCO. It will also
reduce the frequency error for which the PLL must
correct to get the precise desired output frequency. The
self-tuning algorithm will leave the VCO oscillating at a
frequency in error by somewhat less than 1% of the
desired output frequency.
VCO Fcen Range Cnom Lpkg
Lext Range
(nH)
(MHz)
(pF)
(nH)
Min Max
Min
0.5
1.1
2.7
Max
5.1
RF1 947 1720 4.3
RF2 789 1429 4.8
1.5
1.5
1.6
7.0
IF
526 952
6.5
12.5
After self-tuning, the PLL controls the VCO oscillation
frequency. The PLL will complete frequency locking,
eliminating any remaining frequency error. Thereafter, it
will maintain frequency-lock, compensating for effects
caused by temperature and supply voltage variations.
LPKG
2
LEXT
The Si4133G’s self-tuning algorithm will compensate for
component value errors at any temperature within the
specified temperature range. However, the ability of the
PLL to compensate for drift in component values that
occur after self-tuning is limited. For external
inductances with temperature coefficients around
±150 ppm/oC, the PLL will be able to maintain lock for
changes in temperature of approximately ±30oC.
LPKG
2
Figure 15. External Inductance Connection
Applications where the PLL is regularly powered down
(such as GSM) or switched between channels minimize
or eliminate the potential effects of temperature drift
because the VCO is re-tuned when it is powered up or
when a new frequency is programmed. In applications
where the ambient temperature can drift substantially
after self-tuning, it may be necessary to monitor the
LDETB (lock-detect bar) signal on the AUXOUT pin to
determine the locking state of the PLL. (See "Auxiliary
Output (AUXOUT)" on page 18 for how to select
LDETB.)
As a design example, suppose it is desired to
synthesize frequencies in a 25 MHz band between
1120 MHz and 1145 MHz. The center frequency should
be defined as midway between the two extremes, or
1132.5 MHz. The PLL will be able to adjust the VCO
output frequency ±5% of the center frequency, or
±56.6 MHz of 1132.5 MHz (i.e., from approximately
1076 MHz to 1189 MHz, more than enough for this
example). The RF2 VCO has a CNOM of 4.8 pF, and a
4.1 nH inductance (correct to two digits) in parallel with
this capacitance will yield the desired center frequency.
An external inductance of 1.8 nH should be connected
between RFLC and RFLD as shown in Figure 15. This,
The LDETB signal is normally low after self-tuning is
completed but will rise to a logic high condition when
16
Rev. 1.1
Si4133G
either the IF or RF PLL nears the limit of its the RF and IF PLLs Tφ = 5 µS. During the first 6.5
compensation range (LDETB will also be high when update periods, the Si4133G executes the self-tuning
either PLL is executing the self-tuning algorithm). The algorithm. Thereafter the PLL controls the output
output frequency will still be locked when LDETB goes frequency. Because of the unique architecture of the
high, but the PLL will eventually lose lock if the Si4133G PLLs, the time required to settle the output
temperature continues to drift in the same direction. frequency to 0.1 ppm error is approximately 21 update
Therefore, if LDETB goes high both the IF and RF PLLs periods. Thus, the total time after power-up or a change
should promptly be re-tuned by initiating the self-tuning in programmed frequency until the synthesized
algorithm.
frequency is well settled (including time for self-tuning)
is around 28 update periods or 140 µS.
Output Frequencies
RF and IF Outputs (RFOUT and IFOUT)
The IF and RF output frequencies are set by
programming the N-Divider registers. Each RF PLL has The RFOUT pin is driven by an amplifier that buffers the
its own register and can be programmed output pin from the RF VCOs, and must be coupled to
N
independently. All three PLL R dividers are fixed at its load through an AC coupling capacitor. The amplifier
R = 65 to yield a 200 kHz phase detector update rate receives its input from either the RF1 or RF2 VCO,
from a 13 MHz reference frequency. Programming the depending upon which N-Divider register was last
N-Divider register for either RF1 or RF2 automatically written. For example, programming the N-Divider
selects the associated output.
register for RF1 automatically selects the RF1 VCO
output.
The reference frequency on the XIN pin is divided by R
and this signal is the input to the PLL’s phase detector. A matching network is required to maximize power
The other input to the phase detector is the PLL’s VCO delivered into a 50 Ω load. The network consists of a 2
output frequency divided by N. The PLL works to make nH series inductance, which may be realized with a PC
these frequencies equal. That is, after an initial transient board trace, connected between the RFOUT pin and
the AC coupling capacitor. The network is made to
f
fREF
--O----U----T- = -----------
65
provide an adequate match for both the RF1 and RF2
frequency bands, and also filters the output signal to
reduce harmonic distortion. A 50 Ω load is not required
for proper operation of the Si4133G. Depending on
transceiver requirements, the matching network may
not be needed. See Figure 16.
N
or
N
------
fOUT
=
fREF
65
For XIN = 13 MHz this simplifies to
560 pF
fOUT = N 200 kHz
RFOUT
2 nH
The integer N is set by programming the RF1 N-Divider
register (Register 3), the RF2 N-Divider register
(Register 4), and the IF N-Divider register (Register 5).
50 Ω
Each N divider is implemented as a conventional high
speed divider. That is, it consists of a dual-modulus
prescaler, a swallow counter, and a lower speed
synchronous counter. However, the calculation of these
values is done automatically. Only the appropriate N
value needs to be programmed.
Figure 16. RFOUT 50 Ω Test Circuit
The IFOUT pin is driven by an amplifier that buffers the
output pin from the IF VCO. The IFOUT pin must be
coupled to its load through an AC coupling capacitor. A
matching network is required to maximize power
delivered into a 50 Ω load. See Figure 17.
PLL Loop Dynamics
The transient response for each PLL has been
optimized for a GSM application. VCO gain, phase
detector gain, and loop filter characteristics are not
programmable.
The settling time for each PLL is directly proportional to
its phase detector update period Tφ (Tφ equals 1/fφ). For
a GSM application with a 13 MHz reference frequency,
Rev. 1.1
17
Si4133G
Reference Frequency Amplifier
560 pF
The Si4133G provides a reference frequency amplifier.
If the driving signal has CMOS levels it can be
connected directly to the XIN pin. Otherwise, the
reference frequency signal should be AC coupled to the
XIN pin through a 560 pF capacitor.
IFOUT
LMATCH
50 Ω
Power Down Modes
Table 9 summarizes the power down functionality. The
Si4133G can be powered down by taking the PWDNB
pin low or by setting bits in the Power Down register
(Register 1). When the PWDNB pin is low, the Si4133G
will be powered down regardless of the Power Down
register settings. When the PWDNB pin is high, power
management is under control of the Power Down
register bits.
Figure 17. IFOUT 50 Ω Test Circuit
Table 8. L
Values
LMATCH
MATCH
Frequency
500–600 MHz
600–800 MHz
800–1 GHz
40 nH
27 nH
18 nH
The reference frequency amplifier, IF, and RF sections
of the Si4133G circuitry can be individually powered
down by setting the Power Down register bits PDIB and
PDRB low, respectively. The reference frequency
amplifier will also be powered up if either of the PDRB
or PDIB bits are high. Also, setting the AUTOPDB bit to
1 in the Main Configuration register (Register 0) is
equivalent to setting both bits in the Power Down
register to 1. The serial interface remains available and
can be written in all power down modes.
The IF output level is dependent upon the load.
Figure 18 displays the output level versus load
resistance for a variety of output frequencies.
450
400
350
Auxiliary Output (AUXOUT)
LPWR=1
LPWR=0
300
The signal appearing on AUXOUT is selected by setting
the AUXSEL bits in the Main Configuration register
(Register 0).
250
200
150
100
50
The LDETB signal can be selected by setting the
AUXSEL bits to 11. As discussed previously, this signal
can be used to indicate that the IF or RF PLL is about to
lose lock due to excessive ambient temperature drift and
should be re-tuned.
0
0
200
400
600
800
1000
1200
Load Resistance (Ω)
Figure 18. Typical IF Output Voltage vs. Load
Resistance at 550 MHz
For resistive loads greater than 500 Ω the output level
saturates and the bias currents in the IF output amplifier
are higher than they need be. The LPWR bit in the Main
Configuration register (Register 0) can be set to 1 to
reduce the bias currents and therefore reduce the
power dissipated by the IF amplifier. For loads less than
500 Ω LPWR should be set to 0 to maximize the output
level.
18
Rev. 1.1
Si4133G
Table 9. Power Down Configuration
PWDNB Pin
AUTOPDB
PDIB
PDRB
IF Circuitry RF Circuitry
x
0
0
0
0
1
x
0
0
1
1
x
x
0
1
0
1
x
OFF
OFF
OFF
ON
OFF
OFF
ON
PWDNB = 0
OFF
ON
PWDNB = 1
ON
ON
ON
Rev. 1.1
19
Si4133G
Control Registers
Table 10. Register Summary
Register Name
Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit
17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
LPWR
AUTO
PDB
AUXSEL
[1:0]
0
Main
Configuration
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
2
3
4
5
6
Reserved
PDIB PDRB
Power Down
RF1 N Divider
RF2 N Divider
IF N Divider
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
NRF1[17:0]
0
0
N
RF[16:0]
0
NIF[15:0]
.
.
.
15
Reserved
Note: Registers 1 and 6–15 are reserved. Writes to these registers may result in unpredictable behavior. Any register not listed
here is reserved and should not be written.
20
Rev. 1.1
Si4133G
Register 0. Main Configuration Address Field = A[3:0] = 0000
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5
D4
D3 D2 D1 D0
LPWR
AUTO
PDB
Name
0
0
0
0
AUXSEL
[1:0]
0
0
0
0
0
0
0
0
1
0
Bit
Name
Function
17:14
13:12
Reserved
Program to zero.
AUXSEL
[1:0]
Auxiliary Output Pin Definition.
00 = Reserved.
01 = Force output low.
10 = Reserved.
11 = Lock Detect—LDETB.
11:6
5
Reserved
LPWR
Program to zero.
Output Power-Level Settings for IF Synthesizer Circuit.
0 = RLOAD < 500 Ω—normal power mode.
1 = RLOAD ≥ 500 Ω—low power mode.
4
3
Reserved
Program to zero.
AUTOPDB
Auto Power Down
0 = Software powerdown is controlled by Register 2.
1 = Equivalent to setting all bits in Register 2 = 1.
2
1
0
Reserved
Reserved
Reserved
Program to zero.
Program to one.
Program to zero.
Rev. 1.1
21
Si4133G
Register 2. Power Down Address Field (A[3:0]) = 0010
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2
D1
D0
PDIB
PDRB
Name
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
17:2
1
Name
Reserved
PDIB
Function
Program to zero.
Power Down IF Synthesizer.
0 = IF synthesizer powered down.
1 = IF synthesizer on.
Note: Always program to 0 for Si4113G.
0
PDRB
Power Down RF Synthesizer.
0 = RF synthesizer powered down.
1 = RF synthesizer on.
Note: Always program to 0 for Si4112G.
Register 3. RF1 N Divider Address Field (A[3:0]) = 0011
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
RF1[17:0]
Name
N
Bit
Name
Function
17:0
NRF1[17:0]
N Divider for RF1 Synthesizer.
Register reserved for Si4112G, Si4122G. Writes to this register may result in unpre-
dictable behavior.
22
Rev. 1.1
Si4133G
Register 4. RF2 N Divider Address Field = A[3:0] = 0100
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
RF2[16:0]
Name
0
N
Bit
17
Name
Function
Reserved
Program to zero.
N Divider for RF2 Synthesizer.
16:0
NRF2[16:0]
Register reserved for Si4112G, Si4123G. Writes to this register may result in
unpredictable behavior.
Register 5. IF N Divider Address Field (A[3:0]) = 0101
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
NIF[15:0]
Name
0
0
Bit
Name
Function
17:16
15:0
Reserved
NIF[15:0]
Program to zero.
N Divider for IF Synthesizer.
Register reserved for Si4113G. Writes to this register may result in
unpredictable behavior.
Rev. 1.1
23
Si4133G
Pin Descriptions: Si4133G-BT
SENB
VDDI
SCLK
SDATA
GNDR
RFLD
1
24
23
22
21
20
19
18
17
16
15
14
13
2
IFOUT
GNDI
IFLB
3
4
RFLC
5
IFLA
GNDR
RFLB
6
GNDD
VDDD
GNDD
XIN
7
RFLA
8
GNDR
GNDR
RFOUT
VDDR
9
10
11
12
PWDNB
AUXOUT
Pin Number(s) Name
Description
1
SCLK
Serial clock input
Serial data input
2
SDATA
GNDR
3, 6, 9, 10
4, 5
7, 8
11
Common ground for RF analog circuitry
RFLC, RFLD Pins for inductor connection to RF2 VCO
RFLA, RFLB
RFOUT
VDDR
Pins for inductor connection to RF1 VCO
Radio frequency (RF) output of the selected RF VCO
Supply voltage for the RF analog circuitry
Auxiliary output
12
13
AUXOUT
PWDNB
XIN
14
Power down input pin
15
Reference frequency amplifier input
Common ground for digital circuitry
Supply voltage for digital circuitry
Pins for inductor connection to IF VCO
Common ground for IF analog circuitry
Intermediate frequency (IF) output of the IF VCO
Supply voltage for IF analog circuitry
Enable serial port input
16, 18
17
GNDD
VDDD
19, 20
21
IFLA, IFLB
GNDI
22
IFOUT
VDDI
23
24
SENB
24
Rev. 1.1
Si4133G
Table 11. Pin Descriptions for Si4133G Derivatives—TSSOP
Pin Number Si4133G-BT Si4123G-BT Si4122G-BT Si4113G-BT Si4112G-BT
1
SCLK
SDATA
GNDR
RFLD
RFLC
GNDR
RFLB
SCLK
SDATA
GNDR
GNDR
GNDR
GNDR
RFLB
SCLK
SDATA
GNDR
RFLD
SCLK
SDATA
GNDR
RFLD
SCLK
SDATA
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
VDDD
AUXOUT
PWDNB
XIN
2
3
4
5
RFLC
RFLC
6
GNDR
GNDR
GNDR
GNDR
GNDR
RFOUT
VDDR
AUXOUT
PWDNB
XIN
GNDR
RFLB
7
8
RFLA
RFLA
RFLA
9
GNDR
GNDR
RFOUT
VDDR
AUXOUT
PWDNB
XIN
GNDR
GNDR
RFOUT
VDDR
AUXOUT
PWDNB
XIN
GNDR
GNDR
RFOUT
VDDR
AUXOUT
PWDNB
XIN
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
GNDD
VDDD
GNDD
IFLA
GNDD
VDDD
GNDD
IFLA
GNDD
VDDD
GNDD
IFLA
GNDD
VDDD
GNDD
GNDD
GNDD
GNDD
GNDD
VDDD
SENB
GNDD
VDDD
GNDD
IFLA
IFLB
IFLB
IFLB
IFLB
GNDI
GNDI
GNDI
GNDI
IFOUT
VDDI
IFOUT
VDDI
IFOUT
VDDI
IFOUT
VDDI
SENB
SENB
SENB
SENB
Rev. 1.1
25
Si4133G
Pin Descriptions: Si4133G-BM
28
27
26
25
24
23
22
1
2
3
4
5
6
7
21
20
19
18
17
16
15
GNDR
RFLD
RFLC
GNDR
RFLB
RFLA
GNDR
GNDI
IFLB
IFLA
GNDD
VDDD
GNDD
XIN
8
9
10
11
12
13
14
Pin Number(s) Name
Description
Common ground for RF analog circuitry
RFLC, RFLD Pins for inductor connection to RF2 VCO
1, 4, 7–9, 28
GNDR
2, 3
5,6
RFLA, RFLB
RFOUT
VDDR
Pins for inductor connection to RF1 VCO
10
Radio frequency (RF) output of the selected RF VCO
Supply voltage for the RF analog circuitry
Auxiliary output
11
12
AUXOUT
PWDNB
GNDD
XIN
13
Power down input pin
14, 16, 18
15
Common ground for digital circuitry
Reference frequency amplifier input
Supply voltage for digital circuitry
Pins for inductor connection to IF VCO
Common ground for IF analog circuitry
Intermediate frequency (IF) output of the IF VCO
Supply voltage for IF analog circuitry
Enable serial port input
17
VDDD
19, 20
21, 22
23
IFLA, IFLB
GNDI
IFOUT
VDDI
24
25
SENB
26
SCLK
Serial clock input
27
SDATA
Serial data input
26
Rev. 1.1
Si4133G
Table 12. Pin Descriptions for Si4133G Derivatives—MLP
Pin Number Si4133G-BM Si4123G-BM Si4122G-BM Si4113G-BM Si4112G-BM
1
GNDR
RFLD
RFLC
GNDR
RFLB
GNDR
GNDR
GNDR
GNDR
RFLB
GNDR
RFLD
RFLC
GNDR
GNDR
GNDR
GNDR
GNDR
GNDR
RFOUT
VDDR
AUXOUT
PWDNB
GNDD
XIN
GNDR
RFLD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
VDDD
AUXOUT
PWDNB
GNDD
XIN
2
3
RFLC
4
GNDR
RFLB
5
6
RFLA
RFLA
RFLA
7
GNDR
GNDR
GNDR
RFOUT
VDDR
AUXOUT
PWDNB
GNDD
XIN
GNDR
GNDR
GNDR
RFOUT
VDDR
AUXOUT
PWDNB
GNDD
XIN
GNDR
GNDR
GNDR
RFOUT
VDDR
AUXOUT
PWDNB
GNDD
XIN
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
GNDD
VDDD
GNDD
IFLA
GNDD
VDDD
GNDD
IFLA
GNDD
VDDD
GNDD
IFLA
GNDD
VDDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
VDDD
SENB
SCLK
GNDD
VDDD
GNDD
IFLA
IFLB
IFLB
IFLB
IFLB
GNDI
GNDI
GNDI
GNDI
GNDI
GNDI
GNDI
GNDI
IFOUT
VDDI
IFOUT
VDDI
IFOUT
VDDI
IFOUT
VDDI
SENB
SCLK
SDATA
GNDR
SENB
SCLK
SDATA
GNDR
SENB
SCLK
SDATA
GNDR
SENB
SCLK
SDATA
GNDD
SDATA
GNDR
Rev. 1.1
27
Si4133G
Ordering Guide
Ordering Part
Number
Description
RF1/RF2/IF
RF1/IF
Operating
Temperature
Si4133G-BT*
Si4133G-BM
–20 to 85oC
–20 to 85oC
–20 to 85oC
–20 to 85oC
–20 to 85oC
Si4123G-BT*
Si4123G-BM
Si4122G-BT*
Si4122G-BM
RF2/IF
Si4113G-BT*
Si4113G-BM
RF1/RF2
IF
Si4112G-BT*
Si4112G-BM
*Note: TSSOP not recommended for new designs.
Si4133G Derivative Devices
The Si4133G performs both IF and dual-band RF frequency synthesis. The Si4112G, Si4113G, Si4122G, and the
Si4123G are derivatives of this device. Table 13 outlines which synthesizers each derivative device features as
well as which pins and registers coincide with each synthesizer.
Table 13. Si4133G Derivatives
Name
Synthesizer
Pins
Registers
Si4112G
IF
IFLA, IFLB
NIF, RIF, PDIB, IFDIV, LPWR, AUTOPDB = 0,
PDRB = 0
Si4113G
RF1, RF2
RFLA, RFLB, RFLC, RFLD
N
RF1, NRF2, RRF1, RRF2, PDRB, AUTOPDB = 0,
PDIB = 0
Si4122G
Si4123G
Si4133G
RF2, IF
RF1, IF
RFLC, RFLD, IFLA, IFLB
RFLA, RFLB, IFLA, IFLB
N
N
RF2, RRF2, PDRB, NIF, RIF, PDIB, LPWR
RF1, RRF1, PDRB, NIF, RIF, PDIB, LPWR
RF1, RF2, IF
RFLA, RFLB, RFLC, RFLD,
IFLA, IFLB
N
RF1, NRF2, RRF1, RRF2, PDRB, NIF, RIF,
PDIB, LPWR
28
Rev. 1.1
Si4133G
Package Outline: Si4133G-BT
θ 2
E1
E
S
R1
R
θ 1
L
e
L1
θ 3
D
c
A2
A
b
A1
Figure 19. 24-pin Thin Small Shrink Outline Package (TSSOP)
Table 14. Package Diagram Dimensions
Symbol
Millimeters
Nom
1.10
Min
—
Max
1.20
0.15
1.05
0.30
0.20
7.90
A
A1
A2
b
c
D
0.05
0.80
0.19
0.09
7.70
—
1.00
—
—
7.80
e
E
E1
L
0.65 BSC
6.40 BSC
4.40
4.30
0.45
4.50
0.75
0.60
L1
R
R1
S
θ1
θ2
θ3
1.00 REF
—
0.09
0.09
0.20
0
—
—
—
8
—
—
—
12 REF
12 REF
Rev. 1.1
29
Si4133G
Package Outline: Si4133G-BM
Figure 20. 28-Pin Micro Leadframe Package (MLP)
Table 15. Package Dimensions
Controlling Dimension: mm
Symbol
Millimeters
Nom
Min
—
Max
1.00
0.05
0.30
A
A1
b
0.90
0.00
0.18
0.01
0.23
D
5.00 BSC
4.75 BSC
5.00 BSC
4.75 BSC
28
D1
E
E1
N
Nd
Ne
e
7
7
0.50 BSC
0.60
L
0.50
0.75
12°
θ
30
Rev. 1.1
Si4133G
NOTES:
Rev. 1.1
31
Si4133G
Contact Information
Silicon Laboratories Inc.
4635 Boston Lane
Austin, Texas 78735
Tel:1+ (512) 416-8500
Fax:1+ (512) 416-9669
Toll Free:1+ (877) 444-3032
Email: productinfo@silabs.com
Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed fea-
tures or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no war-
ranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume
any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applica-
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Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brand names mentioned herein are trademarks or registered trademarks of their respective holders.
32
Rev. 1.1
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