SI4356-B1A-FMR [SILICON]
Audio Single Chip Receiver;
| 型号： | SI4356-B1A-FMR |
| 厂家： | 
SILICON |
| 描述： | Audio Single Chip Receiver 商用集成电路 |
| 文件： | 总24页 (文件大小：343K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si4356
Si4356 STANDALONE SUB-GHZ RECEIVER
Features
Pin configurable
Low RX Current = 12 mA
Frequency range = 315–917 MHz Low standby current = 50 nA
Supply Voltage = 1.8–3.6 V
Max data rate = 120 kbps
Automatic gain control (AGC)
System clock output
Receive sensitivity =
Up to –113 dBm
Modulation
Low BOM
(G)FSK
OOK
20-pin 3x3 mm QFN package
Applications
Remote control
Home automation
Industrial control
Sensor networks
Health monitors
Home security and alarm
Garage and gate openers
Remote keyless entry
Pin Assignments
Description
GND
RST
RXp
RXn
NC
1
2
3
4
5
6
20 19 18 17 16 GND
15 SEL1
Silicon Laboratories' Si4356 is a pin-strap configurable, low current,
sub-GHz EZRadio® receiver. With no external MCU control needed, the
Si4356 provides a true plug-and-play receive option. Excellent sensitivity
up to –113 dBm allows for a longer operating range, while the low current
consumption of 12 mA active and 50 nA standby provides for superior
battery life. The Si4356 provides receive data as well as a system clock
output for use by an external microcontroller or decoder.
14 RX_DATA / OUT1
GND
13 STBY
12 MSTAT / OUT0
GND
7
8
9
10 11 SEL0
20-pin QFN
(Top View)
Patents pending
Rev 1.1 7/13
Copyright © 2013 by Silicon Laboratories
Si4356
Si4356
Functional Block Diagram
XIN XOUT
RST
Synthesizer
CLK_OUT
÷
30MHz XO
ADC
Rx Chain
STBY
RXp
RXn
PGA
LNA
Rx Modem
RX_DATA / OUT1
MSTAT / OUT0
Configuration Decoder
SEL0 SEL1 SEL2 SEL3
VDD
GND
2
Rev 1.1
Si4356
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.1. Definition of Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2. Typical Applications Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3. Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
5. Modes and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
6. Additional Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
6.1. System Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
7. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
8. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
9. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
10. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
11. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
11.1. Si4356 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
11.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Rev 1.1
3
Si4356
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Temperature
Supply Voltage
Symbol
Test Condition
Min
–40
1.8
Typ
25
—
Max
85
Unit
C
V
T
—
—
—
A
V
3.6
3.6
DD
I/O Drive Voltage
V
1.8
—
V
GPIO
Table 2. DC Characteristics*
Parameter
Symbol
Test Condition
Min Typ Max Unit
Standby Mode Current
I
Configuration retained, all other functions OFF
—
—
—
50
12
—
—
nA
Standby
RX Mode Current
I
mA
RX
*Note: All specifications guaranteed by production test unless otherwise noted. Production test conditions and max limits are
listed in the "Production Test Conditions" section of "1.1. Definition of Test Conditions" on page 8.
Table 3. Receiver Electrical Characteristics1
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Only frequencies listed in Table 9
supported
Frequency Range
F
315
—
917
MHz
RANGE
2
Sensitivity
P
P
BER < 0.1%, 2.4 kbps, (G)FSK,
Configuration = FSK1 (See Section 3.)
—
–113
–104
–111
—
dBm
dBm
dBm
FSK
FSK
OOK
BER < 0.1%, 2.4 kbps, (G)FSK,
Configuration = FSK6 (See Section 3.)
P
BER < 0.1%, 2.4 kbps, OOK,
—
—
Configuration = OOK6 (See Section 3.)
3
RX Channel Bandwidth
BW
—
100
—
—
0
535
0.1
kHz
BER Variation vs Power
P
Up to +5 dBm Input Level
ppm
RX_RES
3
Level
Notes:
1. Test conditions and max limits are listed in section “1.1. Definition of Test Conditions”.
2. Sensitivity measured at 434 MHz using a PN9 modulated input signal. Received signal is filtered, deglitched, and
retimed using an external RC filter (R = 1 k, C = 47 nF) and MCU.
3. Guaranteed by qualification. Qualification test conditions are listed in section “1.1. Definition of Test Conditions”.
4
Rev 1.1
Si4356
Table 3. Receiver Electrical Characteristics1 (Continued)
Parameter
200 kHz Selectivity
400 kHz Selectivity
Symbol
Test Condition
Min
—
Typ
–42
–50
Max
—
Unit
dB
3
3
C/I
Desired Ref Signal 3 dB above sensitiv-
ity, BER < 0.1%. Interferer is CW and
desired modulated with
1-CH
C/I
—
—
dB
2-CH
2.4 kbps F = 30 kHz (G)FSK,
BT = 0.5,
Rx BW = 155 kHz,
3
3
—
—
Desired Ref Signal 3 dB above sensitiv-
ity, BER < 0.1% Interferer is CW and
desired modulated with 2.4 kbps
F = 30 kHz (G)FSK, BT = 0.5,
RX BW = 155 kHz
—
—
–57
–68
—
—
dB
dB
Blocking 1 MHz Offset
Blocking 8 MHz Offset
3
Im
IF = 468 kHz
—
—
–35
—
—
dB
Image Rejection
REJ
3
P
Measured at RX pins
–54
dBm
Spurious Emissions
OB_RX1
Notes:
1. Test conditions and max limits are listed in section “1.1. Definition of Test Conditions”.
2. Sensitivity measured at 434 MHz using a PN9 modulated input signal. Received signal is filtered, deglitched, and
retimed using an external RC filter (R = 1 k, C = 47 nF) and MCU.
3. Guaranteed by qualification. Qualification test conditions are listed in section “1.1. Definition of Test Conditions”.
Table 4. Auxiliary Block Specifications1
Parameter
Symbol
Test Condition
Min
—
Typ
10
Max
—
Unit
pF
3
XTAL Nominal Cap
XTAL Frequency
—
—
—
—
—
—
—
—
—
—
30
—
MHz
XTAL Series Resistance
XTAL Stability
—
—
50
—
—
±50
—
ppm
ms
2
Reset to RX Time
t
—
20
RST
Notes:
1. Test conditions and max limits are listed in section in “1.1. Definition of Test Conditions”.
2. Guaranteed by qualification. Qualification test conditions are listed in the "Qualification Test Conditions" subsection of
section “1.1. Definition of Test Conditions”.
3. Targeted nominal capacitive load for both XIN and XOUT pins.
Rev 1.1
5
Si4356
Table 5. Digital I/O Specifications (STBY, RX_DATA, MSTAT, CLK_OUT)1
Parameter
Rise Time
Symbol
Test Condition
0.1xV to 0.9xV ,
DD
Min
Typ
Max
Unit
T
—
2.3
—
ns
RISE
DD
C =10pF, DRV<1:0≥HH
L
Fall Time
T
0.9xV to 0.1xV
,
DD
—
–
2.0
—
ns
FALL
DD
C =10pF, DRV<1:0≥HH
L
Input Capacitance
C
V
—
—
2
–
—
—
pF
V
IN
Logic High Level Input
Voltage
V
x0.7
DD
IH
Logic Low Level Input
Voltage
V
—
—
—
V
x0.3
DD
V
IL
2
Input Current (STBY)
I
0<V <V
DD
–10
1
—
—
10
µA
µA
IN
IN
2
Input Current (STBY)
I
V = 0 V
10
—
INP
IL
Drive Strength for Out-
I
RX_DATA, MSTAT, CLK_OUT
RX_DATA, MSTAT
CLK_OUT
—
1.13
mA
OL
OH
OH
2, 3
put Low Level
Drive Strength for Out-
I
I
—
—
0.96
0.80
–
—
—
—
mA
mA
V
2, 3
put High Level
Drive Strength for Out-
2, 3
put High Level
Logic High Level Out-
put Voltage
V
I
= 500 µA
= 500 µA
V
x0.8
DD
OH
OUT
OUT
Logic Low Level Out-
put Voltage
V
I
—
—
V
x0.2
DD
V
OL
CLK_OUT Frequency
F
Rx Freq = 315 MHZ
All other frequencies
—
—
—
—
10
15
50
—
—
—
MHz
MHz
%
CLK
CLK_OUT Duty Cycle
—
Notes:
1. Guaranteed by qualification. Qualification test conditions are listed in Section “1.1. Definition of Test Conditions”.
2. Currents listed are during normal operation after power up sequence is complete.
3. Output currents measured at 3.3 VDC VDD with VOH = 2.64 VDC and VOL = 0.66 VDC.
Table 6. Thermal Characteristics
Parameter
Symbol
Test Condition
Value
Unit
Still Air
Thermal Resistance Junction to Ambient
30
C/W
JA
6
Rev 1.1
Si4356
Table 7. Absolute Maximum Ratings
Parameter
Value
Unit
V
to GND
–0.3 to +3.6
V
DD
Voltage on Digital Control Inputs
Voltage on Analog Inputs
RX Input Power
–0.3 to V + 0.3
V
V
DD
–0.3 to V + 0.3
DD
+10
dBm
C
Operating Ambient Temperature Range T
–40 to +85
–55 to +125
A
Storage Temperature Range T
C
STG
Note: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These
are stress ratings only and functional operation of the device at or beyond these ratings in the operational sections of
the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability. Caution: ESD sensitive device.
Rev 1.1
7
Si4356
1.1. Definition of Test Conditions
Production Test Conditions:
T = +25 °C
A
V
= +3.3 VDC
DD
External reference signal (XIN) = 1.0 V at 30 MHz, centered around 0.8 VDC
PP
Production test schematic (unless noted otherwise)
All RF input levels referred to the pins of the Si4356 (not the RF module)
Qualification Test Conditions:
T = –40 to +85 °C (typical = 25 °C)
A
V
= +1.8 to +3.6 VDC (typical = 3.3 VDC)
DD
Using reference design or production test schematic
All RF input levels are referred to the antenna port of Si4356 reference design or to the pins of the Si4356
when the production test setup is used.
8
Rev 1.1
Si4356
2. Typical Applications Circuit
30 MHz
C3
SEL1
GND
RST
1
2
15
14
RX_DATA/OUT1
STBY
L2
L1
Si4356
RXp
RXn
13
12
3
4
C1
C2
MSTAT/OUT0
SEL0
NC
5
11
VDD
C4
C5
C6
100 pF
100 nF
1 F
Figure 1. Si4356 Applications Circuit
Table 8. Si4356 Recommended Matching Values
Frequency
(MHz)
C1
(pF)
C2
(pF)
C3
(pF)
L1
(nH)
L2
(nH)
433.92
315.00
434.15
867.84
868.30
917.00
270
470
270
68
2.7
3.0
2.7
1.2
1.2
1.0
5.1
6.2
5.1
3.0
3.0
3.0
56
56
100
56
82
56
22
18
56
22
18
56
22
18
Note: Multi-layer inductors and ceramic chip capacitors with tolerance of ±5% are recommended.
Rev 1.1
9
Si4356
Figure 2 shows the application circuit for a particular radio configuration (433.92 MHz, OOK, 2 kbps, 206 kHz
RxBW) with all optional connections. See Sections 5 and 7 for Si4356 pin functionality.
30 MHz
R11
10 kꢀ
VDD
C3
GND
RST
5.1 pF
SEL1
Reset (Optional)
1
2
3
15
14
13
RX_DATA/OUT12
Data In
L1
56 nH
L2
56 nH
Si4356
STBY
RXp
RXn
Rx STBY (Optional)
Mode Status (Optional)
MSTAT/OUT0
SEL0
C1
270 pF
C2
2.7 pF
4
5
12
11
NC
MCU
Clock In (Optional)
VDD
C4
Optional RC Filter2
C5
C6
1 μF
100 pF
100 nF
R2
C7
Note:
1. R1 is required to minimize power up current. R1 is only necessary for pin configurations where SEL2 or SEL3 is
mapped to GND.
2. An optional external low-pass RC filter may be connected to RX_DATA to filter the output and improve sensitivity.
R2 and C7 should be selected to realize a cut-off frequency that is ~40% larger than that targeted data rate
according to fc = 1/(2RC).
Figure 2. Si4356 Application Circuit Example
10
Rev 1.1
Si4356
3. Device Configuration
The Si4356 is configured for operation using the four configuration selector pins (SEL0 – SEL3). These pins will be
connected to one of four possible inputs: GND, VDD, RX DATA/OUT1 (pin 14), or OUT0 (pin 12). Refer to the
tables below for how these pins should be connected for the desired configuration.
SEL0 and SEL1 may be connected to VDD, GND, or OUT1 to choose desired frequency. Note that a 10 k
resistor should be inserted between SEL1 and OUT1 when SEL1 is mapped to OUT1. See Table 9 for frequency
settings.
Table 9. Frequency Selection
SEL0
GND
VDD
SEL1
VDD
Frequency (MHz)
433.92
VDD
315.00
OUT1
GND
VDD
VDD
434.15
OUT1
OUT1
OUT1
867.84
868.30
OUT1
917.00
SEL2 and SEL3 may be connected to VDD, GND, or OUT1 to choose desired modem configuration. See Table 10
for basic configurations. Note that a 10 k resistor should inserted between SEL2 and/or SEL3 and GND when
SEL2 and/or SEL3 are mapped to GND.
Table 10. Basic Configuration
Config. SEL2
Name
SEL3
Mod
Data Rate RxBW (kHz)
(kbps)
Squelch
Recommended
(kHz)
F
DEV
OOK1
OOK2
GND
VDD
GND
GND
GND
GND
VDD
OOK
OOK
0.5–5
1–10
206
370
370
370
535
100
155
185
275
275
535
155
275
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Enabled
Enabled
—
—
—
—
—
—
30
70
30
70
70
30
30
OOK3 OUT1
OOK4 OUT0
OOK
10–50
OOK
50–120
50–120
0.5–2.4
0.5–30
0.5–30
0.5–30
10–120
10–120
0.5–2.4
0.5–2.4
OOK5
OOK6
FSK1
FSK2
FSK3
FSK4
FSK5
FSK6
FSK7
GND
VDD
GND
VDD
OOK
VDD
OOK
OUT1
OUT1
(G)FSK
(G)FSK
(G)FSK
(G)FSK
(G)FSK
(G)FSK
(G)FSK
OUT1 OUT1
OUT0 OUT1
GND
VDD
OUT0
OUT0
OUT1 OUT0
Rev 1.1
11
Si4356
To disable the system clock, connect CLK_OUT to OUT0. Otherwise, CLK_OUT is enabled. See Table 11 settings.
Table 11. System Clock
CLK_OUT (Pin 10)
Clock Output
OUT0
X
OFF
ON
12
Rev 1.1
Si4356
4. Functional Description
XIN XOUT
RST
Synthesizer
CLK_OUT
÷
30MHz XO
ADC
Rx Chain
STBY
RXp
LNA
PGA
Rx Modem
RX_DATA / OUT1
MSTAT / OUT0
RXn
Configuration Decoder
SEL0 SEL1 SEL2 SEL3
VDD
GND
Figure 3. Si4356 Functional Block Diagram
The Si4356 is an easy-to-use, size efficient, low current wireless receiver that covers the sub-GHz bands. The wide
operating voltage range of 1.8–3.6 V and low current consumption make the Si4356 an ideal solution for battery
powered applications. The Si4356 uses a single-conversion mixer to downconvert the (G)FSK or OOK modulated
receive signal to a low IF frequency. Following a programmable gain amplifier (PGA), the signal is converted to the
digital domain by a high performance ADC, thus allowing filtering and demodulation to be performed in the
built-in DSP and increasing the receiver's performance and flexibility versus analog based architectures. The
receiver demodulates the incoming data asynchronously by oversampling the incoming transmission. The resulting
demodulated signal is output to the system MCU through data output pin RX_DATA.
Integrated configuration tables allow the Si4356 to be completely configured using the four selector pins. The state
of each of these pins is read internally at startup and used to determine which pre-loaded configuration should be
used. The Si4356 then loads this configuration without the need for any external MCU control.
The Si4356 includes an integrated crystal oscillator. The design is differential with the typical crystal load
capacitance integrated on-chip to accommodate a 30 MHz off-chip crystal.
Rev 1.1
13
Si4356
5. Modes and Timing
At initial startup, the Si4356 reads the selector pins and loads all registers with the appropriate values for the
selected configuration, as shown in the Figure 4.
VDD
12 mA
9 mA
3 ms
Total
3 mA
2.5 mA
10 ms
Current
2 mA
1ms
8.5 ms
MSTAT
(Pin12)
RX_ DATA
(Pin14)
2.9 Vp-p
CLK_OUT
(Pin10)
Figure 4. Power Up Timing
14
Rev 1.1
Si4356
The Si4356 provides two operating modes, a receive mode and a standby mode. The operating mode can be
changed by toggling STBY (pin 13) as described in Figure 5. Care should be taken to minimize the trace connected
to STBY to avoid external noise coupling that could result in unintended mode changes. The MSTAT signal (pin 12)
indicates the current operating mode of the device as defined in Table 12 and illustrated in Figure 5.
Table 12. Operating Mode Status
Pin 12 (MSTAT)
LOW
Mode
Receive
Standby
HIGH
STBY
(Pin13)
>250 µS
>2 ms
12 mA
12 mA
Total
Current
3 mA
50 nA
450 µS
1-2 ms
MSTAT
(Pin12)
RX_DATA
(Pin14)
350 µS
2.9Vp-p
CLK_OUT
(Pin10)
Figure 5. Standby Control and Timing
Once in standby mode, the device shuts down most functions, allowing for very low current consumption, but it still
maintains all register settings for a fast transition back to the receive operating mode, as shown in Table 13.
Table 13. Operating State Response Time and Current Consumption
State / Mode
Standby
Response Time to Rx
Current in State/Mode
0.5 ms
N/A
50 nA
Receive
12 mA
Rev 1.1
15
Si4356
It is also possible to reset the device by using RST (pin 2). This mode briefly cycles power on the device, before
retuning the device to the receive operating mode as shown in Figure 6. The device takes approximately 20 ms to
transition from reset to Receive mode.
RST
(Pin2)
>1 ms
12mA
12mA
9mA
Total
Current
3mA
2.5mA
10ms
2mA
1ms
8.5ms
MSTAT
(Pin12)
RX_ DATA
(Pin14)
2.9Vp-p
CLK_OUT
(Pin10)
Figure 6. Device Reset Control and Timing
6. Additional Features
6.1. System Clock Output
A clock output is available on CLK_OUT (pin 10) of the Si4356, which can be used to drive an external MCU and
avoid the need for additional oscillators in the application. The clock signal is valid when MSTAT is low. The clock
frequency is set to 10 MHz for 315 MHz RX frequency selection and 15 MHz for all other frequencies. If this clock
signal is not needed, then it can be turned off by connecting CLK_OUT (pin 10) to MSTAT/OUT0 (pin 12). The
clock signal is turned off during Standby and Device Reset modes.
16
Rev 1.1
Si4356
7. Pin Descriptions
GND
1
2
3
4
5
6
20 19 18 17 16 GND
15 SEL1
RST
RXp
RXn
NC
14 RX_DATA / OUT1
GND
13 STBY
12 MSTAT / OUT0
GND
7
8
9
10 11 SEL0
Pin
1
Pin Name
GND
I/O
Description
GND
Ground
Device reset
2
RST
I
I
I
3
RXp
Differential RF receiver input pin
Differential RF receiver input pin
No Connect
4
RXn
5
NC
6
GND
GND
Ground
7
VDD
V
Supply Voltage
DD
8
VDD
V
Supply Voltage
DD
9
GND
GND
Ground
10
11
CLK_OUT
SEL0
O
I
System reference clock output
Configuration selector pin
MSTAT
OUT0
O
O
Mode status (Rx = 0, STBY = 1)
Configuration output pin
12
13
14
15
STBY
I
Standby mode toggle
RX_DATA
OUT1
O
O
Receiver raw data output
Configuration output pin
SEL1
I
Configuration selector pin
Rev 1.1
17
Si4356
Pin
16
17
18
19
20
Pin Name
GND
I/O
Description
GND
GND
XOUT
XIN
O
I
Crystal oscillator output
Crystal oscillator input
Configuration selector pin
Configuration selector pin
SEL2
SEL3
I
I
18
Rev 1.1
Si4356
8. Ordering Information
*
Description
Package Type
Operating
Temperature
Part Number
Si4356-B1A-FM
Si4356 EZRadio Standalone Receiver
3x3 QFN-20
Pb-free
–40 to 85 °C
*Note: Add an “R” at the end of the device part number to denote tape and reel option.
Rev 1.1
19
Si4356
9. Package Outline
Figure 7. 20-pin QFN Package
20
Rev 1.1
Si4356
Table 14. Package Diagram Dimensions
Dimension
Min
0.80
0.00
Nom
0.85
Max
0.90
0.05
A
A1
A3
b
0.02
0.20 REF
0.25
0.18
0.25
0.30
0.35
c
0.30
D
3.00 BSC.
1.70
D2
e
1.55
1.85
0.50 BSC.
3.00 BSC.
1.70
E
E2
f
1.55
0.30
1.85
0.50
2.40 BSC.
0.40
L
aaa
bbb
ccc
ddd
eee
fff
0.15
0.10
0.10
0.05
0.08
0.10
Note: All dimensions shown are in millimeters (mm) unless otherwise noted.
Rev 1.1
21
Si4356
10. PCB Land Pattern
Figure 8. 20-pin QFN PCB Land Pattern (Top View)
Table 15. PCB Land Pattern Dimensions
Dimension
Min
Max
C1
C2
E
3.00
3.00
0.50 REF
X1
X2
Y1
Y2
Y3
f
0.25
1.65
0.85
1.65
0.37
0.35
1.75
0.95
1.75
0.47
2.40 REF
c
0.25
0.35
Note: : All dimensions shown are in millimeters (mm) unless otherwise noted.
22
Rev 1.1
Si4356
11. Top Marking
11.1. Si4356 Top Marking
Figure 9. Si4356 Top Marking
11.2. Top Marking Explanation
Mark Method:
Pin 1 Mark
Laser
Circle = 0.5 mm Diameter
0.6 mm Right Justified
Product ID
Font Size
Line 1 Marking:
Line 2 Marking:
Line 3 Marking:
356A
TTTT = Trace Code
YWW = Date Code
Internal tracking number
Corresponds to the last digit of the current year (Y) and the
work week (WW) of the assembly date.
Rev 1.1
23
Si4356
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Please visit the Silicon Labs Technical Support web page:
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
Patent Notice
Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, ana-
log-intensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering
team.
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed fea-
tures or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warran-
ty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intend-
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Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
24
Rev 1.1
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