SI4702-B16-GMR [SILICON]
Audio Demodulator, 3 X 3 MM, ROHS COMPLIANT, QFN-20;
| 型号： | SI4702-B16-GMR |
| 厂家： | 
SILICON |
| 描述： | Audio Demodulator, 3 X 3 MM, ROHS COMPLIANT, QFN-20 商用集成电路 |
| 文件： | 总46页 (文件大小：1450K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si4702/03-C19
BROADCAST FM RADIO TUNER FOR PORTABLE APPLICATIONS
Features
This data sheet applies to
Si4702/03-C Firmware 19 and
greater
Adaptive noise suppression
Volume control
Line-level analog output
32.768 kHz reference clock
Worldwide FM band support
(76–108 MHz)
2-wire and 3-wire control
interface
Digital low-IF receiver
Frequency synthesizer with
integrated VCO
2.7 to 5.5 V supply voltage
Ordering Information:
Integrated LDO regulator
allows direct connection to
battery
Seek tuning
See page 38.
Automatic frequency control (AFC)
Automatic gain control (AGC)
Excellent overload immunity
Signal strength measurement
3 x 3 mm 20-pin QFN package
Pb-free/RoHS compliant
Pin Assignments
(Top View)
RDS/RBDS Processor (Si4703)
Integrated crystal oscillator
Programmable de-emphasis
Si4702/03-GM
(50/75 µs)
Applications
Cellular handsets
MP3 players
USB FM radio
Portable navigation
1
2
20
19
18
17 16
15 GND
NC
PDAs
Consumer electronics
FMIP
Portable radios
Notebook PCs
RFGND
GND
3
4
14
13
LOUT
ROUT
GND
PAD
Description
The Si4702/03 integrates the complete tuner function from antenna input
to stereo audio output for FM broadcast radio reception.
RST
5
6
12 GND
11 VD
7
8
9
10
Functional Block Diagram
Headphone
Si4702/03
Cable
U.S. and International Patents
pending—Abbreviated U.S. Patent
List:
DSP
I
LOUT
DAC
DAC
GPIO
ADC
FMIP
FILTER
DEMOD
MPX
LNA
PGA
RFGND
Q
ADC
ROUT
GPIO
7272375, 7127217, 7272373,
7272374, 7321324, 7339503,
7339504, 7355476, 7426376,
7436252, 7471940
AUDIO
AGC
TUNE
REG
0 / 90
LOW-IF
32.768 kHz
2.7–5.5 V
VIO
RST
RCLK
RDS
(Si4703)
AFC
SDIO
SCLK
SEN
VA
VD
XTAL
OSC
RSSI
Rev. 1.1 7/09
Copyright © 2009 by Silicon Laboratories
Si4702/03-C19
2
Rev. 1.1
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
4.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
4.2. FM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
4.3. General Purpose I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.4. RDS/RBDS Processor and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.5. Stereo Audio Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.6. Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.7. Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.8. Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.9. Reset, Powerup, and Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.10. Audio Output Summation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.11. Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.12. Programming Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
5. Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
6. Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
7. Pin Descriptions: Si4702/03-C19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
9. Package Markings (Top Marks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
9.1. Si4702 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
9.2. Si4703 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
9.3. Top Mark Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
10. Package Outline: Si4702/03-C19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
11. PCB Land Pattern: Si4702/03-C19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Additional Reference Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Rev. 1.1
3
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol
Test Condition
Min
2.7
2.7
1.5
10
Typ
—
Max
5.5
5.5
3.6
—
Unit
V
Digital Supply Voltage
Analog Supply Voltage
Interface Supply Voltage
V
D
V
—
V
A
V
—
V
IO
Digital Power Supply Power-Up
Rise Time
V
—
µs
DRISE
Analog Power Supply Power-Up
Rise Time
V
10
10
—
—
25
—
—
85
µs
µs
°C
ARISE
Interface Power Supply Power-Up
Rise Time
V
IORISE
Ambient Temperature
T
–20
A
Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at VD = VA = 3.3 V and 25 °C unless otherwise stated. Parameters are tested in production unless
otherwise stated.
Table 2. Absolute Maximum Ratings1,2
Parameter
Symbol
Value
–0.5 to 5.8
–0.5 to 5.8
–0.5 to 3.9
±10
Unit
V
Digital Supply Voltage
Analog Supply Voltage
Interface Supply Voltage
V
D
V
V
A
V
V
IO
IN
3
Input Current
I
mA
V
3
Input Voltage
V
–0.3 to (V + 0.3)
IN
IO
Operating Temperature
Storage Temperature
T
–40 to 95
–55 to 150
0.4
°C
°C
OP
T
STG
4
RF Input Level
V
pK
Notes:
1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure beyond
recommended operating conditions for extended periods may affect device reliability.
2. The Si4702/03-C19 device is a high-performance RF integrated circuit with an ESD rating of < 2 kV HBM. Handling
and assembly of this device should only be done at ESD-protected workstations.
3. For input pins SCLK, SEN, SDIO, RST, RCLK, GPIO1, GPIO2, and GPIO3.
4. At RF input pins.
4
Rev. 1.1
Table 3. DC Characteristics1
(VD = VA = 2.7 to 3.6 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
ENABLE = 1
ENABLE = 1
ENABLE = 1
Min
—
Typ
10.8
3.3
Max
—
Unit
mA
mA
mA
2
Analog Operating Supply Current
I
A
D
2
Digital Operating Supply Current
I
—
—
Interface Operating Supply
I
—
0.3
—
IO
2
Current
Total Operating Supply
Current
I
ENABLE = 1
Low SNR signal
—
15.3
16.8
mA
OP
2,3,4,5
Total Operating Supply
Current
I
I
ENABLE = 1
—
—
14.4
14.9
15.9
16.4
mA
mA
OP
OP
2,3,4
Total Operating Supply
ENABLE = 1
RDS = 1
2,3,4,6
Current
Total Operating Supply
Current
I
ENABLE = 1
RDS = 1,
—
15.8
16.8
mA
OP
2,3,4,6
Low SNR signal
2,7
Analog Powerdown Supply Current
I
ENABLE = 0
ENABLE = 0
—
—
—
3.5
2.5
2.5
—
—
—
µA
µA
µA
APD
2,7
Digital Powerdown Supply Current
I
DPD
Interface Powerdown Supply
I
ENABLE = 0
SCLK, RCLK inactive
IOPD
2,7
Current
2,7
Total Powerdown Supply Current
I
ENABLE = 0
—
0.7 x V
–0.3
8.5
—
—
—
—
12.0
µA
V
PD
8
High Level Input Voltage
V
V
+ 0.3
IO
IH
IO
8
Low Level Input Voltage
V
0.3 x V
10
V
IL
IO
8
High Level Input Current
I
V
= V = 3.6 V
–10
µA
µA
IH
IN
IO
8
Low Level Input Current
I
V
= 0 V,
IN
–10
10
IL
V
= 3.6 V
IO
9
High Level Output Voltage
V
I
= 500 µA
0.8 x V
—
—
—
—
V
V
OH
OUT
OUT
IO
9
Low Level Output Voltage
V
I
= –500 µA
0.2 x V
OL
IO
Notes:
1. All specifications for the Si4702 unless otherwise noted.
2. Refer to Register 02h, "Power Configuration" on page 24 for ENABLE bit description.
3. The LNA is automatically switched to higher current mode for optimum sensitivity in low SNR conditions.
4. Analog and digital supply currents are simultaneously adjusted based on SNR level.
5. Stereo and RDS functionality are disabled at low SNR levels.
6. RDS functionality only available for Si4703.
7. Refer to Section 4.9. "Reset, Powerup, and Powerdown" on page 19.
8. For input pins SCLK, SEN, SDIO, RST, RCLK, GPIO1, GPIO2, and GPIO3.
9. For output pins SDIO, GPIO1, GPIO2, and GPIO3.
Rev. 1.1
5
Table 4. Reset Timing Characteristics (Busmode Select Method 1)1,2,3
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
4
RSTpulse width and GPIO3 Setup
to RST
t
GPIO3 = 0
100
—
—
µs
GSRST1
SEN and SDIO Setup to RST
t
30
30
—
—
—
—
ns
ns
SRST1
SEN, SDIO, and GPIO3 Hold from
t
HRST1
RST
Notes:
1. When selecting 2-wire Mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST.
2. When selecting 3-wire Mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RST.
3. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high
until after the 1st start condition.
4. If GPIO3 is driven low by the user, then minimum tGSRST1 is only 30 ns. If GPIO3 is hi-Z, then minimum tGSRST1 is
100 µs, to provide time for an on-chip 1 M pulldown device (active while RST is low) to discharge the pin.
tGSRST1
tHRST1
70%
30%
RST
70%
30%
GPIO3
tSRST1
70%
30%
SEN,
SDIO
Figure 1. Reset Timing Parameters for Busmode Select Method 1 (GPIO3 = 0)
6
Rev. 1.1
Table 5. Reset Timing Characteristics (Busmode Select Method 2)1,2,3
Parameter
Symbol
Test Condition
Min
30
Typ
—
Max
—
Unit
ns
GPIO1 and GPIO3 Setup to RST
GPIO1 and GPIO3 Hold from RST
Notes:
t
GPIO3 = 1
SRST2
t
30
—
—
ns
HRST2
1. When selecting 2-wire Mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST.
2. When selecting 3-wire Mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RST.
3. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until
after the 1st start condition.
tSRST2 tHRST2
70%
RST
30%
70%
GPIO3
30%
70%
GPIO1
30%
Figure 2. Reset Timing Parameters for Busmode Select Method 2 (GPIO3 = 1)
Rev. 1.1
7
Table 6. 3-Wire Control Interface Characteristics
(VD = VA = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
0
Typ
—
—
—
—
—
—
—
—
—
Max
2.5
—
Unit
MHz
ns
SCLK Frequency
f
CLK
SCLK High Time
t
25
25
20
10
10
10
2
HIGH
SCLK Low Time
t
—
ns
LOW
SDIO Input, SEN to SCLKSetup
SDIO Input to SCLKHold
SEN Input to SCLKHold
SEN Input to SCLKHold
SCLKto SDIO Output Valid
SCLKto SDIO Output High Z
t
—
ns
S
t
t
—
ns
HSDIO
—
ns
HSEN1
HSEN2
t
—
ns
t
Read
Read
25
25
ns
CDV
t
2
ns
CDZ
Note: When selecting 3-wire Mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RST.
70%
SCLK
30%
tHSDIO
tHIGH
tLOW
tHSEN1
tHSEN2
tS
70%
30%
tS
SEN
A6-A5,
R/W,
A4-A1
70%
30%
A7
A0
D15
D14-D1
D0
SDIO
Address In
Data In
Figure 3. 3-Wire Control Interface Write Timing Parameters
8
Rev. 1.1
70%
30%
SCLK
SEN
tHSDIO
tCDV
tHSEN1
tHSEN2
tS
tCDZ
70%
30%
tS
80%
20%
A6-A5,
R/W,
A4-A1
A7
A0
D15
D14-D1
D0
SDIO
½ Cycle Bus
Turnaround
Address In
Data Out
Figure 4. 3-Wire Control Interface Read Timing Parameters
Rev. 1.1
9
Table 7. 2-Wire Control Interface Characteristics1,2,3
(VD = VA = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol Test Condition
Min
0
Typ
—
Max
400
—
Unit
kHz
µs
SCLK Frequency
SCLK Low Time
SCLK High Time
f
SCL
t
1.3
0.6
0.6
—
LOW
t
—
—
µs
HIGH
SCLK Input to SDIO Setup
t
t
—
—
µs
SU:STA
(START)
SCLK Input to SDIO Hold (START)
SDIO Input to SCLK Setup
0.6
100
—
—
—
—
—
—
—
—
—
µs
ns
ns
µs
µs
ns
ns
HD:STA
SU:DAT
t
t
4,5
SDIO Input to SCLK Hold
0
900
—
HD:DAT
SU:STO
SCLK input to SDIO Setup (STOP)
STOP to START Time
t
0.6
t
1.3
—
BUF
SDIO Output Fall Time
t
20 + 0.1 C
20 + 0.1 C
250
300
f:OUT
b
b
SDIO Input, SCLK Rise/Fall Time
t
t
f:IN
r:IN
SCLK, SDIO Capacitive Loading
Input Filter Pulse Suppression
Notes:
C
—
—
—
—
50
50
pF
ns
b
t
SP
1. When VIO = 0 V, SCLK and SDIO are low impedance.
2. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high
until after the 1st start condition.
3. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST.
4. As a 2-wire transmitter, the Si4702/03-C19 delays SDIO by a minimum of 300 ns from the VIH threshold of SCLK to
comply with the 0 ns tHD:DAT specification.
5. The maximum tHD:DAT has only to be met when fSCL = 400 kHz. At frequencies below 400 KHz, tHD:DAT may be
violated so long as all other timing parameters are met.
10
Rev. 1.1
tSU:STA tHD:STA
tLOW
tHIGH
tr:IN
tf:IN
tSP
tSU:STO
tBUF
70%
30%
SCLK
SDIO
70%
30%
tf:IN,
tf:OUT
START
tHD:DAT tSU:DAT
tr:IN
STOP
START
Figure 5. 2-Wire Control Interface Read and Write Timing Parameters
SCLK
SDIO
A6-A0,
R/W
D7-D0
D7-D0
START
ADDRESS + R/W
ACK
DATA
ACK
DATA
ACK
STOP
Figure 6. 2-Wire Control Interface Read and Write Timing Diagram
Rev. 1.1
11
Table 8. FM Receiver Characteristics1,2
(V = V = 2.7 to 5.5 V, V = 1.5 to 3.6 V, TA = –20 to 85 °C)
D
A
IO
Parameter
Symbol
Test Condition
Min
76
—
Typ
—
Max
108
3.5
—
Unit
MHz
Input Frequency
f
RF
3,4,5,6,7
Sensitivity
(S+N)/N = 26 dB
(S+N)/N = 26 dB
1.7
1.1
µVEMF
µVEMF
Sensitivity (50 matching
—
3,4,5,6,8
network)
8
RDS Sensitivity
f = 2 kHz,
—
15
—
µVEMF
RDS BLER < 5%
8,9
LNA Input Resistance
3
4
4
5
5
k
pF
8,9
LNA Input Capacitance
6
8,10
Input IP3
104
40
35
60
35
—
106
55
—
—
—
—
—
—
dBµVEMF
dB
3,4,5,8,9
AM Suppression
m = 0.3
±200 kHz
±400 kHz
In-band
Adjacent Channel Selectivity
Alternate Channel Selectivity
Spurious Response Rejection
RCLK Frequency
50
dB
70
dB
8
—
dB
32.768
kHz
11
RCLK Frequency Tolerance
Frequency Spacing =
100 or 200 kHz
ppm
–200
–50
—
—
200
50
Frequency Spacing =
50 kHz
3,4,5,9
Audio Output Voltage
72
—
—
15
25
80
—
—
—
—
90
1
mV
RMS
3,4,9,12
Audio Output L/R Imbalance
dB
8
–3 dB
–3 dB
30
—
—
Hz
kHz
dB
Audio Frequency Response Low
8
Audio Frequency Response High
3,9,12
Audio Stereo Separation
Notes:
1. Additional testing information is available in Application Note AN234. Volume = maximum for all tests.
2. Important Note: To ensure proper operation and FM receiver performance, follow the guidelines in “AN231:
Si4700/01/02/03 Headphone and Antenna Interface.” Silicon Laboratories will evaluate schematics and layouts for
qualified customers.
3. F
= 1 kHz, 75 µs de-emphasis
MOD
4. MONO = 1, and L = R unless noted otherwise.
5. f = 22.5 kHz.
6. B = 300 Hz to 15 kHz, A-weighted.
AF
7. Typical sensitivity with headphone matching network.
8. Guaranteed by characterization.
9. V
= 1 mV.
EMF
10. |f – f | > 1 MHz, f = 2 x f – f . AGC is disabled by setting AGCD = 1. Refer to "6. Register Descriptions" on page 23.
2
1
0
1
2
11. The channel spacing is selected with the SPACE[1:0] bits. Refer to "6. Register Descriptions" on page 23. Seek/Tune
timing is guaranteed for 100 and 200 kHz channel spacing.
12. f = 75 kHz.
13. The de-emphasis time constant is selected with the DE bit. Refer to "6. Register Descriptions" on page 23.
14. At LOUT and ROUT pins.
15. Do not enable STC interrupts before the powerup time is complete. If STC interrupts are enabled before the powerup
time is complete, an interrupt will be generated within the powerup interval when the initial default tune operation is
complete. See "AN230: Si4700/01/02/03 Programmer’s Guide" for more information.
16. Minimum and maximum at room temperature (25 °C).
12
Rev. 1.1
Table 8. FM Receiver Characteristics1,2 (Continued)
(V = V = 2.7 to 5.5 V, V = 1.5 to 3.6 V, TA = –20 to 85 °C)
D
A
IO
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
BLNDADJ = 10
10 dB stereo separation
3,8,12
Mono/Stereo Switching Level
—
34
—
dBµVEMF
3,4,5,6,9
Audio Mono S/N
55
—
60
58
—
—
dB
dB
%
3,5,6,8
Audio Stereo S/N
BLNDADJ = 10
3,4,9,12
Audio THD
—
0.1
75
0.5
80
54
0.9
13
De-emphasis Time Constant
DE = 0
DE = 1
70
µs
µs
V
45
50
14
Audio Common Mode Voltage
ENABLE = 1
0.65
0.8
ENABLE = 0
AHIZEN = 1
14
8,14
Audio Common Mode Voltage
—
0.5 x V
—
V
IO
Audio Output Load Resistance
R
Single-ended
Single-ended
10
—
—
—
—
—
—
50
60
k
L
8,14
Audio Output Load Capacitance
C
pF
L
8,11
Seek/Tune Time
SPACE[1:0] = 0x, RCLK
tolerance = 200 ppm,
(x = 0 or 1)
ms/
channel
15
Powerup Time
From powerdown
(Write ENABLE bit to 1)
—
—
—
110
3
ms
dB
16
RSSI Offset
Input levels of 8 and
60 dBµV at RF input
–3
Notes:
1. Additional testing information is available in Application Note AN234. Volume = maximum for all tests.
2. Important Note: To ensure proper operation and FM receiver performance, follow the guidelines in “AN231:
Si4700/01/02/03 Headphone and Antenna Interface.” Silicon Laboratories will evaluate schematics and layouts for
qualified customers.
3. F
= 1 kHz, 75 µs de-emphasis
MOD
4. MONO = 1, and L = R unless noted otherwise.
5. f = 22.5 kHz.
6. B = 300 Hz to 15 kHz, A-weighted.
AF
7. Typical sensitivity with headphone matching network.
8. Guaranteed by characterization.
9. V
= 1 mV.
EMF
10. |f – f | > 1 MHz, f = 2 x f – f . AGC is disabled by setting AGCD = 1. Refer to "6. Register Descriptions" on page 23.
2
1
0
1
2
11. The channel spacing is selected with the SPACE[1:0] bits. Refer to "6. Register Descriptions" on page 23. Seek/Tune
timing is guaranteed for 100 and 200 kHz channel spacing.
12. f = 75 kHz.
13. The de-emphasis time constant is selected with the DE bit. Refer to "6. Register Descriptions" on page 23.
14. At LOUT and ROUT pins.
15. Do not enable STC interrupts before the powerup time is complete. If STC interrupts are enabled before the powerup
time is complete, an interrupt will be generated within the powerup interval when the initial default tune operation is
complete. See "AN230: Si4700/01/02/03 Programmer’s Guide" for more information.
16. Minimum and maximum at room temperature (25 °C).
Rev. 1.1
13
2. Typical Application Schematic
GPIO1
GPIO2
GPIO3
1
15
14
13
12
11
GND
LOUT
ROUT
GND
VD
NC
2
FMIP
LOUT
ROUT
FMIP
RFGND
GND
3
4
5
GND
PAD
RFGND
VBATTERY
2.7 to 5.5 V
RST
C1
RST
SEN
X1
GPIO3
RCLK
SCLK
SDIO
RCLK
VIO
C2
C3
Optional: for crystal oscillator option
1.5 to 3.6 V
Notes:
1. Place C1 close to V pin.
D
2. All grounds connect directly to GND plane on PCB.
3. Pins 1 and 20 are no connects, leave floating.
4. Important Note: FM Receiver performance is subject to adherence to antenna design guidelines in “AN231:
Si4700/01/02/03 Headphone and Antenna Interface.” Failure to use these guidelines will negatively affect the
performance of the Si4702/03-C19, particularly in weak signal and noisy environments. Silicon Laboratories will evaluate
schematics and layouts for qualified customers.
5. Pin 2 connects to the antenna interface, refer to “AN231: Si4700/01/02/03 Headphone and Antenna Interface.”
6. Place Si4702/03-C19 as close as possible to antenna jack and keep the FMIP trace as short as possible.
7. Refer to Si4702/03 Internal Crystal Oscillator Errata.
8. Refer to "AN299: External 32.768 kHz Crystal Oscillator."
3. Bill of Materials
Component(s)
Value/Description
Supplier(s)
C1
Supply bypass capacitor, 22 nF, ±20%, Z5U/X7R
Si4702/03-C19 FM Radio Tuner
Murata
U1
Silicon Laboratories
Venkel
C2, C3
Crystal load capacitors, 22 pF, ±5%, COG (Optional: for
crystal oscillator option)
X1
32.768 kHz crystal (Optional: for crystal oscillator option)
Epson
14
Rev. 1.1
4. Functional Description
Headphone
Cable
Si4702/03
DSP
I
LOUT
DAC
DAC
GPIO
ADC
FMIP
FILTER
DEMOD
MPX
LNA
PGA
RFGND
Q
ADC
ROUT
GPIO
AUDIO
AGC
0 / 90
LOW-IF
32.768 kHz
VIO
RST
RCLK
TUNE
RDS
(Si4703)
AFC
SDIO
SCLK
SEN
2.7 - 5.5 V
VA
VD
XTAL
OSC
REG
RSSI
Figure 7. Si4702/03-C19 FM Receiver Block Diagram
by leading cell-phone and MP3 manufacturers
world-wide.
4.1. Overview
The Si4702/03-C19 extends Silicon Laboratories
Si4700/01 FM tuner family, and further increases the
ease and attractiveness of adding FM radio reception to
mobile devices through small size and board area,
minimum component count, flexible programmability,
and superior, proven performance. Si4702/03-C19
software is backwards compatible to existing Si4700/01
and Si4702/03-B16 FM Tuner designs. The
Si4702/03-C19 benefits from proven digital integration
The Si4702/03-C19 is based on the superior, proven
performance of Silicon Laboratories' Aero architecture
offering unmatched interference rejection and leading
sensitivity. The device uses the same programming
interface as the Si4701 and supports multiple
bus-modes. Power management is also simplified with
an integrated regulator allowing direct connection to a
2.7 to 5.5 V battery.
and 100% CMOS process technology, resulting in a The Si4702/03-C19 device’s high level of integration
completely integrated solution. It is the industry's and complete FM system production testing increases
2
smallest footprint FM tuner IC requiring only 10 mm
board space and one external bypass capacitor.
quality to manufacturers, improves device yields, and
simplifies device manufacturing and final testing.
The device offers significant programmability, and
caters to the subjective nature of FM listeners and
variable FM broadcast environments world-wide
through a simplified programming interface and mature
functionality.
4.2. FM Receiver
The
Si4702/03-C19’s
patented
digital
low-IF
architecture reduces external components and
eliminates the need for factory adjustments. The receive
(RX) section integrates a low noise amplifier (LNA)
supporting the worldwide FM broadcast band (76 to
108 MHz). An automatic gain control (AGC) circuit
controls the gain of the LNA to optimize sensitivity and
rejection of strong interferers. For testing purposes, the
AGC can be disabled with the AGCD bit. Refer to
Section 6. "Register Descriptions" on page 23 for
additional programming and configuration information.
The Si4703-C incorporates a digital processor for the
European Radio Data System (RDS) and the US Radio
Broadcast Data System (RBDS) including all required
symbol decoding, block synchronization, error
detection, and error correction functions.
RDS enables data such as station identification and
song name to be displayed to the user. The Si4703-C
offers a detailed RDS view and a standard view,
allowing adopters to selectively choose granularity of
RDS status, data, and block errors. Si4703-C software
is backwards compatible to the proven Si4701, adopted
The Si4702/03-C19 architecture and antenna design
increases system performance. To ensure proper
performance and operation, designers should refer to
the guidelines in "AN231: Si4700/01/02/03 Headphone
Rev. 1.1
15
and Antenna Interface". Conformance to these (RDSS) and block error rate A, B, C and D (BLERA,
guidelines will help to ensure excellent performance BLERB, BLERC, and BLERD) are unused and will read
even in weak signal or noisy environments.
0. This mode is backward compatible with earlier
firmware revisions.
An image-reject mixer downconverts the RF signal to
low-IF. The quadrature mixer output is amplified, Setting the RDS mode bit high places the device in RDS
filtered, and digitized with high resolution verbose mode. The device sets RDSS high when
analog-to-digital converters (ADCs). This advanced synchronized and low when synchronization is lost. If
architecture achieves superior performance by using the device is synchronized, RDS ready (RDSR) will be
digital signal processing (DSP) to perform channel set for a minimum of 40 ms when a RDS group has
selection, FM demodulation, and stereo audio been received. Setting the RDS interrupt enable
processing
architectures.
compared
to
traditional
analog (RDSIEN) bit and GPIO2[1:0] = 01 will configure GPIO2
to pulse low for a minimum of 5 ms if the device is
synchronized and an RDS group has been received.
BLERA, BLERB, BLERC and BLERD provide
4.3. General Purpose I/O Pins
The pins GPIO1–3 can serve multiple functions. GPIO1 block-error levels for the RDS group. The number of bit
and GPIO3 can be used to select between 2-wire and errors in each block within the group is encoded as
3-wire modes for the control interface as the device is follows: 00 = no errors, 01 = one to two errors,
brought out of reset. See Section “4.9. Reset, Powerup, 10 = three to five errors, 11 = six or more errors. Six or
and Powerdown”. After powerup of the device, the more errors in
a
block indicate the block is
GPIO1–3 pins can be used as general purpose uncorrectable and should not be used.
inputs/outputs, and the GPIO2–3 pins can be used as
interrupt request pins for the seek/tune or RDS ready
functions and as a stereo/mono indicator respectively.
See register 04h, bits [5:0] in Section “6. Register
Descriptions” for information on the control of these
pins. It is recommended that the GPIO2–3 pins not be
used as interrupt request outputs until the powerup time
has completed (see Section “4.9. Reset, Powerup, and
Powerdown”). The GPIO3 pin has an internal, 1 M,
±15% pull-down resistor that is only active while RST is
low. General purpose input/output functionality is
*Note: RDS/RBDS is referred to only as RDS throughout the
remainder of this document.
4.5. Stereo Audio Processing
The output of the FM demodulator is a stereo
multiplexed (MPX) signal. The MPX standard was
developed in 1961 and is used worldwide. Today's MPX
signal format consists of left + right (L+R) audio, left –
right (L–R) audio, a 19 kHz pilot tone, and RDS/RBDS
data as shown in Figure 8.
available regardless of the state of the V and V
A
D
supplies, or the ENABLE and DISABLE bits.
4.4. RDS/RBDS Processor and
Functionality
Mono Audio
Left + Right
Stereo
Pilot
Stereo Audio
Left - Right
RDS/
RBDS
The Si4703 implements an RDS/RBDS* processor for
symbol decoding, block synchronization, error
detection, and error correction. RDS functionality is
enabled by setting the RDS bit. The device offers two
RDS modes, a standard mode and a verbose mode.
The primary difference is increased visibility to RDS
block-error levels and synchronization status with
verbose mode.
0
15 19 23
38
53 57
Frequency (kHz)
Figure 8. MPX Signal Spectrum
The Si4702/03-C19's integrated stereo decoder
automatically decodes the MPX signal. The 0 to 15 kHz
(L+R) signal is the mono output of the FM tuner. Stereo
is generated from the (L+R), (L-R), and a 19 kHz pilot
tone. The pilot tone is used as a reference to recover
the (L-R) signal. Separate left and right channels are
obtained by adding and subtracting the (L+R) and (L-R)
signals, respectively. The Si4703-C uses frequency
information from the 19 kHz stereo pilot to recover the
57 kHz RDS/RBDS signal.
Setting the RDS mode (RDSM) bit low places the
device in standard RDS mode (default). The device will
set the RDS ready (RDSR) bit for a minimum of 40 ms
when a valid RDS group has been received. Setting the
RDS interrupt enable (RDSIEN) bit and GPIO2[1:0] = 01
will configure GPIO2 to pulse low for a minimum of 5 ms
when a valid RDS group has been received. If an invalid
group is received, RDSR will not be set and GPIO2 will
not pulse low. In standard mode RDS synchronization
Adaptive noise suppression is employed to gradually
16
Rev. 1.1
combine the stereo left and right audio channels to a completes, the seek/tune complete (STC) bit will be set
mono (L+R) audio signal as the signal quality degrades and the RSSI level is available by reading bits
to maintain optimum sound fidelity under varying RSSI[7:0]. The TUNE bit must be set low after the STC
reception conditions. The signal level range over which bit is set high in order to complete the tune operation
the stereo to mono blending occurs can be adjusted by and clear the STC bit.
setting the BLNDADJ[1:0] register. Stereo/mono status
can be monitored with the ST register bit and mono
RSSI greater than or equal to the seek threshold set
operation can be forced with the MONO register bit.
Seek tuning searches up or down for a channel with an
with the SEEKTH[7:0] bits. In addition, optional SNR
Pre-emphasis and de-emphasis is a technique used by and/or impulse noise detector criteria may be used to
FM broadcasters to improve the signal-to-noise ratio of qualify valid stations. The SKSNR[3:0] bits set the SNR
FM receivers by reducing the effects of high frequency threshold required. The SKCNT[3:0] bits set the impulse
interference and noise. When the FM signal is noise threshold. Using the extra seek qualifiers can
transmitted,
a
pre-emphasis filter is applied to reduce false stops and, in combination with lowering the
accentuate the high audio frequencies. All FM receivers RSSI seek threshold, increase the number of found
incorporate a de-emphasis filter which attenuates high stations. The SNR and impulse noise detectors are
frequencies to restore a flat frequency response. Two disabled by default for backwards compatibility.
time constants, 50 or 75 µs, are used in various regions.
The de-emphasis time constant is programmable with
(SKMODE) bit is low and a seek is initiated, the device
the DE bit.
Two seek modes are available. When the seek mode
seeks through the band, wraps from one band edge to
High-fidelity stereo digital-to-analog converters (DACs) the other, and continues seeking. If the seek operation
drive analog audio signals onto the LOUT and ROUT is unable to find a valid channel, the seek failure/band
pins. The audio output may be muted with the DMUTE limit (SF/BL) bit is set high and the device returns to the
bit. Volume can be adjusted digitally with the channel selected before the seek operation began.
VOLUME[3:0] bits. The volume dynamic range can be When the SKMODE bit is high and a seek is initiated,
set to either –28 dBFS (default) or –58 dBFS by setting the device seeks through the band until the band limit is
VOLEXT=1.
reached and the SF/BL bit is set high. A seek operation
is initiated by setting the SEEK and SEEKUP bits. After
the seek operation completes, the STC bit is set, and
the RSSI level and tuned channel are available by
reading bits RSSI[7:0] and bits READCHAN[9:0]. During
a seek operation READCHAN[9:0] is also updated and
may be read to determine and report seek progress.
The STC bit is set after the seek operation completes.
The channel is valid if the seek operation completes and
the SF/BL bit is set low. At other times, such as before a
seek operation or after a seek completes and the SF/BL
bit is set high, the channel is valid if the AFC Rail
(AFCRL) bit is set low and the value of RSSI[7:0] is
greater than or equal to SEEKTH[7:0]. Note that if a
valid channel is found but the AFCRL bit is set, the
audio output is muted as in the softmute case discussed
in Section “4.5. Stereo Audio Processing”. The SEEK bit
must be set low after the STC bit is set high in order to
complete the seek operation. Setting the STC bit low
clears STC status and SF/BL bits. The seek operation
may be aborted by setting the SEEK bit low at any time.
The soft mute feature is available to attenuate the audio
outputs and minimize audible noise in weak signal
conditions. The soft mute attack and decay rate can be
adjusted with the SMUTER[1:0] bits where 00 is the
fastest setting. The soft mute attenuation level can be
adjusted with the SMUTEA[1:0] bits where 00 is the
most attenuated. The soft mute disable (DSMUTE) bit
may be set high to disable this feature.
4.6. Tuning
The Si4702/03-C19 uses Silicon Laboratories’ patented
and proven frequency synthesizer technology including
a
completely integrated VCO. The frequency
synthesizer generates the quadrature local oscillator
signal used to downconvert the RF input to a low
intermediate frequency. The VCO frequency is locked to
the reference clock and adjusted with an automatic
frequency control (AFC) servo loop during reception.
The tuning frequency is defined as:
Freq (MHz) = Spacing (kHz) Channel + Bottom of Band (MHz)
The device can be configured to generate an interrupt
on GPIO2 when a tune or seek operation completes.
Setting the seek/tune complete (STCIEN) bit and
GPIO2[1:0] = 01 will configure GPIO2 for a 5 ms low
interrupt when the STC bit is set by the device.
Channel spacing of 50, 100 or 200 kHz is selected with
bits SPACE[1:0]. The channel is selected with bits
CHAN[9:0]. Band selection for Japan, Japan wideband,
or Europe/U.S./Asia is set with BAND[1:0]. The tuning
operation begins by setting the TUNE bit. After tuning
Rev. 1.1
17
For additional recommendations on optimizing the seek
function, consult "AN284: Si4700/01/02/03 Seek
Adjustability and Settings."
4.8. Control Interface
Two-wire slave-transceiver and three-wire interfaces
are provided for the controller IC to read and write the
control registers. Refer to “4.9. Reset, Powerup, and
Powerdown” for a description of bus mode selection.
Registers may be written and read when the V supply
is applied regardless of the state of the V or V
4.7. Reference Clock
The Si4702/03-C19 accepts a 32.768 kHz reference
clock to the RCLK pin. The reference clock is required
whenever the ENABLE bit is set high. Refer to Table 3,
IO
D
A
supplies. RCLK is not required for proper register
operation.
1
“DC Characteristics ,” on page 5 for input switching
voltage
levels
and
Table 8,
"FM
Receiver
4.8.1. 3-Wire Control Interface
Characteristics," on page 12 for frequency tolerance
information.
For three-wire operation, a transfer begins when the
SEN pin is sampled low by the device on a rising SCLK
edge. The control word is latched internally on rising
SCLK edges and is nine bits in length, comprised of a
four bit chip address A7:A4 = 0110b, a read/write bit
(write = 0 and read = 1), and a four bit register address,
A3:A0. The ordering of the control word is A7:A5, R/W,
A4:A0. Refer to Section 5. "Register Summary" on page
22 for a list of all registers and their addresses.
An onboard crystal oscillator is available to generate the
32.768 kHz reference when an external crystal and load
capacitors are provided. Refer to 2. "Typical Application
Schematic" on page 14. The oscillator must be enabled
or disabled while in powerdown (ENABLE = 0) as shown
in Figure 9, “Initialization Sequence,” on page 21.
Register 07h, bits [13:0], must be preserved as 0x0100
while in powerdown. Note that RCLK voltage levels are
not specified. The typical RCLK voltage level, when the For write operations, the serial control word is followed
crystal oscillator is used, is 0.3 V
.
by a 16-bit data word and is latched internally on rising
SCLK edges.
pk-pk
4.7.1. Si4702/03-C19 Internal Crystal Oscillator
Errata
For read operations, a bus turn-around of half a cycle is
followed by a 16-bit data word shifted out on rising
SCLK edges and is clocked into the system controller
on falling SCLK edges. The transfer ends on the rising
SCLK edge after SEN is set high. Note that 26 SCLK
cycles are required for a transfer, however, SCLK may
run continuously.
The Si4702/03-C19 seek/tune performance may be
affected by data activity on the SDIO bus when using
the integrated internal oscillator. SDIO activity results
from polling the tuner for status or communicating with
other devices that share the SDIO bus. If there is SDIO
bus activity while the Si4702/03-C19 is performing the
seek/tune function, the crystal oscillator may experience For details on timing specifications and diagrams, refer
jitter, which may result in mistunes and/or false stops. to Table 6, “3-Wire Control Interface Characteristics,” on
SDIO activity during all other operational states does page 8, Figure 3, “3-Wire Control Interface Write Timing
not affect performance.
Parameters,” on page 8, and Figure 4, “3-Wire Control
Interface Read Timing Parameters,” on page 9.
For best seek/tune results, Silicon Laboratories
recommends that all SDIO data traffic be suspended 4.8.2. 2-wire Control Interface
during Si4702/03-C19 seek and tune operations. This is
For two-wire operation, the SCLK and SDIO pins
achieved by keeping the bus quiet for all other devices
on the bus, and delaying tuner polling until the tune or
seek operation is complete. The STC (seek/tune
complete) interrupt should be used instead of polling to
determine when a seek/tune operation is complete.
Please refer to Sections 4.6. "Tuning" on page 17 and 5.
"Register Summary" on page 22 for specified seek/tune
times and register use guidelines.
function in open-drain mode (pull-down only) and must
be pulled up by an external device. A transfer begins
with the START condition (falling edge of SDIO while
SCLK is high). The control word is latched internally on
rising SCLK edges and is eight bits in length, comprised
of a seven bit device address equal to 0010000b and a
read/write bit (write = 0 and read = 1).
The device acknowledges the address by driving SDIO
low after the next falling SCLK edge, for 1 cycle. For
write operations, the device acknowledge is followed by
an eight bit data word latched internally on rising edges
of SCLK. The device acknowledges each byte of data
The layout guidelines in Si4700/01/02/03 Evaluation
Board User’s Guide, Section 8.3 Si4702/03-C19
Daughter Card should be followed to help ensure robust
FM performance.
Please refer to the posted Si4702/03 Internal Crystal written by driving SDIO low after the next falling SCLK
Oscillator Errata for more information.
edge, for 1 cycle. An internal address counter
automatically increments to allow continuous data byte
18
Rev. 1.1
writes, starting with the upper byte of register 02h,
followed by the lower byte of register 02h, and onward
until the lower byte of the last register is reached. The
internal address counter then automatically wraps
around to the upper byte of register 00h and proceeds
from there until continuous writes end. Data transfer
ends with the STOP condition (rising edge of SDIO
while SCLK is high). After every STOP condition, the
internal address counter is reset.
4.9. Reset, Powerup, and Powerdown
Driving the RST pin low will disable the Si4702/03-C19
and its control bus interface, and reset the registers to
their default settings. Driving the RST pin high will bring
the device out of reset. As the device is brought out of
reset, it will sample the state of several pins to select
between 2-wire and 3-wire control interface operation,
using one of two busmode selection methods.
Busmode selection method 1 requires the use of the
GPIO3, SEN, and SDIO pins. To use this busmode
selection method, the GPIO3 and SDIO pins must be
sampled low by the device on the rising edge of RST.
For read operations, the device acknowledge is
followed by an eight bit data word shifted out on falling
SCLK edges. An internal address counter automatically
increments to allow continuous data byte reads, starting
with the upper byte of register 0Ah, followed by the
lower byte of register 0Ah, and onward until the lower
byte of the last register is reached. The internal address
counter then automatically wraps around to the upper
byte of register 00h and proceeds from there until
continuous reads cease. After each byte of data is read,
The user may either drive the GPIO3 pin low externally,
or leave the pin floating. If the pin is not driven by the
user, it will be pulled low by an internal 1 M resistor
which is active only while RST is low. The user must
drive the SEN and SDIO pins externally to the proper
state.
the controller IC must drive an acknowledge (SDIO = 0) To select 2-wire operation, the SEN pin must be
if an additional byte of data will be requested. Data sampled high by the device on the rising edge of RST.
transfer ends with the STOP condition. After every
STOP condition, the internal address counter is reset.
sampled low by the device on the rising edge of RST.
To select 3-wire operation, the SEN pin must be
For details on timing specifications and diagrams, refer
Refer to Table 4, “Reset Timing Characteristics
1,2,3
to
Table 7,
“2-Wire
Control
Interface
(Busmode Select Method 1)
,” on page 6 and
1,2,3
Characteristics
,” on page 10, Figure 5, “2-Wire
Figure 1, “Reset Timing Parameters for Busmode
Select Method 1 (GPIO3 = 0),” on page 6.
Control Interface Read and Write Timing Parameters,”
on page 11 and Figure 6, “2-Wire Control Interface
Read and Write Timing Diagram,” on page 11.
Busmode selection method 2 requires only the use of
the GPIO3 and GPIO1 pins. This is the recommended
busmode selection method when not using the internal
crystal oscillator. To use this busmode selection
method, the GPIO3 pin must be sampled high on the
rising edge of RST. The user must drive the GPIO3 pin
high externally, or pull it up with a resistor of 100 k or
less. The user must also drive the GPIO1 pin externally
to the proper state.
To select 2-wire operation, the GPIO1 pin must be
sampled high by the device on the rising edge of RST.
To select 3-wire operation, the GPIO1 pin must be
sampled low by the device on the rising edge of RST.
Refer to Table 5, “Reset Timing Characteristics
1,2,3
(Busmode Select Method 2)
,” on page 7 and
Figure 2, “Reset Timing Parameters for Busmode
Select Method 2 (GPIO3 = 1),” on page 7.
Table 9 summarizes the two bus selection methods.
Rev. 1.1
19
4.10. Audio Output Summation
Table 9. Selecting 2-Wire or 3-Wire Control
Interface Busmode Operation1,2,3
The audio outputs LOUT and ROUT may be
capacitively summed with another device. Setting the
audio high-Z enable (AHIZEN) bit maintains a dc bias of
Busmode
Bus
2
SEN SDIO GPIO1
GPIO3
0.5 x V on the LOUT and ROUT pins to prevent the
Select Method
mode
IO
ESD diodes from clamping to the V or GND rail in
response to the output swing of the other device. The
4
IO
1
1
0
1
0
0
0
0
X
X
X
0
3-wire
2-wire
3-wire
4
0
bias point is set with a 370 k resistor to V and GND.
IO
5
Register 07h containing the AHIZEN bit must not be
1
0
written during the powerup sequence and only takes
Xtal Oscillator
effect when in powerdown and V
is supplied. In
5
IO
1
1
0
X
0
2-wire
powerup the LOUT and ROUT pins are set to the
common mode voltage specified in Table 8, “FM
Xtal Oscillator
6
1,2
2
2
X
X
X
X
0
1
1
3-wire
2-wire
NA
Receiver Characteristics ,” on page 12, regardless of
6
the state of AHIZEN. Bits 13:0 of register 07h must be
preserved as 0x0100 while in powerdown and as
0x3C04 while in powerup.
1
2
NA
NA
NA
NA
Xtal Oscillator
4.11. Initialization Sequence
2
NA
NA
NA
NA
NA
Refer to Figure 9, “Initialization Sequence,” on page 21.
To initialize the device:
Xtal Oscillator
Notes:
1. Supply V and V .
1. All parameters applied on rising edge of RST.
A
D
2. When selecting 2-wire mode, the user must ensure
that SCLK is high during the rising edge of RST, and
stays high until the 1st start condition.
2. Supply V while keeping the RST pin low. Note that steps
IO
1 and 2 may be reversed. Power supplies may be
sequenced in any order.
3. GPIO3 is internally pulled down with a 1 M resistor.
4. GPIO3 should be externally driven low, set to high-Z
(10 M or greater pull-up) or float.
5. GPIO3 should be left floating.
6. GPIO3 should be externally driven high (100 kor
smaller pull-up).
3. Select 2-wire or 3-wire control interface bus mode
operation as described in Section 4.9. "Reset, Powerup,
and Powerdown" on page 19.
4. Provide RCLK. Steps 3 and 4 may be reversed when using
an external oscillator. Refer to AN230 when using internal
oscillator.
5. Set the ENABLE bit high and the DISABLE bit low to
powerup the device. Software should wait for the powerup
time (as specified by Table 8, “FM Receiver
When proper voltages are applied to the
Si4702/03-C19, the ENABLE and DISABLE bits in
Register 02h can be used to select between powerup
and powerdown modes. When voltage is first applied to
the device, ENABLE = 0 and DISABLE = 0. Setting
ENABLE = 1 and DISABLE = 0 puts the device in
powerup mode. To power down the device, disable RDS
to prevent any unpredictable behavior (Si4703 only),
then write ENABLE and DISABLE bits to 1.
1,2
Characteristics ,” on page 12) before continuing with
normal part operation.
To power down the device:
1. (Optional) Set the AHIZEN bit high to maintain a dc bias of
0.5 x V volts at the LOUT and ROUT pins while in
IO
powerdown, but preserve the states of the other bits in
Register 07h. Note that in powerup the LOUT and ROUT
pins are set to the common mode voltage specified in
Table 8 on page 12, regardless of the state of AHIZEN.
After being written to 1, both bits will be cleared as part
of the internal device powerdown sequence. To put the
device back into powerup mode, set ENABLE = 1 and
DISABLE = 0 as described above. The ENABLE bit
should never be written to a 0.
2. Set the ENABLE bit high and the DISABLE bit high to
place the device in powerdown mode. Note that all register
states are maintained so long as V is supplied and the
IO
RST pin is high.
3. (Optional) Remove RCLK.
4. Remove V and V supplies as needed.
A
D
20
Rev. 1.1
To power up the device (after power down):
1. Note that V is still supplied in this scenario. If V is not
IO
IO
supplied, refer to device initialization procedure above.
2. (Optional) Set the AHIZEN bit low to disable the dc bias of
0.5 x V volts at the LOUT and ROUT pins, but preserve
IO
the states of the other bits in Register 07h. Note that in
powerup the LOUT and ROUT pins are set to the common
mode voltage specified in Table 8 on page 12, regardless
of the state of AHIZEN.
3. Supply V and V .
A
D
4. Provide RCLK. Refer to AN230 when using internal
oscillator.
5. Set the ENABLE bit high and the DISABLE bit low to
powerup the device.
VA,VD Supply
VIO Supply
RST Pin
RCLK Pin
ENABLE Bit
1
2
3
4
5
Figure 9. Initialization Sequence
4.12. Programming Guide
Refer to "AN230: Si4700/01 Programming Guide" for
control interface programming information.
Rev. 1.1
21
22
Rev. 1.1
6. Register Descriptions
Register 00h. Device ID
Bit
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
PN[3:0]
R
MFGID[11:0]
R
Reset value = 0x1242
Bit
Name
Function
15:12
PN[3:0]
Part Number.
0x01 = Si4702/03
11:0
MFGID[11:0]
Manufacturer ID.
0x242
Register 01h. Chip ID
Bit
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
REV[5:0]
R
DEV[3:0]
R
FIRMWARE[5:0]
R
Si4702C19 Reset value = 0x1053 if ENABLE = 1
Si4702C19 Reset value = 0x1000 if ENABLE = 0
Si4703C19 Reset value = 0x1253 if ENABLE = 1
Si4703C19 Reset value = 0x1200 if ENABLE = 0
Bit
Name
Function
15:10
REV[5:0]
Chip Version.
0x04 = Rev C
9:6
DEV[3:0]
Device.
0 before powerup = Si4702.
0001 after powerup = Si4702.
1000 before powerup = Si4703.
1001 after powerup = Si4703.
5:0
FIRMWARE[5:0] Firmware Version.
0 before powerup.
Firmware version after powerup = 010011.
Rev. 1.1
23
Register 02h. Power Configuration
Bit
D15
D14 D13 D12 D11
D10
D9
D8 D7
D6
DISABLE
R/W
D5 D4 D3 D2 D1
D0
ENABLE
R/W
DSMUTE DMUTE MONO
0
RDSM SKMODE SEEKUP SEEK
0
0
0
0
0
0
Name
Type
R/W
R/W
R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W
Reset value = 0x0000
Bit
Name
Function
15
DSMUTE
Softmute Disable.
0 = Softmute enable (default).
1 = Softmute disable.
14
13
DMUTE
MONO
Mute Disable.
0 = Mute enable (default).
1 = Mute disable.
Mono Select.
0 = Stereo (default).
1 = Force mono.
12
11
Reserved
RDSM
Reserved.
Always write to 0.
RDS Mode.
0 = Standard (default).
1 = Verbose.
Refer to “4.4. RDS/RBDS Processor and Functionality”.
10
9
SKMODE
SEEKUP
SEEK
Seek Mode.
0 = Wrap at the upper or lower band limit and continue seeking (default).
1 = Stop seeking at the upper or lower band limit.
Seek Direction.
0 = Seek down (default).
1 = Seek up.
8
Seek.
0 = Disable (default).
1 = Enable.
Notes:
1. Seek begins at the current channel, and goes in the direction specified with the SEEKUP
bit. Seek operation stops when a channel is qualified as valid according to the seek
parameters, the entire band has been searched (SKMODE = 0), or the upper or lower
band limit has been reached (SKMODE = 1).
2. The STC bit is set high when the seek operation completes and/or the SF/BL bit is set
high if the seek operation was unable to find a channel qualified as valid according to the
seek parameters. The STC and SF/BL bits must be set low by setting the SEEK bit low
before the next seek or tune may begin.
3. Seek performance for 50 kHz channel spacing varies according to RCLK tolerance.
Silicon Laboratories recommends ±50 ppm RCLK crystal tolerance for 50 kHz seek
performance.
4. A seek operation may be aborted by setting SEEK = 0.
24
Rev. 1.1
Bit
Name
Function
7
Reserved
Reserved.
Always write to 0.
6
DISABLE
Powerup Disable.
Refer to “4.9. Reset, Powerup, and Powerdown”.
Default = 0.
5:1
0
Reserved
ENABLE
Reserved.
Always write to 0.
Powerup Enable.
Refer to “4.9. Reset, Powerup, and Powerdown”.
Default = 0.
Register 03h. Channel
Bit
D15
D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Name TUNE
0
0
0
0
0
CHANNEL[9:0]
R/W
Type R/W R/W R/W R/W R/W R/W
Reset value = 0x0000
Bit
Name
Function
15
TUNE
Tune.
0 = Disable (default).
1 = Enable.
The tune operation begins when the TUNE bit is set high. The STC bit is set high
when the tune operation completes. The STC bit must be set low by setting the TUNE
bit low before the next tune or seek may begin.
14:10
9:0
Reserved
Reserved.
Always write to 0.
CHAN[9:0]
Channel Select.
Channel value for tune operation.
If BAND 05h[7:6] = 00, then Freq (MHz) = Spacing (MHz) x Channel + 87.5 MHz.
If BAND 05h[7:6] = 01, BAND 05h[7:6] = 10, then
Freq (MHz) = Spacing (MHz) x Channel + 76 MHz.
CHAN[9:0] is not updated during a seek operation. READCHAN[9:0] provides the
current tuned channel and is updated during a seek operation and after a seek or
tune operation completes. Channel spacing is set with the bits SPACE 05h[5:4].
Rev. 1.1
25
Register 04h. System Configuration 1
Bit
D15
D14
D13 D12 D11 D10 D9
D8
0
D7
D6
D5 D4 D3 D2 D1 D0
RDSIEN STCIEN
0
RDS
R/W
DE
AGCD
R/W
0
BLNDADJ[1:0] GPIO3[1:0]
GPIO2[1:0]
R/W
GPIO1[1:0]
R/W
Name
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset value = 0x0000
Bit
Name
Function
15
RDSIEN
RDS Interrupt Enable.
0 = Disable Interrupt (default).
1 = Enable Interrupt.
Setting RDSIEN = 1 and GPIO2[1:0] = 01 will generate a 5 ms low pulse on GPIO2 when
the RDSR 0Ah[15] bit is set.
14
STCIEN
Seek/Tune Complete Interrupt Enable.
0 = Disable Interrupt (default).
1 = Enable Interrupt.
Setting STCIEN = 1 and GPIO2[1:0] = 01 will generate a 5 ms low pulse on GPIO2 when
the STC 0Ah[14] bit is set.
13
12
Reserved
RDS
Reserved.
Always write to 0.
RDS Enable.
0 = Disable (default).
1 = Enable.
11
10
DE
De-emphasis.
0 = 75 µs. Used in USA (default).
1 = 50 µs. Used in Europe, Australia, Japan.
AGCD
AGC Disable.
0 = AGC enable (default).
1 = AGC disable.
9:8
Reserved
Reserved.
Always write to 0.
6:7 BLNDADJ[1:0] Stereo/Mono Blend Level Adjustment.
Sets the RSSI range for stereo/mono blend.
00 = 31–49 RSSI dBµV (default).
01 = 37–55 RSSI dBµV (+6 dB).
10 = 19–37 RSSI dBµV (–12 dB).
11 = 25–43 RSSI dBµV (–6 dB).
ST bit set for RSSI values greater than low end of range.
5:4
GPIO3[1:0] General Purpose I/O 3.
00 = High impedance (default).
01 = Mono/Stereo indicator (ST). The GPIO3 will output a logic high when the device is in
stereo, otherwise the device will output a logic low for mono.
10 = Low.
11 = High.
26
Rev. 1.1
Bit
Name
Function
3:2
GPIO2[1:0] General Purpose I/O 2.
00 = High impedance (default).
01 = STC/RDS interrupt. A logic high will be output unless an interrupt occurs as
described below.
10 = Low.
11 = High.
Setting STCIEN = 1 will generate a 5 ms low pulse on GPIO2 when the STC 0Ah[14] bit is
set. Setting RDSIEN = 1 will generate a 5 ms low pulse on GPIO2 when the RDSR
0Ah[15] bit is set.
1:0
GPIO1[1:0] General Purpose I/O 1.
00 = High impedance (default).
01 = Reserved.
10 = Low.
11 = High.
Rev. 1.1
27
Register 05h. System Configuration 2
Bit
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
SEEKTH[7:0]
R/W
BAND[1:0] SPACE[1:0]
VOLUME[3:0]
R/W
R/W
R/W
Reset value = 0x0000
Bit
Name
Function
15:8
SEEKTH[7:0]
RSSI Seek Threshold.
0x00 = min RSSI (default).
0x7F = max RSSI.
SEEKTH presents the logarithmic RSSI threshold for the seek operation. The
Si4702/03-C19 will not validate channels with RSSI below the SEEKTH value.
SEEKTH is one of multiple parameters that can be used to validate channels. For
more information, see "AN284: Si4700/01 Firmware 15 Seek Adjustability and Set-
tings."
7:6
BAND[1:0]
Band Select.
00 = 87.5–108 MHz (USA, Europe) (Default).
01 = 76–108 MHz (Japan wide band).
10 = 76–90 MHz (Japan).
11 = Reserved.
5:4
3:0
SPACE[1:0]
Channel Spacing.
00 = 200 kHz (USA, Australia) (default).
01 = 100 kHz (Europe, Japan).
10 = 50 kHz.
VOLUME[3:0] Volume.
Relative value of volume is shifted –30 dBFS with the VOLEXT 06h[8] bit.
VOLEXT = 0 (default).
0000 = mute (default).
0001 = –28 dBFS.
:
:
1110 = –2 dBFS.
1111 = 0 dBFS.
VOLEXT = 1.
0000 = mute.
0001 = –58 dBFS.
:
:
1110 = –32 dBFS.
1111 = –30 dBFS.
FS = full scale.
Volume scale is logarithmic.
28
Rev. 1.1
Register 06h. System Configuration 3
Bit
Name SMUTER[1:0] SMUTEA[1:0]
Type R/W R/W
Reset value = 0x0000
D15
D14
D13 D12
D11
D10
D9
D8
VOLEXT
R/W
D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
SKSNR[3:0]
R/W
SKCNT[3:0]
R/W
R/W R/W R/W
Bit
Name
Function
15:14
SMUTER[1:0] Softmute Attack/Recover Rate.
00 = fastest (default).
01 = fast.
10 = slow.
11 = slowest.
13:12
SMUTEA[1:0] Softmute Attenuation.
00 = 16 dB (default).
01 = 14 dB.
10 = 12 dB.
11 = 10 dB.
11:9
8
Reserved
VOLEXT
Reserved.
Always write to zero.
Extended Volume Range.
0 = disabled (default).
1 = enabled.
This bit attenuates the output by 30 dB. With the bit set to 0, the 15 volume settings
adjust the volume between 0 and –28 dBFS. With the bit set to 1, the 15 volume set-
tings adjust the volume between –30 and –58 dBFS.
Refer to 4.5. "Stereo Audio Processing" on page 16.
7:4
3:0
SKSNR[3:0]
SKCNT[3:0]
Seek SNR Threshold.
0000 = disabled (default).
0001 = min (most stops).
0111 = max (fewest stops).
Required channel SNR for a valid seek channel.
Seek FM Impulse Detection Threshold.
0000 = disabled (default).
0001 = max (most stops).
1111 = min (fewest stops).
Allowable number of FM impulses for a valid seek channel.
Rev. 1.1
29
Register 07h. Test 1
Bit
Name XOSCEN AHIZEN
Type R/W R/W
Reset value = 0x0100
D15
D14
D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Reserved
R/W
Bit
Name
XOSCEN
Function
15
Crystal Oscillator Enable.
0 = Disable (default).
1 = Enable.
The internal crystal oscillator requires an external 32.768 kHz crystal as shown in
2. "Typical Application Schematic" on page 14. The oscillator must be enabled before
powerup (ENABLE = 1) as shown in Figure 9, “Initialization Sequence,” on page 21. It
should only be disabled after powerdown (ENABLE = 0). Bits 13:0 of register 07h
must be preserved as 0x0100 while in powerdown and as 0x3C04 while in powerup.
Refer to Si4702/03 Internal Crystal Oscillator Errata.
14
AHIZEN
Audio High-Z Enable.
0 = Disable (default).
1 = Enable.
Setting AHIZEN maintains a dc bias of 0.5 x V on the LOUT and ROUT pins to pre-
IO
vent the ESD diodes from clamping to the V or GND rail in response to the output
IO
swing of another device. Register 07h containing the AHIZEN bit must not be written
during the powerup sequence and high-Z only takes effect when in powerdown and
V
is supplied. Bits 13:0 of register 07h must be preserved as 0x0100 while in pow-
IO
erdown and as 0x3C04 while in powerup.
13:0
Reserved
Reserved.
If written, these bits should be read first and then written with their pre-existing val-
ues. Do not write during powerup.
30
Rev. 1.1
Register 08h. Test 2
Bit
D15 D14 D13 D12 D11 D10 D9
D8
Reserved
R/W
D7 D6 D5 D4 D3 D2 D1 D0
Name
Type
Reset value = 0x0000
Bit
Name
Function
15:0
Reserved
Reserved.
If written, these bits should be read first and then written with their pre-existing val-
ues. Do not write during powerup.
Register 09h. Boot Configuration
Bit
D15 D14 D13 D12 D11 D10 D9
D8
Reserved
R/W
D7 D6 D5 D4 D3 D2 D1 D0
Name
Type
Reset value = 0x0000
Bit
Name
Function
15:0
Reserved
Reserved.
If written, these bits should be read first and then written with their pre-existing val-
ues. Do not write during powerup.
Rev. 1.1
31
Register 0Ah. Status RSSI
Bit
Name RDSR STC SF/BL AFCRL RDSS BLERA[1:0] ST
Type
Reset value = 0x0000
D15 D14 D13
D12
D11 D10 D9
D8
D7 D6 D5 D4 D3 D2 D1 D0
RSSI[7:0]
R
R
R
R
R
R
R
R
Bit
Name
Function
15
RDSR
RDS Ready.
0 = No RDS group ready (default).
1 = New RDS group ready.
Refer to “4.4. RDS/RBDS Processor and Functionality”.
14
13
STC
Seek/Tune Complete.
0 = Not complete (default).
1 = Complete.
The seek/tune complete flag is set when the seek or tune operation completes. Setting
the SEEK 02h[8] or TUNE 03h[15] bit low will clear STC.
SF/BL
Seek Fail/Band Limit.
0 = Seek successful.
1 = Seek failure/Band limit reached.
The SF/BL flag is set high when SKMODE 02h[10] = 0 and the seek operation fails to
find a channel qualified as valid according to the seek parameters.
The SF/BL flag is set high when SKMODE 02h[10] = 1 and the upper or lower band limit
has been reached.
The SEEK 02h[8] bit must be set low to clear SF/BL.
12
AFCRL
RDSS
AFC Rail.
0 = AFC not railed.
1 = AFC railed, indicating an invalid channel. Audio output is softmuted when set.
AFCRL is updated after a tune or seek operation completes and indicates a valid or
invalid channel. During normal operation, AFCRL is updated to reflect changing RF envi-
ronments.
11
RDS Synchronized.
0 = RDS decoder not synchronized (default).
1 = RDS decoder synchronized.
Available only in RDS Verbose mode (RDSM 02h[11] = 1).
Refer to “4.4. RDS/RBDS Processor and Functionality”.
10:9
BLERA[1:0] RDS Block A Errors.
00 = 0 errors requiring correction.
01 = 1–2 errors requiring correction.
10 = 3–5 errors requiring correction.
11 = 6+ errors or error in checkword, correction not possible.
Available only in RDS Verbose mode (RDSM 02h[11] = 1).
Refer to “4.4. RDS/RBDS Processor and Functionality”.
32
Rev. 1.1
Bit
Name
Function
8
ST
Stereo Indicator.
0 = Mono.
1 = Stereo.
Stereo indication is also available on GPIO3 by setting GPIO3 04h[5:4] = 01.
7:0
RSSI[7:0]
RSSI (Received Signal Strength Indicator).
RSSI is measured units of dBµV in 1 dB increments with a maximum of approximately
75 dBµV. Si4702/03-C19 does not report RSSI levels greater than 75 dBuV.
Rev. 1.1
33
Register 0Bh. Read Channel
Bit
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Name BLERB[1:0] BLERC[1:0] BLERD[1:0]
READCHAN[9:0]
R
Type
R
R
R
Reset value = 0x0000
Bit
Name
Function
15:14
BLERB[1:0]
RDS Block B Errors.
00 = 0 errors requiring correction.
01 = 1–2 errors requiring correction.
10 = 3–5 errors requiring correction.
11 = 6+ errors or error in checkword, correction not possible.
Available only in RDS Verbose mode (RDSM = 1).
Refer to “4.4. RDS/RBDS Processor and Functionality”.
13:12
11:10
9:0
BLERC[1:0]
BLERD[1:0]
RDS Block C Errors.
00 = 0 errors requiring correction.
01 = 1–2 errors requiring correction.
10 = 3–5 errors requiring correction.
11 = 6+ errors or error in checkword, correction not possible.
Available only in RDS Verbose mode (RDSM = 1).
Refer to “4.4. RDS/RBDS Processor and Functionality”.
RDS Block D Errors.
00 = 0 errors requiring correction.
01 = 1–2 errors requiring correction.
10 = 3–5 errors requiring correction.
11 = 6+ errors or error in checkword, correction not possible.
Available only in RDS Verbose mode (RDSM = 1).
Refer to “4.4. RDS/RBDS Processor and Functionality”.
READCHAN[9:0] Read Channel.
If BAND 05h[7:6] = 00, then Freq (MHz) = Spacing (MHz) x Channel + 87.5 MHz.
If BAND 05h[7:6] = 01, BAND 05h[7:6] = 10, then
Freq (MHz) = Spacing (MHz) x Channel + 76 MHz.
READCHAN[9:0] provides the current tuned channel and is updated during a seek
operation and after a seek or tune operation completes. Spacing and channel are set
with the bits SPACE 05h[5:4] and CHAN 03h[9:0].
34
Rev. 1.1
Register 0Ch. RDSA
Bit
D15 D14 D13 D12 D11 D10 D9
D8
D7 D6 D5 D4 D3 D2 D1 D0
Name
RDSA[15:0]
R
Type
Reset value = 0x0000
Bit
Name
Function
15:0
RDSA
RDS Block A Data.
Register 0Dh. RDSB
Bit
D15 D14 D13 D12 D11 D10 D9
D8
D7 D6 D5 D4 D3 D2 D1 D0
Name
RDSB[15:0]
R
Type
Reset value = 0x0000
Bit
Name
Function
15:0
RDSB
RDS Block B Data.
Rev. 1.1
35
Register 0Eh. RDSC
Bit
D15 D14 D13 D12 D11 D10 D9
D8
D7 D6 D5 D4 D3 D2 D1 D0
Name
RDSC[15:0]
R
Type
Reset value = 0x0000
Bit
Name
Function
15:0
RDSC
RDS Block C Data.
Register 0Fh. RDSD
Bit
D15 D14 D13 D12 D11 D10 D9
D8
D7 D6 D5 D4 D3 D2 D1 D0
Name
RDSD[15:0]
R
Type
Reset value = 0x0000
Bit
Name
Function
15:0
RDSD
RDS Block D Data.
36
Rev. 1.1
7. Pin Descriptions: Si4702/03-C19
1
2
20
19
18
17 16
15 GND
NC
FMIP
RFGND
GND
3
4
14
13
LOUT
ROUT
GND
PAD
RST
5
6
12 GND
11 VD
7
8
9
10
Top View
Pin Number(s)
Name
NC
Description
1, 20
No Connect. Leave floating.
FM RF inputs.
2
FMIP
RFGND
GND
3
RF ground. Connect to ground plane on PCB.
Ground. Connect to ground plane on PCB.
Device reset input (active low).
Serial enable input (active low).
Serial clock input.
4, 12, 15, PAD
5
RST
6
SEN
7
SCLK
SDIO
RCLK
8
Serial data input/output.
9
External reference oscillator input.
I/O supply voltage.
10
V
IO
11
13
V
Digital supply voltage. May be connected directly to battery.
Right audio output.
D
ROUT
LOUT
14
Left audio output.
16
V
Analog supply voltage. May be connected directly to battery.
A
17, 18, 19
GPIO3, GPIO2, General purpose input/output.
GPIO1
Rev. 1.1
37
8. Ordering Guide
Part
Number*
Package
Type
Operating
Temperature
Description
Si4702-C19-GM Portable Broadcast Radio Tuner
FM Stereo
QFN
Pb-free
–20 to 85 °C
–20 to 85 °C
Si4703-C19-GM Portable Broadcast Radio Tuner
FM Stereo with RDS
QFN
Pb-free
*Note: Add an “(R)” at the end of the device part number to denote tape and reel option; 2500 quantity per reel.
38
Rev. 1.1
9. Package Markings (Top Marks)
9.1. Si4702 Top Mark
Figure 10. Si4702 Top Mark
9.2. Si4703 Top Mark
Figure 11. Si4703 Top Mark
9.3. Top Mark Explanation
Mark Method:
YAG Laser
Line 1 Marking:
Part Number
02 = Si4702
03 = Si4703
Firmware Revision
R = Die Revision
19 = Firmware Revision 19
C = Revision C Die
Line 2 Marking:
Line 3 Marking:
TTT = Internal Code
Internal tracking code.
Circle = 0.5 mm Diameter Pin 1 Identifier
(Bottom-Left Justified)
Y = Year
Assigned by the Assembly House. Corresponds to the last sig-
nificant digit of the year and workweek of the mold date.
WW = Workweek
Rev. 1.1
39
10. Package Outline: Si4702/03-C19
Figure 12 illustrates the package details for the Si4702/03-C19. Table 10 lists the values for the dimensions shown
in the illustration.
Figure 12. 20-Pin Quad Flat No-Lead (QFN)
Table 10. Package Dimensions
Symbol
Millimeters
Nom
Symbol
Millimeters
Nom
Min
Max
Min
Max
A
A1
b
0.50
0.00
0.18
0.27
0.55
0.02
0.60
0.05
0.30
0.37
f
2.53 BSC
L
0.35
0.00
—
0.40
—
0.45
0.10
0.10
0.10
0.08
0.10
0.10
0.25
L1
c
0.32
aaa
bbb
ccc
ddd
eee
—
D
3.00 BSC
1.70
—
—
D2
e
1.65
1.75
—
—
0.50 BSC
3.00 BSC
1.70
—
—
E
—
—
E2
1.65
1.75
Notes:
1. All dimensions are shown in millimeters unless otherwise noted.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
40
Rev. 1.1
11. PCB Land Pattern: Si4702/03-C19
Figure 13 illustrates the PCB land pattern details for the Si4702/03-C19. Table 11 lists the values for the
dimensions shown in the illustration.
Figure 13. PCB Land Pattern
Rev. 1.1
41
Table 11. PCB Land Pattern Dimensions
Symbol
Millimeters
Min Max
2.71 REF
1.60 1.80
Symbol
Millimeters
Min
Max
D
D2
e
GE
W
2.10
—
—
0.34
0.28
0.50 BSC
2.71 REF
X
—
E
Y
0.61 REF
E2
f
1.60
2.53 BSC
2.10
1.80
ZE
ZD
—
—
3.31
3.31
GD
—
Notes: General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on IPC-SM-782 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Notes: Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Notes: Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should
be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
4. A 1.45 x 1.45 mm square aperture should be used for the center pad. This provides
approximately 70% solder paste coverage on the pad, which is optimum to assure
correct component stand-off.
Notes: Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification
for Small Body Components.
42
Rev. 1.1
ADDITIONAL REFERENCE RESOURCES
AN230: Si4700/01/02/03 Programming Guide
AN231: Si4700/01/02/03 Headphone and Antenna Interface
Si4700/01/02/03 EVB User’s Guide
AN234: Si4700/01/02/03 EVB Test Procedure
AN235: Si4700/01/02/03 EVB Quick Start Guide
AN243: Using RDS/RBDS with the Si4701/03
AN284: Si4700/01/02/03 Seek Adjustability and Settings
AN299: External 32.768 kHz Crystal Oscillator
AN383: Antenna Selection and Universal Layout Guidelines
Si4702/03 Internal Crystal Oscillator Errata
Si4700/01/02/03 Customer Support Site: http://www.mysilabs.com
This site contains all application notes, evaluation board schematics and layouts, and evaluation software. NDA
is required for access. To request access, register at http://www.mysilabs.com and send user’s first and last
name, company, NDA reference number, and mysilabs user name to fminfo@silabs.com. Silicon Labs
recommends an all lower case user name.
Rev. 1.1
43
DOCUMENT CHANGE LIST
Revision 0.8 to Revision 0.9
Updated Figure 1, “Reset Timing Parameters for
Busmode Select Method 1 (GPIO3 = 0),” on page 6.
1
Updated Table 3, “DC Characteristics ,” on page 5.
Updated Table 7, “2-Wire Control Interface
1,2,3
Characteristics
,” on page 10.
1,2
Updated Table 8, “FM Receiver Characteristics ,” on
page 12.
Updated 4.4. "RDS/RBDS Processor and
Functionality" on page 16.
Updated Register 1, “Chip ID,” on page 23.
Updated Register 5, “System Configuration 2,” on
page 28.
Revision 0.9 to Revision 1.0
Updated notes in Table 7 on page 10.
Updated Table 8 on page 12.
Updated “4. Functional Description”.
Updated “5. Register Summary”.
Updated “6. Register Descriptions”.
Updated “7. Pin Descriptions: Si4702/03-C19”.
Revision 1.0 to Revision 1.1
Updated Table 8 on page 12.
Updated “4.11. Initialization Sequence”.
Updated Register 06h: System Configuration 3.
Updated additional reference resources.
44
Rev. 1.1
NOTES:
Rev. 1.1
45
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