SI4704-D50-GM [SILICON]
Baseband Circuit, CMOS, QFN-20;
| 型号： | SI4704-D50-GM |
| 厂家： | 
SILICON |
| 描述： | Baseband Circuit, CMOS, QFN-20 电信 电信集成电路 |
| 文件： | 总34页 (文件大小：1345K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si4704/05-D50
BROADCAST FM RADIO RECEIVER FOR CONSUMER
ELECTRONICS
Features
Worldwide FM band support
(64–108 MHz)
RDS/RBDS decoding engine
(Si4705 only)
Lowest power consumption
Received signal quality indicators
On-chip tuned resonance for
embedded antenna support
Multipath detection and mitigation
FM Hi-cut control
Advanced FM stereo-mono blend
Advanced audio processing
Not EN 55020 compliant*
Automatic gain control (AGC)
Integrated FM LNA
Image-rejection mixer
Frequency synthesizer with
integrated VCO
Low-IF direct conversion with no
external ceramic filters
2.7 to 5.5 V supply voltage
Dual 1.8 and 2.7 V power supplies
Stereo audio out
I2S Digital audio out
20-pin 3 x 3 mm QFN package
Pb-free/RoHS compliant
Ordering Information:
See page 27.
Pin Assignments
Si4704/05-GM
(Top View)
*Note: *For consumer electronics applications that require EN 55020 compliance,
use Si4704/05-D60.
Applications
Cellular handsets
Portable media devices
Dedicated data receiver
Personal navigation devices (PND)
GPS-enabled handsets and portable
devices
20 19 18 17
NC
FMI
1
16
2
15 DOUT
14 LOUT
13 ROUT
12 GND
11 VA
RFGND
LPI
3
4
5
GND
PAD
Description
RST
The Si4704/05-D50 FM/RDS/RDBS receivers provide the highest performance
and lowest power consumption available for portable devices today. The 100%
CMOS IC integrates the complete FM and data receiver function from antenna to
analog or digital audio and data out in a single 3 x 3 mm 20-pin QFN.
6
7
8
9
10
Functional Block Diagram
This product, its features, and/or its
architecture is covered by one or
more of the following patents, as well
as other patents, pending and
issued, both foreign and domestic:
7,127,217; 7,272,373; 7,272,375;
7,321,324; 7,355,476; 7,426,376;
7,471,940; 7,339,503; 7,339,504.
FM Antenna
Si4704/05
ADC
ADC
DAC
FMI
LOUT
ROUT
LNA
AGC
PGA
DSP
RFGND
DAC
GPO
LPI
0/90
DCLK
DOUT
DFS
RDS
(Si4705)
32.768 kHz
(TYP)
RCLK
RSSI
AFC
REG
CONTROL
INTERFACE
VA
2.7–5.5 V
XTAL
OSC
Rev. 1.0 12/10
Copyright © 2010 by Silicon Laboratories
Si4704/05-D50
Si4704/05-D50
2
Rev. 1.0
Si4704/05-D50
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.2. FM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.3. Stereo Audio Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.4. Received Signal Qualifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.5. De-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.6. Volume Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.7. Stereo DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.8. Soft Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.9. FM Hi-Cut Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.10. Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.11. Seek . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.12. Digital Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.13. Embedded Antenna Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4.14. RDS Decoder (Si4705 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4.15. Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4.16. Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.17. GPO Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.18. Reset, Powerup, and Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.19. Programming with Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
5. Commands and Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
6. Pin Descriptions: Si4704/05-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
8. Package Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
8.1. Si4704 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
8.2. Si4705 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
8.3. Top Mark Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
9. Package Outline: Si4704/05 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
10. PCB Land Pattern: Si4704/05 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
11. Additional Reference Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Document Change List: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Rev. 1.0
3
Si4704/05-D50
1. Electrical Specifications
Table 1. Recommended Operating Conditions*
Parameter
Symbol
Test Condition
Min
2.7
Typ
—
Max
5.5
3.6
—
Unit
V
Analog Supply Voltage
V
A
Digital and Interface Supply Voltage
V
1.62
10
—
V
D
Analog Power Supply Powerup Rise
Time
V
—
µs
ARISE
Digital Power Supply Powerup Rise
Time
V
10
—
—
µs
DRISE
Ambient Temperature
T
–20
25
85
C
A
*Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at VA = 3.3 V and 25 C unless otherwise stated. Parameters are tested in production unless
otherwise stated.
Table 2. Absolute Maximum Ratings1,2
Parameter
Symbol
Value
–0.5 to 5.8
–0.5 to 3.9
10
Unit
V
Analog Supply Voltage
V
A
Digital and Interface Supply Voltage
V
V
D
3
Input Current
I
mA
V
IN
3
Input Voltage
V
T
–0.3 to (V + 0.3)
IN
IO
Operating Temperature
Storage Temperature
–40 to 95
–55 to 150
0.4
C
C
OP
T
STG
4
RF Input Level
V
pK
Notes:
1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure beyond
recommended operating conditions for extended periods may affect device reliability.
2. The Si4704/05 devices are high-performance RF integrated circuits with certain pins having an ESD rating of < 2 kV
HBM. Handling and assembly of these devices should only be done at ESD-protected workstations.
3. For input pins DFS, SCLK, SEN, SDIO, RST, RCLK, GPO1, GPO2, GPO3, and DCLK.
4. At RF input pins FMI and LPI.
4
Rev. 1.0
Si4704/05-D50
Table 3. DC Characteristics
(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
FM Receiver to Line Output
V Supply Current
I
—
—
—
7.5
8.5
8.4
9.7
11.1
11.1
mA
mA
mA
A
FMVA
FMVD
FMVD
1
V Supply Current
I
I
Digital Output Mode
D
V Supply Current
Analog Output Mode
D
Powerdown and Interface
V Powerdown Current
I
—
—
4
15
10
µA
µA
V
A
DDPD
V Powerdown Current
I
SCLK, RCLK inactive
3
D
IOPD
2
2
High Level Input Voltage
V
0.7 x V
–0.3
–10
—
—
—
—
V + 0.3
D
IH
D
2
Low Level Input Voltage
V
0.3 x V
10
V
IL
D
High Level Input Current
I
V
= V = 3.6 V
µA
µA
IH
IN
D
2
Low Level Input Current
I
V
= 0 V,
IN
–10
10
IL
V = 3.6 V
D
3
High Level Output Voltage
V
I
= 500 µA
0.8 x V
—
—
—
—
V
V
OH
OUT
OUT
D
3
Low Level Output Voltage
V
I
= –500 µA
0.2 x V
OL
D
Notes:
1. Guaranteed by characterization.
2. For input pins SCLK, SEN, SDIO, RST, RCLK, DCLK, DFS, GPO1, GPO2, and GPO3.
3. For output pins SDIO, DOUT, GPO1, GPO2, and GPO3.
Rev. 1.0
5
Si4704/05-D50
Table 4. Reset Timing Characteristics1,2,3
(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Min
100
30
Typ
—
Max
—
Unit
µs
RST Pulse Width and GPO1, GPO2/INT Setup to RST
GPO1, GPO2/INT Hold from RST
Important Notes:
t
SRST
t
—
—
ns
HRST
1. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST.
2. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until
after the first start condition.
3. When selecting 3-wire mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RST.
4. If GPO1 and GPO2 are actively driven by the user, then minimum tSRST is only 30 ns. If GPO1 or GPO2 is high
impedance, then minimum tSRST is 100 µs to provide time for on-chip 1 M devices (active while RST is low) to pull
GPO1 high and GPO2 low.
tSRST tHRST
70%
RST
30%
70%
GPO1
30%
70%
GPO2
30%
Figure 1. Reset Timing Parameters for Busmode Select Method
6
Rev. 1.0
Si4704/05-D50
Table 5. 2-Wire Control Interface Characteristics1,2,3
(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol Test Condition
Min
0
Typ
—
Max
400
—
Unit
kHz
µs
SCLK Frequency
SCLK Low Time
SCLK High Time
f
SCL
t
1.3
0.6
0.6
—
LOW
t
—
—
µs
HIGH
SCLK Input to SDIO Setup
t
t
—
—
µs
SU:STA
(START)
SCLK Input to SDIO Hold
0.6
—
—
µs
HD:STA
(START)
SDIO Input to SCLK Setup
t
t
100
0
—
—
—
—
900
—
ns
ns
µs
SU:DAT
4, 5
SDIO Input to SCLK Hold
HD:DAT
SU:STO
SCLK Input to SDIO Setup
t
0.6
(STOP)
STOP to START Time
SDIO Output Fall Time
t
1.3
—
—
—
µs
ns
BUF
t
250
f:OUT
Cb
----------
1pF
20 + 0.1
SDIO Input, SCLK Rise/Fall Time
t
t
—
300
ns
f:IN
r:IN
Cb
----------
1pF
20 + 0.1
SCLK, SDIO Capacitive Loading
Input Filter Pulse Suppression
Notes:
C
—
—
—
—
50
50
pF
ns
b
t
SP
1. When VD = 0 V, SCLK and SDIO are low impedance.
2. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST.
3. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high
until after the first start condition.
4. The Si4704/05 delays SDIO by a minimum of 300 ns from the VIH threshold of SCLK to comply with the minimum
tHD:DAT specification.
5. The maximum tHD:DAT has only to be met when fSCL = 400 kHz. At frequencies below 400 kHz, tHD:DAT may be violated
as long as all other timing parameters are met.
Rev. 1.0
7
Si4704/05-D50
tSU:STA tHD:STA
tLOW
tHIGH
tr:IN
tf:IN
tSP
tSU:STO
tBUF
70%
SCLK
30%
70%
SDIO
30%
tf:IN,
tf:OUT
START
tHD:DAT tSU:DAT
tr:IN
STOP
START
Figure 2. 2-Wire Control Interface Read and Write Timing Parameters
SCLK
SDIO
A6-A0,
R/W
D7-D0
D7-D0
START
ADDRESS + R/W
ACK
DATA
ACK
DATA
ACK
STOP
Figure 3. 2-Wire Control Interface Read and Write Timing Diagram
8
Rev. 1.0
Si4704/05-D50
Table 6. 3-Wire Control Interface Characteristics
(V = 2.7 to 5.5 V, V = 1.62 to 3.6 V, TA = –20 to 85 °C)
A
D
Parameter
Symbol
Test Condition
Min
0
Typ
—
—
—
—
—
—
—
—
—
Max
2.5
—
Unit
MHz
ns
SCLK Frequency
SCLK High Time
SCLK Low Time
f
CLK
t
25
25
20
10
10
2
HIGH
t
—
ns
LOW
SDIO Input, SEN to SCLK Setup
SDIO Input to SCLK Hold
t
—
ns
S
t
—
ns
HSDIO
SEN Input to SCLK Hold
t
—
ns
HSEN
SCLK to SDIO Output Valid
SCLK to SDIO Output High Z
SCLK, SEN, SDIO, Rise/Fall Time
t
Read
Read
25
25
10
ns
CDV
t
2
ns
CDZ
t , t
—
ns
R
F
70%
SCLK
30%
tR
tF
tHSDIO
tHIGH
tLOW
tHSEN
tS
70%
tS
SEN
30%
A6-A5,
R/W,
A4-A1
70%
A7
A0
D15
D14-D1
D0
SDIO
30%
Address In
Data In
Figure 4. 3-Wire Control Interface Write Timing Parameters
70%
30%
SCLK
SEN
tHSDIO
tCDV
tHSEN
tS
tCDZ
70%
30%
tS
70%
30%
A6-A5,
R/W,
A4-A1
A7
A0
D15
D14-D1
D0
SDIO
½ Cycle Bus
Turnaround
Address In
Data Out
Figure 5. 3-Wire Control Interface Read Timing Parameters
Rev. 1.0
9
Si4704/05-D50
Table 7. Digital Audio Interface Characteristics
(V = 2.7 to 5.5 V, V = 1.62 to 3.6 V, TA = –20 to 85 °C)
A
D
Parameter
Symbol Test Condition
Min
26
10
10
5
Typ
—
Max
1000
—
Unit
ns
DCLK Cycle Time
t
DCT
DCH
DCLK Pulse Width High
t
—
ns
DCLK Pulse Width Low
t
—
—
ns
DCL
DFS Setup Time to DCLK Rising Edge
DFS Hold Time from DCLK Rising Edge
t
—
—
ns
SU:DFS
HD:DFS
t
5
—
—
ns
DOUT Propagation Delay from DCLK Falling
Edge
t
0
—
12
ns
PD:DOUT
tDCH
tDCL
DCLK
tDCT
DFS
tHD:DFS
tSU:DFS
DOUT
tPD:OUT
Figure 6. Digital Audio Interface Timing Parameters, I2S Mode
10
Rev. 1.0
Si4704/05-D50
Table 8. FM Receiver Characteristics1,2
(V = 2.7 to 5.5 V, V = 1.62 to 3.6 V, TA = –20 to 85 °C, 76–108 MHz)
A
D
Parameter
Symbol
Test Condition
Min
76
—
Typ
—
Max
108
3.5
—
Unit
MHz
Input Frequency
f
RF
3,4,5
Sensitivity
(S+N)/N = 26 dB
2.2
11
µV EMF
µV EMF
6
RDS Sensitivity
f = 2 kHz,
—
RDS BLER < 5%
6,7
6,7
LNA Input Resistance
3
4
4
5
5
6
k
LNA Input Capacitance
pF
6,8
Input IP3
100
40
35
60
35
72
—
—
15
35
55
—
—
70
45
—
—
105
50
50
70
—
—
—
—
—
—
90
1
dBµV EMF
3,4,6,7
m = 0.3
±200 kHz
±400 kHz
In-band
dB
dB
dB
dB
AM Suppression
Adjacent Channel Selectivity
Alternate Channel Selectivity
Spurious Response Rejection
6
3,4,7
80
—
mV
Audio Output Voltage
RMS
3,7,9
dB
Hz
Audio Output L/R Imbalance
Audio Frequency Response Low
6
–3 dB
–3 dB
—
30
—
—
—
—
0.5
80
54
—
—
6
—
kHz
dB
Audio Frequency Response High
7,9
42
63
58
0.1
75
50
34
30
Audio Stereo Separation
3,4,5,7
dB
Audio Mono S/N
4,5,6,7
dB
Audio Stereo S/N
3,7,9
%
Audio THD
6
De-emphasis Time Constant
FM_DEEMPHASIS = 2
FM_DEEMPHASIS = 1
f = ±400 kHz
µs
µs
3,4,5,6,12,13
Blocking Sensitivity
dBµV
dBµV
f = ±4 MHz
Notes:
1. Additional testing information is available in “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure.”
Volume = maximum for all tests. Tested at RF = 98.1 MHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
3. F
= 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.
MOD
4. f = 22.5 kHz.
5. B = 300 Hz to 15 kHz, A-weighted.
AF
6. Guaranteed by characterization.
7. V
= 1 mV.
EMF
8. |f – f | > 2 MHz, f = 2 x f – f . AGC is disabled.
2
1
0
1
2
9. f = 75 kHz.
10. At L and R
pins.
OUT
OUT
11. Analog audio output mode.
12. Blocker Amplitude = 100 dBµV
13. Sensitivity measured at (S+N)/N = 26 dB.
14. At temperature (25°C).
Rev. 1.0
11
Si4704/05-D50
Table 8. FM Receiver Characteristics1,2 (Continued)
(V = 2.7 to 5.5 V, V = 1.62 to 3.6 V, TA = –20 to 85 °C, 76–108 MHz)
A
D
Parameter
Symbol
Test Condition
f = ±400 kHz, ±800 kHz
f = ±4 MHz, ±8 MHz
Single-ended
Min
—
Typ
40
35
—
Max
—
Unit
dBµV
dBµV
k
3,4,5,6,12,13
Intermod Sensitivity
—
—
6,10
R
10
—
—
Audio Output Load Resistance
L
6,10
C
Single-ended
—
50
60
pF
Audio Output Load Capacitance
L
6
Seek/Tune Time
RCLK tolerance
= 100 ppm
—
—
ms/channel
6
Powerup Time
From powerdown
—
—
—
110
3
ms
dB
14
RSSI Offset
Input levels of 8 and
60 dBµV at RF Input
–3
Notes:
1. Additional testing information is available in “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure.”
Volume = maximum for all tests. Tested at RF = 98.1 MHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
3. F
= 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.
MOD
4. f = 22.5 kHz.
5. B = 300 Hz to 15 kHz, A-weighted.
AF
6. Guaranteed by characterization.
7. V
= 1 mV.
EMF
8. |f – f | > 2 MHz, f = 2 x f – f . AGC is disabled.
2
1
0
1
2
9. f = 75 kHz.
10. At L and R
pins.
OUT
OUT
11. Analog audio output mode.
12. Blocker Amplitude = 100 dBµV
13. Sensitivity measured at (S+N)/N = 26 dB.
14. At temperature (25°C).
12
Rev. 1.0
Si4704/05-D50
Table 9. 64–75.9 MHz Input Frequency FM Receiver Characteristics1,2,6
(V = 2.7 to 5.5 V, V = 1.62 to 3.6 V, TA = –20 to 85 °C)
A
D
Parameter
Symbol
Test Condition
Min
64
—
3
Typ
—
Max
75.9
—
5
Unit
MHz
µV EMF
k
Input Frequency
f
RF
3,4,5
Sensitivity
(S+N)/N = 26 dB
3.5
4
7
LNA Input Resistance
7
LNA Input Capacitance
4
5
6
pF
8
Input IP3
—
—
—
—
72
—
—
15
—
—
70
45
10
—
—
105
50
50
70
80
—
—
—
—
—
90
1
dBµV EMF
dB
3,4,7
m = 0.3
±200 kHz
±400 kHz
AM Suppression
dB
Adjacent Channel Selectivity
Alternate Channel Selectivity
dB
3,4,7
mV
Audio Output Voltage
RMS
3,7,9
dB
Audio Output L/R Imbalance
–3 dB
–3 dB
—
30
—
—
—
80
54
—
50
60
Hz
Audio Frequency Response Low
Audio Frequency Response High
—
kHz
3,4,5,7,10
63
0.1
75
50
—
dB
Audio Mono S/N
3,7,9
%
Audio THD
De-emphasis Time Constant
FM_DEEMPHASIS = 2
FM_DEEMPHASIS = 1
Single-ended
µs
µs
k
10
R
Audio Output Load Resistance
L
L
10
C
Single-ended
—
pF
Audio Output Load Capacitance
Seek/Tune Time
RCLK tolerance
= 100 ppm
—
ms/channel
Powerup Time
From powerdown
—
—
—
110
3
ms
dB
11
RSSI Offset
Input levels of 8 and
60 dBµV EMF
–3
Notes:
1. Additional testing information is available in “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure.”
Volume = maximum for all tests. Tested at RF = 98.1 MHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
3. F
= 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.
MOD
4. f = 22.5 kHz.
5. B = 300 Hz to 15 kHz, A-weighted.
AF
6. Guaranteed by characterization.
7. V
= 1 mV.
EMF
8. |f – f | > 2 MHz, f = 2 x f – f . AGC is disabled.
2
1
0
1
2
9. f = 75 kHz.
10. At L and R
pins.
OUT
OUT
11. At temperature (25 °C).
Rev. 1.0
13
Si4704/05-D50
Table 10. Reference Clock and Crystal Characteristics
(V = 2.7 to 5.5 V, V = 1.62 to 3.6 V, TA = –20 to 85 °C)
A
D
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Reference Clock
1,2
RCLK Supported Frequencies
31.130 32.768 40,000
kHz
1,3
RCLK Frequency Tolerance
–100
1
—
—
100
ppm
1,2
REFCLK_PRESCALE
4095
1
REFCLK
31.130 32.768 34.406
kHz
Crystal Oscillator
1
Crystal Oscillator Frequency
—
–100
—
32.768
—
—
kHz
ppm
pF
1,3
Crystal Frequency Tolerance
100
3.5
1
Board Capacitance
—
ESR
40
k
C Single-ended
12
pF
L
Notes:
1. Guaranteed by characterization.
2. The Si4704/05 divide the RCLK input by REFCLK_PRESCALE to obtain REFCLK. There are some RCLK frequencies
between 31.130 kHz and 40 MHz that are not supported. See “AN332: Si47xx Programming Guide,” Table 6 for more
details.
3. A frequency tolerance of ±50 ppm is required for FM seek/tune using 50 kHz channel spacing.
14
Rev. 1.0
Si4704/05-D50
2. Typical Application Schematic
Optional: Digital Audio Out
OPMODE: 0xB0, 0xB5
C9
GPO1
GPO2/INT
R3
R2
R1
GPO3/DCLK
DFS
DOUT
1
15
NC
DOUT
C2
2
3
4
5
14
FM Antenna
FMI
LOUT
LOUT
ROUT
13
RFGND
ROUT
12
Embedded Antenna
Si4704/05
LPI
GND
2.7 to 5.5 V
C1
D50
11
RSTB
VA
VA
1.62 to 3.6 V
C4
VD
RSTB
RCLK
SDIO
SCLK
SENB
GPO3
RCLK
X1
C6
C5
Optional: For Crystal OSC
Notes:
1. Place C1 close to V pin.
A
2. Pins 1 and 20 are no connects, leave floating.
3. Place C4 close to DFS pin.
4. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
5. Pin 2 or Pin 4 connects to the FM antenna interface. Pin 2 is for a half-wave antenna. Pin 4 is for an embedded antenna.
6. Place Si4704/05 as close as possible to antenna jack and keep the FMI and LPI traces as short as possible.
Rev. 1.0
15
Si4704/05-D50
3. Bill of Materials
Table 11. Si4704/05-D50 Bill of Materials
Value/Description
Component(s)
Supplier
Murata
C1
C2
C4
U1
R1
Supply bypass capacitor, 22 nF, ±20%, Z5U/X7R
Coupling capacitor, 1 nF, ±20%, Z5U/X7R
Murata
Supply bypass capacitor, 100 nF, 10%, Z5U/X7R
Si4704/05 FM Radio Tuner
Murata
Silicon Laboratories
Venkel
Resistor, 600
(Optional for digital audio)
R2
R3
Resistor, 2 k
(Optional for digital audio)
Venkel
Venkel
Venkel
Murata
Epson
Resistor, 2 k
(Optional for digital audio)
C5, C6
C9
Crystal load capacitors, 22 pF, ±5%, COG
(Optional for crystal oscillator option)
Noise mitigating capacitor, 2~5 pF
(Optional for digital audio)
X1
32.768 kHz crystal
(Optional for crystal oscillator option)
16
Rev. 1.0
Si4704/05-D50
4. Functional Description
4.1. Overview
FM Antenna
FMI
Si4704/05
ADC
ADC
DAC
LOUT
LNA
PGA
DSP
RFGND
DAC
ROUT
AGC
GPO
LPI
0/90
DCLK
DOUT
DFS
RDS
(Si4705)
32.768 kHz
(TYP)
RCLK
RSSI
AFC
REG
CONTROL
INTERFACE
VA
2.7–5.5 V
XTAL
OSC
Figure 7. Functional Block Diagram
The Si4704/05-D50 offers advanced audio processing The Si4704/05 receiver draws on Silicon Laboratories’
plus advanced RDS processing in a very small, 100% broadcast audio expertise and patent portfolio, using a
CMOS receiver integrated circuit. The device provides digital low intermediate frequency (low-IF) receiver
both analog and digital audio out, and a highly flexible architecture proven by hundreds of millions of Silicon
RDS pre-processor and 100 block RDS buffer. It is an Laboratories’ broadcast audio receivers shipped
ideal product for handsets and portable devices seeking worldwide.
to optimize both sound and data receiver performance.
Silicon Labs has shipped 1/2 billion broadcast audio
For sound, the advanced audio processing is
receivers worldwide using this architecture. The low-IF
unprecedented in portable devices. For RDS data
architecture allows the Si4704/05 to deliver superior
applications such as song-tagging, meta-data, traffic
performance while integrating the great majority of
message channel, or other open data applications, the
external components required by competing solutions.
advanced and patented R(B)DS decoding engine offers
The Si4704/05 digital integration reduces the required
outstanding data synchronization and integrity. The
external components of traditional offerings, resulting in
RDS engine includes demodulation, symbol decoding,
a solution requiring only an external bypass capacitor
2
advanced error correction, detailed visibility to block-
and occupying board space of approximately 15 mm .
error rates (BLER), advanced decoder reliability, and
The Si4704/05 is the first FM radio receiver IC to
synchronization status. The Si4704/05 provides
support embedded antenna technology, allowing the FM
complete, decoded and error-corrected RDS groups
antenna to be integrated into the enclosure or PCB of a
(100 blocks), up to 25 groups at a time. The Si4704/05
portable device. Refer to “AN383: Si47xx Antenna,
offers several modes of operation for various
Schematic, Layout, And Design Guidelines” for antenna
applications which require more or less visibility to the
design guidelines.
RDS status and group data.
The Si4704/05 is feature-rich, providing highly
automated performance with default settings and
extensive programmability and flexibility for customized
system performance.
*Note: The term “RDS” will be used to mean “RDS/RBDS”
throughout the document.
Rev. 1.0
17
Si4704/05-D50
The Si4704/05 performs much of the FM demodulation 4.3.1. Stereo Decoder
digitally to achieve high fidelity, optimal performance
The Si4704/05 integrated stereo decoder automatically
versus power consumption, and flexibility of design. The
on-board DSP provides unmatched pilot rejection,
selectivity, and optimum sound quality. The integrated
micro-controller offers both the manufacturer and the
end-user unmatched programmability and flexibility in
the listening experience.
decodes the MPX signal using DSP techniques. The 0
to 15 kHz (L+R) signal is the mono output of the FM
tuner. Stereo is generated from the (L+R), (L–R), and a
19 kHz pilot tone. The pilot tone is used as a reference
to recover the (L–R) signal. Output left and right
channels are obtained by adding and subtracting the
(L+R) and (L–R) signals, respectively.
4.2. FM Receiver
4.3.2. Stereo-Mono Blending
The Si4704/05 FM receiver is based on the proven
Si4700/01/02/03/04/05 FM radio receiver. The part
leverages Silicon Laboratories' proven and patented FM
broadcast radio receiver digital architecture, delivering
excellent RF performance and interference rejection.
The proven digital techniques provide good sensitivity in
weak signal environments while allowing superb
selectivity and inter-modulation immunity in strong signal
environments.
Adaptive noise suppression is employed to gradually
combine the stereo left and right audio channels to a
mono (L+R) audio signal as the signal quality degrades
to maintain optimum sound fidelity under varying
reception conditions. Three metrics, received signal
strength indicator (RSSI), signal-to-noise ratio (SNR),
and
multipath
interference,
are
monitored
simultaneously in forcing a blend from stereo to mono.
The metric which reflects the minimum signal quality
takes precedence and the signal is blended
appropriately.
The part supports the worldwide FM broadcast band (64
to 108 MHz) with channel spacings of 50–200 kHz. The
low-IF architecture utilizes a single converter stage and
digitizes the signal using a high-resolution analog-to-
digital converter. The audio output can be directed
either to an external headphone amplifier via analog
in/out or to other system ICs through digital audio
All three metrics have programmable stereo/mono
thresholds and attack/release rates detailed in “AN332:
Si47xx Programming Guide.” If a metric falls below its
mono threshold, the signal is blended from stereo to full
mono. If all metrics are above their respective stereo
thresholds, then no action is taken to blend the signal. If
a metric falls between its mono and stereo thresholds,
then the signal is blended to the level proportional to the
metric’s value between its mono and stereo thresholds,
with an associated attack and release rate.
Stereo/mono status can be monitored with the
FM_RSQ_STATUS command.
2
interface (I S) (Si4705 only).
4.3. Stereo Audio Processing
The output of the FM demodulator is a stereo
multiplexed (MPX) signal. The MPX standard was
developed in 1961, and is used worldwide. Today's
MPX signal format consists of left + right (L+R) audio,
left – right (L–R) audio, a 19 kHz pilot tone, and
RDS/RBDS data as shown in Figure 8.
4.4. Received Signal Qualifiers
The quality of a tuned signal can vary depending on
many factors including environmental conditions, time of
day, and position of the antenna. To adequately manage
the audio output and avoid unpleasant audible effects to
the end-user, the Si4704/05-D50 monitors and provides
indicators of the signal quality, allowing the host
processor to perform additional processing if required
by the customer. The Si4704/05-D50 monitors signal
quality metrics including RSSI, SNR, and multipath
interference on FM signals. These metrics are used to
optimize signal processing and are also reported to the
host processor. The signal processing algorithms can
Mono Audio
Left + Right
Stereo
Pilot
Stereo Audio
Left - Right
RDS/
RBDS
0
15 19 23
38
53 57
Frequency (kHz)
Figure 8. MPX Signal Spectrum
use
either
Silicon
Labs'
optimized
settings
(recommended) or be customized to modify
performance.
18
Rev. 1.0
Si4704/05-D50
4.5. De-emphasis
4.10. Tuning
Pre-emphasis and de-emphasis is a technique used by The frequency synthesizer uses Silicon Laboratories’
FM broadcasters to improve the signal-to-noise ratio of proven technology, including a completely integrated
FM receivers by reducing the effects of high-frequency VCO. The frequency synthesizer generates the
interference and noise. When the FM signal is quadrature local oscillator signal used to downconvert
transmitted,
a
pre-emphasis filter is applied to the RF input to a low intermediate frequency. The VCO
accentuate the high audio frequencies. The Si4704/05 frequency is locked to the reference clock and adjusted
incorporates a de-emphasis filter that attenuates high with an automatic frequency control (AFC) servo loop
frequencies to restore a flat frequency response. Two during reception. The tuning frequency can be directly
time constants are used in various regions. The de- programmed using the FM_TUNE_FREQ. The
emphasis time constant is programmable to 50 or 75 µs Si4704/05 supports channel spacing of 50, 100, or
and is set by the FM_DEEMPHASIS property.
200 kHz in FM mode.
4.6. Volume Control
4.11. Seek
The audio output may be muted. Volume is adjusted The Si4704/05 seek functionality is performed
digitally by the RX_VOLUME property.
completely on-chip and will search up or down the
selected frequency band for a valid channel. A valid
4.7. Stereo DAC
channel is qualified according to
a
series of
High-fidelity stereo digital-to-analog converters (DACs) programmable signal indicators and thresholds. The
drive analog audio signals onto the LOUT and ROUT seek function can be made to stop at the band edge and
pins. The audio output may be muted. Volume is provide an interrupt, or wrap the band and continue
adjusted digitally with the RX_VOLUME property.
seeking until arriving at the original departure frequency.
The device sets interrupts with found valid stations or, if
the seek results in zero found valid stations, the device
4.8. Soft Mute
The soft mute feature is available to attenuate the audio indicates failure and again sets an interrupt.(Refer to
outputs and minimize audible noise in very weak signal “AN332: Si47xx Programming Guide”.
conditions. The soft mute feature is triggered by the
SNR metric. The SNR threshold for activating soft mute
is programmable, as are soft mute attenuation levels
and attack and release rates.
The Si4704/05-D50 uses RSSI, SNR, and AFC to
qualify stations. Most of these variables have
programmable thresholds for modifying the seek
function according to customer needs.
RSSI is employed first to screen all possible candidate
stations. SNR and AFC are subsequently used in
screening the RSSI qualified stations. The more
thresholds the system engages, the higher the
confidence that any found stations will indeed be valid
broadcast stations. The Si4704/05-D50 defaults set
RSSI to a mid-level threshold and add an SNR
threshold set to a level delivering acceptable audio
performance. This trade-off will eliminate very low RSSI
stations while keeping the seek time to acceptable
levels. Generally, the time to auto-scan and store valid
channels for an entire FM band with all thresholds
engaged is very short depending on the band content.
4.9. FM Hi-Cut Control
Hi-cut control is employed on audio outputs with
degradation of the signal due to low SNR and/or
multipath interference. Two metrics, SNR and multipath
interference, are monitored concurrently in forcing hi-cut
of the audio outputs. Programmable minimum and
maximum thresholds are available for both metrics. The
transition frequency for hi-cut is also programmable with
up to seven hi-cut filter settings. A single set of attack
and release rates for hi-cut are programmable for both
metrics from a range of 2 ms to 64 s. The level of hi-cut
applied can be monitored with the FM_RSQ_STATUS
command. Hi-cut can be disabled by setting the hi-cut
filter to audio bandwidth of 15 kHz.
Seek is initiated using the FM_SEEK_START
command. The RSSI, SNR, and AFC threshold settings
are adjustable using properties.
Rev. 1.0
19
Si4704/05-D50
4.12.2. Audio Sample Rates
4.12. Digital Audio Interface
The device supports a number of industry-standard
sampling rates including 32, 40, 44.1, and 48 kHz. The
digital audio interface enables low-power operation by
eliminating the need for redundant DACs on the audio
baseband processor.
The digital audio interface operates in slave mode and
supports a variety of MSB-first audio data formats
including I S and left-justified modes. The interface has
2
three pins: digital data input (DIN), digital frame
synchronization input (DFS), and
a
digital bit
synchronization input clock (DCLK). The Si4705
supports a number of industry-standard sampling rates
including 32, 40, 44.1, and 48 kHz. The digital audio
interface enables low-power operation by eliminating
the need for redundant DACs and ADCs on the audio
baseband processor.
4.12.1. Audio Data Formats
The digital audio interface operates in slave mode and
supports three different audio data formats:
2
I S
Left-Justified
DSP Mode
2
In I S mode, by default the MSB is captured on the
second rising edge of DCLK following each DFS
transition. The remaining bits of the word are sent in
order, down to the LSB. The left channel is transferred
first when the DFS is low, and the right channel is
transferred when the DFS is high.
In left-justified mode, by default the MSB is captured on
the first rising edge of DCLK following each DFS
transition. The remaining bits of the word are sent in
order, down to the LSB. The left channel is transferred
first when the DFS is high, and the right channel is
transferred when the DFS is low.
In DSP mode, the DFS becomes a pulse with a width of
1DCLK period. The left channel is transferred first,
followed right away by the right channel. There are two
options in transferring the digital audio data in DSP
mode: the MSB of the left channel can be transferred on
the first rising edge of DCLK following the DFS pulse or
on the second rising edge.
In all audio formats, depending on the word size, DCLK
frequency, and sample rates, there may be unused
DCLK cycles after the LSB of each word before the next
DFS transition and MSB of the next word. In addition, if
preferred, the user can configure the MSB to be
captured on the falling edge of DCLK via properties.
The number of audio bits can be configured for 8, 16,
20, or 24 bits.
20
Rev. 1.0
Si4704/05-D50
INVERTED
DCLK
(OFALL = 1)
(OFALL = 0)
DCLK
DFS
LEFT CHANNEL
I2S
RIGHT CHANNEL
(OMODE = 0000)
1 DCLK
1 DCLK
n-2
DOUT
1
2
3
n-1
n
n-2
n-1
1
2
3
n
MSB
LSB
MSB
LSB
Figure 9. I2S Digital Audio Format
INVERTED
DCLK
(OFALL = 1)
(OFALL = 0)
DCLK
DFS
LEFT CHANNEL
RIGHT CHANNEL
n-2
Left-Justified
(OMODE = 0110)
DOUT
1
2
3
n-2
n-1
n
n-1
n
1
2
3
MSB
LSB
MSB
LSB
Figure 10. Left-Justified Digital Audio Format
(OFALL = 0)
DCLK
DFS
RIGHT CHANNEL
n-2
LEFT CHANNEL
n-2
DOUT
1
2
3
2
n-1
n
(OMODE = 1100)
(OMODE = 1000)
1
2
3
2
n-1
n
(MSB at 1st rising edge)
MSB
LSB
MSB
LSB
LEFT CHANNEL
n-2
1 DCLK
RIGHT CHANNEL
n-2
DOUT
1
3
n-1
n
1
3
n-1
n
(MSB at 2nd rising edge)
MSB
LSB
MSB
LSB
Figure 11. DSP Digital Audio Format
Rev. 1.0
21
Si4704/05-D50
4.13. Embedded Antenna Support
4.14. RDS Decoder (Si4705 Only)
The Si4704/05 is the first FM receiver to support the fast The Si4705 implements an RDS processor for symbol
decoding, block synchronization, error detection, and
error correction.
growing trend to integrate the FM receiver antenna into
the device enclosure. The chip is designed with this
function in mind from the outset, with multiple
international patents pending, thus it is superior to many
other options in price, board space, and performance.
The Si4705 device is user configurable and provides an
optional interrupt when RDS is synchronized, loses
synchronization, and/or the user configurable RDS
FIFO threshold has been met.
Testing indicates that, when using Silicon Laboratories'
patented techniques, embedded antenna performance
can be very similar in many key metrics to a standard
half-wavelength antenna. Refer to “AN383: Si47XX
Antenna, Schematic, Layout, And Design Guidelines”
for additional details on the implementation of support
for an embedded antenna.
The Si4705 reports RDS decoder synchronization
status and detailed bit errors in the information word for
each RDS block with the FM_RDS_STATUS command.
The range of reportable block errors is 0, 1–2, 3–5, or
6+. More than six errors indicates that the
corresponding block information word contains six or
more non-correctable errors or that the block checkword
contains errors.
Figure 12 shows a conceptual block diagram of the
Si4704/05 architecture used to support the embedded
antenna. The half-wavelength FM receive antenna is
therefore optional. Host software can detect the
presence of an external antenna and switch between
the embedded antenna if desired.
4.15. Reference Clock
The Si4704/05 reference clock is programmable,
supporting RCLK frequencies in Table 10. Refer to
Table 3, “DC Characteristics” on page 5 for switching
voltage levels and Table 10, “Reference Clock and
Crystal Characteristics” on page 14 for frequency
tolerance information.
Half-wavelength
Si4704/05
antenna
An onboard crystal oscillator is available to generate the
32.768 kHz reference when an external crystal and load
capacitors are provided. Refer to "2. Typical Application
Schematic" on page 15. This mode is enabled using the
POWER_UP command. Refer to Refer to “AN332:
Si47xx Programming Guide”.
FMI
Integrated
antenna
LPI
RFGND
LNA
AGC
The Si4704/05 performance may be affected by data
activity on the SDIO bus when using the integrated
internal oscillator. SDIO activity results from polling the
tuner for status or communicating with other devices
that share the SDIO bus. If there is SDIO bus activity
while the Si4704/05 is performing the seek/tune
function, the crystal oscillator may experience jitter,
which may result in mistunes, false stops, and/or lower
SNR.
Figure 12. Conceptual Block Diagram of the
Si4704/05 Embedded Antenna Support
For best seek/tune results, Silicon Laboratories
recommends that all SDIO data traffic be suspended
during Si4704/05 seek and tune operations. This is
achieved by keeping the bus quiet for all other devices
on the bus, and delaying tuner polling until the tune or
seek operation is complete. The seek/tune complete
(STC) interrupt should be used instead of polling to
determine when a seek/tune operation is complete.
22
Rev. 1.0
Si4704/05-D50
For write operations, the user then sends an 8-bit data
byte on SDIO, which is captured by the device on rising
edges of SCLK. The Si4704/05 acknowledges each
data byte by driving SDIO low for one cycle, on the next
falling edge of SCLK. The user may write up to 8 data
bytes in a single 2-wire transaction. The first byte is a
command, and the next seven bytes are arguments.
4.16. Control Interface
A serial port slave interface is provided, which allows an
external controller to send commands to the Si4704/05
and receive responses from the device. The serial port
can operate in two bus modes: 2-wire mode and 3-wire
mode. The Si4704/05 selects the bus mode by sampling
the state of the GPO1 and GPO2 pins on the rising
edge of RST. The GPO1 pin includes an internal pull-up
resistor, which is connected while RST is low, and the
GPO2 pin includes an internal pull-down resistor, which
is connected while RST is low. Therefore, it is only
necessary for the user to actively drive pins which differ
from these states. See Table 12.
For read operations, after the Si4704/05 has
acknowledged the control byte, it will drive an 8-bit data
byte on SDIO, changing the state of SDIO on the falling
edge of SCLK. The user acknowledges each data byte
by driving SDIO low for one cycle, on the next falling
edge of SCLK. If a data byte is not acknowledged, the
transaction will end. The user may read up to 16 data
bytes in a single 2-wire transaction. These bytes contain
the response data from the Si4704/05.
Table 12. Bus Mode Select on Rising Edge of
RST
A 2-wire transaction ends with the STOP condition,
which occurs when SDIO rises while SCLK is high. For
details on timing specifications and diagrams, refer to
Table 5, “2-Wire Control Interface Characteristics” on
page 7; Figure 2, “2-Wire Control Interface Read and
Write Timing Parameters,” on page 8, and Figure 3, “2-
Wire Control Interface Read and Write Timing Diagram,”
on page 8.
Bus Mode
2-Wire
GPO1
1
GPO2
0
0
3-Wire
0 (must drive)
After the rising edge of RST, the pins GPO1 and GPO2
are used as general purpose output (O) pins as
described in Section “4.17. GPO Outputs”. In any bus
4.16.2. 3-Wire Control Interface Mode
mode, commands may only be sent after V and V
IO
DD
supplies are applied.
When selecting 3-wire mode, the user must ensure that
a rising edge of SCLK does not occur within 300 ns
before the rising edge of RST.
In any bus mode, before sending a command or reading
a response, the user must first read the status byte to
ensure that the device is ready (CTS bit is high).
The 3-wire bus mode uses the SCLK, SDIO, and SEN_
pins. A transaction begins when the user drives SEN
low. Next, the user drives a 9-bit control word on SDIO,
which is captured by the device on rising edges of
SCLK. The control word consists of a 3-bit device
address (A7:A5 = 101b), a read/write bit (read = 1, write
= 0), and a 5-bit register address (A4:A0).
4.16.1. 2-Wire Control Interface Mode
When selecting 2-wire mode, the user must ensure that
SCLK is high during the rising edge of RST, and stays
high until after the first start condition. Also, a start
condition must not occur within 300 ns before the rising
edge of RST.
For write operations, the control word is followed by a
16-bit data word, which is captured by the device on
rising edges of SCLK.
The 2-wire bus mode uses only the SCLK and SDIO
pins for signaling. A transaction begins with the START
condition, which occurs when SDIO falls while SCLK is
high. Next, the user drives an 8-bit control word serially
on SDIO, which is captured by the device on rising
edges of SCLK. The control word consists of a 7-bit
device address, followed by a read/write bit (read = 1,
write = 0). The Si4704/05 acknowledges the control
word by driving SDIO low on the next falling edge of
SCLK.
For read operations, the control word is followed by a
delay of one-half SCLK cycle for bus turn-around. Next,
the Si4704/05 will drive the 16-bit read data word
serially on SDIO, changing the state of SDIO on each
rising edge of SCLK.
A transaction ends when the user sets SEN high, then
pulses SCLK high and low one final time. SCLK may
either stop or continue to toggle while SEN is high.
Although the Si4704/05 will respond to only a single
device address, this address can be changed with the
SEN pin (note that the SEN pin is not used for signaling
in 2-wire mode). When SEN = 0, the 7-bit device
address is 0010001b. When SEN = 1, the address is
1100011b.
In 3-wire mode, commands are sent by first writing each
argument to register(s) 0xA1–0xA3, then writing the
command word to register 0xA0. A response is
retrieved by reading registers 0xA8–0xAF.
Rev. 1.0
23
Si4704/05-D50
For details on timing specifications and diagrams, refer
to Table 6, “3-Wire Control Interface Characteristics” on
page 9; Figure 4, “3-Wire Control Interface Write Timing
Parameters,” on page 9, and Figure 5, “3-Wire Control
Interface Read Timing Parameters,” on page 9.
4.19. Programming with Commands
To ease development time and offer maximum
customization, the Si4704/05 provides a simple yet
powerful software interface to program the receiver. The
device is programmed using commands, arguments,
properties, and responses. To perform an action, the
user writes a command byte and associated arguments,
causing the chip to execute the given command.
Commands control an action such as powerup the
device, shut down the device, or tune to a station.
Arguments are specific to a given command and are
used to modify the command. A complete list of
commands is available in “AN332: Si47xx Programming
Guide”.
4.17. GPO Outputs
The Si4704/05 provides three general-purpose output
pins. The GPO pins can be configured to output a
constant low, constant high, or high-Z. The GPO pins
are multiplexed with the bus mode pins or DCLK,
depending on the application schematic of the device.
GPO2/INT can be configured to provide interrupts for
seek and tune complete, receive signal quality, and
RDS.
Properties are a special command argument used to
modify the default chip operation and are generally
configured immediately after powerup. Examples of
properties are de-emphasis level, RSSI seek threshold,
and soft mute attenuation threshold. Responses provide
the user information and are echoed after a command
and associated arguments are issued. All commands
provide a one-byte status update indicating interrupt
and clear-to-send status information. For a detailed
description of the commands and properties for the
Si4704/05, see “AN332: Si47xx Programming Guide”.
4.18. Reset, Powerup, and Powerdown
Setting the RST pin low will disable analog and digital
circuitry, reset the registers to their default settings, and
disable the bus. Setting the RST pin high will bring the
device out of reset. A powerdown mode is available to
reduce power consumption when the part is idle. Putting
the device in powerdown mode will disable analog and
digital circuitry while keeping the bus active.
24
Rev. 1.0
Si4704/05-D50
5. Commands and Properties
Refer to “AN332: Si47xx Programming Guide”.
Rev. 1.0
25
Si4704/05-D50
6. Pin Descriptions: Si4704/05-GM
20 19 18 17
NC
1
16
FMI 2
RFGND 3
LPI 4
15 DOUT
14 LOUT
13 ROUT
12 GND
11 VA
GND
PAD
RST 5
6
7
8
9
10
Pin Number(s)
Name
NC
Description
1, 20
2
No connect. Leave floating.
FM RF input.
FMI
3
RFGND
LPI
RF ground. Connect to ground plane on PCB.
Loop antenna RF input.
4
5
Device reset input (active low).
Serial enable input (active low).
Serial clock input.
RST
6
SEN
7
SCLK
SDIO
RCLK
8
Serial data input/output.
9
External reference or crystal oscillator input.
Digital and I/O supply voltage.
Analog supply voltage. May be connected directly to battery.
Right audio analog line output.
Left audio analog line output.
10
11
13
14
15
16
17
V
D
V
A
ROUT
LOUT
DOUT
DFS
Digital audio output data.
Digital frame synchronization.
GPO3/DCLK General purpose output/digital bit synchronous clock or crystal oscillator
input.
18
19
General purpose output/interrupt.
General purpose output.
GPO2/INT
GPO1
12, GND PAD
GND
Ground. Connect to ground plane on PCB.
26
Rev. 1.0
Si4704/05-D50
7. Ordering Guide
Part Number*
Description
Package
Type
Operating
Temperature
Si4704-D50-GM FM Broadcast Radio Receiver
QFN
Pb-free
–20 to 85 °C
–20 to 85 °C
Si4705-D50-GM FM RDS Broadcast Radio Receiver
QFN
Pb-free
*Note: Add an “(R)” at the end of the device part number to denote tape and reel option.
Rev. 1.0
27
Si4704/05-D50
8. Package Markings
8.1. Si4704 Top Mark
0450
DTTT
YWW
Figure 13. Si4704 Top Mark
8.2. Si4705 Top Mark
0550
DTTT
YWW
Figure 14. Si4705 Top Mark
8.3. Top Mark Explanation
Mark Method:
YAG Laser
Line 1 Marking:
Part Number
04 = Si4704
05 = Si4705
Firmware Revision
R = Die Revision
50 = Firmware Revision 5.0
D = Revision D Die.
Line 2 Marking:
Line 3 Marking:
TTT = Internal Code
Internal tracking code.
Circle = 0.5 mm Diameter Pin 1 Identifier.
(Bottom-Left Justified)
Y = Year
Assigned by the Assembly House. Corresponds to the last
significant digit of the year and workweek of the mold date.
WW = Workweek
28
Rev. 1.0
Si4704/05-D50
9. Package Outline: Si4704/05
Figure 15 illustrates the package details for the Si4704/05. Table 13 lists the values for the dimensions shown in
the illustration.
Figure 15. 20-pin Quad Flat No-Lead (QFN)
Table 13. Package Dimensions
Symbol
Millimeters
Nom
Symbol
Millimeters
Nom
Min
Max
Min
Max
A
A1
b
0.50
0.00
0.18
0.27
0.55
0.02
0.60
0.05
0.30
0.37
f
2.53 BSC
L
0.35
0.00
—
0.40
—
0.45
0.10
0.05
0.05
0.08
0.10
0.10
0.25
L1
c
0.32
aaa
bbb
ccc
ddd
eee
—
D
3.00 BSC
1.70
—
—
D2
e
1.60
1.80
—
—
0.50 BSC
3.00 BSC
1.70
—
—
E
—
—
E2
1.60
1.80
Notes:
1. All dimensions are shown in millimeters unless otherwise noted.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
Rev. 1.0
29
Si4704/05-D50
10. PCB Land Pattern: Si4704/05
Figure 16 illustrates the PCB land pattern details for the Si4704/05-GM. Table 14 lists the values for the dimensions
shown in the illustration.
Figure 16. PCB Land Pattern
30
Rev. 1.0
Si4704/05-D50
Table 14. PCB Land Pattern Dimensions
Symbol
Millimeters
Min Max
2.71 REF
1.60 1.80
Symbol
Millimeters
Min
Max
D
D2
e
GE
W
2.10
—
—
0.34
0.28
0.50 BSC
2.71 REF
X
—
E
Y
0.61 REF
E2
f
1.60
2.53 BSC
2.10
1.80
ZE
ZD
—
—
3.31
3.31
GD
—
Notes: General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and tolerancing is per the ANSI Y14.5M-1994 specification.
3. This land pattern design is based on IPC-SM-782 guidelines.
4. All dimensions shown are at maximum material condition (MMC). Least material
condition (LMC) is calculated based on a fabrication allowance of 0.05 mm.
Notes: Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the
pad.
Notes: Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls
should be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
4. A 1.45 x 1.45 mm square aperture should be used for the center pad. This
provides approximately 70% solder paste coverage on the pad, which is optimum
to assure correct component stand-off.
Notes: Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for small body components.
Rev. 1.0
31
Si4704/05-D50
11. Additional Reference Resources
Customer Support Site:
This site contains all application notes, evaluation board schematics and layouts, and evaluation software. NDA
is required for complete access. Please visit the Silicon Labs Technical Support web page:
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support
request.
AN332: Si47xx Programming Guide
AN342: Quick Start Guide
AN383: Si47xx Antenna, Schematic, Layout and Design Guidelines
AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure
Si47xx EVB User’s Guide
32
Rev. 1.0
Si4704/05-D50
DOCUMENT CHANGE LIST:
Revision 0.2 to Revision 1.0
Updated functional block diagram
Updated specification tables, removed TBDs
Updated “2. Typical Application Schematic”
Updated“3. Bill of Materials”
Added support for FM for 64–75.9 MHz frequency
range
Added Section “4.6. Volume Control”
Digital audio output now available in Si4704-D50
Removed references to "AN344: Si4706/07/4x
Programming Guide"
Rev. 1.0
33
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www.silabs.com/products
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Disclaimer
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using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific
device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories
reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy
or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply
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相关型号：
SI4705-C40
Worldwide FM band support (64-108 MHz) integrated antenna support EN55020 compliant
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