SI4709-C [SILICON]
BROADCAST FM RADIO TUNER FOR PORTABLE APPLICATIONS;
| 型号： | SI4709-C |
| 厂家： | 
SILICON |
| 描述： | BROADCAST FM RADIO TUNER FOR PORTABLE APPLICATIONS |
| 文件： | 总40页 (文件大小：1398K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si4708/09-C
BROADCAST FM RADIO TUNER FOR PORTABLE APPLICATIONS
Features
Worldwide FM band support
Adjustable soft mute
Volume control
(76–108 MHz)
Digital low-IF receiver
Line-level analog output
32.768 kHz reference clock
Frequency synthesizer with
integrated VCO
2-wire and 3-wire control
Adjustable seek tuning
interface
Ordering Information:
Automatic frequency control
2.7 to 5.5 V supply voltage
D
See page 34.
(AFC)
2.7 to 5.5 V supply voltage
A
Automatic gain control (AGC)
Excellent overload immunity
Signal strength measurement
Integrated LDO regulator allows
Pin Assignments
(Top View)
direct connection to battery
2.5 x 2.5 mm 16-pin QFN
package
Pb-free/RoHS compliant
RDS/RBDS Processor (Si4709)
Programmable de-emphasis
(50/75 µs)
Si4708/09-GM
Adaptive noise suppression
1
2
16
15
14
13
LOUT
Applications
FMI
12 ROUT
GND
PAD
Cellular handsets
MP3 players
Portable navigation USB FM radio
Consumer electronics PDAs
RFGND
3
11 GND
4
5
10 VD
9
RST
SEN
Portable radios
Mobile Internet
Notebook PCs
Net PCs
6
7
8
devices
Description
The Si4708/09 is the world's smallest FM broadcast receiver, integrating
the complete tuner function from antenna input to stereo audio output with
RDS (Si4709).
This product, its features, and/or its
architecture is covered by one or
more of the following patents, as well
as other patents, pending and
issued, both foreign and domestic:
7,127,217; 7,272,373; 7,272,375;
7,321,324; 7,355,476; 7,426,376;
7,471,940; 7,339,503; 7,339,504.
Functional Block Diagram
Headphone
Si4708/09
Cable
I
LOUT
DAC
DAC
GPIO
Notes:
ADC
FMI
1. To ensure proper operation and FM
receiver performance, follow the
guidelines in “AN350: Si4708/09
Antenna, Schematic, Layout, and
Design Guidelines" and “AN383:
Si47xx Antenna Selection and
Universal Layout Guidelines.” Silicon
Laboratories will evaluate schematics
and layouts for qualified customers.
2. Place Si4708/09 as close as possible
to antenna jack and keep the FMI
trace as short as possible.
LNA
PGA
DSP
RFGND
Q
ADC
ROUT
GPO
AGC
TUNE
REG
0 / 90
LOW-IF
32.768 kHz
VIO
RST
RCLK
RDS
(Si4709)
AFC
SDIO
SCLK
SEN
VA
VD
RSSI
Rev. 1.2 10/10
Copyright © 2010 by Silicon Laboratories
Si4708/09-C
Si4708/09-C
2
Rev. 1.2
Si4708/09-C
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
4.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
4.2. FM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
4.3. General Purpose Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
4.4. RDS/RBDS Processor and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
4.5. Stereo Audio Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
4.6. Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
4.7. Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.8. Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.9. Reset, Powerup, and Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.10. Audio Output Summation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.11. Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.12. Programming Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
5. Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
6. Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
7. Pin Descriptions: Si4708/09-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
9. Package Markings (Top Marks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
9.1. Si4708 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
9.2. Si4709 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
9.3. Top Mark Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
10. Package Outline: Si4708/09-GM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
11. PCB Land Pattern: Si4708/09-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
12. Additional Reference Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Rev. 1.2
3
Si4708/09-C
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol Test Condition
Min
2.7
2.7
1.62
–20
10
Typ
—
Max
5.5
5.5
3.6
85
Unit
V
Digital Supply Voltage
V
D
Analog Supply Voltage
V
—
V
A
Interface Supply Voltage
V
—
V
IO
Ambient Temperature
T
25
—
°C
µs
µs
µs
A
Digital Power Supply Power-Up Rise Time
Analog Power Supply Power-Up Rise Time
Interface Power Supply Power-Up Rise Time
V
—
DRISE
V
10
—
—
ARISE
V
10
—
—
IRISE
Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at V = V = 3.3 V and 25 °C unless otherwise stated. Parameters are tested in production unless
D
A
otherwise stated.
Table 2. Absolute Maximum Ratings1,2
Parameter
Symbol
Value
–0.5 to 5.8
–0.5 to 5.8
–0.5 to 3.9
±10
Unit
V
Digital Supply Voltage
Analog Supply Voltage
Interface Supply Voltage
V
D
V
V
A
V
V
IO
IN
3
Input Current
I
mA
V
3
Input Voltage
V
–0.3 to (V + 0.3)
IN
IO
Operating Temperature
Storage Temperature
T
–40 to 95
–55 to 150
0.4
°C
°C
OP
T
STG
4
RF Input Level
V
pK
Notes:
1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure beyond
recommended operating conditions for extended periods may affect device reliability.
2. The Si4708/09 device is a high-performance RF integrated circuit with an ESD rating of < 2 kV HBM. Handling and
assembly of this device should only be done at ESD-protected workstations.
3. For input pins SCLK, SEN, SDIO, RST, RCLK, and GPO.
4. At RF input pins.
4
Rev. 1.2
Si4708/09-C
Table 3. DC Characteristics
(VD = VA = 2.7 to 3.6 V, VIO = 1.62 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
FM Receiver to Line Output
V
V
V
Supply Current
Supply Current
I
I
I
—
—
—
16.4
18.2
17
19.3
21.1
19.8
mA
mA
mA
DD
DD
DD
FM
FM
FM
1
Low SNR level
2
RDS Supply Current
Supplies and Interface
Interface Supply Current
I
—
—
300
2.6
4.4
4.0
—
—
—
—
—
µA
µA
µA
µA
V
IO
Digital Powerdown Current
Analog Powerdown Current
I
DDPD
I
Enable = 0
—
APD
V
Powerdown Current
I
SCLK, RCLK inactive
—
IO
IOPD
3
High Level Input Voltage
V
0.7 x V
–0.3
–10
–10
V
+ 0.3
IO
IH
IO
3
Low Level Input Voltage
V
—
0.3 x V
10
V
IL
IO
3
High Level Input Current
I
V
= V = 3.6 V
—
µA
µA
IH
IN
IO
3
Low Level Input Current
I
V
= 0 V,
IN
—
10
IL
V
= 3.6 V
IO
4
High Level Output Voltage
V
I
= 500 µA
0.8 x V
—
—
—
—
V
V
OH
OUT
OUT
IO
4
Low Level Output Voltage
V
I
= –500 µA
0.2 x V
OL
IO
Notes:
1. LNA is automatically switched to higher current mode for optimum sensitivity in weak signal conditions.
2. Guaranteed by characterization.
3. For input pins SCLK, SEN, SDIO, RST, RCLK, DCLK, DFS, GPO1, GPO2, and GPO3.
4. For output pins SDIO, DOUT, GPO1, GPO2, and GPO3.
Rev. 1.2
5
Si4708/09-C
Table 4. Reset Timing Characteristics (Busmode Select Method)1,2,3
(VDD = 2.7 to 5.5 V, VIO = 1.62 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Min
30
Typ
—
Max
—
Unit
ns
SEN Input to RSTSetup
SEN Input to RSTHold
Notes:
t
SRST1
t
30
—
—
ns
HRST1
1. When selecting 2-wire Mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST.
2. When selecting 3-wire Mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RST.
3. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until
after the 1st start condition.
tSRST
tHRST
70%
30%
RST
SEN
70%
30%
Figure 1. Reset Timing Parameters
6
Rev. 1.2
Si4708/09-C
Table 5. 3-Wire Control Interface Characteristics
(VD = VA = 2.7 to 5.5 V, VIO = 1.62 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
0
Typ
—
—
—
—
—
—
—
—
—
Max
2.5
—
Unit
MHz
ns
SCLK Frequency
f
CLK
SCLK High Time
t
25
25
20
10
10
10
2
HIGH
SCLK Low Time
t
—
ns
LOW
SDIO Input, SEN to SCLKSetup
SDIO Input to SCLKHold
SEN Input to SCLKHold
SEN Input to SCLKHold
SCLKto SDIO Output Valid
SCLKto SDIO Output High Z
t
—
ns
S
t
t
—
ns
HSDIO
—
ns
HSEN1
HSEN2
t
—
ns
t
Read
Read
25
25
ns
CDV
t
2
ns
CDZ
Note: When selecting 3-wire Mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RST.
70%
SCLK
30%
tHSDIO
tHIGH
tLOW
tHSEN1
tHSEN2
tS
70%
30%
tS
SEN
A6-A5,
R/W,
A4-A1
70%
30%
A7
A0
D15
D14-D1
D0
SDIO
Address In
Data In
Figure 2. 3-Wire Control Interface Write Timing Parameters
70%
30%
SCLK
SEN
tHSDIO
tCDV
tHSEN1
tHSEN2
tS
tCDZ
70%
30%
tS
80%
20%
A6-A5,
R/W,
A4-A1
A7
A0
D15
D14-D1
D0
SDIO
½ Cycle Bus
Turnaround
Address In
Data Out
Figure 3. 3-Wire Control Interface Read Timing Parameters
Rev. 1.2
7
Si4708/09-C
Table 6. 2-Wire Control Interface Characteristics1,2,3
(VD = VA = 2.7 to 5.5 V, VIO = 1.62 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol Test Condition
Min
0
Typ
—
Max
400
—
Unit
kHz
µs
SCLK Frequency
SCLK Low Time
SCLK High Time
f
SCL
t
1.3
0.6
0.6
—
LOW
t
—
—
µs
HIGH
SCLK Input to SDIO Setup
t
t
—
—
µs
SU:STA
(START)
SCLK Input to SDIO Hold (START)
SDIO Input to SCLK Setup
0.6
100
—
—
—
—
—
—
—
—
—
µs
ns
ns
µs
µs
ns
ns
HD:STA
SU:DAT
t
t
4,5
SDIO Input to SCLK Hold
0
900
—
HD:DAT
SU:STO
SCLK input to SDIO Setup (STOP)
STOP to START Time
t
0.6
t
1.3
—
BUF
SDIO Output Fall Time
t
20 + 0.1 C
20 + 0.1 C
250
300
f:OUT
b
b
SDIO Input, SCLK Rise/Fall Time
t
t
f:IN
r:IN
SCLK, SDIO Capacitive Loading
Input Filter Pulse Suppression
Notes:
C
—
—
—
—
50
50
pF
ns
b
t
SP
1. When VIO = 0 V, SCLK and SDIO are low impedance.
2. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high
until after the 1st start condition.
3. When selecting 2-wire Mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST.
4. As a 2-wire transmitter, the Si4708/09-C delays SDIO by a minimum of 300 ns from the VIH threshold of SCLK to
comply with the 0 ns tHD:DAT specification.
5. The maximum tHD:DAT has only to be met when fSCL = 400 kHz. At frequencies below 400 kHz, tHD:DAT may be violated
so long as all other timing parameters are met.
8
Rev. 1.2
Si4708/09-C
tSU:STA tHD:STA
tLOW
tHIGH
tr:IN
tf:IN
tSP
tSU:STO
tBUF
70%
30%
SCLK
SDIO
70%
30%
tf:IN,
tf:OUT
START
tHD:DAT tSU:DAT
tr:IN
STOP
START
Figure 4. 2-Wire Control Interface Read and Write Timing Parameters
SCLK
A6-A0,
R/W
D7-D0
D7-D0
SDIO
START
ADDRESS + R/W
ACK
DATA
ACK
DATA
ACK
STOP
Figure 5. 2-Wire Control Interface Read and Write Timing Diagram
Rev. 1.2
9
Si4708/09-C
Table 7. FM Receiver Characteristics1,2
(V = V = 2.7 to 5.5 V, V = 1.62 to 3.6 V, TA = –20 to 85 °C)
D
A
IO
Parameter
Symbol
Test Condition
Min
76
—
Typ
—
Max
108
3.5
—
Unit
MHz
Input Frequency
f
RF
3,4,5,6,7
Sensitivity
(S+N)/N = 26 dB
(S+N)/N = 26 dB
1.7
1.1
µVEMF
µVEMF
Sensitivity (50 matching
—
3,4,5,6,8
network)
8
RDS Sensitivity
f = 2 kHz,
—
15
—
µVEMF
RDS BLER < 5%
8,9
LNA Input Resistance
3
4
4
5
5
6
k
pF
8,9
LNA Input Capacitance
8,10
Input IP3
103
40
35
60
35
—
106
55
—
—
—
—
—
—
200
50
90
1
dBµVEMF
dB
3,4,5,8,9
AM Suppression
m = 0.3
±200 kHz
±400 kHz
In-band
Adjacent Channel Selectivity
Alternate Channel Selectivity
Spurious Response Rejection
RCLK Frequency
50
dB
70
dB
8
—
dB
32.768
—
kHz
11
RCLK Frequency Tolerance
SPACE[1:0] = 00 or 01 –200
ppm
SPACE[1:0] = 10
–50
72
—
—
3,4,5,9
Audio Output Voltage
80
mV
RMS
3,4,9,12
8
Audio Output L/R Imbalance
—
dB
–3 dB
–3 dB
—
—
30
—
—
Hz
kHz
dB
Audio Frequency Response Low
8
15
25
—
Audio Frequency Response High
3,9,12
Audio Stereo Separation
—
Notes:
1. Additional testing information is available in Application Note AN388. Volume = maximum for all tests.
2. Important Note: To ensure proper operation and FM receiver performance, follow the guidelines in “AN350: Si4708/09
Antenna, Schematic, Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for
qualified customers.
3. F
= 1 kHz, 75 µs de-emphasis
MOD
4. MONO = 1, and L = R unless noted otherwise.
5. f = 22.5 kHz.
6. B = 300 Hz to 15 kHz, A-weighted.
AF
7. Typical sensitivity with headphone matching network.
8. Guaranteed by characterization.
9. V
= 1 mV.
EMF
10. |f – f | > 1 MHz, f = 2 x f – f . AGC is disabled by setting AGCD = 1. Refer to "6. Register Descriptions" on page
2
1
0
1
2
20.
11. The channel spacing is selected with the SPACE[1:0] bits. Refer to "6. Register Descriptions" on page 20. Seek/Tune
timing is guaranteed for 100 and 200 kHz channel spacing. ±50 ppm PCLK tolerance required for 50 kHz channel
spacing.
12. f = 75 kHz.
13. The de-emphasis time constant is selected with the DE bit. Refer to "6. Register Descriptions" on page 20.
14. At LOUT and ROUT pins.
15. Do not enable STC interrupts before the powerup time is complete. If STC interrupts are enabled before the powerup
time is complete, an interrupt will be generated within the powerup interval when the initial default tune operation is
complete. See "AN349: Si4708/09 Programming Guide" for more information.
16. Minimum and maximum at room temperature (25 °C).
10
Rev. 1.2
Si4708/09-C
Table 7. FM Receiver Characteristics1,2 (Continued)
(V = V = 2.7 to 5.5 V, V = 1.62 to 3.6 V, TA = –20 to 85 °C)
D
A
IO
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
BLNDADJ = 10
10 dB stereo separation
3,8,12
Mono/Stereo Switching Level
—
34
—
dBµVEMF
3,4,5,6,9
Audio Mono S/N
55
—
60
58
—
—
dB
dB
%
3,5,6,8
Audio Stereo S/N
BLNDADJ = 10
3,4,9,12
Audio THD
—
0.1
75
0.5
80
54
0.9
13
De-emphasis Time Constant
DE = 0
DE = 1
70
µs
µs
V
45
50
14
Audio Common Mode Voltage
ENABLE = 1
0.65
0.8
ENABLE = 0
AHIZEN = 1
14
8,14
Audio Common Mode Voltage
—
0.5 x V
—
V
IO
Audio Output Load Resistance
R
Single-ended
Single-ended
10
—
—
—
—
—
—
50
60
k
L
8,14
Audio Output Load Capacitance
C
pF
L
8,11
Seek/Tune Time
SPACE[1:0] = 0x,
RCLK
ms/
channel
tolerance = 200 ppm,
(x = 0 or 1)
15
Powerup Time
From powerdown
(Write ENABLE bit to 1)
—
—
—
110
3
ms
dB
16
RSSI Offset
Input levels of 8 and
60 dBµV at RF input
–3
Notes:
1. Additional testing information is available in Application Note AN388. Volume = maximum for all tests.
2. Important Note: To ensure proper operation and FM receiver performance, follow the guidelines in “AN350: Si4708/09
Antenna, Schematic, Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for
qualified customers.
3. F
= 1 kHz, 75 µs de-emphasis
MOD
4. MONO = 1, and L = R unless noted otherwise.
5. f = 22.5 kHz.
6. B = 300 Hz to 15 kHz, A-weighted.
AF
7. Typical sensitivity with headphone matching network.
8. Guaranteed by characterization.
9. V
= 1 mV.
EMF
10. |f – f | > 1 MHz, f = 2 x f – f . AGC is disabled by setting AGCD = 1. Refer to "6. Register Descriptions" on page
2
1
0
1
2
20.
11. The channel spacing is selected with the SPACE[1:0] bits. Refer to "6. Register Descriptions" on page 20. Seek/Tune
timing is guaranteed for 100 and 200 kHz channel spacing. ±50 ppm PCLK tolerance required for 50 kHz channel
spacing.
12. f = 75 kHz.
13. The de-emphasis time constant is selected with the DE bit. Refer to "6. Register Descriptions" on page 20.
14. At LOUT and ROUT pins.
15. Do not enable STC interrupts before the powerup time is complete. If STC interrupts are enabled before the powerup
time is complete, an interrupt will be generated within the powerup interval when the initial default tune operation is
complete. See "AN349: Si4708/09 Programming Guide" for more information.
16. Minimum and maximum at room temperature (25 °C).
Rev. 1.2
11
Si4708/09-C
2. Typical Application Schematic
R1
GPO
LOUT
1
12
11
10
9
ROUT
NC
2
ROUT
GND
VD
FMI
FMIP
3
4
VBATTERY
2.7 to 5.5 V
RFGND
RFGND
RST
RCLK
C1
RST
SEN
RCLK
SCLK
SDIO
VIO
1.62 to 3.6 V
Notes:
1. Place C1 close to V pin.
D
2. All grounds connect directly to GND plane on PCB.
3. Pins 1 and 16 are no connects, leave floating.
4. Important Note: FM Receiver performance is subject to adherence to antenna design guidelines in “AN350: Si4708/09
Antenna, Schematic, Layout, and Design Guidelines.” Failure to use these guidelines may negatively affect the
performance of the Si4708/09, particularly in weak signal and noisy environments. Silicon Laboratories will evaluate
schematics and layouts for qualified customers.
5. Pin 2 connects to the antenna interface, refer to “AN350: Si4708/09 Antenna, Schematic, Layout, and Design
Guidelines” and "AN383: Si47xx Antenna, Schematic, Layout, and Design Guidelines."
6. RFGND should be locally isolated from GND, refer to “AN350: Si4708/09 Antenna, Schematic, Layout, and Design
Guidelines.”
7. Place Si4708/09 as close as possible to antenna jack and keep the FMI trace as short as possible.
8. V and V may be supplied from the same V or may be supplied by independent power supplies.
A
D
BAT
9. Place R1 on the opposite side of the PCB as the tuner (as close to pin 15 as possible), and route the GPO trace to the
system controller on this layer.
3. Bill of Materials
Component(s)
Value/Description
Supplier(s)
C1
R1
U1
Supply bypass capacitor, 22 nF, ±20%, Z5U/X7R
GPO resistor, 1 k
Murata
Venkel
Si4708/09 FM Radio Tuner
Silicon Laboratories
12
Rev. 1.2
Si4708/09-C
4. Functional Description
Headphone
Cable
Si4708/09
I
LOUT
DAC
ADC
FMI
LNA
PGA
DSP
RFGND
Q
ADC
ROUT
GPO
DAC
AGC
0 / 90
LOW-IF
GPIO
32.768 kHz
VIO
RST
RCLK
TUNE
RDS
(Si4709)
AFC
SDIO
SCLK
SEN
VA
REG
VD
RSSI
Figure 6. Si4708/09 FM Receiver Block Diagram
RDS status, data, and block errors. Si4709 RDS
4.1. Overview
software is backwards compatible to the proven
Si4701/03, adopted by leading cell-phone and MP3
manufacturers world-wide.
The Si4708/09 extends Silicon Laboratories Si4700 FM
tuner family, and further increases the ease and
attractiveness of adding FM radio reception to mobile
devices through small size and board area, minimum
component count, flexible programmability, and
superior, proven performance. Si4708/09 software is
backwards compatible to existing Si4700/01/02/03 FM
Tuner designs and leverages Silicon Laboratories'
highly successful and patented Si4700/01/02/03 FM
tuner. The Si4708/09 benefits from proven digital
integration and 100% CMOS process technology,
resulting in a completely integrated solution. It is the
The Si4708/09 is based on the superior, proven
performance of Silicon Laboratories' Si4700/01/02/03
architecture offering unmatched interference rejection
and leading sensitivity. The device uses the same
programming interface as the Si4700/01/02/03 and
supports multiple bus modes. Power management is
simplified with an integrated regulator allowing direct
connection to a 2.7 to 5.5 V battery for V and 2.7 to 5.5
D
V battery for V .
A
industry's smallest footprint FM tuner IC requiring only The Si4708/09 device’s high level of integration and
2
6.25 mm board space and one external bypass complete FM system production testing increases
capacitor.
quality to manufacturers, improves device yields, and
simplifies device manufacturing and final testing.
The device offers significant programmability, catering
to the subjective nature of FM listeners’ audio
preferences and variable FM broadcast environments
worldwide.
*Note: RDS/RBDS is referred to as RDS throughout the
remainder of this document.
The Si4709 incorporates a digital processor for the
European Radio Data System (RDS) and the US Radio
Broadcast Data System (RBDS) including all required
symbol decoding, block synchronization, error
detection, and error correction functions.
RDS/RDBS* enables data such as station identification
and song name to be displayed to the user. The Si4709
offers a detailed RDS view and a standard view,
allowing adopters to selectively choose granularity of
Rev. 1.2
13
Si4708/09-C
4.2. FM Receiver
4.4. RDS/RBDS Processor and
Functionality
The Si4708/09 architecture and antenna design
increases system performance. To ensure proper
performance and operation, designers should refer to
the guidelines in "AN350: Si4708/09 Antenna,
The Si4709 implements an RDS/RBDS processor for
symbol decoding, block synchronization, error
detection, and error correction. RDS functionality is
enabled by setting the RDS bit. The device offers two
RDS modes, a standard mode and a verbose mode.
The primary difference is increased visibility to RDS
block-error levels and synchronization status with
verbose mode.
Schematic,
Layout,
and
Design
Guidelines".
Conformance to these guidelines will help to ensure
excellent performance in weak signal, noisy, and
crowded signal environments where many strong
channels are present.
The Si4708/09’s patented digital low-IF architecture
reduces external components and eliminates the need
for factory adjustments. The receive (RX) section
integrates a low noise amplifier (LNA) supporting the
worldwide FM broadcast band (76 to 108 MHz). An
automatic gain control (AGC) circuit controls the gain of
the LNA to optimize sensitivity and rejection of strong
interferers.
Setting the RDS mode (RDSM) bit low places the
device in standard RDS mode (default). The device will
set the RDS ready (RDSR) bit for a minimum of 40 ms
when a valid RDS group has been received. Setting the
RDS interrupt enable (RDSIEN) bit and GPO[1:0] = 01
will configure GPO to pulse low for a minimum of 5 ms
when a valid RDS group has been received. If an invalid
group is received, RDSR will not be set and GPO will
not pulse low. In standard mode RDS synchronization
(RDSS) and block error rate A, B, C and D (BLERA,
BLERB, BLERC, and BLERD) are unused and will read
0. This mode is backward compatible with earlier
firmware revisions.
An image-reject mixer downconverts the RF signal to
low-IF. The quadrature mixer output is amplified,
filtered,
and
digitized
with
high
resolution
analog-to-digital converters (ADCs). This advanced
architecture achieves superior performance by using
digital signal processing (DSP) to perform channel
selection, FM demodulation, and stereo audio
Setting the RDS mode bit high places the device in RDS
verbose mode. The device sets RDSS high when
synchronized and low when synchronization is lost. If
the device is synchronized, RDS ready (RDSR) will be
set for a minimum of 40 ms when a RDS group has
been received. Setting the RDS interrupt enable
(RDSIEN) bit and GPO[1:0] = 01 will configure GPO to
pulse low for a minimum of 5 ms if the device is
synchronized and an RDS group has been received.
BLERA, BLERB, BLERC and BLERD provide
block-error levels for the RDS group. The number of bit
errors in each block within the group is encoded as
follows: 00 = no errors, 01 = one to two errors, 10 =
three to five errors, 11 = six or more errors. Six or more
errors in a block indicate the block is uncorrectable and
should not be used.
processing
compared
to
traditional
analog
architectures.
4.3. General Purpose Output
The GPO pin can serve multiple functions. After
powerup of the device, the GPO pin can be used as a
general purpose input/output, and can be used as an
interrupt request pin for the seek/tune or RDS ready
functions. See register 04h, bits [3:2] in Section “6.
Register Descriptions” for information on GPO control. It
is recommended that the GPO pin not be used as an
interrupt request output until the powerup time has
completed (see Section “4.9. Reset, Powerup, and
Powerdown”). The GPO pin is powered from the V
IO
supply; therefore, general purpose input/output
functionality is available regardless of the state of the V
A
and V supplies, or the ENABLE and DISABLE bits.
D
14
Rev. 1.2
Si4708/09-C
High-fidelity stereo digital-to-analog converters (DACs)
drive analog audio signals onto the LOUT and ROUT
pins. The audio output may be muted with the DMUTE
bit. Volume can be adjusted digitally with the
VOLUME[3:0] bits. The volume dynamic range can be
set to either –28 dBFS (default) or –58 dBFS by setting
VOLEXT=1.
4.5. Stereo Audio Processing
The output of the FM demodulator is a stereo
multiplexed (MPX) signal. The MPX standard was
developed in 1961 and is used worldwide. Today's MPX
signal format consists of left + right (L+R) audio, left –
right (L–R) audio, a 19 kHz pilot tone, and RDS/RBDS
data as shown in Figure 7.
The soft mute feature is available to attenuate the audio
outputs and minimize audible noise in very weak signal
conditions. The soft mute attack and decay rate can be
adjusted with the SMUTER[1:0] bits where 00 is the
fastest setting. The soft mute attenuation level can be
adjusted with the SMUTEA[1:0] bits where 00 is the
most attenuated. The soft mute disable (DSMUTE) bit
may be set high to disable this feature.
Mono Audio
Left + Right
Stereo
Pilot
Stereo Audio
RDS/
Left - Right
RBDS
4.6. Tuning
0
15 19 23
38
53 57
The Si4708/09 uses Silicon Laboratories’ patented and
proven frequency synthesizer technology including a
completely integrated VCO. The frequency synthesizer
generates the quadrature local oscillator signal used to
downconvert the RF input to a low intermediate
frequency. The VCO frequency is locked to the
reference clock and adjusted with an automatic
frequency control (AFC) servo loop during reception.
Frequency (kHz)
Figure 7. MPX Signal Spectrum
The
Si4708/09's
integrated
stereo
decoder
automatically decodes the MPX signal. The 0 to 15 kHz
(L+R) signal is the mono output of the FM tuner. Stereo
is generated from the (L+R), (L-R), and a 19 kHz pilot
tone. The pilot tone is used as a reference to recover
the (L-R) signal. Separate left and right channels are
obtained by adding and subtracting the (L+R) and (L-R)
signals, respectively. The Si4709 uses frequency
information from the 19 kHz stereo pilot to recover the
57 kHz RDS/RBDS signal.
The tuning frequency is defined as:
Freq (MHz) = Spacing (kHz) Channel + Bottom of Band (MHz)
Channel spacing of 50, 100 or 200 KHz is selected with
bits SPACE[1:0]. The channel is selected with bits
CHAN[9:0]. The bottom of the band is set to 76 MHz or
87.5 MHz with the bits BAND[1:0]. The tuning operation
begins by setting the TUNE bit. After tuning completes,
the seek/tune complete (STC) bit will be set and the
RSSI level is available by reading bits RSSI[7:0]. The
TUNE bit must be set low after the STC bit is set high in
order to complete the tune operation and clear the STC
bit.
Adaptive noise suppression is employed to gradually
combine the stereo left and right audio channels to a
mono (L+R) audio signal as the signal quality degrades
to maintain optimum sound fidelity under varying
reception conditions. The signal level range over which
the stereo to mono blending occurs can be adjusted by
setting the BLNDADJ[1:0] register. Stereo/mono status
can be monitored with the ST register bit and mono
operation can be forced with the MONO register bit.
Seek tuning searches up or down for a channel with an
RSSI greater than or equal to the seek threshold set
with the SEEKTH[7:0] bits. In addition, an optional SNR
and/or impulse noise detector may be used to qualify
valid stations. The SKSNR[3:0] bits set the SNR
threshold required. The SKCNT[3:0] bits set the impulse
noise threshold. Using the extra seek qualifiers can
reduce false stops and, in combination with lowering the
RSSI seek threshold, increase the number of found
stations. The SNR and impulse noise detectors are
disabled by default.
Pre-emphasis and de-emphasis is a technique used by
FM broadcasters to improve the signal-to-noise ratio of
FM receivers by reducing the effects of high frequency
interference and noise. When the FM signal is
transmitted,
a
pre-emphasis filter is applied to
accentuate the high audio frequencies. All FM receivers
incorporate a de-emphasis filter which attenuates high
frequencies to restore a flat frequency response. Two
time constants, 50 or 75 µs, are used in various regions.
The de-emphasis time constant is programmable with
the DE bit.
Two seek modes are available. When the seek mode
(SKMODE) bit is low and a seek is initiated, the device
seeks through the band, wraps from one band edge to
the other, and continues seeking. If the seek operation
Rev. 1.2
15
Si4708/09-C
was unable to find a channel, the seek failure/band limit
(SF/BL) bit will be set high and the device will return to
the channel selected before the seek operation began.
When the SKMODE bit is high and a seek is initiated,
the device seeks through the band until the band limit is
reached and the SF/BL bit will be set high. A seek
operation is initiated by setting the SEEK and SEEKUP
bits. After the seek operation completes, the STC bit will
be set, and the RSSI level and tuned channel are
available by reading bits RSSI[7:0] and bits
4.8. Control Interface
Two-wire slave-transceiver and three-wire interfaces
are provided for the controller IC to read and write the
control registers. Refer to “4.9. Reset, Powerup, and
Powerdown” for a description of bus mode selection.
Registers may be written and read when the V supply
is applied regardless of the state of the V or V
IO
D
A
supplies. RCLK is not required for proper register
operation.
4.8.1. 3-Wire Control Interface
READCHAN[9:0].
During
a
seek
operation
READCHAN[9:0] is also updated and may be read to For three-wire operation, a transfer begins when the
determine seek progress. The STC bit will be set after SEN pin is sampled low by the device on a rising SCLK
the seek operation completes. The channel is valid if the edge. The control word is latched internally on rising
seek operation completes and the SF/BL bit is set low. SCLK edges and is nine bits in length, comprised of a
At other times, such as before a seek operation or after four bit chip address A7:A4 = 0110b, a read/write bit
a seek completes and the SF/BL bit is set high, the (write = 0 and read = 1), and a four bit register address,
channel is valid if the AFC Rail (AFCRL) bit is set low A3:A0. The ordering of the control word is A7:A5, R/W,
and the value of RSSI[7:0] is greater than or equal to A4:A0. Refer to Section 5. "Register Summary" on page
SEEKTH[7:0]. Note that if the AFCRL bit is set, the 19 for a list of all registers and their addresses.
audio output is muted as in the softmute case discussed
For write operations, the serial control word is followed
in Section “4.5. Stereo Audio Processing”. The SEEK bit
by a 16-bit data word and is latched internally on rising
must be set low after the STC bit is set high in order to
SCLK edges.
complete the seek operation and clear the STC and
For read operations, a bus turn-around of half a cycle is
SF/BL bits. The seek operation may be aborted by
followed by a 16-bit data word shifted out on rising
setting the SEEK bit low at any time.
SCLK edges and is clocked into the system controller
The device can be configured to generate an interrupt
on falling SCLK edges. The transfer ends on the rising
on GPO when a tune or seek operation completes.
SCLK edge after SEN is set high. Note that 26 SCLK
Setting the seek/tune complete (STCIEN) bit and
cycles are required for a transfer, however, SCLK may
GPO[1:0] = 01 will configure GPO for a 5 ms low
run continuously.
interrupt when the STC bit is set by the device.
For details on timing specifications and diagrams, refer
For additional recommendations on optimizing the seek
to Table 5, “3-Wire Control Interface Characteristics,” on
function, consult "AN349: Si4708/09 Programming
Guide."
page 7, Figure 2, “3-Wire Control Interface Write Timing
Parameters,” on page 7, and Figure 3, “3-Wire Control
Interface Read Timing Parameters,” on page 7.
4.7. Reference Clock
The Si4708/09-C accepts a 32.768 kHz reference clock
to the RCLK pin. The reference clock is required
whenever the ENABLE bit is set high. Refer to Table 3,
“DC Characteristics,” on page 5 for input switching
voltage
levels
and
Table 7,
"FM
Receiver
Characteristics," on page 10 for frequency tolerance
information.
16
Rev. 1.2
Si4708/09-C
4.8.2. 2-Wire Control Interface
4.9. Reset, Powerup, and Powerdown
For two-wire operation, the SCLK and SDIO pins
function in open-drain mode (pull-down only) and must
be pulled up by an external device. A transfer begins
with the START condition (falling edge of SDIO while
SCLK is high). The control word is latched internally on
rising SCLK edges and is eight bits in length, comprised
of a seven bit device address equal to 0010000b and a
read/write bit (write = 0 and read = 1).
Driving the RST pin low will disable the Si4708/09 and
its control bus interface, and reset the registers to their
default settings. Driving the RST pin high will bring the
device out of reset. As the part is brought out of reset,
the SEN pin is used to select between 2-wire and 3-wire
control interface operation.
Table 8. Selecting 2-Wire or 3-Wire Control
Interface Busmode Operation
The device acknowledges the address by driving SDIO
low after the next falling SCLK edge, for 1 cycle. For
write operations, the device acknowledge is followed by
an eight bit data word latched internally on rising edges
of SCLK. The device acknowledges each byte of data
written by driving SDIO low after the next falling SCLK
edge, for 1 cycle. An internal address counter
automatically increments to allow continuous data byte
writes, starting with the upper byte of register 02h,
Bus Mode
3-wire
SEN
0
1
2-wire
Note: All parameters applied on rising edge of RST.
followed by the lower byte of register 02h, and onward The bus mode selection method requires the use of the
until the lower byte of the last register is reached. The SEN pin. To select 2-wire operation, the SEN pin must
internal address counter then automatically wraps be sampled high by the device on the rising edge of
around to the upper byte of register 00h and proceeds RST. To select 3-wire operation, the SEN pin must be
from there until continuous writes end. Data transfer sampled low by the device on the rising edge of RST.
ends with the STOP condition (rising edge of SDIO
while SCLK is high). After every STOP condition, the
ENABLE and DISABLE bits in register 02h can be used
internal address counter is reset.
When proper voltages are applied to the Si4708/09, the
to select between powerup and powerdown modes.
For read operations, the device acknowledge is When voltage is first applied to the device, ENABLE =
followed by an eight bit data word shifted out on falling DISABLE = 0. Setting ENABLE = 1 and DISABLE = 0
SCLK edges. An internal address counter automatically puts the device in powerup mode. To power down the
increments to allow continuous data byte reads, starting device, disable RDS (Si4709 only), set Reg4(5:4),
with the upper byte of register 0Ah, followed by the Reg4(3:2), and Reg4(1:0) to 0b10. then write 1 to the
lower byte of register 0Ah, and onward until the lower ENABLE and DISABLE bits. After being written to 1,
byte of the last register is reached. The internal address both bits will get cleared as part of the internal device
counter then automatically wraps around to the upper powerdown sequence. To put the device back into
byte of register 00h and proceeds from there until powerup mode, set ENABLE = 1 and DISABLE = 0 as
continuous reads cease. After each byte of data is read, described above. The ENABLE bit should never be
the controller IC must drive an acknowledge (SDIO = 0) written to a 0.
if an additional byte of data will be requested. Data
transfer ends with the STOP condition. After every
STOP condition, the internal address counter is reset.
For details on timing specifications and diagrams, refer
to
Table 6,
“2-Wire
Control
Interface
1,2,3
Characteristics
,” on page 8, Figure 4, “2-Wire
Control Interface Read and Write Timing Parameters,”
on page 9 and Figure 5, “2-Wire Control Interface Read
and Write Timing Diagram,” on page 9.
Rev. 1.2
17
Si4708/09-C
1. Note that V is still supplied in this scenario. If V is
4.10. Audio Output Summation
IO
IO
not supplied, refer to device initialization procedure
above.
The audio outputs LOUT and ROUT may be
capacitively summed with another device. Setting the
audio high-Z enable (AHIZEN) bit maintains a dc bias of
2. (Optional) Set the AHIZEN bit low to disable the dc
bias of 0.5 x V volts at the LOUT and ROUT pins,
IO
0.5 x V on the LOUT and ROUT pins to prevent the
IO
but preserve the states of the other bits in Register
07h. Note that in powerup the LOUT and ROUT pins
are set to the common mode voltage specified in
Table 7 on page 10, regardless of the state of
AHIZEN.
ESD diodes from clamping to the V or GND rail in
response to the output swing of the other device. The
IO
bias point is set with a 370 k resistor to V and GND.
IO
Register 07h containing the AHIZEN bit must not be
written during the powerup sequence and only takes
effect when in powerdown and V is supplied. In 3. Supply V and V .
IO
A
D
powerup the LOUT and ROUT pins are set to the
4. Provide RCLK. Steps 3 and 4 may be reversed when
using an external oscillator.
common mode voltage specified in Table 7, “FM
1,2
Receiver Characteristics ,” on page 10, regardless of
5. Set the ENABLE bit high and the DISABLE bit low to
powerup the device. Software should wait for the
powerup time (as specified by Table 7, “FM Receiver
the state of AHIZEN. Bits 13:0 of register 07h must be
preserved as 0x0100 while in powerdown and as
0x3C04 while in powerup.
1,2
Characteristics ,” on page 10) before continuing
with normal part operation.
4.11. Initialization Sequence
Refer to Figure 8, “Initialization Sequence,” on page 18.
To initialize the device:
VA,VD Supply
VIO Supply
RST Pin
1. Supply V and V .
A
D
2. Supply V while keeping the RST pin low. Note that
IO
steps 1 and 2 may be reversed. Power supplies may
be sequenced in any order.
3. Select 2-wire or 3-wire control interface bus mode
operation as described in Section 4.9. "Reset,
Powerup, and Powerdown" on page 17.
RCLK Pin
ENABLE Bit
4. Provide RCLK. Steps 3 and 4 may be reversed when
using an external oscillator.
1
2
3
4
5
5. Set the ENABLE bit high and the DISABLE bit low to
powerup the device. Software should wait for the
powerup time (as specified by Table 7, “FM Receiver
Figure 8. Initialization Sequence
4.12. Programming Guide
1,2
Characteristics ,” on page 10) before continuing
with normal part operation.
Refer to "AN349: Si4708/09 Programming Guide" for
control interface programming information.
To power down the device:
1. (Optional) Set the AHIZEN bit high to maintain a dc
bias of 0.5 x V volts at the LOUT and ROUT pins
IO
while in powerdown, but preserve the states of the
other bits in Register 07h. Note that in powerup the
LOUT and ROUT pins are set to the common mode
voltage specified in Table 7 on page 10, regardless
of the state of AHIZEN.
2. Set the ENABLE bit high and the DISABLE bit high
to place the device in powerdown mode. Note that all
register states are maintained so long as V is
IO
supplied and the RST pin is high.
3. (Optional) Remove RCLK.
4. Remove V and V supplies as needed.
A
D
To power up the device (after power down):
18
Rev. 1.2
Si4708/09-C
Rev. 1.2
19
Si4708/09-C
6. Register Descriptions
Register 00h. Device ID
Bit
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
PN[3:0]
R
MFGID[11:0]
R
Reset value = 0x1242
Bit
Name
Function
15:12
PN[3:0]
Part Number.
0x01 = Si4708/09
11:0
MFGID[11:0]
Manufacturer ID.
0x242
Register 01h. Chip ID
Bit
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
REV[5:0]
R
DEV[3:0]
R
FIRMWARE[5:0]
R
Si4708C Reset value = 0x1093 or 0x109E if ENABLE = 1
Si4708C Reset value = 0x1000 or 0x101E if ENABLE = 0
Si4709C Reset value = 0x1293 or 0x0129E if ENABLE = 1
Si4709C Reset value = 0x1200 or 0x121E if ENABLE = 0
Bit
Name
Function
15:10
REV[5:0]
Chip Version.
0x04 = Rev C
9:6
DEV[3:0]
Device.
0000 before powerup = Si4708.
1000 before powerup = Si4709.
0010 after powerup = Si4708.
1010 after powerup = Si4709.
5:0
FIRMWARE[5:0] Firmware Version.
0 before powerup.
Firmware version after powerup = 010011 or 011110.
20
Rev. 1.2
Si4708/09-C
Register 02h. Power Configuration
Bit
D15
D14 D13 D12 D11
D10
D9
D8 D7
D6
DISABLE
R/W
D5 D4 D3 D2 D1
D0
ENABLE
R/W
DSMUTE DMUTE MONO
0
RDSM SKMODE SEEKUP SEEK
0
0
0
0
0
0
Name
Type
R/W
R/W
R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W
Reset value = 0x0000
Bit
Name
Function
15
DSMUTE
Softmute Disable.
0 = Softmute enable (default).
1 = Softmute disable.
14
13
DMUTE
MONO
Mute Disable.
0 = Mute enable (default).
1 = Mute disable.
Mono Select.
0 = Stereo (default).
1 = Force mono.
12
11
Reserved
RDSM
Reserved.
Always write to 0.
RDS Mode (Si4709 only).
0 = Standard (default).
1 = Verbose.
Refer to “4.4. RDS/RBDS Processor and Functionality”.
10
9
SKMODE
SEEKUP
SEEK
Seek Mode.
0 = Wrap at the upper or lower band limit and continue seeking (default).
1 = Stop seeking at the upper or lower band limit.
Seek Direction.
0 = Seek down (default).
1 = Seek up.
8
Seek.
0 = Disable (default).
1 = Enable.
Notes:
1. Seek begins at the current channel, and goes in the direction specified with the SEEKUP
bit. Seek operation stops when a channel is qualified as valid according to the seek
parameters, the entire band has been searched (SKMODE = 0), or the upper or lower
band limit has been reached (SKMODE = 1).
2. The STC bit is set high when the seek operation completes and/or the SF/BL bit is set
high if the seek operation was unable to find a channel qualified as valid according to the
seek parameters. The STC and SF/BL bits must be set low by setting the SEEK bit low
before the next seek or tune may begin.
3. Seek performance for 50 kHz channel spacing varies according to RCLK tolerance.
Silicon Laboratories recommends ±50 ppm RCLK crystal tolerance for 50 kHz seek
performance.
4. A seek operation may be aborted by setting SEEK = 0.
7
Reserved
Always write to 0.
Rev. 1.2
21
Si4708/09-C
Bit
Name
Function
6
DISABLE
Powerup Disable.
Refer to “4.9. Reset, Powerup, and Powerdown”.
Default = 0.
5:1
0
Reserved
ENABLE
Always write to 0.
Powerup Enable.
Refer to “4.9. Reset, Powerup, and Powerdown”.
Default = 0.
Register 03h. Channel
Bit
D15
D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Name TUNE
0
0
0
0
0
CHANNEL[9:0]
R/W
Type R/W R/W R/W R/W R/W R/W
Reset value = 0x0000
Bit
Name
Function
15
TUNE
Tune.
0 = Disable (default).
1 = Enable.
The tune operation begins when the TUNE bit is set high. The STC bit is set high
when the tune operation completes. The STC bit must be set low by setting the TUNE
bit low before the next tune or seek may begin.
14:10
9:0
Reserved
Always write to 0.
CHAN[9:0]
Channel Select.
Channel value for tune operation.
If BAND 05h[7:6] = 00, then Freq (MHz) = Spacing (kHz) x Channel + 87.5 MHz.
If BAND 05h[7:6] = 01, BAND 05h[7:6] = 10, then
Freq (MHz) = Spacing (kHz) x Channel + 76 MHz.
CHAN[9:0] is not updated during a seek operation. READCHAN[9:0] provides the
current tuned channel and is updated during a seek operation and after a seek or
tune operation completes. Channel spacing is set with the bits SPACE 05h[5:4].
22
Rev. 1.2
Si4708/09-C
Register 04h. System Configuration 1
Bit
D15
D14
D13 D12 D11 D10 D9
D8
0
D7
D6
D5 D4 D3 D2 D1 D0
RDSIEN STCIEN
0
RDS
R/W
DE
AGCD
R/W
0
BLNDADJ[1:0]
R/W
0
0
GPO[1:0]
R/W
0
0
Name
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W R/W
R/W R/W
Reset value = 0x0000
Bit
Name
Function
15
RDSIEN
RDS Interrupt Enable (Si4709 only).
0 = Disable Interrupt (default).
1 = Enable Interrupt.
Setting RDSIEN = 1 and GPO[1:0] = 01 will generate a 5 ms low pulse on GPO when the
RDSR 0Ah[15] bit is set.
14
STCIEN
Seek/Tune Complete Interrupt Enable.
0 = Disable Interrupt (default).
1 = Enable Interrupt.
Setting STCIEN = 1 and GPO[1:0] = 01 will generate a 5 ms low pulse on GPO when the
STC 0Ah[14] bit is set.
13
12
Reserved
RDS
Always write to 0.
RDS Enable (Si4709 only).
0 = Disable (default).
1 = Enable.
11
10
DE
De-emphasis.
0 = 75 µs. Used in USA (default).
1 = 50 µs. Used in Europe, Australia, Japan.
AGCD
AGC Disable.
0 = AGC enable (default).
1 = AGC disable.
9:8
Reserved
Always write to 0.
7:6 BLNDADJ[1:0] Stereo/Mono Blend Level Adjustment.
Sets the RSSI range for stereo/mono blend.
00 = 31–49 RSSI dBµV (default).
01 = 37–55 RSSI dBµV (+6 dB).
10 = 19–37 RSSI dBµV (–12 dB).
11 = 25–43 RSSI dBµV (–6 dB).
ST bit set for RSSI values greater than low end of range.
5:4
Reserved
Always write to 10.
Rev. 1.2
23
Si4708/09-C
Bit
Name
Function
3:2
GPO[1:0]
General Purpose I/O.
00 = High impedance (default).
01 = STC/RDS interrupt. A logic high will be output unless an interrupt occurs as
described below.
10 = Low.
11 = High.
Setting STCIEN = 1 will generate a 5 ms low pulse on GPO when the STC 0Ah[14] bit is
set. Setting RDSIEN = 1 will generate a 5 ms low pulse on GPO when the RDSR 0Ah[15]
bit is set.
1:0
Reserved
Always write to 10.
24
Rev. 1.2
Si4708/09-C
Register 05h. System Configuration 2
Bit
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
SEEKTH[7:0]
R/W
BAND[1:0] SPACE[1:0]
VOLUME[3:0]
R/W
R/W
R/W
Reset value = 0x0000
Bit
Name
Function
15:8
SEEKTH[7:0]
RSSI Seek Threshold.
0x00 = min RSSI (default).
0x7F = max RSSI.
SEEKTH presents the logarithmic RSSI threshold for the seek operation. The
Si4708/09 will not validate channels with RSSI below the SEEKTH value. SEEKTH is
one of multiple parameters that can be used to validate channels. For more informa-
tion, see "AN349: Si4708/09 Programming Guide."
7:6
BAND[1:0]
Band Select.
00 = 87.5–108 MHz (US/Europe, Default).
01 = 76–108 MHz (Japan wide band).
10 = 76–90 MHz (Japan).
11 = Reserved.
5:4
3:0
SPACE[1:0]
Channel Spacing.
00 = 200 kHz (USA, Australia) (default).
01 = 100 kHz (Europe, Japan).
10 = 50 kHz.
VOLUME[3:0] Volume.
Relative value of volume is shifted –30 dBFS with the VOLEXT 06h[8] bit.
VOLEXT = 0 (default).
0000 = mute (default).
0001 = –28 dBFS.
:
:
1110 = –2 dBFS.
1111 = 0 dBFS.
VOLEXT = 1.
0000 = mute.
0001 = –58 dBFS.
:
:
1110 = –32 dBFS.
1111 = –30 dBFS.
FS = full scale.
Volume scale is logarithmic.
Rev. 1.2
25
Si4708/09-C
Register 06h. System Configuration 3
Bit
Name SMUTER[1:0] SMUTEA[1:0]
Type R/W R/W
Reset value = 0x0000
D15
D14
D13 D12
D11
D10
D9
D8
VOLEXT
R/W
D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
SKSNR[3:0]
R/W
SKCNT[3:0]
R/W
R/W R/W R/W
Bit
Name
Function
15:14
SMUTER[1:0] Softmute Attack/Recover Rate.
00 = fastest (default).
01 = fast.
10 = slow.
11 = slowest.
13:12
SMUTEA[1:0] Softmute Attenuation.
00 = 16 dB (default).
01 = 14 dB.
10 = 12 dB.
11 = 10 dB.
11:9
8
Reserved
VOLEXT
Always write to zero.
Extended Volume Range.
0 = disabled (default).
1 = enabled.
This bit attenuates the output by 30 dB. With the bit set to 0, the 15 volume settings
adjust the volume between 0 and –28 dBFS. With the bit set to 1, the 15 volume set-
tings adjust the volume between –30 and –58 dBFS.
Refer to 4.5. "Stereo Audio Processing" on page 15.
7:4
3:0
SKSNR[3:0]
SKCNT[3:0]
Seek SNR Threshold.
0000 = disabled (default).
0001 = min (most stops).
1111 = max (fewest stops).
Required channel SNR for a valid seek channel.
Seek FM Impulse Detection Threshold.
0000 = disabled (default).
0001 = max (most stops).
1111 = min (fewest stops).
Allowable number of FM impulses for a valid seek channel.
26
Rev. 1.2
Si4708/09-C
Register 07h. Test 1
Bit
Name Reserved AHIZEN
Type R/W R/W
Reset value = 0x0100
D15
D14
D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Reserved
R/W
Bit
15
14
Name
Function
Reserved
AHIZEN
Always write to zero.
Audio High-Z Enable.
0 = Disable (default).
1 = Enable.
Setting AHIZEN maintains a dc bias of 0.5 x V on the LOUT and ROUT pins to pre-
IO
vent the ESD diodes from clamping to the V or GND rail in response to the output
IO
swing of another device. Register 07h containing the AHIZEN bit must not be written
during the powerup sequence and high-Z only takes effect when in powerdown and
V
is supplied. Bits 13:0 of register 07h must be preserved as 0x0100 while in pow-
IO
erdown and as 0x3C04 while in powerup.
13:0
Reserved
If written, these bits should be read first and then written with their pre-existing values.
Do not write during powerup.
Register 08h. Test 2
Bit
D15 D14 D13 D12 D11 D10 D9
D8
Reserved
R/W
D7 D6 D5 D4 D3 D2 D1 D0
Name
Type
Reset value = 0x0000
Bit
Name
Function
15:0
Reserved
If written, these bits should be read first and then written with their pre-existing values.
Do not write during powerup.
Rev. 1.2
27
Si4708/09-C
Register 09h. Boot Configuration
Bit
D15 D14 D13 D12 D11 D10 D9
D8
Reserved
R/W
D7 D6 D5 D4 D3 D2 D1 D0
Name
Type
Reset value = 0x0000
Bit
Name
Function
15:0
Reserved
If written, these bits should be read first and then written with their pre-existing values.
Do not write during powerup.
Register 0Ah. Status RSSI
Bit
Name RDSR STC SF/BL AFCRL RDSS BLERA[1:0] ST
Type
Reset value = 0x0000
D15 D14 D13
D12
D11 D10 D9
D8
D7 D6 D5 D4 D3 D2 D1 D0
RSSI[7:0]
R
R
R
R
R
R
R
R
Bit
Name
Function
15
RDSR
RDS Ready (Si4709 only).
0 = No RDS group ready (default).
1 = New RDS group ready.
Refer to “4.4. RDS/RBDS Processor and Functionality”.
14
13
STC
Seek/Tune Complete.
0 = Not complete (default).
1 = Complete.
The seek/tune complete flag is set when the seek or tune operation completes. Setting
the SEEK 02h[8] or TUNE 03h[15] bit low will clear STC.
SF/BL
Seek Fail/Band Limit.
0 = Seek successful.
1 = Seek failure/Band limit reached.
The SF/BL flag is set high when SKMODE 02h[10] = 0 and the seek operation fails to
find a channel qualified as valid according to the seek parameters.
The SF/BL flag is set high when SKMODE 02h[10] = 1 and the upper or lower band limit
has been reached.
The SEEK 02h[8] bit must be set low to clear SF/BL.
12
AFCRL
AFC Rail.
0 = AFC not railed.
1 = AFC railed, indicating an invalid channel. Audio output is softmuted when set.
AFCRL is updated after a tune or seek operation completes and indicates a valid or
invalid channel. During normal operation, AFCRL is updated to reflect changing RF envi-
ronments.
28
Rev. 1.2
Si4708/09-C
Bit
Name
Function
11
RDSS
RDS Synchronized (Si4709 only).
0 = RDS decoder not synchronized (default).
1 = RDS decoder synchronized.
Available only in RDS Verbose mode (RDSM 02h[11] = 1).
Refer to “4.4. RDS/RBDS Processor and Functionality”.
10:9
BLERA[1:0] RDS Block A Errors (Si4709 only).
00 = 0 errors requiring correction.
01 = 1–2 errors requiring correction.
10 = 3–5 errors requiring correction.
11 = 6+ errors or error in checkword, correction not possible.
Available only in RDS Verbose mode (RDSM 02h[11] = 1).
Refer to “4.4. RDS/RBDS Processor and Functionality”.
8
ST
Stereo Indicator.
0 = Mono.
1 = Stereo.
7:0
RSSI[7:0]
RSSI (Received Signal Strength Indicator).
RSSI is measured units of dBµV in 1 dB increments with a maximum of approximately
75 dBµV. Si4708/09-C does not report RSSI levels greater than 75 dBuV.
Rev. 1.2
29
Si4708/09-C
Register 0Bh. Read Channel
Bit
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Name BLERB[1:0] BLERC[1:0] BLERD[1:0]
READCHAN[9:0]
R
Type
R
R
R
Reset value = 0x0000
Bit
Name
Function
15:14
BLERB[1:0]
RDS Block B Errors (Si4709 only).
00 = 0 errors requiring correction.
01 = 1–2 errors requiring correction.
10 = 3–5 errors requiring correction.
11 = 6+ errors or error in checkword, correction not possible.
Available only in RDS Verbose mode (RDSM = 1).
Refer to “4.4. RDS/RBDS Processor and Functionality”.
13:12
11:10
9:0
BLERC[1:0]
BLERD[1:0]
RDS Block C Errors (Si4709 only).
00 = 0 errors requiring correction.
01 = 1–2 errors requiring correction.
10 = 3–5 errors requiring correction.
11 = 6+ errors or error in checkword, correction not possible.
Available only in RDS Verbose mode (RDSM = 1).
Refer to “4.4. RDS/RBDS Processor and Functionality”.
RDS Block D Errors (Si4709 only).
00 = 0 errors requiring correction.
01 = 1–2 errors requiring correction.
10 = 3–5 errors requiring correction.
11 = 6+ errors or error in checkword, correction not possible.
Available only in RDS Verbose mode (RDSM = 1).
Refer to “4.4. RDS/RBDS Processor and Functionality”.
READCHAN[9:0] Read Channel.
If BAND 05h[7:6] = 00, then Freq (MHz) = Spacing (kHz) x Channel + 87.5 MHz.
If BAND 05h[7:6] = 01, BAND 05h[7:6] = 10, then
Freq (MHz) = Spacing (kHz) x Channel + 76 MHz.
READCHAN[9:0] provides the current tuned channel and is updated during a seek
operation and after a seek or tune operation completes. Spacing and channel are set
with the bits SPACE 05h[5:4] and CHAN 03h[9:0].
30
Rev. 1.2
Si4708/09-C
Register 0Ch. RDSA
Bit
D15 D14 D13 D12 D11 D10 D9
D8
D7 D6 D5 D4 D3 D2 D1 D0
Name
RDSA[15:0]
R
Type
Reset value = 0x0000
Bit
Name
Function
15:0
RDSA
RDS Block A Data (Si4709 only).
Register 0Dh. RDSB
Bit
D15 D14 D13 D12 D11 D10 D9
D8
D7 D6 D5 D4 D3 D2 D1 D0
Name
RDSB[15:0]
R
Type
Reset value = 0x0000
Bit
Name
Function
15:0
RDSB
RDS Block B Data (Si4709 only).
Rev. 1.2
31
Si4708/09-C
Register 0Eh. RDSC
Bit
D15 D14 D13 D12 D11 D10 D9
D8
D7 D6 D5 D4 D3 D2 D1 D0
Name
RDSC[15:0]
R
Type
Reset value = 0x0000
Bit
Name
Function
15:0
RDSC
RDS Block C Data (Si4709 only).
Register 0Fh. RDSD
Bit
D15 D14 D13 D12 D11 D10 D9
D8
D7 D6 D5 D4 D3 D2 D1 D0
Name
RDSD[15:0]
R
Type
Reset value = 0x0000
Bit
Name
Function
15:0
RDSD
RDS Block D Data (Si4709 only).
32
Rev. 1.2
Si4708/09-C
7. Pin Descriptions: Si4708/09-GM
1
2
16
15
14
13
LOUT
FMI
12 ROUT
GND
PAD
RFGND
3
11 GND
4
5
10 VD
9
RST
SEN
6
7
8
Top View
Pin Number(s)
Name
NC
Description
1, 16
No Connect. Leave floating.
FM RF inputs.
2
FMI
3
RFGND
RST
RF ground. Connect to ground plane on PCB.
Device reset input (active low).
Serial enable input (active low).
Serial clock input.
4
5
SEN
6
SCLK
SDIO
7
8
Serial data input/output.
V
I/O supply voltage.
IO
9
RCLK
External reference oscillator input.
10
V
Digital supply voltage. May be connected directly to battery.
Ground. Connect to ground plane on PCB.
Right audio output.
D
11, PAD
12
GND
ROUT
LOUT
13
Left audio output.
14
V
Analog supply voltage. May be connected directly to battery.
General purpose input/output.
A
15
GPO
Rev. 1.2
33
Si4708/09-C
8. Ordering Guide
Part
Package
Type
Operating
Temperature
Description
Number*
Si4708-C-GM Portable Broadcast Radio Tuner
FM Stereo
QFN
Pb-free
–20 to 85 °C
–20 to 85 °C
Si4709-C-GM Portable Broadcast Radio Tuner
FM Stereo with RDS
QFN
Pb-free
*Note: Add an “(R)” at the end of the device part number to denote tape and reel option.
34
Rev. 1.2
Si4708/09-C
9. Package Markings (Top Marks)
9.1. Si4708 Top Mark
9.2. Si4709 Top Mark
9.3. Top Mark Explanation
Mark Method:
YAG Laser
Line 1 Marking:
Device Number
4708 = Si4708
4709 = Si4709
Line 2 Marking:
Line 3 Marking:
TTTT = Mfg Code
Line 2 from the "Markings" section of the Assem-
bly Purchase Order form.
Pin 1 Identifier.
Circle = 0.3 mm Diameter
YWW = Date Code
Assigned by the Assembly House. Corresponds
to the last digit of the current year (Y) and the
workweek (WW) of the assembly release.
Rev. 1.2
35
Si4708/09-C
10. Package Outline: Si4708/09-GM
Figure 9 illustrates the package details for the Si4708/09-GM. Table 9 lists the values for the dimensions shown in
the illustration.
Figure 9. 16-Pin Quad Flat No-Lead (QFN)
Table 9. Package Dimensions
Symbol
Millimeters
Nom
Symbol
Millimeters
Nom
Min
Max
Min
Max
A
A1
b
0.50
0.00
0.18
0.25
0.55
0.02
0.60
0.05
0.28
0.35
E2
f
1.35
1.40
1.45
2.00 BSC
0.23
L
0.25
—
0.30
—
0.35
0.05
0.05
0.08
0.10
0.10
c
0.30
aaa
bbb
ccc
ddd
eee
D
2.50 BSC
1.40
—
—
D2
e
1.35
1.45
—
—
0.50 BSC
2.50 BSC
—
—
E
—
—
Notes:
1. All dimensions are shown in millimeters unless otherwise noted.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
36
Rev. 1.2
Si4708/09-C
11. PCB Land Pattern: Si4708/09-GM
Figure 10 illustrates the PCB land pattern details for the Si4708/09-GM. Table 10 lists the values for the dimensions
shown in the illustration.
Figure 10. PCB Land Pattern
Table 10. PCB Land Pattern Dimensions
Symbol
Millimeters
Symbol
Millimeters
Min
Max
Min
Max
D
D2
e
2.60 REF
GE
W
1.95
—
—
1.35
1.45
0.30
0.30
0.50 BSC
2.60 REF
X
—
E
Y
0.65 REF
E2
f
1.35
1.95
1.45
—
ZE
ZD
—
—
3.25
3.25
2.00 BSC
GD
Notes: General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on IPC-SM-782 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based
on a Fabrication Allowance of 0.05 mm.
Notes: Solder Mask Design
1. All pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be
60 µm minimum, all the way around the pad.
Notes: Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder
paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
4. A 1.18x1.18 mm square aperture should be used for the center pad. This provides approximately 70%
solder paste coverage on the pad, which is optimum to assure correct component stand-off.
Notes: Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
Rev. 1.2
37
Si4708/09-C
12. Additional Reference Resources
AN230: Si4700/01/02/03 Programming Guide
AN235: Si4700/01/02/03/08/09 EVB Quick Start Guide
AN243: Using RDS/RBDS with the Si4701/03/09
AN316: AM/FM Tuner Field Test ProcedureSi4700/01/02/03
AN349: Si4708/09 Programming Guide
AN350: Si4708/09 Antenna, Schematic, Layout, and Design Guidelines
AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure
Si4708/09 EVB User’s Guide
Customer Support Site: http://www.silabs.com
This site contains all application notes, evaluation board schematics and layouts, and evaluation software. NDA
is required for access. To request access, register at http://www.mysilabs.com and send user’s first and last
name, company, NDA reference number, and mysilabs user name to fminfo@silabs.com. Silicon Labs
recommends an all lower case user name.
38
Rev. 1.2
Si4708/09-C
DOCUMENT CHANGE LIST
Revision 0.6 to Revision 1.0
Updated patent list on cover page
Updated Table 3 with full production values
Updated Table 4
Updated Table 7 to reflect specifications from 76–
108 MHz
Added Table 7 to reflect specifications from 64–
75.9 MHz
Revision 1.0 to Revision 1.1
FM frequency range 64-76.9 MHz no longer
supported
Chip ID register values changed
Typical VDD Supply Current values changed in
Table 3
Minimum V value changed in Table 2
IO
Revision 1.1 to Revision 1.2
Min V value changed in Table 1, Table 5, Table 6,
IO
and Table 7
Chip ID register value changed
Rev. 1.2
39
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