SI5018-BM [SILICON]
SiPHY⑩ OC-48/STM-16 CLOCK AND DATA RECOVERY IC WITH FEC; SiPHY⑩ OC- 48 / STM -16的时钟和具有FEC数据恢复IC
| 型号： | SI5018-BM |
| 厂家： | 
SILICON |
| 描述： | SiPHY⑩ OC-48/STM-16 CLOCK AND DATA RECOVERY IC WITH FEC |
| 文件： | 总22页 (文件大小：213K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si5018
SiPHY™ OC-48/STM-16 CLOCK AND DATA RECOVERY IC WITH FEC
Features
Complete high-speed, low-power, CDR solution includes the following:
! Supports OC-48 /STM-16 & FEC! Exceeds all SONET/SDH jitter
specifications
! Low power—270 mW
(typ OC-48)
! Jitter generation
3.0 mUI
(typ)
! Small footprint: 4x4 mm
rms
! Device powerdown
! Loss-of-lock indicator
! Single 2.5 V Supply
! DSPLL™ Eliminates external
Ordering Information:
loop filter components
! 3.3 V tolerant control inputs
See page 17.
Applications
Pin Assignments
Si5018
! SONET/SDH/ATM routers
! Add/drop multiplexers
! Optical transceiver modules
! SONET/SDH regenerators
! Board level serial links
! Digital cross connects
! SONET/SDH test equipment
description
20 19 18 17 16
REXT
VDD
1
2
3
4
5
15
14
13
12
11
The Si5018 is a fully-integrated low-power clock and data recovery (CDR)
IC designed for high-speed serial communication systems. It extracts
timing information and data from a serial input at OC-48/STM-16 data
rates. In addition, support for 2.7 Gbps data streams is also provided for
applications that employ forward error correction (FEC). DSPLL™
technology eliminates sensitive noise entry points thus making the PLL
less susceptible to board-level interaction and helping to ensure optimal
jitter performance.
PWRDN/CAL
VDD
GND
Pad
Connection
GND
DOUT+
DOUT–
VDD
REFCLK+
REFCLK–
6
7
8
9
10
The Si5018 represents a new standard in low jitter, low power, and small
size for high speed CDRs. It operates from a single 2.5 V supply over the
industrial temperature range (–40 to 85 °C).
Functional Block Diagram
LOL
DSPLLTM
Phase-Locked
Loop
DIN +
DIN –
DOUT +
DOUT –
BUF
BUF
BUF
Retim er
2
2
2
PW RDN/CAL
CLKOUT +
CLKOUT –
Bias
2
REXT
REFCLKIN +
REFCLKIN –
Rev. 1.2 1/04
Copyright © 2004 by Silicon Laboratories
Si5018-DS12
Si5018
2
Rev. 1.2
Si5018
TABLE OF CONTENTS
Section
Page
Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
DSPLL™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
PLL Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Reference Clock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Forward Error Correction (FEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Lock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Device Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Pin Descriptions: Si5018 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Package Outline: Si5018-BM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4x4 mm 20L MLP Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Rev. 1.2
3
Si5018
Detailed Block Diagram
DOUT+
DOUT–
Retime
c
DIN+
CLKOUT+
CLKOUT–
Phase
Detector
CLK
A/D
VCO
DSP
c
Divider
DIN–
n
REFCLK+
REFCLK–
Lock
Detector
LOL
REXT
Calibration
Bias
Generation
PWRDN/CAL
4
Rev. 1.2
Si5018
Electrical Specifications
Table 1. Recommended Operating Conditions
1
1
Parameter
Symbol
Test Condition
Typ
Unit
Min
Max
85
Ambient Temperature
Si5018 Supply Voltage
Notes:
T
–40
25
°C
V
A
2
V
2.375
2.5
2.625
DD
1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated.
2. The Si5018 specifications are guaranteed when using the recommended application circuit (including component
tolerance) shown in "Typical Application Schematic‚" on page 9.
V
SIGNAL+
V
,V
Differential
I/Os
V
ICM OCM
Single-Ended Voltage
IS
SIGNAL–
(SIGNAL+) – (SIGNAL–)
Differential Peak-to-Peak Voltage
t
V ,V (V = 2V )
ID OD
ID
IS
Differential
Voltage Swing
Figure 1. Differential Voltage Measurement (DIN, REFCLK, DOUT, CLKOUT)
tC-D
DOUT
CLKOUT
Figure 2. Differential Clock to Data Timing
80%
DOUT,
CLKOUT
20%
tF
tR
Figure 3. Differential DOUT and CLKOUT Rise/Fall Times
Rev. 1.2
5
Si5018
Table 2. DC Characteristics
(VDD = 2.5 V ±5%, TA = –40 to 85 °C)
Parameter
Symbol Test Condition
Min
—
Typ
108
Max
122
320
—
Unit
mA
mW
V
Supply Current
I
DD
Power Dissipation
P
—
270
D
Common Mode Input Voltage (DIN, REFCLK)*
Single Ended Input Voltage (DIN, REFCLK)*
Differential Input Voltage Swing (DIN, REFCLK)*
Input Impedance (DIN, REFCLK)
V
varies with V
—
.80 x V
ICM
DD
DD
V
See Figure 1
See Figure 1
Line-to-Line
200
200
84
—
750
1500
116
mV
mV
IS
ID
IN
PP
PP
V
—
R
100
Ω
Differential Output Voltage Swing (DOUT)
OC48
V
100 Ω Load
Line-to-Line
780
990
1260
mV
OD
PP
Differential Output Voltage Swing (CLKOUT)
OC48
V
100 Ω Load
Line-to-Line
550
—
900
1260
—
mV
PP
OD
Output Common Mode Voltage
(DOUT,CLKOUT)
V
100 Ω Load
Line-to-Line
V
–
DD
V
OCM
0.23
100
25
Output Impedance (DOUT,CLKOUT)
Output Short to GND (DOUT,CLKOUT)
R
Single-ended
84
—
116
31
—
Ω
mA
mA
V
OUT
SC(–)
SC(+)
I
I
Output Short to V (DOUT,CLKOUT)
–17.5
—
–14.5
—
DD
Input Voltage Low (LVTTL Inputs)
Input Voltage High (LVTTL Inputs)
Input Low Current (LVTTL Inputs)
Input High Current (LVTTL Inputs)
Output Voltage Low (LVTTL Outputs)
Output Voltage High (LVTTL Outputs)
Input Impedance (LVTTL Inputs)
PWRDN/CAL Leakage Current
V
.8
IL
V
I
2.0
—
—
—
V
IH
—
10
10
0.4
—
µA
µA
V
IL
I
—
—
IH
V
I = 2 mA
—
—
OL
O
V
I = 2 mA
2.4
10
—
V
OH
O
R
—
—
kΩ
µA
IN
PWRDN
I
V
≥ 0.8 V
15
25
35
PWRDN
*Note: The DIN and REFCLK inputs may be driven differentially or single-endedly. When driving single-endedly, the voltage swing
of the signal applied to the active input must exceed the specified minimum Differential Input Voltage Swing (VID min), and
the unused input must be ac coupled to ground. When driving differentially, the difference between the positive and
negative input signals must exceed VID min. (Each individual input signal needs to swing only half of this range.) In either
case, the voltage applied to any individual pin (DIN+, DIN–, REFCLK+, or REFCLK–) must not exceed the specified
maximum Input Voltage Range (VIS max).
6
Rev. 1.2
Si5018
Table 3. AC Characteristics (Clock and Data)
(VA 2.5 V ±5%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
2.4
—
Typ
—
Max
2.7
Unit
GHz
ps
Output Clock Rate
Output Rise/Fall Time
f
CLK
t t
Figure 3
Figure 2
80
110
R, F
Clock to Data Delay
FEC (2.7 GHz)
OC-48
t
C-D
225
225
250
250
270
270
ps
Input Return Loss
100 kHz–2.5 GHz
2.5 GHz–4.0 GHz
—
—
16
13
—
—
dB
dB
Table 4. AC Characteristics (PLL Characteristics)
(VA 2.5 V ±5%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
f = 600 Hz
Min
40
4
Typ
—
Max
—
Unit
Jitter Tolerance*
J
UI
UI
UI
UI
TOL(P–P)
PP
PP
PP
PP
f = 6000 Hz
—
—
f = 100 kHz
4
—
—
f = 1 MHz
.4
—
—
*
RMS Jitter Generation
J
with no jitter on serial data
with no jitter on serial data
—
—
—
—
1.45
2.9
25
5.0
55
mUI
mUI
MHz
dB
GEN(rms)
*
Peak-to-Peak Jitter Generation
J
GEN(PP)
*
Jitter Transfer Bandwidth
J
—
2.0
0.1
1.7
BW
*
Jitter Transfer Peaking
J
0.03
1.5
P
Acquisition Time
T
After falling edge of
PWRDN/CAL
ms
AQ
From the return of valid data
40
40
60
50
150
60
µs
Input Reference Clock Duty
Cycle
C
%
DUTY
Input Reference Clock Frequency
Tolerance
C
–100
—
100
ppm
TOL
Reference Clock Range
19.44
450
—
168.75
750
MHz
ppm
Frequency Difference at which
Receive PLL goes out of Lock
(REFCLK compared to the
divided down VCO clock)
LOL
600
Frequency Difference at which
Receive PLL goes into Lock
(REFCLK compared to the
divided down VCO clock)
LOCK
150
300
450
ppm
*Note: Bellcore specifications: GR-253-CORE, Issue 2, December 1995. Using PRBS 223 – 1 data pattern.
Rev. 1.2
7
Si5018
Table 5. Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
V
DC Supply Voltage
V
–0.5 to 2.8
–0.3 to 3.6
DD
LVTTL Input Voltage
V
V
DIG
Differential Input Voltages
Maximum Current any output PIN
Operating Junction Temperature
Storage Temperature Range
ESD HBM Tolerance (100 pf, 1.5 kΩ)
V
–0.3 to (V + 0.3)
V
DIF
DD
±50
–55 to 150
–55 to 150
1
mA
°C
°C
kV
T
JCT
T
STG
Note: Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Table 6. Thermal Characteristics
Parameter
Symbol
Test Condition
Value
Unit
Thermal Resistance Junction to Ambient
ϕ
Still Air
38
°C/W
JA
8
Rev. 1.2
Si5018
Typical Application Schematic
Powerdown
Loss-of-Lock
Indicator
DIN+
DIN–
DOUT+
High-Speed
Serial Input
Recovered
Data
DOUT–
Si5018
System
Reference
Clock
REFCLK+
REFCLK–
CLKOUT+
CLKOUT–
Recovered
Clock
0.1 µF
10 kΩ
VDD
(1%)
2200 pF
20 pF
Rev. 1.2
9
Si5018
no activity exists on REFCLK, indicating the lock status
of the PLL is unknown. Additionally, the Si5018 uses the
Functional Description
The Si5018 utilizes a phase-locked loop (PLL) to reference clock to center the VCO output frequency at
recover a clock synchronous to the input data stream. the OC-48/STM-16 data rate. The device will self-
This clock is used to retime the data, and both the configure for operation with one of three reference clock
recovered clock and data are output synchronously via frequencies. This eliminates the need to externally
current mode logic (CML) drivers. Optimal jitter configure the device to operate with a particular
performance is obtained by using Silicon Laboratories' reference clock.
DSPLL™ technology to eliminate the noise entry points
caused by external PLL loop filter components.
The reference clock centers the VCO for a nominal
output between 2.488 GHz and 2.7 GHz. The VCO
frequency is centered at 16, 32, or 128 times the
reference clock frequency. Detection circuitry
DSPLL™
The phase-locked loop structure (shown in "Typical
Application Schematic‚" on page 9) utilizes Silicon
Laboratories' DSPLL™ technology to eliminate the
need for external loop filter components found in
traditional PLL implementations. This is achieved by
using a digital signal processing (DSP) algorithm to
replace the loop filter commonly found in analog PLL
designs. This algorithm processes the phase detector
error term and generates a digital control value to adjust
the frequency of the voltage-controlled oscillator (VCO).
Because external loop filter components are not
required, sensitive noise entry points are eliminated
thus making the DSPLL less susceptible to board-level
noise sources that make SONET/SDH jitter compliance
difficult to attain.
continuously monitors the reference clock input to
determine whether the device should be configured for
a reference clock that is 1/16, 1/32, or 1/128 the
nominal VCO output. Approximate reference clock
frequencies are given in Table 7.
Table 7. Typical REFCLK Frequencies
OC-48/
STM-16
OC-48/STM-16 w/
15/14 FEC
Ratio of
VCO to
(2.488 GHz)
(2.666 GHz)
REFCLK
19.44 MHz
77.76 MHz
155.52 MHz
20.83 MHz
83.31 MHz
166.63 MHz
128
32
16
PLL Self-Calibration
Forward Error Correction (FEC)
The Si5018 achieves optimal jitter performance by
using self-calibration circuitry to set the loop gain
parameters within the DSPLL. For the self-calibration
circuitry to operate correctly, the power supply voltage
must exceed 2.25 V when calibration occurs. For best
performance, the user should force a self-calibration
once the supply has stabilized on powerup.
The Si5018 supports FEC in SONET OC-48 (SDH
STM-16) applications for data rates up to 2.7 Gbps. In
FEC applications, the appropriate reference clock
frequency is determined by dividing the input data rate
by 16, 32, or 128. For example, if an FEC code is used
that produces a 2.7 Gbps data rate, the required
reference clock would be 168.75 MHz, 84.375 MHz, or
21.09 MHz.
A self-calibration can be initiated by forcing a high-to-
low transition on the power-down control input,
PWRDN/CAL, while a valid reference clock is supplied
to the REFCLK input. The PWRDN/CAL input should be
held high at least 1 µs before transitioning low to
guarantee a self-calibration. Several application circuits
that could be used to initiate a power-on self-calibration
are provided in Silicon Laboratories’ “AN42: Controlling
DSPLL™ Self-Calibration for the Si5020/5018/5010
CDR Devices and Si531x Clock Multiplier/Regenerator
Devices.”
Lock Detect
The Si5018 provides lock-detect circuitry that indicates
whether the PLL has achieved frequency lock with the
incoming data. The circuit compares the frequency of a
divided-down version of the recovered clock with the
frequency of the applied reference clock (REFCLK). If
the recovered clock frequency deviates from that of the
reference clock by the amount specified in Table 4 on
page 7, the PLL is declared out of lock, and the loss-of-
lock (LOL) pin is asserted high. In this state, the PLL will
periodically try to reacquire lock with the incoming data
stream. During reacquisition, the recovered clock may
drift over a ±600 ppm range relative to the applied
reference clock, and the LOL output alarm may toggle
until the PLL has reacquired frequency lock. Due to the
Reference Clock Detect
The Si5018 CDR requires an external reference clock
applied to the REFCLK input for normal device
operation. When REFCLK is absent, the LOL alarm will
always be asserted when it has been determined that
10
Rev. 1.2
Si5018
low noise and stability of the DSPLL, under the
condition where data is removed from the inputs, there
is the possibility that the PLL will not drift enough to
render an out-of-lock condition.
Sinusoidal
Input
Jitter (UIPP
)
20 dB/Decade Slope
If REFCLK is removed, the LOL output alarm is always
asserted when it has been determined that no activity
exists on REFCLK, indicating the frequency lock status
of the PLL is unknown.
15
1.5
0.15
Note: LOL is not asserted during PWRDN/CAL.
PLL Performance
f0
f1
f2
f3
ft
Frequency
The PLL implementation used in the Si5018 is fully
compliant with the jitter specifications proposed for
SONET/SDH equipment by Bellcore GR-253-CORE,
Issue 2, December 1995 and ITU-T G.958.
F0
(Hz)
F1
F2
F3
Ft
SONET
Data Rate
(Hz)
(Hz)
(kHz) (kHz)
Jitter Tolerance
OC- 48
10
600
6000
100 1000
The Si5018’s tolerance to input jitter exceeds that of the
Bellcore/ITU mask shown in Figure 4. This mask
defines the level of peak-to-peak sinusoid jitter that
must be tolerated when applied to the differential data
input of the device.
Figure 4. Jitter Tolerance Specification
Jitter
Jitter Transfer
Transfer
The Si5018 is fully compliant with the relevant Bellcore/
ITU specifications related to SONET/SDH jitter transfer.
Jitter transfer is defined as the ratio of output signal jitter
to input signal jitter as a function of jitter frequency (see
Figure 5). These measurements are made with an input
test signal that is degraded with sinusoidal jitter whose
magnitude is defined by the mask in Figure 4.
20 dB / Decade
Slope
0.1 dB
Acceptable
Range
Jitter Generation
Fc
The Si5018 exceeds all relevant specifications for jitter
generation proposed for SONET/SDH equipment. The
jitter generation specification defines the amount of jitter
that may be present on the recovered clock and data
outputs when a jitter free input signal is provided. The
Frequency
SONET
Fc
Data Rate
OC- 48
(kHz)
Si5018 generates less than 3.0 mUI
presented with jitter free input data.
of jitter when
2000
rms
Figure 5. Jitter Transfer Specification
Powerdown
The Si5018 provides a powerdown pin, PWRDN/CAL,
that disables the output drivers (DOUT, CLKOUT).
When the PWRDN/CAL pin is driven high, the positive
and negative terminals of CLKOUT and DOUT are each
tied to VDD through 100 Ω on-chip resistors. This
feature is useful in reducing power consumption in
applications that employ redundant serial channels.
When PWRDN/CAL is released (set to low) the digital
logic resets to a known initial condition, recalibrates the
DSPLL, and will begin to lock to the data stream.
Rev. 1.2
11
Si5018
Device Grounding
Differential Input Circuitry
The Si5018 uses the GND pad on the bottom of the 20- The Si5018 provides differential inputs for both the high
pin micro leaded package (MLP) for device ground. This speed data (DIN) and the reference clock (REFCLK)
pad should be connected directly to the analog supply inputs. An example termination for these inputs is
ground. See Figures 10 and 11 for the ground (GND) shown in Figure 6. In applications where direct dc
pad location.
coupling is possible, the 0.1 µF capacitors may be
omitted. The DIN and REFCLK input amplifiers require
an input signal with a minimum differential peak-to-peak
Bias Generation Circuitry
The Si5018 makes use of an external resistor to set voltage listed in Table 2 on page 6.
internal bias currents. The external resistor allows
precise generation of bias currents which significantly
reduces power consumption versus traditional
implementations that use an internal resistor. The bias
generation circuitry requires a 10 kΩ (1%) resistor
connected between REXT and GND.
Si5018
Differential Driver
VDD
2.5 kΩ
DIN +,
RFCLK +
0.1 µ F
0.1 µ F
Zo = 50 Ω
10 kΩ
2.5 kΩ
102Ω
DIN –,
RFCLK –
Zo = 50 Ω
10 kΩ
GND
Figure 6. Input Termination for DIN and REFCLK (AC Coupled)
Si5018
Clock
VDD
source
2.5 kΩ
0.1
µ
F
Zo = 50
Ω
REFCLK +
REFCLK –
10 kΩ
2.5 kΩ
102
Ω
100
Ω
10 kΩ
0.1 µF
GND
Figure 7. Single-Ended Input Termination for REFCLK (AC Coupled)
12
Rev. 1.2
Si5018
Si5018
VDD
Clock
source
2.5 kΩ
0.1
µ
F
Zo = 50
Ω
DIN +
DIN –
10 kΩ
2.5 kΩ
102
Ω
100
Ω
10 kΩ
0.1 µF
GND
Figure 8. Single-Ended Input Termination for DIN (AC Coupled)
Rev. 1.2
13
Si5018
Differential Output Circuitry
The Si5018 utilizes a current mode logic (CML) architecture to output both the recovered clock (CLKOUT) and data
(DOUT). An example of output termination with ac coupling is shown in Figure 9. In applications in which direct dc
coupling is possible, the 0.1 µF capacitors may be omitted. The differential peak-to-peak voltage swing of the CML
architecture is listed in Table 2 on page 6.
Si5018
VDD
VDD
50 Ω
100 Ω
DOUT +,
CLKOUT +
0.1 µ F
0.1 µ F
Zo = 50 Ω
DOUT –,
CLKOUT –
Zo = 50 Ω
100 Ω
VDD
50 Ω
VDD
Figure 9. Output Termination for DOUT and CLKOUT (AC Coupled)
14
Rev. 1.2
Si5018
Pin Descriptions: Si5018
20 19 18 17 16
REXT
VDD
1
2
3
4
5
15
14
13
12
11
PWRDN/CAL
VDD
GND
Pad
Connection
GND
DOUT+
DOUT–
VDD
REFCLK+
REFCLK–
6
7
8
9
10
Figure 10. Si5018 Pin Configuration
Table 8. Si5018 Pin Descriptions
Pin #
Pin Name
I/O
Signal Level
Description
External Bias Resistor.
1
REXT
This resistor is used by onboard circuitry to estab-
lish bias currents within the device. This pin must
be connected to GND through a 10 kΩ (1%) resis-
tor.
Differential Reference Clock.
4
5
REFCLK+
REFCLK–
I
See Table 2
LVTTL
The reference clock sets the initial operating fre-
quency used by the onboard PLL for clock and data
recovery. Additionally, the reference clock is used to
derive the clock output when no data is present.
Loss-of-Lock.
6
LOL
O
This output is driven high when the recovered clock
frequency deviates from the reference clock by the
amount specified in Table 4 on page 7.
Differential Data Input.
9
10
DIN+
DIN–
I
See Table 2
CML
Clock and data are recovered from the differential
signal present on these pins.
Differential Data Output.
12
13
DOUT–
DOUT+
O
The data output signal is a retimed version of the
data recovered from the signal present on DIN. It is
phase aligned with CLKOUT and is updated on the
rising edge of CLKOUT.
Rev. 1.2
15
Si5018
Table 8. Si5018 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
15
PWRDN/CAL
I
LVTTL
Powerdown.
To shut down the high-speed outputs and reduce
power consumption, hold this pin high. For normal
operation, hold this pin low.
Calibration.
To initiate an internal self-calibration, force a high-
to-low transition on this pin. (See "PLL Self-Calibra-
tion‚" on page 10.)
Note: This input has a weak internal pulldown.
Differential Clock Output.
16
17
CLKOUT–
CLKOUT+
O
CML
The output clock is recovered from the data signal
present on DIN. In the absence of data, the output
clock is derived from REFCLK.
Supply Voltage.
2, 7, 11, 14
VDD
GND
2.5 V
GND
Nominally 2.5 V.
Supply Ground.
3, 8, 18, 19,
20, and
GND Pad
Nominally 0.0 V. The GND pad found on the bottom
of the 20-pin micro leaded package (see Figure 11)
must be connected directly to supply ground.
16
Rev. 1.2
Si5018
Ordering Guide
Part Number
Package
Temperature
Si5018-BM
20-pin MLP
–40 to 85 °C
Top Mark
Silicon Labs
Die Revision (R)
Part Designator (Z)
Part Number
Si5018-BM
B
C
Rev. 1.2
17
Si5018
Package Outline: Si5018-BM
Figure 11 illustrates the package details for the Si5018-BM. Table 9 lists the values for the dimensions shown in the
illustration.
A
D
D1
A1
D2
A2
L
b
PIN1 ID
0.50 DIA.
A3
b
20
20
1
2
3
1
2
3
E1
E
E2
θ
e
e
Top View
Side View
Bottom View
Figure 11. 20-pin Micro Leadframe Package (MLP)
Table 9. Package Dimensions
Symbol
Millimeters
Symbol
Millimeters
Min
—
Nom
0.85
Max
0.90
0.05
0.70
Min
Nom
3.75 BSC
2.10
Max
A
A1
D1, E1
0.00
—
0.01
D2, E2
1.95
2.25
A2
0.65
e
θ
L
0.50 BSC
—
A3
0.20 REF.
0.23
—
12°
b
0.18
0.30
0.50
0.60
0.75
D, E
4.00 BSC
Notes:
1. Dimensioning and tolerances conform to ASME Y14.5M. - 1994
2. Package warpage MAX 0.05 mm.
3. “b” applies to plated terminal and is measured between 0.20 and 0.25 mm from terminal TIP.
4. The package weight is approximately 42 mg.
5. The mold compound for this package has a flammability rating of UL94-V0 with an oxygen index of 28
minimum/54 typical.
6. The recommended reflow profile for this package is defined by the JEDEC-020B Small Body specification.
18
Rev. 1.2
Si5018
4x4 mm 20L MLP Recommended PCB Layout
See Note 8
See Note 9
Gnd Pin
Symbol
Parameter
Dimensions
Nom
Min
2.23
2.03
—
Max
2.28
2.13
—
A
D
e
Pad Row/Column Width/Length
Thermal Pad Width/Height
Pad Pitch
2.25
2.08
0.50 BSC
2.46
G
R
X
Y
Z
Pad Row/Column Separation
Pad Radius
2.43
—
2.48
—
0.12 REF
0.25
Pad Width
0.23
—
0.28
—
Pad Length
0.94 REF
4.28
Pad Row/Column Extents
4.26
4.31
Notes:
1. All dimensions listed are in millimeters (mm).
2. The perimeter pads are to be Non-Solder Mask Defined (NSMD). Solder mask openings should be designed to leave 60-75 mm
separation between solder mask and pad metal, all the way around the pad.
3. The center thermal pad is to be Solder Mask Defined (SMD).
4. Thermal/Ground vias placed in the center pad should be no less than 0.2 mm (8 mil) diameter and tented from the top to prevent
solder from flowing into the via hole.
5. The stencil aperture should match the pad size (1:1 ratio) for the perimeter pads. A 3x3 array of 0.5 mm square stencil openings, on a
0.65 mm pitch, should be used for the center thermal pad.
6. A stencil thickness of 5 mil is recommended. The stencil should be laser cut and electropolished, with trapezoidal walls to facilitate
paste release.
7. A “No-Clean”, Type 3 solder paste should be used for assembly. Nitrogen purge during reflow is recommended.
8. Do not place any signal or power plane vias in these “keep out” regions.
9. Suggest four 0.38 mm (15 mil) vias to the ground plane.
Rev. 1.2
19
Si5018
Document Change List
Revision 1.0 to Revision 1.1
! Added "Top Mark‚" on page 17.
! Updated "Package Outline: Si5018-BM‚" on page 18.
! Added "4x4 mm 20L MLP Recommended PCB
Layout‚" on page 19.
Revision 1.1 to Revision 1.2
! Made minor note corrections to "4x4 mm 20L MLP
Recommended PCB Layout‚" on page 19.
20
Rev. 1.2
Si5018
Notes:
Rev. 1.2
21
Si5018
Contact Information
Silicon Laboratories Inc.
4635 Boston Lane
Austin, TX 78735
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Email: productinfo@silabs.com
Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-
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plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Silicon Laboratories, Silicon Labs, DSPLL, and SiPHY are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
22
Rev. 1.2
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