SI51218-A09469-GM [SILICON]
PLL Based Clock Driver,;
| 型号： | SI51218-A09469-GM |
| 厂家： | 
SILICON |
| 描述： | PLL Based Clock Driver, |
| 文件： | 总15页 (文件大小：470K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si51218 Data Sheet
Three Output Factory Programmable Clock Generator
KEY FEATURES
The factory programmable Si51218 is a low power, small footprint and frequency flexible
programmable clock generator targeting low power, low cost and high volume consumer
and embedded applications. The device operates from a single crystal or an external
clock source and generates up to 3 outputs from 32.768 kHz to 170 MHz. The device is
factory programmed to provide customized output frequencies and control input such as
power down and output enable.
• Generates up to 3 LVCMOS clock outputs
from 32.768 kHz to 170 MHz
• Accepts crystal or reference clock input
• 3 to 165 MHz reference clock input
• 8 to 48 MHz crystal input
• Programmable OE input function
Applications
• Portable devices
• DTV/IPTV
• Crystal/XO replacement
• Digital media players
4
CLKOUT1/REFOUT1
(VDD)/OE
PLL with
Modulation
Control
XIN/
3
CLKIN
Buffers,
Dividers,
and
Switch
Matrix
2
8
1
XOUT
VDDO
VDD
CLKOUT2/REFOUT2
(VDDO)/
OE
6
7
Programmable
Configuration
Register
To Pin 6/7
V-REG
To Core
To Pin 4
CLKOUT3 (VDDO)
5
VSS
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Rev. 1.1
Si51218 Data Sheet
Feature List
1. Feature List
The Si51218 highlighted features are listed below.
• Generates up to 3 LVCMOS clock outputs from 32.768 kHz
to 170 MHz
• Separate voltage supply pins
• VDD = 2.5 to 3.3 V
• Accepts crystal or reference clock input
• 3 to 165 MHz reference clock input
• 8 to 48 MHz crystal input
• VDDO = 1.8 to 3.3 V (VDDO < VDD
)
• Low cycle-cycle jitter
• Ultra small 8-pin TDFN package (1.4 mm x 1.6 mm)
• Programmable OE input function
• Low power dissipation
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Rev. 1.1 | 1
Si51218 Data Sheet
Design Considerations
2. Design Considerations
2.1 Typical Application Schematic
2.2 Comments and Recommendations
Decoupling Capacitor: A decoupling capacitor of 0.1 μF must be used between VDD and VSS on pins 1 and 8. Place the capacitor on
the component side of the PCB as close to the VDD pin as possible. The PCB trace to the VDD pin and to the GND via should be kept
as short as possible. Do not use vias between the decoupling capacitor and the VDD pin. In addition, a 10 µF capacitor should be
placed between VDD and VSS.
Crystal and Crystal Load: Only use a parallel resonant fundamental AT cut crystal. Do not use higher overtone crystals. To meet the
crystal initial accuracy specification (in ppm) make sure that the external crystal load capacitor is matched to the crystal load specifica-
tion. To determine the value of CL1 and CL2, use the following formula:
CL1 = CL2 = 2CL − (Cpin + Cp);
where CL is the load capacitance stated by the crystal manufacturer,
Cpin is the Si51218 pin capacitance (3 pF), and
Cp is the parasitic capacitance of the PCB traces.
Example: If a crystal with CL = 12 pF specification is used and Cp = 1 pF (parasitic PCB capacitance on PCB), 19 pF external capaci-
tors from pins XIN (pin 3) and XOUT (Pin 2) to VSS are required. Users must verify Cp value.
Table 2.1. Crystal Specifications
Equivalent Series Resistance (ESR)
Crystal Output Capacitance (CO)
Load Capacitance (CL)
< 50 Ω
< 3 pF
< 13 pF
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Si51218 Data Sheet
Electrical Specifications
3. Electrical Specifications
Table 3.1. DC Electrical Specifications
(VDD = 2.5 V ±10%, or VDD = 3.3V ±-10%, VDDO = VDD, CL = 10 pF, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
VDD= 3.3 V ± 10%
VDD= 2.5 V ± 10%
VDDO < VDD
Min
2.97
2.25
1.71
Typ
3.3
2.5
—
Max
3.63
2.75
3.6
Unit
V
Operating Voltage
VDD
V
VDDO
VOH
V
Output High Voltage
IOH= –4 mA
VDDX
0.5
–
—
—
V
VDDX = VDD or VDDO
IOL= 4 mA
Output Low Voltage
Input High Voltage
Input Low Voltage
VOL
VIH
VIL
—
—
—
0.3
—
V
V
CMOS Level
0.7 VDD
—
CMOS Level
—
0.3 VDD
9
V
Operating Supply Current1
IDD
FIN = 20 MHz, CLKOUT1 = 32.768
kHz, REFOUT2 = 20 MHz,
CLKOUT3 = 26 MHz, CL= 5 pF,
VDD = VDDO = 3.3 V
—
7.6
mA
Nominal Output Impedance
ZO
—
—
—
—
30
150k
3
—
—
5
Ω
Ω
Internal Pull-up/Pull-down Resistor RPUP/RPD
Pin 6
Input Pin Capacitance
Load Capacitance
Note:
CIN
CL
Input pin capacitance
pF
pF
—
10
1. IDD depends on input and output frequency configurations.
Table 3.2. AC Electrical Specifications
(VDD = 2.5 V ±10%, or VDD = 3.3 V ±10%, VDDO = VDD, CL = 10 pF, TA = –40 to 85 °C)
Parameter
Symbol
FIN1
Condition
Crystal input
Min
8
Typ
—
Max
48
Unit
MHz
MHz
MHz
Input Frequency Range
Input Frequency Range
Output Frequency Range
FIN2
Reference clock Input
3
—
165
170
FOUT
CLKOUT1: 32.768 kHz to 170 MHz 0.032768
CLKOUT2/3: 3 MHz to 170 MHz
—
Frequency Accuracy
Output Duty Cycle
FACC
Configuration dependent
Measured at VDDO/2
FOUT < 75 MHz
—
0
—
ppm
%
DCOUT
45
50
55
Measured at VDDO/2
FOUT > 75 MHz
40
30
50
50
60
70
%
Input Duty Cycle
DCIN
CLKIN, CLKOUT through PLL
%
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Si51218 Data Sheet
Electrical Specifications
Parameter
Symbol
tr/tf
Condition
Min
—
Typ
1
Max
2
Unit
ns
Output Rise/Fall Time
Period Jitter
CL= 10 pF, 20 to 80%
PJ1
CLKOUT1/2/3, at the same fre-
quency
—
12
20
ps rms
952
PJ2
PJ3
CLKOUT1/2/3, at different output
frequencies1
—
30
ps rms
ps
15002
85
CLKOUT1/3 at 32.768 kHz, VDD
VDDO = 3.3 V
=
Cycle-to-Cycle Jitter
CCJ1
CCJ2
CLKOUT1/2/3, at the same fre-
quency
—
—
150
ps
ps
2902
5
CLKOUT1/2/3, at different output
frequencies1
145
Power-up Time
tPU
Time from 0.9 VDD to valid
frequencies at all clock outputs
—
—
1.2
15
ms
ns
Output Enable Time
tOE
Time from OE rising edge to active
at outputs SSCLK1/2 (asynchro-
nous), FOUT = 133 MHz
—
Output Disable Time
tOD
Time from OE falling edge to active
at outputs SSCLK1/2 (asynchro-
nous), FOUT = 133 MHz
—
15
—
ns
Note:
1. Example frequency configurations:
• 8 MHz, 100 MHz, 75 MHz
• 48 MHz, 100 MHz, 66 2/3 MHz
• 96 MHz, 133 1/3 MHz, 133 1/3 MHz
2. Jitter performance depends on configuration and programming parameters.
Table 3.3. Absolute Maximum Conditions
Parameter
Symbol
VDD_3.3V
VIN
Condition
Min
–0.5
–0.5
–65
–40
—
Typ
—
—
—
—
—
—
—
Max
4.2
Unit
V
Main Supply Voltage
Input Voltage
Relative to VSS
Non-functional
VDD+0.5
150
V
Temperature, Storage
Temperature, Operating Ambient
Temperature, Junction
Temperature, Soldering
TS
°C
°C
°C
°C
V
TA
Functional, I-Grade
Functional, power is applied
Non-functional
85
TJ
125
TSol
—
260
ESD Protection (Human Body Mod- ESDHBM
el)
JEDEC (JESD 22-A114)
–4000
4000
ESD Protection (Charge Device
Model)
ESDCDM
JEDEC (JESD 22-C101)
JEDEC (JESD 22-A115)
–1500
–200
—
—
1500
200
V
V
ESD Protection (Machine Model)
ESDMM
Note:
1. While using multiple power supplies, the voltage on any input or I/O pin cannot exceed the power pin during power-up. Power
supply sequencing is not required.
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Si51218 Data Sheet
Electrical Specifications
Table 3.4. Thermal Characteristics
Parameter
Symbol
θJA
Condition
Still air
Value
170.8
Unit
°C/W
°C/W
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Case
θJC
Still air
VDD+0.5
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Si51218 Data Sheet
Functional Description
4. Functional Description
4.1 Input Frequency Range
The input frequency range is from 8.0 to 48.0 MHz for crystals and ceramic resonators. If an external clock is used, the input frequency
range is from 3.0 to 165.0 MHz.
4.2 Output Frequency Range and Outputs
Up to three outputs can be programmed as CLKOUT or REFOUT. The CLKOUT1 synthesized frequencies can have values from
32.768 kHz to 170 MHz. REFOUT is the buffered output of the oscillator and is the same frequency as the input frequency. By using
only low cost, fundamental mode crystals, the Si51218 can synthesize output frequencies up to 170 MHz (CLKOUT2/3), eliminating the
need for higher order crystals (Xtals) and crystal oscillators (XOs). The 32.768 kHz output can replace the 32.768 kHz crystal, which is
widely used in many embedded and mobile systems. This reduces the cost while improving the system clock accuracy, performance,
and reliability.
4.3 Output Enable (OE)
The Si51218 pin 4 and pin 6 can be programmed as OE input. OE only disables the output buffers to Hi-Z. The OE function is asyn-
chronous. Any requirement for synchronous operations (like glitchless output clock switching) needs to be handled externally.
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Si51218 Data Sheet
Pin Description
5. Pin Description
VDD
XOUT
VDDO
1
2
3
4
8
7
6
CLKOUT3
Si51218
CLKOUT2/REFOUT2/
OE
XIN/CLKIN
CLKOUT1/
REFOUT1/OE
5
VSS
Figure 5.1. 8-Pin TDFN
Table 5.1. Si51218 8-Pin Descriptions
Pin #
Name
VDD
Type
PWR
O
Description
1
2
2.5 to 3.3 V power supply.
XOUT
Crystal output. Leave this pin unconnected (floating) if an external
clock input is used.
3
XIN/CLKIN
I
External crystal and clock input.
4
CLKOUT1/REFOUT1/OE
I/O
Programmable CLKOUT1 or REFOUT1 output or OE control in-
put. The frequency at this pin is synthesized by the internal PLL if
programmed as CLKOUT1. If programmed as REFOUT1, the out-
put clock is a buffered output of the crystal or reference clock in-
put.
5
6
VSS
GND
I/O
Ground.
CLKOUT2/REFOUT2/OE
Programmable CLKOUT2 or REFOUT2 output or OE control in-
put. The frequency at this pin is synthesized by the internal PLL if
programmed as CLKOUT2. This output clock can also be the buf-
fered output (REFOUT2) of the crystal or reference clock input. It
is powered by the VDDO pin (pin 8).
7
8
CLKOUT3
VDDO
O
Programmable CLKOUT3 output. The frequency at this pin is syn-
thesized by the internal PLL. It is powered by the VDDO pin (pin 8).
PWR
1.8 to 3.3 V output power supply to CLKOUT2/3 (pin 6/7).
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Si51218 Data Sheet
Ordering Guide
6. Ordering Guide
Table 6.1. Si51218 Ordering Guide
Part Number
Package Type
8-pin TDFN
Temperature
Si51218-Axxxxx-GM
Si51218-Axxxxx-GMR
Industrial, –40 to 85 °C
Industrial, –40 to 85 °C
8-pin TDFN—Tape and Reel
GMR
Axxxxx
Si51218
G = -40 to 85°C (Operating temp
range)
M = TDFN, ROHS6, Pb free
Base part number
R = Tape & Reel; (Blank) = Coil Tape
A = Product Revision A
xxxxx = 2nd option code
A five character code will be assigned
for each unique configuration
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Si51218 Data Sheet
Package Outline
7. Package Outline
Figure 7.1. 8-pin TDFN
Table 7.1. Si51218 Package Dimensions
Dimension
Min
0.70
0.00
Nom
0.75
Max
0.80
0.05
A
A1
A3
b
0.02
0.20 REF
0.20
0.15
1.00
0.25
1.10
D
1.60 BSC
1.05
D2
e
0.40 BSC
1.40 BSC
0.25
E
E2
L
0.20
0.30
0.30
0.40
0.35
aaa
bbb
ccc
ddd
eee
0.10
0.10
0.10
0.07
0.08
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Si51218 Data Sheet
Package Outline
Dimension
Min
Nom
Max
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted..
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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Si51218 Data Sheet
PCB Land Pattern
8. PCB Land Pattern
The figure below illustrates the PCB land pattern details for the device. The table below lists the values for the dimensions shown in the
illustration.
Figure 8.1. Si51218 8-pin TDFN PCB Land Pattern
Table 8.1. PCB Land Pattern Dimensions
Dimension
mm
1.40
0.40
0.75
0.20
0.25
1.10
C
E
X1
Y1
X2
Y2
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Si51218 Data Sheet
Revision History
9. Revision History
9.1 Revision 1.0
April 20, 2016
• Updated max output frequency to 170 MHz
• Updated max clock input frequency to 165 MHz
• Updated Operating Temperature to Industrial temperature, –40 °C to 85 °C
• Removed programmable output rise/fall time.
• Updated Table 3.1 DC Electrical Specifications on page 3
• Updated Table 3.2 AC Electrical Specifications on page 3
• Updated pin descriptions in Pin Descriptions table.
• Updated customized part numbering nomenclature in 6. Ordering Guide
• Added land pattern drawing
• Removed FSEL and PD functions
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Rev. 1.1 | 12
Table of Contents
1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Design Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.1 Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . 2
2.2 Comments and Recommendations . . . . . . . . . . . . . . . . . . . . . . . 2
3. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
4. Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.1 Input Frequency Range . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.2 Output Frequency Range and Outputs . . . . . . . . . . . . . . . . . . . . . 6
4.3 Output Enable (OE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5. Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
7. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
8. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
9. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
9.1 Revision 1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Table of Contents 13
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