SI52147 [SILICON]
PCI-EXPRESS GEN 1, GEN 2, & GEN 3 NINE OUTPUT CLOCK GENERATOR; PCI - EXPRESS GEN 1 ， GEN 2 ，与第3代九个输出时钟发生器
| 型号： | SI52147 |
| 厂家： | 
SILICON |
| 描述： | PCI-EXPRESS GEN 1, GEN 2, & GEN 3 NINE OUTPUT CLOCK GENERATOR |
| 文件： | 总22页 (文件大小：182K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si52147
PCI-EXPRESS GEN 1, GEN 2, & GEN 3 NINE OUTPUT
CLOCK GENERATOR
Features
PCI-Express Gen 1, Gen 2, &
25 MHz crystal input or clock
Gen 3 compliant
input
2
Low power push-pull type
I C support with readback
differential output buffers
capabilities
Integrated resistors on differential
Triangular spread spectrum
profile for maximum
clocks
Output enable pin for all clocks
electromagnetic interference
(EMI) reduction
Hardware selectable spread
control
Industrial temperature:
o
Nine PCI-Express clocks
–40 to 85 C
Ordering Information:
3.3 V power supply
48-pin QFN package
See page 20.
Pin Assignments
Applications
Network attached storage
Multi-function printer
Wireless access point
Routers
48
47
46
45
44
43
42
41
40
39
38
37
DIFF8
DIFF8
36
35
34
33
VDD
1
2
3
4
VDD
Description
OE01
VDD
DIFF7
OE11
32 DIFF7
SSON2
VSS_PLL3
VSS_PLL4
OE21
5
6
7
8
9
The Si52147 is a spread-controlled PCIe clock generator that can source
nine PCIe clocks simultaneously. The device has six hardware output
enable control inputs for enabling the respective differential outputs on the
fly while powered on along with the hardware spread control for EMI
reduction.
31
30
29
28
DIFF6
DIFF6
49
GND
VDD
OE31
DIFF5
27 DIFF5
OE[4:5]1 10
DIFF4
DIFF4
26
25
OE[6:8]1
11
12
VDD
13
14
15
16
17
18
19
20
21
22
23
24
Functional Block Diagram
Notes:
1. Internal 100 kohm pull-up.
2. Internal 100 kohm pull-down.
Patents pending
DIFF0
XIN/CLKIN
XOUT
DIFF1
DIFF2
DIFF3
PLL1
Divider
DIFF4
(SSC)
DIFF5
DIFF6
SCLK
Control & Memory
SDATA
DIFF7
CKPWRGD/PDB
Control
RAM
OE [8:0]
SSON
DIFF8
Preliminary Rev. 0.1 12/11
Copyright © 2011 by Silicon Laboratories
Si52147
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si52147
2
Preliminary Rev. 0.1
Si52147
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.1. Crystal Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.2. CKPWRGD_PDB (Power down) Clarification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.3. PDB (Power down) Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.4. PDB Deassertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.5. OE Clarification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.6. OE Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.7. OE Deassertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.8. SSON Clarification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3. Test and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.1. Serial Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.2. Data Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
5. Pin Descriptions: 48-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
7. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Preliminary Rev. 0.1
3
Si52147
1. Electrical Specifications
Table 1. DC Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
3.3 V Operating Voltage
VDD core
3.3 ±5%
3.135
3.3
3.465
V
3.3 V Input High Voltage
3.3 V Input Low Voltage
Input High Voltage
V
Control input pins
Control input pins
SDATA, SCLK
2.0
—
—
—
—
—
V
+ 0.3
DD
V
V
IH
V
V
– 0.3
SS
0.8
IL
V
2.2
—
1.0
5
V
IHI2C
Input Low Voltage
V
SDATA, SCLK
—
—
V
ILI2C
Input High Leakage Current
I
Except internal pull-down
A
IH
resistors, 0 < V < V
IN
DD
Input Low Leakage Current
I
Except internal pull-up
resistors, 0 < V < V
–5
—
—
A
IL
IN
DD
3.3 V Output High Voltage
(SE)
V
I
= –1 mA
2.4
—
—
—
—
—
0.4
10
V
V
OH
OH
3.3 V Output Low Voltage
(SE)
V
I
OL
= 1 mA
OL
OZ
High-impedance Output
Current
I
–10
A
Input Pin Capacitance
Output Pin Capacitance
Pin Inductance
C
1.5
—
—
—
—
—
—
—
—
—
5
6
pF
pF
IN
C
OUT
L
7
nH
mA
mA
IN
Power Down Current
Dynamic Supply Current
I
_
1
DD PD
I
All outputs enabled. Differ-
ential clocks with 5” traces
and 2 pF load.
85
DD_3.3V
4
Preliminary Rev. 0.1
Si52147
Table 2. AC Electrical Specifications
Parameter
Symbol
Condition
Min
Typ
Max
Unit
Crystal
Long-term Accuracy
Clock Input
L
Measured at V /2 differential
—
—
250
ppm
ACC
DD
CLKIN Duty Cycle
CLKIN Rise and Fall Times
T
Measured at V /2
47
—
—
53
%
DC
DD
T /T
Measured between 0.2 V and
0.5
4.0
V/ns
R
F
DD
0.8 V
DD
CLKIN Cycle to Cycle Jitter
CLKIN Long Term Jitter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
DIFF at 0.7 V
T
Measured at VDD/2
Measured at VDD/2
XIN/CLKIN pin
—
—
2
—
—
—
—
—
—
250
350
ps
ps
V
CCJ
T
LTJ
V
VDD+0.3
0.8
IH
V
XIN/CLKIN pin
—
—
–35
V
IL
I
XIN/CLKIN pin, VIN = VDD
XIN/CLKIN pin, 0 < VIN <0.8
35
uA
uA
IH
I
—
IL
DIFF Duty Cycle
T
Measured at 0 V differential
Measured at 0 V differential
45
—
—
—
55
50
%
DC
Any DIFF Clock Skew from the T
Earliest Bank to the Latest
Bank
ps
SKEW(win
dow)
DIFF Cycle to Cycle Jitter
T
Measured at 0 V differential
—
0
35
40
50
ps
ps
CCJ
Output PCIe Gen1 REFCLK
Phase Jitter
RMS
108
Includes PLL BW 1.5–22 MHz,
ζ = 0.54, Td=10 ns,
GEN1
Ftrk=1.5 MHz with BER = 1E-12
Output PCIe Gen2 REFCLK
Phase Jitter
RMS
RMS
Includes PLL BW 8–16 MHz, Jitter
Peaking = 3 dB, ζ = 0.54, Td=12 ns,
Low Band, F < 1.5 MHz
0
0
0
2
2
3.0
3.1
1.0
ps
ps
ps
GEN2
GEN2
GEN3
Output PCIe Gen2 REFCLK
Phase Jitter
Includes PLL BW 8–16 MHz, Jitter
Peaking = 3 dB, ζ = 0.54, Td=12 ns,
High Band,1.5 MHz < F < Nyquist
Output Phase Jitter Impact— RMS
PCIe Gen3
Includes PLL BW 2–4 MHz,
CDR = 10 MHz
0.5
DIFF Long Term Accuracy
L
Measured at 0 V differential
—
1
—
—
100
8
ppm
V/ns
ACC
DIFF Rising/Falling Slew Rate
T /T
Measured differentially from
±150 mV
R
F
Voltage High
Voltage Low
V
—
—
—
—
1.15
—
V
V
HIGH
V
–0.3
300
LOW
Crossing Point Voltage at
0.7 V Swing
V
550
mV
OX
Enable/Disable and Setup
Clock Stabilization from
Power-up
T
—
—
—
1.8
—
ms
ns
STABLE
Stopclock Set-up Time
T
10.0
SS
Preliminary Rev. 0.1
5
Si52147
Table 3. Absolute Maximum Conditions
Parameter
Main Supply Voltage
Symbol
Condition
Min
Typ
Max Unit
V
Functional
—
—
4.6
4.6
150
85
V
DD_3.3V
Input Voltage
V
Relative to V
–0.5
–65
–40
—
—
—
—
—
—
—
—
V–0
2
V
DC
IN
SS
Temperature, Storage
T
Non-functional
Functional
°C
S
Temperature, Operating Ambient
Temperature, Junction
T
°C
°C
A
T
Functional
150
22
J
Dissipation, Junction to Case
Dissipation, Junction to Ambient
ESD Protection (Human Body Model)
Flammability Rating
Ø
JEDEC (JESD 51)
JEDEC (JESD 51)
—
°C/W
°C/W
V
JC
JA
Ø
—
30
ESD
JEDEC (JESD 22-A114) 2000
UL (Class)
—
HBM
UL-94
MSL
Moisture Sensitivity Level
JEDEC (J-STD-020)
Note: While using multiple power supplies, the voltage on any input or I/O pin cannot exceed the power pin during power-up.
Power supply sequencing is not required.
6
Preliminary Rev. 0.1
Si52147
2. Functional Description
2.1. Crystal Recommendations
The clock device requires a parallel resonance crystal. Substituting a series resonance crystal causes the clock
device to operate at the wrong frequency and violates the ppm specification. For most applications there is a
300 ppm frequency shift between series and parallel crystals due to incorrect loading.
Table 4. Crystal Recommendations
Frequency
(Fund)
Cut
Loading Load Cap
Shunt
Cap (max)
Motional
(max)
Tolerance
(max)
Stability
(max)
Aging
(max)
25 MHz
AT
Parallel 12–15 pF
5 pF
0.016 pF
35 ppm
30 ppm
5 ppm
2.1.1. Crystal Loading
Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, use the
total capacitance the crystal sees to calculate the appropriate capacitive loading (CL).
Figure 1 shows a typical crystal configuration using the two trim capacitors. It is important that the trim capacitors
are in series with the crystal. It is not true that load capacitors are in parallel with the crystal and are approximately
equal to the load capacitance of the crystal.
Figure 1. Crystal Capacitive Clarification
2.1.2. Calculating Load Capacitors
In addition to the standard external trim capacitors, consider the trace capacitance and pin capacitance to calculate
the crystal loading correctly. Again, the capacitance on each side is in series with the crystal. The total capacitance
on both side is twice the specified crystal load capacitance (CL). Trim capacitors are calculated to provide equal
capacitive loading on both sides.
Figure 2. Crystal Loading Example
Preliminary Rev. 0.1
7
Si52147
Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2.
Load Capacitance (each side)
Ce = 2 x CL – (Cs + Ci)
Total Capacitance (as seen by the crystal)
1
CLe
=
1
1
(
)
+
Ce2 + Cs2 + Ci2
Ce1 + Cs1 + Ci1
CL: Crystal load capacitance
CLe: Actual loading seen by crystal using standard value trim capacitors
Ce: External trim capacitors
Cs: Stray capacitance (terraced)
Ci : Internal capacitance (lead frame, bond wires, etc.)
2.2. CKPWRGD_PDB (Power down) Clarification
The CKPWRGD_PDB pin is a dual-function pin. During initial power up, the pin functions as CKPWRGD. Upon the
2
first powerup if the CKPWRGD is low, the device outputs will be disabled, but the crystal oscillator and I C logics
are active. Once CKPWRGD has been sampled high by the clock chip, the pin assumes a PDB functionality. When
the pin has assumed a PDB functionality and the pin is pull low, the device will be placed in standby mode.
2.3. PDB (Power down) Assertion
The PDB pin is an asynchronous active low input used to disable all clocks in a glitch free manner. All outputs will
2
be driven low in power down mode. In power down mode, all outputs, the crystal oscillator and the I C logic are
disabled.
2.4. PDB Deassertion
When a valid rising edge on CKPWRGD/PDB pin is applied, all outputs are enabled in a glitch free manner within
two to six output clock cycle.
2.5. OE Clarification
The OE pins are active high inputs used to enable and disable the output clocks. To enable the output clock, the OE
2
pin needs to be logic high and the I C output enable bit needs to be logic high. There are two methods to disable
2
the output clocks: the OE is pulled to a logic low, or the I C enable bit is set to a logic low. The OE pins is required
to be driven at all time and even though it has an internally 100 k resistor.
2.6. OE Assertion
The OE signals are active high input used for synchronous stopping and starting the DIFF output clocks respectively
while the rest of the clock generator continues to function. The assertion of the OE signal by making it logic high
causes stopped respective DIFF output to resume normal operation. No short or stretched clock pulses are produced
when the clock resumes. The maximum latency from the assertion to active outputs is no more than two to six output
clock cycles.
2.7. OE Deassertion
When the OE pin is deasserted by making its logic low, the corresponding DIFF output is stopped cleanly, and the
final output state is driven low.
2.8. SSON Clarification
SSON is an active input used to enable –0.5% spread on all DIFF outputs. When sampled high, –0.5% spread is
enabled on all DIFF outputs. When sampled low, the DIFF output frequencies are non-spread.
8
Preliminary Rev. 0.1
Si52147
3. Test and Measurement Setup
This diagram shows the test load configuration for the differential clock signals.
M easurem ent
L1
P oint
O U T+
50
2 pF
L1 = 5"
M easurem ent
P oint
L1
O U T-
50
2 pF
Figure 3. 0.7 V Differential Load Configuration
Figure 4. Differential Output Signals (for AC Parameters Measurement)
Preliminary Rev. 0.1
9
Si52147
VMIN = –0.30V
VMIN = –0.30V
Figure 5. Single-ended Measurement for Differential Output Signals
(for AC Parameters Measurement)
10
Preliminary Rev. 0.1
Si52147
4. Control Registers
4.1. Serial Data Interface
To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through
the Serial Data Interface, various device functions, such as individual clock output buffers are individually enabled
or disabled. The registers associated with the Serial Data Interface initialize to their default setting at power-up.
The use of this interface is optional. Clock device register changes are normally made at system initialization, if any
are required. The interface cannot be used during system operation for power management functions.
4.2. Data Protocol
The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the
controller. For block write/read operation, access the bytes in sequential order from lowest to highest (most
significant bit first) with the ability to stop after any complete byte is transferred. For byte write and byte read
operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded
in the command code described in Table 1 on page 4.
The block write and block read protocol is outlined in Table 5 while Table 6 outlines byte write and byte read
protocol. The slave receiver address is 11010110 (D6h).
Table 5. Block Read and Block Write Protocol
Block Write Protocol
Description
Block Read Protocol
Description
Bit
1
Bit
1
Start
Start
8:2
9
Slave address—7 bits
Write
8:2
9
Slave address–7 bits
Write
10
Acknowledge from slave
Command Code—8 bits
Acknowledge from slave
Byte Count—8 bits
Acknowledge from slave
Data byte 1–8 bits
10
Acknowledge from slave
18:11
19
18:11 Command Code–8 bits
19
20
Acknowledge from slave
Repeat start
27:20
28
27:21 Slave address–7 bits
36:29
37
28
29
Read = 1
Acknowledge from slave
Data byte 2–8 bits
Acknowledge from slave
45:38
46
37:30 Byte Count from slave–8 bits
38 Acknowledge
46:39 Data byte 1 from slave–8 bits
47 Acknowledge
55:48 Data byte 2 from slave–8 bits
Acknowledge from slave
Data Byte/Slave Acknowledges
Data Byte N–8 bits
Acknowledge from slave
Stop
....
....
....
....
56
....
....
....
....
Acknowledge
Data bytes from slave/Acknowledge
Data Byte N from slave–8 bits
NOT Acknowledge
Stop
Preliminary Rev. 0.1
11
Si52147
Table 6. Byte Read and Byte Write Protocol
Byte Write Protocol
Byte Read Protocol
Description
Bit
Description
Bit
1
Start
1
Start
8:2
9
Slave address–7 bits
Write
8:2
9
Slave address–7 bits
Write
10
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Data byte–8 bits
10
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Repeated start
18:11
19
18:11
19
27:20
28
20
Acknowledge from slave
Stop
27:21
28
Slave address–7 bits
Read
29
29
Acknowledge from slave
Data from slave–8 bits
NOT Acknowledge
Stop
37:30
38
39
12
Preliminary Rev. 0.1
Si52147
Control Register 0. Byte 0
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset settings = 00000000
Bit
Name
Reserved
Function
7:0
Control Register 1. Byte 1
Bit
D7
D6
D5
D4
DIFF0_OE
R/W
D3
D2
DIFF1_OE
R/W
D1
DIFF2_OE
R/W
D0
DIFF3_OE
R/W
Name
Type
R/W
R/W
R/W
R/W
Reset settings = 00010111
Bit
Name
Function
7:5
Reserved
4
DIFF0_OE
Output Enable for DIFF0.
0: Output disabled.
1: Output enabled.
3
2
Reserved
DIFF1_OE
Output Enable for DIFF1.
0: Output disabled.
1: Output enabled.
1
0
DIFF2_OE
DIFF3_OE
Output Enable for DIFF2.
0: Output disabled.
1: Output enabled.
Output Enable for DIFF3.
0: Output disabled.
1: Output enabled.
Preliminary Rev. 0.1
13
Si52147
Control Register 2. Byte 2
Bit
D7
D6
D5
D4
D3
D2
D1
D0
DIFF4_OE
DIFF5_OE
DIFF6_OE
DIFF7_OE
DIFF8_OE
Name
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset settings = 11111000
Bit
Name
Function
7
DIFF4_OE
Output Enable for DIFF4.
0: Output disabled.
1: Output enabled.
6
5
DIFF5_OE
DIFF6_OE
DIFF7_OE
Output Enable for DIFF5.
0: Output disabled.
1: Output enabled.
Output Enable for DIFF6.
0: Output disabled.
1: Output enabled.
4
3
Output Enable for DIFF7.
0: Output disabled.
1: Output enabled.
DIFF8_OE
Reserved
Output Enable for DIFF8.
0: Output disabled.
1: Output enabled.
2:0
14
Preliminary Rev. 0.1
Si52147
Control Register 3. Byte 3
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
Rev Code[3:0]
Vendor ID[3:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset settings = 00001000
Bit
Name
Function
7:4
Rev Code[3:0]
Vendor ID[3:0]
Program Revision Code.
3:0
Vendor Identification Code.
Control Register 4. Byte 4
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
BC[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset settings = 00000110
Bit
Name
BC[7:0]
Function
7:0
Byte Count Register.
Preliminary Rev. 0.1
15
Si52147
Control Register 5. Byte 5
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name DIFF_Amp_Sel DIFF_Amp_Cntl[2] DIFF_Amp_Cntl[1] DIFF_Amp_Cntl[0]
Type
R/W
R/W
R/W
R/W
R/W R/W R/W R/W
Reset settings = 11011000
Bit
Name
Function
7
DIFF_Amp_Sel
Amplitude Control for DIFF Differential Outputs.
0: Differential outputs with Default amplitude.
1: Differential outputs amplitude is set by Byte 5[6:4].
6
5
DIFF_Amp_Cntl[2]
DIFF_Amp_Cntl[1]
DIFF_Amp_Cntl[0]
Reserved
DIFF Differential Outputs Amplitude Adjustment.
000: 300 mV 001: 400 mV 010: 500 mV 011: 600 mV
100: 700 mV 101: 800 mV 110: 900 mV 111: 1000 mV
4
3:0
16
Preliminary Rev. 0.1
Si52147
5. Pin Descriptions: 48-Pin QFN
48
47
46
45
44
43
42
41
40
39
38
37
DIFF8
DIFF8
36
35
34
33
VDD
1
2
3
4
5
6
7
8
9
VDD
OE01
VDD
DIFF7
OE11
32 DIFF7
SSON2
VSS_PLL3
VSS_PLL4
OE21
31
30
29
28
DIFF6
DIFF6
49
GND
VDD
OE31
DIFF5
27 DIFF5
OE[4:5]1 10
DIFF4
DIFF4
26
25
OE[6:8]1
11
12
VDD
13
14
15
16
17
18
19
20
21
22
23
24
Notes:
1. Internal 100 kohm pull-up.
2. Internal 100 kohm pull-down.
Table 7. Part Number 48-Pin QFN Descriptions
Pin #
Name
Type
Description
PWR 3.3 V Power Supply
1
VDD
PWR 3.3 V Power Supply
2
3
VDD
OE0
I,PU 3.3 V input to disable DIFF0 (internal 100 k pull-up).
Refer to Table 1 on page 4 for OE specifications.
I,PU 3.3 V input to disable DIFF1 (internal 100 k pull-up).
4
5
6
OE1
SSON
VSS
Refer to Table 1 on page 4 for OE specifications.
I, PD 3.3 V-tolerant input for enabling –0.5% spread on DIFF clocks (internal
100 k pull-down)
GND Ground
Preliminary Rev. 0.1
17
Si52147
Table 7. Part Number 48-Pin QFN Descriptions
Pin #
Name
Type
Description
GND Ground
7
VSS
OE2
I,PU 3.3 V input to disable DIFF2 (internal 100 k pull-up).
8
9
Refer to Table 1 on page 4 for OE specifications.
I,PU 3.3 V input to disable DIFF3 (internal 100 k pull-up).
OE3
Refer to Table 1 on page 4 for OE specifications.
I,PU
10
OE[4:5]
3.3 V input to disable DIFF[4:5] (internal 100 k pull-up).
Refer to Table 1 on page 4 for OE specifications.
I,PU 3.3 V input to disable DIFF[6:8] (internal 100 k pull-up).
11
OE[6:8]
Refer to Table 1 on page 4 for OE specifications.
PWR 3.3 V Power Supply
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
VDD
VDD
PWR 3.3 V Power Supply
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
VSS Ground
DIFF0
DIFF0
VSS
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
PWR 3.3V Power Supply
DIFF1
DIFF1
DIFF2
DIFF2
DIFF3
DIFF3
VDD
GND Ground
VSS
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
GND Ground
DIFF4
DIFF4
DIFF5
DIFF5
VSS
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
DIFF6
DIFF6
DIFF7
DIFF7
18
Preliminary Rev. 0.1
Si52147
Table 7. Part Number 48-Pin QFN Descriptions
Pin #
Name
Type
Description
PWR 3.3 V Power Supply
34
VDD
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
35
36
37
38
39
DIFF8
DIFF8
I
SMBus compatible SCLOCK
SCLK
I/O SMBus compatible SDATA
I, PU
SDATA
CKPWRGD_PDB
3.3 V CMOS input. A real-time active low input for asserting power
down (PDB) and disabling all outputs (internal 100 k pull-up).
PWR 3.3 V Power Supply
40
41
42
43
44
45
46
47
48
49
VDD_CORE
XOUT
XIN/CLKIN
NC
O
I
25.00 MHz Crystal output, Float XOUT if using only CLKIN (Clock input)
25.00 MHz Crystal input or 3.3 V, 25 MHz Clock Input
NC No Connect
NC No Connect
GND Ground
NC
VSS_CORE
VSS
GND Ground
NC No Connect
NC No Connect
NC
NC
GND
GND Ground for bottom pad of the IC.
Preliminary Rev. 0.1
19
Si52147
6. Ordering Guide
Part Number
Lead-free
Package Type
Temperature
Si52147-A01AGM
Si52147-A01AGMR
48-pin QFN
Industrial, –40 to 85 C
Industrial, –40 to 85 C
48-pin QFN—Tape and Reel
20
Preliminary Rev. 0.1
Si52147
7. Package Outline
Figure 6 illustrates the package details for the Si52147. Table 8 lists the values for the dimensions shown in the
illustration.
Figure 6. 48-Pin Quad Flat No Lead (QFN) Package
Table 8. Package Diagram Dimensions
Symbol
Millimeters
Nom
Min
0.70
0.00
0.15
Max
0.80
0.05
0.25
A
A1
b
0.75
0.025
0.20
D
6.00 BSC
4.40
D2
e
4.30
4.50
0.40 BSC
6.00 BSC
4.40
E
E2
L
4.30
0.30
4.50
0.50
0.40
aaa
bbb
ccc
ddd
0.10
0.10
0.08
0.07
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise
noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-220, variation VGGD-8
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components
Preliminary Rev. 0.1
21
Si52147
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Please visit the Silicon Labs Technical Support web page:
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-
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plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
22
Preliminary Rev. 0.1
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