SI5316-B-GM [SILICON]
PRELIMINARY DATA SHEET PRECISION CLOCK JITTER ATTENUATOR; 初步数据表精确时钟抖动衰减器
| 型号： | SI5316-B-GM |
| 厂家： | 
SILICON |
| 描述： | PRELIMINARY DATA SHEET PRECISION CLOCK JITTER ATTENUATOR |
| 文件： | 总16页 (文件大小：584K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si5316
PRELIMINARY DATA SHEET
PRECISION CLOCK JITTER ATTENUATOR
Description
Features
The Si5316 is a low jitter, precision jitter attenuator for
high-speed communication systems, including OC-48,
OC-192, 10G Ethernet, and 10G Fibre Channel. The
Si5316 accepts dual clock inputs in the 19, 38, 77, 155,
311, or 622 MHz frequency range and generates a
jitter-attenuated clock output at the same frequency.
Within each of these clock ranges, the device can be
tuned approximately 15% higher than nominal
SONET/SDH frequencies, up to a maximum of
710 MHz in the 622 MHz range. The Si5316 is based
Fixed frequency jitter attenuator with selectable
clock ranges at 19, 38, 77, 155, 311, and 622 MHz
(710 MHz max)
Support for SONET, 10GbE, 10GFC, and
corresponding FEC rates
Ultra-low jitter clock output with jitter generation as
low as 0.3 ps
(50 kHz–80 MHz)
RMS
Integrated loop filter with selectable loop bandwidth
(100 Hz to 7.9 kHz)
®
Meets OC-192 GR-253-CORE jitter specifications
Dual clock inputs with integrated clock select mux
on Silicon Laboratories' 3rd-generation DSPLL
technology, which provides any-rate frequency
synthesis and jitter attenuation in a highly integrated
PLL solution that eliminates the need for external
VCXO and loop filter components. The DSPLL loop
bandwidth is digitally programmable, providing jitter
performance optimization at the application level.
Operating from a single 1.8, 2.5, or 3.3 V supply, the
Si5316 is ideal for providing jitter attenuation in high
performance timing applications.
One clock input can be 1x, 4x, or 32x the frequency
of the second clock input
Single clock output with selectable signal format:
LVPECL, LVDS, CML, CMOS
LOL, LOS alarm outputs
Pin programmable settings
On-chip voltage regulator for 1.8, 2.5, or 3.3 V
±10% operation
Applications
Small size (6 x 6 mm 36-lead QFN)
Pb-free, RoHS compliant
Optical modules
SONET/SDH OC-48/OC-192 line cards
10GbE, 10GFC line cards
ITU G.709 line cards
Wireless basestations
Test and measurement
Xtal or Refclock
CK1DIV
Signal Format
CKIN1
÷
DSPLL®
CKOUT
Disable
CK2DIV
CKIN2
÷
Signal
Detect
VDD (1.8, 2.5, or 3.3 V)
GND
Loss of Signal
Frequency Bandwidth
Select Select
PLL
Bypass
Clock
Select
Loss of
Lock
Preliminary Rev. 0.24 3/07
Copyright © 2007 by Silicon Laboratories
Si5316
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si5316
Table 1. Performance Specifications
(VDD = 1.8, 2.5, or 3.3 V ±10%, TA = –40 to 85 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Temperature Range
Supply Voltage
T
–40
2.97
2.25
1.62
—
25
3.3
2.5
1.8
217
85
ºC
V
A
V
3.63
2.75
1.98
243
DD
V
V
Supply Current
I
f
= 622.08 MHz
mA
DD
OUT
LVPECL format output
f
= 19.44 MHz
—
194
220
mA
OUT
CMOS format output
Tristate/Sleep Mode
—
TBD
TBD
mA
Input/Output Clock Fre-
quency (CKIN1, CKIN2,
CKOUT)
CK
FRQSEL[1:0] = LL
FRQSEL[1:0] = LM
FRQSEL[1:0] = LH
FRQSEL[1:0] = ML
FRQSEL[1:0] = MM
FRQSEL[1:0] = MH
19.38
38.75
77.5
155.0
310.0
620.0
—
—
—
—
—
—
22.28
44.56
89.13
178.25
356.5
710.0
MHz
F
Input Clocks (CKIN1, CKIN2)
Differential Voltage Swing
Common Mode Voltage
CKN
CKN
0.25
0.9
1.0
1.1
—
—
—
—
—
—
—
—
1.9
1.4
1.7
1.95
11
V
PP
DPP
1.8V ±10%
2.5V ±10%
V
V
VCM
3.3V ±10%
V
Rise/Fall Time
Duty Cycle
CKN
20–80%
ns
%
ns
TRF
CKN
Whichever is less
40
60
DC
50
—
Output Clock (CKOUT)
Common Mode
V
LVPECL
100 Ω load
line-to-line
V
– 1.42
—
—
—
V – 1.25
DD
V
OCM
DD
Differential Output Swing
Single Ended Output Swing
V
1.1
0.5
1.9
V
PP
OD
V
0.93
V
SE
Rise/Fall Time
Duty Cycle
CKO
20–80%
—
230
—
350
55
ps
%
TRF
CKO
45
DC
PLL Performance
Jitter Generation
J
f
= 622.08 MHz,
—
0.3
TBD
ps rms
GEN
OUT
LVPECL output format
50 kHz–80 MHz
12 kHz–20 MHz
—
—
0.3
TBD
0.1
ps rms
dB
Jitter Transfer
J
0.05
PK
Note: For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision
Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing.
2
Preliminary Rev. 0.24
Si5316
Table 1. Performance Specifications (Continued)
(VDD = 1.8, 2.5, or 3.3 V ±10%, TA = –40 to 85 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
External Reference Jitter
Transfer
J
—
TBD
TBD
dB
PKEXTN
Phase Noise
CKO
f
= 622.08 MHz
—
TBD
TBD
dBc/Hz
PN
OUT
100 Hz offset
1 kHz offset
—
—
—
—
—
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc
10 kHz offset
100 kHz offset
1 MHz offset
Subharmonic Noise
Spurious Noise
Package
SP
SP
Phase Noise @ 100 kHz
Offset
SUBH
SPUR
Max spur @ n x F3
(n > 1, n x F3 < 100 MHz)
—
TBD
TBD
dBc
Thermal Resistance
Junction to Ambient
θ
Still Air
—
38
—
ºC/W
JA
Note: For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision
Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing.
Table 2. Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
DC Supply Voltage
V
–0.5 to 3.6
V
V
DD
DIG
JCT
STG
LVCMOS Input Voltage
V
–0.3 to (V + 0.3)
DD
Operating Junction Temperature
Storage Temperature Range
ESD HBM Tolerance (100 pF, 1.5 kΩ)
ESD MM Tolerance
T
–55 to 150
–55 to 150
2
ºC
ºC
kV
V
T
200
Latch-Up Tolerance
JESD78 Compliant
Note: Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operation sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods of time may affect device reliability.
Preliminary Rev. 0.24
3
Si5316
155.52 MHz in, 622.08 MHz out
0
-20
-40
-60
-80
-100
-120
-140
-160
100
1000
10000
100000
1000000
10000000
100000000
Offset Frequency (Hz)
Figure 1. Typical Phase Noise Plot
4
Preliminary Rev. 0.24
Si5316
Figure 2. Si5316 Typical Application Circuit
Preliminary Rev. 0.24
5
Si5316
The Si5316 has one differential clock output. The
electrical format of the clock output is programmable to
1. Functional Description
The Si5316 is a precision jitter attenuator for high-speed support LVPECL, LVDS, CML, or CMOS loads. For
communication systems, including OC-48, OC-192, system-level debugging, a bypass mode is available
10G Ethernet, and 10G Fibre Channel. The Si5316 which drives the output clock directly from the input
accepts dual clock inputs in the 19, 38, 77, 155, 311, or clock, bypassing the internal DSPLL. The device is
622 MHz frequency range and generates a jitter- powered by a single 1.8, 2.5, or 3.3 V supply.
attenuated clock output at the same frequency. Within
1.1. External Reference
each of these clock ranges, the device can be tuned
approximately 15% higher than nominal SONET/SDH An external, 38.88 MHz clock or
a
low-cost
frequencies, up to a maximum of 710 MHz in the 114.285 MHz 3rd overtone crystal is used as part of a
622 MHz range. The Si5316 is based on Silicon fixed-frequency oscillator within the DSPLL. This
®
Laboratories' 3rd-generation DSPLL technology, which external reference is required for the device to perform
provides any-rate frequency synthesis and jitter jitter attenuation. Silicon Laboratories recommends
attenuation in a highly integrated PLL solution that using a high-quality crystal from TXC (www.txc.com.tw),
eliminates the need for external VCXO and loop filter part number 7MA1400014. An external 38.88 MHz
components. For applications which require input clocks clock from a high quality OCXO or TCXO can also be
at different frequencies, the frequency of CKIN1 can be used as a reference for the device.
1x, 4x, or 32x the frequency of CKIN2 as specified by
the CK1DIV and CK2DIV inputs.
In digital hold, the DSPLL remains locked to this
external reference. Any changes in the frequency of this
The Si5316 PLL loop bandwidth is selectable via the reference when the DSPLL is in digital hold will be
BWSEL[1:0] pins and supports a range from 100 Hz to tracked by the output of the device. Note that crystals
7.9 kHz. To calculate potential loop bandwidth values can have temperature sensitivities.
for a given input/output clock frequency, Silicon
1.2. Further Documentation
Laboratories offers
a
PC-based software utility,
DSPLLsim, that calculates valid loop bandwidth settings Consult the Silicon Laboratories Any-Rate Precision
automatically. This utility can be downloaded from Clock Family Reference Manual (FRM) for more
www.silabs.com/timing.
detailed information about the Si5316. The FRM can be
downloaded from www.silabs.com/timing.
The Si5316 supports manual active input clock
selection. The Si5316 monitors both input clocks for Silicon Laboratories has developed
a PC-based
loss-of-signal and provides a LOS alarm when it detects software utility called DSPLLsim to simplify device
missing pulses on either input clock. Hitless switching is configuration, including frequency planning and loop
not supported by the Si5316. During a clock transition, bandwidth selection. This utility can be downloaded
the phase of the output clock will slew at a rate defined from www.silabs.com/timing.
by the PLL loop bandwidth until the original input clock
phase to output clock phase is restored. The device
monitors the lock status of the PLL. The lock detect
algorithm works by continuously monitoring the phase
of the input clock in relation to the phase of the
feedback clock.
6
Preliminary Rev. 0.24
Si5316
2. Pin Descriptions: Si5316
36 35 34 33 32 31 30 29 28
RST
NC
1
2
3
4
5
6
7
8
9
27 CK2DIV
26
CK1DIV
25 FRQSEL1
C1B
C2B
VDD
XA
24
23
FRQSEL0
BWSEL1
GND
Pad
22 BWSEL0
XB
21
20
19
CS
NC
NC
GND
NC
10 11 12 13 14 15 16 17 18
Pin assignments are preliminary and subject to change.
Table 3. Si5316 Pin Descriptions
Pin #
Pin Name I/O Signal Level
Description
1
RST
I
LVCMOS
External Reset.
Active low input that performs external hardware reset of device.
Resets all internal logic to a known state. Clock outputs are tristated
during reset. After rising edge of RST signal, the Si5316 will perform
an internal self-calibration.
This pin has a weak pull-up.
2, 9, 11,
19, 20,
28, 29, 36
NC
—
O
—
No Connect.
These pins must be left unconnected for normal operation.
3
C1B
LVCMOS
CKIN1 Loss of Signal.
Active high Loss-of-signal indicator for CKIN1. Once triggered, the
alarm will remain active until CKIN1 is validated.
0 = CKIN1 present
1 = LOS on CKIN1
4
C2B
O
LVCMOS
Supply
CKIN2 Loss of Signal.
Active high Loss-of-signal indicator for CKIN2. Once triggered, the
alarm will remain active until CKIN2 is validated.
0 = CKIN2 present
1 = LOS on CKIN2
5, 10, 32
V
V
Supply.
DD
DD
The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass capaci-
tors should be associated with the following V pins:
DD
5
10
32
0.1 µF
0.1 µF
0.1 µF
A 1.0 µF should be placed as close to device as is practical.
Preliminary Rev. 0.24
7
Si5316
Table 3. Si5316 Pin Descriptions (Continued)
Pin Name I/O Signal Level Description
Pin #
7
6
XB
XA
I
Analog
External Crystal or Reference Clock.
External crystal should be connected to these pins to use internal
oscillator based reference. If external reference is used, apply refer-
ence clock to XA input and leave XB pin floating. External reference
must be from a high-quality clock source (TCXO, OCXO). Frequency
of crystal or external clock is set by the RATE pin.
8, 31
15
GND
GND
I
Supply
3-Level
Ground.
Must be connected to system ground. Minimize the ground path
impedance for optimal performance of this device.
RATE
External Crystal or Reference Clock Rate.
Three level input that selects the type and rate of external crystal or
reference clock to be applied to the XA/XB port.
L = 38.88 MHz external clock
M = 114.285 MHz 3rd OT crystal
H = Reserved
12
13
CKIN2+
CKIN2–
I
I
Multi
Clock Input 2.
Differential input clock. This input can also be driven with a single-
ended signal.
14
DBL_BY
3-Level
Output Disable/Bypass Mode Control.
Controls enable of CKOUT divider/output buffer path and PLL
bypass mode.
L = CKOUT enabled
M = CKOUT disabled
H = Bypass mode with CKOUT enabled
16
17
CKIN1+
CKIN1–
I
Multi
Clock Input 1.
Differential input clock. This input can also be driven with a single-
ended signal.
18
LOL
O
LVCMOS
PLL Loss of Lock Indicator.
This pin functions as the active high PLL loss of lock indicator.
0 = PLL locked
1 = PLL unlocked
21
CS
I
LVCMOS
Input Clock Select.
This pin functions as the input clock selector. This input is internally
deglitched to prevent inadvertent clock switching during changes in
the CKSEL input state.
0 = Select CKIN1
1 = Select CKIN2
23
22
BWSEL1
BWSEL0
I
I
3-Level
3-Level
Bandwidth Select.
Three level inputs that select the DSPLL closed loop bandwidth.
Detailed operations and timing characteristics for these pins may be
found in the Any-Rate Precision Clock Family Reference Manual.
25
24
FRQSEL1
FRQSEL0
Frequency Select.
Sets the output frequency of the device. When the frequency of
CKIN1 is not equal to CKIN2, the lower frequency input clock must
be equal to the output clock frequency.
8
Preliminary Rev. 0.24
Si5316
Table 3. Si5316 Pin Descriptions (Continued)
Pin #
Pin Name I/O Signal Level
Description
Input Clock 1 Pre-Divider Select.
26
CK1DIV
I
I
I
3-Level
3-Level
3-Level
Pre-divider on CKIN1. Used with CK2DIV to divide input clock
frequencies to a common value. When the frequencies applied to
CKIN1 and CKIN2 are equal, CK1DIV must be tied low.
L = CKIN1 input divider set to 1.
M = CKIN1 input divider set to 4.
H = CKIN1 input divider set to 32.
27
CK2DIV
Input Clock 2 Pre-Divider Select.
Pre-divider on CKIN2. Used with CK1DIV to divide input clock
frequencies to a common value. When the frequencies applied to
CKIN1 and CKIN2 are equal, CK2DIV must be tied low.
L = CKIN2 input divider set to 1.
M = CKIN2 input divider set to 4.
H = CKIN2 input divider set to 32.
33
30
SFOUT0
SFOUT1
Signal Format Select.
Three level inputs that select the output signal format (common
mode voltage and differential swing) for CKOUT. Valid settings
include LVPECL, LVDS, and CML. Also includes selections for
CMOS mode, tristate mode, and tristate/sleep mode.
SFOUT[1:0]
Signal Format
Reserved
HH
HM
HL
Reserved
CML
MH
MM
ML
LH
LVPECL
Reserved
LVDS
CMOS
LM
LL
Tristate/Sleep
Reserved
34
35
CKOUT–
CKOUT+
O
Multi
Clock Output.
Differential output clock with a frequency selected from a table of val-
ues. Output signal format is selected by SFOUT pins. Output is differ-
ential for LVPECL, LVDS, and CML compatible modes. For CMOS
format, both output pins drive identical single-ended clock outputs.
GND PAD
GND
GND
Supply
Ground Pad.
The ground pad must provide a low thermal and electrical impedance
to a ground plane.
Preliminary Rev. 0.24
9
Si5316
3. Ordering Guide
Ordering Part Number
Si5316-B-GM
Package
Temperature Range
36-Lead 6 x 6 mm QFN
–40 to 85 °C
10
Preliminary Rev. 0.24
Si5316
4. Package Outline: 36-Lead QFN
Figure 3 illustrates the package details for the Si5316. Table 4 lists the values for the dimensions shown in the
illustration.
Figure 3. 36-Pin Quad Flat No-lead (QFN)
Table 4. Package Dimensions
Symbol
Millimeters
Symbol
Millimeters
Min
0.80
0.00
0.18
Nom
0.85
Max
0.90
0.05
0.30
Min
0.50
—
Nom
0.60
—
Max
0.75
12º
A
A1
b
L
0.01
θ
0.23
aaa
bbb
ccc
ddd
eee
—
—
0.10
0.10
0.05
0.10
0.05
D
6.00 BSC
4.10
—
—
D2
e
3.95
4.25
—
—
0.50 BSC
6.00 BSC
4.10
—
—
E
—
—
E2
3.95
4.25
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-220, variation VJJD.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body
Components.
Preliminary Rev. 0.24
11
Si5316
5. Recommended PCB Layout
Figure 4. PCB Land Pattern Diagram
12
Preliminary Rev. 0.24
Si5316
Table 5. PCB Land Pattern Dimensions
Dimension
MIN
MAX
e
E
0.50 BSC.
5.42 REF.
5.42 REF.
D
E2
D2
GE
GD
X
4.00
4.00
4.53
4.53
—
4.20
4.20
—
—
0.28
Y
0.89 REF.
ZE
ZD
—
—
6.31
6.31
Notes (General):
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on IPC-SM-782 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Notes (Solder Mask Design):
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Notes (Stencil Design):
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be
used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
4. A 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the
center ground pad.
Notes (Card Assembly):
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification
for Small Body Components.
Preliminary Rev. 0.24
13
Si5316
DOCUMENT CHANGE LIST
Revision 0.23 to 0.24
Changed LVTTL to LVCMOS in Table 2, “Absolute
Maximum Ratings,” on page 3.
Added Figure 1, “Typical Phase Noise Plot,” on page
4.
Showed preferred interface for an external reference
clock in Figure 2, “Si5316 Typical Application
Circuit,” on page 5.
Updated 3. "Ordering Guide" on page 10.
Added “5. Recommended PCB Layout”.
14
Preliminary Rev. 0.24
Si5316
NOTES:
Preliminary Rev. 0.24
15
Si5316
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Email: Clockinfo@silabs.com
Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
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Silicon Laboratories, Silicon Labs, and 5323 are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
16
Preliminary Rev. 0.24
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